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[mesa.git] / src / intel / compiler / brw_eu.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_EU_H
34 #define BRW_EU_H
35
36 #include <stdbool.h>
37 #include <stdio.h>
38 #include "brw_inst.h"
39 #include "brw_eu_defines.h"
40 #include "brw_reg.h"
41 #include "brw_disasm_info.h"
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 #define BRW_EU_MAX_INSN_STACK 5
48
49 struct brw_insn_state {
50 /* One of BRW_EXECUTE_* */
51 unsigned exec_size:3;
52
53 /* Group in units of channels */
54 unsigned group:5;
55
56 /* Compression control on gen4-5 */
57 bool compressed:1;
58
59 /* One of BRW_MASK_* */
60 unsigned mask_control:1;
61
62 /* Scheduling info for Gen12+ */
63 struct tgl_swsb swsb;
64
65 bool saturate:1;
66
67 /* One of BRW_ALIGN_* */
68 unsigned access_mode:1;
69
70 /* One of BRW_PREDICATE_* */
71 enum brw_predicate predicate:4;
72
73 bool pred_inv:1;
74
75 /* Flag subreg. Bottom bit is subreg, top bit is reg */
76 unsigned flag_subreg:2;
77
78 bool acc_wr_control:1;
79 };
80
81
82 /* A helper for accessing the last instruction emitted. This makes it easy
83 * to set various bits on an instruction without having to create temporary
84 * variable and assign the emitted instruction to those.
85 */
86 #define brw_last_inst (&p->store[p->nr_insn - 1])
87
88 struct brw_codegen {
89 brw_inst *store;
90 int store_size;
91 unsigned nr_insn;
92 unsigned int next_insn_offset;
93
94 void *mem_ctx;
95
96 /* Allow clients to push/pop instruction state:
97 */
98 struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
99 struct brw_insn_state *current;
100
101 /** Whether or not the user wants automatic exec sizes
102 *
103 * If true, codegen will try to automatically infer the exec size of an
104 * instruction from the width of the destination register. If false, it
105 * will take whatever is set by brw_set_default_exec_size verbatim.
106 *
107 * This is set to true by default in brw_init_codegen.
108 */
109 bool automatic_exec_sizes;
110
111 bool single_program_flow;
112 const struct gen_device_info *devinfo;
113
114 /* Control flow stacks:
115 * - if_stack contains IF and ELSE instructions which must be patched
116 * (and popped) once the matching ENDIF instruction is encountered.
117 *
118 * Just store the instruction pointer(an index).
119 */
120 int *if_stack;
121 int if_stack_depth;
122 int if_stack_array_size;
123
124 /**
125 * loop_stack contains the instruction pointers of the starts of loops which
126 * must be patched (and popped) once the matching WHILE instruction is
127 * encountered.
128 */
129 int *loop_stack;
130 /**
131 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
132 * blocks they were popping out of, to fix up the mask stack. This tracks
133 * the IF/ENDIF nesting in each current nested loop level.
134 */
135 int *if_depth_in_loop;
136 int loop_stack_depth;
137 int loop_stack_array_size;
138 };
139
140 struct brw_label {
141 int offset;
142 int number;
143 struct brw_label *next;
144 };
145
146 void brw_pop_insn_state( struct brw_codegen *p );
147 void brw_push_insn_state( struct brw_codegen *p );
148 unsigned brw_get_default_exec_size(struct brw_codegen *p);
149 unsigned brw_get_default_group(struct brw_codegen *p);
150 unsigned brw_get_default_access_mode(struct brw_codegen *p);
151 struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
152 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
153 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
154 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
155 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
156 void brw_inst_set_compression(const struct gen_device_info *devinfo,
157 brw_inst *inst, bool on);
158 void brw_set_default_compression(struct brw_codegen *p, bool on);
159 void brw_inst_set_group(const struct gen_device_info *devinfo,
160 brw_inst *inst, unsigned group);
161 void brw_set_default_group(struct brw_codegen *p, unsigned group);
162 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
163 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
164 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
165 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
166 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
167 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
168
169 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
170 void *mem_ctx);
171 bool brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode);
172 bool brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode);
173 const struct brw_label *brw_find_label(const struct brw_label *root, int offset);
174 void brw_create_label(struct brw_label **labels, int offset, void *mem_ctx);
175 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
176 const struct brw_inst *inst, bool is_compacted,
177 int offset, const struct brw_label *root_label);
178 const struct brw_label *brw_label_assembly(const struct gen_device_info *devinfo,
179 const void *assembly, int start, int end,
180 void *mem_ctx);
181 void brw_disassemble_with_labels(const struct gen_device_info *devinfo,
182 const void *assembly, int start, int end, FILE *out);
183 void brw_disassemble(const struct gen_device_info *devinfo,
184 const void *assembly, int start, int end,
185 const struct brw_label *root_label, FILE *out);
186 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
187
188 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
189 const char *identifier);
190
191 void brw_realign(struct brw_codegen *p, unsigned align);
192 int brw_append_data(struct brw_codegen *p, void *data,
193 unsigned size, unsigned align);
194 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
195 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
196 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
197
198 void gen6_resolve_implied_move(struct brw_codegen *p,
199 struct brw_reg *src,
200 unsigned msg_reg_nr);
201
202 /* Helpers for regular instructions:
203 */
204 #define ALU1(OP) \
205 brw_inst *brw_##OP(struct brw_codegen *p, \
206 struct brw_reg dest, \
207 struct brw_reg src0);
208
209 #define ALU2(OP) \
210 brw_inst *brw_##OP(struct brw_codegen *p, \
211 struct brw_reg dest, \
212 struct brw_reg src0, \
213 struct brw_reg src1);
214
215 #define ALU3(OP) \
216 brw_inst *brw_##OP(struct brw_codegen *p, \
217 struct brw_reg dest, \
218 struct brw_reg src0, \
219 struct brw_reg src1, \
220 struct brw_reg src2);
221
222 ALU1(MOV)
223 ALU2(SEL)
224 ALU1(NOT)
225 ALU2(AND)
226 ALU2(OR)
227 ALU2(XOR)
228 ALU2(SHR)
229 ALU2(SHL)
230 ALU1(DIM)
231 ALU2(ASR)
232 ALU2(ROL)
233 ALU2(ROR)
234 ALU3(CSEL)
235 ALU1(F32TO16)
236 ALU1(F16TO32)
237 ALU2(ADD)
238 ALU2(AVG)
239 ALU2(MUL)
240 ALU1(FRC)
241 ALU1(RNDD)
242 ALU1(RNDE)
243 ALU1(RNDU)
244 ALU1(RNDZ)
245 ALU2(MAC)
246 ALU2(MACH)
247 ALU1(LZD)
248 ALU2(DP4)
249 ALU2(DPH)
250 ALU2(DP3)
251 ALU2(DP2)
252 ALU2(LINE)
253 ALU2(PLN)
254 ALU3(MAD)
255 ALU3(LRP)
256 ALU1(BFREV)
257 ALU3(BFE)
258 ALU2(BFI1)
259 ALU3(BFI2)
260 ALU1(FBH)
261 ALU1(FBL)
262 ALU1(CBIT)
263 ALU2(ADDC)
264 ALU2(SUBB)
265 ALU2(MAC)
266
267 #undef ALU1
268 #undef ALU2
269 #undef ALU3
270
271
272 /* Helpers for SEND instruction:
273 */
274
275 /**
276 * Construct a message descriptor immediate with the specified common
277 * descriptor controls.
278 */
279 static inline uint32_t
280 brw_message_desc(const struct gen_device_info *devinfo,
281 unsigned msg_length,
282 unsigned response_length,
283 bool header_present)
284 {
285 if (devinfo->gen >= 5) {
286 return (SET_BITS(msg_length, 28, 25) |
287 SET_BITS(response_length, 24, 20) |
288 SET_BITS(header_present, 19, 19));
289 } else {
290 return (SET_BITS(msg_length, 23, 20) |
291 SET_BITS(response_length, 19, 16));
292 }
293 }
294
295 static inline unsigned
296 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
297 {
298 if (devinfo->gen >= 5)
299 return GET_BITS(desc, 28, 25);
300 else
301 return GET_BITS(desc, 23, 20);
302 }
303
304 static inline unsigned
305 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
306 {
307 if (devinfo->gen >= 5)
308 return GET_BITS(desc, 24, 20);
309 else
310 return GET_BITS(desc, 19, 16);
311 }
312
313 static inline bool
314 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
315 uint32_t desc)
316 {
317 assert(devinfo->gen >= 5);
318 return GET_BITS(desc, 19, 19);
319 }
320
321 static inline unsigned
322 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
323 unsigned ex_msg_length)
324 {
325 return SET_BITS(ex_msg_length, 9, 6);
326 }
327
328 static inline unsigned
329 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
330 uint32_t ex_desc)
331 {
332 return GET_BITS(ex_desc, 9, 6);
333 }
334
335 static inline uint32_t
336 brw_urb_desc(const struct gen_device_info *devinfo,
337 unsigned msg_type,
338 bool per_slot_offset_present,
339 bool channel_mask_present,
340 unsigned global_offset)
341 {
342 if (devinfo->gen >= 8) {
343 return (SET_BITS(per_slot_offset_present, 17, 17) |
344 SET_BITS(channel_mask_present, 15, 15) |
345 SET_BITS(global_offset, 14, 4) |
346 SET_BITS(msg_type, 3, 0));
347 } else if (devinfo->gen >= 7) {
348 assert(!channel_mask_present);
349 return (SET_BITS(per_slot_offset_present, 16, 16) |
350 SET_BITS(global_offset, 13, 3) |
351 SET_BITS(msg_type, 3, 0));
352 } else {
353 unreachable("unhandled URB write generation");
354 }
355 }
356
357 static inline uint32_t
358 brw_urb_desc_msg_type(ASSERTED const struct gen_device_info *devinfo,
359 uint32_t desc)
360 {
361 assert(devinfo->gen >= 7);
362 return GET_BITS(desc, 3, 0);
363 }
364
365 /**
366 * Construct a message descriptor immediate with the specified sampler
367 * function controls.
368 */
369 static inline uint32_t
370 brw_sampler_desc(const struct gen_device_info *devinfo,
371 unsigned binding_table_index,
372 unsigned sampler,
373 unsigned msg_type,
374 unsigned simd_mode,
375 unsigned return_format)
376 {
377 const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
378 SET_BITS(sampler, 11, 8));
379 if (devinfo->gen >= 7)
380 return (desc | SET_BITS(msg_type, 16, 12) |
381 SET_BITS(simd_mode, 18, 17));
382 else if (devinfo->gen >= 5)
383 return (desc | SET_BITS(msg_type, 15, 12) |
384 SET_BITS(simd_mode, 17, 16));
385 else if (devinfo->is_g4x)
386 return desc | SET_BITS(msg_type, 15, 12);
387 else
388 return (desc | SET_BITS(return_format, 13, 12) |
389 SET_BITS(msg_type, 15, 14));
390 }
391
392 static inline unsigned
393 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
394 uint32_t desc)
395 {
396 return GET_BITS(desc, 7, 0);
397 }
398
399 static inline unsigned
400 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
401 {
402 return GET_BITS(desc, 11, 8);
403 }
404
405 static inline unsigned
406 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
407 {
408 if (devinfo->gen >= 7)
409 return GET_BITS(desc, 16, 12);
410 else if (devinfo->gen >= 5 || devinfo->is_g4x)
411 return GET_BITS(desc, 15, 12);
412 else
413 return GET_BITS(desc, 15, 14);
414 }
415
416 static inline unsigned
417 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
418 {
419 assert(devinfo->gen >= 5);
420 if (devinfo->gen >= 7)
421 return GET_BITS(desc, 18, 17);
422 else
423 return GET_BITS(desc, 17, 16);
424 }
425
426 static inline unsigned
427 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
428 uint32_t desc)
429 {
430 assert(devinfo->gen == 4 && !devinfo->is_g4x);
431 return GET_BITS(desc, 13, 12);
432 }
433
434 /**
435 * Construct a message descriptor for the dataport
436 */
437 static inline uint32_t
438 brw_dp_desc(const struct gen_device_info *devinfo,
439 unsigned binding_table_index,
440 unsigned msg_type,
441 unsigned msg_control)
442 {
443 /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
444 * helpers instead.
445 */
446 assert(devinfo->gen >= 6);
447 const unsigned desc = SET_BITS(binding_table_index, 7, 0);
448 if (devinfo->gen >= 8) {
449 return (desc | SET_BITS(msg_control, 13, 8) |
450 SET_BITS(msg_type, 18, 14));
451 } else if (devinfo->gen >= 7) {
452 return (desc | SET_BITS(msg_control, 13, 8) |
453 SET_BITS(msg_type, 17, 14));
454 } else {
455 return (desc | SET_BITS(msg_control, 12, 8) |
456 SET_BITS(msg_type, 16, 13));
457 }
458 }
459
460 static inline unsigned
461 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
462 uint32_t desc)
463 {
464 return GET_BITS(desc, 7, 0);
465 }
466
467 static inline unsigned
468 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
469 {
470 assert(devinfo->gen >= 6);
471 if (devinfo->gen >= 8)
472 return GET_BITS(desc, 18, 14);
473 else if (devinfo->gen >= 7)
474 return GET_BITS(desc, 17, 14);
475 else
476 return GET_BITS(desc, 16, 13);
477 }
478
479 static inline unsigned
480 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
481 {
482 assert(devinfo->gen >= 6);
483 if (devinfo->gen >= 7)
484 return GET_BITS(desc, 13, 8);
485 else
486 return GET_BITS(desc, 12, 8);
487 }
488
489 /**
490 * Construct a message descriptor immediate with the specified dataport read
491 * function controls.
492 */
493 static inline uint32_t
494 brw_dp_read_desc(const struct gen_device_info *devinfo,
495 unsigned binding_table_index,
496 unsigned msg_control,
497 unsigned msg_type,
498 unsigned target_cache)
499 {
500 if (devinfo->gen >= 6)
501 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
502 else if (devinfo->gen >= 5 || devinfo->is_g4x)
503 return (SET_BITS(binding_table_index, 7, 0) |
504 SET_BITS(msg_control, 10, 8) |
505 SET_BITS(msg_type, 13, 11) |
506 SET_BITS(target_cache, 15, 14));
507 else
508 return (SET_BITS(binding_table_index, 7, 0) |
509 SET_BITS(msg_control, 11, 8) |
510 SET_BITS(msg_type, 13, 12) |
511 SET_BITS(target_cache, 15, 14));
512 }
513
514 static inline unsigned
515 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
516 {
517 if (devinfo->gen >= 6)
518 return brw_dp_desc_msg_type(devinfo, desc);
519 else if (devinfo->gen >= 5 || devinfo->is_g4x)
520 return GET_BITS(desc, 13, 11);
521 else
522 return GET_BITS(desc, 13, 12);
523 }
524
525 static inline unsigned
526 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
527 uint32_t desc)
528 {
529 if (devinfo->gen >= 6)
530 return brw_dp_desc_msg_control(devinfo, desc);
531 else if (devinfo->gen >= 5 || devinfo->is_g4x)
532 return GET_BITS(desc, 10, 8);
533 else
534 return GET_BITS(desc, 11, 8);
535 }
536
537 /**
538 * Construct a message descriptor immediate with the specified dataport write
539 * function controls.
540 */
541 static inline uint32_t
542 brw_dp_write_desc(const struct gen_device_info *devinfo,
543 unsigned binding_table_index,
544 unsigned msg_control,
545 unsigned msg_type,
546 unsigned last_render_target,
547 unsigned send_commit_msg)
548 {
549 assert(devinfo->gen <= 6 || !send_commit_msg);
550 if (devinfo->gen >= 6)
551 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
552 SET_BITS(last_render_target, 12, 12) |
553 SET_BITS(send_commit_msg, 17, 17);
554 else
555 return (SET_BITS(binding_table_index, 7, 0) |
556 SET_BITS(msg_control, 11, 8) |
557 SET_BITS(last_render_target, 11, 11) |
558 SET_BITS(msg_type, 14, 12) |
559 SET_BITS(send_commit_msg, 15, 15));
560 }
561
562 static inline unsigned
563 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
564 uint32_t desc)
565 {
566 if (devinfo->gen >= 6)
567 return brw_dp_desc_msg_type(devinfo, desc);
568 else
569 return GET_BITS(desc, 14, 12);
570 }
571
572 static inline unsigned
573 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
574 uint32_t desc)
575 {
576 if (devinfo->gen >= 6)
577 return brw_dp_desc_msg_control(devinfo, desc);
578 else
579 return GET_BITS(desc, 11, 8);
580 }
581
582 static inline bool
583 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
584 uint32_t desc)
585 {
586 if (devinfo->gen >= 6)
587 return GET_BITS(desc, 12, 12);
588 else
589 return GET_BITS(desc, 11, 11);
590 }
591
592 static inline bool
593 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
594 uint32_t desc)
595 {
596 assert(devinfo->gen <= 6);
597 if (devinfo->gen >= 6)
598 return GET_BITS(desc, 17, 17);
599 else
600 return GET_BITS(desc, 15, 15);
601 }
602
603 /**
604 * Construct a message descriptor immediate with the specified dataport
605 * surface function controls.
606 */
607 static inline uint32_t
608 brw_dp_surface_desc(const struct gen_device_info *devinfo,
609 unsigned msg_type,
610 unsigned msg_control)
611 {
612 assert(devinfo->gen >= 7);
613 /* We'll OR in the binding table index later */
614 return brw_dp_desc(devinfo, 0, msg_type, msg_control);
615 }
616
617 static inline uint32_t
618 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
619 unsigned exec_size, /**< 0 for SIMD4x2 */
620 unsigned atomic_op,
621 bool response_expected)
622 {
623 assert(exec_size <= 8 || exec_size == 16);
624
625 unsigned msg_type;
626 if (devinfo->gen >= 8 || devinfo->is_haswell) {
627 if (exec_size > 0) {
628 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
629 } else {
630 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
631 }
632 } else {
633 msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
634 }
635
636 const unsigned msg_control =
637 SET_BITS(atomic_op, 3, 0) |
638 SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
639 SET_BITS(response_expected, 5, 5);
640
641 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
642 }
643
644 static inline uint32_t
645 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
646 unsigned exec_size,
647 unsigned atomic_op,
648 bool response_expected)
649 {
650 assert(exec_size <= 8 || exec_size == 16);
651 assert(devinfo->gen >= 9);
652
653 assert(exec_size > 0);
654 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
655
656 const unsigned msg_control =
657 SET_BITS(atomic_op, 1, 0) |
658 SET_BITS(exec_size <= 8, 4, 4) |
659 SET_BITS(response_expected, 5, 5);
660
661 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
662 }
663
664 static inline unsigned
665 brw_mdc_cmask(unsigned num_channels)
666 {
667 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
668 return 0xf & (0xf << num_channels);
669 }
670
671 static inline uint32_t
672 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
673 unsigned exec_size, /**< 0 for SIMD4x2 */
674 unsigned num_channels,
675 bool write)
676 {
677 assert(exec_size <= 8 || exec_size == 16);
678
679 unsigned msg_type;
680 if (write) {
681 if (devinfo->gen >= 8 || devinfo->is_haswell) {
682 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
683 } else {
684 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
685 }
686 } else {
687 /* Read */
688 if (devinfo->gen >= 8 || devinfo->is_haswell) {
689 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
690 } else {
691 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
692 }
693 }
694
695 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
696 if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
697 exec_size = 8;
698
699 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
700 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
701 exec_size <= 8 ? 2 : 1;
702
703 const unsigned msg_control =
704 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
705 SET_BITS(simd_mode, 5, 4);
706
707 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
708 }
709
710 static inline unsigned
711 brw_mdc_ds(unsigned bit_size)
712 {
713 switch (bit_size) {
714 case 8:
715 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
716 case 16:
717 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
718 case 32:
719 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
720 default:
721 unreachable("Unsupported bit_size for byte scattered messages");
722 }
723 }
724
725 static inline uint32_t
726 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
727 unsigned exec_size,
728 unsigned bit_size,
729 bool write)
730 {
731 assert(exec_size <= 8 || exec_size == 16);
732
733 assert(devinfo->gen > 7 || devinfo->is_haswell);
734 const unsigned msg_type =
735 write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
736 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
737
738 assert(exec_size > 0);
739 const unsigned msg_control =
740 SET_BITS(exec_size == 16, 0, 0) |
741 SET_BITS(brw_mdc_ds(bit_size), 3, 2);
742
743 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
744 }
745
746 static inline uint32_t
747 brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
748 unsigned exec_size,
749 bool write)
750 {
751 assert(exec_size == 8 || exec_size == 16);
752
753 unsigned msg_type;
754 if (write) {
755 if (devinfo->gen >= 6) {
756 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
757 } else {
758 msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
759 }
760 } else {
761 if (devinfo->gen >= 7) {
762 msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
763 } else if (devinfo->gen > 4 || devinfo->is_g4x) {
764 msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
765 } else {
766 msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
767 }
768 }
769
770 const unsigned msg_control =
771 SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
772 SET_BITS(exec_size == 16, 0, 0);
773
774 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
775 }
776
777 static inline uint32_t
778 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
779 unsigned exec_size, /**< 0 for SIMD4x2 */
780 unsigned num_channels,
781 bool write)
782 {
783 assert(exec_size <= 8 || exec_size == 16);
784 assert(devinfo->gen >= 8);
785
786 unsigned msg_type =
787 write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
788 GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
789
790 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
791 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
792 exec_size <= 8 ? 2 : 1;
793
794 const unsigned msg_control =
795 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
796 SET_BITS(simd_mode, 5, 4);
797
798 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
799 msg_type, msg_control);
800 }
801
802 /**
803 * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
804 * Skylake PRM).
805 */
806 static inline uint32_t
807 brw_mdc_a64_ds(unsigned elems)
808 {
809 switch (elems) {
810 case 1: return 0;
811 case 2: return 1;
812 case 4: return 2;
813 case 8: return 3;
814 default:
815 unreachable("Unsupported elmeent count for A64 scattered message");
816 }
817 }
818
819 static inline uint32_t
820 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
821 unsigned exec_size, /**< 0 for SIMD4x2 */
822 unsigned bit_size,
823 bool write)
824 {
825 assert(exec_size <= 8 || exec_size == 16);
826 assert(devinfo->gen >= 8);
827
828 unsigned msg_type =
829 write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
830 GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
831
832 const unsigned msg_control =
833 SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
834 SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
835 SET_BITS(exec_size == 16, 4, 4);
836
837 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
838 msg_type, msg_control);
839 }
840
841 static inline uint32_t
842 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
843 ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
844 unsigned bit_size,
845 unsigned atomic_op,
846 bool response_expected)
847 {
848 assert(exec_size == 8);
849 assert(devinfo->gen >= 8);
850 assert(bit_size == 32 || bit_size == 64);
851
852 const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
853
854 const unsigned msg_control =
855 SET_BITS(atomic_op, 3, 0) |
856 SET_BITS(bit_size == 64, 4, 4) |
857 SET_BITS(response_expected, 5, 5);
858
859 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
860 msg_type, msg_control);
861 }
862
863 static inline uint32_t
864 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
865 ASSERTED unsigned exec_size,
866 unsigned atomic_op,
867 bool response_expected)
868 {
869 assert(exec_size == 8);
870 assert(devinfo->gen >= 9);
871
872 assert(exec_size > 0);
873 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
874
875 const unsigned msg_control =
876 SET_BITS(atomic_op, 1, 0) |
877 SET_BITS(response_expected, 5, 5);
878
879 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
880 msg_type, msg_control);
881 }
882
883 static inline uint32_t
884 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
885 unsigned exec_size,
886 unsigned exec_group,
887 unsigned atomic_op,
888 bool response_expected)
889 {
890 assert(exec_size > 0 || exec_group == 0);
891 assert(exec_group % 8 == 0);
892
893 unsigned msg_type;
894 if (devinfo->gen >= 8 || devinfo->is_haswell) {
895 if (exec_size == 0) {
896 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
897 } else {
898 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
899 }
900 } else {
901 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
902 assert(exec_size > 0);
903 msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
904 }
905
906 const bool high_sample_mask = (exec_group / 8) % 2 == 1;
907
908 const unsigned msg_control =
909 SET_BITS(atomic_op, 3, 0) |
910 SET_BITS(high_sample_mask, 4, 4) |
911 SET_BITS(response_expected, 5, 5);
912
913 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
914 }
915
916 static inline uint32_t
917 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
918 unsigned exec_size,
919 unsigned exec_group,
920 unsigned num_channels,
921 bool write)
922 {
923 assert(exec_size > 0 || exec_group == 0);
924 assert(exec_group % 8 == 0);
925
926 /* Typed surface reads and writes don't support SIMD16 */
927 assert(exec_size <= 8);
928
929 unsigned msg_type;
930 if (write) {
931 if (devinfo->gen >= 8 || devinfo->is_haswell) {
932 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
933 } else {
934 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
935 }
936 } else {
937 if (devinfo->gen >= 8 || devinfo->is_haswell) {
938 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
939 } else {
940 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
941 }
942 }
943
944 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
945 unsigned msg_control;
946 if (devinfo->gen >= 8 || devinfo->is_haswell) {
947 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
948 const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
949 1 + ((exec_group / 8) % 2);
950
951 msg_control =
952 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
953 SET_BITS(slot_group, 5, 4);
954 } else {
955 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
956 assert(exec_size > 0);
957 const unsigned slot_group = ((exec_group / 8) % 2);
958
959 msg_control =
960 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
961 SET_BITS(slot_group, 5, 5);
962 }
963
964 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
965 }
966
967 /**
968 * Construct a message descriptor immediate with the specified pixel
969 * interpolator function controls.
970 */
971 static inline uint32_t
972 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
973 unsigned msg_type,
974 bool noperspective,
975 unsigned simd_mode,
976 unsigned slot_group)
977 {
978 return (SET_BITS(slot_group, 11, 11) |
979 SET_BITS(msg_type, 13, 12) |
980 SET_BITS(!!noperspective, 14, 14) |
981 SET_BITS(simd_mode, 16, 16));
982 }
983
984 void brw_urb_WRITE(struct brw_codegen *p,
985 struct brw_reg dest,
986 unsigned msg_reg_nr,
987 struct brw_reg src0,
988 enum brw_urb_write_flags flags,
989 unsigned msg_length,
990 unsigned response_length,
991 unsigned offset,
992 unsigned swizzle);
993
994 /**
995 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
996 * desc. If \p desc is not an immediate it will be transparently loaded to an
997 * address register using an OR instruction.
998 */
999 void
1000 brw_send_indirect_message(struct brw_codegen *p,
1001 unsigned sfid,
1002 struct brw_reg dst,
1003 struct brw_reg payload,
1004 struct brw_reg desc,
1005 unsigned desc_imm,
1006 bool eot);
1007
1008 void
1009 brw_send_indirect_split_message(struct brw_codegen *p,
1010 unsigned sfid,
1011 struct brw_reg dst,
1012 struct brw_reg payload0,
1013 struct brw_reg payload1,
1014 struct brw_reg desc,
1015 unsigned desc_imm,
1016 struct brw_reg ex_desc,
1017 unsigned ex_desc_imm,
1018 bool eot);
1019
1020 void brw_ff_sync(struct brw_codegen *p,
1021 struct brw_reg dest,
1022 unsigned msg_reg_nr,
1023 struct brw_reg src0,
1024 bool allocate,
1025 unsigned response_length,
1026 bool eot);
1027
1028 void brw_svb_write(struct brw_codegen *p,
1029 struct brw_reg dest,
1030 unsigned msg_reg_nr,
1031 struct brw_reg src0,
1032 unsigned binding_table_index,
1033 bool send_commit_msg);
1034
1035 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
1036 struct brw_reg payload,
1037 struct brw_reg implied_header,
1038 unsigned msg_control,
1039 unsigned binding_table_index,
1040 unsigned msg_length,
1041 unsigned response_length,
1042 bool eot,
1043 bool last_render_target,
1044 bool header_present);
1045
1046 brw_inst *gen9_fb_READ(struct brw_codegen *p,
1047 struct brw_reg dst,
1048 struct brw_reg payload,
1049 unsigned binding_table_index,
1050 unsigned msg_length,
1051 unsigned response_length,
1052 bool per_sample);
1053
1054 void brw_SAMPLE(struct brw_codegen *p,
1055 struct brw_reg dest,
1056 unsigned msg_reg_nr,
1057 struct brw_reg src0,
1058 unsigned binding_table_index,
1059 unsigned sampler,
1060 unsigned msg_type,
1061 unsigned response_length,
1062 unsigned msg_length,
1063 unsigned header_present,
1064 unsigned simd_mode,
1065 unsigned return_format);
1066
1067 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
1068 struct brw_reg header,
1069 struct brw_reg sampler_index);
1070
1071 void gen4_math(struct brw_codegen *p,
1072 struct brw_reg dest,
1073 unsigned function,
1074 unsigned msg_reg_nr,
1075 struct brw_reg src,
1076 unsigned precision );
1077
1078 void gen6_math(struct brw_codegen *p,
1079 struct brw_reg dest,
1080 unsigned function,
1081 struct brw_reg src0,
1082 struct brw_reg src1);
1083
1084 void brw_oword_block_read(struct brw_codegen *p,
1085 struct brw_reg dest,
1086 struct brw_reg mrf,
1087 uint32_t offset,
1088 uint32_t bind_table_index);
1089
1090 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1091
1092 void brw_oword_block_read_scratch(struct brw_codegen *p,
1093 struct brw_reg dest,
1094 struct brw_reg mrf,
1095 int num_regs,
1096 unsigned offset);
1097
1098 void brw_oword_block_write_scratch(struct brw_codegen *p,
1099 struct brw_reg mrf,
1100 int num_regs,
1101 unsigned offset);
1102
1103 void gen7_block_read_scratch(struct brw_codegen *p,
1104 struct brw_reg dest,
1105 int num_regs,
1106 unsigned offset);
1107
1108 void brw_shader_time_add(struct brw_codegen *p,
1109 struct brw_reg payload,
1110 uint32_t surf_index);
1111
1112 /**
1113 * Return the generation-specific jump distance scaling factor.
1114 *
1115 * Given the number of instructions to jump, we need to scale by
1116 * some number to obtain the actual jump distance to program in an
1117 * instruction.
1118 */
1119 static inline unsigned
1120 brw_jump_scale(const struct gen_device_info *devinfo)
1121 {
1122 /* Broadwell measures jump targets in bytes. */
1123 if (devinfo->gen >= 8)
1124 return 16;
1125
1126 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1127 * (to support compaction), so each 128-bit instruction requires 2 chunks.
1128 */
1129 if (devinfo->gen >= 5)
1130 return 2;
1131
1132 /* Gen4 simply uses the number of 128-bit instructions. */
1133 return 1;
1134 }
1135
1136 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1137
1138 /* If/else/endif. Works by manipulating the execution flags on each
1139 * channel.
1140 */
1141 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1142 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1143 struct brw_reg src0, struct brw_reg src1);
1144
1145 void brw_ELSE(struct brw_codegen *p);
1146 void brw_ENDIF(struct brw_codegen *p);
1147
1148 /* DO/WHILE loops:
1149 */
1150 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1151
1152 brw_inst *brw_WHILE(struct brw_codegen *p);
1153
1154 brw_inst *brw_BREAK(struct brw_codegen *p);
1155 brw_inst *brw_CONT(struct brw_codegen *p);
1156 brw_inst *brw_HALT(struct brw_codegen *p);
1157
1158 /* Forward jumps:
1159 */
1160 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1161
1162 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1163 unsigned predicate_control);
1164
1165 void brw_NOP(struct brw_codegen *p);
1166
1167 void brw_WAIT(struct brw_codegen *p);
1168
1169 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func);
1170
1171 /* Special case: there is never a destination, execution size will be
1172 * taken from src0:
1173 */
1174 void brw_CMP(struct brw_codegen *p,
1175 struct brw_reg dest,
1176 unsigned conditional,
1177 struct brw_reg src0,
1178 struct brw_reg src1);
1179
1180 void
1181 brw_untyped_atomic(struct brw_codegen *p,
1182 struct brw_reg dst,
1183 struct brw_reg payload,
1184 struct brw_reg surface,
1185 unsigned atomic_op,
1186 unsigned msg_length,
1187 bool response_expected,
1188 bool header_present);
1189
1190 void
1191 brw_untyped_surface_read(struct brw_codegen *p,
1192 struct brw_reg dst,
1193 struct brw_reg payload,
1194 struct brw_reg surface,
1195 unsigned msg_length,
1196 unsigned num_channels);
1197
1198 void
1199 brw_untyped_surface_write(struct brw_codegen *p,
1200 struct brw_reg payload,
1201 struct brw_reg surface,
1202 unsigned msg_length,
1203 unsigned num_channels,
1204 bool header_present);
1205
1206 void
1207 brw_memory_fence(struct brw_codegen *p,
1208 struct brw_reg dst,
1209 struct brw_reg src,
1210 enum opcode send_op,
1211 enum brw_message_target sfid,
1212 bool commit_enable,
1213 unsigned bti);
1214
1215 void
1216 brw_pixel_interpolator_query(struct brw_codegen *p,
1217 struct brw_reg dest,
1218 struct brw_reg mrf,
1219 bool noperspective,
1220 unsigned mode,
1221 struct brw_reg data,
1222 unsigned msg_length,
1223 unsigned response_length);
1224
1225 void
1226 brw_find_live_channel(struct brw_codegen *p,
1227 struct brw_reg dst,
1228 struct brw_reg mask);
1229
1230 void
1231 brw_broadcast(struct brw_codegen *p,
1232 struct brw_reg dst,
1233 struct brw_reg src,
1234 struct brw_reg idx);
1235
1236 void
1237 brw_float_controls_mode(struct brw_codegen *p,
1238 unsigned mode, unsigned mask);
1239
1240 /***********************************************************************
1241 * brw_eu_util.c:
1242 */
1243
1244 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1245 struct brw_indirect dst_ptr,
1246 struct brw_indirect src_ptr,
1247 unsigned count);
1248
1249 void brw_copy_from_indirect(struct brw_codegen *p,
1250 struct brw_reg dst,
1251 struct brw_indirect ptr,
1252 unsigned count);
1253
1254 void brw_copy4(struct brw_codegen *p,
1255 struct brw_reg dst,
1256 struct brw_reg src,
1257 unsigned count);
1258
1259 void brw_copy8(struct brw_codegen *p,
1260 struct brw_reg dst,
1261 struct brw_reg src,
1262 unsigned count);
1263
1264 void brw_math_invert( struct brw_codegen *p,
1265 struct brw_reg dst,
1266 struct brw_reg src);
1267
1268 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1269
1270 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1271 unsigned desc, unsigned ex_desc);
1272
1273 static inline void
1274 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1275 {
1276 brw_set_desc_ex(p, insn, desc, 0);
1277 }
1278
1279 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1280
1281 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1282 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1283
1284 /* brw_eu_compact.c */
1285 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1286 struct disasm_info *disasm);
1287 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1288 brw_inst *dst, brw_compact_inst *src);
1289 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1290 brw_compact_inst *dst, const brw_inst *src);
1291
1292 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1293 brw_inst *orig, brw_inst *uncompacted);
1294
1295 /* brw_eu_validate.c */
1296 bool brw_validate_instruction(const struct gen_device_info *devinfo,
1297 const brw_inst *inst, int offset,
1298 struct disasm_info *disasm);
1299 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1300 const void *assembly, int start_offset, int end_offset,
1301 struct disasm_info *disasm);
1302
1303 static inline int
1304 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1305 {
1306 brw_inst *insn = (brw_inst *)((char *)store + offset);
1307
1308 if (brw_inst_cmpt_control(devinfo, insn))
1309 return offset + 8;
1310 else
1311 return offset + 16;
1312 }
1313
1314 struct opcode_desc {
1315 unsigned ir;
1316 unsigned hw;
1317 const char *name;
1318 int nsrc;
1319 int ndst;
1320 int gens;
1321 };
1322
1323 const struct opcode_desc *
1324 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1325
1326 const struct opcode_desc *
1327 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1328
1329 static inline unsigned
1330 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1331 {
1332 return brw_opcode_desc(devinfo, opcode)->hw;
1333 }
1334
1335 static inline enum opcode
1336 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1337 {
1338 const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1339 return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1340 }
1341
1342 static inline void
1343 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1344 brw_inst *inst, enum opcode opcode)
1345 {
1346 brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1347 }
1348
1349 static inline enum opcode
1350 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1351 {
1352 return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1353 }
1354
1355 static inline bool
1356 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1357 {
1358 const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1359 return desc && desc->nsrc == 3;
1360 }
1361
1362 /** Maximum SEND message length */
1363 #define BRW_MAX_MSG_LENGTH 15
1364
1365 /** First MRF register used by pull loads */
1366 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1367
1368 /** First MRF register used by spills */
1369 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1370
1371 #ifdef __cplusplus
1372 }
1373 #endif
1374
1375 #endif