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[mesa.git] / src / intel / compiler / brw_eu.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_EU_H
34 #define BRW_EU_H
35
36 #include <stdbool.h>
37 #include <stdio.h>
38 #include "brw_inst.h"
39 #include "brw_eu_defines.h"
40 #include "brw_reg.h"
41 #include "brw_disasm_info.h"
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 #define BRW_EU_MAX_INSN_STACK 5
48
49 struct brw_insn_state {
50 /* One of BRW_EXECUTE_* */
51 unsigned exec_size:3;
52
53 /* Group in units of channels */
54 unsigned group:5;
55
56 /* Compression control on gen4-5 */
57 bool compressed:1;
58
59 /* One of BRW_MASK_* */
60 unsigned mask_control:1;
61
62 /* Scheduling info for Gen12+ */
63 struct tgl_swsb swsb;
64
65 bool saturate:1;
66
67 /* One of BRW_ALIGN_* */
68 unsigned access_mode:1;
69
70 /* One of BRW_PREDICATE_* */
71 enum brw_predicate predicate:4;
72
73 bool pred_inv:1;
74
75 /* Flag subreg. Bottom bit is subreg, top bit is reg */
76 unsigned flag_subreg:2;
77
78 bool acc_wr_control:1;
79 };
80
81
82 /* A helper for accessing the last instruction emitted. This makes it easy
83 * to set various bits on an instruction without having to create temporary
84 * variable and assign the emitted instruction to those.
85 */
86 #define brw_last_inst (&p->store[p->nr_insn - 1])
87
88 struct brw_codegen {
89 brw_inst *store;
90 int store_size;
91 unsigned nr_insn;
92 unsigned int next_insn_offset;
93
94 void *mem_ctx;
95
96 /* Allow clients to push/pop instruction state:
97 */
98 struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
99 struct brw_insn_state *current;
100
101 /** Whether or not the user wants automatic exec sizes
102 *
103 * If true, codegen will try to automatically infer the exec size of an
104 * instruction from the width of the destination register. If false, it
105 * will take whatever is set by brw_set_default_exec_size verbatim.
106 *
107 * This is set to true by default in brw_init_codegen.
108 */
109 bool automatic_exec_sizes;
110
111 bool single_program_flow;
112 const struct gen_device_info *devinfo;
113
114 /* Control flow stacks:
115 * - if_stack contains IF and ELSE instructions which must be patched
116 * (and popped) once the matching ENDIF instruction is encountered.
117 *
118 * Just store the instruction pointer(an index).
119 */
120 int *if_stack;
121 int if_stack_depth;
122 int if_stack_array_size;
123
124 /**
125 * loop_stack contains the instruction pointers of the starts of loops which
126 * must be patched (and popped) once the matching WHILE instruction is
127 * encountered.
128 */
129 int *loop_stack;
130 /**
131 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
132 * blocks they were popping out of, to fix up the mask stack. This tracks
133 * the IF/ENDIF nesting in each current nested loop level.
134 */
135 int *if_depth_in_loop;
136 int loop_stack_depth;
137 int loop_stack_array_size;
138 };
139
140 struct brw_label {
141 int offset;
142 int number;
143 struct brw_label *next;
144 };
145
146 void brw_pop_insn_state( struct brw_codegen *p );
147 void brw_push_insn_state( struct brw_codegen *p );
148 unsigned brw_get_default_exec_size(struct brw_codegen *p);
149 unsigned brw_get_default_group(struct brw_codegen *p);
150 unsigned brw_get_default_access_mode(struct brw_codegen *p);
151 struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
152 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
153 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
154 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
155 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
156 void brw_inst_set_compression(const struct gen_device_info *devinfo,
157 brw_inst *inst, bool on);
158 void brw_set_default_compression(struct brw_codegen *p, bool on);
159 void brw_inst_set_group(const struct gen_device_info *devinfo,
160 brw_inst *inst, unsigned group);
161 void brw_set_default_group(struct brw_codegen *p, unsigned group);
162 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
163 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
164 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
165 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
166 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
167 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
168
169 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
170 void *mem_ctx);
171 bool brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode);
172 bool brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode);
173 const struct brw_label *brw_find_label(const struct brw_label *root, int offset);
174 void brw_create_label(struct brw_label **labels, int offset, void *mem_ctx);
175 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
176 const struct brw_inst *inst, bool is_compacted,
177 int offset, const struct brw_label *root_label);
178 const struct brw_label *brw_label_assembly(const struct gen_device_info *devinfo,
179 const void *assembly, int start, int end,
180 void *mem_ctx);
181 void brw_disassemble_with_labels(const struct gen_device_info *devinfo,
182 const void *assembly, int start, int end, FILE *out);
183 void brw_disassemble(const struct gen_device_info *devinfo,
184 const void *assembly, int start, int end,
185 const struct brw_label *root_label, FILE *out);
186 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
187
188 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
189 const char *identifier);
190
191 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
192 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
193 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
194
195 void gen6_resolve_implied_move(struct brw_codegen *p,
196 struct brw_reg *src,
197 unsigned msg_reg_nr);
198
199 /* Helpers for regular instructions:
200 */
201 #define ALU1(OP) \
202 brw_inst *brw_##OP(struct brw_codegen *p, \
203 struct brw_reg dest, \
204 struct brw_reg src0);
205
206 #define ALU2(OP) \
207 brw_inst *brw_##OP(struct brw_codegen *p, \
208 struct brw_reg dest, \
209 struct brw_reg src0, \
210 struct brw_reg src1);
211
212 #define ALU3(OP) \
213 brw_inst *brw_##OP(struct brw_codegen *p, \
214 struct brw_reg dest, \
215 struct brw_reg src0, \
216 struct brw_reg src1, \
217 struct brw_reg src2);
218
219 ALU1(MOV)
220 ALU2(SEL)
221 ALU1(NOT)
222 ALU2(AND)
223 ALU2(OR)
224 ALU2(XOR)
225 ALU2(SHR)
226 ALU2(SHL)
227 ALU1(DIM)
228 ALU2(ASR)
229 ALU2(ROL)
230 ALU2(ROR)
231 ALU3(CSEL)
232 ALU1(F32TO16)
233 ALU1(F16TO32)
234 ALU2(ADD)
235 ALU2(AVG)
236 ALU2(MUL)
237 ALU1(FRC)
238 ALU1(RNDD)
239 ALU1(RNDE)
240 ALU1(RNDU)
241 ALU1(RNDZ)
242 ALU2(MAC)
243 ALU2(MACH)
244 ALU1(LZD)
245 ALU2(DP4)
246 ALU2(DPH)
247 ALU2(DP3)
248 ALU2(DP2)
249 ALU2(LINE)
250 ALU2(PLN)
251 ALU3(MAD)
252 ALU3(LRP)
253 ALU1(BFREV)
254 ALU3(BFE)
255 ALU2(BFI1)
256 ALU3(BFI2)
257 ALU1(FBH)
258 ALU1(FBL)
259 ALU1(CBIT)
260 ALU2(ADDC)
261 ALU2(SUBB)
262 ALU2(MAC)
263
264 #undef ALU1
265 #undef ALU2
266 #undef ALU3
267
268
269 /* Helpers for SEND instruction:
270 */
271
272 /**
273 * Construct a message descriptor immediate with the specified common
274 * descriptor controls.
275 */
276 static inline uint32_t
277 brw_message_desc(const struct gen_device_info *devinfo,
278 unsigned msg_length,
279 unsigned response_length,
280 bool header_present)
281 {
282 if (devinfo->gen >= 5) {
283 return (SET_BITS(msg_length, 28, 25) |
284 SET_BITS(response_length, 24, 20) |
285 SET_BITS(header_present, 19, 19));
286 } else {
287 return (SET_BITS(msg_length, 23, 20) |
288 SET_BITS(response_length, 19, 16));
289 }
290 }
291
292 static inline unsigned
293 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
294 {
295 if (devinfo->gen >= 5)
296 return GET_BITS(desc, 28, 25);
297 else
298 return GET_BITS(desc, 23, 20);
299 }
300
301 static inline unsigned
302 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
303 {
304 if (devinfo->gen >= 5)
305 return GET_BITS(desc, 24, 20);
306 else
307 return GET_BITS(desc, 19, 16);
308 }
309
310 static inline bool
311 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
312 uint32_t desc)
313 {
314 assert(devinfo->gen >= 5);
315 return GET_BITS(desc, 19, 19);
316 }
317
318 static inline unsigned
319 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
320 unsigned ex_msg_length)
321 {
322 return SET_BITS(ex_msg_length, 9, 6);
323 }
324
325 static inline unsigned
326 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
327 uint32_t ex_desc)
328 {
329 return GET_BITS(ex_desc, 9, 6);
330 }
331
332 static inline uint32_t
333 brw_urb_desc(const struct gen_device_info *devinfo,
334 unsigned msg_type,
335 bool per_slot_offset_present,
336 bool channel_mask_present,
337 unsigned global_offset)
338 {
339 if (devinfo->gen >= 8) {
340 return (SET_BITS(per_slot_offset_present, 17, 17) |
341 SET_BITS(channel_mask_present, 15, 15) |
342 SET_BITS(global_offset, 14, 4) |
343 SET_BITS(msg_type, 3, 0));
344 } else if (devinfo->gen >= 7) {
345 assert(!channel_mask_present);
346 return (SET_BITS(per_slot_offset_present, 16, 16) |
347 SET_BITS(global_offset, 13, 3) |
348 SET_BITS(msg_type, 3, 0));
349 } else {
350 unreachable("unhandled URB write generation");
351 }
352 }
353
354 static inline uint32_t
355 brw_urb_desc_msg_type(ASSERTED const struct gen_device_info *devinfo,
356 uint32_t desc)
357 {
358 assert(devinfo->gen >= 7);
359 return GET_BITS(desc, 3, 0);
360 }
361
362 /**
363 * Construct a message descriptor immediate with the specified sampler
364 * function controls.
365 */
366 static inline uint32_t
367 brw_sampler_desc(const struct gen_device_info *devinfo,
368 unsigned binding_table_index,
369 unsigned sampler,
370 unsigned msg_type,
371 unsigned simd_mode,
372 unsigned return_format)
373 {
374 const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
375 SET_BITS(sampler, 11, 8));
376 if (devinfo->gen >= 7)
377 return (desc | SET_BITS(msg_type, 16, 12) |
378 SET_BITS(simd_mode, 18, 17));
379 else if (devinfo->gen >= 5)
380 return (desc | SET_BITS(msg_type, 15, 12) |
381 SET_BITS(simd_mode, 17, 16));
382 else if (devinfo->is_g4x)
383 return desc | SET_BITS(msg_type, 15, 12);
384 else
385 return (desc | SET_BITS(return_format, 13, 12) |
386 SET_BITS(msg_type, 15, 14));
387 }
388
389 static inline unsigned
390 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
391 uint32_t desc)
392 {
393 return GET_BITS(desc, 7, 0);
394 }
395
396 static inline unsigned
397 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
398 {
399 return GET_BITS(desc, 11, 8);
400 }
401
402 static inline unsigned
403 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
404 {
405 if (devinfo->gen >= 7)
406 return GET_BITS(desc, 16, 12);
407 else if (devinfo->gen >= 5 || devinfo->is_g4x)
408 return GET_BITS(desc, 15, 12);
409 else
410 return GET_BITS(desc, 15, 14);
411 }
412
413 static inline unsigned
414 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
415 {
416 assert(devinfo->gen >= 5);
417 if (devinfo->gen >= 7)
418 return GET_BITS(desc, 18, 17);
419 else
420 return GET_BITS(desc, 17, 16);
421 }
422
423 static inline unsigned
424 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
425 uint32_t desc)
426 {
427 assert(devinfo->gen == 4 && !devinfo->is_g4x);
428 return GET_BITS(desc, 13, 12);
429 }
430
431 /**
432 * Construct a message descriptor for the dataport
433 */
434 static inline uint32_t
435 brw_dp_desc(const struct gen_device_info *devinfo,
436 unsigned binding_table_index,
437 unsigned msg_type,
438 unsigned msg_control)
439 {
440 /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
441 * helpers instead.
442 */
443 assert(devinfo->gen >= 6);
444 const unsigned desc = SET_BITS(binding_table_index, 7, 0);
445 if (devinfo->gen >= 8) {
446 return (desc | SET_BITS(msg_control, 13, 8) |
447 SET_BITS(msg_type, 18, 14));
448 } else if (devinfo->gen >= 7) {
449 return (desc | SET_BITS(msg_control, 13, 8) |
450 SET_BITS(msg_type, 17, 14));
451 } else {
452 return (desc | SET_BITS(msg_control, 12, 8) |
453 SET_BITS(msg_type, 16, 13));
454 }
455 }
456
457 static inline unsigned
458 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
459 uint32_t desc)
460 {
461 return GET_BITS(desc, 7, 0);
462 }
463
464 static inline unsigned
465 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
466 {
467 assert(devinfo->gen >= 6);
468 if (devinfo->gen >= 8)
469 return GET_BITS(desc, 18, 14);
470 else if (devinfo->gen >= 7)
471 return GET_BITS(desc, 17, 14);
472 else
473 return GET_BITS(desc, 16, 13);
474 }
475
476 static inline unsigned
477 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
478 {
479 assert(devinfo->gen >= 6);
480 if (devinfo->gen >= 7)
481 return GET_BITS(desc, 13, 8);
482 else
483 return GET_BITS(desc, 12, 8);
484 }
485
486 /**
487 * Construct a message descriptor immediate with the specified dataport read
488 * function controls.
489 */
490 static inline uint32_t
491 brw_dp_read_desc(const struct gen_device_info *devinfo,
492 unsigned binding_table_index,
493 unsigned msg_control,
494 unsigned msg_type,
495 unsigned target_cache)
496 {
497 if (devinfo->gen >= 6)
498 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
499 else if (devinfo->gen >= 5 || devinfo->is_g4x)
500 return (SET_BITS(binding_table_index, 7, 0) |
501 SET_BITS(msg_control, 10, 8) |
502 SET_BITS(msg_type, 13, 11) |
503 SET_BITS(target_cache, 15, 14));
504 else
505 return (SET_BITS(binding_table_index, 7, 0) |
506 SET_BITS(msg_control, 11, 8) |
507 SET_BITS(msg_type, 13, 12) |
508 SET_BITS(target_cache, 15, 14));
509 }
510
511 static inline unsigned
512 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
513 {
514 if (devinfo->gen >= 6)
515 return brw_dp_desc_msg_type(devinfo, desc);
516 else if (devinfo->gen >= 5 || devinfo->is_g4x)
517 return GET_BITS(desc, 13, 11);
518 else
519 return GET_BITS(desc, 13, 12);
520 }
521
522 static inline unsigned
523 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
524 uint32_t desc)
525 {
526 if (devinfo->gen >= 6)
527 return brw_dp_desc_msg_control(devinfo, desc);
528 else if (devinfo->gen >= 5 || devinfo->is_g4x)
529 return GET_BITS(desc, 10, 8);
530 else
531 return GET_BITS(desc, 11, 8);
532 }
533
534 /**
535 * Construct a message descriptor immediate with the specified dataport write
536 * function controls.
537 */
538 static inline uint32_t
539 brw_dp_write_desc(const struct gen_device_info *devinfo,
540 unsigned binding_table_index,
541 unsigned msg_control,
542 unsigned msg_type,
543 unsigned last_render_target,
544 unsigned send_commit_msg)
545 {
546 assert(devinfo->gen <= 6 || !send_commit_msg);
547 if (devinfo->gen >= 6)
548 return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
549 SET_BITS(last_render_target, 12, 12) |
550 SET_BITS(send_commit_msg, 17, 17);
551 else
552 return (SET_BITS(binding_table_index, 7, 0) |
553 SET_BITS(msg_control, 11, 8) |
554 SET_BITS(last_render_target, 11, 11) |
555 SET_BITS(msg_type, 14, 12) |
556 SET_BITS(send_commit_msg, 15, 15));
557 }
558
559 static inline unsigned
560 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
561 uint32_t desc)
562 {
563 if (devinfo->gen >= 6)
564 return brw_dp_desc_msg_type(devinfo, desc);
565 else
566 return GET_BITS(desc, 14, 12);
567 }
568
569 static inline unsigned
570 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
571 uint32_t desc)
572 {
573 if (devinfo->gen >= 6)
574 return brw_dp_desc_msg_control(devinfo, desc);
575 else
576 return GET_BITS(desc, 11, 8);
577 }
578
579 static inline bool
580 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
581 uint32_t desc)
582 {
583 if (devinfo->gen >= 6)
584 return GET_BITS(desc, 12, 12);
585 else
586 return GET_BITS(desc, 11, 11);
587 }
588
589 static inline bool
590 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
591 uint32_t desc)
592 {
593 assert(devinfo->gen <= 6);
594 if (devinfo->gen >= 6)
595 return GET_BITS(desc, 17, 17);
596 else
597 return GET_BITS(desc, 15, 15);
598 }
599
600 /**
601 * Construct a message descriptor immediate with the specified dataport
602 * surface function controls.
603 */
604 static inline uint32_t
605 brw_dp_surface_desc(const struct gen_device_info *devinfo,
606 unsigned msg_type,
607 unsigned msg_control)
608 {
609 assert(devinfo->gen >= 7);
610 /* We'll OR in the binding table index later */
611 return brw_dp_desc(devinfo, 0, msg_type, msg_control);
612 }
613
614 static inline uint32_t
615 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
616 unsigned exec_size, /**< 0 for SIMD4x2 */
617 unsigned atomic_op,
618 bool response_expected)
619 {
620 assert(exec_size <= 8 || exec_size == 16);
621
622 unsigned msg_type;
623 if (devinfo->gen >= 8 || devinfo->is_haswell) {
624 if (exec_size > 0) {
625 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
626 } else {
627 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
628 }
629 } else {
630 msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
631 }
632
633 const unsigned msg_control =
634 SET_BITS(atomic_op, 3, 0) |
635 SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
636 SET_BITS(response_expected, 5, 5);
637
638 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
639 }
640
641 static inline uint32_t
642 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
643 unsigned exec_size,
644 unsigned atomic_op,
645 bool response_expected)
646 {
647 assert(exec_size <= 8 || exec_size == 16);
648 assert(devinfo->gen >= 9);
649
650 assert(exec_size > 0);
651 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
652
653 const unsigned msg_control =
654 SET_BITS(atomic_op, 1, 0) |
655 SET_BITS(exec_size <= 8, 4, 4) |
656 SET_BITS(response_expected, 5, 5);
657
658 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
659 }
660
661 static inline unsigned
662 brw_mdc_cmask(unsigned num_channels)
663 {
664 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
665 return 0xf & (0xf << num_channels);
666 }
667
668 static inline uint32_t
669 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
670 unsigned exec_size, /**< 0 for SIMD4x2 */
671 unsigned num_channels,
672 bool write)
673 {
674 assert(exec_size <= 8 || exec_size == 16);
675
676 unsigned msg_type;
677 if (write) {
678 if (devinfo->gen >= 8 || devinfo->is_haswell) {
679 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
680 } else {
681 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
682 }
683 } else {
684 /* Read */
685 if (devinfo->gen >= 8 || devinfo->is_haswell) {
686 msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
687 } else {
688 msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
689 }
690 }
691
692 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
693 if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
694 exec_size = 8;
695
696 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
697 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
698 exec_size <= 8 ? 2 : 1;
699
700 const unsigned msg_control =
701 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
702 SET_BITS(simd_mode, 5, 4);
703
704 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
705 }
706
707 static inline unsigned
708 brw_mdc_ds(unsigned bit_size)
709 {
710 switch (bit_size) {
711 case 8:
712 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
713 case 16:
714 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
715 case 32:
716 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
717 default:
718 unreachable("Unsupported bit_size for byte scattered messages");
719 }
720 }
721
722 static inline uint32_t
723 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
724 unsigned exec_size,
725 unsigned bit_size,
726 bool write)
727 {
728 assert(exec_size <= 8 || exec_size == 16);
729
730 assert(devinfo->gen > 7 || devinfo->is_haswell);
731 const unsigned msg_type =
732 write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
733 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
734
735 assert(exec_size > 0);
736 const unsigned msg_control =
737 SET_BITS(exec_size == 16, 0, 0) |
738 SET_BITS(brw_mdc_ds(bit_size), 3, 2);
739
740 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
741 }
742
743 static inline uint32_t
744 brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
745 unsigned exec_size,
746 bool write)
747 {
748 assert(exec_size == 8 || exec_size == 16);
749
750 unsigned msg_type;
751 if (write) {
752 if (devinfo->gen >= 6) {
753 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
754 } else {
755 msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
756 }
757 } else {
758 if (devinfo->gen >= 7) {
759 msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
760 } else if (devinfo->gen > 4 || devinfo->is_g4x) {
761 msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
762 } else {
763 msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
764 }
765 }
766
767 const unsigned msg_control =
768 SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
769 SET_BITS(exec_size == 16, 0, 0);
770
771 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
772 }
773
774 static inline uint32_t
775 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
776 unsigned exec_size, /**< 0 for SIMD4x2 */
777 unsigned num_channels,
778 bool write)
779 {
780 assert(exec_size <= 8 || exec_size == 16);
781 assert(devinfo->gen >= 8);
782
783 unsigned msg_type =
784 write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
785 GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
786
787 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
788 const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
789 exec_size <= 8 ? 2 : 1;
790
791 const unsigned msg_control =
792 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
793 SET_BITS(simd_mode, 5, 4);
794
795 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
796 msg_type, msg_control);
797 }
798
799 /**
800 * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
801 * Skylake PRM).
802 */
803 static inline uint32_t
804 brw_mdc_a64_ds(unsigned elems)
805 {
806 switch (elems) {
807 case 1: return 0;
808 case 2: return 1;
809 case 4: return 2;
810 case 8: return 3;
811 default:
812 unreachable("Unsupported elmeent count for A64 scattered message");
813 }
814 }
815
816 static inline uint32_t
817 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
818 unsigned exec_size, /**< 0 for SIMD4x2 */
819 unsigned bit_size,
820 bool write)
821 {
822 assert(exec_size <= 8 || exec_size == 16);
823 assert(devinfo->gen >= 8);
824
825 unsigned msg_type =
826 write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
827 GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
828
829 const unsigned msg_control =
830 SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
831 SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
832 SET_BITS(exec_size == 16, 4, 4);
833
834 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
835 msg_type, msg_control);
836 }
837
838 static inline uint32_t
839 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
840 ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
841 unsigned bit_size,
842 unsigned atomic_op,
843 bool response_expected)
844 {
845 assert(exec_size == 8);
846 assert(devinfo->gen >= 8);
847 assert(bit_size == 32 || bit_size == 64);
848
849 const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
850
851 const unsigned msg_control =
852 SET_BITS(atomic_op, 3, 0) |
853 SET_BITS(bit_size == 64, 4, 4) |
854 SET_BITS(response_expected, 5, 5);
855
856 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
857 msg_type, msg_control);
858 }
859
860 static inline uint32_t
861 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
862 ASSERTED unsigned exec_size,
863 unsigned atomic_op,
864 bool response_expected)
865 {
866 assert(exec_size == 8);
867 assert(devinfo->gen >= 9);
868
869 assert(exec_size > 0);
870 const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
871
872 const unsigned msg_control =
873 SET_BITS(atomic_op, 1, 0) |
874 SET_BITS(response_expected, 5, 5);
875
876 return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
877 msg_type, msg_control);
878 }
879
880 static inline uint32_t
881 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
882 unsigned exec_size,
883 unsigned exec_group,
884 unsigned atomic_op,
885 bool response_expected)
886 {
887 assert(exec_size > 0 || exec_group == 0);
888 assert(exec_group % 8 == 0);
889
890 unsigned msg_type;
891 if (devinfo->gen >= 8 || devinfo->is_haswell) {
892 if (exec_size == 0) {
893 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
894 } else {
895 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
896 }
897 } else {
898 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
899 assert(exec_size > 0);
900 msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
901 }
902
903 const bool high_sample_mask = (exec_group / 8) % 2 == 1;
904
905 const unsigned msg_control =
906 SET_BITS(atomic_op, 3, 0) |
907 SET_BITS(high_sample_mask, 4, 4) |
908 SET_BITS(response_expected, 5, 5);
909
910 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
911 }
912
913 static inline uint32_t
914 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
915 unsigned exec_size,
916 unsigned exec_group,
917 unsigned num_channels,
918 bool write)
919 {
920 assert(exec_size > 0 || exec_group == 0);
921 assert(exec_group % 8 == 0);
922
923 /* Typed surface reads and writes don't support SIMD16 */
924 assert(exec_size <= 8);
925
926 unsigned msg_type;
927 if (write) {
928 if (devinfo->gen >= 8 || devinfo->is_haswell) {
929 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
930 } else {
931 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
932 }
933 } else {
934 if (devinfo->gen >= 8 || devinfo->is_haswell) {
935 msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
936 } else {
937 msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
938 }
939 }
940
941 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
942 unsigned msg_control;
943 if (devinfo->gen >= 8 || devinfo->is_haswell) {
944 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
945 const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
946 1 + ((exec_group / 8) % 2);
947
948 msg_control =
949 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
950 SET_BITS(slot_group, 5, 4);
951 } else {
952 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
953 assert(exec_size > 0);
954 const unsigned slot_group = ((exec_group / 8) % 2);
955
956 msg_control =
957 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
958 SET_BITS(slot_group, 5, 5);
959 }
960
961 return brw_dp_surface_desc(devinfo, msg_type, msg_control);
962 }
963
964 /**
965 * Construct a message descriptor immediate with the specified pixel
966 * interpolator function controls.
967 */
968 static inline uint32_t
969 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
970 unsigned msg_type,
971 bool noperspective,
972 unsigned simd_mode,
973 unsigned slot_group)
974 {
975 return (SET_BITS(slot_group, 11, 11) |
976 SET_BITS(msg_type, 13, 12) |
977 SET_BITS(!!noperspective, 14, 14) |
978 SET_BITS(simd_mode, 16, 16));
979 }
980
981 void brw_urb_WRITE(struct brw_codegen *p,
982 struct brw_reg dest,
983 unsigned msg_reg_nr,
984 struct brw_reg src0,
985 enum brw_urb_write_flags flags,
986 unsigned msg_length,
987 unsigned response_length,
988 unsigned offset,
989 unsigned swizzle);
990
991 /**
992 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
993 * desc. If \p desc is not an immediate it will be transparently loaded to an
994 * address register using an OR instruction.
995 */
996 void
997 brw_send_indirect_message(struct brw_codegen *p,
998 unsigned sfid,
999 struct brw_reg dst,
1000 struct brw_reg payload,
1001 struct brw_reg desc,
1002 unsigned desc_imm,
1003 bool eot);
1004
1005 void
1006 brw_send_indirect_split_message(struct brw_codegen *p,
1007 unsigned sfid,
1008 struct brw_reg dst,
1009 struct brw_reg payload0,
1010 struct brw_reg payload1,
1011 struct brw_reg desc,
1012 unsigned desc_imm,
1013 struct brw_reg ex_desc,
1014 unsigned ex_desc_imm,
1015 bool eot);
1016
1017 void brw_ff_sync(struct brw_codegen *p,
1018 struct brw_reg dest,
1019 unsigned msg_reg_nr,
1020 struct brw_reg src0,
1021 bool allocate,
1022 unsigned response_length,
1023 bool eot);
1024
1025 void brw_svb_write(struct brw_codegen *p,
1026 struct brw_reg dest,
1027 unsigned msg_reg_nr,
1028 struct brw_reg src0,
1029 unsigned binding_table_index,
1030 bool send_commit_msg);
1031
1032 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
1033 struct brw_reg payload,
1034 struct brw_reg implied_header,
1035 unsigned msg_control,
1036 unsigned binding_table_index,
1037 unsigned msg_length,
1038 unsigned response_length,
1039 bool eot,
1040 bool last_render_target,
1041 bool header_present);
1042
1043 brw_inst *gen9_fb_READ(struct brw_codegen *p,
1044 struct brw_reg dst,
1045 struct brw_reg payload,
1046 unsigned binding_table_index,
1047 unsigned msg_length,
1048 unsigned response_length,
1049 bool per_sample);
1050
1051 void brw_SAMPLE(struct brw_codegen *p,
1052 struct brw_reg dest,
1053 unsigned msg_reg_nr,
1054 struct brw_reg src0,
1055 unsigned binding_table_index,
1056 unsigned sampler,
1057 unsigned msg_type,
1058 unsigned response_length,
1059 unsigned msg_length,
1060 unsigned header_present,
1061 unsigned simd_mode,
1062 unsigned return_format);
1063
1064 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
1065 struct brw_reg header,
1066 struct brw_reg sampler_index);
1067
1068 void gen4_math(struct brw_codegen *p,
1069 struct brw_reg dest,
1070 unsigned function,
1071 unsigned msg_reg_nr,
1072 struct brw_reg src,
1073 unsigned precision );
1074
1075 void gen6_math(struct brw_codegen *p,
1076 struct brw_reg dest,
1077 unsigned function,
1078 struct brw_reg src0,
1079 struct brw_reg src1);
1080
1081 void brw_oword_block_read(struct brw_codegen *p,
1082 struct brw_reg dest,
1083 struct brw_reg mrf,
1084 uint32_t offset,
1085 uint32_t bind_table_index);
1086
1087 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1088
1089 void brw_oword_block_read_scratch(struct brw_codegen *p,
1090 struct brw_reg dest,
1091 struct brw_reg mrf,
1092 int num_regs,
1093 unsigned offset);
1094
1095 void brw_oword_block_write_scratch(struct brw_codegen *p,
1096 struct brw_reg mrf,
1097 int num_regs,
1098 unsigned offset);
1099
1100 void gen7_block_read_scratch(struct brw_codegen *p,
1101 struct brw_reg dest,
1102 int num_regs,
1103 unsigned offset);
1104
1105 void brw_shader_time_add(struct brw_codegen *p,
1106 struct brw_reg payload,
1107 uint32_t surf_index);
1108
1109 /**
1110 * Return the generation-specific jump distance scaling factor.
1111 *
1112 * Given the number of instructions to jump, we need to scale by
1113 * some number to obtain the actual jump distance to program in an
1114 * instruction.
1115 */
1116 static inline unsigned
1117 brw_jump_scale(const struct gen_device_info *devinfo)
1118 {
1119 /* Broadwell measures jump targets in bytes. */
1120 if (devinfo->gen >= 8)
1121 return 16;
1122
1123 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1124 * (to support compaction), so each 128-bit instruction requires 2 chunks.
1125 */
1126 if (devinfo->gen >= 5)
1127 return 2;
1128
1129 /* Gen4 simply uses the number of 128-bit instructions. */
1130 return 1;
1131 }
1132
1133 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1134
1135 /* If/else/endif. Works by manipulating the execution flags on each
1136 * channel.
1137 */
1138 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1139 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1140 struct brw_reg src0, struct brw_reg src1);
1141
1142 void brw_ELSE(struct brw_codegen *p);
1143 void brw_ENDIF(struct brw_codegen *p);
1144
1145 /* DO/WHILE loops:
1146 */
1147 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1148
1149 brw_inst *brw_WHILE(struct brw_codegen *p);
1150
1151 brw_inst *brw_BREAK(struct brw_codegen *p);
1152 brw_inst *brw_CONT(struct brw_codegen *p);
1153 brw_inst *brw_HALT(struct brw_codegen *p);
1154
1155 /* Forward jumps:
1156 */
1157 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1158
1159 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1160 unsigned predicate_control);
1161
1162 void brw_NOP(struct brw_codegen *p);
1163
1164 void brw_WAIT(struct brw_codegen *p);
1165
1166 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func);
1167
1168 /* Special case: there is never a destination, execution size will be
1169 * taken from src0:
1170 */
1171 void brw_CMP(struct brw_codegen *p,
1172 struct brw_reg dest,
1173 unsigned conditional,
1174 struct brw_reg src0,
1175 struct brw_reg src1);
1176
1177 void
1178 brw_untyped_atomic(struct brw_codegen *p,
1179 struct brw_reg dst,
1180 struct brw_reg payload,
1181 struct brw_reg surface,
1182 unsigned atomic_op,
1183 unsigned msg_length,
1184 bool response_expected,
1185 bool header_present);
1186
1187 void
1188 brw_untyped_surface_read(struct brw_codegen *p,
1189 struct brw_reg dst,
1190 struct brw_reg payload,
1191 struct brw_reg surface,
1192 unsigned msg_length,
1193 unsigned num_channels);
1194
1195 void
1196 brw_untyped_surface_write(struct brw_codegen *p,
1197 struct brw_reg payload,
1198 struct brw_reg surface,
1199 unsigned msg_length,
1200 unsigned num_channels,
1201 bool header_present);
1202
1203 void
1204 brw_memory_fence(struct brw_codegen *p,
1205 struct brw_reg dst,
1206 struct brw_reg src,
1207 enum opcode send_op,
1208 enum brw_message_target sfid,
1209 bool commit_enable,
1210 unsigned bti);
1211
1212 void
1213 brw_pixel_interpolator_query(struct brw_codegen *p,
1214 struct brw_reg dest,
1215 struct brw_reg mrf,
1216 bool noperspective,
1217 unsigned mode,
1218 struct brw_reg data,
1219 unsigned msg_length,
1220 unsigned response_length);
1221
1222 void
1223 brw_find_live_channel(struct brw_codegen *p,
1224 struct brw_reg dst,
1225 struct brw_reg mask);
1226
1227 void
1228 brw_broadcast(struct brw_codegen *p,
1229 struct brw_reg dst,
1230 struct brw_reg src,
1231 struct brw_reg idx);
1232
1233 void
1234 brw_float_controls_mode(struct brw_codegen *p,
1235 unsigned mode, unsigned mask);
1236
1237 /***********************************************************************
1238 * brw_eu_util.c:
1239 */
1240
1241 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1242 struct brw_indirect dst_ptr,
1243 struct brw_indirect src_ptr,
1244 unsigned count);
1245
1246 void brw_copy_from_indirect(struct brw_codegen *p,
1247 struct brw_reg dst,
1248 struct brw_indirect ptr,
1249 unsigned count);
1250
1251 void brw_copy4(struct brw_codegen *p,
1252 struct brw_reg dst,
1253 struct brw_reg src,
1254 unsigned count);
1255
1256 void brw_copy8(struct brw_codegen *p,
1257 struct brw_reg dst,
1258 struct brw_reg src,
1259 unsigned count);
1260
1261 void brw_math_invert( struct brw_codegen *p,
1262 struct brw_reg dst,
1263 struct brw_reg src);
1264
1265 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1266
1267 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1268 unsigned desc, unsigned ex_desc);
1269
1270 static inline void
1271 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1272 {
1273 brw_set_desc_ex(p, insn, desc, 0);
1274 }
1275
1276 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1277
1278 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1279 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1280
1281 /* brw_eu_compact.c */
1282 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1283 struct disasm_info *disasm);
1284 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1285 brw_inst *dst, brw_compact_inst *src);
1286 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1287 brw_compact_inst *dst, const brw_inst *src);
1288
1289 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1290 brw_inst *orig, brw_inst *uncompacted);
1291
1292 /* brw_eu_validate.c */
1293 bool brw_validate_instruction(const struct gen_device_info *devinfo,
1294 const brw_inst *inst, int offset,
1295 struct disasm_info *disasm);
1296 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1297 const void *assembly, int start_offset, int end_offset,
1298 struct disasm_info *disasm);
1299
1300 static inline int
1301 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1302 {
1303 brw_inst *insn = (brw_inst *)((char *)store + offset);
1304
1305 if (brw_inst_cmpt_control(devinfo, insn))
1306 return offset + 8;
1307 else
1308 return offset + 16;
1309 }
1310
1311 struct opcode_desc {
1312 unsigned ir;
1313 unsigned hw;
1314 const char *name;
1315 int nsrc;
1316 int ndst;
1317 int gens;
1318 };
1319
1320 const struct opcode_desc *
1321 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1322
1323 const struct opcode_desc *
1324 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1325
1326 static inline unsigned
1327 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1328 {
1329 return brw_opcode_desc(devinfo, opcode)->hw;
1330 }
1331
1332 static inline enum opcode
1333 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1334 {
1335 const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1336 return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1337 }
1338
1339 static inline void
1340 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1341 brw_inst *inst, enum opcode opcode)
1342 {
1343 brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1344 }
1345
1346 static inline enum opcode
1347 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1348 {
1349 return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1350 }
1351
1352 static inline bool
1353 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1354 {
1355 const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1356 return desc && desc->nsrc == 3;
1357 }
1358
1359 /** Maximum SEND message length */
1360 #define BRW_MAX_MSG_LENGTH 15
1361
1362 /** First MRF register used by pull loads */
1363 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1364
1365 /** First MRF register used by spills */
1366 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1367
1368 #ifdef __cplusplus
1369 }
1370 #endif
1371
1372 #endif