src/intel/compiler/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include <stdbool.h>
  37 #include <stdio.h>
  38 #include "brw_inst.h"
  39 #include "brw_eu_defines.h"
  40 #include "brw_reg.h"
  41 #include "brw_disasm_info.h"
  42
  43 #ifdef __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define BRW_EU_MAX_INSN_STACK 5
  48
  49 struct brw_insn_state {
  50    /* One of BRW_EXECUTE_* */
  51    unsigned exec_size:3;
  52
  53    /* Group in units of channels */
  54    unsigned group:5;
  55
  56    /* Compression control on gen4-5 */
  57    bool compressed:1;
  58
  59    /* One of BRW_MASK_* */
  60    unsigned mask_control:1;
  61
  62    bool saturate:1;
  63
  64    /* One of BRW_ALIGN_* */
  65    unsigned access_mode:1;
  66
  67    /* One of BRW_PREDICATE_* */
  68    enum brw_predicate predicate:4;
  69
  70    bool pred_inv:1;
  71
  72    /* Flag subreg.  Bottom bit is subreg, top bit is reg */
  73    unsigned flag_subreg:2;
  74
  75    bool acc_wr_control:1;
  76 };
  77
  78
  79 /* A helper for accessing the last instruction emitted.  This makes it easy
  80  * to set various bits on an instruction without having to create temporary
  81  * variable and assign the emitted instruction to those.
  82  */
  83 #define brw_last_inst (&p->store[p->nr_insn - 1])
  84
  85 struct brw_codegen {
  86    brw_inst *store;
  87    int store_size;
  88    unsigned nr_insn;
  89    unsigned int next_insn_offset;
  90
  91    void *mem_ctx;
  92
  93    /* Allow clients to push/pop instruction state:
  94     */
  95    struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
  96    struct brw_insn_state *current;
  97
  98    /** Whether or not the user wants automatic exec sizes
  99     *
 100     * If true, codegen will try to automatically infer the exec size of an
 101     * instruction from the width of the destination register.  If false, it
 102     * will take whatever is set by brw_set_default_exec_size verbatim.
 103     *
 104     * This is set to true by default in brw_init_codegen.
 105     */
 106    bool automatic_exec_sizes;
 107
 108    bool single_program_flow;
 109    const struct gen_device_info *devinfo;
 110
 111    /* Control flow stacks:
 112     * - if_stack contains IF and ELSE instructions which must be patched
 113     *   (and popped) once the matching ENDIF instruction is encountered.
 114     *
 115     *   Just store the instruction pointer(an index).
 116     */
 117    int *if_stack;
 118    int if_stack_depth;
 119    int if_stack_array_size;
 120
 121    /**
 122     * loop_stack contains the instruction pointers of the starts of loops which
 123     * must be patched (and popped) once the matching WHILE instruction is
 124     * encountered.
 125     */
 126    int *loop_stack;
 127    /**
 128     * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
 129     * blocks they were popping out of, to fix up the mask stack.  This tracks
 130     * the IF/ENDIF nesting in each current nested loop level.
 131     */
 132    int *if_depth_in_loop;
 133    int loop_stack_depth;
 134    int loop_stack_array_size;
 135 };
 136
 137 void brw_pop_insn_state( struct brw_codegen *p );
 138 void brw_push_insn_state( struct brw_codegen *p );
 139 unsigned brw_get_default_exec_size(struct brw_codegen *p);
 140 unsigned brw_get_default_group(struct brw_codegen *p);
 141 unsigned brw_get_default_access_mode(struct brw_codegen *p);
 142 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
 143 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
 144 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
 145 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
 146 void brw_inst_set_compression(const struct gen_device_info *devinfo,
 147                               brw_inst *inst, bool on);
 148 void brw_set_default_compression(struct brw_codegen *p, bool on);
 149 void brw_inst_set_group(const struct gen_device_info *devinfo,
 150                         brw_inst *inst, unsigned group);
 151 void brw_set_default_group(struct brw_codegen *p, unsigned group);
 152 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
 153 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
 154 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
 155 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
 156 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
 157
 158 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
 159                       void *mem_ctx);
 160 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
 161                          const struct brw_inst *inst, bool is_compacted);
 162 void brw_disassemble(const struct gen_device_info *devinfo,
 163                      const void *assembly, int start, int end, FILE *out);
 164 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
 165
 166 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
 167                                const char *identifier);
 168
 169 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
 170 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
 171 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
 172
 173 void gen6_resolve_implied_move(struct brw_codegen *p,
 174                                struct brw_reg *src,
 175                                unsigned msg_reg_nr);
 176
 177 /* Helpers for regular instructions:
 178  */
 179 #define ALU1(OP)                                \
 180 brw_inst *brw_##OP(struct brw_codegen *p,       \
 181               struct brw_reg dest,              \
 182               struct brw_reg src0);
 183
 184 #define ALU2(OP)                                \
 185 brw_inst *brw_##OP(struct brw_codegen *p,       \
 186               struct brw_reg dest,              \
 187               struct brw_reg src0,              \
 188               struct brw_reg src1);
 189
 190 #define ALU3(OP)                                \
 191 brw_inst *brw_##OP(struct brw_codegen *p,       \
 192               struct brw_reg dest,              \
 193               struct brw_reg src0,              \
 194               struct brw_reg src1,              \
 195               struct brw_reg src2);
 196
 197 #define ROUND(OP) \
 198 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
 199
 200 ALU1(MOV)
 201 ALU2(SEL)
 202 ALU1(NOT)
 203 ALU2(AND)
 204 ALU2(OR)
 205 ALU2(XOR)
 206 ALU2(SHR)
 207 ALU2(SHL)
 208 ALU1(DIM)
 209 ALU2(ASR)
 210 ALU2(ROL)
 211 ALU2(ROR)
 212 ALU3(CSEL)
 213 ALU1(F32TO16)
 214 ALU1(F16TO32)
 215 ALU2(ADD)
 216 ALU2(AVG)
 217 ALU2(MUL)
 218 ALU1(FRC)
 219 ALU1(RNDD)
 220 ALU2(MAC)
 221 ALU2(MACH)
 222 ALU1(LZD)
 223 ALU2(DP4)
 224 ALU2(DPH)
 225 ALU2(DP3)
 226 ALU2(DP2)
 227 ALU2(LINE)
 228 ALU2(PLN)
 229 ALU3(MAD)
 230 ALU3(LRP)
 231 ALU1(BFREV)
 232 ALU3(BFE)
 233 ALU2(BFI1)
 234 ALU3(BFI2)
 235 ALU1(FBH)
 236 ALU1(FBL)
 237 ALU1(CBIT)
 238 ALU2(ADDC)
 239 ALU2(SUBB)
 240 ALU2(MAC)
 241
 242 ROUND(RNDZ)
 243 ROUND(RNDE)
 244
 245 #undef ALU1
 246 #undef ALU2
 247 #undef ALU3
 248 #undef ROUND
 249
 250
 251 /* Helpers for SEND instruction:
 252  */
 253
 254 /**
 255  * Construct a message descriptor immediate with the specified common
 256  * descriptor controls.
 257  */
 258 static inline uint32_t
 259 brw_message_desc(const struct gen_device_info *devinfo,
 260                  unsigned msg_length,
 261                  unsigned response_length,
 262                  bool header_present)
 263 {
 264    if (devinfo->gen >= 5) {
 265       return (SET_BITS(msg_length, 28, 25) |
 266               SET_BITS(response_length, 24, 20) |
 267               SET_BITS(header_present, 19, 19));
 268    } else {
 269       return (SET_BITS(msg_length, 23, 20) |
 270               SET_BITS(response_length, 19, 16));
 271    }
 272 }
 273
 274 static inline unsigned
 275 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
 276 {
 277    if (devinfo->gen >= 5)
 278       return GET_BITS(desc, 28, 25);
 279    else
 280       return GET_BITS(desc, 23, 20);
 281 }
 282
 283 static inline unsigned
 284 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
 285 {
 286    if (devinfo->gen >= 5)
 287       return GET_BITS(desc, 24, 20);
 288    else
 289       return GET_BITS(desc, 19, 16);
 290 }
 291
 292 static inline bool
 293 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
 294                                 uint32_t desc)
 295 {
 296    assert(devinfo->gen >= 5);
 297    return GET_BITS(desc, 19, 19);
 298 }
 299
 300 static inline unsigned
 301 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
 302                     unsigned ex_msg_length)
 303 {
 304    return SET_BITS(ex_msg_length, 9, 6);
 305 }
 306
 307 static inline unsigned
 308 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
 309                             uint32_t ex_desc)
 310 {
 311    return GET_BITS(ex_desc, 9, 6);
 312 }
 313
 314 /**
 315  * Construct a message descriptor immediate with the specified sampler
 316  * function controls.
 317  */
 318 static inline uint32_t
 319 brw_sampler_desc(const struct gen_device_info *devinfo,
 320                  unsigned binding_table_index,
 321                  unsigned sampler,
 322                  unsigned msg_type,
 323                  unsigned simd_mode,
 324                  unsigned return_format)
 325 {
 326    const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
 327                           SET_BITS(sampler, 11, 8));
 328    if (devinfo->gen >= 7)
 329       return (desc | SET_BITS(msg_type, 16, 12) |
 330               SET_BITS(simd_mode, 18, 17));
 331    else if (devinfo->gen >= 5)
 332       return (desc | SET_BITS(msg_type, 15, 12) |
 333               SET_BITS(simd_mode, 17, 16));
 334    else if (devinfo->is_g4x)
 335       return desc | SET_BITS(msg_type, 15, 12);
 336    else
 337       return (desc | SET_BITS(return_format, 13, 12) |
 338               SET_BITS(msg_type, 15, 14));
 339 }
 340
 341 static inline unsigned
 342 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 343                                      uint32_t desc)
 344 {
 345    return GET_BITS(desc, 7, 0);
 346 }
 347
 348 static inline unsigned
 349 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
 350 {
 351    return GET_BITS(desc, 11, 8);
 352 }
 353
 354 static inline unsigned
 355 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 356 {
 357    if (devinfo->gen >= 7)
 358       return GET_BITS(desc, 16, 12);
 359    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 360       return GET_BITS(desc, 15, 12);
 361    else
 362       return GET_BITS(desc, 15, 14);
 363 }
 364
 365 static inline unsigned
 366 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
 367 {
 368    assert(devinfo->gen >= 5);
 369    if (devinfo->gen >= 7)
 370       return GET_BITS(desc, 18, 17);
 371    else
 372       return GET_BITS(desc, 17, 16);
 373 }
 374
 375 static  inline unsigned
 376 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
 377                                uint32_t desc)
 378 {
 379    assert(devinfo->gen == 4 && !devinfo->is_g4x);
 380    return GET_BITS(desc, 13, 12);
 381 }
 382
 383 /**
 384  * Construct a message descriptor for the dataport
 385  */
 386 static inline uint32_t
 387 brw_dp_desc(const struct gen_device_info *devinfo,
 388             unsigned binding_table_index,
 389             unsigned msg_type,
 390             unsigned msg_control)
 391 {
 392    /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
 393     * helpers instead.
 394     */
 395    assert(devinfo->gen >= 6);
 396    const unsigned desc = SET_BITS(binding_table_index, 7, 0);
 397    if (devinfo->gen >= 8) {
 398       return (desc | SET_BITS(msg_control, 13, 8) |
 399               SET_BITS(msg_type, 18, 14));
 400    } else if (devinfo->gen >= 7) {
 401       return (desc | SET_BITS(msg_control, 13, 8) |
 402               SET_BITS(msg_type, 17, 14));
 403    } else {
 404       return (desc | SET_BITS(msg_control, 12, 8) |
 405               SET_BITS(msg_type, 16, 13));
 406    }
 407 }
 408
 409 static inline unsigned
 410 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 411                                 uint32_t desc)
 412 {
 413    return GET_BITS(desc, 7, 0);
 414 }
 415
 416 static inline unsigned
 417 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 418 {
 419    assert(devinfo->gen >= 6);
 420    if (devinfo->gen >= 8)
 421       return GET_BITS(desc, 18, 14);
 422    else if (devinfo->gen >= 7)
 423       return GET_BITS(desc, 17, 14);
 424    else
 425       return GET_BITS(desc, 16, 13);
 426 }
 427
 428 static inline unsigned
 429 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
 430 {
 431    assert(devinfo->gen >= 6);
 432    if (devinfo->gen >= 7)
 433       return GET_BITS(desc, 13, 8);
 434    else
 435       return GET_BITS(desc, 12, 8);
 436 }
 437
 438 /**
 439  * Construct a message descriptor immediate with the specified dataport read
 440  * function controls.
 441  */
 442 static inline uint32_t
 443 brw_dp_read_desc(const struct gen_device_info *devinfo,
 444                  unsigned binding_table_index,
 445                  unsigned msg_control,
 446                  unsigned msg_type,
 447                  unsigned target_cache)
 448 {
 449    if (devinfo->gen >= 6)
 450       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
 451    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 452       return (SET_BITS(binding_table_index, 7, 0) |
 453               SET_BITS(msg_control, 10, 8) |
 454               SET_BITS(msg_type, 13, 11) |
 455               SET_BITS(target_cache, 15, 14));
 456    else
 457       return (SET_BITS(binding_table_index, 7, 0) |
 458               SET_BITS(msg_control, 11, 8) |
 459               SET_BITS(msg_type, 13, 12) |
 460               SET_BITS(target_cache, 15, 14));
 461 }
 462
 463 static inline unsigned
 464 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 465 {
 466    if (devinfo->gen >= 6)
 467       return brw_dp_desc_msg_type(devinfo, desc);
 468    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 469       return GET_BITS(desc, 13, 11);
 470    else
 471       return GET_BITS(desc, 13, 12);
 472 }
 473
 474 static inline unsigned
 475 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
 476                              uint32_t desc)
 477 {
 478    if (devinfo->gen >= 6)
 479       return brw_dp_desc_msg_control(devinfo, desc);
 480    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 481       return GET_BITS(desc, 10, 8);
 482    else
 483       return GET_BITS(desc, 11, 8);
 484 }
 485
 486 /**
 487  * Construct a message descriptor immediate with the specified dataport write
 488  * function controls.
 489  */
 490 static inline uint32_t
 491 brw_dp_write_desc(const struct gen_device_info *devinfo,
 492                   unsigned binding_table_index,
 493                   unsigned msg_control,
 494                   unsigned msg_type,
 495                   unsigned last_render_target,
 496                   unsigned send_commit_msg)
 497 {
 498    assert(devinfo->gen <= 6 || !send_commit_msg);
 499    if (devinfo->gen >= 6)
 500       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
 501              SET_BITS(last_render_target, 12, 12) |
 502              SET_BITS(send_commit_msg, 17, 17);
 503    else
 504       return (SET_BITS(binding_table_index, 7, 0) |
 505               SET_BITS(msg_control, 11, 8) |
 506               SET_BITS(last_render_target, 11, 11) |
 507               SET_BITS(msg_type, 14, 12) |
 508               SET_BITS(send_commit_msg, 15, 15));
 509 }
 510
 511 static inline unsigned
 512 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
 513                            uint32_t desc)
 514 {
 515    if (devinfo->gen >= 6)
 516       return brw_dp_desc_msg_type(devinfo, desc);
 517    else
 518       return GET_BITS(desc, 14, 12);
 519 }
 520
 521 static inline unsigned
 522 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
 523                               uint32_t desc)
 524 {
 525    if (devinfo->gen >= 6)
 526       return brw_dp_desc_msg_control(devinfo, desc);
 527    else
 528       return GET_BITS(desc, 11, 8);
 529 }
 530
 531 static inline bool
 532 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
 533                                      uint32_t desc)
 534 {
 535    if (devinfo->gen >= 6)
 536       return GET_BITS(desc, 12, 12);
 537    else
 538       return GET_BITS(desc, 11, 11);
 539 }
 540
 541 static inline bool
 542 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
 543                                uint32_t desc)
 544 {
 545    assert(devinfo->gen <= 6);
 546    if (devinfo->gen >= 6)
 547       return GET_BITS(desc, 17, 17);
 548    else
 549       return GET_BITS(desc, 15, 15);
 550 }
 551
 552 /**
 553  * Construct a message descriptor immediate with the specified dataport
 554  * surface function controls.
 555  */
 556 static inline uint32_t
 557 brw_dp_surface_desc(const struct gen_device_info *devinfo,
 558                     unsigned msg_type,
 559                     unsigned msg_control)
 560 {
 561    assert(devinfo->gen >= 7);
 562    /* We'll OR in the binding table index later */
 563    return brw_dp_desc(devinfo, 0, msg_type, msg_control);
 564 }
 565
 566 static inline uint32_t
 567 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
 568                            unsigned exec_size, /**< 0 for SIMD4x2 */
 569                            unsigned atomic_op,
 570                            bool response_expected)
 571 {
 572    assert(exec_size <= 8 || exec_size == 16);
 573
 574    unsigned msg_type;
 575    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 576       if (exec_size > 0) {
 577          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
 578       } else {
 579          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
 580       }
 581    } else {
 582       msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
 583    }
 584
 585    const unsigned msg_control =
 586       SET_BITS(atomic_op, 3, 0) |
 587       SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
 588       SET_BITS(response_expected, 5, 5);
 589
 590    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 591 }
 592
 593 static inline uint32_t
 594 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 595                                  unsigned exec_size,
 596                                  unsigned atomic_op,
 597                                  bool response_expected)
 598 {
 599    assert(exec_size <= 8 || exec_size == 16);
 600    assert(devinfo->gen >= 9);
 601
 602    assert(exec_size > 0);
 603    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
 604
 605    const unsigned msg_control =
 606       SET_BITS(atomic_op, 1, 0) |
 607       SET_BITS(exec_size <= 8, 4, 4) |
 608       SET_BITS(response_expected, 5, 5);
 609
 610    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 611 }
 612
 613 static inline unsigned
 614 brw_mdc_cmask(unsigned num_channels)
 615 {
 616    /* See also MDC_CMASK in the SKL PRM Vol 2d. */
 617    return 0xf & (0xf << num_channels);
 618 }
 619
 620 static inline uint32_t
 621 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 622                                unsigned exec_size, /**< 0 for SIMD4x2 */
 623                                unsigned num_channels,
 624                                bool write)
 625 {
 626    assert(exec_size <= 8 || exec_size == 16);
 627
 628    unsigned msg_type;
 629    if (write) {
 630       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 631          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
 632       } else {
 633          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
 634       }
 635    } else {
 636       /* Read */
 637       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 638          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
 639       } else {
 640          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
 641       }
 642    }
 643
 644    /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
 645    if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
 646       exec_size = 8;
 647
 648    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 649    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 650                               exec_size <= 8 ? 2 : 1;
 651
 652    const unsigned msg_control =
 653       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 654       SET_BITS(simd_mode, 5, 4);
 655
 656    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 657 }
 658
 659 static inline unsigned
 660 brw_mdc_ds(unsigned bit_size)
 661 {
 662    switch (bit_size) {
 663    case 8:
 664       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
 665    case 16:
 666       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
 667    case 32:
 668       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
 669    default:
 670       unreachable("Unsupported bit_size for byte scattered messages");
 671    }
 672 }
 673
 674 static inline uint32_t
 675 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 676                               unsigned exec_size,
 677                               unsigned bit_size,
 678                               bool write)
 679 {
 680    assert(exec_size <= 8 || exec_size == 16);
 681
 682    assert(devinfo->gen > 7 || devinfo->is_haswell);
 683    const unsigned msg_type =
 684       write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
 685               HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
 686
 687    assert(exec_size > 0);
 688    const unsigned msg_control =
 689       SET_BITS(exec_size == 16, 0, 0) |
 690       SET_BITS(brw_mdc_ds(bit_size), 3, 2);
 691
 692    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 693 }
 694
 695 static inline uint32_t
 696 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 697                                    unsigned exec_size, /**< 0 for SIMD4x2 */
 698                                    unsigned num_channels,
 699                                    bool write)
 700 {
 701    assert(exec_size <= 8 || exec_size == 16);
 702    assert(devinfo->gen >= 8);
 703
 704    unsigned msg_type =
 705       write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
 706               GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
 707
 708    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 709    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 710                               exec_size <= 8 ? 2 : 1;
 711
 712    const unsigned msg_control =
 713       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 714       SET_BITS(simd_mode, 5, 4);
 715
 716    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 717 }
 718
 719 /**
 720  * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
 721  * Skylake PRM).
 722  */
 723 static inline uint32_t
 724 brw_mdc_a64_ds(unsigned elems)
 725 {
 726    switch (elems) {
 727    case 1:  return 0;
 728    case 2:  return 1;
 729    case 4:  return 2;
 730    case 8:  return 3;
 731    default:
 732       unreachable("Unsupported elmeent count for A64 scattered message");
 733    }
 734 }
 735
 736 static inline uint32_t
 737 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 738                                   unsigned exec_size, /**< 0 for SIMD4x2 */
 739                                   unsigned bit_size,
 740                                   bool write)
 741 {
 742    assert(exec_size <= 8 || exec_size == 16);
 743    assert(devinfo->gen >= 8);
 744
 745    unsigned msg_type =
 746       write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
 747               GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
 748
 749    const unsigned msg_control =
 750       SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
 751       SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
 752       SET_BITS(exec_size == 16, 4, 4);
 753
 754    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 755 }
 756
 757 static inline uint32_t
 758 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
 759                                ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
 760                                unsigned bit_size,
 761                                unsigned atomic_op,
 762                                bool response_expected)
 763 {
 764    assert(exec_size == 8);
 765    assert(devinfo->gen >= 8);
 766    assert(bit_size == 32 || bit_size == 64);
 767
 768    const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
 769
 770    const unsigned msg_control =
 771       SET_BITS(atomic_op, 3, 0) |
 772       SET_BITS(bit_size == 64, 4, 4) |
 773       SET_BITS(response_expected, 5, 5);
 774
 775    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 776 }
 777
 778 static inline uint32_t
 779 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 780                                      ASSERTED unsigned exec_size,
 781                                      unsigned atomic_op,
 782                                      bool response_expected)
 783 {
 784    assert(exec_size == 8);
 785    assert(devinfo->gen >= 9);
 786
 787    assert(exec_size > 0);
 788    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
 789
 790    const unsigned msg_control =
 791       SET_BITS(atomic_op, 1, 0) |
 792       SET_BITS(response_expected, 5, 5);
 793
 794    return brw_dp_desc(devinfo, BRW_BTI_STATELESS, msg_type, msg_control);
 795 }
 796
 797 static inline uint32_t
 798 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
 799                          unsigned exec_size,
 800                          unsigned exec_group,
 801                          unsigned atomic_op,
 802                          bool response_expected)
 803 {
 804    assert(exec_size > 0 || exec_group == 0);
 805    assert(exec_group % 8 == 0);
 806
 807    unsigned msg_type;
 808    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 809       if (exec_size == 0) {
 810          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
 811       } else {
 812          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
 813       }
 814    } else {
 815       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 816       assert(exec_size > 0);
 817       msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
 818    }
 819
 820    const bool high_sample_mask = (exec_group / 8) % 2 == 1;
 821
 822    const unsigned msg_control =
 823       SET_BITS(atomic_op, 3, 0) |
 824       SET_BITS(high_sample_mask, 4, 4) |
 825       SET_BITS(response_expected, 5, 5);
 826
 827    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 828 }
 829
 830 static inline uint32_t
 831 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
 832                              unsigned exec_size,
 833                              unsigned exec_group,
 834                              unsigned num_channels,
 835                              bool write)
 836 {
 837    assert(exec_size > 0 || exec_group == 0);
 838    assert(exec_group % 8 == 0);
 839
 840    /* Typed surface reads and writes don't support SIMD16 */
 841    assert(exec_size <= 8);
 842
 843    unsigned msg_type;
 844    if (write) {
 845       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 846          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
 847       } else {
 848          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
 849       }
 850    } else {
 851       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 852          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
 853       } else {
 854          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
 855       }
 856    }
 857
 858    /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 859    unsigned msg_control;
 860    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 861       /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 862       const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
 863                                   1 + ((exec_group / 8) % 2);
 864
 865       msg_control =
 866          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 867          SET_BITS(slot_group, 5, 4);
 868    } else {
 869       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 870       assert(exec_size > 0);
 871       const unsigned slot_group = ((exec_group / 8) % 2);
 872
 873       msg_control =
 874          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 875          SET_BITS(slot_group, 5, 5);
 876    }
 877
 878    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 879 }
 880
 881 /**
 882  * Construct a message descriptor immediate with the specified pixel
 883  * interpolator function controls.
 884  */
 885 static inline uint32_t
 886 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
 887                       unsigned msg_type,
 888                       bool noperspective,
 889                       unsigned simd_mode,
 890                       unsigned slot_group)
 891 {
 892    return (SET_BITS(slot_group, 11, 11) |
 893            SET_BITS(msg_type, 13, 12) |
 894            SET_BITS(!!noperspective, 14, 14) |
 895            SET_BITS(simd_mode, 16, 16));
 896 }
 897
 898 void brw_urb_WRITE(struct brw_codegen *p,
 899                    struct brw_reg dest,
 900                    unsigned msg_reg_nr,
 901                    struct brw_reg src0,
 902                    enum brw_urb_write_flags flags,
 903                    unsigned msg_length,
 904                    unsigned response_length,
 905                    unsigned offset,
 906                    unsigned swizzle);
 907
 908 /**
 909  * Send message to shared unit \p sfid with a possibly indirect descriptor \p
 910  * desc.  If \p desc is not an immediate it will be transparently loaded to an
 911  * address register using an OR instruction.
 912  */
 913 void
 914 brw_send_indirect_message(struct brw_codegen *p,
 915                           unsigned sfid,
 916                           struct brw_reg dst,
 917                           struct brw_reg payload,
 918                           struct brw_reg desc,
 919                           unsigned desc_imm,
 920                           bool eot);
 921
 922 void
 923 brw_send_indirect_split_message(struct brw_codegen *p,
 924                                 unsigned sfid,
 925                                 struct brw_reg dst,
 926                                 struct brw_reg payload0,
 927                                 struct brw_reg payload1,
 928                                 struct brw_reg desc,
 929                                 unsigned desc_imm,
 930                                 struct brw_reg ex_desc,
 931                                 unsigned ex_desc_imm,
 932                                 bool eot);
 933
 934 void brw_ff_sync(struct brw_codegen *p,
 935                    struct brw_reg dest,
 936                    unsigned msg_reg_nr,
 937                    struct brw_reg src0,
 938                    bool allocate,
 939                    unsigned response_length,
 940                    bool eot);
 941
 942 void brw_svb_write(struct brw_codegen *p,
 943                    struct brw_reg dest,
 944                    unsigned msg_reg_nr,
 945                    struct brw_reg src0,
 946                    unsigned binding_table_index,
 947                    bool   send_commit_msg);
 948
 949 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
 950                        struct brw_reg payload,
 951                        struct brw_reg implied_header,
 952                        unsigned msg_control,
 953                        unsigned binding_table_index,
 954                        unsigned msg_length,
 955                        unsigned response_length,
 956                        bool eot,
 957                        bool last_render_target,
 958                        bool header_present);
 959
 960 brw_inst *gen9_fb_READ(struct brw_codegen *p,
 961                        struct brw_reg dst,
 962                        struct brw_reg payload,
 963                        unsigned binding_table_index,
 964                        unsigned msg_length,
 965                        unsigned response_length,
 966                        bool per_sample);
 967
 968 void brw_SAMPLE(struct brw_codegen *p,
 969                 struct brw_reg dest,
 970                 unsigned msg_reg_nr,
 971                 struct brw_reg src0,
 972                 unsigned binding_table_index,
 973                 unsigned sampler,
 974                 unsigned msg_type,
 975                 unsigned response_length,
 976                 unsigned msg_length,
 977                 unsigned header_present,
 978                 unsigned simd_mode,
 979                 unsigned return_format);
 980
 981 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
 982                                       struct brw_reg header,
 983                                       struct brw_reg sampler_index);
 984
 985 void gen4_math(struct brw_codegen *p,
 986                struct brw_reg dest,
 987                unsigned function,
 988                unsigned msg_reg_nr,
 989                struct brw_reg src,
 990                unsigned precision );
 991
 992 void gen6_math(struct brw_codegen *p,
 993                struct brw_reg dest,
 994                unsigned function,
 995                struct brw_reg src0,
 996                struct brw_reg src1);
 997
 998 void brw_oword_block_read(struct brw_codegen *p,
 999                           struct brw_reg dest,
1000                           struct brw_reg mrf,
1001                           uint32_t offset,
1002                           uint32_t bind_table_index);
1003
1004 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1005
1006 void brw_oword_block_read_scratch(struct brw_codegen *p,
1007                                   struct brw_reg dest,
1008                                   struct brw_reg mrf,
1009                                   int num_regs,
1010                                   unsigned offset);
1011
1012 void brw_oword_block_write_scratch(struct brw_codegen *p,
1013                                    struct brw_reg mrf,
1014                                    int num_regs,
1015                                    unsigned offset);
1016
1017 void gen7_block_read_scratch(struct brw_codegen *p,
1018                              struct brw_reg dest,
1019                              int num_regs,
1020                              unsigned offset);
1021
1022 void brw_shader_time_add(struct brw_codegen *p,
1023                          struct brw_reg payload,
1024                          uint32_t surf_index);
1025
1026 /**
1027  * Return the generation-specific jump distance scaling factor.
1028  *
1029  * Given the number of instructions to jump, we need to scale by
1030  * some number to obtain the actual jump distance to program in an
1031  * instruction.
1032  */
1033 static inline unsigned
1034 brw_jump_scale(const struct gen_device_info *devinfo)
1035 {
1036    /* Broadwell measures jump targets in bytes. */
1037    if (devinfo->gen >= 8)
1038       return 16;
1039
1040    /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1041     * (to support compaction), so each 128-bit instruction requires 2 chunks.
1042     */
1043    if (devinfo->gen >= 5)
1044       return 2;
1045
1046    /* Gen4 simply uses the number of 128-bit instructions. */
1047    return 1;
1048 }
1049
1050 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1051
1052 /* If/else/endif.  Works by manipulating the execution flags on each
1053  * channel.
1054  */
1055 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1056 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1057                   struct brw_reg src0, struct brw_reg src1);
1058
1059 void brw_ELSE(struct brw_codegen *p);
1060 void brw_ENDIF(struct brw_codegen *p);
1061
1062 /* DO/WHILE loops:
1063  */
1064 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1065
1066 brw_inst *brw_WHILE(struct brw_codegen *p);
1067
1068 brw_inst *brw_BREAK(struct brw_codegen *p);
1069 brw_inst *brw_CONT(struct brw_codegen *p);
1070 brw_inst *gen6_HALT(struct brw_codegen *p);
1071
1072 /* Forward jumps:
1073  */
1074 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1075
1076 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1077                    unsigned predicate_control);
1078
1079 void brw_NOP(struct brw_codegen *p);
1080
1081 void brw_WAIT(struct brw_codegen *p);
1082
1083 /* Special case: there is never a destination, execution size will be
1084  * taken from src0:
1085  */
1086 void brw_CMP(struct brw_codegen *p,
1087              struct brw_reg dest,
1088              unsigned conditional,
1089              struct brw_reg src0,
1090              struct brw_reg src1);
1091
1092 void
1093 brw_untyped_atomic(struct brw_codegen *p,
1094                    struct brw_reg dst,
1095                    struct brw_reg payload,
1096                    struct brw_reg surface,
1097                    unsigned atomic_op,
1098                    unsigned msg_length,
1099                    bool response_expected,
1100                    bool header_present);
1101
1102 void
1103 brw_untyped_surface_read(struct brw_codegen *p,
1104                          struct brw_reg dst,
1105                          struct brw_reg payload,
1106                          struct brw_reg surface,
1107                          unsigned msg_length,
1108                          unsigned num_channels);
1109
1110 void
1111 brw_untyped_surface_write(struct brw_codegen *p,
1112                           struct brw_reg payload,
1113                           struct brw_reg surface,
1114                           unsigned msg_length,
1115                           unsigned num_channels,
1116                           bool header_present);
1117
1118 void
1119 brw_memory_fence(struct brw_codegen *p,
1120                  struct brw_reg dst,
1121                  struct brw_reg src,
1122                  enum opcode send_op,
1123                  bool stall,
1124                  unsigned bti);
1125
1126 void
1127 brw_pixel_interpolator_query(struct brw_codegen *p,
1128                              struct brw_reg dest,
1129                              struct brw_reg mrf,
1130                              bool noperspective,
1131                              unsigned mode,
1132                              struct brw_reg data,
1133                              unsigned msg_length,
1134                              unsigned response_length);
1135
1136 void
1137 brw_find_live_channel(struct brw_codegen *p,
1138                       struct brw_reg dst,
1139                       struct brw_reg mask);
1140
1141 void
1142 brw_broadcast(struct brw_codegen *p,
1143               struct brw_reg dst,
1144               struct brw_reg src,
1145               struct brw_reg idx);
1146
1147 void
1148 brw_float_controls_mode(struct brw_codegen *p,
1149                         unsigned mode, unsigned mask);
1150
1151 /***********************************************************************
1152  * brw_eu_util.c:
1153  */
1154
1155 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1156                                    struct brw_indirect dst_ptr,
1157                                    struct brw_indirect src_ptr,
1158                                    unsigned count);
1159
1160 void brw_copy_from_indirect(struct brw_codegen *p,
1161                             struct brw_reg dst,
1162                             struct brw_indirect ptr,
1163                             unsigned count);
1164
1165 void brw_copy4(struct brw_codegen *p,
1166                struct brw_reg dst,
1167                struct brw_reg src,
1168                unsigned count);
1169
1170 void brw_copy8(struct brw_codegen *p,
1171                struct brw_reg dst,
1172                struct brw_reg src,
1173                unsigned count);
1174
1175 void brw_math_invert( struct brw_codegen *p,
1176                       struct brw_reg dst,
1177                       struct brw_reg src);
1178
1179 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1180
1181 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1182                      unsigned desc, unsigned ex_desc);
1183
1184 static inline void
1185 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1186 {
1187    brw_set_desc_ex(p, insn, desc, 0);
1188 }
1189
1190 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1191
1192 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1193 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1194
1195 /* brw_eu_compact.c */
1196 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
1197 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1198                               struct disasm_info *disasm);
1199 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1200                                brw_inst *dst, brw_compact_inst *src);
1201 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1202                                  brw_compact_inst *dst, const brw_inst *src);
1203
1204 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1205                                  brw_inst *orig, brw_inst *uncompacted);
1206
1207 /* brw_eu_validate.c */
1208 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1209                                const void *assembly, int start_offset, int end_offset,
1210                                struct disasm_info *disasm);
1211
1212 static inline int
1213 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1214 {
1215    brw_inst *insn = (brw_inst *)((char *)store + offset);
1216
1217    if (brw_inst_cmpt_control(devinfo, insn))
1218       return offset + 8;
1219    else
1220       return offset + 16;
1221 }
1222
1223 struct opcode_desc {
1224    unsigned ir;
1225    unsigned hw;
1226    const char *name;
1227    int nsrc;
1228    int ndst;
1229    int gens;
1230 };
1231
1232 const struct opcode_desc *
1233 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1234
1235 const struct opcode_desc *
1236 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1237
1238 static inline unsigned
1239 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1240 {
1241    return brw_opcode_desc(devinfo, opcode)->hw;
1242 }
1243
1244 static inline enum opcode
1245 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1246 {
1247    const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1248    return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1249 }
1250
1251 static inline void
1252 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1253                     brw_inst *inst, enum opcode opcode)
1254 {
1255    brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1256 }
1257
1258 static inline enum opcode
1259 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1260 {
1261    return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1262 }
1263
1264 static inline bool
1265 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1266 {
1267    const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1268    return desc && desc->nsrc == 3;
1269 }
1270
1271 /** Maximum SEND message length */
1272 #define BRW_MAX_MSG_LENGTH 15
1273
1274 /** First MRF register used by pull loads */
1275 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1276
1277 /** First MRF register used by spills */
1278 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1279
1280 #ifdef __cplusplus
1281 }
1282 #endif
1283
1284 #endif