2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
38 #include "brw_eu_defines.h"
40 #include "intel_asm_annotation.h"
46 #define BRW_EU_MAX_INSN_STACK 5
48 /* A helper for accessing the last instruction emitted. This makes it easy
49 * to set various bits on an instruction without having to create temporary
50 * variable and assign the emitted instruction to those.
52 #define brw_last_inst (&p->store[p->nr_insn - 1])
58 unsigned int next_insn_offset
;
62 /* Allow clients to push/pop instruction state:
64 brw_inst stack
[BRW_EU_MAX_INSN_STACK
];
65 bool compressed_stack
[BRW_EU_MAX_INSN_STACK
];
68 /** Whether or not the user wants automatic exec sizes
70 * If true, codegen will try to automatically infer the exec size of an
71 * instruction from the width of the destination register. If false, it
72 * will take whatever is set by brw_set_default_exec_size verbatim.
74 * This is set to true by default in brw_init_codegen.
76 bool automatic_exec_sizes
;
78 bool single_program_flow
;
79 const struct gen_device_info
*devinfo
;
81 /* Control flow stacks:
82 * - if_stack contains IF and ELSE instructions which must be patched
83 * (and popped) once the matching ENDIF instruction is encountered.
85 * Just store the instruction pointer(an index).
89 int if_stack_array_size
;
92 * loop_stack contains the instruction pointers of the starts of loops which
93 * must be patched (and popped) once the matching WHILE instruction is
98 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
99 * blocks they were popping out of, to fix up the mask stack. This tracks
100 * the IF/ENDIF nesting in each current nested loop level.
102 int *if_depth_in_loop
;
103 int loop_stack_depth
;
104 int loop_stack_array_size
;
107 void brw_pop_insn_state( struct brw_codegen
*p
);
108 void brw_push_insn_state( struct brw_codegen
*p
);
109 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
110 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
111 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
112 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
113 void brw_inst_set_compression(const struct gen_device_info
*devinfo
,
114 brw_inst
*inst
, bool on
);
115 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
116 void brw_inst_set_group(const struct gen_device_info
*devinfo
,
117 brw_inst
*inst
, unsigned group
);
118 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
119 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
120 void brw_set_default_predicate_control( struct brw_codegen
*p
, unsigned pc
);
121 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
122 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
123 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
125 void brw_init_codegen(const struct gen_device_info
*, struct brw_codegen
*p
,
127 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
128 const struct brw_inst
*inst
, bool is_compacted
);
129 void brw_disassemble(const struct gen_device_info
*devinfo
,
130 const void *assembly
, int start
, int end
, FILE *out
);
131 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
133 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
134 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
135 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
137 void gen6_resolve_implied_move(struct brw_codegen
*p
,
139 unsigned msg_reg_nr
);
141 /* Helpers for regular instructions:
144 brw_inst *brw_##OP(struct brw_codegen *p, \
145 struct brw_reg dest, \
146 struct brw_reg src0);
149 brw_inst *brw_##OP(struct brw_codegen *p, \
150 struct brw_reg dest, \
151 struct brw_reg src0, \
152 struct brw_reg src1);
155 brw_inst *brw_##OP(struct brw_codegen *p, \
156 struct brw_reg dest, \
157 struct brw_reg src0, \
158 struct brw_reg src1, \
159 struct brw_reg src2);
162 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
212 /* Helpers for SEND instruction:
214 void brw_set_sampler_message(struct brw_codegen
*p
,
216 unsigned binding_table_index
,
219 unsigned response_length
,
221 unsigned header_present
,
223 unsigned return_format
);
225 void brw_set_message_descriptor(struct brw_codegen
*p
,
227 enum brw_message_target sfid
,
229 unsigned response_length
,
233 void brw_set_dp_read_message(struct brw_codegen
*p
,
235 unsigned binding_table_index
,
236 unsigned msg_control
,
238 unsigned target_cache
,
241 unsigned response_length
);
243 void brw_set_dp_write_message(struct brw_codegen
*p
,
245 unsigned binding_table_index
,
246 unsigned msg_control
,
248 unsigned target_cache
,
251 unsigned last_render_target
,
252 unsigned response_length
,
253 unsigned end_of_thread
,
254 unsigned send_commit_msg
);
256 void brw_urb_WRITE(struct brw_codegen
*p
,
260 enum brw_urb_write_flags flags
,
262 unsigned response_length
,
267 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
268 * desc. If \p desc is not an immediate it will be transparently loaded to an
269 * address register using an OR instruction. The returned instruction can be
270 * passed as argument to the usual brw_set_*_message() functions in order to
271 * specify any additional descriptor bits -- If \p desc is an immediate this
272 * will be the SEND instruction itself, otherwise it will be the OR
276 brw_send_indirect_message(struct brw_codegen
*p
,
279 struct brw_reg payload
,
280 struct brw_reg desc
);
282 void brw_ff_sync(struct brw_codegen
*p
,
287 unsigned response_length
,
290 void brw_svb_write(struct brw_codegen
*p
,
294 unsigned binding_table_index
,
295 bool send_commit_msg
);
297 void brw_fb_WRITE(struct brw_codegen
*p
,
298 struct brw_reg payload
,
299 struct brw_reg implied_header
,
300 unsigned msg_control
,
301 unsigned binding_table_index
,
303 unsigned response_length
,
305 bool last_render_target
,
306 bool header_present
);
308 brw_inst
*gen9_fb_READ(struct brw_codegen
*p
,
310 struct brw_reg payload
,
311 unsigned binding_table_index
,
313 unsigned response_length
,
316 void brw_SAMPLE(struct brw_codegen
*p
,
320 unsigned binding_table_index
,
323 unsigned response_length
,
325 unsigned header_present
,
327 unsigned return_format
);
329 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
330 struct brw_reg header
,
331 struct brw_reg sampler_index
);
333 void gen4_math(struct brw_codegen
*p
,
338 unsigned precision
);
340 void gen6_math(struct brw_codegen
*p
,
344 struct brw_reg src1
);
346 void brw_oword_block_read(struct brw_codegen
*p
,
350 uint32_t bind_table_index
);
352 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
354 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
360 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
365 void gen7_block_read_scratch(struct brw_codegen
*p
,
370 void brw_shader_time_add(struct brw_codegen
*p
,
371 struct brw_reg payload
,
372 uint32_t surf_index
);
375 * Return the generation-specific jump distance scaling factor.
377 * Given the number of instructions to jump, we need to scale by
378 * some number to obtain the actual jump distance to program in an
381 static inline unsigned
382 brw_jump_scale(const struct gen_device_info
*devinfo
)
384 /* Broadwell measures jump targets in bytes. */
385 if (devinfo
->gen
>= 8)
388 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
389 * (to support compaction), so each 128-bit instruction requires 2 chunks.
391 if (devinfo
->gen
>= 5)
394 /* Gen4 simply uses the number of 128-bit instructions. */
398 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
400 /* If/else/endif. Works by manipulating the execution flags on each
403 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
404 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
405 struct brw_reg src0
, struct brw_reg src1
);
407 void brw_ELSE(struct brw_codegen
*p
);
408 void brw_ENDIF(struct brw_codegen
*p
);
412 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
414 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
416 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
417 brw_inst
*brw_CONT(struct brw_codegen
*p
);
418 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
422 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
424 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
425 unsigned predicate_control
);
427 void brw_NOP(struct brw_codegen
*p
);
429 void brw_WAIT(struct brw_codegen
*p
);
431 /* Special case: there is never a destination, execution size will be
434 void brw_CMP(struct brw_codegen
*p
,
436 unsigned conditional
,
438 struct brw_reg src1
);
441 brw_untyped_atomic(struct brw_codegen
*p
,
443 struct brw_reg payload
,
444 struct brw_reg surface
,
447 bool response_expected
);
450 brw_untyped_surface_read(struct brw_codegen
*p
,
452 struct brw_reg payload
,
453 struct brw_reg surface
,
455 unsigned num_channels
);
458 brw_untyped_surface_write(struct brw_codegen
*p
,
459 struct brw_reg payload
,
460 struct brw_reg surface
,
462 unsigned num_channels
);
465 brw_typed_atomic(struct brw_codegen
*p
,
467 struct brw_reg payload
,
468 struct brw_reg surface
,
471 bool response_expected
);
474 brw_typed_surface_read(struct brw_codegen
*p
,
476 struct brw_reg payload
,
477 struct brw_reg surface
,
479 unsigned num_channels
);
482 brw_typed_surface_write(struct brw_codegen
*p
,
483 struct brw_reg payload
,
484 struct brw_reg surface
,
486 unsigned num_channels
);
489 brw_memory_fence(struct brw_codegen
*p
,
493 brw_pixel_interpolator_query(struct brw_codegen
*p
,
500 unsigned response_length
);
503 brw_find_live_channel(struct brw_codegen
*p
,
505 struct brw_reg mask
);
508 brw_broadcast(struct brw_codegen
*p
,
513 /***********************************************************************
517 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
518 struct brw_indirect dst_ptr
,
519 struct brw_indirect src_ptr
,
522 void brw_copy_from_indirect(struct brw_codegen
*p
,
524 struct brw_indirect ptr
,
527 void brw_copy4(struct brw_codegen
*p
,
532 void brw_copy8(struct brw_codegen
*p
,
537 void brw_math_invert( struct brw_codegen
*p
,
541 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
543 void brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
);
545 enum brw_conditional_mod
brw_negate_cmod(uint32_t cmod
);
546 enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod
);
548 /* brw_eu_compact.c */
549 void brw_init_compaction_tables(const struct gen_device_info
*devinfo
);
550 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
551 int num_annotations
, struct annotation
*annotation
);
552 void brw_uncompact_instruction(const struct gen_device_info
*devinfo
,
553 brw_inst
*dst
, brw_compact_inst
*src
);
554 bool brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
555 brw_compact_inst
*dst
, const brw_inst
*src
);
557 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
558 brw_inst
*orig
, brw_inst
*uncompacted
);
560 /* brw_eu_validate.c */
561 bool brw_validate_instructions(const struct gen_device_info
*devinfo
,
562 const void *assembly
, int start_offset
, int end_offset
,
563 struct annotation_info
*annotation
);
566 next_offset(const struct gen_device_info
*devinfo
, void *store
, int offset
)
568 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
570 if (brw_inst_cmpt_control(devinfo
, insn
))
577 /* The union is an implementation detail used by brw_opcode_desc() to handle
578 * opcodes that have been reused for different instructions across hardware
581 * The gens field acts as a tag. If it is non-zero, name points to a string
582 * containing the instruction mnemonic. If it is zero, the table field is
583 * valid and either points to a secondary opcode_desc table with 'size'
584 * elements or is NULL and no such instruction exists for the opcode.
592 const struct opcode_desc
*table
;
600 const struct opcode_desc
*
601 brw_opcode_desc(const struct gen_device_info
*devinfo
, enum opcode opcode
);
604 is_3src(const struct gen_device_info
*devinfo
, enum opcode opcode
)
606 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
607 return desc
&& desc
->nsrc
== 3;
610 /** Maximum SEND message length */
611 #define BRW_MAX_MSG_LENGTH 15
613 /** First MRF register used by pull loads */
614 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
616 /** First MRF register used by spills */
617 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)