src/intel/compiler/brw_eu.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32
  33 #ifndef BRW_EU_H
  34 #define BRW_EU_H
  35
  36 #include <stdbool.h>
  37 #include <stdio.h>
  38 #include "brw_inst.h"
  39 #include "brw_eu_defines.h"
  40 #include "brw_reg.h"
  41 #include "brw_disasm_info.h"
  42
  43 #ifdef __cplusplus
  44 extern "C" {
  45 #endif
  46
  47 #define BRW_EU_MAX_INSN_STACK 5
  48
  49 struct brw_insn_state {
  50    /* One of BRW_EXECUTE_* */
  51    unsigned exec_size:3;
  52
  53    /* Group in units of channels */
  54    unsigned group:5;
  55
  56    /* Compression control on gen4-5 */
  57    bool compressed:1;
  58
  59    /* One of BRW_MASK_* */
  60    unsigned mask_control:1;
  61
  62    /* Scheduling info for Gen12+ */
  63    struct tgl_swsb swsb;
  64
  65    bool saturate:1;
  66
  67    /* One of BRW_ALIGN_* */
  68    unsigned access_mode:1;
  69
  70    /* One of BRW_PREDICATE_* */
  71    enum brw_predicate predicate:4;
  72
  73    bool pred_inv:1;
  74
  75    /* Flag subreg.  Bottom bit is subreg, top bit is reg */
  76    unsigned flag_subreg:2;
  77
  78    bool acc_wr_control:1;
  79 };
  80
  81
  82 /* A helper for accessing the last instruction emitted.  This makes it easy
  83  * to set various bits on an instruction without having to create temporary
  84  * variable and assign the emitted instruction to those.
  85  */
  86 #define brw_last_inst (&p->store[p->nr_insn - 1])
  87
  88 struct brw_codegen {
  89    brw_inst *store;
  90    int store_size;
  91    unsigned nr_insn;
  92    unsigned int next_insn_offset;
  93
  94    void *mem_ctx;
  95
  96    /* Allow clients to push/pop instruction state:
  97     */
  98    struct brw_insn_state stack[BRW_EU_MAX_INSN_STACK];
  99    struct brw_insn_state *current;
 100
 101    /** Whether or not the user wants automatic exec sizes
 102     *
 103     * If true, codegen will try to automatically infer the exec size of an
 104     * instruction from the width of the destination register.  If false, it
 105     * will take whatever is set by brw_set_default_exec_size verbatim.
 106     *
 107     * This is set to true by default in brw_init_codegen.
 108     */
 109    bool automatic_exec_sizes;
 110
 111    bool single_program_flow;
 112    const struct gen_device_info *devinfo;
 113
 114    /* Control flow stacks:
 115     * - if_stack contains IF and ELSE instructions which must be patched
 116     *   (and popped) once the matching ENDIF instruction is encountered.
 117     *
 118     *   Just store the instruction pointer(an index).
 119     */
 120    int *if_stack;
 121    int if_stack_depth;
 122    int if_stack_array_size;
 123
 124    /**
 125     * loop_stack contains the instruction pointers of the starts of loops which
 126     * must be patched (and popped) once the matching WHILE instruction is
 127     * encountered.
 128     */
 129    int *loop_stack;
 130    /**
 131     * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
 132     * blocks they were popping out of, to fix up the mask stack.  This tracks
 133     * the IF/ENDIF nesting in each current nested loop level.
 134     */
 135    int *if_depth_in_loop;
 136    int loop_stack_depth;
 137    int loop_stack_array_size;
 138 };
 139
 140 void brw_pop_insn_state( struct brw_codegen *p );
 141 void brw_push_insn_state( struct brw_codegen *p );
 142 unsigned brw_get_default_exec_size(struct brw_codegen *p);
 143 unsigned brw_get_default_group(struct brw_codegen *p);
 144 unsigned brw_get_default_access_mode(struct brw_codegen *p);
 145 struct tgl_swsb brw_get_default_swsb(struct brw_codegen *p);
 146 void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
 147 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
 148 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
 149 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
 150 void brw_inst_set_compression(const struct gen_device_info *devinfo,
 151                               brw_inst *inst, bool on);
 152 void brw_set_default_compression(struct brw_codegen *p, bool on);
 153 void brw_inst_set_group(const struct gen_device_info *devinfo,
 154                         brw_inst *inst, unsigned group);
 155 void brw_set_default_group(struct brw_codegen *p, unsigned group);
 156 void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
 157 void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
 158 void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse);
 159 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
 160 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
 161 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
 162
 163 void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
 164                       void *mem_ctx);
 165 int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
 166                          const struct brw_inst *inst, bool is_compacted);
 167 void brw_disassemble(const struct gen_device_info *devinfo,
 168                      const void *assembly, int start, int end, FILE *out);
 169 const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
 170
 171 bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
 172                                const char *identifier);
 173
 174 brw_inst *brw_next_insn(struct brw_codegen *p, unsigned opcode);
 175 void brw_set_dest(struct brw_codegen *p, brw_inst *insn, struct brw_reg dest);
 176 void brw_set_src0(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
 177
 178 void gen6_resolve_implied_move(struct brw_codegen *p,
 179                                struct brw_reg *src,
 180                                unsigned msg_reg_nr);
 181
 182 /* Helpers for regular instructions:
 183  */
 184 #define ALU1(OP)                                \
 185 brw_inst *brw_##OP(struct brw_codegen *p,       \
 186               struct brw_reg dest,              \
 187               struct brw_reg src0);
 188
 189 #define ALU2(OP)                                \
 190 brw_inst *brw_##OP(struct brw_codegen *p,       \
 191               struct brw_reg dest,              \
 192               struct brw_reg src0,              \
 193               struct brw_reg src1);
 194
 195 #define ALU3(OP)                                \
 196 brw_inst *brw_##OP(struct brw_codegen *p,       \
 197               struct brw_reg dest,              \
 198               struct brw_reg src0,              \
 199               struct brw_reg src1,              \
 200               struct brw_reg src2);
 201
 202 ALU1(MOV)
 203 ALU2(SEL)
 204 ALU1(NOT)
 205 ALU2(AND)
 206 ALU2(OR)
 207 ALU2(XOR)
 208 ALU2(SHR)
 209 ALU2(SHL)
 210 ALU1(DIM)
 211 ALU2(ASR)
 212 ALU2(ROL)
 213 ALU2(ROR)
 214 ALU3(CSEL)
 215 ALU1(F32TO16)
 216 ALU1(F16TO32)
 217 ALU2(ADD)
 218 ALU2(AVG)
 219 ALU2(MUL)
 220 ALU1(FRC)
 221 ALU1(RNDD)
 222 ALU1(RNDE)
 223 ALU1(RNDZ)
 224 ALU2(MAC)
 225 ALU2(MACH)
 226 ALU1(LZD)
 227 ALU2(DP4)
 228 ALU2(DPH)
 229 ALU2(DP3)
 230 ALU2(DP2)
 231 ALU2(LINE)
 232 ALU2(PLN)
 233 ALU3(MAD)
 234 ALU3(LRP)
 235 ALU1(BFREV)
 236 ALU3(BFE)
 237 ALU2(BFI1)
 238 ALU3(BFI2)
 239 ALU1(FBH)
 240 ALU1(FBL)
 241 ALU1(CBIT)
 242 ALU2(ADDC)
 243 ALU2(SUBB)
 244 ALU2(MAC)
 245
 246 #undef ALU1
 247 #undef ALU2
 248 #undef ALU3
 249
 250
 251 /* Helpers for SEND instruction:
 252  */
 253
 254 /**
 255  * Construct a message descriptor immediate with the specified common
 256  * descriptor controls.
 257  */
 258 static inline uint32_t
 259 brw_message_desc(const struct gen_device_info *devinfo,
 260                  unsigned msg_length,
 261                  unsigned response_length,
 262                  bool header_present)
 263 {
 264    if (devinfo->gen >= 5) {
 265       return (SET_BITS(msg_length, 28, 25) |
 266               SET_BITS(response_length, 24, 20) |
 267               SET_BITS(header_present, 19, 19));
 268    } else {
 269       return (SET_BITS(msg_length, 23, 20) |
 270               SET_BITS(response_length, 19, 16));
 271    }
 272 }
 273
 274 static inline unsigned
 275 brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
 276 {
 277    if (devinfo->gen >= 5)
 278       return GET_BITS(desc, 28, 25);
 279    else
 280       return GET_BITS(desc, 23, 20);
 281 }
 282
 283 static inline unsigned
 284 brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
 285 {
 286    if (devinfo->gen >= 5)
 287       return GET_BITS(desc, 24, 20);
 288    else
 289       return GET_BITS(desc, 19, 16);
 290 }
 291
 292 static inline bool
 293 brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
 294                                 uint32_t desc)
 295 {
 296    assert(devinfo->gen >= 5);
 297    return GET_BITS(desc, 19, 19);
 298 }
 299
 300 static inline unsigned
 301 brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
 302                     unsigned ex_msg_length)
 303 {
 304    return SET_BITS(ex_msg_length, 9, 6);
 305 }
 306
 307 static inline unsigned
 308 brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
 309                             uint32_t ex_desc)
 310 {
 311    return GET_BITS(ex_desc, 9, 6);
 312 }
 313
 314 /**
 315  * Construct a message descriptor immediate with the specified sampler
 316  * function controls.
 317  */
 318 static inline uint32_t
 319 brw_sampler_desc(const struct gen_device_info *devinfo,
 320                  unsigned binding_table_index,
 321                  unsigned sampler,
 322                  unsigned msg_type,
 323                  unsigned simd_mode,
 324                  unsigned return_format)
 325 {
 326    const unsigned desc = (SET_BITS(binding_table_index, 7, 0) |
 327                           SET_BITS(sampler, 11, 8));
 328    if (devinfo->gen >= 7)
 329       return (desc | SET_BITS(msg_type, 16, 12) |
 330               SET_BITS(simd_mode, 18, 17));
 331    else if (devinfo->gen >= 5)
 332       return (desc | SET_BITS(msg_type, 15, 12) |
 333               SET_BITS(simd_mode, 17, 16));
 334    else if (devinfo->is_g4x)
 335       return desc | SET_BITS(msg_type, 15, 12);
 336    else
 337       return (desc | SET_BITS(return_format, 13, 12) |
 338               SET_BITS(msg_type, 15, 14));
 339 }
 340
 341 static inline unsigned
 342 brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 343                                      uint32_t desc)
 344 {
 345    return GET_BITS(desc, 7, 0);
 346 }
 347
 348 static inline unsigned
 349 brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
 350 {
 351    return GET_BITS(desc, 11, 8);
 352 }
 353
 354 static inline unsigned
 355 brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 356 {
 357    if (devinfo->gen >= 7)
 358       return GET_BITS(desc, 16, 12);
 359    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 360       return GET_BITS(desc, 15, 12);
 361    else
 362       return GET_BITS(desc, 15, 14);
 363 }
 364
 365 static inline unsigned
 366 brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
 367 {
 368    assert(devinfo->gen >= 5);
 369    if (devinfo->gen >= 7)
 370       return GET_BITS(desc, 18, 17);
 371    else
 372       return GET_BITS(desc, 17, 16);
 373 }
 374
 375 static  inline unsigned
 376 brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
 377                                uint32_t desc)
 378 {
 379    assert(devinfo->gen == 4 && !devinfo->is_g4x);
 380    return GET_BITS(desc, 13, 12);
 381 }
 382
 383 /**
 384  * Construct a message descriptor for the dataport
 385  */
 386 static inline uint32_t
 387 brw_dp_desc(const struct gen_device_info *devinfo,
 388             unsigned binding_table_index,
 389             unsigned msg_type,
 390             unsigned msg_control)
 391 {
 392    /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
 393     * helpers instead.
 394     */
 395    assert(devinfo->gen >= 6);
 396    const unsigned desc = SET_BITS(binding_table_index, 7, 0);
 397    if (devinfo->gen >= 8) {
 398       return (desc | SET_BITS(msg_control, 13, 8) |
 399               SET_BITS(msg_type, 18, 14));
 400    } else if (devinfo->gen >= 7) {
 401       return (desc | SET_BITS(msg_control, 13, 8) |
 402               SET_BITS(msg_type, 17, 14));
 403    } else {
 404       return (desc | SET_BITS(msg_control, 12, 8) |
 405               SET_BITS(msg_type, 16, 13));
 406    }
 407 }
 408
 409 static inline unsigned
 410 brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
 411                                 uint32_t desc)
 412 {
 413    return GET_BITS(desc, 7, 0);
 414 }
 415
 416 static inline unsigned
 417 brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 418 {
 419    assert(devinfo->gen >= 6);
 420    if (devinfo->gen >= 8)
 421       return GET_BITS(desc, 18, 14);
 422    else if (devinfo->gen >= 7)
 423       return GET_BITS(desc, 17, 14);
 424    else
 425       return GET_BITS(desc, 16, 13);
 426 }
 427
 428 static inline unsigned
 429 brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
 430 {
 431    assert(devinfo->gen >= 6);
 432    if (devinfo->gen >= 7)
 433       return GET_BITS(desc, 13, 8);
 434    else
 435       return GET_BITS(desc, 12, 8);
 436 }
 437
 438 /**
 439  * Construct a message descriptor immediate with the specified dataport read
 440  * function controls.
 441  */
 442 static inline uint32_t
 443 brw_dp_read_desc(const struct gen_device_info *devinfo,
 444                  unsigned binding_table_index,
 445                  unsigned msg_control,
 446                  unsigned msg_type,
 447                  unsigned target_cache)
 448 {
 449    if (devinfo->gen >= 6)
 450       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control);
 451    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 452       return (SET_BITS(binding_table_index, 7, 0) |
 453               SET_BITS(msg_control, 10, 8) |
 454               SET_BITS(msg_type, 13, 11) |
 455               SET_BITS(target_cache, 15, 14));
 456    else
 457       return (SET_BITS(binding_table_index, 7, 0) |
 458               SET_BITS(msg_control, 11, 8) |
 459               SET_BITS(msg_type, 13, 12) |
 460               SET_BITS(target_cache, 15, 14));
 461 }
 462
 463 static inline unsigned
 464 brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
 465 {
 466    if (devinfo->gen >= 6)
 467       return brw_dp_desc_msg_type(devinfo, desc);
 468    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 469       return GET_BITS(desc, 13, 11);
 470    else
 471       return GET_BITS(desc, 13, 12);
 472 }
 473
 474 static inline unsigned
 475 brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
 476                              uint32_t desc)
 477 {
 478    if (devinfo->gen >= 6)
 479       return brw_dp_desc_msg_control(devinfo, desc);
 480    else if (devinfo->gen >= 5 || devinfo->is_g4x)
 481       return GET_BITS(desc, 10, 8);
 482    else
 483       return GET_BITS(desc, 11, 8);
 484 }
 485
 486 /**
 487  * Construct a message descriptor immediate with the specified dataport write
 488  * function controls.
 489  */
 490 static inline uint32_t
 491 brw_dp_write_desc(const struct gen_device_info *devinfo,
 492                   unsigned binding_table_index,
 493                   unsigned msg_control,
 494                   unsigned msg_type,
 495                   unsigned last_render_target,
 496                   unsigned send_commit_msg)
 497 {
 498    assert(devinfo->gen <= 6 || !send_commit_msg);
 499    if (devinfo->gen >= 6)
 500       return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) |
 501              SET_BITS(last_render_target, 12, 12) |
 502              SET_BITS(send_commit_msg, 17, 17);
 503    else
 504       return (SET_BITS(binding_table_index, 7, 0) |
 505               SET_BITS(msg_control, 11, 8) |
 506               SET_BITS(last_render_target, 11, 11) |
 507               SET_BITS(msg_type, 14, 12) |
 508               SET_BITS(send_commit_msg, 15, 15));
 509 }
 510
 511 static inline unsigned
 512 brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
 513                            uint32_t desc)
 514 {
 515    if (devinfo->gen >= 6)
 516       return brw_dp_desc_msg_type(devinfo, desc);
 517    else
 518       return GET_BITS(desc, 14, 12);
 519 }
 520
 521 static inline unsigned
 522 brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
 523                               uint32_t desc)
 524 {
 525    if (devinfo->gen >= 6)
 526       return brw_dp_desc_msg_control(devinfo, desc);
 527    else
 528       return GET_BITS(desc, 11, 8);
 529 }
 530
 531 static inline bool
 532 brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
 533                                      uint32_t desc)
 534 {
 535    if (devinfo->gen >= 6)
 536       return GET_BITS(desc, 12, 12);
 537    else
 538       return GET_BITS(desc, 11, 11);
 539 }
 540
 541 static inline bool
 542 brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
 543                                uint32_t desc)
 544 {
 545    assert(devinfo->gen <= 6);
 546    if (devinfo->gen >= 6)
 547       return GET_BITS(desc, 17, 17);
 548    else
 549       return GET_BITS(desc, 15, 15);
 550 }
 551
 552 /**
 553  * Construct a message descriptor immediate with the specified dataport
 554  * surface function controls.
 555  */
 556 static inline uint32_t
 557 brw_dp_surface_desc(const struct gen_device_info *devinfo,
 558                     unsigned msg_type,
 559                     unsigned msg_control)
 560 {
 561    assert(devinfo->gen >= 7);
 562    /* We'll OR in the binding table index later */
 563    return brw_dp_desc(devinfo, 0, msg_type, msg_control);
 564 }
 565
 566 static inline uint32_t
 567 brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
 568                            unsigned exec_size, /**< 0 for SIMD4x2 */
 569                            unsigned atomic_op,
 570                            bool response_expected)
 571 {
 572    assert(exec_size <= 8 || exec_size == 16);
 573
 574    unsigned msg_type;
 575    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 576       if (exec_size > 0) {
 577          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
 578       } else {
 579          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
 580       }
 581    } else {
 582       msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
 583    }
 584
 585    const unsigned msg_control =
 586       SET_BITS(atomic_op, 3, 0) |
 587       SET_BITS(0 < exec_size && exec_size <= 8, 4, 4) |
 588       SET_BITS(response_expected, 5, 5);
 589
 590    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 591 }
 592
 593 static inline uint32_t
 594 brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 595                                  unsigned exec_size,
 596                                  unsigned atomic_op,
 597                                  bool response_expected)
 598 {
 599    assert(exec_size <= 8 || exec_size == 16);
 600    assert(devinfo->gen >= 9);
 601
 602    assert(exec_size > 0);
 603    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP;
 604
 605    const unsigned msg_control =
 606       SET_BITS(atomic_op, 1, 0) |
 607       SET_BITS(exec_size <= 8, 4, 4) |
 608       SET_BITS(response_expected, 5, 5);
 609
 610    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 611 }
 612
 613 static inline unsigned
 614 brw_mdc_cmask(unsigned num_channels)
 615 {
 616    /* See also MDC_CMASK in the SKL PRM Vol 2d. */
 617    return 0xf & (0xf << num_channels);
 618 }
 619
 620 static inline uint32_t
 621 brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 622                                unsigned exec_size, /**< 0 for SIMD4x2 */
 623                                unsigned num_channels,
 624                                bool write)
 625 {
 626    assert(exec_size <= 8 || exec_size == 16);
 627
 628    unsigned msg_type;
 629    if (write) {
 630       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 631          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE;
 632       } else {
 633          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE;
 634       }
 635    } else {
 636       /* Read */
 637       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 638          msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
 639       } else {
 640          msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
 641       }
 642    }
 643
 644    /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
 645    if (write && devinfo->gen == 7 && !devinfo->is_haswell && exec_size == 0)
 646       exec_size = 8;
 647
 648    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 649    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 650                               exec_size <= 8 ? 2 : 1;
 651
 652    const unsigned msg_control =
 653       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 654       SET_BITS(simd_mode, 5, 4);
 655
 656    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 657 }
 658
 659 static inline unsigned
 660 brw_mdc_ds(unsigned bit_size)
 661 {
 662    switch (bit_size) {
 663    case 8:
 664       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE;
 665    case 16:
 666       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD;
 667    case 32:
 668       return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD;
 669    default:
 670       unreachable("Unsupported bit_size for byte scattered messages");
 671    }
 672 }
 673
 674 static inline uint32_t
 675 brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 676                               unsigned exec_size,
 677                               unsigned bit_size,
 678                               bool write)
 679 {
 680    assert(exec_size <= 8 || exec_size == 16);
 681
 682    assert(devinfo->gen > 7 || devinfo->is_haswell);
 683    const unsigned msg_type =
 684       write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE :
 685               HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ;
 686
 687    assert(exec_size > 0);
 688    const unsigned msg_control =
 689       SET_BITS(exec_size == 16, 0, 0) |
 690       SET_BITS(brw_mdc_ds(bit_size), 3, 2);
 691
 692    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 693 }
 694
 695 static inline uint32_t
 696 brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
 697                                unsigned exec_size,
 698                                bool write)
 699 {
 700    assert(exec_size == 8 || exec_size == 16);
 701
 702    unsigned msg_type;
 703    if (write) {
 704       if (devinfo->gen >= 6) {
 705          msg_type = GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
 706       } else {
 707          msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE;
 708       }
 709    } else {
 710       if (devinfo->gen >= 7) {
 711          msg_type = GEN7_DATAPORT_DC_DWORD_SCATTERED_READ;
 712       } else if (devinfo->gen > 4 || devinfo->is_g4x) {
 713          msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
 714       } else {
 715          msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ;
 716       }
 717    }
 718
 719    const unsigned msg_control =
 720       SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
 721       SET_BITS(exec_size == 16, 0, 0);
 722
 723    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 724 }
 725
 726 static inline uint32_t
 727 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
 728                                    unsigned exec_size, /**< 0 for SIMD4x2 */
 729                                    unsigned num_channels,
 730                                    bool write)
 731 {
 732    assert(exec_size <= 8 || exec_size == 16);
 733    assert(devinfo->gen >= 8);
 734
 735    unsigned msg_type =
 736       write ? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE :
 737               GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ;
 738
 739    /* See also MDC_SM3 in the SKL PRM Vol 2d. */
 740    const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */
 741                               exec_size <= 8 ? 2 : 1;
 742
 743    const unsigned msg_control =
 744       SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 745       SET_BITS(simd_mode, 5, 4);
 746
 747    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 748                       msg_type, msg_control);
 749 }
 750
 751 /**
 752  * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
 753  * Skylake PRM).
 754  */
 755 static inline uint32_t
 756 brw_mdc_a64_ds(unsigned elems)
 757 {
 758    switch (elems) {
 759    case 1:  return 0;
 760    case 2:  return 1;
 761    case 4:  return 2;
 762    case 8:  return 3;
 763    default:
 764       unreachable("Unsupported elmeent count for A64 scattered message");
 765    }
 766 }
 767
 768 static inline uint32_t
 769 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
 770                                   unsigned exec_size, /**< 0 for SIMD4x2 */
 771                                   unsigned bit_size,
 772                                   bool write)
 773 {
 774    assert(exec_size <= 8 || exec_size == 16);
 775    assert(devinfo->gen >= 8);
 776
 777    unsigned msg_type =
 778       write ? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE :
 779               GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ;
 780
 781    const unsigned msg_control =
 782       SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE, 1, 0) |
 783       SET_BITS(brw_mdc_a64_ds(bit_size / 8), 3, 2) |
 784       SET_BITS(exec_size == 16, 4, 4);
 785
 786    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 787                       msg_type, msg_control);
 788 }
 789
 790 static inline uint32_t
 791 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
 792                                ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
 793                                unsigned bit_size,
 794                                unsigned atomic_op,
 795                                bool response_expected)
 796 {
 797    assert(exec_size == 8);
 798    assert(devinfo->gen >= 8);
 799    assert(bit_size == 32 || bit_size == 64);
 800
 801    const unsigned msg_type = GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP;
 802
 803    const unsigned msg_control =
 804       SET_BITS(atomic_op, 3, 0) |
 805       SET_BITS(bit_size == 64, 4, 4) |
 806       SET_BITS(response_expected, 5, 5);
 807
 808    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 809                       msg_type, msg_control);
 810 }
 811
 812 static inline uint32_t
 813 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
 814                                      ASSERTED unsigned exec_size,
 815                                      unsigned atomic_op,
 816                                      bool response_expected)
 817 {
 818    assert(exec_size == 8);
 819    assert(devinfo->gen >= 9);
 820
 821    assert(exec_size > 0);
 822    const unsigned msg_type = GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP;
 823
 824    const unsigned msg_control =
 825       SET_BITS(atomic_op, 1, 0) |
 826       SET_BITS(response_expected, 5, 5);
 827
 828    return brw_dp_desc(devinfo, GEN8_BTI_STATELESS_NON_COHERENT,
 829                       msg_type, msg_control);
 830 }
 831
 832 static inline uint32_t
 833 brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
 834                          unsigned exec_size,
 835                          unsigned exec_group,
 836                          unsigned atomic_op,
 837                          bool response_expected)
 838 {
 839    assert(exec_size > 0 || exec_group == 0);
 840    assert(exec_group % 8 == 0);
 841
 842    unsigned msg_type;
 843    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 844       if (exec_size == 0) {
 845          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2;
 846       } else {
 847          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP;
 848       }
 849    } else {
 850       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 851       assert(exec_size > 0);
 852       msg_type = GEN7_DATAPORT_RC_TYPED_ATOMIC_OP;
 853    }
 854
 855    const bool high_sample_mask = (exec_group / 8) % 2 == 1;
 856
 857    const unsigned msg_control =
 858       SET_BITS(atomic_op, 3, 0) |
 859       SET_BITS(high_sample_mask, 4, 4) |
 860       SET_BITS(response_expected, 5, 5);
 861
 862    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 863 }
 864
 865 static inline uint32_t
 866 brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
 867                              unsigned exec_size,
 868                              unsigned exec_group,
 869                              unsigned num_channels,
 870                              bool write)
 871 {
 872    assert(exec_size > 0 || exec_group == 0);
 873    assert(exec_group % 8 == 0);
 874
 875    /* Typed surface reads and writes don't support SIMD16 */
 876    assert(exec_size <= 8);
 877
 878    unsigned msg_type;
 879    if (write) {
 880       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 881          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE;
 882       } else {
 883          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE;
 884       }
 885    } else {
 886       if (devinfo->gen >= 8 || devinfo->is_haswell) {
 887          msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ;
 888       } else {
 889          msg_type = GEN7_DATAPORT_RC_TYPED_SURFACE_READ;
 890       }
 891    }
 892
 893    /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 894    unsigned msg_control;
 895    if (devinfo->gen >= 8 || devinfo->is_haswell) {
 896       /* See also MDC_SG3 in the SKL PRM Vol 2d. */
 897       const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */
 898                                   1 + ((exec_group / 8) % 2);
 899
 900       msg_control =
 901          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 902          SET_BITS(slot_group, 5, 4);
 903    } else {
 904       /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
 905       assert(exec_size > 0);
 906       const unsigned slot_group = ((exec_group / 8) % 2);
 907
 908       msg_control =
 909          SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
 910          SET_BITS(slot_group, 5, 5);
 911    }
 912
 913    return brw_dp_surface_desc(devinfo, msg_type, msg_control);
 914 }
 915
 916 /**
 917  * Construct a message descriptor immediate with the specified pixel
 918  * interpolator function controls.
 919  */
 920 static inline uint32_t
 921 brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
 922                       unsigned msg_type,
 923                       bool noperspective,
 924                       unsigned simd_mode,
 925                       unsigned slot_group)
 926 {
 927    return (SET_BITS(slot_group, 11, 11) |
 928            SET_BITS(msg_type, 13, 12) |
 929            SET_BITS(!!noperspective, 14, 14) |
 930            SET_BITS(simd_mode, 16, 16));
 931 }
 932
 933 void brw_urb_WRITE(struct brw_codegen *p,
 934                    struct brw_reg dest,
 935                    unsigned msg_reg_nr,
 936                    struct brw_reg src0,
 937                    enum brw_urb_write_flags flags,
 938                    unsigned msg_length,
 939                    unsigned response_length,
 940                    unsigned offset,
 941                    unsigned swizzle);
 942
 943 /**
 944  * Send message to shared unit \p sfid with a possibly indirect descriptor \p
 945  * desc.  If \p desc is not an immediate it will be transparently loaded to an
 946  * address register using an OR instruction.
 947  */
 948 void
 949 brw_send_indirect_message(struct brw_codegen *p,
 950                           unsigned sfid,
 951                           struct brw_reg dst,
 952                           struct brw_reg payload,
 953                           struct brw_reg desc,
 954                           unsigned desc_imm,
 955                           bool eot);
 956
 957 void
 958 brw_send_indirect_split_message(struct brw_codegen *p,
 959                                 unsigned sfid,
 960                                 struct brw_reg dst,
 961                                 struct brw_reg payload0,
 962                                 struct brw_reg payload1,
 963                                 struct brw_reg desc,
 964                                 unsigned desc_imm,
 965                                 struct brw_reg ex_desc,
 966                                 unsigned ex_desc_imm,
 967                                 bool eot);
 968
 969 void brw_ff_sync(struct brw_codegen *p,
 970                    struct brw_reg dest,
 971                    unsigned msg_reg_nr,
 972                    struct brw_reg src0,
 973                    bool allocate,
 974                    unsigned response_length,
 975                    bool eot);
 976
 977 void brw_svb_write(struct brw_codegen *p,
 978                    struct brw_reg dest,
 979                    unsigned msg_reg_nr,
 980                    struct brw_reg src0,
 981                    unsigned binding_table_index,
 982                    bool   send_commit_msg);
 983
 984 brw_inst *brw_fb_WRITE(struct brw_codegen *p,
 985                        struct brw_reg payload,
 986                        struct brw_reg implied_header,
 987                        unsigned msg_control,
 988                        unsigned binding_table_index,
 989                        unsigned msg_length,
 990                        unsigned response_length,
 991                        bool eot,
 992                        bool last_render_target,
 993                        bool header_present);
 994
 995 brw_inst *gen9_fb_READ(struct brw_codegen *p,
 996                        struct brw_reg dst,
 997                        struct brw_reg payload,
 998                        unsigned binding_table_index,
 999                        unsigned msg_length,
1000                        unsigned response_length,
1001                        bool per_sample);
1002
1003 void brw_SAMPLE(struct brw_codegen *p,
1004                 struct brw_reg dest,
1005                 unsigned msg_reg_nr,
1006                 struct brw_reg src0,
1007                 unsigned binding_table_index,
1008                 unsigned sampler,
1009                 unsigned msg_type,
1010                 unsigned response_length,
1011                 unsigned msg_length,
1012                 unsigned header_present,
1013                 unsigned simd_mode,
1014                 unsigned return_format);
1015
1016 void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
1017                                       struct brw_reg header,
1018                                       struct brw_reg sampler_index);
1019
1020 void gen4_math(struct brw_codegen *p,
1021                struct brw_reg dest,
1022                unsigned function,
1023                unsigned msg_reg_nr,
1024                struct brw_reg src,
1025                unsigned precision );
1026
1027 void gen6_math(struct brw_codegen *p,
1028                struct brw_reg dest,
1029                unsigned function,
1030                struct brw_reg src0,
1031                struct brw_reg src1);
1032
1033 void brw_oword_block_read(struct brw_codegen *p,
1034                           struct brw_reg dest,
1035                           struct brw_reg mrf,
1036                           uint32_t offset,
1037                           uint32_t bind_table_index);
1038
1039 unsigned brw_scratch_surface_idx(const struct brw_codegen *p);
1040
1041 void brw_oword_block_read_scratch(struct brw_codegen *p,
1042                                   struct brw_reg dest,
1043                                   struct brw_reg mrf,
1044                                   int num_regs,
1045                                   unsigned offset);
1046
1047 void brw_oword_block_write_scratch(struct brw_codegen *p,
1048                                    struct brw_reg mrf,
1049                                    int num_regs,
1050                                    unsigned offset);
1051
1052 void gen7_block_read_scratch(struct brw_codegen *p,
1053                              struct brw_reg dest,
1054                              int num_regs,
1055                              unsigned offset);
1056
1057 void brw_shader_time_add(struct brw_codegen *p,
1058                          struct brw_reg payload,
1059                          uint32_t surf_index);
1060
1061 /**
1062  * Return the generation-specific jump distance scaling factor.
1063  *
1064  * Given the number of instructions to jump, we need to scale by
1065  * some number to obtain the actual jump distance to program in an
1066  * instruction.
1067  */
1068 static inline unsigned
1069 brw_jump_scale(const struct gen_device_info *devinfo)
1070 {
1071    /* Broadwell measures jump targets in bytes. */
1072    if (devinfo->gen >= 8)
1073       return 16;
1074
1075    /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1076     * (to support compaction), so each 128-bit instruction requires 2 chunks.
1077     */
1078    if (devinfo->gen >= 5)
1079       return 2;
1080
1081    /* Gen4 simply uses the number of 128-bit instructions. */
1082    return 1;
1083 }
1084
1085 void brw_barrier(struct brw_codegen *p, struct brw_reg src);
1086
1087 /* If/else/endif.  Works by manipulating the execution flags on each
1088  * channel.
1089  */
1090 brw_inst *brw_IF(struct brw_codegen *p, unsigned execute_size);
1091 brw_inst *gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
1092                   struct brw_reg src0, struct brw_reg src1);
1093
1094 void brw_ELSE(struct brw_codegen *p);
1095 void brw_ENDIF(struct brw_codegen *p);
1096
1097 /* DO/WHILE loops:
1098  */
1099 brw_inst *brw_DO(struct brw_codegen *p, unsigned execute_size);
1100
1101 brw_inst *brw_WHILE(struct brw_codegen *p);
1102
1103 brw_inst *brw_BREAK(struct brw_codegen *p);
1104 brw_inst *brw_CONT(struct brw_codegen *p);
1105 brw_inst *brw_HALT(struct brw_codegen *p);
1106
1107 /* Forward jumps:
1108  */
1109 void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx);
1110
1111 brw_inst *brw_JMPI(struct brw_codegen *p, struct brw_reg index,
1112                    unsigned predicate_control);
1113
1114 void brw_NOP(struct brw_codegen *p);
1115
1116 void brw_WAIT(struct brw_codegen *p);
1117
1118 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func);
1119
1120 /* Special case: there is never a destination, execution size will be
1121  * taken from src0:
1122  */
1123 void brw_CMP(struct brw_codegen *p,
1124              struct brw_reg dest,
1125              unsigned conditional,
1126              struct brw_reg src0,
1127              struct brw_reg src1);
1128
1129 void
1130 brw_untyped_atomic(struct brw_codegen *p,
1131                    struct brw_reg dst,
1132                    struct brw_reg payload,
1133                    struct brw_reg surface,
1134                    unsigned atomic_op,
1135                    unsigned msg_length,
1136                    bool response_expected,
1137                    bool header_present);
1138
1139 void
1140 brw_untyped_surface_read(struct brw_codegen *p,
1141                          struct brw_reg dst,
1142                          struct brw_reg payload,
1143                          struct brw_reg surface,
1144                          unsigned msg_length,
1145                          unsigned num_channels);
1146
1147 void
1148 brw_untyped_surface_write(struct brw_codegen *p,
1149                           struct brw_reg payload,
1150                           struct brw_reg surface,
1151                           unsigned msg_length,
1152                           unsigned num_channels,
1153                           bool header_present);
1154
1155 void
1156 brw_memory_fence(struct brw_codegen *p,
1157                  struct brw_reg dst,
1158                  struct brw_reg src,
1159                  enum opcode send_op,
1160                  enum brw_message_target sfid,
1161                  bool commit_enable,
1162                  unsigned bti);
1163
1164 void
1165 brw_pixel_interpolator_query(struct brw_codegen *p,
1166                              struct brw_reg dest,
1167                              struct brw_reg mrf,
1168                              bool noperspective,
1169                              unsigned mode,
1170                              struct brw_reg data,
1171                              unsigned msg_length,
1172                              unsigned response_length);
1173
1174 void
1175 brw_find_live_channel(struct brw_codegen *p,
1176                       struct brw_reg dst,
1177                       struct brw_reg mask);
1178
1179 void
1180 brw_broadcast(struct brw_codegen *p,
1181               struct brw_reg dst,
1182               struct brw_reg src,
1183               struct brw_reg idx);
1184
1185 void
1186 brw_float_controls_mode(struct brw_codegen *p,
1187                         unsigned mode, unsigned mask);
1188
1189 /***********************************************************************
1190  * brw_eu_util.c:
1191  */
1192
1193 void brw_copy_indirect_to_indirect(struct brw_codegen *p,
1194                                    struct brw_indirect dst_ptr,
1195                                    struct brw_indirect src_ptr,
1196                                    unsigned count);
1197
1198 void brw_copy_from_indirect(struct brw_codegen *p,
1199                             struct brw_reg dst,
1200                             struct brw_indirect ptr,
1201                             unsigned count);
1202
1203 void brw_copy4(struct brw_codegen *p,
1204                struct brw_reg dst,
1205                struct brw_reg src,
1206                unsigned count);
1207
1208 void brw_copy8(struct brw_codegen *p,
1209                struct brw_reg dst,
1210                struct brw_reg src,
1211                unsigned count);
1212
1213 void brw_math_invert( struct brw_codegen *p,
1214                       struct brw_reg dst,
1215                       struct brw_reg src);
1216
1217 void brw_set_src1(struct brw_codegen *p, brw_inst *insn, struct brw_reg reg);
1218
1219 void brw_set_desc_ex(struct brw_codegen *p, brw_inst *insn,
1220                      unsigned desc, unsigned ex_desc);
1221
1222 static inline void
1223 brw_set_desc(struct brw_codegen *p, brw_inst *insn, unsigned desc)
1224 {
1225    brw_set_desc_ex(p, insn, desc, 0);
1226 }
1227
1228 void brw_set_uip_jip(struct brw_codegen *p, int start_offset);
1229
1230 enum brw_conditional_mod brw_negate_cmod(enum brw_conditional_mod cmod);
1231 enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
1232
1233 /* brw_eu_compact.c */
1234 void brw_init_compaction_tables(const struct gen_device_info *devinfo);
1235 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
1236                               struct disasm_info *disasm);
1237 void brw_uncompact_instruction(const struct gen_device_info *devinfo,
1238                                brw_inst *dst, brw_compact_inst *src);
1239 bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
1240                                  brw_compact_inst *dst, const brw_inst *src);
1241
1242 void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
1243                                  brw_inst *orig, brw_inst *uncompacted);
1244
1245 /* brw_eu_validate.c */
1246 bool brw_validate_instruction(const struct gen_device_info *devinfo,
1247                               const brw_inst *inst, int offset,
1248                               struct disasm_info *disasm);
1249 bool brw_validate_instructions(const struct gen_device_info *devinfo,
1250                                const void *assembly, int start_offset, int end_offset,
1251                                struct disasm_info *disasm);
1252
1253 static inline int
1254 next_offset(const struct gen_device_info *devinfo, void *store, int offset)
1255 {
1256    brw_inst *insn = (brw_inst *)((char *)store + offset);
1257
1258    if (brw_inst_cmpt_control(devinfo, insn))
1259       return offset + 8;
1260    else
1261       return offset + 16;
1262 }
1263
1264 struct opcode_desc {
1265    unsigned ir;
1266    unsigned hw;
1267    const char *name;
1268    int nsrc;
1269    int ndst;
1270    int gens;
1271 };
1272
1273 const struct opcode_desc *
1274 brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
1275
1276 const struct opcode_desc *
1277 brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
1278
1279 static inline unsigned
1280 brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
1281 {
1282    return brw_opcode_desc(devinfo, opcode)->hw;
1283 }
1284
1285 static inline enum opcode
1286 brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
1287 {
1288    const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
1289    return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
1290 }
1291
1292 static inline void
1293 brw_inst_set_opcode(const struct gen_device_info *devinfo,
1294                     brw_inst *inst, enum opcode opcode)
1295 {
1296    brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
1297 }
1298
1299 static inline enum opcode
1300 brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
1301 {
1302    return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
1303 }
1304
1305 static inline bool
1306 is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
1307 {
1308    const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
1309    return desc && desc->nsrc == 3;
1310 }
1311
1312 /** Maximum SEND message length */
1313 #define BRW_MAX_MSG_LENGTH 15
1314
1315 /** First MRF register used by pull loads */
1316 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1317
1318 /** First MRF register used by spills */
1319 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)
1320
1321 #ifdef __cplusplus
1322 }
1323 #endif
1324
1325 #endif