2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
39 #include "brw_eu_defines.h"
41 #include "brw_disasm_info.h"
47 #define BRW_EU_MAX_INSN_STACK 5
49 struct brw_insn_state
{
50 /* One of BRW_EXECUTE_* */
53 /* Group in units of channels */
56 /* Compression control on gen4-5 */
59 /* One of BRW_MASK_* */
60 unsigned mask_control
:1;
64 /* One of BRW_ALIGN_* */
65 unsigned access_mode
:1;
67 /* One of BRW_PREDICATE_* */
68 enum brw_predicate predicate
:4;
72 /* Flag subreg. Bottom bit is subreg, top bit is reg */
73 unsigned flag_subreg
:2;
75 bool acc_wr_control
:1;
79 /* A helper for accessing the last instruction emitted. This makes it easy
80 * to set various bits on an instruction without having to create temporary
81 * variable and assign the emitted instruction to those.
83 #define brw_last_inst (&p->store[p->nr_insn - 1])
89 unsigned int next_insn_offset
;
93 /* Allow clients to push/pop instruction state:
95 struct brw_insn_state stack
[BRW_EU_MAX_INSN_STACK
];
96 struct brw_insn_state
*current
;
98 /** Whether or not the user wants automatic exec sizes
100 * If true, codegen will try to automatically infer the exec size of an
101 * instruction from the width of the destination register. If false, it
102 * will take whatever is set by brw_set_default_exec_size verbatim.
104 * This is set to true by default in brw_init_codegen.
106 bool automatic_exec_sizes
;
108 bool single_program_flow
;
109 const struct gen_device_info
*devinfo
;
111 /* Control flow stacks:
112 * - if_stack contains IF and ELSE instructions which must be patched
113 * (and popped) once the matching ENDIF instruction is encountered.
115 * Just store the instruction pointer(an index).
119 int if_stack_array_size
;
122 * loop_stack contains the instruction pointers of the starts of loops which
123 * must be patched (and popped) once the matching WHILE instruction is
128 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
129 * blocks they were popping out of, to fix up the mask stack. This tracks
130 * the IF/ENDIF nesting in each current nested loop level.
132 int *if_depth_in_loop
;
133 int loop_stack_depth
;
134 int loop_stack_array_size
;
137 void brw_pop_insn_state( struct brw_codegen
*p
);
138 void brw_push_insn_state( struct brw_codegen
*p
);
139 unsigned brw_get_default_exec_size(struct brw_codegen
*p
);
140 unsigned brw_get_default_group(struct brw_codegen
*p
);
141 unsigned brw_get_default_access_mode(struct brw_codegen
*p
);
142 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
143 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
144 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
145 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
146 void brw_inst_set_compression(const struct gen_device_info
*devinfo
,
147 brw_inst
*inst
, bool on
);
148 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
149 void brw_inst_set_group(const struct gen_device_info
*devinfo
,
150 brw_inst
*inst
, unsigned group
);
151 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
152 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
153 void brw_set_default_predicate_control( struct brw_codegen
*p
, unsigned pc
);
154 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
155 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
156 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
158 void brw_init_codegen(const struct gen_device_info
*, struct brw_codegen
*p
,
160 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
161 const struct brw_inst
*inst
, bool is_compacted
);
162 void brw_disassemble(const struct gen_device_info
*devinfo
,
163 const void *assembly
, int start
, int end
, FILE *out
);
164 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
166 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
167 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
168 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
170 void gen6_resolve_implied_move(struct brw_codegen
*p
,
172 unsigned msg_reg_nr
);
174 /* Helpers for regular instructions:
177 brw_inst *brw_##OP(struct brw_codegen *p, \
178 struct brw_reg dest, \
179 struct brw_reg src0);
182 brw_inst *brw_##OP(struct brw_codegen *p, \
183 struct brw_reg dest, \
184 struct brw_reg src0, \
185 struct brw_reg src1);
188 brw_inst *brw_##OP(struct brw_codegen *p, \
189 struct brw_reg dest, \
190 struct brw_reg src0, \
191 struct brw_reg src1, \
192 struct brw_reg src2);
195 void brw_##OP(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0);
246 /* Helpers for SEND instruction:
250 * Construct a message descriptor immediate with the specified common
251 * descriptor controls.
253 static inline uint32_t
254 brw_message_desc(const struct gen_device_info
*devinfo
,
256 unsigned response_length
,
259 if (devinfo
->gen
>= 5) {
260 return (SET_BITS(msg_length
, 28, 25) |
261 SET_BITS(response_length
, 24, 20) |
262 SET_BITS(header_present
, 19, 19));
264 return (SET_BITS(msg_length
, 23, 20) |
265 SET_BITS(response_length
, 19, 16));
270 * Construct a message descriptor immediate with the specified sampler
273 static inline uint32_t
274 brw_sampler_desc(const struct gen_device_info
*devinfo
,
275 unsigned binding_table_index
,
279 unsigned return_format
)
281 const unsigned desc
= (SET_BITS(binding_table_index
, 7, 0) |
282 SET_BITS(sampler
, 11, 8));
283 if (devinfo
->gen
>= 7)
284 return (desc
| SET_BITS(msg_type
, 16, 12) |
285 SET_BITS(simd_mode
, 18, 17));
286 else if (devinfo
->gen
>= 5)
287 return (desc
| SET_BITS(msg_type
, 15, 12) |
288 SET_BITS(simd_mode
, 17, 16));
289 else if (devinfo
->is_g4x
)
290 return desc
| SET_BITS(msg_type
, 15, 12);
292 return (desc
| SET_BITS(return_format
, 13, 12) |
293 SET_BITS(msg_type
, 15, 14));
297 * Construct a message descriptor immediate with the specified dataport read
300 static inline uint32_t
301 brw_dp_read_desc(const struct gen_device_info
*devinfo
,
302 unsigned binding_table_index
,
303 unsigned msg_control
,
305 unsigned target_cache
)
307 const unsigned desc
= SET_BITS(binding_table_index
, 7, 0);
308 if (devinfo
->gen
>= 7)
309 return (desc
| SET_BITS(msg_control
, 13, 8) |
310 SET_BITS(msg_type
, 17, 14));
311 else if (devinfo
->gen
>= 6)
312 return (desc
| SET_BITS(msg_control
, 12, 8) |
313 SET_BITS(msg_type
, 16, 13));
314 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
315 return (desc
| SET_BITS(msg_control
, 10, 8) |
316 SET_BITS(msg_type
, 13, 11) |
317 SET_BITS(target_cache
, 15, 14));
319 return (desc
| SET_BITS(msg_control
, 11, 8) |
320 SET_BITS(msg_type
, 13, 12) |
321 SET_BITS(target_cache
, 15, 14));
325 * Construct a message descriptor immediate with the specified dataport write
328 static inline uint32_t
329 brw_dp_write_desc(const struct gen_device_info
*devinfo
,
330 unsigned binding_table_index
,
331 unsigned msg_control
,
333 unsigned last_render_target
,
334 unsigned send_commit_msg
)
336 const unsigned desc
= SET_BITS(binding_table_index
, 7, 0);
337 if (devinfo
->gen
>= 7)
338 return (desc
| SET_BITS(msg_control
, 13, 8) |
339 SET_BITS(last_render_target
, 12, 12) |
340 SET_BITS(msg_type
, 17, 14));
341 else if (devinfo
->gen
>= 6)
342 return (desc
| SET_BITS(msg_control
, 12, 8) |
343 SET_BITS(last_render_target
, 12, 12) |
344 SET_BITS(msg_type
, 16, 13) |
345 SET_BITS(send_commit_msg
, 17, 17));
347 return (desc
| SET_BITS(msg_control
, 11, 8) |
348 SET_BITS(last_render_target
, 11, 11) |
349 SET_BITS(msg_type
, 14, 12) |
350 SET_BITS(send_commit_msg
, 15, 15));
354 * Construct a message descriptor immediate with the specified dataport
355 * surface function controls.
357 static inline uint32_t
358 brw_dp_surface_desc(const struct gen_device_info
*devinfo
,
360 unsigned msg_control
)
362 assert(devinfo
->gen
>= 7);
363 if (devinfo
->gen
>= 8) {
364 return (SET_BITS(msg_control
, 13, 8) |
365 SET_BITS(msg_type
, 18, 14));
367 return (SET_BITS(msg_control
, 13, 8) |
368 SET_BITS(msg_type
, 17, 14));
372 static inline uint32_t
373 brw_dp_untyped_atomic_desc(const struct gen_device_info
*devinfo
,
374 unsigned exec_size
, /**< 0 for SIMD4x2 */
376 bool response_expected
)
378 assert(exec_size
<= 8 || exec_size
== 16);
381 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
383 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
;
385 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
;
388 msg_type
= GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
;
391 const unsigned msg_control
=
392 SET_BITS(atomic_op
, 3, 0) |
393 SET_BITS(0 < exec_size
&& exec_size
<= 8, 4, 4) |
394 SET_BITS(response_expected
, 5, 5);
396 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
399 static inline uint32_t
400 brw_dp_untyped_atomic_float_desc(const struct gen_device_info
*devinfo
,
403 bool response_expected
)
405 assert(exec_size
<= 8 || exec_size
== 16);
406 assert(devinfo
->gen
>= 9);
408 assert(exec_size
> 0);
409 const unsigned msg_type
= GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
;
411 const unsigned msg_control
=
412 SET_BITS(atomic_op
, 1, 0) |
413 SET_BITS(exec_size
<= 8, 4, 4) |
414 SET_BITS(response_expected
, 5, 5);
416 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
419 static inline unsigned
420 brw_mdc_cmask(unsigned num_channels
)
422 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
423 return 0xf & (0xf << num_channels
);
426 static inline uint32_t
427 brw_dp_untyped_surface_rw_desc(const struct gen_device_info
*devinfo
,
428 unsigned exec_size
, /**< 0 for SIMD4x2 */
429 unsigned num_channels
,
432 assert(exec_size
<= 8 || exec_size
== 16);
436 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
437 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
;
439 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
;
443 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
444 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
;
446 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
;
450 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
451 if (write
&& devinfo
->gen
== 7 && !devinfo
->is_haswell
&& exec_size
== 0)
454 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
455 const unsigned simd_mode
= exec_size
== 0 ? 0 : /* SIMD4x2 */
456 exec_size
<= 8 ? 2 : 1;
458 const unsigned msg_control
=
459 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
460 SET_BITS(simd_mode
, 5, 4);
462 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
465 static inline unsigned
466 brw_mdc_ds(unsigned bit_size
)
470 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE
;
472 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD
;
474 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD
;
476 unreachable("Unsupported bit_size for byte scattered messages");
480 static inline uint32_t
481 brw_dp_byte_scattered_rw_desc(const struct gen_device_info
*devinfo
,
486 assert(exec_size
<= 8 || exec_size
== 16);
488 assert(devinfo
->gen
> 7 || devinfo
->is_haswell
);
489 const unsigned msg_type
=
490 write
? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
491 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
;
493 assert(exec_size
> 0);
494 const unsigned msg_control
=
495 SET_BITS(exec_size
== 16, 0, 0) |
496 SET_BITS(brw_mdc_ds(bit_size
), 3, 2);
498 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
501 static inline uint32_t
502 brw_dp_typed_atomic_desc(const struct gen_device_info
*devinfo
,
506 bool response_expected
)
508 assert(exec_size
> 0 || exec_group
== 0);
509 assert(exec_group
% 8 == 0);
512 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
513 if (exec_size
== 0) {
514 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
;
516 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
;
519 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
520 assert(exec_size
> 0);
521 msg_type
= GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
;
524 const bool high_sample_mask
= (exec_group
/ 8) % 2 == 1;
526 const unsigned msg_control
=
527 SET_BITS(atomic_op
, 3, 0) |
528 SET_BITS(high_sample_mask
, 4, 4) |
529 SET_BITS(response_expected
, 5, 5);
531 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
534 static inline uint32_t
535 brw_dp_typed_surface_rw_desc(const struct gen_device_info
*devinfo
,
538 unsigned num_channels
,
541 assert(exec_size
> 0 || exec_group
== 0);
542 assert(exec_group
% 8 == 0);
544 /* Typed surface reads and writes don't support SIMD16 */
545 assert(exec_size
<= 8);
549 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
550 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
;
552 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
;
555 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
556 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
;
558 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_READ
;
562 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
563 unsigned msg_control
;
564 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
565 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
566 const unsigned slot_group
= exec_size
== 0 ? 0 : /* SIMD4x2 */
567 1 + ((exec_group
/ 8) % 2);
570 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
571 SET_BITS(slot_group
, 5, 4);
573 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
574 assert(exec_size
> 0);
575 const unsigned slot_group
= ((exec_group
/ 8) % 2);
578 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
579 SET_BITS(slot_group
, 5, 5);
582 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
586 * Construct a message descriptor immediate with the specified pixel
587 * interpolator function controls.
589 static inline uint32_t
590 brw_pixel_interp_desc(UNUSED
const struct gen_device_info
*devinfo
,
596 return (SET_BITS(slot_group
, 11, 11) |
597 SET_BITS(msg_type
, 13, 12) |
598 SET_BITS(!!noperspective
, 14, 14) |
599 SET_BITS(simd_mode
, 16, 16));
602 void brw_urb_WRITE(struct brw_codegen
*p
,
606 enum brw_urb_write_flags flags
,
608 unsigned response_length
,
613 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
614 * desc. If \p desc is not an immediate it will be transparently loaded to an
615 * address register using an OR instruction.
618 brw_send_indirect_message(struct brw_codegen
*p
,
621 struct brw_reg payload
,
625 void brw_ff_sync(struct brw_codegen
*p
,
630 unsigned response_length
,
633 void brw_svb_write(struct brw_codegen
*p
,
637 unsigned binding_table_index
,
638 bool send_commit_msg
);
640 brw_inst
*brw_fb_WRITE(struct brw_codegen
*p
,
641 struct brw_reg payload
,
642 struct brw_reg implied_header
,
643 unsigned msg_control
,
644 unsigned binding_table_index
,
646 unsigned response_length
,
648 bool last_render_target
,
649 bool header_present
);
651 brw_inst
*gen9_fb_READ(struct brw_codegen
*p
,
653 struct brw_reg payload
,
654 unsigned binding_table_index
,
656 unsigned response_length
,
659 void brw_SAMPLE(struct brw_codegen
*p
,
663 unsigned binding_table_index
,
666 unsigned response_length
,
668 unsigned header_present
,
670 unsigned return_format
);
672 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
673 struct brw_reg header
,
674 struct brw_reg sampler_index
);
676 void gen4_math(struct brw_codegen
*p
,
681 unsigned precision
);
683 void gen6_math(struct brw_codegen
*p
,
687 struct brw_reg src1
);
689 void brw_oword_block_read(struct brw_codegen
*p
,
693 uint32_t bind_table_index
);
695 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
697 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
703 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
708 void gen7_block_read_scratch(struct brw_codegen
*p
,
713 void brw_shader_time_add(struct brw_codegen
*p
,
714 struct brw_reg payload
,
715 uint32_t surf_index
);
718 * Return the generation-specific jump distance scaling factor.
720 * Given the number of instructions to jump, we need to scale by
721 * some number to obtain the actual jump distance to program in an
724 static inline unsigned
725 brw_jump_scale(const struct gen_device_info
*devinfo
)
727 /* Broadwell measures jump targets in bytes. */
728 if (devinfo
->gen
>= 8)
731 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
732 * (to support compaction), so each 128-bit instruction requires 2 chunks.
734 if (devinfo
->gen
>= 5)
737 /* Gen4 simply uses the number of 128-bit instructions. */
741 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
743 /* If/else/endif. Works by manipulating the execution flags on each
746 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
747 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
748 struct brw_reg src0
, struct brw_reg src1
);
750 void brw_ELSE(struct brw_codegen
*p
);
751 void brw_ENDIF(struct brw_codegen
*p
);
755 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
757 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
759 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
760 brw_inst
*brw_CONT(struct brw_codegen
*p
);
761 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
765 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
767 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
768 unsigned predicate_control
);
770 void brw_NOP(struct brw_codegen
*p
);
772 void brw_WAIT(struct brw_codegen
*p
);
774 /* Special case: there is never a destination, execution size will be
777 void brw_CMP(struct brw_codegen
*p
,
779 unsigned conditional
,
781 struct brw_reg src1
);
784 brw_untyped_atomic(struct brw_codegen
*p
,
786 struct brw_reg payload
,
787 struct brw_reg surface
,
790 bool response_expected
,
791 bool header_present
);
794 brw_untyped_surface_read(struct brw_codegen
*p
,
796 struct brw_reg payload
,
797 struct brw_reg surface
,
799 unsigned num_channels
);
802 brw_untyped_surface_write(struct brw_codegen
*p
,
803 struct brw_reg payload
,
804 struct brw_reg surface
,
806 unsigned num_channels
,
807 bool header_present
);
810 brw_typed_atomic(struct brw_codegen
*p
,
812 struct brw_reg payload
,
813 struct brw_reg surface
,
816 bool response_expected
,
817 bool header_present
);
820 brw_typed_surface_read(struct brw_codegen
*p
,
822 struct brw_reg payload
,
823 struct brw_reg surface
,
825 unsigned num_channels
,
826 bool header_present
);
829 brw_typed_surface_write(struct brw_codegen
*p
,
830 struct brw_reg payload
,
831 struct brw_reg surface
,
833 unsigned num_channels
,
834 bool header_present
);
837 brw_memory_fence(struct brw_codegen
*p
,
839 enum opcode send_op
);
842 brw_pixel_interpolator_query(struct brw_codegen
*p
,
849 unsigned response_length
);
852 brw_find_live_channel(struct brw_codegen
*p
,
854 struct brw_reg mask
);
857 brw_broadcast(struct brw_codegen
*p
,
863 brw_rounding_mode(struct brw_codegen
*p
,
864 enum brw_rnd_mode mode
);
866 /***********************************************************************
870 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
871 struct brw_indirect dst_ptr
,
872 struct brw_indirect src_ptr
,
875 void brw_copy_from_indirect(struct brw_codegen
*p
,
877 struct brw_indirect ptr
,
880 void brw_copy4(struct brw_codegen
*p
,
885 void brw_copy8(struct brw_codegen
*p
,
890 void brw_math_invert( struct brw_codegen
*p
,
894 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
896 void brw_set_desc_ex(struct brw_codegen
*p
, brw_inst
*insn
,
897 unsigned desc
, unsigned ex_desc
);
900 brw_set_desc(struct brw_codegen
*p
, brw_inst
*insn
, unsigned desc
)
902 brw_set_desc_ex(p
, insn
, desc
, 0);
905 void brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
);
907 enum brw_conditional_mod
brw_negate_cmod(uint32_t cmod
);
908 enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod
);
910 /* brw_eu_compact.c */
911 void brw_init_compaction_tables(const struct gen_device_info
*devinfo
);
912 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
913 struct disasm_info
*disasm
);
914 void brw_uncompact_instruction(const struct gen_device_info
*devinfo
,
915 brw_inst
*dst
, brw_compact_inst
*src
);
916 bool brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
917 brw_compact_inst
*dst
, const brw_inst
*src
);
919 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
920 brw_inst
*orig
, brw_inst
*uncompacted
);
922 /* brw_eu_validate.c */
923 bool brw_validate_instructions(const struct gen_device_info
*devinfo
,
924 const void *assembly
, int start_offset
, int end_offset
,
925 struct disasm_info
*disasm
);
928 next_offset(const struct gen_device_info
*devinfo
, void *store
, int offset
)
930 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
932 if (brw_inst_cmpt_control(devinfo
, insn
))
939 /* The union is an implementation detail used by brw_opcode_desc() to handle
940 * opcodes that have been reused for different instructions across hardware
943 * The gens field acts as a tag. If it is non-zero, name points to a string
944 * containing the instruction mnemonic. If it is zero, the table field is
945 * valid and either points to a secondary opcode_desc table with 'size'
946 * elements or is NULL and no such instruction exists for the opcode.
954 const struct opcode_desc
*table
;
962 const struct opcode_desc
*
963 brw_opcode_desc(const struct gen_device_info
*devinfo
, enum opcode opcode
);
966 is_3src(const struct gen_device_info
*devinfo
, enum opcode opcode
)
968 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
969 return desc
&& desc
->nsrc
== 3;
972 /** Maximum SEND message length */
973 #define BRW_MAX_MSG_LENGTH 15
975 /** First MRF register used by pull loads */
976 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
978 /** First MRF register used by spills */
979 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)