2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
39 #include "brw_eu_defines.h"
41 #include "brw_disasm_info.h"
47 #define BRW_EU_MAX_INSN_STACK 5
49 struct brw_insn_state
{
50 /* One of BRW_EXECUTE_* */
53 /* Group in units of channels */
56 /* Compression control on gen4-5 */
59 /* One of BRW_MASK_* */
60 unsigned mask_control
:1;
62 /* Scheduling info for Gen12+ */
67 /* One of BRW_ALIGN_* */
68 unsigned access_mode
:1;
70 /* One of BRW_PREDICATE_* */
71 enum brw_predicate predicate
:4;
75 /* Flag subreg. Bottom bit is subreg, top bit is reg */
76 unsigned flag_subreg
:2;
78 bool acc_wr_control
:1;
82 /* A helper for accessing the last instruction emitted. This makes it easy
83 * to set various bits on an instruction without having to create temporary
84 * variable and assign the emitted instruction to those.
86 #define brw_last_inst (&p->store[p->nr_insn - 1])
92 unsigned int next_insn_offset
;
96 /* Allow clients to push/pop instruction state:
98 struct brw_insn_state stack
[BRW_EU_MAX_INSN_STACK
];
99 struct brw_insn_state
*current
;
101 /** Whether or not the user wants automatic exec sizes
103 * If true, codegen will try to automatically infer the exec size of an
104 * instruction from the width of the destination register. If false, it
105 * will take whatever is set by brw_set_default_exec_size verbatim.
107 * This is set to true by default in brw_init_codegen.
109 bool automatic_exec_sizes
;
111 bool single_program_flow
;
112 const struct gen_device_info
*devinfo
;
114 /* Control flow stacks:
115 * - if_stack contains IF and ELSE instructions which must be patched
116 * (and popped) once the matching ENDIF instruction is encountered.
118 * Just store the instruction pointer(an index).
122 int if_stack_array_size
;
125 * loop_stack contains the instruction pointers of the starts of loops which
126 * must be patched (and popped) once the matching WHILE instruction is
131 * pre-gen6, the BREAK and CONT instructions had to tell how many IF/ENDIF
132 * blocks they were popping out of, to fix up the mask stack. This tracks
133 * the IF/ENDIF nesting in each current nested loop level.
135 int *if_depth_in_loop
;
136 int loop_stack_depth
;
137 int loop_stack_array_size
;
140 void brw_pop_insn_state( struct brw_codegen
*p
);
141 void brw_push_insn_state( struct brw_codegen
*p
);
142 unsigned brw_get_default_exec_size(struct brw_codegen
*p
);
143 unsigned brw_get_default_group(struct brw_codegen
*p
);
144 unsigned brw_get_default_access_mode(struct brw_codegen
*p
);
145 struct tgl_swsb
brw_get_default_swsb(struct brw_codegen
*p
);
146 void brw_set_default_exec_size(struct brw_codegen
*p
, unsigned value
);
147 void brw_set_default_mask_control( struct brw_codegen
*p
, unsigned value
);
148 void brw_set_default_saturate( struct brw_codegen
*p
, bool enable
);
149 void brw_set_default_access_mode( struct brw_codegen
*p
, unsigned access_mode
);
150 void brw_inst_set_compression(const struct gen_device_info
*devinfo
,
151 brw_inst
*inst
, bool on
);
152 void brw_set_default_compression(struct brw_codegen
*p
, bool on
);
153 void brw_inst_set_group(const struct gen_device_info
*devinfo
,
154 brw_inst
*inst
, unsigned group
);
155 void brw_set_default_group(struct brw_codegen
*p
, unsigned group
);
156 void brw_set_default_compression_control(struct brw_codegen
*p
, enum brw_compression c
);
157 void brw_set_default_predicate_control(struct brw_codegen
*p
, enum brw_predicate pc
);
158 void brw_set_default_predicate_inverse(struct brw_codegen
*p
, bool predicate_inverse
);
159 void brw_set_default_flag_reg(struct brw_codegen
*p
, int reg
, int subreg
);
160 void brw_set_default_acc_write_control(struct brw_codegen
*p
, unsigned value
);
161 void brw_set_default_swsb(struct brw_codegen
*p
, struct tgl_swsb value
);
163 void brw_init_codegen(const struct gen_device_info
*, struct brw_codegen
*p
,
165 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
166 const struct brw_inst
*inst
, bool is_compacted
);
167 void brw_disassemble(const struct gen_device_info
*devinfo
,
168 const void *assembly
, int start
, int end
, FILE *out
);
169 const unsigned *brw_get_program( struct brw_codegen
*p
, unsigned *sz
);
171 bool brw_try_override_assembly(struct brw_codegen
*p
, int start_offset
,
172 const char *identifier
);
174 brw_inst
*brw_next_insn(struct brw_codegen
*p
, unsigned opcode
);
175 void brw_set_dest(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg dest
);
176 void brw_set_src0(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
178 void gen6_resolve_implied_move(struct brw_codegen
*p
,
180 unsigned msg_reg_nr
);
182 /* Helpers for regular instructions:
185 brw_inst *brw_##OP(struct brw_codegen *p, \
186 struct brw_reg dest, \
187 struct brw_reg src0);
190 brw_inst *brw_##OP(struct brw_codegen *p, \
191 struct brw_reg dest, \
192 struct brw_reg src0, \
193 struct brw_reg src1);
196 brw_inst *brw_##OP(struct brw_codegen *p, \
197 struct brw_reg dest, \
198 struct brw_reg src0, \
199 struct brw_reg src1, \
200 struct brw_reg src2);
251 /* Helpers for SEND instruction:
255 * Construct a message descriptor immediate with the specified common
256 * descriptor controls.
258 static inline uint32_t
259 brw_message_desc(const struct gen_device_info
*devinfo
,
261 unsigned response_length
,
264 if (devinfo
->gen
>= 5) {
265 return (SET_BITS(msg_length
, 28, 25) |
266 SET_BITS(response_length
, 24, 20) |
267 SET_BITS(header_present
, 19, 19));
269 return (SET_BITS(msg_length
, 23, 20) |
270 SET_BITS(response_length
, 19, 16));
274 static inline unsigned
275 brw_message_desc_mlen(const struct gen_device_info
*devinfo
, uint32_t desc
)
277 if (devinfo
->gen
>= 5)
278 return GET_BITS(desc
, 28, 25);
280 return GET_BITS(desc
, 23, 20);
283 static inline unsigned
284 brw_message_desc_rlen(const struct gen_device_info
*devinfo
, uint32_t desc
)
286 if (devinfo
->gen
>= 5)
287 return GET_BITS(desc
, 24, 20);
289 return GET_BITS(desc
, 19, 16);
293 brw_message_desc_header_present(ASSERTED
const struct gen_device_info
*devinfo
,
296 assert(devinfo
->gen
>= 5);
297 return GET_BITS(desc
, 19, 19);
300 static inline unsigned
301 brw_message_ex_desc(UNUSED
const struct gen_device_info
*devinfo
,
302 unsigned ex_msg_length
)
304 return SET_BITS(ex_msg_length
, 9, 6);
307 static inline unsigned
308 brw_message_ex_desc_ex_mlen(UNUSED
const struct gen_device_info
*devinfo
,
311 return GET_BITS(ex_desc
, 9, 6);
315 * Construct a message descriptor immediate with the specified sampler
318 static inline uint32_t
319 brw_sampler_desc(const struct gen_device_info
*devinfo
,
320 unsigned binding_table_index
,
324 unsigned return_format
)
326 const unsigned desc
= (SET_BITS(binding_table_index
, 7, 0) |
327 SET_BITS(sampler
, 11, 8));
328 if (devinfo
->gen
>= 7)
329 return (desc
| SET_BITS(msg_type
, 16, 12) |
330 SET_BITS(simd_mode
, 18, 17));
331 else if (devinfo
->gen
>= 5)
332 return (desc
| SET_BITS(msg_type
, 15, 12) |
333 SET_BITS(simd_mode
, 17, 16));
334 else if (devinfo
->is_g4x
)
335 return desc
| SET_BITS(msg_type
, 15, 12);
337 return (desc
| SET_BITS(return_format
, 13, 12) |
338 SET_BITS(msg_type
, 15, 14));
341 static inline unsigned
342 brw_sampler_desc_binding_table_index(UNUSED
const struct gen_device_info
*devinfo
,
345 return GET_BITS(desc
, 7, 0);
348 static inline unsigned
349 brw_sampler_desc_sampler(UNUSED
const struct gen_device_info
*devinfo
, uint32_t desc
)
351 return GET_BITS(desc
, 11, 8);
354 static inline unsigned
355 brw_sampler_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
357 if (devinfo
->gen
>= 7)
358 return GET_BITS(desc
, 16, 12);
359 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
360 return GET_BITS(desc
, 15, 12);
362 return GET_BITS(desc
, 15, 14);
365 static inline unsigned
366 brw_sampler_desc_simd_mode(const struct gen_device_info
*devinfo
, uint32_t desc
)
368 assert(devinfo
->gen
>= 5);
369 if (devinfo
->gen
>= 7)
370 return GET_BITS(desc
, 18, 17);
372 return GET_BITS(desc
, 17, 16);
375 static inline unsigned
376 brw_sampler_desc_return_format(ASSERTED
const struct gen_device_info
*devinfo
,
379 assert(devinfo
->gen
== 4 && !devinfo
->is_g4x
);
380 return GET_BITS(desc
, 13, 12);
384 * Construct a message descriptor for the dataport
386 static inline uint32_t
387 brw_dp_desc(const struct gen_device_info
*devinfo
,
388 unsigned binding_table_index
,
390 unsigned msg_control
)
392 /* Prior to gen6, things are too inconsistent; use the dp_read/write_desc
395 assert(devinfo
->gen
>= 6);
396 const unsigned desc
= SET_BITS(binding_table_index
, 7, 0);
397 if (devinfo
->gen
>= 8) {
398 return (desc
| SET_BITS(msg_control
, 13, 8) |
399 SET_BITS(msg_type
, 18, 14));
400 } else if (devinfo
->gen
>= 7) {
401 return (desc
| SET_BITS(msg_control
, 13, 8) |
402 SET_BITS(msg_type
, 17, 14));
404 return (desc
| SET_BITS(msg_control
, 12, 8) |
405 SET_BITS(msg_type
, 16, 13));
409 static inline unsigned
410 brw_dp_desc_binding_table_index(UNUSED
const struct gen_device_info
*devinfo
,
413 return GET_BITS(desc
, 7, 0);
416 static inline unsigned
417 brw_dp_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
419 assert(devinfo
->gen
>= 6);
420 if (devinfo
->gen
>= 8)
421 return GET_BITS(desc
, 18, 14);
422 else if (devinfo
->gen
>= 7)
423 return GET_BITS(desc
, 17, 14);
425 return GET_BITS(desc
, 16, 13);
428 static inline unsigned
429 brw_dp_desc_msg_control(const struct gen_device_info
*devinfo
, uint32_t desc
)
431 assert(devinfo
->gen
>= 6);
432 if (devinfo
->gen
>= 7)
433 return GET_BITS(desc
, 13, 8);
435 return GET_BITS(desc
, 12, 8);
439 * Construct a message descriptor immediate with the specified dataport read
442 static inline uint32_t
443 brw_dp_read_desc(const struct gen_device_info
*devinfo
,
444 unsigned binding_table_index
,
445 unsigned msg_control
,
447 unsigned target_cache
)
449 if (devinfo
->gen
>= 6)
450 return brw_dp_desc(devinfo
, binding_table_index
, msg_type
, msg_control
);
451 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
452 return (SET_BITS(binding_table_index
, 7, 0) |
453 SET_BITS(msg_control
, 10, 8) |
454 SET_BITS(msg_type
, 13, 11) |
455 SET_BITS(target_cache
, 15, 14));
457 return (SET_BITS(binding_table_index
, 7, 0) |
458 SET_BITS(msg_control
, 11, 8) |
459 SET_BITS(msg_type
, 13, 12) |
460 SET_BITS(target_cache
, 15, 14));
463 static inline unsigned
464 brw_dp_read_desc_msg_type(const struct gen_device_info
*devinfo
, uint32_t desc
)
466 if (devinfo
->gen
>= 6)
467 return brw_dp_desc_msg_type(devinfo
, desc
);
468 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
469 return GET_BITS(desc
, 13, 11);
471 return GET_BITS(desc
, 13, 12);
474 static inline unsigned
475 brw_dp_read_desc_msg_control(const struct gen_device_info
*devinfo
,
478 if (devinfo
->gen
>= 6)
479 return brw_dp_desc_msg_control(devinfo
, desc
);
480 else if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
481 return GET_BITS(desc
, 10, 8);
483 return GET_BITS(desc
, 11, 8);
487 * Construct a message descriptor immediate with the specified dataport write
490 static inline uint32_t
491 brw_dp_write_desc(const struct gen_device_info
*devinfo
,
492 unsigned binding_table_index
,
493 unsigned msg_control
,
495 unsigned last_render_target
,
496 unsigned send_commit_msg
)
498 assert(devinfo
->gen
<= 6 || !send_commit_msg
);
499 if (devinfo
->gen
>= 6)
500 return brw_dp_desc(devinfo
, binding_table_index
, msg_type
, msg_control
) |
501 SET_BITS(last_render_target
, 12, 12) |
502 SET_BITS(send_commit_msg
, 17, 17);
504 return (SET_BITS(binding_table_index
, 7, 0) |
505 SET_BITS(msg_control
, 11, 8) |
506 SET_BITS(last_render_target
, 11, 11) |
507 SET_BITS(msg_type
, 14, 12) |
508 SET_BITS(send_commit_msg
, 15, 15));
511 static inline unsigned
512 brw_dp_write_desc_msg_type(const struct gen_device_info
*devinfo
,
515 if (devinfo
->gen
>= 6)
516 return brw_dp_desc_msg_type(devinfo
, desc
);
518 return GET_BITS(desc
, 14, 12);
521 static inline unsigned
522 brw_dp_write_desc_msg_control(const struct gen_device_info
*devinfo
,
525 if (devinfo
->gen
>= 6)
526 return brw_dp_desc_msg_control(devinfo
, desc
);
528 return GET_BITS(desc
, 11, 8);
532 brw_dp_write_desc_last_render_target(const struct gen_device_info
*devinfo
,
535 if (devinfo
->gen
>= 6)
536 return GET_BITS(desc
, 12, 12);
538 return GET_BITS(desc
, 11, 11);
542 brw_dp_write_desc_write_commit(const struct gen_device_info
*devinfo
,
545 assert(devinfo
->gen
<= 6);
546 if (devinfo
->gen
>= 6)
547 return GET_BITS(desc
, 17, 17);
549 return GET_BITS(desc
, 15, 15);
553 * Construct a message descriptor immediate with the specified dataport
554 * surface function controls.
556 static inline uint32_t
557 brw_dp_surface_desc(const struct gen_device_info
*devinfo
,
559 unsigned msg_control
)
561 assert(devinfo
->gen
>= 7);
562 /* We'll OR in the binding table index later */
563 return brw_dp_desc(devinfo
, 0, msg_type
, msg_control
);
566 static inline uint32_t
567 brw_dp_untyped_atomic_desc(const struct gen_device_info
*devinfo
,
568 unsigned exec_size
, /**< 0 for SIMD4x2 */
570 bool response_expected
)
572 assert(exec_size
<= 8 || exec_size
== 16);
575 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
577 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
;
579 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
;
582 msg_type
= GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
;
585 const unsigned msg_control
=
586 SET_BITS(atomic_op
, 3, 0) |
587 SET_BITS(0 < exec_size
&& exec_size
<= 8, 4, 4) |
588 SET_BITS(response_expected
, 5, 5);
590 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
593 static inline uint32_t
594 brw_dp_untyped_atomic_float_desc(const struct gen_device_info
*devinfo
,
597 bool response_expected
)
599 assert(exec_size
<= 8 || exec_size
== 16);
600 assert(devinfo
->gen
>= 9);
602 assert(exec_size
> 0);
603 const unsigned msg_type
= GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP
;
605 const unsigned msg_control
=
606 SET_BITS(atomic_op
, 1, 0) |
607 SET_BITS(exec_size
<= 8, 4, 4) |
608 SET_BITS(response_expected
, 5, 5);
610 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
613 static inline unsigned
614 brw_mdc_cmask(unsigned num_channels
)
616 /* See also MDC_CMASK in the SKL PRM Vol 2d. */
617 return 0xf & (0xf << num_channels
);
620 static inline uint32_t
621 brw_dp_untyped_surface_rw_desc(const struct gen_device_info
*devinfo
,
622 unsigned exec_size
, /**< 0 for SIMD4x2 */
623 unsigned num_channels
,
626 assert(exec_size
<= 8 || exec_size
== 16);
630 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
631 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
;
633 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
;
637 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
638 msg_type
= HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
;
640 msg_type
= GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ
;
644 /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */
645 if (write
&& devinfo
->gen
== 7 && !devinfo
->is_haswell
&& exec_size
== 0)
648 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
649 const unsigned simd_mode
= exec_size
== 0 ? 0 : /* SIMD4x2 */
650 exec_size
<= 8 ? 2 : 1;
652 const unsigned msg_control
=
653 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
654 SET_BITS(simd_mode
, 5, 4);
656 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
659 static inline unsigned
660 brw_mdc_ds(unsigned bit_size
)
664 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE
;
666 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD
;
668 return GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD
;
670 unreachable("Unsupported bit_size for byte scattered messages");
674 static inline uint32_t
675 brw_dp_byte_scattered_rw_desc(const struct gen_device_info
*devinfo
,
680 assert(exec_size
<= 8 || exec_size
== 16);
682 assert(devinfo
->gen
> 7 || devinfo
->is_haswell
);
683 const unsigned msg_type
=
684 write
? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE
:
685 HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ
;
687 assert(exec_size
> 0);
688 const unsigned msg_control
=
689 SET_BITS(exec_size
== 16, 0, 0) |
690 SET_BITS(brw_mdc_ds(bit_size
), 3, 2);
692 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
695 static inline uint32_t
696 brw_dp_dword_scattered_rw_desc(const struct gen_device_info
*devinfo
,
700 assert(exec_size
== 8 || exec_size
== 16);
704 if (devinfo
->gen
>= 6) {
705 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
;
707 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
;
710 if (devinfo
->gen
>= 7) {
711 msg_type
= GEN7_DATAPORT_DC_DWORD_SCATTERED_READ
;
712 } else if (devinfo
->gen
> 4 || devinfo
->is_g4x
) {
713 msg_type
= G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
715 msg_type
= BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
;
719 const unsigned msg_control
=
720 SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */
721 SET_BITS(exec_size
== 16, 0, 0);
723 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
726 static inline uint32_t
727 brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info
*devinfo
,
728 unsigned exec_size
, /**< 0 for SIMD4x2 */
729 unsigned num_channels
,
732 assert(exec_size
<= 8 || exec_size
== 16);
733 assert(devinfo
->gen
>= 8);
736 write
? GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE
:
737 GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ
;
739 /* See also MDC_SM3 in the SKL PRM Vol 2d. */
740 const unsigned simd_mode
= exec_size
== 0 ? 0 : /* SIMD4x2 */
741 exec_size
<= 8 ? 2 : 1;
743 const unsigned msg_control
=
744 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
745 SET_BITS(simd_mode
, 5, 4);
747 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
751 * Calculate the data size (see MDC_A64_DS in the "Structures" volume of the
754 static inline uint32_t
755 brw_mdc_a64_ds(unsigned elems
)
763 unreachable("Unsupported elmeent count for A64 scattered message");
767 static inline uint32_t
768 brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info
*devinfo
,
769 unsigned exec_size
, /**< 0 for SIMD4x2 */
773 assert(exec_size
<= 8 || exec_size
== 16);
774 assert(devinfo
->gen
>= 8);
777 write
? GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE
:
778 GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ
;
780 const unsigned msg_control
=
781 SET_BITS(GEN8_A64_SCATTERED_SUBTYPE_BYTE
, 1, 0) |
782 SET_BITS(brw_mdc_a64_ds(bit_size
/ 8), 3, 2) |
783 SET_BITS(exec_size
== 16, 4, 4);
785 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
788 static inline uint32_t
789 brw_dp_a64_untyped_atomic_desc(const struct gen_device_info
*devinfo
,
790 ASSERTED
unsigned exec_size
, /**< 0 for SIMD4x2 */
793 bool response_expected
)
795 assert(exec_size
== 8);
796 assert(devinfo
->gen
>= 8);
797 assert(bit_size
== 32 || bit_size
== 64);
799 const unsigned msg_type
= GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP
;
801 const unsigned msg_control
=
802 SET_BITS(atomic_op
, 3, 0) |
803 SET_BITS(bit_size
== 64, 4, 4) |
804 SET_BITS(response_expected
, 5, 5);
806 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
809 static inline uint32_t
810 brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info
*devinfo
,
811 ASSERTED
unsigned exec_size
,
813 bool response_expected
)
815 assert(exec_size
== 8);
816 assert(devinfo
->gen
>= 9);
818 assert(exec_size
> 0);
819 const unsigned msg_type
= GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP
;
821 const unsigned msg_control
=
822 SET_BITS(atomic_op
, 1, 0) |
823 SET_BITS(response_expected
, 5, 5);
825 return brw_dp_desc(devinfo
, BRW_BTI_STATELESS
, msg_type
, msg_control
);
828 static inline uint32_t
829 brw_dp_typed_atomic_desc(const struct gen_device_info
*devinfo
,
833 bool response_expected
)
835 assert(exec_size
> 0 || exec_group
== 0);
836 assert(exec_group
% 8 == 0);
839 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
840 if (exec_size
== 0) {
841 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
;
843 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
;
846 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
847 assert(exec_size
> 0);
848 msg_type
= GEN7_DATAPORT_RC_TYPED_ATOMIC_OP
;
851 const bool high_sample_mask
= (exec_group
/ 8) % 2 == 1;
853 const unsigned msg_control
=
854 SET_BITS(atomic_op
, 3, 0) |
855 SET_BITS(high_sample_mask
, 4, 4) |
856 SET_BITS(response_expected
, 5, 5);
858 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
861 static inline uint32_t
862 brw_dp_typed_surface_rw_desc(const struct gen_device_info
*devinfo
,
865 unsigned num_channels
,
868 assert(exec_size
> 0 || exec_group
== 0);
869 assert(exec_group
% 8 == 0);
871 /* Typed surface reads and writes don't support SIMD16 */
872 assert(exec_size
<= 8);
876 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
877 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
;
879 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE
;
882 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
883 msg_type
= HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
;
885 msg_type
= GEN7_DATAPORT_RC_TYPED_SURFACE_READ
;
889 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
890 unsigned msg_control
;
891 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
) {
892 /* See also MDC_SG3 in the SKL PRM Vol 2d. */
893 const unsigned slot_group
= exec_size
== 0 ? 0 : /* SIMD4x2 */
894 1 + ((exec_group
/ 8) % 2);
897 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
898 SET_BITS(slot_group
, 5, 4);
900 /* SIMD4x2 typed surface R/W messages only exist on HSW+ */
901 assert(exec_size
> 0);
902 const unsigned slot_group
= ((exec_group
/ 8) % 2);
905 SET_BITS(brw_mdc_cmask(num_channels
), 3, 0) |
906 SET_BITS(slot_group
, 5, 5);
909 return brw_dp_surface_desc(devinfo
, msg_type
, msg_control
);
913 * Construct a message descriptor immediate with the specified pixel
914 * interpolator function controls.
916 static inline uint32_t
917 brw_pixel_interp_desc(UNUSED
const struct gen_device_info
*devinfo
,
923 return (SET_BITS(slot_group
, 11, 11) |
924 SET_BITS(msg_type
, 13, 12) |
925 SET_BITS(!!noperspective
, 14, 14) |
926 SET_BITS(simd_mode
, 16, 16));
929 void brw_urb_WRITE(struct brw_codegen
*p
,
933 enum brw_urb_write_flags flags
,
935 unsigned response_length
,
940 * Send message to shared unit \p sfid with a possibly indirect descriptor \p
941 * desc. If \p desc is not an immediate it will be transparently loaded to an
942 * address register using an OR instruction.
945 brw_send_indirect_message(struct brw_codegen
*p
,
948 struct brw_reg payload
,
954 brw_send_indirect_split_message(struct brw_codegen
*p
,
957 struct brw_reg payload0
,
958 struct brw_reg payload1
,
961 struct brw_reg ex_desc
,
962 unsigned ex_desc_imm
,
965 void brw_ff_sync(struct brw_codegen
*p
,
970 unsigned response_length
,
973 void brw_svb_write(struct brw_codegen
*p
,
977 unsigned binding_table_index
,
978 bool send_commit_msg
);
980 brw_inst
*brw_fb_WRITE(struct brw_codegen
*p
,
981 struct brw_reg payload
,
982 struct brw_reg implied_header
,
983 unsigned msg_control
,
984 unsigned binding_table_index
,
986 unsigned response_length
,
988 bool last_render_target
,
989 bool header_present
);
991 brw_inst
*gen9_fb_READ(struct brw_codegen
*p
,
993 struct brw_reg payload
,
994 unsigned binding_table_index
,
996 unsigned response_length
,
999 void brw_SAMPLE(struct brw_codegen
*p
,
1000 struct brw_reg dest
,
1001 unsigned msg_reg_nr
,
1002 struct brw_reg src0
,
1003 unsigned binding_table_index
,
1006 unsigned response_length
,
1007 unsigned msg_length
,
1008 unsigned header_present
,
1010 unsigned return_format
);
1012 void brw_adjust_sampler_state_pointer(struct brw_codegen
*p
,
1013 struct brw_reg header
,
1014 struct brw_reg sampler_index
);
1016 void gen4_math(struct brw_codegen
*p
,
1017 struct brw_reg dest
,
1019 unsigned msg_reg_nr
,
1021 unsigned precision
);
1023 void gen6_math(struct brw_codegen
*p
,
1024 struct brw_reg dest
,
1026 struct brw_reg src0
,
1027 struct brw_reg src1
);
1029 void brw_oword_block_read(struct brw_codegen
*p
,
1030 struct brw_reg dest
,
1033 uint32_t bind_table_index
);
1035 unsigned brw_scratch_surface_idx(const struct brw_codegen
*p
);
1037 void brw_oword_block_read_scratch(struct brw_codegen
*p
,
1038 struct brw_reg dest
,
1043 void brw_oword_block_write_scratch(struct brw_codegen
*p
,
1048 void gen7_block_read_scratch(struct brw_codegen
*p
,
1049 struct brw_reg dest
,
1053 void brw_shader_time_add(struct brw_codegen
*p
,
1054 struct brw_reg payload
,
1055 uint32_t surf_index
);
1058 * Return the generation-specific jump distance scaling factor.
1060 * Given the number of instructions to jump, we need to scale by
1061 * some number to obtain the actual jump distance to program in an
1064 static inline unsigned
1065 brw_jump_scale(const struct gen_device_info
*devinfo
)
1067 /* Broadwell measures jump targets in bytes. */
1068 if (devinfo
->gen
>= 8)
1071 /* Ironlake and later measure jump targets in 64-bit data chunks (in order
1072 * (to support compaction), so each 128-bit instruction requires 2 chunks.
1074 if (devinfo
->gen
>= 5)
1077 /* Gen4 simply uses the number of 128-bit instructions. */
1081 void brw_barrier(struct brw_codegen
*p
, struct brw_reg src
);
1083 /* If/else/endif. Works by manipulating the execution flags on each
1086 brw_inst
*brw_IF(struct brw_codegen
*p
, unsigned execute_size
);
1087 brw_inst
*gen6_IF(struct brw_codegen
*p
, enum brw_conditional_mod conditional
,
1088 struct brw_reg src0
, struct brw_reg src1
);
1090 void brw_ELSE(struct brw_codegen
*p
);
1091 void brw_ENDIF(struct brw_codegen
*p
);
1095 brw_inst
*brw_DO(struct brw_codegen
*p
, unsigned execute_size
);
1097 brw_inst
*brw_WHILE(struct brw_codegen
*p
);
1099 brw_inst
*brw_BREAK(struct brw_codegen
*p
);
1100 brw_inst
*brw_CONT(struct brw_codegen
*p
);
1101 brw_inst
*gen6_HALT(struct brw_codegen
*p
);
1105 void brw_land_fwd_jump(struct brw_codegen
*p
, int jmp_insn_idx
);
1107 brw_inst
*brw_JMPI(struct brw_codegen
*p
, struct brw_reg index
,
1108 unsigned predicate_control
);
1110 void brw_NOP(struct brw_codegen
*p
);
1112 void brw_WAIT(struct brw_codegen
*p
);
1114 void brw_SYNC(struct brw_codegen
*p
, enum tgl_sync_function func
);
1116 /* Special case: there is never a destination, execution size will be
1119 void brw_CMP(struct brw_codegen
*p
,
1120 struct brw_reg dest
,
1121 unsigned conditional
,
1122 struct brw_reg src0
,
1123 struct brw_reg src1
);
1126 brw_untyped_atomic(struct brw_codegen
*p
,
1128 struct brw_reg payload
,
1129 struct brw_reg surface
,
1131 unsigned msg_length
,
1132 bool response_expected
,
1133 bool header_present
);
1136 brw_untyped_surface_read(struct brw_codegen
*p
,
1138 struct brw_reg payload
,
1139 struct brw_reg surface
,
1140 unsigned msg_length
,
1141 unsigned num_channels
);
1144 brw_untyped_surface_write(struct brw_codegen
*p
,
1145 struct brw_reg payload
,
1146 struct brw_reg surface
,
1147 unsigned msg_length
,
1148 unsigned num_channels
,
1149 bool header_present
);
1152 brw_memory_fence(struct brw_codegen
*p
,
1155 enum opcode send_op
,
1156 enum brw_message_target sfid
,
1161 brw_pixel_interpolator_query(struct brw_codegen
*p
,
1162 struct brw_reg dest
,
1166 struct brw_reg data
,
1167 unsigned msg_length
,
1168 unsigned response_length
);
1171 brw_find_live_channel(struct brw_codegen
*p
,
1173 struct brw_reg mask
);
1176 brw_broadcast(struct brw_codegen
*p
,
1179 struct brw_reg idx
);
1182 brw_float_controls_mode(struct brw_codegen
*p
,
1183 unsigned mode
, unsigned mask
);
1185 /***********************************************************************
1189 void brw_copy_indirect_to_indirect(struct brw_codegen
*p
,
1190 struct brw_indirect dst_ptr
,
1191 struct brw_indirect src_ptr
,
1194 void brw_copy_from_indirect(struct brw_codegen
*p
,
1196 struct brw_indirect ptr
,
1199 void brw_copy4(struct brw_codegen
*p
,
1204 void brw_copy8(struct brw_codegen
*p
,
1209 void brw_math_invert( struct brw_codegen
*p
,
1211 struct brw_reg src
);
1213 void brw_set_src1(struct brw_codegen
*p
, brw_inst
*insn
, struct brw_reg reg
);
1215 void brw_set_desc_ex(struct brw_codegen
*p
, brw_inst
*insn
,
1216 unsigned desc
, unsigned ex_desc
);
1219 brw_set_desc(struct brw_codegen
*p
, brw_inst
*insn
, unsigned desc
)
1221 brw_set_desc_ex(p
, insn
, desc
, 0);
1224 void brw_set_uip_jip(struct brw_codegen
*p
, int start_offset
);
1226 enum brw_conditional_mod
brw_negate_cmod(enum brw_conditional_mod cmod
);
1227 enum brw_conditional_mod
brw_swap_cmod(enum brw_conditional_mod cmod
);
1229 /* brw_eu_compact.c */
1230 void brw_init_compaction_tables(const struct gen_device_info
*devinfo
);
1231 void brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
1232 struct disasm_info
*disasm
);
1233 void brw_uncompact_instruction(const struct gen_device_info
*devinfo
,
1234 brw_inst
*dst
, brw_compact_inst
*src
);
1235 bool brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
1236 brw_compact_inst
*dst
, const brw_inst
*src
);
1238 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
1239 brw_inst
*orig
, brw_inst
*uncompacted
);
1241 /* brw_eu_validate.c */
1242 bool brw_validate_instruction(const struct gen_device_info
*devinfo
,
1243 const brw_inst
*inst
, int offset
,
1244 struct disasm_info
*disasm
);
1245 bool brw_validate_instructions(const struct gen_device_info
*devinfo
,
1246 const void *assembly
, int start_offset
, int end_offset
,
1247 struct disasm_info
*disasm
);
1250 next_offset(const struct gen_device_info
*devinfo
, void *store
, int offset
)
1252 brw_inst
*insn
= (brw_inst
*)((char *)store
+ offset
);
1254 if (brw_inst_cmpt_control(devinfo
, insn
))
1260 struct opcode_desc
{
1269 const struct opcode_desc
*
1270 brw_opcode_desc(const struct gen_device_info
*devinfo
, enum opcode opcode
);
1272 const struct opcode_desc
*
1273 brw_opcode_desc_from_hw(const struct gen_device_info
*devinfo
, unsigned hw
);
1275 static inline unsigned
1276 brw_opcode_encode(const struct gen_device_info
*devinfo
, enum opcode opcode
)
1278 return brw_opcode_desc(devinfo
, opcode
)->hw
;
1281 static inline enum opcode
1282 brw_opcode_decode(const struct gen_device_info
*devinfo
, unsigned hw
)
1284 const struct opcode_desc
*desc
= brw_opcode_desc_from_hw(devinfo
, hw
);
1285 return desc
? (enum opcode
)desc
->ir
: BRW_OPCODE_ILLEGAL
;
1289 brw_inst_set_opcode(const struct gen_device_info
*devinfo
,
1290 brw_inst
*inst
, enum opcode opcode
)
1292 brw_inst_set_hw_opcode(devinfo
, inst
, brw_opcode_encode(devinfo
, opcode
));
1295 static inline enum opcode
1296 brw_inst_opcode(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
1298 return brw_opcode_decode(devinfo
, brw_inst_hw_opcode(devinfo
, inst
));
1302 is_3src(const struct gen_device_info
*devinfo
, enum opcode opcode
)
1304 const struct opcode_desc
*desc
= brw_opcode_desc(devinfo
, opcode
);
1305 return desc
&& desc
->nsrc
== 3;
1308 /** Maximum SEND message length */
1309 #define BRW_MAX_MSG_LENGTH 15
1311 /** First MRF register used by pull loads */
1312 #define FIRST_SPILL_MRF(gen) ((gen) == 6 ? 21 : 13)
1314 /** First MRF register used by spills */
1315 #define FIRST_PULL_LOAD_MRF(gen) ((gen) == 6 ? 16 : 13)