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24 /** @file brw_eu_compact.c
26 * Instruction compaction is a feature of G45 and newer hardware that allows
27 * for a smaller instruction encoding.
29 * The instruction cache is on the order of 32KB, and many programs generate
30 * far more instructions than that. The instruction cache is built to barely
31 * keep up with instruction dispatch ability in cache hit cases -- L1
32 * instruction cache misses that still hit in the next level could limit
33 * throughput by around 50%.
35 * The idea of instruction compaction is that most instructions use a tiny
36 * subset of the GPU functionality, so we can encode what would be a 16 byte
37 * instruction in 8 bytes using some lookup tables for various fields.
40 * Instruction compaction capabilities vary subtly by generation.
42 * G45's support for instruction compaction is very limited. Jump counts on
43 * this generation are in units of 16-byte uncompacted instructions. As such,
44 * all jump targets must be 16-byte aligned. Also, all instructions must be
45 * naturally aligned, i.e. uncompacted instructions must be 16-byte aligned.
46 * A G45-only instruction, NENOP, must be used to provide padding to align
47 * uncompacted instructions.
49 * Gen5 removes these restrictions and changes jump counts to be in units of
50 * 8-byte compacted instructions, allowing jump targets to be only 8-byte
51 * aligned. Uncompacted instructions can also be placed on 8-byte boundaries.
53 * Gen6 adds the ability to compact instructions with a limited range of
54 * immediate values. Compactable immediates have 12 unrestricted bits, and a
55 * 13th bit that's replicated through the high 20 bits, to create the 32-bit
56 * value of DW3 in the uncompacted instruction word.
58 * On Gen7 we can compact some control flow instructions with a small positive
59 * immediate in the low bits of DW3, like ENDIF with the JIP field. Other
60 * control flow instructions with UIP cannot be compacted, because of the
61 * replicated 13th bit. No control flow instructions can be compacted on Gen6
62 * since the jump count field is not in DW3.
68 * else JIP (plus UIP on BDW+)
70 * while JIP (must be negative)
72 * Gen 8 adds support for compacting 3-src instructions.
76 #include "brw_shader.h"
77 #include "intel_asm_annotation.h"
78 #include "common/gen_debug.h"
80 static const uint32_t g45_control_index_table
[32] = {
115 static const uint32_t g45_datatype_table
[32] = {
116 0b001000000000100001,
117 0b001011010110101101,
118 0b001000001000110001,
119 0b001111011110111101,
120 0b001011010110101100,
121 0b001000000110101101,
122 0b001000000000100000,
123 0b010100010110110001,
124 0b001100011000101101,
125 0b001000000000100010,
126 0b001000001000110110,
127 0b010000001000110001,
128 0b001000001000110010,
129 0b011000001000110010,
130 0b001111011110111100,
131 0b001000000100101000,
132 0b010100011000110001,
133 0b001010010100101001,
134 0b001000001000101001,
135 0b010000001000110110,
136 0b101000001000110001,
137 0b001011011000101101,
138 0b001000000100001001,
139 0b001011011000101100,
140 0b110100011000110001,
141 0b001000001110111101,
142 0b110000001000110001,
143 0b011000000100101010,
144 0b101000001000101001,
145 0b001011010110001100,
146 0b001000000110100001,
150 static const uint16_t g45_subreg_table
[32] = {
185 static const uint16_t g45_src_index_table
[32] = {
220 static const uint32_t gen6_control_index_table
[32] = {
255 static const uint32_t gen6_datatype_table
[32] = {
256 0b001001110000000000,
257 0b001000110000100000,
258 0b001001110000000001,
259 0b001000000001100000,
260 0b001010110100101001,
261 0b001000000110101101,
262 0b001100011000101100,
263 0b001011110110101101,
264 0b001000000111101100,
265 0b001000000001100001,
266 0b001000110010100101,
267 0b001000000001000001,
268 0b001000001000110001,
269 0b001000001000101001,
270 0b001000000000100000,
271 0b001000001000110010,
272 0b001010010100101001,
273 0b001011010010100101,
274 0b001000000110100101,
275 0b001100011000101001,
276 0b001011011000101100,
277 0b001011010110100101,
278 0b001011110110100101,
279 0b001111011110111101,
280 0b001111011110111100,
281 0b001111011110111101,
282 0b001111011110011101,
283 0b001111011110111110,
284 0b001000000000100001,
285 0b001000000000100010,
286 0b001001111111011101,
287 0b001000001110111110,
290 static const uint16_t gen6_subreg_table
[32] = {
325 static const uint16_t gen6_src_index_table
[32] = {
360 static const uint32_t gen7_control_index_table
[32] = {
361 0b0000000000000000010,
362 0b0000100000000000000,
363 0b0000100000000000001,
364 0b0000100000000000010,
365 0b0000100000000000011,
366 0b0000100000000000100,
367 0b0000100000000000101,
368 0b0000100000000000111,
369 0b0000100000000001000,
370 0b0000100000000001001,
371 0b0000100000000001101,
372 0b0000110000000000000,
373 0b0000110000000000001,
374 0b0000110000000000010,
375 0b0000110000000000011,
376 0b0000110000000000100,
377 0b0000110000000000101,
378 0b0000110000000000111,
379 0b0000110000000001001,
380 0b0000110000000001101,
381 0b0000110000000010000,
382 0b0000110000100000000,
383 0b0001000000000000000,
384 0b0001000000000000010,
385 0b0001000000000000100,
386 0b0001000000100000000,
387 0b0010110000000000000,
388 0b0010110000000010000,
389 0b0011000000000000000,
390 0b0011000000100000000,
391 0b0101000000000000000,
392 0b0101000000100000000
395 static const uint32_t gen7_datatype_table
[32] = {
396 0b001000000000000001,
397 0b001000000000100000,
398 0b001000000000100001,
399 0b001000000001100001,
400 0b001000000010111101,
401 0b001000001011111101,
402 0b001000001110100001,
403 0b001000001110100101,
404 0b001000001110111101,
405 0b001000010000100001,
406 0b001000110000100000,
407 0b001000110000100001,
408 0b001001010010100101,
409 0b001001110010100100,
410 0b001001110010100101,
411 0b001111001110111101,
412 0b001111011110011101,
413 0b001111011110111100,
414 0b001111011110111101,
415 0b001111111110111100,
416 0b000000001000001100,
417 0b001000000000111101,
418 0b001000000010100101,
419 0b001000010000100000,
420 0b001001010010100100,
421 0b001001110010000100,
422 0b001010010100001001,
423 0b001101111110111101,
424 0b001111111110111101,
425 0b001011110110101100,
426 0b001010010100101000,
430 static const uint16_t gen7_subreg_table
[32] = {
465 static const uint16_t gen7_src_index_table
[32] = {
500 static const uint32_t gen8_control_index_table
[32] = {
501 0b0000000000000000010,
502 0b0000100000000000000,
503 0b0000100000000000001,
504 0b0000100000000000010,
505 0b0000100000000000011,
506 0b0000100000000000100,
507 0b0000100000000000101,
508 0b0000100000000000111,
509 0b0000100000000001000,
510 0b0000100000000001001,
511 0b0000100000000001101,
512 0b0000110000000000000,
513 0b0000110000000000001,
514 0b0000110000000000010,
515 0b0000110000000000011,
516 0b0000110000000000100,
517 0b0000110000000000101,
518 0b0000110000000000111,
519 0b0000110000000001001,
520 0b0000110000000001101,
521 0b0000110000000010000,
522 0b0000110000100000000,
523 0b0001000000000000000,
524 0b0001000000000000010,
525 0b0001000000000000100,
526 0b0001000000100000000,
527 0b0010110000000000000,
528 0b0010110000000010000,
529 0b0011000000000000000,
530 0b0011000000100000000,
531 0b0101000000000000000,
532 0b0101000000100000000
535 static const uint32_t gen8_datatype_table
[32] = {
536 0b001000000000000000001,
537 0b001000000000001000000,
538 0b001000000000001000001,
539 0b001000000000011000001,
540 0b001000000000101011101,
541 0b001000000010111011101,
542 0b001000000011101000001,
543 0b001000000011101000101,
544 0b001000000011101011101,
545 0b001000001000001000001,
546 0b001000011000001000000,
547 0b001000011000001000001,
548 0b001000101000101000101,
549 0b001000111000101000100,
550 0b001000111000101000101,
551 0b001011100011101011101,
552 0b001011101011100011101,
553 0b001011101011101011100,
554 0b001011101011101011101,
555 0b001011111011101011100,
556 0b000000000010000001100,
557 0b001000000000001011101,
558 0b001000000000101000101,
559 0b001000001000001000000,
560 0b001000101000101000100,
561 0b001000111000100000100,
562 0b001001001001000001001,
563 0b001010111011101011101,
564 0b001011111011101011101,
565 0b001001111001101001100,
566 0b001001001001001001000,
567 0b001001011001001001000
570 static const uint16_t gen8_subreg_table
[32] = {
605 static const uint16_t gen8_src_index_table
[32] = {
640 /* This is actually the control index table for Cherryview (26 bits), but the
641 * only difference from Broadwell (24 bits) is that it has two extra 0-bits at
644 * The low 24 bits have the same mappings on both hardware.
646 static const uint32_t gen8_3src_control_index_table
[4] = {
647 0b00100000000110000000000001,
648 0b00000000000110000000000001,
649 0b00000000001000000000000001,
650 0b00000000001000000000100001
653 /* This is actually the control index table for Cherryview (49 bits), but the
654 * only difference from Broadwell (46 bits) is that it has three extra 0-bits
657 * The low 44 bits have the same mappings on both hardware, and since the high
658 * three bits on Broadwell are zero, we can reuse Cherryview's table.
660 static const uint64_t gen8_3src_source_index_table
[4] = {
661 0b0000001110010011100100111001000001111000000000000,
662 0b0000001110010011100100111001000001111000000000010,
663 0b0000001110010011100100111001000001111000000001000,
664 0b0000001110010011100100111001000001111000000100000
667 static const uint32_t *control_index_table
;
668 static const uint32_t *datatype_table
;
669 static const uint16_t *subreg_table
;
670 static const uint16_t *src_index_table
;
673 set_control_index(const struct gen_device_info
*devinfo
,
674 brw_compact_inst
*dst
, const brw_inst
*src
)
676 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 17b/G45; 19b/IVB+ */
677 ? (brw_inst_bits(src
, 33, 31) << 16) | /* 3b */
678 (brw_inst_bits(src
, 23, 12) << 4) | /* 12b */
679 (brw_inst_bits(src
, 10, 9) << 2) | /* 2b */
680 (brw_inst_bits(src
, 34, 34) << 1) | /* 1b */
681 (brw_inst_bits(src
, 8, 8)) /* 1b */
682 : (brw_inst_bits(src
, 31, 31) << 16) | /* 1b */
683 (brw_inst_bits(src
, 23, 8)); /* 16b */
685 /* On gen7, the flag register and subregister numbers are integrated into
688 if (devinfo
->gen
== 7)
689 uncompacted
|= brw_inst_bits(src
, 90, 89) << 17; /* 2b */
691 for (int i
= 0; i
< 32; i
++) {
692 if (control_index_table
[i
] == uncompacted
) {
693 brw_compact_inst_set_control_index(devinfo
, dst
, i
);
702 set_datatype_index(const struct gen_device_info
*devinfo
, brw_compact_inst
*dst
,
705 uint32_t uncompacted
= devinfo
->gen
>= 8 /* 18b/G45+; 21b/BDW+ */
706 ? (brw_inst_bits(src
, 63, 61) << 18) | /* 3b */
707 (brw_inst_bits(src
, 94, 89) << 12) | /* 6b */
708 (brw_inst_bits(src
, 46, 35)) /* 12b */
709 : (brw_inst_bits(src
, 63, 61) << 15) | /* 3b */
710 (brw_inst_bits(src
, 46, 32)); /* 15b */
712 for (int i
= 0; i
< 32; i
++) {
713 if (datatype_table
[i
] == uncompacted
) {
714 brw_compact_inst_set_datatype_index(devinfo
, dst
, i
);
723 set_subreg_index(const struct gen_device_info
*devinfo
, brw_compact_inst
*dst
,
724 const brw_inst
*src
, bool is_immediate
)
726 uint16_t uncompacted
= /* 15b */
727 (brw_inst_bits(src
, 52, 48) << 0) | /* 5b */
728 (brw_inst_bits(src
, 68, 64) << 5); /* 5b */
731 uncompacted
|= brw_inst_bits(src
, 100, 96) << 10; /* 5b */
733 for (int i
= 0; i
< 32; i
++) {
734 if (subreg_table
[i
] == uncompacted
) {
735 brw_compact_inst_set_subreg_index(devinfo
, dst
, i
);
744 get_src_index(uint16_t uncompacted
,
747 for (int i
= 0; i
< 32; i
++) {
748 if (src_index_table
[i
] == uncompacted
) {
758 set_src0_index(const struct gen_device_info
*devinfo
,
759 brw_compact_inst
*dst
, const brw_inst
*src
)
762 uint16_t uncompacted
= brw_inst_bits(src
, 88, 77); /* 12b */
764 if (!get_src_index(uncompacted
, &compacted
))
767 brw_compact_inst_set_src0_index(devinfo
, dst
, compacted
);
773 set_src1_index(const struct gen_device_info
*devinfo
, brw_compact_inst
*dst
,
774 const brw_inst
*src
, bool is_immediate
)
779 compacted
= (brw_inst_imm_ud(devinfo
, src
) >> 8) & 0x1f;
781 uint16_t uncompacted
= brw_inst_bits(src
, 120, 109); /* 12b */
783 if (!get_src_index(uncompacted
, &compacted
))
787 brw_compact_inst_set_src1_index(devinfo
, dst
, compacted
);
793 set_3src_control_index(const struct gen_device_info
*devinfo
,
794 brw_compact_inst
*dst
, const brw_inst
*src
)
796 assert(devinfo
->gen
>= 8);
798 uint32_t uncompacted
= /* 24b/BDW; 26b/CHV */
799 (brw_inst_bits(src
, 34, 32) << 21) | /* 3b */
800 (brw_inst_bits(src
, 28, 8)); /* 21b */
802 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
803 uncompacted
|= brw_inst_bits(src
, 36, 35) << 24; /* 2b */
805 for (unsigned i
= 0; i
< ARRAY_SIZE(gen8_3src_control_index_table
); i
++) {
806 if (gen8_3src_control_index_table
[i
] == uncompacted
) {
807 brw_compact_inst_set_3src_control_index(devinfo
, dst
, i
);
816 set_3src_source_index(const struct gen_device_info
*devinfo
,
817 brw_compact_inst
*dst
, const brw_inst
*src
)
819 assert(devinfo
->gen
>= 8);
821 uint64_t uncompacted
= /* 46b/BDW; 49b/CHV */
822 (brw_inst_bits(src
, 83, 83) << 43) | /* 1b */
823 (brw_inst_bits(src
, 114, 107) << 35) | /* 8b */
824 (brw_inst_bits(src
, 93, 86) << 27) | /* 8b */
825 (brw_inst_bits(src
, 72, 65) << 19) | /* 8b */
826 (brw_inst_bits(src
, 55, 37)); /* 19b */
828 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
830 (brw_inst_bits(src
, 126, 125) << 47) | /* 2b */
831 (brw_inst_bits(src
, 105, 104) << 45) | /* 2b */
832 (brw_inst_bits(src
, 84, 84) << 44); /* 1b */
835 (brw_inst_bits(src
, 125, 125) << 45) | /* 1b */
836 (brw_inst_bits(src
, 104, 104) << 44); /* 1b */
839 for (unsigned i
= 0; i
< ARRAY_SIZE(gen8_3src_source_index_table
); i
++) {
840 if (gen8_3src_source_index_table
[i
] == uncompacted
) {
841 brw_compact_inst_set_3src_source_index(devinfo
, dst
, i
);
850 has_unmapped_bits(const struct gen_device_info
*devinfo
, const brw_inst
*src
)
852 /* EOT can only be mapped on a send if the src1 is an immediate */
853 if ((brw_inst_opcode(devinfo
, src
) == BRW_OPCODE_SENDC
||
854 brw_inst_opcode(devinfo
, src
) == BRW_OPCODE_SEND
) &&
855 brw_inst_eot(devinfo
, src
))
858 /* Check for instruction bits that don't map to any of the fields of the
859 * compacted instruction. The instruction cannot be compacted if any of
860 * them are set. They overlap with:
861 * - NibCtrl (bit 47 on Gen7, bit 11 on Gen8)
862 * - Dst.AddrImm[9] (bit 47 on Gen8)
863 * - Src0.AddrImm[9] (bit 95 on Gen8)
864 * - Imm64[27:31] (bits 91-95 on Gen7, bit 95 on Gen8)
865 * - UIP[31] (bit 95 on Gen8)
867 if (devinfo
->gen
>= 8) {
868 assert(!brw_inst_bits(src
, 7, 7));
869 return brw_inst_bits(src
, 95, 95) ||
870 brw_inst_bits(src
, 47, 47) ||
871 brw_inst_bits(src
, 11, 11);
873 assert(!brw_inst_bits(src
, 7, 7) &&
874 !(devinfo
->gen
< 7 && brw_inst_bits(src
, 90, 90)));
875 return brw_inst_bits(src
, 95, 91) ||
876 brw_inst_bits(src
, 47, 47);
881 has_3src_unmapped_bits(const struct gen_device_info
*devinfo
,
884 /* Check for three-source instruction bits that don't map to any of the
885 * fields of the compacted instruction. All of them seem to be reserved
888 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
889 assert(!brw_inst_bits(src
, 127, 127) &&
890 !brw_inst_bits(src
, 7, 7));
892 assert(devinfo
->gen
>= 8);
893 assert(!brw_inst_bits(src
, 127, 126) &&
894 !brw_inst_bits(src
, 105, 105) &&
895 !brw_inst_bits(src
, 84, 84) &&
896 !brw_inst_bits(src
, 36, 35) &&
897 !brw_inst_bits(src
, 7, 7));
904 brw_try_compact_3src_instruction(const struct gen_device_info
*devinfo
,
905 brw_compact_inst
*dst
, const brw_inst
*src
)
907 assert(devinfo
->gen
>= 8);
909 if (has_3src_unmapped_bits(devinfo
, src
))
912 #define compact(field) \
913 brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_##field(devinfo, src))
917 if (!set_3src_control_index(devinfo
, dst
, src
))
920 if (!set_3src_source_index(devinfo
, dst
, src
))
924 compact(src0_rep_ctrl
);
925 brw_compact_inst_set_3src_cmpt_control(devinfo
, dst
, true);
926 compact(debug_control
);
928 compact(src1_rep_ctrl
);
929 compact(src2_rep_ctrl
);
930 compact(src0_reg_nr
);
931 compact(src1_reg_nr
);
932 compact(src2_reg_nr
);
933 compact(src0_subreg_nr
);
934 compact(src1_subreg_nr
);
935 compact(src2_subreg_nr
);
942 /* Compacted instructions have 12-bits for immediate sources, and a 13th bit
943 * that's replicated through the high 20 bits.
945 * Effectively this means we get 12-bit integers, 0.0f, and some limited uses
946 * of packed vectors as compactable immediates.
949 is_compactable_immediate(unsigned imm
)
951 /* We get the low 12 bits as-is. */
954 /* We get one bit replicated through the top 20 bits. */
955 return imm
== 0 || imm
== 0xfffff000;
959 * Applies some small changes to instruction types to increase chances of
963 precompact(const struct gen_device_info
*devinfo
, brw_inst inst
)
965 if (brw_inst_src0_reg_file(devinfo
, &inst
) != BRW_IMMEDIATE_VALUE
)
968 /* The Bspec's section titled "Non-present Operands" claims that if src0
969 * is an immediate that src1's type must be the same as that of src0.
971 * The SNB+ DataTypeIndex instruction compaction tables contain mappings
972 * that do not follow this rule. E.g., from the IVB/HSW table:
974 * DataTypeIndex 18-Bit Mapping Mapped Meaning
975 * 3 001000001011111101 r:f | i:vf | a:ud | <1> | dir |
977 * And from the SNB table:
979 * DataTypeIndex 18-Bit Mapping Mapped Meaning
980 * 8 001000000111101100 a:w | i:w | a:ud | <1> | dir |
982 * Neither of these cause warnings from the simulator when used,
983 * compacted or otherwise. In fact, all compaction mappings that have an
984 * immediate in src0 use a:ud for src1.
986 * The GM45 instruction compaction tables do not contain mapped meanings
987 * so it's not clear whether it has the restriction. We'll assume it was
988 * lifted on SNB. (FINISHME: decode the GM45 tables and check.)
990 * Don't do any of this for 64-bit immediates, since the src1 fields
991 * overlap with the immediate and setting them would overwrite the
994 if (devinfo
->gen
>= 6 &&
995 !(devinfo
->is_haswell
&&
996 brw_inst_opcode(devinfo
, &inst
) == BRW_OPCODE_DIM
) &&
997 !(devinfo
->gen
>= 8 &&
998 (brw_inst_src0_reg_type(devinfo
, &inst
) == GEN8_HW_REG_IMM_TYPE_DF
||
999 brw_inst_src0_reg_type(devinfo
, &inst
) == GEN8_HW_REG_TYPE_UQ
||
1000 brw_inst_src0_reg_type(devinfo
, &inst
) == GEN8_HW_REG_TYPE_Q
))) {
1001 brw_inst_set_src1_reg_type(devinfo
, &inst
, BRW_HW_REG_TYPE_UD
);
1004 /* Compacted instructions only have 12-bits (plus 1 for the other 20)
1005 * for immediate values. Presumably the hardware engineers realized
1006 * that the only useful floating-point value that could be represented
1007 * in this format is 0.0, which can also be represented as a VF-typed
1008 * immediate, so they gave us the previously mentioned mapping on IVB+.
1010 * Strangely, we do have a mapping for imm:f in src1, so we don't need
1013 * If we see a 0.0:F, change the type to VF so that it can be compacted.
1015 if (brw_inst_imm_ud(devinfo
, &inst
) == 0x0 &&
1016 brw_inst_src0_reg_type(devinfo
, &inst
) == BRW_HW_REG_TYPE_F
&&
1017 brw_inst_dst_reg_type(devinfo
, &inst
) == BRW_HW_REG_TYPE_F
&&
1018 brw_inst_dst_hstride(devinfo
, &inst
) == BRW_HORIZONTAL_STRIDE_1
) {
1019 brw_inst_set_src0_reg_type(devinfo
, &inst
, BRW_HW_REG_IMM_TYPE_VF
);
1022 /* There are no mappings for dst:d | i:d, so if the immediate is suitable
1023 * set the types to :UD so the instruction can be compacted.
1025 if (is_compactable_immediate(brw_inst_imm_ud(devinfo
, &inst
)) &&
1026 brw_inst_cond_modifier(devinfo
, &inst
) == BRW_CONDITIONAL_NONE
&&
1027 brw_inst_src0_reg_type(devinfo
, &inst
) == BRW_HW_REG_TYPE_D
&&
1028 brw_inst_dst_reg_type(devinfo
, &inst
) == BRW_HW_REG_TYPE_D
) {
1029 brw_inst_set_src0_reg_type(devinfo
, &inst
, BRW_HW_REG_TYPE_UD
);
1030 brw_inst_set_dst_reg_type(devinfo
, &inst
, BRW_HW_REG_TYPE_UD
);
1037 * Tries to compact instruction src into dst.
1039 * It doesn't modify dst unless src is compactable, which is relied on by
1040 * brw_compact_instructions().
1043 brw_try_compact_instruction(const struct gen_device_info
*devinfo
,
1044 brw_compact_inst
*dst
, const brw_inst
*src
)
1046 brw_compact_inst temp
;
1048 assert(brw_inst_cmpt_control(devinfo
, src
) == 0);
1050 if (is_3src(devinfo
, brw_inst_opcode(devinfo
, src
))) {
1051 if (devinfo
->gen
>= 8) {
1052 memset(&temp
, 0, sizeof(temp
));
1053 if (brw_try_compact_3src_instruction(devinfo
, &temp
, src
)) {
1065 brw_inst_src0_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
||
1066 brw_inst_src1_reg_file(devinfo
, src
) == BRW_IMMEDIATE_VALUE
;
1068 (devinfo
->gen
< 6 ||
1069 !is_compactable_immediate(brw_inst_imm_ud(devinfo
, src
)))) {
1073 if (has_unmapped_bits(devinfo
, src
))
1076 memset(&temp
, 0, sizeof(temp
));
1078 #define compact(field) \
1079 brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
1082 compact(debug_control
);
1084 if (!set_control_index(devinfo
, &temp
, src
))
1086 if (!set_datatype_index(devinfo
, &temp
, src
))
1088 if (!set_subreg_index(devinfo
, &temp
, src
, is_immediate
))
1091 if (devinfo
->gen
>= 6) {
1092 compact(acc_wr_control
);
1094 compact(mask_control_ex
);
1097 compact(cond_modifier
);
1099 if (devinfo
->gen
<= 6)
1100 compact(flag_subreg_nr
);
1102 brw_compact_inst_set_cmpt_control(devinfo
, &temp
, true);
1104 if (!set_src0_index(devinfo
, &temp
, src
))
1106 if (!set_src1_index(devinfo
, &temp
, src
, is_immediate
))
1109 brw_compact_inst_set_dst_reg_nr(devinfo
, &temp
,
1110 brw_inst_dst_da_reg_nr(devinfo
, src
));
1111 brw_compact_inst_set_src0_reg_nr(devinfo
, &temp
,
1112 brw_inst_src0_da_reg_nr(devinfo
, src
));
1115 brw_compact_inst_set_src1_reg_nr(devinfo
, &temp
,
1116 brw_inst_imm_ud(devinfo
, src
) & 0xff);
1118 brw_compact_inst_set_src1_reg_nr(devinfo
, &temp
,
1119 brw_inst_src1_da_reg_nr(devinfo
, src
));
1130 set_uncompacted_control(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1131 brw_compact_inst
*src
)
1133 uint32_t uncompacted
=
1134 control_index_table
[brw_compact_inst_control_index(devinfo
, src
)];
1136 if (devinfo
->gen
>= 8) {
1137 brw_inst_set_bits(dst
, 33, 31, (uncompacted
>> 16));
1138 brw_inst_set_bits(dst
, 23, 12, (uncompacted
>> 4) & 0xfff);
1139 brw_inst_set_bits(dst
, 10, 9, (uncompacted
>> 2) & 0x3);
1140 brw_inst_set_bits(dst
, 34, 34, (uncompacted
>> 1) & 0x1);
1141 brw_inst_set_bits(dst
, 8, 8, (uncompacted
>> 0) & 0x1);
1143 brw_inst_set_bits(dst
, 31, 31, (uncompacted
>> 16) & 0x1);
1144 brw_inst_set_bits(dst
, 23, 8, (uncompacted
& 0xffff));
1146 if (devinfo
->gen
== 7)
1147 brw_inst_set_bits(dst
, 90, 89, uncompacted
>> 17);
1152 set_uncompacted_datatype(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1153 brw_compact_inst
*src
)
1155 uint32_t uncompacted
=
1156 datatype_table
[brw_compact_inst_datatype_index(devinfo
, src
)];
1158 if (devinfo
->gen
>= 8) {
1159 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 18));
1160 brw_inst_set_bits(dst
, 94, 89, (uncompacted
>> 12) & 0x3f);
1161 brw_inst_set_bits(dst
, 46, 35, (uncompacted
>> 0) & 0xfff);
1163 brw_inst_set_bits(dst
, 63, 61, (uncompacted
>> 15));
1164 brw_inst_set_bits(dst
, 46, 32, (uncompacted
& 0x7fff));
1169 set_uncompacted_subreg(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1170 brw_compact_inst
*src
)
1172 uint16_t uncompacted
=
1173 subreg_table
[brw_compact_inst_subreg_index(devinfo
, src
)];
1175 brw_inst_set_bits(dst
, 100, 96, (uncompacted
>> 10));
1176 brw_inst_set_bits(dst
, 68, 64, (uncompacted
>> 5) & 0x1f);
1177 brw_inst_set_bits(dst
, 52, 48, (uncompacted
>> 0) & 0x1f);
1181 set_uncompacted_src0(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1182 brw_compact_inst
*src
)
1184 uint32_t compacted
= brw_compact_inst_src0_index(devinfo
, src
);
1185 uint16_t uncompacted
= src_index_table
[compacted
];
1187 brw_inst_set_bits(dst
, 88, 77, uncompacted
);
1191 set_uncompacted_src1(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1192 brw_compact_inst
*src
, bool is_immediate
)
1195 signed high5
= brw_compact_inst_src1_index(devinfo
, src
);
1196 /* Replicate top bit of src1_index into high 20 bits of the immediate. */
1197 brw_inst_set_imm_ud(devinfo
, dst
, (high5
<< 27) >> 19);
1199 uint16_t uncompacted
=
1200 src_index_table
[brw_compact_inst_src1_index(devinfo
, src
)];
1202 brw_inst_set_bits(dst
, 120, 109, uncompacted
);
1207 set_uncompacted_3src_control_index(const struct gen_device_info
*devinfo
,
1208 brw_inst
*dst
, brw_compact_inst
*src
)
1210 assert(devinfo
->gen
>= 8);
1212 uint32_t compacted
= brw_compact_inst_3src_control_index(devinfo
, src
);
1213 uint32_t uncompacted
= gen8_3src_control_index_table
[compacted
];
1215 brw_inst_set_bits(dst
, 34, 32, (uncompacted
>> 21) & 0x7);
1216 brw_inst_set_bits(dst
, 28, 8, (uncompacted
>> 0) & 0x1fffff);
1218 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
)
1219 brw_inst_set_bits(dst
, 36, 35, (uncompacted
>> 24) & 0x3);
1223 set_uncompacted_3src_source_index(const struct gen_device_info
*devinfo
,
1224 brw_inst
*dst
, brw_compact_inst
*src
)
1226 assert(devinfo
->gen
>= 8);
1228 uint32_t compacted
= brw_compact_inst_3src_source_index(devinfo
, src
);
1229 uint64_t uncompacted
= gen8_3src_source_index_table
[compacted
];
1231 brw_inst_set_bits(dst
, 83, 83, (uncompacted
>> 43) & 0x1);
1232 brw_inst_set_bits(dst
, 114, 107, (uncompacted
>> 35) & 0xff);
1233 brw_inst_set_bits(dst
, 93, 86, (uncompacted
>> 27) & 0xff);
1234 brw_inst_set_bits(dst
, 72, 65, (uncompacted
>> 19) & 0xff);
1235 brw_inst_set_bits(dst
, 55, 37, (uncompacted
>> 0) & 0x7ffff);
1237 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
1238 brw_inst_set_bits(dst
, 126, 125, (uncompacted
>> 47) & 0x3);
1239 brw_inst_set_bits(dst
, 105, 104, (uncompacted
>> 45) & 0x3);
1240 brw_inst_set_bits(dst
, 84, 84, (uncompacted
>> 44) & 0x1);
1242 brw_inst_set_bits(dst
, 125, 125, (uncompacted
>> 45) & 0x1);
1243 brw_inst_set_bits(dst
, 104, 104, (uncompacted
>> 44) & 0x1);
1248 brw_uncompact_3src_instruction(const struct gen_device_info
*devinfo
,
1249 brw_inst
*dst
, brw_compact_inst
*src
)
1251 assert(devinfo
->gen
>= 8);
1253 #define uncompact(field) \
1254 brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
1258 set_uncompacted_3src_control_index(devinfo
, dst
, src
);
1259 set_uncompacted_3src_source_index(devinfo
, dst
, src
);
1261 uncompact(dst_reg_nr
);
1262 uncompact(src0_rep_ctrl
);
1263 brw_inst_set_3src_cmpt_control(devinfo
, dst
, false);
1264 uncompact(debug_control
);
1265 uncompact(saturate
);
1266 uncompact(src1_rep_ctrl
);
1267 uncompact(src2_rep_ctrl
);
1268 uncompact(src0_reg_nr
);
1269 uncompact(src1_reg_nr
);
1270 uncompact(src2_reg_nr
);
1271 uncompact(src0_subreg_nr
);
1272 uncompact(src1_subreg_nr
);
1273 uncompact(src2_subreg_nr
);
1279 brw_uncompact_instruction(const struct gen_device_info
*devinfo
, brw_inst
*dst
,
1280 brw_compact_inst
*src
)
1282 memset(dst
, 0, sizeof(*dst
));
1284 if (devinfo
->gen
>= 8 &&
1285 is_3src(devinfo
, brw_compact_inst_3src_opcode(devinfo
, src
))) {
1286 brw_uncompact_3src_instruction(devinfo
, dst
, src
);
1290 #define uncompact(field) \
1291 brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
1294 uncompact(debug_control
);
1296 set_uncompacted_control(devinfo
, dst
, src
);
1297 set_uncompacted_datatype(devinfo
, dst
, src
);
1299 /* src0/1 register file fields are in the datatype table. */
1300 bool is_immediate
= brw_inst_src0_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
||
1301 brw_inst_src1_reg_file(devinfo
, dst
) == BRW_IMMEDIATE_VALUE
;
1303 set_uncompacted_subreg(devinfo
, dst
, src
);
1305 if (devinfo
->gen
>= 6) {
1306 uncompact(acc_wr_control
);
1308 uncompact(mask_control_ex
);
1311 uncompact(cond_modifier
);
1313 if (devinfo
->gen
<= 6)
1314 uncompact(flag_subreg_nr
);
1316 set_uncompacted_src0(devinfo
, dst
, src
);
1317 set_uncompacted_src1(devinfo
, dst
, src
, is_immediate
);
1319 brw_inst_set_dst_da_reg_nr(devinfo
, dst
,
1320 brw_compact_inst_dst_reg_nr(devinfo
, src
));
1321 brw_inst_set_src0_da_reg_nr(devinfo
, dst
,
1322 brw_compact_inst_src0_reg_nr(devinfo
, src
));
1325 brw_inst_set_imm_ud(devinfo
, dst
,
1326 brw_inst_imm_ud(devinfo
, dst
) |
1327 brw_compact_inst_src1_reg_nr(devinfo
, src
));
1329 brw_inst_set_src1_da_reg_nr(devinfo
, dst
,
1330 brw_compact_inst_src1_reg_nr(devinfo
, src
));
1336 void brw_debug_compact_uncompact(const struct gen_device_info
*devinfo
,
1338 brw_inst
*uncompacted
)
1340 fprintf(stderr
, "Instruction compact/uncompact changed (gen%d):\n",
1343 fprintf(stderr
, " before: ");
1344 brw_disassemble_inst(stderr
, devinfo
, orig
, true);
1346 fprintf(stderr
, " after: ");
1347 brw_disassemble_inst(stderr
, devinfo
, uncompacted
, false);
1349 uint32_t *before_bits
= (uint32_t *)orig
;
1350 uint32_t *after_bits
= (uint32_t *)uncompacted
;
1351 fprintf(stderr
, " changed bits:\n");
1352 for (int i
= 0; i
< 128; i
++) {
1353 uint32_t before
= before_bits
[i
/ 32] & (1 << (i
& 31));
1354 uint32_t after
= after_bits
[i
/ 32] & (1 << (i
& 31));
1356 if (before
!= after
) {
1357 fprintf(stderr
, " bit %d, %s to %s\n", i
,
1358 before
? "set" : "unset",
1359 after
? "set" : "unset");
1365 compacted_between(int old_ip
, int old_target_ip
, int *compacted_counts
)
1367 int this_compacted_count
= compacted_counts
[old_ip
];
1368 int target_compacted_count
= compacted_counts
[old_target_ip
];
1369 return target_compacted_count
- this_compacted_count
;
1373 update_uip_jip(const struct gen_device_info
*devinfo
, brw_inst
*insn
,
1374 int this_old_ip
, int *compacted_counts
)
1376 /* JIP and UIP are in units of:
1377 * - bytes on Gen8+; and
1378 * - compacted instructions on Gen6+.
1380 int shift
= devinfo
->gen
>= 8 ? 3 : 0;
1382 int32_t jip_compacted
= brw_inst_jip(devinfo
, insn
) >> shift
;
1383 jip_compacted
-= compacted_between(this_old_ip
,
1384 this_old_ip
+ (jip_compacted
/ 2),
1386 brw_inst_set_jip(devinfo
, insn
, jip_compacted
<< shift
);
1388 if (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ENDIF
||
1389 brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_WHILE
||
1390 (brw_inst_opcode(devinfo
, insn
) == BRW_OPCODE_ELSE
&& devinfo
->gen
<= 7))
1393 int32_t uip_compacted
= brw_inst_uip(devinfo
, insn
) >> shift
;
1394 uip_compacted
-= compacted_between(this_old_ip
,
1395 this_old_ip
+ (uip_compacted
/ 2),
1397 brw_inst_set_uip(devinfo
, insn
, uip_compacted
<< shift
);
1401 update_gen4_jump_count(const struct gen_device_info
*devinfo
, brw_inst
*insn
,
1402 int this_old_ip
, int *compacted_counts
)
1404 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
);
1406 /* Jump Count is in units of:
1407 * - uncompacted instructions on G45; and
1408 * - compacted instructions on Gen5.
1410 int shift
= devinfo
->is_g4x
? 1 : 0;
1412 int jump_count_compacted
= brw_inst_gen4_jump_count(devinfo
, insn
) << shift
;
1414 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1416 int this_compacted_count
= compacted_counts
[this_old_ip
];
1417 int target_compacted_count
= compacted_counts
[target_old_ip
];
1419 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1420 brw_inst_set_gen4_jump_count(devinfo
, insn
, jump_count_compacted
>> shift
);
1424 brw_init_compaction_tables(const struct gen_device_info
*devinfo
)
1426 assert(g45_control_index_table
[ARRAY_SIZE(g45_control_index_table
) - 1] != 0);
1427 assert(g45_datatype_table
[ARRAY_SIZE(g45_datatype_table
) - 1] != 0);
1428 assert(g45_subreg_table
[ARRAY_SIZE(g45_subreg_table
) - 1] != 0);
1429 assert(g45_src_index_table
[ARRAY_SIZE(g45_src_index_table
) - 1] != 0);
1430 assert(gen6_control_index_table
[ARRAY_SIZE(gen6_control_index_table
) - 1] != 0);
1431 assert(gen6_datatype_table
[ARRAY_SIZE(gen6_datatype_table
) - 1] != 0);
1432 assert(gen6_subreg_table
[ARRAY_SIZE(gen6_subreg_table
) - 1] != 0);
1433 assert(gen6_src_index_table
[ARRAY_SIZE(gen6_src_index_table
) - 1] != 0);
1434 assert(gen7_control_index_table
[ARRAY_SIZE(gen7_control_index_table
) - 1] != 0);
1435 assert(gen7_datatype_table
[ARRAY_SIZE(gen7_datatype_table
) - 1] != 0);
1436 assert(gen7_subreg_table
[ARRAY_SIZE(gen7_subreg_table
) - 1] != 0);
1437 assert(gen7_src_index_table
[ARRAY_SIZE(gen7_src_index_table
) - 1] != 0);
1438 assert(gen8_control_index_table
[ARRAY_SIZE(gen8_control_index_table
) - 1] != 0);
1439 assert(gen8_datatype_table
[ARRAY_SIZE(gen8_datatype_table
) - 1] != 0);
1440 assert(gen8_subreg_table
[ARRAY_SIZE(gen8_subreg_table
) - 1] != 0);
1441 assert(gen8_src_index_table
[ARRAY_SIZE(gen8_src_index_table
) - 1] != 0);
1443 switch (devinfo
->gen
) {
1447 control_index_table
= gen8_control_index_table
;
1448 datatype_table
= gen8_datatype_table
;
1449 subreg_table
= gen8_subreg_table
;
1450 src_index_table
= gen8_src_index_table
;
1453 control_index_table
= gen7_control_index_table
;
1454 datatype_table
= gen7_datatype_table
;
1455 subreg_table
= gen7_subreg_table
;
1456 src_index_table
= gen7_src_index_table
;
1459 control_index_table
= gen6_control_index_table
;
1460 datatype_table
= gen6_datatype_table
;
1461 subreg_table
= gen6_subreg_table
;
1462 src_index_table
= gen6_src_index_table
;
1466 control_index_table
= g45_control_index_table
;
1467 datatype_table
= g45_datatype_table
;
1468 subreg_table
= g45_subreg_table
;
1469 src_index_table
= g45_src_index_table
;
1472 unreachable("unknown generation");
1477 brw_compact_instructions(struct brw_codegen
*p
, int start_offset
,
1478 int num_annotations
, struct annotation
*annotation
)
1480 if (unlikely(INTEL_DEBUG
& DEBUG_NO_COMPACTION
))
1483 const struct gen_device_info
*devinfo
= p
->devinfo
;
1484 void *store
= p
->store
+ start_offset
/ 16;
1485 /* For an instruction at byte offset 16*i before compaction, this is the
1486 * number of compacted instructions minus the number of padding NOP/NENOPs
1489 int compacted_counts
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_inst
)];
1490 /* For an instruction at byte offset 8*i after compaction, this was its IP
1491 * (in 16-byte units) before compaction.
1493 int old_ip
[(p
->next_insn_offset
- start_offset
) / sizeof(brw_compact_inst
)];
1495 if (devinfo
->gen
== 4 && !devinfo
->is_g4x
)
1499 int compacted_count
= 0;
1500 for (int src_offset
= 0; src_offset
< p
->next_insn_offset
- start_offset
;
1501 src_offset
+= sizeof(brw_inst
)) {
1502 brw_inst
*src
= store
+ src_offset
;
1503 void *dst
= store
+ offset
;
1505 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1506 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1508 brw_inst inst
= precompact(devinfo
, *src
);
1509 brw_inst saved
= inst
;
1511 if (brw_try_compact_instruction(devinfo
, dst
, &inst
)) {
1515 brw_inst uncompacted
;
1516 brw_uncompact_instruction(devinfo
, &uncompacted
, dst
);
1517 if (memcmp(&saved
, &uncompacted
, sizeof(uncompacted
))) {
1518 brw_debug_compact_uncompact(devinfo
, &saved
, &uncompacted
);
1522 offset
+= sizeof(brw_compact_inst
);
1524 /* All uncompacted instructions need to be aligned on G45. */
1525 if ((offset
& sizeof(brw_compact_inst
)) != 0 && devinfo
->is_g4x
){
1526 brw_compact_inst
*align
= store
+ offset
;
1527 memset(align
, 0, sizeof(*align
));
1528 brw_compact_inst_set_opcode(devinfo
, align
, BRW_OPCODE_NENOP
);
1529 brw_compact_inst_set_cmpt_control(devinfo
, align
, true);
1530 offset
+= sizeof(brw_compact_inst
);
1532 compacted_counts
[src_offset
/ sizeof(brw_inst
)] = compacted_count
;
1533 old_ip
[offset
/ sizeof(brw_compact_inst
)] = src_offset
/ sizeof(brw_inst
);
1535 dst
= store
+ offset
;
1538 /* If we didn't compact this intruction, we need to move it down into
1541 if (offset
!= src_offset
) {
1542 memmove(dst
, src
, sizeof(brw_inst
));
1544 offset
+= sizeof(brw_inst
);
1548 /* Fix up control flow offsets. */
1549 p
->next_insn_offset
= start_offset
+ offset
;
1550 for (offset
= 0; offset
< p
->next_insn_offset
- start_offset
;
1551 offset
= next_offset(devinfo
, store
, offset
)) {
1552 brw_inst
*insn
= store
+ offset
;
1553 int this_old_ip
= old_ip
[offset
/ sizeof(brw_compact_inst
)];
1554 int this_compacted_count
= compacted_counts
[this_old_ip
];
1556 switch (brw_inst_opcode(devinfo
, insn
)) {
1557 case BRW_OPCODE_BREAK
:
1558 case BRW_OPCODE_CONTINUE
:
1559 case BRW_OPCODE_HALT
:
1560 if (devinfo
->gen
>= 6) {
1561 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1563 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1569 case BRW_OPCODE_IFF
:
1570 case BRW_OPCODE_ELSE
:
1571 case BRW_OPCODE_ENDIF
:
1572 case BRW_OPCODE_WHILE
:
1573 if (devinfo
->gen
>= 7) {
1574 if (brw_inst_cmpt_control(devinfo
, insn
)) {
1575 brw_inst uncompacted
;
1576 brw_uncompact_instruction(devinfo
, &uncompacted
,
1577 (brw_compact_inst
*)insn
);
1579 update_uip_jip(devinfo
, &uncompacted
, this_old_ip
,
1582 bool ret
= brw_try_compact_instruction(devinfo
,
1583 (brw_compact_inst
*)insn
,
1585 assert(ret
); (void)ret
;
1587 update_uip_jip(devinfo
, insn
, this_old_ip
, compacted_counts
);
1589 } else if (devinfo
->gen
== 6) {
1590 assert(!brw_inst_cmpt_control(devinfo
, insn
));
1592 /* Jump Count is in units of compacted instructions on Gen6. */
1593 int jump_count_compacted
= brw_inst_gen6_jump_count(devinfo
, insn
);
1595 int target_old_ip
= this_old_ip
+ (jump_count_compacted
/ 2);
1596 int target_compacted_count
= compacted_counts
[target_old_ip
];
1597 jump_count_compacted
-= (target_compacted_count
- this_compacted_count
);
1598 brw_inst_set_gen6_jump_count(devinfo
, insn
, jump_count_compacted
);
1600 update_gen4_jump_count(devinfo
, insn
, this_old_ip
,
1605 case BRW_OPCODE_ADD
:
1606 /* Add instructions modifying the IP register use an immediate src1,
1607 * and Gens that use this cannot compact instructions with immediate
1610 if (brw_inst_cmpt_control(devinfo
, insn
))
1613 if (brw_inst_dst_reg_file(devinfo
, insn
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
1614 brw_inst_dst_da_reg_nr(devinfo
, insn
) == BRW_ARF_IP
) {
1615 assert(brw_inst_src1_reg_file(devinfo
, insn
) == BRW_IMMEDIATE_VALUE
);
1618 int jump_compacted
= brw_inst_imm_d(devinfo
, insn
) >> shift
;
1620 int target_old_ip
= this_old_ip
+ (jump_compacted
/ 2);
1621 int target_compacted_count
= compacted_counts
[target_old_ip
];
1622 jump_compacted
-= (target_compacted_count
- this_compacted_count
);
1623 brw_inst_set_imm_ud(devinfo
, insn
, jump_compacted
<< shift
);
1629 /* p->nr_insn is counting the number of uncompacted instructions still, so
1630 * divide. We do want to be sure there's a valid instruction in any
1631 * alignment padding, so that the next compression pass (for the FS 8/16
1632 * compile passes) parses correctly.
1634 if (p
->next_insn_offset
& sizeof(brw_compact_inst
)) {
1635 brw_compact_inst
*align
= store
+ offset
;
1636 memset(align
, 0, sizeof(*align
));
1637 brw_compact_inst_set_opcode(devinfo
, align
, BRW_OPCODE_NOP
);
1638 brw_compact_inst_set_cmpt_control(devinfo
, align
, true);
1639 p
->next_insn_offset
+= sizeof(brw_compact_inst
);
1641 p
->nr_insn
= p
->next_insn_offset
/ sizeof(brw_inst
);
1643 /* Update the instruction offsets for each annotation. */
1645 for (int offset
= 0, i
= 0; i
< num_annotations
; i
++) {
1646 while (start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1647 sizeof(brw_inst
) != annotation
[i
].offset
) {
1648 assert(start_offset
+ old_ip
[offset
/ sizeof(brw_compact_inst
)] *
1649 sizeof(brw_inst
) < annotation
[i
].offset
);
1650 offset
= next_offset(devinfo
, store
, offset
);
1653 annotation
[i
].offset
= start_offset
+ offset
;
1655 offset
= next_offset(devinfo
, store
, offset
);
1658 annotation
[num_annotations
].offset
= p
->next_insn_offset
;