projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
intel/nir: Stop using nir_lower_vars_to_scratch
[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include <stdint.h>
36 #include <stdlib.h>
37 #include "util/macros.h"
38
39 /* The following hunk, up-to "Execution Unit" is used by both the
40 * intel/compiler and i965 codebase. */
41
42 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
43 /* Using the GNU statement expression extension */
44 #define SET_FIELD(value, field) \
45 ({ \
46 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \
47 assert((fieldval & ~ field ## _MASK) == 0); \
48 fieldval & field ## _MASK; \
49 })
50
51 #define SET_BITS(value, high, low) \
52 ({ \
53 const uint32_t fieldval = (uint32_t)(value) << (low); \
54 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
55 fieldval & INTEL_MASK(high, low); \
56 })
57
58 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
59 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
60
61 #define _3DPRIM_POINTLIST 0x01
62 #define _3DPRIM_LINELIST 0x02
63 #define _3DPRIM_LINESTRIP 0x03
64 #define _3DPRIM_TRILIST 0x04
65 #define _3DPRIM_TRISTRIP 0x05
66 #define _3DPRIM_TRIFAN 0x06
67 #define _3DPRIM_QUADLIST 0x07
68 #define _3DPRIM_QUADSTRIP 0x08
69 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
70 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
71 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
72 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
73 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
74 #define _3DPRIM_POLYGON 0x0E
75 #define _3DPRIM_RECTLIST 0x0F
76 #define _3DPRIM_LINELOOP 0x10
77 #define _3DPRIM_POINTLIST_BF 0x11
78 #define _3DPRIM_LINESTRIP_CONT 0x12
79 #define _3DPRIM_LINESTRIP_BF 0x13
80 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
81 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
82 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
83
84 /* Bitfields for the URB_WRITE message, DW2 of message header: */
85 #define URB_WRITE_PRIM_END 0x1
86 #define URB_WRITE_PRIM_START 0x2
87 #define URB_WRITE_PRIM_TYPE_SHIFT 2
88
89 #define BRW_SPRITE_POINT_ENABLE 16
90
91 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
92 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
93
94 /* Execution Unit (EU) defines
95 */
96
97 #define BRW_ALIGN_1 0
98 #define BRW_ALIGN_16 1
99
100 #define BRW_ADDRESS_DIRECT 0
101 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
102
103 #define BRW_CHANNEL_X 0
104 #define BRW_CHANNEL_Y 1
105 #define BRW_CHANNEL_Z 2
106 #define BRW_CHANNEL_W 3
107
108 enum brw_compression {
109 BRW_COMPRESSION_NONE = 0,
110 BRW_COMPRESSION_2NDHALF = 1,
111 BRW_COMPRESSION_COMPRESSED = 2,
112 };
113
114 #define GEN6_COMPRESSION_1Q 0
115 #define GEN6_COMPRESSION_2Q 1
116 #define GEN6_COMPRESSION_3Q 2
117 #define GEN6_COMPRESSION_4Q 3
118 #define GEN6_COMPRESSION_1H 0
119 #define GEN6_COMPRESSION_2H 2
120
121 enum PACKED brw_conditional_mod {
122 BRW_CONDITIONAL_NONE = 0,
123 BRW_CONDITIONAL_Z = 1,
124 BRW_CONDITIONAL_NZ = 2,
125 BRW_CONDITIONAL_EQ = 1, /* Z */
126 BRW_CONDITIONAL_NEQ = 2, /* NZ */
127 BRW_CONDITIONAL_G = 3,
128 BRW_CONDITIONAL_GE = 4,
129 BRW_CONDITIONAL_L = 5,
130 BRW_CONDITIONAL_LE = 6,
131 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
132 BRW_CONDITIONAL_O = 8,
133 BRW_CONDITIONAL_U = 9,
134 };
135
136 #define BRW_DEBUG_NONE 0
137 #define BRW_DEBUG_BREAKPOINT 1
138
139 #define BRW_DEPENDENCY_NORMAL 0
140 #define BRW_DEPENDENCY_NOTCLEARED 1
141 #define BRW_DEPENDENCY_NOTCHECKED 2
142 #define BRW_DEPENDENCY_DISABLE 3
143
144 enum PACKED brw_execution_size {
145 BRW_EXECUTE_1 = 0,
146 BRW_EXECUTE_2 = 1,
147 BRW_EXECUTE_4 = 2,
148 BRW_EXECUTE_8 = 3,
149 BRW_EXECUTE_16 = 4,
150 BRW_EXECUTE_32 = 5,
151 };
152
153 enum PACKED brw_horizontal_stride {
154 BRW_HORIZONTAL_STRIDE_0 = 0,
155 BRW_HORIZONTAL_STRIDE_1 = 1,
156 BRW_HORIZONTAL_STRIDE_2 = 2,
157 BRW_HORIZONTAL_STRIDE_4 = 3,
158 };
159
160 enum PACKED gen10_align1_3src_src_horizontal_stride {
161 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
162 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
163 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
164 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
165 };
166
167 enum PACKED gen10_align1_3src_dst_horizontal_stride {
168 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
169 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
170 };
171
172 #define BRW_INSTRUCTION_NORMAL 0
173 #define BRW_INSTRUCTION_SATURATE 1
174
175 #define BRW_MASK_ENABLE 0
176 #define BRW_MASK_DISABLE 1
177
178 /** @{
179 *
180 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
181 * effectively the same but much simpler to think about. Now, there
182 * are two contributors ANDed together to whether channels are
183 * executed: The predication on the instruction, and the channel write
184 * enable.
185 */
186 /**
187 * This is the default value. It means that a channel's write enable is set
188 * if the per-channel IP is pointing at this instruction.
189 */
190 #define BRW_WE_NORMAL 0
191 /**
192 * This is used like BRW_MASK_DISABLE, and causes all channels to have
193 * their write enable set. Note that predication still contributes to
194 * whether the channel actually gets written.
195 */
196 #define BRW_WE_ALL 1
197 /** @} */
198
199 enum opcode {
200 /* These are the actual hardware instructions. */
201 BRW_OPCODE_ILLEGAL,
202 BRW_OPCODE_SYNC,
203 BRW_OPCODE_MOV,
204 BRW_OPCODE_SEL,
205 BRW_OPCODE_MOVI, /**< G45+ */
206 BRW_OPCODE_NOT,
207 BRW_OPCODE_AND,
208 BRW_OPCODE_OR,
209 BRW_OPCODE_XOR,
210 BRW_OPCODE_SHR,
211 BRW_OPCODE_SHL,
212 BRW_OPCODE_DIM, /**< Gen7.5 only */
213 BRW_OPCODE_SMOV, /**< Gen8+ */
214 BRW_OPCODE_ASR,
215 BRW_OPCODE_ROR, /**< Gen11+ */
216 BRW_OPCODE_ROL, /**< Gen11+ */
217 BRW_OPCODE_CMP,
218 BRW_OPCODE_CMPN,
219 BRW_OPCODE_CSEL, /**< Gen8+ */
220 BRW_OPCODE_F32TO16, /**< Gen7 only */
221 BRW_OPCODE_F16TO32, /**< Gen7 only */
222 BRW_OPCODE_BFREV, /**< Gen7+ */
223 BRW_OPCODE_BFE, /**< Gen7+ */
224 BRW_OPCODE_BFI1, /**< Gen7+ */
225 BRW_OPCODE_BFI2, /**< Gen7+ */
226 BRW_OPCODE_JMPI,
227 BRW_OPCODE_BRD, /**< Gen7+ */
228 BRW_OPCODE_IF,
229 BRW_OPCODE_IFF, /**< Pre-Gen6 */
230 BRW_OPCODE_BRC, /**< Gen7+ */
231 BRW_OPCODE_ELSE,
232 BRW_OPCODE_ENDIF,
233 BRW_OPCODE_DO, /**< Pre-Gen6 */
234 BRW_OPCODE_CASE, /**< Gen6 only */
235 BRW_OPCODE_WHILE,
236 BRW_OPCODE_BREAK,
237 BRW_OPCODE_CONTINUE,
238 BRW_OPCODE_HALT,
239 BRW_OPCODE_CALLA, /**< Gen7.5+ */
240 BRW_OPCODE_MSAVE, /**< Pre-Gen6 */
241 BRW_OPCODE_CALL, /**< Gen6+ */
242 BRW_OPCODE_MREST, /**< Pre-Gen6 */
243 BRW_OPCODE_RET, /**< Gen6+ */
244 BRW_OPCODE_PUSH, /**< Pre-Gen6 */
245 BRW_OPCODE_FORK, /**< Gen6 only */
246 BRW_OPCODE_GOTO, /**< Gen8+ */
247 BRW_OPCODE_POP, /**< Pre-Gen6 */
248 BRW_OPCODE_WAIT,
249 BRW_OPCODE_SEND,
250 BRW_OPCODE_SENDC,
251 BRW_OPCODE_SENDS, /**< Gen9+ */
252 BRW_OPCODE_SENDSC, /**< Gen9+ */
253 BRW_OPCODE_MATH, /**< Gen6+ */
254 BRW_OPCODE_ADD,
255 BRW_OPCODE_MUL,
256 BRW_OPCODE_AVG,
257 BRW_OPCODE_FRC,
258 BRW_OPCODE_RNDU,
259 BRW_OPCODE_RNDD,
260 BRW_OPCODE_RNDE,
261 BRW_OPCODE_RNDZ,
262 BRW_OPCODE_MAC,
263 BRW_OPCODE_MACH,
264 BRW_OPCODE_LZD,
265 BRW_OPCODE_FBH, /**< Gen7+ */
266 BRW_OPCODE_FBL, /**< Gen7+ */
267 BRW_OPCODE_CBIT, /**< Gen7+ */
268 BRW_OPCODE_ADDC, /**< Gen7+ */
269 BRW_OPCODE_SUBB, /**< Gen7+ */
270 BRW_OPCODE_SAD2,
271 BRW_OPCODE_SADA2,
272 BRW_OPCODE_DP4,
273 BRW_OPCODE_DPH,
274 BRW_OPCODE_DP3,
275 BRW_OPCODE_DP2,
276 BRW_OPCODE_LINE,
277 BRW_OPCODE_PLN, /**< G45+ */
278 BRW_OPCODE_MAD, /**< Gen6+ */
279 BRW_OPCODE_LRP, /**< Gen6+ */
280 BRW_OPCODE_MADM, /**< Gen8+ */
281 BRW_OPCODE_NENOP, /**< G45 only */
282 BRW_OPCODE_NOP,
283
284 NUM_BRW_OPCODES,
285
286 /* These are compiler backend opcodes that get translated into other
287 * instructions.
288 */
289 FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES,
290
291 /**
292 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
293 * individual sources instead of as a single payload blob. The
294 * position/ordering of the arguments are defined by the enum
295 * fb_write_logical_srcs.
296 */
297 FS_OPCODE_FB_WRITE_LOGICAL,
298
299 FS_OPCODE_REP_FB_WRITE,
300
301 FS_OPCODE_FB_READ,
302 FS_OPCODE_FB_READ_LOGICAL,
303
304 SHADER_OPCODE_RCP,
305 SHADER_OPCODE_RSQ,
306 SHADER_OPCODE_SQRT,
307 SHADER_OPCODE_EXP2,
308 SHADER_OPCODE_LOG2,
309 SHADER_OPCODE_POW,
310 SHADER_OPCODE_INT_QUOTIENT,
311 SHADER_OPCODE_INT_REMAINDER,
312 SHADER_OPCODE_SIN,
313 SHADER_OPCODE_COS,
314
315 /**
316 * A generic "send" opcode. The first two sources are the message
317 * descriptor and extended message descriptor respectively. The third
318 * and optional fourth sources are the message payload
319 */
320 SHADER_OPCODE_SEND,
321
322 /**
323 * An "undefined" write which does nothing but indicates to liveness that
324 * we don't care about any values in the register which predate this
325 * instruction. Used to prevent partial writes from causing issues with
326 * live ranges.
327 */
328 SHADER_OPCODE_UNDEF,
329
330 /**
331 * Texture sampling opcodes.
332 *
333 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
334 * opcode but instead of taking a single payload blob they expect their
335 * arguments separately as individual sources. The position/ordering of the
336 * arguments are defined by the enum tex_logical_srcs.
337 */
338 SHADER_OPCODE_TEX,
339 SHADER_OPCODE_TEX_LOGICAL,
340 SHADER_OPCODE_TXD,
341 SHADER_OPCODE_TXD_LOGICAL,
342 SHADER_OPCODE_TXF,
343 SHADER_OPCODE_TXF_LOGICAL,
344 SHADER_OPCODE_TXF_LZ,
345 SHADER_OPCODE_TXL,
346 SHADER_OPCODE_TXL_LOGICAL,
347 SHADER_OPCODE_TXL_LZ,
348 SHADER_OPCODE_TXS,
349 SHADER_OPCODE_TXS_LOGICAL,
350 FS_OPCODE_TXB,
351 FS_OPCODE_TXB_LOGICAL,
352 SHADER_OPCODE_TXF_CMS,
353 SHADER_OPCODE_TXF_CMS_LOGICAL,
354 SHADER_OPCODE_TXF_CMS_W,
355 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
356 SHADER_OPCODE_TXF_UMS,
357 SHADER_OPCODE_TXF_UMS_LOGICAL,
358 SHADER_OPCODE_TXF_MCS,
359 SHADER_OPCODE_TXF_MCS_LOGICAL,
360 SHADER_OPCODE_LOD,
361 SHADER_OPCODE_LOD_LOGICAL,
362 SHADER_OPCODE_TG4,
363 SHADER_OPCODE_TG4_LOGICAL,
364 SHADER_OPCODE_TG4_OFFSET,
365 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
366 SHADER_OPCODE_SAMPLEINFO,
367 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
368
369 SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
370
371 /**
372 * Combines multiple sources of size 1 into a larger virtual GRF.
373 * For example, parameters for a send-from-GRF message. Or, updating
374 * channels of a size 4 VGRF used to store vec4s such as texturing results.
375 *
376 * This will be lowered into MOVs from each source to consecutive offsets
377 * of the destination VGRF.
378 *
379 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
380 * but still reserves the first channel of the destination VGRF. This can be
381 * used to reserve space for, say, a message header set up by the generators.
382 */
383 SHADER_OPCODE_LOAD_PAYLOAD,
384
385 /**
386 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
387 * acts intra-channel, obtaining the final value for each channel by
388 * combining the sources values for the same channel, the first source
389 * occupying the lowest bits and the last source occupying the highest
390 * bits.
391 */
392 FS_OPCODE_PACK,
393
394 SHADER_OPCODE_SHADER_TIME_ADD,
395
396 /**
397 * Typed and untyped surface access opcodes.
398 *
399 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
400 * opcode but instead of taking a single payload blob they expect their
401 * arguments separately as individual sources:
402 *
403 * Source 0: [required] Surface coordinates.
404 * Source 1: [optional] Operation source.
405 * Source 2: [required] Surface index.
406 * Source 3: [required] Number of coordinate components (as UD immediate).
407 * Source 4: [required] Opcode-specific control immediate, same as source 2
408 * of the matching non-LOGICAL opcode.
409 */
410 VEC4_OPCODE_UNTYPED_ATOMIC,
411 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
412 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
413 VEC4_OPCODE_UNTYPED_SURFACE_READ,
414 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
415 VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
416 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
417
418 /**
419 * Untyped A64 surface access opcodes.
420 *
421 * Source 0: 64-bit address
422 * Source 1: Operational source
423 * Source 2: [required] Opcode-specific control immediate, same as source 2
424 * of the matching non-LOGICAL opcode.
425 */
426 SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
427 SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
428 SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
429 SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
430 SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
431 SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
432 SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
433
434 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
435 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
436 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
437
438 SHADER_OPCODE_RND_MODE,
439 SHADER_OPCODE_FLOAT_CONTROL_MODE,
440
441 /**
442 * Byte scattered write/read opcodes.
443 *
444 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
445 * opcode, but instead of taking a single payload blog they expect their
446 * arguments separately as individual sources, like untyped write/read.
447 */
448 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
449 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
450 SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
451 SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
452
453 /**
454 * Memory fence messages.
455 *
456 * Source 0: Must be register g0, used as header.
457 * Source 1: Immediate bool to indicate whether control is returned to the
458 * thread only after the fence has been honored.
459 * Source 2: Immediate byte indicating which memory to fence. Zero means
460 * global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
461 *
462 * Vec4 backend only uses Source 0.
463 */
464 SHADER_OPCODE_MEMORY_FENCE,
465
466 /**
467 * Scheduling-only fence.
468 *
469 * Sources can be used to force a stall until the registers in those are
470 * available. This might generate MOVs or SYNC_NOPs (Gen12+).
471 */
472 FS_OPCODE_SCHEDULING_FENCE,
473
474 SHADER_OPCODE_GEN4_SCRATCH_READ,
475 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
476 SHADER_OPCODE_GEN7_SCRATCH_READ,
477
478 /**
479 * Gen8+ SIMD8 URB Read messages.
480 */
481 SHADER_OPCODE_URB_READ_SIMD8,
482 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
483
484 SHADER_OPCODE_URB_WRITE_SIMD8,
485 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
486 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
487 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
488
489 /**
490 * Return the index of an arbitrary live channel (i.e. one of the channels
491 * enabled in the current execution mask) and assign it to the first
492 * component of the destination. Expected to be used as input for the
493 * BROADCAST pseudo-opcode.
494 */
495 SHADER_OPCODE_FIND_LIVE_CHANNEL,
496
497 /**
498 * Return the current execution mask in the specified flag subregister.
499 * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register.
500 */
501 FS_OPCODE_LOAD_LIVE_CHANNELS,
502
503 /**
504 * Pick the channel from its first source register given by the index
505 * specified as second source. Useful for variable indexing of surfaces.
506 *
507 * Note that because the result of this instruction is by definition
508 * uniform and it can always be splatted to multiple channels using a
509 * scalar regioning mode, only the first channel of the destination region
510 * is guaranteed to be updated, which implies that BROADCAST instructions
511 * should usually be marked force_writemask_all.
512 */
513 SHADER_OPCODE_BROADCAST,
514
515 /* Pick the channel from its first source register given by the index
516 * specified as second source.
517 *
518 * This is similar to the BROADCAST instruction except that it takes a
519 * dynamic index and potentially puts a different value in each output
520 * channel.
521 */
522 SHADER_OPCODE_SHUFFLE,
523
524 /* Select between src0 and src1 based on channel enables.
525 *
526 * This instruction copies src0 into the enabled channels of the
527 * destination and copies src1 into the disabled channels.
528 */
529 SHADER_OPCODE_SEL_EXEC,
530
531 /* This turns into an align16 mov from src0 to dst with a swizzle
532 * provided as an immediate in src1.
533 */
534 SHADER_OPCODE_QUAD_SWIZZLE,
535
536 /* Take every Nth element in src0 and broadcast it to the group of N
537 * channels in which it lives in the destination. The offset within the
538 * cluster is given by src1 and the cluster size is given by src2.
539 */
540 SHADER_OPCODE_CLUSTER_BROADCAST,
541
542 SHADER_OPCODE_GET_BUFFER_SIZE,
543
544 SHADER_OPCODE_INTERLOCK,
545
546 VEC4_OPCODE_MOV_BYTES,
547 VEC4_OPCODE_PACK_BYTES,
548 VEC4_OPCODE_UNPACK_UNIFORM,
549 VEC4_OPCODE_DOUBLE_TO_F32,
550 VEC4_OPCODE_DOUBLE_TO_D32,
551 VEC4_OPCODE_DOUBLE_TO_U32,
552 VEC4_OPCODE_TO_DOUBLE,
553 VEC4_OPCODE_PICK_LOW_32BIT,
554 VEC4_OPCODE_PICK_HIGH_32BIT,
555 VEC4_OPCODE_SET_LOW_32BIT,
556 VEC4_OPCODE_SET_HIGH_32BIT,
557
558 FS_OPCODE_DDX_COARSE,
559 FS_OPCODE_DDX_FINE,
560 /**
561 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
562 */
563 FS_OPCODE_DDY_COARSE,
564 FS_OPCODE_DDY_FINE,
565 FS_OPCODE_LINTERP,
566 FS_OPCODE_PIXEL_X,
567 FS_OPCODE_PIXEL_Y,
568 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
569 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
570 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
571 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
572 FS_OPCODE_DISCARD_JUMP,
573 FS_OPCODE_SET_SAMPLE_ID,
574 FS_OPCODE_PACK_HALF_2x16_SPLIT,
575 FS_OPCODE_PLACEHOLDER_HALT,
576 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
577 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
578 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
579
580 VS_OPCODE_URB_WRITE,
581 VS_OPCODE_PULL_CONSTANT_LOAD,
582 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
583 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
584
585 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
586
587 /**
588 * Write geometry shader output data to the URB.
589 *
590 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
591 * R0 to the first MRF. This allows the geometry shader to override the
592 * "Slot {0,1} Offset" fields in the message header.
593 */
594 GS_OPCODE_URB_WRITE,
595
596 /**
597 * Write geometry shader output data to the URB and request a new URB
598 * handle (gen6).
599 *
600 * This opcode doesn't do an implied move from R0 to the first MRF.
601 */
602 GS_OPCODE_URB_WRITE_ALLOCATE,
603
604 /**
605 * Terminate the geometry shader thread by doing an empty URB write.
606 *
607 * This opcode doesn't do an implied move from R0 to the first MRF. This
608 * allows the geometry shader to override the "GS Number of Output Vertices
609 * for Slot {0,1}" fields in the message header.
610 */
611 GS_OPCODE_THREAD_END,
612
613 /**
614 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
615 *
616 * - dst is the MRF containing the message header.
617 *
618 * - src0.x indicates which portion of the URB should be written to (e.g. a
619 * vertex number)
620 *
621 * - src1 is an immediate multiplier which will be applied to src0
622 * (e.g. the size of a single vertex in the URB).
623 *
624 * Note: the hardware will apply this offset *in addition to* the offset in
625 * vec4_instruction::offset.
626 */
627 GS_OPCODE_SET_WRITE_OFFSET,
628
629 /**
630 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
631 * URB_WRITE message header.
632 *
633 * - dst is the MRF containing the message header.
634 *
635 * - src0.x is the vertex count. The upper 16 bits will be ignored.
636 */
637 GS_OPCODE_SET_VERTEX_COUNT,
638
639 /**
640 * Set DWORD 2 of dst to the value in src.
641 */
642 GS_OPCODE_SET_DWORD_2,
643
644 /**
645 * Prepare the dst register for storage in the "Channel Mask" fields of a
646 * URB_WRITE message header.
647 *
648 * DWORD 4 of dst is shifted left by 4 bits, so that later,
649 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
650 * final channel mask.
651 *
652 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
653 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
654 * have any extraneous bits set prior to execution of this opcode (that is,
655 * they should be in the range 0x0 to 0xf).
656 */
657 GS_OPCODE_PREPARE_CHANNEL_MASKS,
658
659 /**
660 * Set the "Channel Mask" fields of a URB_WRITE message header.
661 *
662 * - dst is the MRF containing the message header.
663 *
664 * - src.x is the channel mask, as prepared by
665 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
666 * form the final channel mask.
667 */
668 GS_OPCODE_SET_CHANNEL_MASKS,
669
670 /**
671 * Get the "Instance ID" fields from the payload.
672 *
673 * - dst is the GRF for gl_InvocationID.
674 */
675 GS_OPCODE_GET_INSTANCE_ID,
676
677 /**
678 * Send a FF_SYNC message to allocate initial URB handles (gen6).
679 *
680 * - dst will be used as the writeback register for the FF_SYNC operation.
681 *
682 * - src0 is the number of primitives written.
683 *
684 * - src1 is the value to hold in M0.0: number of SO vertices to write
685 * and number of SO primitives needed. Its value will be overwritten
686 * with the SVBI values if transform feedback is enabled.
687 *
688 * Note: This opcode uses an implicit MRF register for the ff_sync message
689 * header, so the caller is expected to set inst->base_mrf and initialize
690 * that MRF register to r0. This opcode will also write to this MRF register
691 * to include the allocated URB handle so it can then be reused directly as
692 * the header in the URB write operation we are allocating the handle for.
693 */
694 GS_OPCODE_FF_SYNC,
695
696 /**
697 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
698 * register.
699 *
700 * - dst is the GRF where PrimitiveID information will be moved.
701 */
702 GS_OPCODE_SET_PRIMITIVE_ID,
703
704 /**
705 * Write transform feedback data to the SVB by sending a SVB WRITE message.
706 * Used in gen6.
707 *
708 * - dst is the MRF register containing the message header.
709 *
710 * - src0 is the register where the vertex data is going to be copied from.
711 *
712 * - src1 is the destination register when write commit occurs.
713 */
714 GS_OPCODE_SVB_WRITE,
715
716 /**
717 * Set destination index in the SVB write message payload (M0.5). Used
718 * in gen6 for transform feedback.
719 *
720 * - dst is the header to save the destination indices for SVB WRITE.
721 * - src is the register that holds the destination indices value.
722 */
723 GS_OPCODE_SVB_SET_DST_INDEX,
724
725 /**
726 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
727 * Used in gen6 for transform feedback.
728 *
729 * - dst will hold the register with the final Mx.0 value.
730 *
731 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
732 *
733 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
734 *
735 * - src2 is the value to hold in M0: number of SO vertices to write
736 * and number of SO primitives needed.
737 */
738 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
739
740 /**
741 * Terminate the compute shader.
742 */
743 CS_OPCODE_CS_TERMINATE,
744
745 /**
746 * GLSL barrier()
747 */
748 SHADER_OPCODE_BARRIER,
749
750 /**
751 * Calculate the high 32-bits of a 32x32 multiply.
752 */
753 SHADER_OPCODE_MULH,
754
755 /** Signed subtraction with saturation. */
756 SHADER_OPCODE_ISUB_SAT,
757
758 /** Unsigned subtraction with saturation. */
759 SHADER_OPCODE_USUB_SAT,
760
761 /**
762 * A MOV that uses VxH indirect addressing.
763 *
764 * Source 0: A register to start from (HW_REG).
765 * Source 1: An indirect offset (in bytes, UD GRF).
766 * Source 2: The length of the region that could be accessed (in bytes,
767 * UD immediate).
768 */
769 SHADER_OPCODE_MOV_INDIRECT,
770
771 /** Fills out a relocatable immediate */
772 SHADER_OPCODE_MOV_RELOC_IMM,
773
774 VEC4_OPCODE_URB_READ,
775 TCS_OPCODE_GET_INSTANCE_ID,
776 TCS_OPCODE_URB_WRITE,
777 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
778 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
779 TCS_OPCODE_GET_PRIMITIVE_ID,
780 TCS_OPCODE_CREATE_BARRIER_HEADER,
781 TCS_OPCODE_SRC0_010_IS_ZERO,
782 TCS_OPCODE_RELEASE_INPUT,
783 TCS_OPCODE_THREAD_END,
784
785 TES_OPCODE_GET_PRIMITIVE_ID,
786 TES_OPCODE_CREATE_INPUT_READ_HEADER,
787 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
788 };
789
790 enum brw_urb_write_flags {
791 BRW_URB_WRITE_NO_FLAGS = 0,
792
793 /**
794 * Causes a new URB entry to be allocated, and its address stored in the
795 * destination register (gen < 7).
796 */
797 BRW_URB_WRITE_ALLOCATE = 0x1,
798
799 /**
800 * Causes the current URB entry to be deallocated (gen < 7).
801 */
802 BRW_URB_WRITE_UNUSED = 0x2,
803
804 /**
805 * Causes the thread to terminate.
806 */
807 BRW_URB_WRITE_EOT = 0x4,
808
809 /**
810 * Indicates that the given URB entry is complete, and may be sent further
811 * down the 3D pipeline (gen < 7).
812 */
813 BRW_URB_WRITE_COMPLETE = 0x8,
814
815 /**
816 * Indicates that an additional offset (which may be different for the two
817 * vec4 slots) is stored in the message header (gen == 7).
818 */
819 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
820
821 /**
822 * Indicates that the channel masks in the URB_WRITE message header should
823 * not be overridden to 0xff (gen == 7).
824 */
825 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
826
827 /**
828 * Indicates that the data should be sent to the URB using the
829 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
830 * causes offsets to be interpreted as multiples of an OWORD instead of an
831 * HWORD, and only allows one OWORD to be written.
832 */
833 BRW_URB_WRITE_OWORD = 0x40,
834
835 /**
836 * Convenient combination of flags: end the thread while simultaneously
837 * marking the given URB entry as complete.
838 */
839 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
840
841 /**
842 * Convenient combination of flags: mark the given URB entry as complete
843 * and simultaneously allocate a new one.
844 */
845 BRW_URB_WRITE_ALLOCATE_COMPLETE =
846 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
847 };
848
849 enum fb_write_logical_srcs {
850 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
851 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
852 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
853 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
854 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
855 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
856 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
857 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
858 FB_WRITE_LOGICAL_NUM_SRCS
859 };
860
861 enum tex_logical_srcs {
862 /** Texture coordinates */
863 TEX_LOGICAL_SRC_COORDINATE,
864 /** Shadow comparator */
865 TEX_LOGICAL_SRC_SHADOW_C,
866 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
867 TEX_LOGICAL_SRC_LOD,
868 /** dPdy if the operation takes explicit derivatives */
869 TEX_LOGICAL_SRC_LOD2,
870 /** Min LOD */
871 TEX_LOGICAL_SRC_MIN_LOD,
872 /** Sample index */
873 TEX_LOGICAL_SRC_SAMPLE_INDEX,
874 /** MCS data */
875 TEX_LOGICAL_SRC_MCS,
876 /** REQUIRED: Texture surface index */
877 TEX_LOGICAL_SRC_SURFACE,
878 /** Texture sampler index */
879 TEX_LOGICAL_SRC_SAMPLER,
880 /** Texture surface bindless handle */
881 TEX_LOGICAL_SRC_SURFACE_HANDLE,
882 /** Texture sampler bindless handle */
883 TEX_LOGICAL_SRC_SAMPLER_HANDLE,
884 /** Texel offset for gathers */
885 TEX_LOGICAL_SRC_TG4_OFFSET,
886 /** REQUIRED: Number of coordinate components (as UD immediate) */
887 TEX_LOGICAL_SRC_COORD_COMPONENTS,
888 /** REQUIRED: Number of derivative components (as UD immediate) */
889 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
890
891 TEX_LOGICAL_NUM_SRCS,
892 };
893
894 enum surface_logical_srcs {
895 /** Surface binding table index */
896 SURFACE_LOGICAL_SRC_SURFACE,
897 /** Surface bindless handle */
898 SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
899 /** Surface address; could be multi-dimensional for typed opcodes */
900 SURFACE_LOGICAL_SRC_ADDRESS,
901 /** Data to be written or used in an atomic op */
902 SURFACE_LOGICAL_SRC_DATA,
903 /** Surface number of dimensions. Affects the size of ADDRESS */
904 SURFACE_LOGICAL_SRC_IMM_DIMS,
905 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */
906 SURFACE_LOGICAL_SRC_IMM_ARG,
907
908 SURFACE_LOGICAL_NUM_SRCS
909 };
910
911 #ifdef __cplusplus
912 /**
913 * Allow brw_urb_write_flags enums to be ORed together.
914 */
915 inline brw_urb_write_flags
916 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
917 {
918 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
919 static_cast<int>(y));
920 }
921 #endif
922
923 enum PACKED brw_predicate {
924 BRW_PREDICATE_NONE = 0,
925 BRW_PREDICATE_NORMAL = 1,
926 BRW_PREDICATE_ALIGN1_ANYV = 2,
927 BRW_PREDICATE_ALIGN1_ALLV = 3,
928 BRW_PREDICATE_ALIGN1_ANY2H = 4,
929 BRW_PREDICATE_ALIGN1_ALL2H = 5,
930 BRW_PREDICATE_ALIGN1_ANY4H = 6,
931 BRW_PREDICATE_ALIGN1_ALL4H = 7,
932 BRW_PREDICATE_ALIGN1_ANY8H = 8,
933 BRW_PREDICATE_ALIGN1_ALL8H = 9,
934 BRW_PREDICATE_ALIGN1_ANY16H = 10,
935 BRW_PREDICATE_ALIGN1_ALL16H = 11,
936 BRW_PREDICATE_ALIGN1_ANY32H = 12,
937 BRW_PREDICATE_ALIGN1_ALL32H = 13,
938 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
939 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
940 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
941 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
942 BRW_PREDICATE_ALIGN16_ANY4H = 6,
943 BRW_PREDICATE_ALIGN16_ALL4H = 7,
944 };
945
946 enum PACKED brw_reg_file {
947 BRW_ARCHITECTURE_REGISTER_FILE = 0,
948 BRW_GENERAL_REGISTER_FILE = 1,
949 BRW_MESSAGE_REGISTER_FILE = 2,
950 BRW_IMMEDIATE_VALUE = 3,
951
952 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
953 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
954 MRF = BRW_MESSAGE_REGISTER_FILE,
955 IMM = BRW_IMMEDIATE_VALUE,
956
957 /* These are not hardware values */
958 VGRF,
959 ATTR,
960 UNIFORM, /* prog_data->params[reg] */
961 BAD_FILE,
962 };
963
964 enum PACKED gen10_align1_3src_reg_file {
965 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
966 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
967 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
968 };
969
970 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
971 * word is "Execution Datatype" which controls whether the instruction operates
972 * on float or integer types. The register arguments have fields that offer
973 * more fine control their respective types.
974 */
975 enum PACKED gen10_align1_3src_exec_type {
976 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
977 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
978 };
979
980 #define BRW_ARF_NULL 0x00
981 #define BRW_ARF_ADDRESS 0x10
982 #define BRW_ARF_ACCUMULATOR 0x20
983 #define BRW_ARF_FLAG 0x30
984 #define BRW_ARF_MASK 0x40
985 #define BRW_ARF_MASK_STACK 0x50
986 #define BRW_ARF_MASK_STACK_DEPTH 0x60
987 #define BRW_ARF_STATE 0x70
988 #define BRW_ARF_CONTROL 0x80
989 #define BRW_ARF_NOTIFICATION_COUNT 0x90
990 #define BRW_ARF_IP 0xA0
991 #define BRW_ARF_TDR 0xB0
992 #define BRW_ARF_TIMESTAMP 0xC0
993
994 #define BRW_MRF_COMPR4 (1 << 7)
995
996 #define BRW_AMASK 0
997 #define BRW_IMASK 1
998 #define BRW_LMASK 2
999 #define BRW_CMASK 3
1000
1001
1002
1003 #define BRW_THREAD_NORMAL 0
1004 #define BRW_THREAD_ATOMIC 1
1005 #define BRW_THREAD_SWITCH 2
1006
1007 enum PACKED brw_vertical_stride {
1008 BRW_VERTICAL_STRIDE_0 = 0,
1009 BRW_VERTICAL_STRIDE_1 = 1,
1010 BRW_VERTICAL_STRIDE_2 = 2,
1011 BRW_VERTICAL_STRIDE_4 = 3,
1012 BRW_VERTICAL_STRIDE_8 = 4,
1013 BRW_VERTICAL_STRIDE_16 = 5,
1014 BRW_VERTICAL_STRIDE_32 = 6,
1015 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
1016 };
1017
1018 enum PACKED gen10_align1_3src_vertical_stride {
1019 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
1020 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
1021 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
1022 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
1023 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1024 };
1025
1026 enum PACKED brw_width {
1027 BRW_WIDTH_1 = 0,
1028 BRW_WIDTH_2 = 1,
1029 BRW_WIDTH_4 = 2,
1030 BRW_WIDTH_8 = 3,
1031 BRW_WIDTH_16 = 4,
1032 };
1033
1034 /**
1035 * Gen12+ SWSB SBID synchronization mode.
1036 *
1037 * This is represented as a bitmask including any required SBID token
1038 * synchronization modes, used to synchronize out-of-order instructions. Only
1039 * the strongest mode of the mask will be provided to the hardware in the SWSB
1040 * field of an actual hardware instruction, but virtual instructions may be
1041 * able to take into account multiple of them.
1042 */
1043 enum tgl_sbid_mode {
1044 TGL_SBID_NULL = 0,
1045 TGL_SBID_SRC = 1,
1046 TGL_SBID_DST = 2,
1047 TGL_SBID_SET = 4
1048 };
1049
1050 #ifdef __cplusplus
1051 /**
1052 * Allow bitwise arithmetic of tgl_sbid_mode enums.
1053 */
1054 inline tgl_sbid_mode
1055 operator|(tgl_sbid_mode x, tgl_sbid_mode y)
1056 {
1057 return tgl_sbid_mode(unsigned(x) | unsigned(y));
1058 }
1059
1060 inline tgl_sbid_mode
1061 operator&(tgl_sbid_mode x, tgl_sbid_mode y)
1062 {
1063 return tgl_sbid_mode(unsigned(x) & unsigned(y));
1064 }
1065
1066 inline tgl_sbid_mode &
1067 operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
1068 {
1069 return x = x | y;
1070 }
1071
1072 #endif
1073
1074 /**
1075 * Logical representation of the SWSB scheduling information of a hardware
1076 * instruction. The binary representation is slightly more compact.
1077 */
1078 struct tgl_swsb {
1079 unsigned regdist : 3;
1080 unsigned sbid : 4;
1081 enum tgl_sbid_mode mode : 3;
1082 };
1083
1084 /**
1085 * Construct a scheduling annotation with a single RegDist dependency. This
1086 * synchronizes with the completion of the d-th previous in-order instruction.
1087 * The index is one-based, zero causes a no-op tgl_swsb to be constructed.
1088 */
1089 static inline struct tgl_swsb
1090 tgl_swsb_regdist(unsigned d)
1091 {
1092 const struct tgl_swsb swsb = { d };
1093 assert(swsb.regdist == d);
1094 return swsb;
1095 }
1096
1097 /**
1098 * Construct a scheduling annotation that synchronizes with the specified SBID
1099 * token.
1100 */
1101 static inline struct tgl_swsb
1102 tgl_swsb_sbid(enum tgl_sbid_mode mode, unsigned sbid)
1103 {
1104 const struct tgl_swsb swsb = { 0, sbid, mode };
1105 assert(swsb.sbid == sbid);
1106 return swsb;
1107 }
1108
1109 /**
1110 * Construct a no-op scheduling annotation.
1111 */
1112 static inline struct tgl_swsb
1113 tgl_swsb_null(void)
1114 {
1115 return tgl_swsb_regdist(0);
1116 }
1117
1118 /**
1119 * Return a scheduling annotation that allocates the same SBID synchronization
1120 * token as \p swsb. In addition it will synchronize against a previous
1121 * in-order instruction if \p regdist is non-zero.
1122 */
1123 static inline struct tgl_swsb
1124 tgl_swsb_dst_dep(struct tgl_swsb swsb, unsigned regdist)
1125 {
1126 swsb.regdist = regdist;
1127 swsb.mode = swsb.mode & TGL_SBID_SET;
1128 return swsb;
1129 }
1130
1131 /**
1132 * Return a scheduling annotation that synchronizes against the same SBID and
1133 * RegDist dependencies as \p swsb, but doesn't allocate any SBID token.
1134 */
1135 static inline struct tgl_swsb
1136 tgl_swsb_src_dep(struct tgl_swsb swsb)
1137 {
1138 swsb.mode = swsb.mode & (TGL_SBID_SRC | TGL_SBID_DST);
1139 return swsb;
1140 }
1141
1142 /**
1143 * Convert the provided tgl_swsb to the hardware's binary representation of an
1144 * SWSB annotation.
1145 */
1146 static inline uint8_t
1147 tgl_swsb_encode(struct tgl_swsb swsb)
1148 {
1149 if (!swsb.mode) {
1150 return swsb.regdist;
1151 } else if (swsb.regdist) {
1152 return 0x80 | swsb.regdist << 4 | swsb.sbid;
1153 } else {
1154 return swsb.sbid | (swsb.mode & TGL_SBID_SET ? 0x40 :
1155 swsb.mode & TGL_SBID_DST ? 0x20 : 0x30);
1156 }
1157 }
1158
1159 /**
1160 * Convert the provided binary representation of an SWSB annotation to a
1161 * tgl_swsb.
1162 */
1163 static inline struct tgl_swsb
1164 tgl_swsb_decode(enum opcode opcode, uint8_t x)
1165 {
1166 if (x & 0x80) {
1167 const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
1168 (opcode == BRW_OPCODE_SEND ||
1169 opcode == BRW_OPCODE_SENDC ||
1170 opcode == BRW_OPCODE_MATH) ?
1171 TGL_SBID_SET : TGL_SBID_DST };
1172 return swsb;
1173 } else if ((x & 0x70) == 0x20) {
1174 return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);
1175 } else if ((x & 0x70) == 0x30) {
1176 return tgl_swsb_sbid(TGL_SBID_SRC, x & 0xfu);
1177 } else if ((x & 0x70) == 0x40) {
1178 return tgl_swsb_sbid(TGL_SBID_SET, x & 0xfu);
1179 } else {
1180 return tgl_swsb_regdist(x & 0x7u);
1181 }
1182 }
1183
1184 enum tgl_sync_function {
1185 TGL_SYNC_NOP = 0x0,
1186 TGL_SYNC_ALLRD = 0x2,
1187 TGL_SYNC_ALLWR = 0x3,
1188 TGL_SYNC_BAR = 0xe,
1189 TGL_SYNC_HOST = 0xf
1190 };
1191
1192 /**
1193 * Message target: Shared Function ID for where to SEND a message.
1194 *
1195 * These are enumerated in the ISA reference under "send - Send Message".
1196 * In particular, see the following tables:
1197 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1198 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1199 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1200 */
1201 enum brw_message_target {
1202 BRW_SFID_NULL = 0,
1203 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
1204 BRW_SFID_SAMPLER = 2,
1205 BRW_SFID_MESSAGE_GATEWAY = 3,
1206 BRW_SFID_DATAPORT_READ = 4,
1207 BRW_SFID_DATAPORT_WRITE = 5,
1208 BRW_SFID_URB = 6,
1209 BRW_SFID_THREAD_SPAWNER = 7,
1210 BRW_SFID_VME = 8,
1211
1212 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
1213 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
1214 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1215
1216 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
1217 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
1218 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
1219 HSW_SFID_CRE = 13,
1220 };
1221
1222 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
1223
1224 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
1225 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
1226 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
1227
1228 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
1229 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
1230 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
1231 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
1232 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
1233 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
1234 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
1235 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
1236 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
1237 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1238 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1239 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1240 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1241 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1242 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1243 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1244 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1245 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1246
1247 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1248 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1249 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1250 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1251 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1252 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1253 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1254 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1255 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1256 #define GEN5_SAMPLER_MESSAGE_LOD 9
1257 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1258 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
1259 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1260 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1261 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1262 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1263 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
1264 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
1265 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
1266 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
1267 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1268 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1269 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1270
1271 /* for GEN5 only */
1272 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1273 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1274 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1275 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1276
1277 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1278 * behavior by setting bit 22 of dword 2 in the message header. */
1279 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
1280 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
1281
1282 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1283 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1284 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1285 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1286 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1287 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1288 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1289 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1290 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1291 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1292 (abort(), ~0))
1293
1294 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1295 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1296
1297 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1298 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1299
1300 /* This one stays the same across generations. */
1301 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1302 /* GEN4 */
1303 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1304 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1305 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1306 /* G45, GEN5 */
1307 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1308 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1309 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1310 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1311 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1312 /* GEN6 */
1313 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1314 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1315 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1316 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1317 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1318
1319 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1320 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1321 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1322
1323 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1324 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1325 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1326 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1327 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1328
1329 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1330 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1331 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1332 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1333 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1334 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1335 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1336
1337 /* GEN6 */
1338 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1339 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1340 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1341 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1342 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1343 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1344 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1345 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1346
1347 /* GEN7 */
1348 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1349 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1350 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1351 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1352 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1353 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1354 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1355 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1356 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1357 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1358 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1359 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1360 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1361 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1362 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1363 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1364 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1365 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1366 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1367 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1368
1369 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1370 (0 << 17))
1371 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1372 (1 << 17))
1373 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1374
1375 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1376 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1377 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1378 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1379
1380 /* HSW */
1381 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1382 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1383 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1384 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1385 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1386 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1387 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1388 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1389 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1390 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1391
1392 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1393 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1394 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1395 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1396 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1397 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1398 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1399 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1400 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1401 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1402 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1403 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1404 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
1405 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
1406 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
1407 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
1408 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
1409 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
1410 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
1411
1412 /* GEN9 */
1413 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1414 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1415
1416 /* A64 scattered message subtype */
1417 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE 0
1418 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD 1
1419 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD 2
1420 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD 3
1421
1422 /* Dataport special binding table indices: */
1423 #define BRW_BTI_STATELESS 255
1424 #define GEN7_BTI_SLM 254
1425
1426 #define HSW_BTI_STATELESS_LOCALLY_COHERENT 255
1427 #define HSW_BTI_STATELESS_NON_COHERENT 253
1428 #define HSW_BTI_STATELESS_GLOBALLY_COHERENT 252
1429 #define HSW_BTI_STATELESS_LLC_COHERENT 251
1430 #define HSW_BTI_STATELESS_L3_UNCACHED 250
1431
1432 /* The hardware docs are a bit contradictory here. On Haswell, where they
1433 * first added cache ability control, there were 5 different cache modes (see
1434 * HSW_BTI_STATELESS_* above). On Broadwell, they reduced to two:
1435 *
1436 * - IA-Coherent (BTI=255): Coherent within Gen and coherent within the
1437 * entire IA cache memory hierarchy.
1438 *
1439 * - Non-Coherent (BTI=253): Coherent within Gen, same cache type.
1440 *
1441 * Information about stateless cache coherency can be found in the "A32
1442 * Stateless" section of the "3D Media GPGPU" volume of the PRM for each
1443 * hardware generation.
1444 *
1445 * Unfortunately, the docs for MDC_STATELESS appear to have been copied and
1446 * pasted from Haswell and give the Haswell definitions for the BTI values of
1447 * 255 and 253 including a warning about accessing 253 surfaces from multiple
1448 * threads. This seems to be a copy+paste error and the definitions from the
1449 * "A32 Stateless" section should be trusted instead.
1450 *
1451 * Note that because the DRM sets bit 4 of HDC_CHICKEN0 on BDW, CHV and at
1452 * least some pre-production steppings of SKL due to WaForceEnableNonCoherent,
1453 * HDC memory access may have been overridden by the kernel to be non-coherent
1454 * (matching the behavior of the same BTI on pre-Gen8 hardware) and BTI 255
1455 * may actually be an alias for BTI 253.
1456 */
1457 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1458 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1459 #define GEN9_BTI_BINDLESS 252
1460
1461 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1462 * (and others).
1463 */
1464 #define BRW_AOP_AND 1
1465 #define BRW_AOP_OR 2
1466 #define BRW_AOP_XOR 3
1467 #define BRW_AOP_MOV 4
1468 #define BRW_AOP_INC 5
1469 #define BRW_AOP_DEC 6
1470 #define BRW_AOP_ADD 7
1471 #define BRW_AOP_SUB 8
1472 #define BRW_AOP_REVSUB 9
1473 #define BRW_AOP_IMAX 10
1474 #define BRW_AOP_IMIN 11
1475 #define BRW_AOP_UMAX 12
1476 #define BRW_AOP_UMIN 13
1477 #define BRW_AOP_CMPWR 14
1478 #define BRW_AOP_PREDEC 15
1479
1480 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1481 #define BRW_AOP_FMAX 1
1482 #define BRW_AOP_FMIN 2
1483 #define BRW_AOP_FCMPWR 3
1484
1485 #define BRW_MATH_FUNCTION_INV 1
1486 #define BRW_MATH_FUNCTION_LOG 2
1487 #define BRW_MATH_FUNCTION_EXP 3
1488 #define BRW_MATH_FUNCTION_SQRT 4
1489 #define BRW_MATH_FUNCTION_RSQ 5
1490 #define BRW_MATH_FUNCTION_SIN 6
1491 #define BRW_MATH_FUNCTION_COS 7
1492 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1493 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1494 #define BRW_MATH_FUNCTION_POW 10
1495 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1496 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1497 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1498 #define GEN8_MATH_FUNCTION_INVM 14
1499 #define GEN8_MATH_FUNCTION_RSQRTM 15
1500
1501 #define BRW_MATH_INTEGER_UNSIGNED 0
1502 #define BRW_MATH_INTEGER_SIGNED 1
1503
1504 #define BRW_MATH_PRECISION_FULL 0
1505 #define BRW_MATH_PRECISION_PARTIAL 1
1506
1507 #define BRW_MATH_SATURATE_NONE 0
1508 #define BRW_MATH_SATURATE_SATURATE 1
1509
1510 #define BRW_MATH_DATA_VECTOR 0
1511 #define BRW_MATH_DATA_SCALAR 1
1512
1513 #define BRW_URB_OPCODE_WRITE_HWORD 0
1514 #define BRW_URB_OPCODE_WRITE_OWORD 1
1515 #define BRW_URB_OPCODE_READ_HWORD 2
1516 #define BRW_URB_OPCODE_READ_OWORD 3
1517 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1518 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1519 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1520 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1521 #define GEN8_URB_OPCODE_SIMD8_READ 8
1522
1523 #define BRW_URB_SWIZZLE_NONE 0
1524 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1525 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1526
1527 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1528 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1529 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1530 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1531 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1532 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1533 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1534 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1535 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1536 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1537 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1538 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1539
1540 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1541 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1542 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1543 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1544 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1545 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1546 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1547
1548
1549 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1550 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1551 *
1552 * Identical for VS, DS, and HS.
1553 */
1554 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1555 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1556 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1557 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1558
1559 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1560 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1561 */
1562 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1563
1564 /* GS Thread Payload
1565 */
1566
1567 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1568 * counted in multiples of 16 bytes.
1569 */
1570 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1571
1572
1573 /* R0 */
1574 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1575
1576 /* CR0.0[5:4] Floating-Point Rounding Modes
1577 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1578 */
1579
1580 #define BRW_CR0_RND_MODE_MASK 0x30
1581 #define BRW_CR0_RND_MODE_SHIFT 4
1582
1583 enum PACKED brw_rnd_mode {
1584 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1585 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1586 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1587 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1588 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */
1589 };
1590
1591 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1592 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1593 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1594
1595 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1596 BRW_CR0_FP32_DENORM_PRESERVE | \
1597 BRW_CR0_FP16_DENORM_PRESERVE | \
1598 BRW_CR0_RND_MODE_MASK)
1599
1600 /* MDC_DS - Data Size Message Descriptor Control Field
1601 * Skylake PRM, Volume 2d, page 129
1602 *
1603 * Specifies the number of Bytes to be read or written per Dword used at
1604 * byte_scattered read/write and byte_scaled read/write messages.
1605 */
1606 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
1607 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
1608 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
1609
1610 #endif /* BRW_EU_DEFINES_H */