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[mesa.git] / src / intel / compiler / brw_eu_defines.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32 #ifndef BRW_EU_DEFINES_H
33 #define BRW_EU_DEFINES_H
34
35 #include <stdint.h>
36 #include <stdlib.h>
37 #include "util/macros.h"
38
39 /* The following hunk, up-to "Execution Unit" is used by both the
40 * intel/compiler and i965 codebase. */
41
42 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
43 /* Using the GNU statement expression extension */
44 #define SET_FIELD(value, field) \
45 ({ \
46 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \
47 assert((fieldval & ~ field ## _MASK) == 0); \
48 fieldval & field ## _MASK; \
49 })
50
51 #define SET_BITS(value, high, low) \
52 ({ \
53 const uint32_t fieldval = (uint32_t)(value) << (low); \
54 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
55 fieldval & INTEL_MASK(high, low); \
56 })
57
58 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
59 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
60
61 #define _3DPRIM_POINTLIST 0x01
62 #define _3DPRIM_LINELIST 0x02
63 #define _3DPRIM_LINESTRIP 0x03
64 #define _3DPRIM_TRILIST 0x04
65 #define _3DPRIM_TRISTRIP 0x05
66 #define _3DPRIM_TRIFAN 0x06
67 #define _3DPRIM_QUADLIST 0x07
68 #define _3DPRIM_QUADSTRIP 0x08
69 #define _3DPRIM_LINELIST_ADJ 0x09 /* G45+ */
70 #define _3DPRIM_LINESTRIP_ADJ 0x0A /* G45+ */
71 #define _3DPRIM_TRILIST_ADJ 0x0B /* G45+ */
72 #define _3DPRIM_TRISTRIP_ADJ 0x0C /* G45+ */
73 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
74 #define _3DPRIM_POLYGON 0x0E
75 #define _3DPRIM_RECTLIST 0x0F
76 #define _3DPRIM_LINELOOP 0x10
77 #define _3DPRIM_POINTLIST_BF 0x11
78 #define _3DPRIM_LINESTRIP_CONT 0x12
79 #define _3DPRIM_LINESTRIP_BF 0x13
80 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
81 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x16
82 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
83
84 /* Bitfields for the URB_WRITE message, DW2 of message header: */
85 #define URB_WRITE_PRIM_END 0x1
86 #define URB_WRITE_PRIM_START 0x2
87 #define URB_WRITE_PRIM_TYPE_SHIFT 2
88
89 #define BRW_SPRITE_POINT_ENABLE 16
90
91 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
92 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
93
94 /* Execution Unit (EU) defines
95 */
96
97 #define BRW_ALIGN_1 0
98 #define BRW_ALIGN_16 1
99
100 #define BRW_ADDRESS_DIRECT 0
101 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
102
103 #define BRW_CHANNEL_X 0
104 #define BRW_CHANNEL_Y 1
105 #define BRW_CHANNEL_Z 2
106 #define BRW_CHANNEL_W 3
107
108 enum brw_compression {
109 BRW_COMPRESSION_NONE = 0,
110 BRW_COMPRESSION_2NDHALF = 1,
111 BRW_COMPRESSION_COMPRESSED = 2,
112 };
113
114 #define GEN6_COMPRESSION_1Q 0
115 #define GEN6_COMPRESSION_2Q 1
116 #define GEN6_COMPRESSION_3Q 2
117 #define GEN6_COMPRESSION_4Q 3
118 #define GEN6_COMPRESSION_1H 0
119 #define GEN6_COMPRESSION_2H 2
120
121 enum PACKED brw_conditional_mod {
122 BRW_CONDITIONAL_NONE = 0,
123 BRW_CONDITIONAL_Z = 1,
124 BRW_CONDITIONAL_NZ = 2,
125 BRW_CONDITIONAL_EQ = 1, /* Z */
126 BRW_CONDITIONAL_NEQ = 2, /* NZ */
127 BRW_CONDITIONAL_G = 3,
128 BRW_CONDITIONAL_GE = 4,
129 BRW_CONDITIONAL_L = 5,
130 BRW_CONDITIONAL_LE = 6,
131 BRW_CONDITIONAL_R = 7, /* Gen <= 5 */
132 BRW_CONDITIONAL_O = 8,
133 BRW_CONDITIONAL_U = 9,
134 };
135
136 #define BRW_DEBUG_NONE 0
137 #define BRW_DEBUG_BREAKPOINT 1
138
139 #define BRW_DEPENDENCY_NORMAL 0
140 #define BRW_DEPENDENCY_NOTCLEARED 1
141 #define BRW_DEPENDENCY_NOTCHECKED 2
142 #define BRW_DEPENDENCY_DISABLE 3
143
144 enum PACKED brw_execution_size {
145 BRW_EXECUTE_1 = 0,
146 BRW_EXECUTE_2 = 1,
147 BRW_EXECUTE_4 = 2,
148 BRW_EXECUTE_8 = 3,
149 BRW_EXECUTE_16 = 4,
150 BRW_EXECUTE_32 = 5,
151 };
152
153 enum PACKED brw_horizontal_stride {
154 BRW_HORIZONTAL_STRIDE_0 = 0,
155 BRW_HORIZONTAL_STRIDE_1 = 1,
156 BRW_HORIZONTAL_STRIDE_2 = 2,
157 BRW_HORIZONTAL_STRIDE_4 = 3,
158 };
159
160 enum PACKED gen10_align1_3src_src_horizontal_stride {
161 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
162 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
163 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
164 BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
165 };
166
167 enum PACKED gen10_align1_3src_dst_horizontal_stride {
168 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
169 BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
170 };
171
172 #define BRW_INSTRUCTION_NORMAL 0
173 #define BRW_INSTRUCTION_SATURATE 1
174
175 #define BRW_MASK_ENABLE 0
176 #define BRW_MASK_DISABLE 1
177
178 /** @{
179 *
180 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
181 * effectively the same but much simpler to think about. Now, there
182 * are two contributors ANDed together to whether channels are
183 * executed: The predication on the instruction, and the channel write
184 * enable.
185 */
186 /**
187 * This is the default value. It means that a channel's write enable is set
188 * if the per-channel IP is pointing at this instruction.
189 */
190 #define BRW_WE_NORMAL 0
191 /**
192 * This is used like BRW_MASK_DISABLE, and causes all channels to have
193 * their write enable set. Note that predication still contributes to
194 * whether the channel actually gets written.
195 */
196 #define BRW_WE_ALL 1
197 /** @} */
198
199 enum opcode {
200 /* These are the actual hardware instructions. */
201 BRW_OPCODE_ILLEGAL,
202 BRW_OPCODE_SYNC,
203 BRW_OPCODE_MOV,
204 BRW_OPCODE_SEL,
205 BRW_OPCODE_MOVI, /**< G45+ */
206 BRW_OPCODE_NOT,
207 BRW_OPCODE_AND,
208 BRW_OPCODE_OR,
209 BRW_OPCODE_XOR,
210 BRW_OPCODE_SHR,
211 BRW_OPCODE_SHL,
212 BRW_OPCODE_DIM, /**< Gen7.5 only */
213 BRW_OPCODE_SMOV, /**< Gen8+ */
214 BRW_OPCODE_ASR,
215 BRW_OPCODE_ROR, /**< Gen11+ */
216 BRW_OPCODE_ROL, /**< Gen11+ */
217 BRW_OPCODE_CMP,
218 BRW_OPCODE_CMPN,
219 BRW_OPCODE_CSEL, /**< Gen8+ */
220 BRW_OPCODE_F32TO16, /**< Gen7 only */
221 BRW_OPCODE_F16TO32, /**< Gen7 only */
222 BRW_OPCODE_BFREV, /**< Gen7+ */
223 BRW_OPCODE_BFE, /**< Gen7+ */
224 BRW_OPCODE_BFI1, /**< Gen7+ */
225 BRW_OPCODE_BFI2, /**< Gen7+ */
226 BRW_OPCODE_JMPI,
227 BRW_OPCODE_BRD, /**< Gen7+ */
228 BRW_OPCODE_IF,
229 BRW_OPCODE_IFF, /**< Pre-Gen6 */
230 BRW_OPCODE_BRC, /**< Gen7+ */
231 BRW_OPCODE_ELSE,
232 BRW_OPCODE_ENDIF,
233 BRW_OPCODE_DO, /**< Pre-Gen6 */
234 BRW_OPCODE_CASE, /**< Gen6 only */
235 BRW_OPCODE_WHILE,
236 BRW_OPCODE_BREAK,
237 BRW_OPCODE_CONTINUE,
238 BRW_OPCODE_HALT,
239 BRW_OPCODE_CALLA, /**< Gen7.5+ */
240 BRW_OPCODE_MSAVE, /**< Pre-Gen6 */
241 BRW_OPCODE_CALL, /**< Gen6+ */
242 BRW_OPCODE_MREST, /**< Pre-Gen6 */
243 BRW_OPCODE_RET, /**< Gen6+ */
244 BRW_OPCODE_PUSH, /**< Pre-Gen6 */
245 BRW_OPCODE_FORK, /**< Gen6 only */
246 BRW_OPCODE_GOTO, /**< Gen8+ */
247 BRW_OPCODE_POP, /**< Pre-Gen6 */
248 BRW_OPCODE_WAIT,
249 BRW_OPCODE_SEND,
250 BRW_OPCODE_SENDC,
251 BRW_OPCODE_SENDS, /**< Gen9+ */
252 BRW_OPCODE_SENDSC, /**< Gen9+ */
253 BRW_OPCODE_MATH, /**< Gen6+ */
254 BRW_OPCODE_ADD,
255 BRW_OPCODE_MUL,
256 BRW_OPCODE_AVG,
257 BRW_OPCODE_FRC,
258 BRW_OPCODE_RNDU,
259 BRW_OPCODE_RNDD,
260 BRW_OPCODE_RNDE,
261 BRW_OPCODE_RNDZ,
262 BRW_OPCODE_MAC,
263 BRW_OPCODE_MACH,
264 BRW_OPCODE_LZD,
265 BRW_OPCODE_FBH, /**< Gen7+ */
266 BRW_OPCODE_FBL, /**< Gen7+ */
267 BRW_OPCODE_CBIT, /**< Gen7+ */
268 BRW_OPCODE_ADDC, /**< Gen7+ */
269 BRW_OPCODE_SUBB, /**< Gen7+ */
270 BRW_OPCODE_SAD2,
271 BRW_OPCODE_SADA2,
272 BRW_OPCODE_DP4,
273 BRW_OPCODE_DPH,
274 BRW_OPCODE_DP3,
275 BRW_OPCODE_DP2,
276 BRW_OPCODE_LINE,
277 BRW_OPCODE_PLN, /**< G45+ */
278 BRW_OPCODE_MAD, /**< Gen6+ */
279 BRW_OPCODE_LRP, /**< Gen6+ */
280 BRW_OPCODE_MADM, /**< Gen8+ */
281 BRW_OPCODE_NENOP, /**< G45 only */
282 BRW_OPCODE_NOP,
283
284 NUM_BRW_OPCODES,
285
286 /* These are compiler backend opcodes that get translated into other
287 * instructions.
288 */
289 FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES,
290
291 /**
292 * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
293 * individual sources instead of as a single payload blob. The
294 * position/ordering of the arguments are defined by the enum
295 * fb_write_logical_srcs.
296 */
297 FS_OPCODE_FB_WRITE_LOGICAL,
298
299 FS_OPCODE_REP_FB_WRITE,
300
301 FS_OPCODE_FB_READ,
302 FS_OPCODE_FB_READ_LOGICAL,
303
304 SHADER_OPCODE_RCP,
305 SHADER_OPCODE_RSQ,
306 SHADER_OPCODE_SQRT,
307 SHADER_OPCODE_EXP2,
308 SHADER_OPCODE_LOG2,
309 SHADER_OPCODE_POW,
310 SHADER_OPCODE_INT_QUOTIENT,
311 SHADER_OPCODE_INT_REMAINDER,
312 SHADER_OPCODE_SIN,
313 SHADER_OPCODE_COS,
314
315 /**
316 * A generic "send" opcode. The first two sources are the message
317 * descriptor and extended message descriptor respectively. The third
318 * and optional fourth sources are the message payload
319 */
320 SHADER_OPCODE_SEND,
321
322 /**
323 * An "undefined" write which does nothing but indicates to liveness that
324 * we don't care about any values in the register which predate this
325 * instruction. Used to prevent partial writes from causing issues with
326 * live ranges.
327 */
328 SHADER_OPCODE_UNDEF,
329
330 /**
331 * Texture sampling opcodes.
332 *
333 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
334 * opcode but instead of taking a single payload blob they expect their
335 * arguments separately as individual sources. The position/ordering of the
336 * arguments are defined by the enum tex_logical_srcs.
337 */
338 SHADER_OPCODE_TEX,
339 SHADER_OPCODE_TEX_LOGICAL,
340 SHADER_OPCODE_TXD,
341 SHADER_OPCODE_TXD_LOGICAL,
342 SHADER_OPCODE_TXF,
343 SHADER_OPCODE_TXF_LOGICAL,
344 SHADER_OPCODE_TXF_LZ,
345 SHADER_OPCODE_TXL,
346 SHADER_OPCODE_TXL_LOGICAL,
347 SHADER_OPCODE_TXL_LZ,
348 SHADER_OPCODE_TXS,
349 SHADER_OPCODE_TXS_LOGICAL,
350 FS_OPCODE_TXB,
351 FS_OPCODE_TXB_LOGICAL,
352 SHADER_OPCODE_TXF_CMS,
353 SHADER_OPCODE_TXF_CMS_LOGICAL,
354 SHADER_OPCODE_TXF_CMS_W,
355 SHADER_OPCODE_TXF_CMS_W_LOGICAL,
356 SHADER_OPCODE_TXF_UMS,
357 SHADER_OPCODE_TXF_UMS_LOGICAL,
358 SHADER_OPCODE_TXF_MCS,
359 SHADER_OPCODE_TXF_MCS_LOGICAL,
360 SHADER_OPCODE_LOD,
361 SHADER_OPCODE_LOD_LOGICAL,
362 SHADER_OPCODE_TG4,
363 SHADER_OPCODE_TG4_LOGICAL,
364 SHADER_OPCODE_TG4_OFFSET,
365 SHADER_OPCODE_TG4_OFFSET_LOGICAL,
366 SHADER_OPCODE_SAMPLEINFO,
367 SHADER_OPCODE_SAMPLEINFO_LOGICAL,
368
369 SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
370
371 /**
372 * Combines multiple sources of size 1 into a larger virtual GRF.
373 * For example, parameters for a send-from-GRF message. Or, updating
374 * channels of a size 4 VGRF used to store vec4s such as texturing results.
375 *
376 * This will be lowered into MOVs from each source to consecutive offsets
377 * of the destination VGRF.
378 *
379 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV,
380 * but still reserves the first channel of the destination VGRF. This can be
381 * used to reserve space for, say, a message header set up by the generators.
382 */
383 SHADER_OPCODE_LOAD_PAYLOAD,
384
385 /**
386 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
387 * acts intra-channel, obtaining the final value for each channel by
388 * combining the sources values for the same channel, the first source
389 * occupying the lowest bits and the last source occupying the highest
390 * bits.
391 */
392 FS_OPCODE_PACK,
393
394 SHADER_OPCODE_SHADER_TIME_ADD,
395
396 /**
397 * Typed and untyped surface access opcodes.
398 *
399 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
400 * opcode but instead of taking a single payload blob they expect their
401 * arguments separately as individual sources:
402 *
403 * Source 0: [required] Surface coordinates.
404 * Source 1: [optional] Operation source.
405 * Source 2: [required] Surface index.
406 * Source 3: [required] Number of coordinate components (as UD immediate).
407 * Source 4: [required] Opcode-specific control immediate, same as source 2
408 * of the matching non-LOGICAL opcode.
409 */
410 VEC4_OPCODE_UNTYPED_ATOMIC,
411 SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
412 SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
413 VEC4_OPCODE_UNTYPED_SURFACE_READ,
414 SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
415 VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
416 SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
417
418 /**
419 * Untyped A64 surface access opcodes.
420 *
421 * Source 0: 64-bit address
422 * Source 1: Operational source
423 * Source 2: [required] Opcode-specific control immediate, same as source 2
424 * of the matching non-LOGICAL opcode.
425 */
426 SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
427 SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
428 SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
429 SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
430 SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
431 SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
432 SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
433
434 SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
435 SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
436 SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
437
438 SHADER_OPCODE_RND_MODE,
439 SHADER_OPCODE_FLOAT_CONTROL_MODE,
440
441 /**
442 * Byte scattered write/read opcodes.
443 *
444 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
445 * opcode, but instead of taking a single payload blog they expect their
446 * arguments separately as individual sources, like untyped write/read.
447 */
448 SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
449 SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
450 SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
451 SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
452
453 /**
454 * Memory fence messages.
455 *
456 * Source 0: Must be register g0, used as header.
457 * Source 1: Immediate bool to indicate whether or not we need to stall
458 * until memory transactions prior to the fence are completed.
459 * Source 2: Immediate byte indicating which memory to fence. Zero means
460 * global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
461 *
462 * Vec4 backend only uses Source 0.
463 */
464 SHADER_OPCODE_MEMORY_FENCE,
465
466 /**
467 * Scheduling-only fence.
468 */
469 FS_OPCODE_SCHEDULING_FENCE,
470
471 SHADER_OPCODE_GEN4_SCRATCH_READ,
472 SHADER_OPCODE_GEN4_SCRATCH_WRITE,
473 SHADER_OPCODE_GEN7_SCRATCH_READ,
474
475 /**
476 * Gen8+ SIMD8 URB Read messages.
477 */
478 SHADER_OPCODE_URB_READ_SIMD8,
479 SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
480
481 SHADER_OPCODE_URB_WRITE_SIMD8,
482 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
483 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
484 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
485
486 /**
487 * Return the index of an arbitrary live channel (i.e. one of the channels
488 * enabled in the current execution mask) and assign it to the first
489 * component of the destination. Expected to be used as input for the
490 * BROADCAST pseudo-opcode.
491 */
492 SHADER_OPCODE_FIND_LIVE_CHANNEL,
493
494 /**
495 * Return the current execution mask in the specified flag subregister.
496 * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register.
497 */
498 FS_OPCODE_LOAD_LIVE_CHANNELS,
499
500 /**
501 * Pick the channel from its first source register given by the index
502 * specified as second source. Useful for variable indexing of surfaces.
503 *
504 * Note that because the result of this instruction is by definition
505 * uniform and it can always be splatted to multiple channels using a
506 * scalar regioning mode, only the first channel of the destination region
507 * is guaranteed to be updated, which implies that BROADCAST instructions
508 * should usually be marked force_writemask_all.
509 */
510 SHADER_OPCODE_BROADCAST,
511
512 /* Pick the channel from its first source register given by the index
513 * specified as second source.
514 *
515 * This is similar to the BROADCAST instruction except that it takes a
516 * dynamic index and potentially puts a different value in each output
517 * channel.
518 */
519 SHADER_OPCODE_SHUFFLE,
520
521 /* Select between src0 and src1 based on channel enables.
522 *
523 * This instruction copies src0 into the enabled channels of the
524 * destination and copies src1 into the disabled channels.
525 */
526 SHADER_OPCODE_SEL_EXEC,
527
528 /* This turns into an align16 mov from src0 to dst with a swizzle
529 * provided as an immediate in src1.
530 */
531 SHADER_OPCODE_QUAD_SWIZZLE,
532
533 /* Take every Nth element in src0 and broadcast it to the group of N
534 * channels in which it lives in the destination. The offset within the
535 * cluster is given by src1 and the cluster size is given by src2.
536 */
537 SHADER_OPCODE_CLUSTER_BROADCAST,
538
539 SHADER_OPCODE_GET_BUFFER_SIZE,
540
541 SHADER_OPCODE_INTERLOCK,
542
543 VEC4_OPCODE_MOV_BYTES,
544 VEC4_OPCODE_PACK_BYTES,
545 VEC4_OPCODE_UNPACK_UNIFORM,
546 VEC4_OPCODE_DOUBLE_TO_F32,
547 VEC4_OPCODE_DOUBLE_TO_D32,
548 VEC4_OPCODE_DOUBLE_TO_U32,
549 VEC4_OPCODE_TO_DOUBLE,
550 VEC4_OPCODE_PICK_LOW_32BIT,
551 VEC4_OPCODE_PICK_HIGH_32BIT,
552 VEC4_OPCODE_SET_LOW_32BIT,
553 VEC4_OPCODE_SET_HIGH_32BIT,
554
555 FS_OPCODE_DDX_COARSE,
556 FS_OPCODE_DDX_FINE,
557 /**
558 * Compute dFdy(), dFdyCoarse(), or dFdyFine().
559 */
560 FS_OPCODE_DDY_COARSE,
561 FS_OPCODE_DDY_FINE,
562 FS_OPCODE_LINTERP,
563 FS_OPCODE_PIXEL_X,
564 FS_OPCODE_PIXEL_Y,
565 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
566 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
567 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
568 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
569 FS_OPCODE_DISCARD_JUMP,
570 FS_OPCODE_SET_SAMPLE_ID,
571 FS_OPCODE_PACK_HALF_2x16_SPLIT,
572 FS_OPCODE_PLACEHOLDER_HALT,
573 FS_OPCODE_INTERPOLATE_AT_SAMPLE,
574 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
575 FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
576
577 VS_OPCODE_URB_WRITE,
578 VS_OPCODE_PULL_CONSTANT_LOAD,
579 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
580 VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
581
582 VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
583
584 /**
585 * Write geometry shader output data to the URB.
586 *
587 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
588 * R0 to the first MRF. This allows the geometry shader to override the
589 * "Slot {0,1} Offset" fields in the message header.
590 */
591 GS_OPCODE_URB_WRITE,
592
593 /**
594 * Write geometry shader output data to the URB and request a new URB
595 * handle (gen6).
596 *
597 * This opcode doesn't do an implied move from R0 to the first MRF.
598 */
599 GS_OPCODE_URB_WRITE_ALLOCATE,
600
601 /**
602 * Terminate the geometry shader thread by doing an empty URB write.
603 *
604 * This opcode doesn't do an implied move from R0 to the first MRF. This
605 * allows the geometry shader to override the "GS Number of Output Vertices
606 * for Slot {0,1}" fields in the message header.
607 */
608 GS_OPCODE_THREAD_END,
609
610 /**
611 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
612 *
613 * - dst is the MRF containing the message header.
614 *
615 * - src0.x indicates which portion of the URB should be written to (e.g. a
616 * vertex number)
617 *
618 * - src1 is an immediate multiplier which will be applied to src0
619 * (e.g. the size of a single vertex in the URB).
620 *
621 * Note: the hardware will apply this offset *in addition to* the offset in
622 * vec4_instruction::offset.
623 */
624 GS_OPCODE_SET_WRITE_OFFSET,
625
626 /**
627 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
628 * URB_WRITE message header.
629 *
630 * - dst is the MRF containing the message header.
631 *
632 * - src0.x is the vertex count. The upper 16 bits will be ignored.
633 */
634 GS_OPCODE_SET_VERTEX_COUNT,
635
636 /**
637 * Set DWORD 2 of dst to the value in src.
638 */
639 GS_OPCODE_SET_DWORD_2,
640
641 /**
642 * Prepare the dst register for storage in the "Channel Mask" fields of a
643 * URB_WRITE message header.
644 *
645 * DWORD 4 of dst is shifted left by 4 bits, so that later,
646 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
647 * final channel mask.
648 *
649 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
650 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
651 * have any extraneous bits set prior to execution of this opcode (that is,
652 * they should be in the range 0x0 to 0xf).
653 */
654 GS_OPCODE_PREPARE_CHANNEL_MASKS,
655
656 /**
657 * Set the "Channel Mask" fields of a URB_WRITE message header.
658 *
659 * - dst is the MRF containing the message header.
660 *
661 * - src.x is the channel mask, as prepared by
662 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
663 * form the final channel mask.
664 */
665 GS_OPCODE_SET_CHANNEL_MASKS,
666
667 /**
668 * Get the "Instance ID" fields from the payload.
669 *
670 * - dst is the GRF for gl_InvocationID.
671 */
672 GS_OPCODE_GET_INSTANCE_ID,
673
674 /**
675 * Send a FF_SYNC message to allocate initial URB handles (gen6).
676 *
677 * - dst will be used as the writeback register for the FF_SYNC operation.
678 *
679 * - src0 is the number of primitives written.
680 *
681 * - src1 is the value to hold in M0.0: number of SO vertices to write
682 * and number of SO primitives needed. Its value will be overwritten
683 * with the SVBI values if transform feedback is enabled.
684 *
685 * Note: This opcode uses an implicit MRF register for the ff_sync message
686 * header, so the caller is expected to set inst->base_mrf and initialize
687 * that MRF register to r0. This opcode will also write to this MRF register
688 * to include the allocated URB handle so it can then be reused directly as
689 * the header in the URB write operation we are allocating the handle for.
690 */
691 GS_OPCODE_FF_SYNC,
692
693 /**
694 * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
695 * register.
696 *
697 * - dst is the GRF where PrimitiveID information will be moved.
698 */
699 GS_OPCODE_SET_PRIMITIVE_ID,
700
701 /**
702 * Write transform feedback data to the SVB by sending a SVB WRITE message.
703 * Used in gen6.
704 *
705 * - dst is the MRF register containing the message header.
706 *
707 * - src0 is the register where the vertex data is going to be copied from.
708 *
709 * - src1 is the destination register when write commit occurs.
710 */
711 GS_OPCODE_SVB_WRITE,
712
713 /**
714 * Set destination index in the SVB write message payload (M0.5). Used
715 * in gen6 for transform feedback.
716 *
717 * - dst is the header to save the destination indices for SVB WRITE.
718 * - src is the register that holds the destination indices value.
719 */
720 GS_OPCODE_SVB_SET_DST_INDEX,
721
722 /**
723 * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
724 * Used in gen6 for transform feedback.
725 *
726 * - dst will hold the register with the final Mx.0 value.
727 *
728 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
729 *
730 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
731 *
732 * - src2 is the value to hold in M0: number of SO vertices to write
733 * and number of SO primitives needed.
734 */
735 GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
736
737 /**
738 * Terminate the compute shader.
739 */
740 CS_OPCODE_CS_TERMINATE,
741
742 /**
743 * GLSL barrier()
744 */
745 SHADER_OPCODE_BARRIER,
746
747 /**
748 * Calculate the high 32-bits of a 32x32 multiply.
749 */
750 SHADER_OPCODE_MULH,
751
752 /** Signed subtraction with saturation. */
753 SHADER_OPCODE_ISUB_SAT,
754
755 /** Unsigned subtraction with saturation. */
756 SHADER_OPCODE_USUB_SAT,
757
758 /**
759 * A MOV that uses VxH indirect addressing.
760 *
761 * Source 0: A register to start from (HW_REG).
762 * Source 1: An indirect offset (in bytes, UD GRF).
763 * Source 2: The length of the region that could be accessed (in bytes,
764 * UD immediate).
765 */
766 SHADER_OPCODE_MOV_INDIRECT,
767
768 VEC4_OPCODE_URB_READ,
769 TCS_OPCODE_GET_INSTANCE_ID,
770 TCS_OPCODE_URB_WRITE,
771 TCS_OPCODE_SET_INPUT_URB_OFFSETS,
772 TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
773 TCS_OPCODE_GET_PRIMITIVE_ID,
774 TCS_OPCODE_CREATE_BARRIER_HEADER,
775 TCS_OPCODE_SRC0_010_IS_ZERO,
776 TCS_OPCODE_RELEASE_INPUT,
777 TCS_OPCODE_THREAD_END,
778
779 TES_OPCODE_GET_PRIMITIVE_ID,
780 TES_OPCODE_CREATE_INPUT_READ_HEADER,
781 TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
782 };
783
784 enum brw_urb_write_flags {
785 BRW_URB_WRITE_NO_FLAGS = 0,
786
787 /**
788 * Causes a new URB entry to be allocated, and its address stored in the
789 * destination register (gen < 7).
790 */
791 BRW_URB_WRITE_ALLOCATE = 0x1,
792
793 /**
794 * Causes the current URB entry to be deallocated (gen < 7).
795 */
796 BRW_URB_WRITE_UNUSED = 0x2,
797
798 /**
799 * Causes the thread to terminate.
800 */
801 BRW_URB_WRITE_EOT = 0x4,
802
803 /**
804 * Indicates that the given URB entry is complete, and may be sent further
805 * down the 3D pipeline (gen < 7).
806 */
807 BRW_URB_WRITE_COMPLETE = 0x8,
808
809 /**
810 * Indicates that an additional offset (which may be different for the two
811 * vec4 slots) is stored in the message header (gen == 7).
812 */
813 BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
814
815 /**
816 * Indicates that the channel masks in the URB_WRITE message header should
817 * not be overridden to 0xff (gen == 7).
818 */
819 BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
820
821 /**
822 * Indicates that the data should be sent to the URB using the
823 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
824 * causes offsets to be interpreted as multiples of an OWORD instead of an
825 * HWORD, and only allows one OWORD to be written.
826 */
827 BRW_URB_WRITE_OWORD = 0x40,
828
829 /**
830 * Convenient combination of flags: end the thread while simultaneously
831 * marking the given URB entry as complete.
832 */
833 BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
834
835 /**
836 * Convenient combination of flags: mark the given URB entry as complete
837 * and simultaneously allocate a new one.
838 */
839 BRW_URB_WRITE_ALLOCATE_COMPLETE =
840 BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
841 };
842
843 enum fb_write_logical_srcs {
844 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */
845 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */
846 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
847 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */
848 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GEN4-5: passthrough from thread */
849 FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
850 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */
851 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */
852 FB_WRITE_LOGICAL_NUM_SRCS
853 };
854
855 enum tex_logical_srcs {
856 /** Texture coordinates */
857 TEX_LOGICAL_SRC_COORDINATE,
858 /** Shadow comparator */
859 TEX_LOGICAL_SRC_SHADOW_C,
860 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
861 TEX_LOGICAL_SRC_LOD,
862 /** dPdy if the operation takes explicit derivatives */
863 TEX_LOGICAL_SRC_LOD2,
864 /** Min LOD */
865 TEX_LOGICAL_SRC_MIN_LOD,
866 /** Sample index */
867 TEX_LOGICAL_SRC_SAMPLE_INDEX,
868 /** MCS data */
869 TEX_LOGICAL_SRC_MCS,
870 /** REQUIRED: Texture surface index */
871 TEX_LOGICAL_SRC_SURFACE,
872 /** Texture sampler index */
873 TEX_LOGICAL_SRC_SAMPLER,
874 /** Texture surface bindless handle */
875 TEX_LOGICAL_SRC_SURFACE_HANDLE,
876 /** Texture sampler bindless handle */
877 TEX_LOGICAL_SRC_SAMPLER_HANDLE,
878 /** Texel offset for gathers */
879 TEX_LOGICAL_SRC_TG4_OFFSET,
880 /** REQUIRED: Number of coordinate components (as UD immediate) */
881 TEX_LOGICAL_SRC_COORD_COMPONENTS,
882 /** REQUIRED: Number of derivative components (as UD immediate) */
883 TEX_LOGICAL_SRC_GRAD_COMPONENTS,
884
885 TEX_LOGICAL_NUM_SRCS,
886 };
887
888 enum surface_logical_srcs {
889 /** Surface binding table index */
890 SURFACE_LOGICAL_SRC_SURFACE,
891 /** Surface bindless handle */
892 SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
893 /** Surface address; could be multi-dimensional for typed opcodes */
894 SURFACE_LOGICAL_SRC_ADDRESS,
895 /** Data to be written or used in an atomic op */
896 SURFACE_LOGICAL_SRC_DATA,
897 /** Surface number of dimensions. Affects the size of ADDRESS */
898 SURFACE_LOGICAL_SRC_IMM_DIMS,
899 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */
900 SURFACE_LOGICAL_SRC_IMM_ARG,
901
902 SURFACE_LOGICAL_NUM_SRCS
903 };
904
905 #ifdef __cplusplus
906 /**
907 * Allow brw_urb_write_flags enums to be ORed together.
908 */
909 inline brw_urb_write_flags
910 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
911 {
912 return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
913 static_cast<int>(y));
914 }
915 #endif
916
917 enum PACKED brw_predicate {
918 BRW_PREDICATE_NONE = 0,
919 BRW_PREDICATE_NORMAL = 1,
920 BRW_PREDICATE_ALIGN1_ANYV = 2,
921 BRW_PREDICATE_ALIGN1_ALLV = 3,
922 BRW_PREDICATE_ALIGN1_ANY2H = 4,
923 BRW_PREDICATE_ALIGN1_ALL2H = 5,
924 BRW_PREDICATE_ALIGN1_ANY4H = 6,
925 BRW_PREDICATE_ALIGN1_ALL4H = 7,
926 BRW_PREDICATE_ALIGN1_ANY8H = 8,
927 BRW_PREDICATE_ALIGN1_ALL8H = 9,
928 BRW_PREDICATE_ALIGN1_ANY16H = 10,
929 BRW_PREDICATE_ALIGN1_ALL16H = 11,
930 BRW_PREDICATE_ALIGN1_ANY32H = 12,
931 BRW_PREDICATE_ALIGN1_ALL32H = 13,
932 BRW_PREDICATE_ALIGN16_REPLICATE_X = 2,
933 BRW_PREDICATE_ALIGN16_REPLICATE_Y = 3,
934 BRW_PREDICATE_ALIGN16_REPLICATE_Z = 4,
935 BRW_PREDICATE_ALIGN16_REPLICATE_W = 5,
936 BRW_PREDICATE_ALIGN16_ANY4H = 6,
937 BRW_PREDICATE_ALIGN16_ALL4H = 7,
938 };
939
940 enum PACKED brw_reg_file {
941 BRW_ARCHITECTURE_REGISTER_FILE = 0,
942 BRW_GENERAL_REGISTER_FILE = 1,
943 BRW_MESSAGE_REGISTER_FILE = 2,
944 BRW_IMMEDIATE_VALUE = 3,
945
946 ARF = BRW_ARCHITECTURE_REGISTER_FILE,
947 FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
948 MRF = BRW_MESSAGE_REGISTER_FILE,
949 IMM = BRW_IMMEDIATE_VALUE,
950
951 /* These are not hardware values */
952 VGRF,
953 ATTR,
954 UNIFORM, /* prog_data->params[reg] */
955 BAD_FILE,
956 };
957
958 enum PACKED gen10_align1_3src_reg_file {
959 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
960 BRW_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */
961 BRW_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */
962 };
963
964 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
965 * word is "Execution Datatype" which controls whether the instruction operates
966 * on float or integer types. The register arguments have fields that offer
967 * more fine control their respective types.
968 */
969 enum PACKED gen10_align1_3src_exec_type {
970 BRW_ALIGN1_3SRC_EXEC_TYPE_INT = 0,
971 BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
972 };
973
974 #define BRW_ARF_NULL 0x00
975 #define BRW_ARF_ADDRESS 0x10
976 #define BRW_ARF_ACCUMULATOR 0x20
977 #define BRW_ARF_FLAG 0x30
978 #define BRW_ARF_MASK 0x40
979 #define BRW_ARF_MASK_STACK 0x50
980 #define BRW_ARF_MASK_STACK_DEPTH 0x60
981 #define BRW_ARF_STATE 0x70
982 #define BRW_ARF_CONTROL 0x80
983 #define BRW_ARF_NOTIFICATION_COUNT 0x90
984 #define BRW_ARF_IP 0xA0
985 #define BRW_ARF_TDR 0xB0
986 #define BRW_ARF_TIMESTAMP 0xC0
987
988 #define BRW_MRF_COMPR4 (1 << 7)
989
990 #define BRW_AMASK 0
991 #define BRW_IMASK 1
992 #define BRW_LMASK 2
993 #define BRW_CMASK 3
994
995
996
997 #define BRW_THREAD_NORMAL 0
998 #define BRW_THREAD_ATOMIC 1
999 #define BRW_THREAD_SWITCH 2
1000
1001 enum PACKED brw_vertical_stride {
1002 BRW_VERTICAL_STRIDE_0 = 0,
1003 BRW_VERTICAL_STRIDE_1 = 1,
1004 BRW_VERTICAL_STRIDE_2 = 2,
1005 BRW_VERTICAL_STRIDE_4 = 3,
1006 BRW_VERTICAL_STRIDE_8 = 4,
1007 BRW_VERTICAL_STRIDE_16 = 5,
1008 BRW_VERTICAL_STRIDE_32 = 6,
1009 BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
1010 };
1011
1012 enum PACKED gen10_align1_3src_vertical_stride {
1013 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
1014 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
1015 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
1016 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
1017 BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1018 };
1019
1020 enum PACKED brw_width {
1021 BRW_WIDTH_1 = 0,
1022 BRW_WIDTH_2 = 1,
1023 BRW_WIDTH_4 = 2,
1024 BRW_WIDTH_8 = 3,
1025 BRW_WIDTH_16 = 4,
1026 };
1027
1028 /**
1029 * Gen12+ SWSB SBID synchronization mode.
1030 *
1031 * This is represented as a bitmask including any required SBID token
1032 * synchronization modes, used to synchronize out-of-order instructions. Only
1033 * the strongest mode of the mask will be provided to the hardware in the SWSB
1034 * field of an actual hardware instruction, but virtual instructions may be
1035 * able to take into account multiple of them.
1036 */
1037 enum tgl_sbid_mode {
1038 TGL_SBID_NULL = 0,
1039 TGL_SBID_SRC = 1,
1040 TGL_SBID_DST = 2,
1041 TGL_SBID_SET = 4
1042 };
1043
1044 #ifdef __cplusplus
1045 /**
1046 * Allow bitwise arithmetic of tgl_sbid_mode enums.
1047 */
1048 inline tgl_sbid_mode
1049 operator|(tgl_sbid_mode x, tgl_sbid_mode y)
1050 {
1051 return tgl_sbid_mode(unsigned(x) | unsigned(y));
1052 }
1053
1054 inline tgl_sbid_mode
1055 operator&(tgl_sbid_mode x, tgl_sbid_mode y)
1056 {
1057 return tgl_sbid_mode(unsigned(x) & unsigned(y));
1058 }
1059
1060 inline tgl_sbid_mode &
1061 operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
1062 {
1063 return x = x | y;
1064 }
1065
1066 #endif
1067
1068 /**
1069 * Logical representation of the SWSB scheduling information of a hardware
1070 * instruction. The binary representation is slightly more compact.
1071 */
1072 struct tgl_swsb {
1073 unsigned regdist : 3;
1074 unsigned sbid : 4;
1075 enum tgl_sbid_mode mode : 3;
1076 };
1077
1078 /**
1079 * Construct a scheduling annotation with a single RegDist dependency. This
1080 * synchronizes with the completion of the d-th previous in-order instruction.
1081 * The index is one-based, zero causes a no-op tgl_swsb to be constructed.
1082 */
1083 static inline struct tgl_swsb
1084 tgl_swsb_regdist(unsigned d)
1085 {
1086 const struct tgl_swsb swsb = { d };
1087 assert(swsb.regdist == d);
1088 return swsb;
1089 }
1090
1091 /**
1092 * Construct a scheduling annotation that synchronizes with the specified SBID
1093 * token.
1094 */
1095 static inline struct tgl_swsb
1096 tgl_swsb_sbid(enum tgl_sbid_mode mode, unsigned sbid)
1097 {
1098 const struct tgl_swsb swsb = { 0, sbid, mode };
1099 assert(swsb.sbid == sbid);
1100 return swsb;
1101 }
1102
1103 /**
1104 * Construct a no-op scheduling annotation.
1105 */
1106 static inline struct tgl_swsb
1107 tgl_swsb_null(void)
1108 {
1109 return tgl_swsb_regdist(0);
1110 }
1111
1112 /**
1113 * Return a scheduling annotation that allocates the same SBID synchronization
1114 * token as \p swsb. In addition it will synchronize against a previous
1115 * in-order instruction if \p regdist is non-zero.
1116 */
1117 static inline struct tgl_swsb
1118 tgl_swsb_dst_dep(struct tgl_swsb swsb, unsigned regdist)
1119 {
1120 swsb.regdist = regdist;
1121 swsb.mode = swsb.mode & TGL_SBID_SET;
1122 return swsb;
1123 }
1124
1125 /**
1126 * Return a scheduling annotation that synchronizes against the same SBID and
1127 * RegDist dependencies as \p swsb, but doesn't allocate any SBID token.
1128 */
1129 static inline struct tgl_swsb
1130 tgl_swsb_src_dep(struct tgl_swsb swsb)
1131 {
1132 swsb.mode = swsb.mode & (TGL_SBID_SRC | TGL_SBID_DST);
1133 return swsb;
1134 }
1135
1136 /**
1137 * Convert the provided tgl_swsb to the hardware's binary representation of an
1138 * SWSB annotation.
1139 */
1140 static inline uint8_t
1141 tgl_swsb_encode(struct tgl_swsb swsb)
1142 {
1143 if (!swsb.mode) {
1144 return swsb.regdist;
1145 } else if (swsb.regdist) {
1146 return 0x80 | swsb.regdist << 4 | swsb.sbid;
1147 } else {
1148 return swsb.sbid | (swsb.mode & TGL_SBID_SET ? 0x40 :
1149 swsb.mode & TGL_SBID_DST ? 0x20 : 0x30);
1150 }
1151 }
1152
1153 /**
1154 * Convert the provided binary representation of an SWSB annotation to a
1155 * tgl_swsb.
1156 */
1157 static inline struct tgl_swsb
1158 tgl_swsb_decode(enum opcode opcode, uint8_t x)
1159 {
1160 if (x & 0x80) {
1161 const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
1162 (opcode == BRW_OPCODE_SEND ||
1163 opcode == BRW_OPCODE_SENDC ||
1164 opcode == BRW_OPCODE_MATH) ?
1165 TGL_SBID_SET : TGL_SBID_DST };
1166 return swsb;
1167 } else if ((x & 0x70) == 0x20) {
1168 return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);
1169 } else if ((x & 0x70) == 0x30) {
1170 return tgl_swsb_sbid(TGL_SBID_SRC, x & 0xfu);
1171 } else if ((x & 0x70) == 0x40) {
1172 return tgl_swsb_sbid(TGL_SBID_SET, x & 0xfu);
1173 } else {
1174 return tgl_swsb_regdist(x & 0x7u);
1175 }
1176 }
1177
1178 enum tgl_sync_function {
1179 TGL_SYNC_NOP = 0x0,
1180 TGL_SYNC_ALLRD = 0x2,
1181 TGL_SYNC_ALLWR = 0x3,
1182 TGL_SYNC_BAR = 0xe,
1183 TGL_SYNC_HOST = 0xf
1184 };
1185
1186 /**
1187 * Message target: Shared Function ID for where to SEND a message.
1188 *
1189 * These are enumerated in the ISA reference under "send - Send Message".
1190 * In particular, see the following tables:
1191 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1192 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1193 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1194 */
1195 enum brw_message_target {
1196 BRW_SFID_NULL = 0,
1197 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */
1198 BRW_SFID_SAMPLER = 2,
1199 BRW_SFID_MESSAGE_GATEWAY = 3,
1200 BRW_SFID_DATAPORT_READ = 4,
1201 BRW_SFID_DATAPORT_WRITE = 5,
1202 BRW_SFID_URB = 6,
1203 BRW_SFID_THREAD_SPAWNER = 7,
1204 BRW_SFID_VME = 8,
1205
1206 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
1207 GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
1208 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1209
1210 GEN7_SFID_DATAPORT_DATA_CACHE = 10,
1211 GEN7_SFID_PIXEL_INTERPOLATOR = 11,
1212 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
1213 HSW_SFID_CRE = 13,
1214 };
1215
1216 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
1217
1218 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
1219 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
1220 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
1221
1222 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
1223 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
1224 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
1225 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
1226 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
1227 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
1228 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
1229 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
1230 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
1231 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1232 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1233 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1234 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1235 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1236 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1237 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1238 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1239 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1240
1241 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1242 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1243 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1244 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1245 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1246 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1247 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1248 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1249 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1250 #define GEN5_SAMPLER_MESSAGE_LOD 9
1251 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1252 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11
1253 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1254 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1255 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1256 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1257 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ 24
1258 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ 25
1259 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ 26
1260 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W 28
1261 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1262 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1263 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1264
1265 /* for GEN5 only */
1266 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1267 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1268 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1269 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1270
1271 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1272 * behavior by setting bit 22 of dword 2 in the message header. */
1273 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D 0
1274 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2 (1 << 22)
1275
1276 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1277 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1278 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1279 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1280 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1281 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n) \
1282 ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \
1283 (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS : \
1284 (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS : \
1285 (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS : \
1286 (abort(), ~0))
1287
1288 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1289 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1290
1291 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1292 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1293
1294 /* This one stays the same across generations. */
1295 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1296 /* GEN4 */
1297 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1298 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1299 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1300 /* G45, GEN5 */
1301 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1302 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1303 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1304 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1305 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1306 /* GEN6 */
1307 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1308 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1309 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1310 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1311 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1312
1313 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1314 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1315 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1316
1317 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1318 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1319 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1320 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1321 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1322
1323 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1324 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1325 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1326 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1327 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1328 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1329 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1330
1331 /* GEN6 */
1332 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1333 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1334 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1335 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1336 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1337 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1338 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1339 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1340
1341 /* GEN7 */
1342 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ 4
1343 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ 5
1344 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP 6
1345 #define GEN7_DATAPORT_RC_MEMORY_FENCE 7
1346 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10
1347 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE 12
1348 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE 13
1349 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1350 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1351 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1352 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1353 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1354 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1355 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1356 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1357 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1358 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1359 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1360 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1361 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1362
1363 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1364 (0 << 17))
1365 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1366 (1 << 17))
1367 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1368
1369 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
1370 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1
1371 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID 2
1372 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3
1373
1374 /* HSW */
1375 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1376 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1377 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1378 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1379 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1380 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1381 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1382 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1383 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1384 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1385
1386 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1387 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1388 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1389 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1390 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1391 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1392 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1393 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1394 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1395 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1396 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1397 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1398 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10
1399 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11
1400 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12
1401 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19
1402 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a
1403 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP 0x1b
1404 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP 0x1d
1405
1406 /* GEN9 */
1407 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE 12
1408 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ 13
1409
1410 /* A64 scattered message subtype */
1411 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE 0
1412 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD 1
1413 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD 2
1414 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD 3
1415
1416 /* Dataport special binding table indices: */
1417 #define BRW_BTI_STATELESS 255
1418 #define GEN7_BTI_SLM 254
1419 /* Note that on Gen8+ BTI 255 was redefined to be IA-coherent according to the
1420 * hardware spec, however because the DRM sets bit 4 of HDC_CHICKEN0 on BDW,
1421 * CHV and at least some pre-production steppings of SKL due to
1422 * WaForceEnableNonCoherent, HDC memory access may have been overridden by the
1423 * kernel to be non-coherent (matching the behavior of the same BTI on
1424 * pre-Gen8 hardware) and BTI 255 may actually be an alias for BTI 253.
1425 */
1426 #define GEN8_BTI_STATELESS_IA_COHERENT 255
1427 #define GEN8_BTI_STATELESS_NON_COHERENT 253
1428 #define GEN9_BTI_BINDLESS 252
1429
1430 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1431 * (and others).
1432 */
1433 #define BRW_AOP_AND 1
1434 #define BRW_AOP_OR 2
1435 #define BRW_AOP_XOR 3
1436 #define BRW_AOP_MOV 4
1437 #define BRW_AOP_INC 5
1438 #define BRW_AOP_DEC 6
1439 #define BRW_AOP_ADD 7
1440 #define BRW_AOP_SUB 8
1441 #define BRW_AOP_REVSUB 9
1442 #define BRW_AOP_IMAX 10
1443 #define BRW_AOP_IMIN 11
1444 #define BRW_AOP_UMAX 12
1445 #define BRW_AOP_UMIN 13
1446 #define BRW_AOP_CMPWR 14
1447 #define BRW_AOP_PREDEC 15
1448
1449 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1450 #define BRW_AOP_FMAX 1
1451 #define BRW_AOP_FMIN 2
1452 #define BRW_AOP_FCMPWR 3
1453
1454 #define BRW_MATH_FUNCTION_INV 1
1455 #define BRW_MATH_FUNCTION_LOG 2
1456 #define BRW_MATH_FUNCTION_EXP 3
1457 #define BRW_MATH_FUNCTION_SQRT 4
1458 #define BRW_MATH_FUNCTION_RSQ 5
1459 #define BRW_MATH_FUNCTION_SIN 6
1460 #define BRW_MATH_FUNCTION_COS 7
1461 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1462 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1463 #define BRW_MATH_FUNCTION_POW 10
1464 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1465 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1466 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1467 #define GEN8_MATH_FUNCTION_INVM 14
1468 #define GEN8_MATH_FUNCTION_RSQRTM 15
1469
1470 #define BRW_MATH_INTEGER_UNSIGNED 0
1471 #define BRW_MATH_INTEGER_SIGNED 1
1472
1473 #define BRW_MATH_PRECISION_FULL 0
1474 #define BRW_MATH_PRECISION_PARTIAL 1
1475
1476 #define BRW_MATH_SATURATE_NONE 0
1477 #define BRW_MATH_SATURATE_SATURATE 1
1478
1479 #define BRW_MATH_DATA_VECTOR 0
1480 #define BRW_MATH_DATA_SCALAR 1
1481
1482 #define BRW_URB_OPCODE_WRITE_HWORD 0
1483 #define BRW_URB_OPCODE_WRITE_OWORD 1
1484 #define BRW_URB_OPCODE_READ_HWORD 2
1485 #define BRW_URB_OPCODE_READ_OWORD 3
1486 #define GEN7_URB_OPCODE_ATOMIC_MOV 4
1487 #define GEN7_URB_OPCODE_ATOMIC_INC 5
1488 #define GEN8_URB_OPCODE_ATOMIC_ADD 6
1489 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1490 #define GEN8_URB_OPCODE_SIMD8_READ 8
1491
1492 #define BRW_URB_SWIZZLE_NONE 0
1493 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1494 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1495
1496 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1497 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1498 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1499 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1500 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1501 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1502 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1503 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1504 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1505 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1506 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1507 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1508
1509 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0
1510 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1
1511 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2
1512 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3
1513 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4
1514 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1515 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6
1516
1517
1518 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1519 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1520 *
1521 * Identical for VS, DS, and HS.
1522 */
1523 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1524 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64)
1525 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64)
1526 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64)
1527
1528 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1529 * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1530 */
1531 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
1532
1533 /* GS Thread Payload
1534 */
1535
1536 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1537 * counted in multiples of 16 bytes.
1538 */
1539 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1540
1541
1542 /* R0 */
1543 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1544
1545 /* CR0.0[5:4] Floating-Point Rounding Modes
1546 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1547 */
1548
1549 #define BRW_CR0_RND_MODE_MASK 0x30
1550 #define BRW_CR0_RND_MODE_SHIFT 4
1551
1552 enum PACKED brw_rnd_mode {
1553 BRW_RND_MODE_RTNE = 0, /* Round to Nearest or Even */
1554 BRW_RND_MODE_RU = 1, /* Round Up, toward +inf */
1555 BRW_RND_MODE_RD = 2, /* Round Down, toward -inf */
1556 BRW_RND_MODE_RTZ = 3, /* Round Toward Zero */
1557 BRW_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */
1558 };
1559
1560 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1561 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1562 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1563
1564 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1565 BRW_CR0_FP32_DENORM_PRESERVE | \
1566 BRW_CR0_FP16_DENORM_PRESERVE | \
1567 BRW_CR0_RND_MODE_MASK)
1568
1569 /* MDC_DS - Data Size Message Descriptor Control Field
1570 * Skylake PRM, Volume 2d, page 129
1571 *
1572 * Specifies the number of Bytes to be read or written per Dword used at
1573 * byte_scattered read/write and byte_scaled read/write messages.
1574 */
1575 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0
1576 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1
1577 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
1578
1579 #endif /* BRW_EU_DEFINES_H */