src/intel/compiler/brw_eu_defines.h

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32 #ifndef BRW_EU_DEFINES_H
  33 #define BRW_EU_DEFINES_H
  34
  35 #include <stdint.h>
  36 #include <stdlib.h>
  37 #include "util/macros.h"
  38
  39 /* The following hunk, up-to "Execution Unit" is used by both the
  40  * intel/compiler and i965 codebase. */
  41
  42 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
  43 /* Using the GNU statement expression extension */
  44 #define SET_FIELD(value, field)                                         \
  45    ({                                                                   \
  46       uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT;         \
  47       assert((fieldval & ~ field ## _MASK) == 0);                       \
  48       fieldval & field ## _MASK;                                        \
  49    })
  50
  51 #define SET_BITS(value, high, low)                                      \
  52    ({                                                                   \
  53       const uint32_t fieldval = (uint32_t)(value) << (low);             \
  54       assert((fieldval & ~INTEL_MASK(high, low)) == 0);                 \
  55       fieldval & INTEL_MASK(high, low);                                 \
  56    })
  57
  58 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
  59 #define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
  60
  61 #define _3DPRIM_POINTLIST         0x01
  62 #define _3DPRIM_LINELIST          0x02
  63 #define _3DPRIM_LINESTRIP         0x03
  64 #define _3DPRIM_TRILIST           0x04
  65 #define _3DPRIM_TRISTRIP          0x05
  66 #define _3DPRIM_TRIFAN            0x06
  67 #define _3DPRIM_QUADLIST          0x07
  68 #define _3DPRIM_QUADSTRIP         0x08
  69 #define _3DPRIM_LINELIST_ADJ      0x09 /* G45+ */
  70 #define _3DPRIM_LINESTRIP_ADJ     0x0A /* G45+ */
  71 #define _3DPRIM_TRILIST_ADJ       0x0B /* G45+ */
  72 #define _3DPRIM_TRISTRIP_ADJ      0x0C /* G45+ */
  73 #define _3DPRIM_TRISTRIP_REVERSE  0x0D
  74 #define _3DPRIM_POLYGON           0x0E
  75 #define _3DPRIM_RECTLIST          0x0F
  76 #define _3DPRIM_LINELOOP          0x10
  77 #define _3DPRIM_POINTLIST_BF      0x11
  78 #define _3DPRIM_LINESTRIP_CONT    0x12
  79 #define _3DPRIM_LINESTRIP_BF      0x13
  80 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
  81 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
  82 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
  83
  84 /* Bitfields for the URB_WRITE message, DW2 of message header: */
  85 #define URB_WRITE_PRIM_END              0x1
  86 #define URB_WRITE_PRIM_START            0x2
  87 #define URB_WRITE_PRIM_TYPE_SHIFT       2
  88
  89 #define BRW_SPRITE_POINT_ENABLE  16
  90
  91 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT          0
  92 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID          1
  93
  94 /* Execution Unit (EU) defines
  95  */
  96
  97 #define BRW_ALIGN_1   0
  98 #define BRW_ALIGN_16  1
  99
 100 #define BRW_ADDRESS_DIRECT                        0
 101 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER    1
 102
 103 #define BRW_CHANNEL_X     0
 104 #define BRW_CHANNEL_Y     1
 105 #define BRW_CHANNEL_Z     2
 106 #define BRW_CHANNEL_W     3
 107
 108 enum brw_compression {
 109    BRW_COMPRESSION_NONE       = 0,
 110    BRW_COMPRESSION_2NDHALF    = 1,
 111    BRW_COMPRESSION_COMPRESSED = 2,
 112 };
 113
 114 #define GEN6_COMPRESSION_1Q             0
 115 #define GEN6_COMPRESSION_2Q             1
 116 #define GEN6_COMPRESSION_3Q             2
 117 #define GEN6_COMPRESSION_4Q             3
 118 #define GEN6_COMPRESSION_1H             0
 119 #define GEN6_COMPRESSION_2H             2
 120
 121 enum PACKED brw_conditional_mod {
 122    BRW_CONDITIONAL_NONE = 0,
 123    BRW_CONDITIONAL_Z    = 1,
 124    BRW_CONDITIONAL_NZ   = 2,
 125    BRW_CONDITIONAL_EQ   = 1,    /* Z */
 126    BRW_CONDITIONAL_NEQ  = 2,    /* NZ */
 127    BRW_CONDITIONAL_G    = 3,
 128    BRW_CONDITIONAL_GE   = 4,
 129    BRW_CONDITIONAL_L    = 5,
 130    BRW_CONDITIONAL_LE   = 6,
 131    BRW_CONDITIONAL_R    = 7,    /* Gen <= 5 */
 132    BRW_CONDITIONAL_O    = 8,
 133    BRW_CONDITIONAL_U    = 9,
 134 };
 135
 136 #define BRW_DEBUG_NONE        0
 137 #define BRW_DEBUG_BREAKPOINT  1
 138
 139 #define BRW_DEPENDENCY_NORMAL         0
 140 #define BRW_DEPENDENCY_NOTCLEARED     1
 141 #define BRW_DEPENDENCY_NOTCHECKED     2
 142 #define BRW_DEPENDENCY_DISABLE        3
 143
 144 enum PACKED brw_execution_size {
 145    BRW_EXECUTE_1  = 0,
 146    BRW_EXECUTE_2  = 1,
 147    BRW_EXECUTE_4  = 2,
 148    BRW_EXECUTE_8  = 3,
 149    BRW_EXECUTE_16 = 4,
 150    BRW_EXECUTE_32 = 5,
 151 };
 152
 153 enum PACKED brw_horizontal_stride {
 154    BRW_HORIZONTAL_STRIDE_0 = 0,
 155    BRW_HORIZONTAL_STRIDE_1 = 1,
 156    BRW_HORIZONTAL_STRIDE_2 = 2,
 157    BRW_HORIZONTAL_STRIDE_4 = 3,
 158 };
 159
 160 enum PACKED gen10_align1_3src_src_horizontal_stride {
 161    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0,
 162    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1,
 163    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2,
 164    BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3,
 165 };
 166
 167 enum PACKED gen10_align1_3src_dst_horizontal_stride {
 168    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0,
 169    BRW_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1,
 170 };
 171
 172 #define BRW_INSTRUCTION_NORMAL    0
 173 #define BRW_INSTRUCTION_SATURATE  1
 174
 175 #define BRW_MASK_ENABLE   0
 176 #define BRW_MASK_DISABLE  1
 177
 178 /** @{
 179  *
 180  * Gen6 has replaced "mask enable/disable" with WECtrl, which is
 181  * effectively the same but much simpler to think about.  Now, there
 182  * are two contributors ANDed together to whether channels are
 183  * executed: The predication on the instruction, and the channel write
 184  * enable.
 185  */
 186 /**
 187  * This is the default value.  It means that a channel's write enable is set
 188  * if the per-channel IP is pointing at this instruction.
 189  */
 190 #define BRW_WE_NORMAL           0
 191 /**
 192  * This is used like BRW_MASK_DISABLE, and causes all channels to have
 193  * their write enable set.  Note that predication still contributes to
 194  * whether the channel actually gets written.
 195  */
 196 #define BRW_WE_ALL              1
 197 /** @} */
 198
 199 enum opcode {
 200    /* These are the actual hardware instructions. */
 201    BRW_OPCODE_ILLEGAL,
 202    BRW_OPCODE_SYNC,
 203    BRW_OPCODE_MOV,
 204    BRW_OPCODE_SEL,
 205    BRW_OPCODE_MOVI, /**< G45+ */
 206    BRW_OPCODE_NOT,
 207    BRW_OPCODE_AND,
 208    BRW_OPCODE_OR,
 209    BRW_OPCODE_XOR,
 210    BRW_OPCODE_SHR,
 211    BRW_OPCODE_SHL,
 212    BRW_OPCODE_DIM, /**< Gen7.5 only */
 213    BRW_OPCODE_SMOV, /**< Gen8+ */
 214    BRW_OPCODE_ASR,
 215    BRW_OPCODE_ROR,  /**< Gen11+ */
 216    BRW_OPCODE_ROL,  /**< Gen11+ */
 217    BRW_OPCODE_CMP,
 218    BRW_OPCODE_CMPN,
 219    BRW_OPCODE_CSEL, /**< Gen8+ */
 220    BRW_OPCODE_F32TO16, /**< Gen7 only */
 221    BRW_OPCODE_F16TO32, /**< Gen7 only */
 222    BRW_OPCODE_BFREV, /**< Gen7+ */
 223    BRW_OPCODE_BFE, /**< Gen7+ */
 224    BRW_OPCODE_BFI1, /**< Gen7+ */
 225    BRW_OPCODE_BFI2, /**< Gen7+ */
 226    BRW_OPCODE_JMPI,
 227    BRW_OPCODE_BRD, /**< Gen7+ */
 228    BRW_OPCODE_IF,
 229    BRW_OPCODE_IFF, /**< Pre-Gen6 */
 230    BRW_OPCODE_BRC, /**< Gen7+ */
 231    BRW_OPCODE_ELSE,
 232    BRW_OPCODE_ENDIF,
 233    BRW_OPCODE_DO, /**< Pre-Gen6 */
 234    BRW_OPCODE_CASE, /**< Gen6 only */
 235    BRW_OPCODE_WHILE,
 236    BRW_OPCODE_BREAK,
 237    BRW_OPCODE_CONTINUE,
 238    BRW_OPCODE_HALT,
 239    BRW_OPCODE_CALLA, /**< Gen7.5+ */
 240    BRW_OPCODE_MSAVE, /**< Pre-Gen6 */
 241    BRW_OPCODE_CALL, /**< Gen6+ */
 242    BRW_OPCODE_MREST, /**< Pre-Gen6 */
 243    BRW_OPCODE_RET, /**< Gen6+ */
 244    BRW_OPCODE_PUSH, /**< Pre-Gen6 */
 245    BRW_OPCODE_FORK, /**< Gen6 only */
 246    BRW_OPCODE_GOTO, /**< Gen8+ */
 247    BRW_OPCODE_POP, /**< Pre-Gen6 */
 248    BRW_OPCODE_WAIT,
 249    BRW_OPCODE_SEND,
 250    BRW_OPCODE_SENDC,
 251    BRW_OPCODE_SENDS, /**< Gen9+ */
 252    BRW_OPCODE_SENDSC, /**< Gen9+ */
 253    BRW_OPCODE_MATH, /**< Gen6+ */
 254    BRW_OPCODE_ADD,
 255    BRW_OPCODE_MUL,
 256    BRW_OPCODE_AVG,
 257    BRW_OPCODE_FRC,
 258    BRW_OPCODE_RNDU,
 259    BRW_OPCODE_RNDD,
 260    BRW_OPCODE_RNDE,
 261    BRW_OPCODE_RNDZ,
 262    BRW_OPCODE_MAC,
 263    BRW_OPCODE_MACH,
 264    BRW_OPCODE_LZD,
 265    BRW_OPCODE_FBH, /**< Gen7+ */
 266    BRW_OPCODE_FBL, /**< Gen7+ */
 267    BRW_OPCODE_CBIT, /**< Gen7+ */
 268    BRW_OPCODE_ADDC, /**< Gen7+ */
 269    BRW_OPCODE_SUBB, /**< Gen7+ */
 270    BRW_OPCODE_SAD2,
 271    BRW_OPCODE_SADA2,
 272    BRW_OPCODE_DP4,
 273    BRW_OPCODE_DPH,
 274    BRW_OPCODE_DP3,
 275    BRW_OPCODE_DP2,
 276    BRW_OPCODE_LINE,
 277    BRW_OPCODE_PLN, /**< G45+ */
 278    BRW_OPCODE_MAD, /**< Gen6+ */
 279    BRW_OPCODE_LRP, /**< Gen6+ */
 280    BRW_OPCODE_MADM, /**< Gen8+ */
 281    BRW_OPCODE_NENOP, /**< G45 only */
 282    BRW_OPCODE_NOP,
 283
 284    NUM_BRW_OPCODES,
 285
 286    /* These are compiler backend opcodes that get translated into other
 287     * instructions.
 288     */
 289    FS_OPCODE_FB_WRITE = NUM_BRW_OPCODES,
 290
 291    /**
 292     * Same as FS_OPCODE_FB_WRITE but expects its arguments separately as
 293     * individual sources instead of as a single payload blob. The
 294     * position/ordering of the arguments are defined by the enum
 295     * fb_write_logical_srcs.
 296     */
 297    FS_OPCODE_FB_WRITE_LOGICAL,
 298
 299    FS_OPCODE_REP_FB_WRITE,
 300
 301    FS_OPCODE_FB_READ,
 302    FS_OPCODE_FB_READ_LOGICAL,
 303
 304    SHADER_OPCODE_RCP,
 305    SHADER_OPCODE_RSQ,
 306    SHADER_OPCODE_SQRT,
 307    SHADER_OPCODE_EXP2,
 308    SHADER_OPCODE_LOG2,
 309    SHADER_OPCODE_POW,
 310    SHADER_OPCODE_INT_QUOTIENT,
 311    SHADER_OPCODE_INT_REMAINDER,
 312    SHADER_OPCODE_SIN,
 313    SHADER_OPCODE_COS,
 314
 315    /**
 316     * A generic "send" opcode.  The first two sources are the message
 317     * descriptor and extended message descriptor respectively.  The third
 318     * and optional fourth sources are the message payload
 319     */
 320    SHADER_OPCODE_SEND,
 321
 322    /**
 323     * An "undefined" write which does nothing but indicates to liveness that
 324     * we don't care about any values in the register which predate this
 325     * instruction.  Used to prevent partial writes from causing issues with
 326     * live ranges.
 327     */
 328    SHADER_OPCODE_UNDEF,
 329
 330    /**
 331     * Texture sampling opcodes.
 332     *
 333     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 334     * opcode but instead of taking a single payload blob they expect their
 335     * arguments separately as individual sources. The position/ordering of the
 336     * arguments are defined by the enum tex_logical_srcs.
 337     */
 338    SHADER_OPCODE_TEX,
 339    SHADER_OPCODE_TEX_LOGICAL,
 340    SHADER_OPCODE_TXD,
 341    SHADER_OPCODE_TXD_LOGICAL,
 342    SHADER_OPCODE_TXF,
 343    SHADER_OPCODE_TXF_LOGICAL,
 344    SHADER_OPCODE_TXF_LZ,
 345    SHADER_OPCODE_TXL,
 346    SHADER_OPCODE_TXL_LOGICAL,
 347    SHADER_OPCODE_TXL_LZ,
 348    SHADER_OPCODE_TXS,
 349    SHADER_OPCODE_TXS_LOGICAL,
 350    FS_OPCODE_TXB,
 351    FS_OPCODE_TXB_LOGICAL,
 352    SHADER_OPCODE_TXF_CMS,
 353    SHADER_OPCODE_TXF_CMS_LOGICAL,
 354    SHADER_OPCODE_TXF_CMS_W,
 355    SHADER_OPCODE_TXF_CMS_W_LOGICAL,
 356    SHADER_OPCODE_TXF_UMS,
 357    SHADER_OPCODE_TXF_UMS_LOGICAL,
 358    SHADER_OPCODE_TXF_MCS,
 359    SHADER_OPCODE_TXF_MCS_LOGICAL,
 360    SHADER_OPCODE_LOD,
 361    SHADER_OPCODE_LOD_LOGICAL,
 362    SHADER_OPCODE_TG4,
 363    SHADER_OPCODE_TG4_LOGICAL,
 364    SHADER_OPCODE_TG4_OFFSET,
 365    SHADER_OPCODE_TG4_OFFSET_LOGICAL,
 366    SHADER_OPCODE_SAMPLEINFO,
 367    SHADER_OPCODE_SAMPLEINFO_LOGICAL,
 368
 369    SHADER_OPCODE_IMAGE_SIZE_LOGICAL,
 370
 371    /**
 372     * Combines multiple sources of size 1 into a larger virtual GRF.
 373     * For example, parameters for a send-from-GRF message.  Or, updating
 374     * channels of a size 4 VGRF used to store vec4s such as texturing results.
 375     *
 376     * This will be lowered into MOVs from each source to consecutive offsets
 377     * of the destination VGRF.
 378     *
 379     * src[0] may be BAD_FILE.  If so, the lowering pass skips emitting the MOV,
 380     * but still reserves the first channel of the destination VGRF.  This can be
 381     * used to reserve space for, say, a message header set up by the generators.
 382     */
 383    SHADER_OPCODE_LOAD_PAYLOAD,
 384
 385    /**
 386     * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
 387     * acts intra-channel, obtaining the final value for each channel by
 388     * combining the sources values for the same channel, the first source
 389     * occupying the lowest bits and the last source occupying the highest
 390     * bits.
 391     */
 392    FS_OPCODE_PACK,
 393
 394    SHADER_OPCODE_SHADER_TIME_ADD,
 395
 396    /**
 397     * Typed and untyped surface access opcodes.
 398     *
 399     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 400     * opcode but instead of taking a single payload blob they expect their
 401     * arguments separately as individual sources:
 402     *
 403     * Source 0: [required] Surface coordinates.
 404     * Source 1: [optional] Operation source.
 405     * Source 2: [required] Surface index.
 406     * Source 3: [required] Number of coordinate components (as UD immediate).
 407     * Source 4: [required] Opcode-specific control immediate, same as source 2
 408     *                      of the matching non-LOGICAL opcode.
 409     */
 410    VEC4_OPCODE_UNTYPED_ATOMIC,
 411    SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
 412    SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
 413    VEC4_OPCODE_UNTYPED_SURFACE_READ,
 414    SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
 415    VEC4_OPCODE_UNTYPED_SURFACE_WRITE,
 416    SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
 417
 418    /**
 419     * Untyped A64 surface access opcodes.
 420     *
 421     * Source 0: 64-bit address
 422     * Source 1: Operational source
 423     * Source 2: [required] Opcode-specific control immediate, same as source 2
 424     *                      of the matching non-LOGICAL opcode.
 425     */
 426    SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL,
 427    SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL,
 428    SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL,
 429    SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL,
 430    SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL,
 431    SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL,
 432    SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL,
 433
 434    SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
 435    SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
 436    SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
 437
 438    SHADER_OPCODE_RND_MODE,
 439    SHADER_OPCODE_FLOAT_CONTROL_MODE,
 440
 441    /**
 442     * Byte scattered write/read opcodes.
 443     *
 444     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
 445     * opcode, but instead of taking a single payload blog they expect their
 446     * arguments separately as individual sources, like untyped write/read.
 447     */
 448    SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
 449    SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
 450    SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL,
 451    SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL,
 452
 453    /**
 454     * Memory fence messages.
 455     *
 456     * Source 0: Must be register g0, used as header.
 457     * Source 1: Immediate bool to indicate whether control is returned to the
 458     *           thread only after the fence has been honored.
 459     * Source 2: Immediate byte indicating which memory to fence.  Zero means
 460     *           global memory; GEN7_BTI_SLM means SLM (for Gen11+ only).
 461     *
 462     * Vec4 backend only uses Source 0.
 463     */
 464    SHADER_OPCODE_MEMORY_FENCE,
 465
 466    /**
 467     * Scheduling-only fence.
 468     *
 469     * Sources can be used to force a stall until the registers in those are
 470     * available.  This might generate MOVs or SYNC_NOPs (Gen12+).
 471     */
 472    FS_OPCODE_SCHEDULING_FENCE,
 473
 474    SHADER_OPCODE_GEN4_SCRATCH_READ,
 475    SHADER_OPCODE_GEN4_SCRATCH_WRITE,
 476    SHADER_OPCODE_GEN7_SCRATCH_READ,
 477
 478    /**
 479     * Gen8+ SIMD8 URB Read messages.
 480     */
 481    SHADER_OPCODE_URB_READ_SIMD8,
 482    SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT,
 483
 484    SHADER_OPCODE_URB_WRITE_SIMD8,
 485    SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
 486    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,
 487    SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT,
 488
 489    /**
 490     * Return the index of an arbitrary live channel (i.e. one of the channels
 491     * enabled in the current execution mask) and assign it to the first
 492     * component of the destination.  Expected to be used as input for the
 493     * BROADCAST pseudo-opcode.
 494     */
 495    SHADER_OPCODE_FIND_LIVE_CHANNEL,
 496
 497    /**
 498     * Return the current execution mask in the specified flag subregister.
 499     * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register.
 500     */
 501    FS_OPCODE_LOAD_LIVE_CHANNELS,
 502
 503    /**
 504     * Pick the channel from its first source register given by the index
 505     * specified as second source.  Useful for variable indexing of surfaces.
 506     *
 507     * Note that because the result of this instruction is by definition
 508     * uniform and it can always be splatted to multiple channels using a
 509     * scalar regioning mode, only the first channel of the destination region
 510     * is guaranteed to be updated, which implies that BROADCAST instructions
 511     * should usually be marked force_writemask_all.
 512     */
 513    SHADER_OPCODE_BROADCAST,
 514
 515    /* Pick the channel from its first source register given by the index
 516     * specified as second source.
 517     *
 518     * This is similar to the BROADCAST instruction except that it takes a
 519     * dynamic index and potentially puts a different value in each output
 520     * channel.
 521     */
 522    SHADER_OPCODE_SHUFFLE,
 523
 524    /* Select between src0 and src1 based on channel enables.
 525     *
 526     * This instruction copies src0 into the enabled channels of the
 527     * destination and copies src1 into the disabled channels.
 528     */
 529    SHADER_OPCODE_SEL_EXEC,
 530
 531    /* This turns into an align16 mov from src0 to dst with a swizzle
 532     * provided as an immediate in src1.
 533     */
 534    SHADER_OPCODE_QUAD_SWIZZLE,
 535
 536    /* Take every Nth element in src0 and broadcast it to the group of N
 537     * channels in which it lives in the destination.  The offset within the
 538     * cluster is given by src1 and the cluster size is given by src2.
 539     */
 540    SHADER_OPCODE_CLUSTER_BROADCAST,
 541
 542    SHADER_OPCODE_GET_BUFFER_SIZE,
 543
 544    SHADER_OPCODE_INTERLOCK,
 545
 546    VEC4_OPCODE_MOV_BYTES,
 547    VEC4_OPCODE_PACK_BYTES,
 548    VEC4_OPCODE_UNPACK_UNIFORM,
 549    VEC4_OPCODE_DOUBLE_TO_F32,
 550    VEC4_OPCODE_DOUBLE_TO_D32,
 551    VEC4_OPCODE_DOUBLE_TO_U32,
 552    VEC4_OPCODE_TO_DOUBLE,
 553    VEC4_OPCODE_PICK_LOW_32BIT,
 554    VEC4_OPCODE_PICK_HIGH_32BIT,
 555    VEC4_OPCODE_SET_LOW_32BIT,
 556    VEC4_OPCODE_SET_HIGH_32BIT,
 557
 558    FS_OPCODE_DDX_COARSE,
 559    FS_OPCODE_DDX_FINE,
 560    /**
 561     * Compute dFdy(), dFdyCoarse(), or dFdyFine().
 562     */
 563    FS_OPCODE_DDY_COARSE,
 564    FS_OPCODE_DDY_FINE,
 565    FS_OPCODE_LINTERP,
 566    FS_OPCODE_PIXEL_X,
 567    FS_OPCODE_PIXEL_Y,
 568    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
 569    FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
 570    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
 571    FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
 572    FS_OPCODE_DISCARD_JUMP,
 573    FS_OPCODE_SET_SAMPLE_ID,
 574    FS_OPCODE_PACK_HALF_2x16_SPLIT,
 575    FS_OPCODE_PLACEHOLDER_HALT,
 576    FS_OPCODE_INTERPOLATE_AT_SAMPLE,
 577    FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
 578    FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
 579
 580    VS_OPCODE_URB_WRITE,
 581    VS_OPCODE_PULL_CONSTANT_LOAD,
 582    VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
 583    VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
 584
 585    VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
 586
 587    /**
 588     * Write geometry shader output data to the URB.
 589     *
 590     * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
 591     * R0 to the first MRF.  This allows the geometry shader to override the
 592     * "Slot {0,1} Offset" fields in the message header.
 593     */
 594    GS_OPCODE_URB_WRITE,
 595
 596    /**
 597     * Write geometry shader output data to the URB and request a new URB
 598     * handle (gen6).
 599     *
 600     * This opcode doesn't do an implied move from R0 to the first MRF.
 601     */
 602    GS_OPCODE_URB_WRITE_ALLOCATE,
 603
 604    /**
 605     * Terminate the geometry shader thread by doing an empty URB write.
 606     *
 607     * This opcode doesn't do an implied move from R0 to the first MRF.  This
 608     * allows the geometry shader to override the "GS Number of Output Vertices
 609     * for Slot {0,1}" fields in the message header.
 610     */
 611    GS_OPCODE_THREAD_END,
 612
 613    /**
 614     * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
 615     *
 616     * - dst is the MRF containing the message header.
 617     *
 618     * - src0.x indicates which portion of the URB should be written to (e.g. a
 619     *   vertex number)
 620     *
 621     * - src1 is an immediate multiplier which will be applied to src0
 622     *   (e.g. the size of a single vertex in the URB).
 623     *
 624     * Note: the hardware will apply this offset *in addition to* the offset in
 625     * vec4_instruction::offset.
 626     */
 627    GS_OPCODE_SET_WRITE_OFFSET,
 628
 629    /**
 630     * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
 631     * URB_WRITE message header.
 632     *
 633     * - dst is the MRF containing the message header.
 634     *
 635     * - src0.x is the vertex count.  The upper 16 bits will be ignored.
 636     */
 637    GS_OPCODE_SET_VERTEX_COUNT,
 638
 639    /**
 640     * Set DWORD 2 of dst to the value in src.
 641     */
 642    GS_OPCODE_SET_DWORD_2,
 643
 644    /**
 645     * Prepare the dst register for storage in the "Channel Mask" fields of a
 646     * URB_WRITE message header.
 647     *
 648     * DWORD 4 of dst is shifted left by 4 bits, so that later,
 649     * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
 650     * final channel mask.
 651     *
 652     * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
 653     * form the final channel mask, DWORDs 0 and 4 of the dst register must not
 654     * have any extraneous bits set prior to execution of this opcode (that is,
 655     * they should be in the range 0x0 to 0xf).
 656     */
 657    GS_OPCODE_PREPARE_CHANNEL_MASKS,
 658
 659    /**
 660     * Set the "Channel Mask" fields of a URB_WRITE message header.
 661     *
 662     * - dst is the MRF containing the message header.
 663     *
 664     * - src.x is the channel mask, as prepared by
 665     *   GS_OPCODE_PREPARE_CHANNEL_MASKS.  DWORDs 0 and 4 are OR'ed together to
 666     *   form the final channel mask.
 667     */
 668    GS_OPCODE_SET_CHANNEL_MASKS,
 669
 670    /**
 671     * Get the "Instance ID" fields from the payload.
 672     *
 673     * - dst is the GRF for gl_InvocationID.
 674     */
 675    GS_OPCODE_GET_INSTANCE_ID,
 676
 677    /**
 678     * Send a FF_SYNC message to allocate initial URB handles (gen6).
 679     *
 680     * - dst will be used as the writeback register for the FF_SYNC operation.
 681     *
 682     * - src0 is the number of primitives written.
 683     *
 684     * - src1 is the value to hold in M0.0: number of SO vertices to write
 685     *   and number of SO primitives needed. Its value will be overwritten
 686     *   with the SVBI values if transform feedback is enabled.
 687     *
 688     * Note: This opcode uses an implicit MRF register for the ff_sync message
 689     * header, so the caller is expected to set inst->base_mrf and initialize
 690     * that MRF register to r0. This opcode will also write to this MRF register
 691     * to include the allocated URB handle so it can then be reused directly as
 692     * the header in the URB write operation we are allocating the handle for.
 693     */
 694    GS_OPCODE_FF_SYNC,
 695
 696    /**
 697     * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
 698     * register.
 699     *
 700     * - dst is the GRF where PrimitiveID information will be moved.
 701     */
 702    GS_OPCODE_SET_PRIMITIVE_ID,
 703
 704    /**
 705     * Write transform feedback data to the SVB by sending a SVB WRITE message.
 706     * Used in gen6.
 707     *
 708     * - dst is the MRF register containing the message header.
 709     *
 710     * - src0 is the register where the vertex data is going to be copied from.
 711     *
 712     * - src1 is the destination register when write commit occurs.
 713     */
 714    GS_OPCODE_SVB_WRITE,
 715
 716    /**
 717     * Set destination index in the SVB write message payload (M0.5). Used
 718     * in gen6 for transform feedback.
 719     *
 720     * - dst is the header to save the destination indices for SVB WRITE.
 721     * - src is the register that holds the destination indices value.
 722     */
 723    GS_OPCODE_SVB_SET_DST_INDEX,
 724
 725    /**
 726     * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
 727     * Used in gen6 for transform feedback.
 728     *
 729     * - dst will hold the register with the final Mx.0 value.
 730     *
 731     * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
 732     *
 733     * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
 734     *
 735     * - src2 is the value to hold in M0: number of SO vertices to write
 736     *   and number of SO primitives needed.
 737     */
 738    GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
 739
 740    /**
 741     * Terminate the compute shader.
 742     */
 743    CS_OPCODE_CS_TERMINATE,
 744
 745    /**
 746     * GLSL barrier()
 747     */
 748    SHADER_OPCODE_BARRIER,
 749
 750    /**
 751     * Calculate the high 32-bits of a 32x32 multiply.
 752     */
 753    SHADER_OPCODE_MULH,
 754
 755    /** Signed subtraction with saturation. */
 756    SHADER_OPCODE_ISUB_SAT,
 757
 758    /** Unsigned subtraction with saturation. */
 759    SHADER_OPCODE_USUB_SAT,
 760
 761    /**
 762     * A MOV that uses VxH indirect addressing.
 763     *
 764     * Source 0: A register to start from (HW_REG).
 765     * Source 1: An indirect offset (in bytes, UD GRF).
 766     * Source 2: The length of the region that could be accessed (in bytes,
 767     *           UD immediate).
 768     */
 769    SHADER_OPCODE_MOV_INDIRECT,
 770
 771    VEC4_OPCODE_URB_READ,
 772    TCS_OPCODE_GET_INSTANCE_ID,
 773    TCS_OPCODE_URB_WRITE,
 774    TCS_OPCODE_SET_INPUT_URB_OFFSETS,
 775    TCS_OPCODE_SET_OUTPUT_URB_OFFSETS,
 776    TCS_OPCODE_GET_PRIMITIVE_ID,
 777    TCS_OPCODE_CREATE_BARRIER_HEADER,
 778    TCS_OPCODE_SRC0_010_IS_ZERO,
 779    TCS_OPCODE_RELEASE_INPUT,
 780    TCS_OPCODE_THREAD_END,
 781
 782    TES_OPCODE_GET_PRIMITIVE_ID,
 783    TES_OPCODE_CREATE_INPUT_READ_HEADER,
 784    TES_OPCODE_ADD_INDIRECT_URB_OFFSET,
 785 };
 786
 787 enum brw_urb_write_flags {
 788    BRW_URB_WRITE_NO_FLAGS = 0,
 789
 790    /**
 791     * Causes a new URB entry to be allocated, and its address stored in the
 792     * destination register (gen < 7).
 793     */
 794    BRW_URB_WRITE_ALLOCATE = 0x1,
 795
 796    /**
 797     * Causes the current URB entry to be deallocated (gen < 7).
 798     */
 799    BRW_URB_WRITE_UNUSED = 0x2,
 800
 801    /**
 802     * Causes the thread to terminate.
 803     */
 804    BRW_URB_WRITE_EOT = 0x4,
 805
 806    /**
 807     * Indicates that the given URB entry is complete, and may be sent further
 808     * down the 3D pipeline (gen < 7).
 809     */
 810    BRW_URB_WRITE_COMPLETE = 0x8,
 811
 812    /**
 813     * Indicates that an additional offset (which may be different for the two
 814     * vec4 slots) is stored in the message header (gen == 7).
 815     */
 816    BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
 817
 818    /**
 819     * Indicates that the channel masks in the URB_WRITE message header should
 820     * not be overridden to 0xff (gen == 7).
 821     */
 822    BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
 823
 824    /**
 825     * Indicates that the data should be sent to the URB using the
 826     * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7).  This
 827     * causes offsets to be interpreted as multiples of an OWORD instead of an
 828     * HWORD, and only allows one OWORD to be written.
 829     */
 830    BRW_URB_WRITE_OWORD = 0x40,
 831
 832    /**
 833     * Convenient combination of flags: end the thread while simultaneously
 834     * marking the given URB entry as complete.
 835     */
 836    BRW_URB_WRITE_EOT_COMPLETE = BRW_URB_WRITE_EOT | BRW_URB_WRITE_COMPLETE,
 837
 838    /**
 839     * Convenient combination of flags: mark the given URB entry as complete
 840     * and simultaneously allocate a new one.
 841     */
 842    BRW_URB_WRITE_ALLOCATE_COMPLETE =
 843       BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
 844 };
 845
 846 enum fb_write_logical_srcs {
 847    FB_WRITE_LOGICAL_SRC_COLOR0,      /* REQUIRED */
 848    FB_WRITE_LOGICAL_SRC_COLOR1,      /* for dual source blend messages */
 849    FB_WRITE_LOGICAL_SRC_SRC0_ALPHA,
 850    FB_WRITE_LOGICAL_SRC_SRC_DEPTH,   /* gl_FragDepth */
 851    FB_WRITE_LOGICAL_SRC_DST_DEPTH,   /* GEN4-5: passthrough from thread */
 852    FB_WRITE_LOGICAL_SRC_SRC_STENCIL, /* gl_FragStencilRefARB */
 853    FB_WRITE_LOGICAL_SRC_OMASK,       /* Sample Mask (gl_SampleMask) */
 854    FB_WRITE_LOGICAL_SRC_COMPONENTS,  /* REQUIRED */
 855    FB_WRITE_LOGICAL_NUM_SRCS
 856 };
 857
 858 enum tex_logical_srcs {
 859    /** Texture coordinates */
 860    TEX_LOGICAL_SRC_COORDINATE,
 861    /** Shadow comparator */
 862    TEX_LOGICAL_SRC_SHADOW_C,
 863    /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
 864    TEX_LOGICAL_SRC_LOD,
 865    /** dPdy if the operation takes explicit derivatives */
 866    TEX_LOGICAL_SRC_LOD2,
 867    /** Min LOD */
 868    TEX_LOGICAL_SRC_MIN_LOD,
 869    /** Sample index */
 870    TEX_LOGICAL_SRC_SAMPLE_INDEX,
 871    /** MCS data */
 872    TEX_LOGICAL_SRC_MCS,
 873    /** REQUIRED: Texture surface index */
 874    TEX_LOGICAL_SRC_SURFACE,
 875    /** Texture sampler index */
 876    TEX_LOGICAL_SRC_SAMPLER,
 877    /** Texture surface bindless handle */
 878    TEX_LOGICAL_SRC_SURFACE_HANDLE,
 879    /** Texture sampler bindless handle */
 880    TEX_LOGICAL_SRC_SAMPLER_HANDLE,
 881    /** Texel offset for gathers */
 882    TEX_LOGICAL_SRC_TG4_OFFSET,
 883    /** REQUIRED: Number of coordinate components (as UD immediate) */
 884    TEX_LOGICAL_SRC_COORD_COMPONENTS,
 885    /** REQUIRED: Number of derivative components (as UD immediate) */
 886    TEX_LOGICAL_SRC_GRAD_COMPONENTS,
 887
 888    TEX_LOGICAL_NUM_SRCS,
 889 };
 890
 891 enum surface_logical_srcs {
 892    /** Surface binding table index */
 893    SURFACE_LOGICAL_SRC_SURFACE,
 894    /** Surface bindless handle */
 895    SURFACE_LOGICAL_SRC_SURFACE_HANDLE,
 896    /** Surface address; could be multi-dimensional for typed opcodes */
 897    SURFACE_LOGICAL_SRC_ADDRESS,
 898    /** Data to be written or used in an atomic op */
 899    SURFACE_LOGICAL_SRC_DATA,
 900    /** Surface number of dimensions.  Affects the size of ADDRESS */
 901    SURFACE_LOGICAL_SRC_IMM_DIMS,
 902    /** Per-opcode immediate argument.  For atomics, this is the atomic opcode */
 903    SURFACE_LOGICAL_SRC_IMM_ARG,
 904
 905    SURFACE_LOGICAL_NUM_SRCS
 906 };
 907
 908 #ifdef __cplusplus
 909 /**
 910  * Allow brw_urb_write_flags enums to be ORed together.
 911  */
 912 inline brw_urb_write_flags
 913 operator|(brw_urb_write_flags x, brw_urb_write_flags y)
 914 {
 915    return static_cast<brw_urb_write_flags>(static_cast<int>(x) |
 916                                            static_cast<int>(y));
 917 }
 918 #endif
 919
 920 enum PACKED brw_predicate {
 921    BRW_PREDICATE_NONE                =  0,
 922    BRW_PREDICATE_NORMAL              =  1,
 923    BRW_PREDICATE_ALIGN1_ANYV         =  2,
 924    BRW_PREDICATE_ALIGN1_ALLV         =  3,
 925    BRW_PREDICATE_ALIGN1_ANY2H        =  4,
 926    BRW_PREDICATE_ALIGN1_ALL2H        =  5,
 927    BRW_PREDICATE_ALIGN1_ANY4H        =  6,
 928    BRW_PREDICATE_ALIGN1_ALL4H        =  7,
 929    BRW_PREDICATE_ALIGN1_ANY8H        =  8,
 930    BRW_PREDICATE_ALIGN1_ALL8H        =  9,
 931    BRW_PREDICATE_ALIGN1_ANY16H       = 10,
 932    BRW_PREDICATE_ALIGN1_ALL16H       = 11,
 933    BRW_PREDICATE_ALIGN1_ANY32H       = 12,
 934    BRW_PREDICATE_ALIGN1_ALL32H       = 13,
 935    BRW_PREDICATE_ALIGN16_REPLICATE_X =  2,
 936    BRW_PREDICATE_ALIGN16_REPLICATE_Y =  3,
 937    BRW_PREDICATE_ALIGN16_REPLICATE_Z =  4,
 938    BRW_PREDICATE_ALIGN16_REPLICATE_W =  5,
 939    BRW_PREDICATE_ALIGN16_ANY4H       =  6,
 940    BRW_PREDICATE_ALIGN16_ALL4H       =  7,
 941 };
 942
 943 enum PACKED brw_reg_file {
 944    BRW_ARCHITECTURE_REGISTER_FILE = 0,
 945    BRW_GENERAL_REGISTER_FILE      = 1,
 946    BRW_MESSAGE_REGISTER_FILE      = 2,
 947    BRW_IMMEDIATE_VALUE            = 3,
 948
 949    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
 950    FIXED_GRF = BRW_GENERAL_REGISTER_FILE,
 951    MRF = BRW_MESSAGE_REGISTER_FILE,
 952    IMM = BRW_IMMEDIATE_VALUE,
 953
 954    /* These are not hardware values */
 955    VGRF,
 956    ATTR,
 957    UNIFORM, /* prog_data->params[reg] */
 958    BAD_FILE,
 959 };
 960
 961 enum PACKED gen10_align1_3src_reg_file {
 962    BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0,
 963    BRW_ALIGN1_3SRC_IMMEDIATE_VALUE       = 1, /* src0, src2 */
 964    BRW_ALIGN1_3SRC_ACCUMULATOR           = 1, /* dest, src1 */
 965 };
 966
 967 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction
 968  * word is "Execution Datatype" which controls whether the instruction operates
 969  * on float or integer types. The register arguments have fields that offer
 970  * more fine control their respective types.
 971  */
 972 enum PACKED gen10_align1_3src_exec_type {
 973    BRW_ALIGN1_3SRC_EXEC_TYPE_INT   = 0,
 974    BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1,
 975 };
 976
 977 #define BRW_ARF_NULL                  0x00
 978 #define BRW_ARF_ADDRESS               0x10
 979 #define BRW_ARF_ACCUMULATOR           0x20
 980 #define BRW_ARF_FLAG                  0x30
 981 #define BRW_ARF_MASK                  0x40
 982 #define BRW_ARF_MASK_STACK            0x50
 983 #define BRW_ARF_MASK_STACK_DEPTH      0x60
 984 #define BRW_ARF_STATE                 0x70
 985 #define BRW_ARF_CONTROL               0x80
 986 #define BRW_ARF_NOTIFICATION_COUNT    0x90
 987 #define BRW_ARF_IP                    0xA0
 988 #define BRW_ARF_TDR                   0xB0
 989 #define BRW_ARF_TIMESTAMP             0xC0
 990
 991 #define BRW_MRF_COMPR4                  (1 << 7)
 992
 993 #define BRW_AMASK   0
 994 #define BRW_IMASK   1
 995 #define BRW_LMASK   2
 996 #define BRW_CMASK   3
 997
 998
 999
1000 #define BRW_THREAD_NORMAL     0
1001 #define BRW_THREAD_ATOMIC     1
1002 #define BRW_THREAD_SWITCH     2
1003
1004 enum PACKED brw_vertical_stride {
1005    BRW_VERTICAL_STRIDE_0               = 0,
1006    BRW_VERTICAL_STRIDE_1               = 1,
1007    BRW_VERTICAL_STRIDE_2               = 2,
1008    BRW_VERTICAL_STRIDE_4               = 3,
1009    BRW_VERTICAL_STRIDE_8               = 4,
1010    BRW_VERTICAL_STRIDE_16              = 5,
1011    BRW_VERTICAL_STRIDE_32              = 6,
1012    BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
1013 };
1014
1015 enum PACKED gen10_align1_3src_vertical_stride {
1016    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0,
1017    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1,
1018    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1,
1019    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2,
1020    BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3,
1021 };
1022
1023 enum PACKED brw_width {
1024    BRW_WIDTH_1  = 0,
1025    BRW_WIDTH_2  = 1,
1026    BRW_WIDTH_4  = 2,
1027    BRW_WIDTH_8  = 3,
1028    BRW_WIDTH_16 = 4,
1029 };
1030
1031 /**
1032  * Gen12+ SWSB SBID synchronization mode.
1033  *
1034  * This is represented as a bitmask including any required SBID token
1035  * synchronization modes, used to synchronize out-of-order instructions.  Only
1036  * the strongest mode of the mask will be provided to the hardware in the SWSB
1037  * field of an actual hardware instruction, but virtual instructions may be
1038  * able to take into account multiple of them.
1039  */
1040 enum tgl_sbid_mode {
1041    TGL_SBID_NULL = 0,
1042    TGL_SBID_SRC = 1,
1043    TGL_SBID_DST = 2,
1044    TGL_SBID_SET = 4
1045 };
1046
1047 #ifdef __cplusplus
1048 /**
1049  * Allow bitwise arithmetic of tgl_sbid_mode enums.
1050  */
1051 inline tgl_sbid_mode
1052 operator|(tgl_sbid_mode x, tgl_sbid_mode y)
1053 {
1054    return tgl_sbid_mode(unsigned(x) | unsigned(y));
1055 }
1056
1057 inline tgl_sbid_mode
1058 operator&(tgl_sbid_mode x, tgl_sbid_mode y)
1059 {
1060    return tgl_sbid_mode(unsigned(x) & unsigned(y));
1061 }
1062
1063 inline tgl_sbid_mode &
1064 operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
1065 {
1066    return x = x | y;
1067 }
1068
1069 #endif
1070
1071 /**
1072  * Logical representation of the SWSB scheduling information of a hardware
1073  * instruction.  The binary representation is slightly more compact.
1074  */
1075 struct tgl_swsb {
1076    unsigned regdist : 3;
1077    unsigned sbid : 4;
1078    enum tgl_sbid_mode mode : 3;
1079 };
1080
1081 /**
1082  * Construct a scheduling annotation with a single RegDist dependency.  This
1083  * synchronizes with the completion of the d-th previous in-order instruction.
1084  * The index is one-based, zero causes a no-op tgl_swsb to be constructed.
1085  */
1086 static inline struct tgl_swsb
1087 tgl_swsb_regdist(unsigned d)
1088 {
1089    const struct tgl_swsb swsb = { d };
1090    assert(swsb.regdist == d);
1091    return swsb;
1092 }
1093
1094 /**
1095  * Construct a scheduling annotation that synchronizes with the specified SBID
1096  * token.
1097  */
1098 static inline struct tgl_swsb
1099 tgl_swsb_sbid(enum tgl_sbid_mode mode, unsigned sbid)
1100 {
1101    const struct tgl_swsb swsb = { 0, sbid, mode };
1102    assert(swsb.sbid == sbid);
1103    return swsb;
1104 }
1105
1106 /**
1107  * Construct a no-op scheduling annotation.
1108  */
1109 static inline struct tgl_swsb
1110 tgl_swsb_null(void)
1111 {
1112    return tgl_swsb_regdist(0);
1113 }
1114
1115 /**
1116  * Return a scheduling annotation that allocates the same SBID synchronization
1117  * token as \p swsb.  In addition it will synchronize against a previous
1118  * in-order instruction if \p regdist is non-zero.
1119  */
1120 static inline struct tgl_swsb
1121 tgl_swsb_dst_dep(struct tgl_swsb swsb, unsigned regdist)
1122 {
1123    swsb.regdist = regdist;
1124    swsb.mode = swsb.mode & TGL_SBID_SET;
1125    return swsb;
1126 }
1127
1128 /**
1129  * Return a scheduling annotation that synchronizes against the same SBID and
1130  * RegDist dependencies as \p swsb, but doesn't allocate any SBID token.
1131  */
1132 static inline struct tgl_swsb
1133 tgl_swsb_src_dep(struct tgl_swsb swsb)
1134 {
1135    swsb.mode = swsb.mode & (TGL_SBID_SRC | TGL_SBID_DST);
1136    return swsb;
1137 }
1138
1139 /**
1140  * Convert the provided tgl_swsb to the hardware's binary representation of an
1141  * SWSB annotation.
1142  */
1143 static inline uint8_t
1144 tgl_swsb_encode(struct tgl_swsb swsb)
1145 {
1146    if (!swsb.mode) {
1147       return swsb.regdist;
1148    } else if (swsb.regdist) {
1149       return 0x80 | swsb.regdist << 4 | swsb.sbid;
1150    } else {
1151       return swsb.sbid | (swsb.mode & TGL_SBID_SET ? 0x40 :
1152                           swsb.mode & TGL_SBID_DST ? 0x20 : 0x30);
1153    }
1154 }
1155
1156 /**
1157  * Convert the provided binary representation of an SWSB annotation to a
1158  * tgl_swsb.
1159  */
1160 static inline struct tgl_swsb
1161 tgl_swsb_decode(enum opcode opcode, uint8_t x)
1162 {
1163    if (x & 0x80) {
1164       const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
1165                                      (opcode == BRW_OPCODE_SEND ||
1166                                       opcode == BRW_OPCODE_SENDC ||
1167                                       opcode == BRW_OPCODE_MATH) ?
1168                                      TGL_SBID_SET : TGL_SBID_DST };
1169       return swsb;
1170    } else if ((x & 0x70) == 0x20) {
1171       return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);
1172    } else if ((x & 0x70) == 0x30) {
1173       return tgl_swsb_sbid(TGL_SBID_SRC, x & 0xfu);
1174    } else if ((x & 0x70) == 0x40) {
1175       return tgl_swsb_sbid(TGL_SBID_SET, x & 0xfu);
1176    } else {
1177       return tgl_swsb_regdist(x & 0x7u);
1178    }
1179 }
1180
1181 enum tgl_sync_function {
1182    TGL_SYNC_NOP = 0x0,
1183    TGL_SYNC_ALLRD = 0x2,
1184    TGL_SYNC_ALLWR = 0x3,
1185    TGL_SYNC_BAR = 0xe,
1186    TGL_SYNC_HOST = 0xf
1187 };
1188
1189 /**
1190  * Message target: Shared Function ID for where to SEND a message.
1191  *
1192  * These are enumerated in the ISA reference under "send - Send Message".
1193  * In particular, see the following tables:
1194  * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1195  * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1196  * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1197  */
1198 enum brw_message_target {
1199    BRW_SFID_NULL                     = 0,
1200    BRW_SFID_MATH                     = 1, /* Only valid on Gen4-5 */
1201    BRW_SFID_SAMPLER                  = 2,
1202    BRW_SFID_MESSAGE_GATEWAY          = 3,
1203    BRW_SFID_DATAPORT_READ            = 4,
1204    BRW_SFID_DATAPORT_WRITE           = 5,
1205    BRW_SFID_URB                      = 6,
1206    BRW_SFID_THREAD_SPAWNER           = 7,
1207    BRW_SFID_VME                      = 8,
1208
1209    GEN6_SFID_DATAPORT_SAMPLER_CACHE  = 4,
1210    GEN6_SFID_DATAPORT_RENDER_CACHE   = 5,
1211    GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
1212
1213    GEN7_SFID_DATAPORT_DATA_CACHE     = 10,
1214    GEN7_SFID_PIXEL_INTERPOLATOR      = 11,
1215    HSW_SFID_DATAPORT_DATA_CACHE_1    = 12,
1216    HSW_SFID_CRE                      = 13,
1217 };
1218
1219 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE     10
1220
1221 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
1222 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
1223 #define BRW_SAMPLER_RETURN_FORMAT_SINT32      3
1224
1225 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE              0
1226 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE             0
1227 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS        0
1228 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX             1
1229 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD        1
1230 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD         1
1231 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS  2
1232 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS    2
1233 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE    0
1234 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE     2
1235 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1236 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1237 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE  1
1238 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO           2
1239 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO            2
1240 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD                3
1241 #define BRW_SAMPLER_MESSAGE_SIMD8_LD                  3
1242 #define BRW_SAMPLER_MESSAGE_SIMD16_LD                 3
1243
1244 #define GEN5_SAMPLER_MESSAGE_SAMPLE              0
1245 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS         1
1246 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD          2
1247 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE      3
1248 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS       4
1249 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1250 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE  6
1251 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD           7
1252 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4      8
1253 #define GEN5_SAMPLER_MESSAGE_LOD                 9
1254 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO      10
1255 #define GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO   11
1256 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C    16
1257 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO   17
1258 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1259 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1260 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LZ           24
1261 #define GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ         25
1262 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ        26
1263 #define GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W     28
1264 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
1265 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
1266 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS       31
1267
1268 /* for GEN5 only */
1269 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2                   0
1270 #define BRW_SAMPLER_SIMD_MODE_SIMD8                     1
1271 #define BRW_SAMPLER_SIMD_MODE_SIMD16                    2
1272 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64                 3
1273
1274 /* GEN9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
1275  * behavior by setting bit 22 of dword 2 in the message header. */
1276 #define GEN9_SAMPLER_SIMD_MODE_SIMD8D                   0
1277 #define GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2        (1 << 22)
1278
1279 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW   0
1280 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH  1
1281 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS     2
1282 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS     3
1283 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS     4
1284 #define BRW_DATAPORT_OWORD_BLOCK_DWORDS(n)              \
1285    ((n) == 4 ? BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW :    \
1286     (n) == 8 ? BRW_DATAPORT_OWORD_BLOCK_2_OWORDS :      \
1287     (n) == 16 ? BRW_DATAPORT_OWORD_BLOCK_4_OWORDS :     \
1288     (n) == 32 ? BRW_DATAPORT_OWORD_BLOCK_8_OWORDS :     \
1289     (abort(), ~0))
1290
1291 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD     0
1292 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS    2
1293
1294 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS   2
1295 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS  3
1296
1297 /* This one stays the same across generations. */
1298 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ          0
1299 /* GEN4 */
1300 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     1
1301 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          2
1302 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      3
1303 /* G45, GEN5 */
1304 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ         1
1305 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1306 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ      3
1307 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1308 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1309 /* GEN6 */
1310 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ        1
1311 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
1312 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ          4
1313 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ  5
1314 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
1315
1316 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE      0
1317 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE    1
1318 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE   2
1319
1320 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE                0
1321 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED     1
1322 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01         2
1323 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23         3
1324 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01       4
1325
1326 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE                0
1327 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE           1
1328 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE                2
1329 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE            3
1330 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE              4
1331 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE     5
1332 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE               7
1333
1334 /* GEN6 */
1335 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE              7
1336 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE               8
1337 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE          9
1338 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE               10
1339 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE           11
1340 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE             12
1341 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE               13
1342 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE       14
1343
1344 /* GEN7 */
1345 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_READ                           4
1346 #define GEN7_DATAPORT_RC_TYPED_SURFACE_READ                         5
1347 #define GEN7_DATAPORT_RC_TYPED_ATOMIC_OP                            6
1348 #define GEN7_DATAPORT_RC_MEMORY_FENCE                               7
1349 #define GEN7_DATAPORT_RC_MEDIA_BLOCK_WRITE                          10
1350 #define GEN7_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1351 #define GEN7_DATAPORT_RC_TYPED_SURFACE_WRITE                        13
1352 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ                           0
1353 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ                 1
1354 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ                      2
1355 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ                       3
1356 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ                        4
1357 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ                       5
1358 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP                          6
1359 #define GEN7_DATAPORT_DC_MEMORY_FENCE                               7
1360 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE                          8
1361 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE                     10
1362 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE                      11
1363 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE                       12
1364 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE                      13
1365
1366 #define GEN7_DATAPORT_SCRATCH_READ                            ((1 << 18) | \
1367                                                                (0 << 17))
1368 #define GEN7_DATAPORT_SCRATCH_WRITE                           ((1 << 18) | \
1369                                                                (1 << 17))
1370 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT                        12
1371
1372 #define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET     0
1373 #define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE            1
1374 #define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID          2
1375 #define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET   3
1376
1377 /* HSW */
1378 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ                      0
1379 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ            1
1380 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ                 2
1381 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ                  3
1382 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ                   4
1383 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE                          7
1384 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE                     8
1385 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE                10
1386 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE                 11
1387 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE                  12
1388
1389 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ                  1
1390 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP                     2
1391 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2             3
1392 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ                      4
1393 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ                    5
1394 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP                       6
1395 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2               7
1396 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE                 9
1397 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE                     10
1398 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP                     11
1399 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2             12
1400 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE                   13
1401 #define GEN9_DATAPORT_DC_PORT1_A64_SCATTERED_READ                   0x10
1402 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ             0x11
1403 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP                0x12
1404 #define GEN8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE            0x19
1405 #define GEN8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE                  0x1a
1406 #define GEN9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP              0x1b
1407 #define GEN9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP          0x1d
1408
1409 /* GEN9 */
1410 #define GEN9_DATAPORT_RC_RENDER_TARGET_WRITE                        12
1411 #define GEN9_DATAPORT_RC_RENDER_TARGET_READ                         13
1412
1413 /* A64 scattered message subtype */
1414 #define GEN8_A64_SCATTERED_SUBTYPE_BYTE                             0
1415 #define GEN8_A64_SCATTERED_SUBTYPE_DWORD                            1
1416 #define GEN8_A64_SCATTERED_SUBTYPE_QWORD                            2
1417 #define GEN8_A64_SCATTERED_SUBTYPE_HWORD                            3
1418
1419 /* Dataport special binding table indices: */
1420 #define BRW_BTI_STATELESS                255
1421 #define GEN7_BTI_SLM                     254
1422
1423 #define HSW_BTI_STATELESS_LOCALLY_COHERENT 255
1424 #define HSW_BTI_STATELESS_NON_COHERENT 253
1425 #define HSW_BTI_STATELESS_GLOBALLY_COHERENT 252
1426 #define HSW_BTI_STATELESS_LLC_COHERENT 251
1427 #define HSW_BTI_STATELESS_L3_UNCACHED 250
1428
1429 /* The hardware docs are a bit contradictory here.  On Haswell, where they
1430  * first added cache ability control, there were 5 different cache modes (see
1431  * HSW_BTI_STATELESS_* above).  On Broadwell, they reduced to two:
1432  *
1433  *  - IA-Coherent (BTI=255): Coherent within Gen and coherent within the
1434  *    entire IA cache memory hierarchy.
1435  *
1436  *  - Non-Coherent (BTI=253): Coherent within Gen, same cache type.
1437  *
1438  * Information about stateless cache coherency can be found in the "A32
1439  * Stateless" section of the "3D Media GPGPU" volume of the PRM for each
1440  * hardware generation.
1441  *
1442  * Unfortunately, the docs for MDC_STATELESS appear to have been copied and
1443  * pasted from Haswell and give the Haswell definitions for the BTI values of
1444  * 255 and 253 including a warning about accessing 253 surfaces from multiple
1445  * threads.  This seems to be a copy+paste error and the definitions from the
1446  * "A32 Stateless" section should be trusted instead.
1447  *
1448  * Note that because the DRM sets bit 4 of HDC_CHICKEN0 on BDW, CHV and at
1449  * least some pre-production steppings of SKL due to WaForceEnableNonCoherent,
1450  * HDC memory access may have been overridden by the kernel to be non-coherent
1451  * (matching the behavior of the same BTI on pre-Gen8 hardware) and BTI 255
1452  * may actually be an alias for BTI 253.
1453  */
1454 #define GEN8_BTI_STATELESS_IA_COHERENT   255
1455 #define GEN8_BTI_STATELESS_NON_COHERENT  253
1456 #define GEN9_BTI_BINDLESS                252
1457
1458 /* Dataport atomic operations for Untyped Atomic Integer Operation message
1459  * (and others).
1460  */
1461 #define BRW_AOP_AND                   1
1462 #define BRW_AOP_OR                    2
1463 #define BRW_AOP_XOR                   3
1464 #define BRW_AOP_MOV                   4
1465 #define BRW_AOP_INC                   5
1466 #define BRW_AOP_DEC                   6
1467 #define BRW_AOP_ADD                   7
1468 #define BRW_AOP_SUB                   8
1469 #define BRW_AOP_REVSUB                9
1470 #define BRW_AOP_IMAX                  10
1471 #define BRW_AOP_IMIN                  11
1472 #define BRW_AOP_UMAX                  12
1473 #define BRW_AOP_UMIN                  13
1474 #define BRW_AOP_CMPWR                 14
1475 #define BRW_AOP_PREDEC                15
1476
1477 /* Dataport atomic operations for Untyped Atomic Float Operation message. */
1478 #define BRW_AOP_FMAX                  1
1479 #define BRW_AOP_FMIN                  2
1480 #define BRW_AOP_FCMPWR                3
1481
1482 #define BRW_MATH_FUNCTION_INV                              1
1483 #define BRW_MATH_FUNCTION_LOG                              2
1484 #define BRW_MATH_FUNCTION_EXP                              3
1485 #define BRW_MATH_FUNCTION_SQRT                             4
1486 #define BRW_MATH_FUNCTION_RSQ                              5
1487 #define BRW_MATH_FUNCTION_SIN                              6
1488 #define BRW_MATH_FUNCTION_COS                              7
1489 #define BRW_MATH_FUNCTION_SINCOS                           8 /* gen4, gen5 */
1490 #define BRW_MATH_FUNCTION_FDIV                             9 /* gen6+ */
1491 #define BRW_MATH_FUNCTION_POW                              10
1492 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER   11
1493 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT                 12
1494 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER                13
1495 #define GEN8_MATH_FUNCTION_INVM                            14
1496 #define GEN8_MATH_FUNCTION_RSQRTM                          15
1497
1498 #define BRW_MATH_INTEGER_UNSIGNED     0
1499 #define BRW_MATH_INTEGER_SIGNED       1
1500
1501 #define BRW_MATH_PRECISION_FULL        0
1502 #define BRW_MATH_PRECISION_PARTIAL     1
1503
1504 #define BRW_MATH_SATURATE_NONE         0
1505 #define BRW_MATH_SATURATE_SATURATE     1
1506
1507 #define BRW_MATH_DATA_VECTOR  0
1508 #define BRW_MATH_DATA_SCALAR  1
1509
1510 #define BRW_URB_OPCODE_WRITE_HWORD  0
1511 #define BRW_URB_OPCODE_WRITE_OWORD  1
1512 #define BRW_URB_OPCODE_READ_HWORD   2
1513 #define BRW_URB_OPCODE_READ_OWORD   3
1514 #define GEN7_URB_OPCODE_ATOMIC_MOV  4
1515 #define GEN7_URB_OPCODE_ATOMIC_INC  5
1516 #define GEN8_URB_OPCODE_ATOMIC_ADD  6
1517 #define GEN8_URB_OPCODE_SIMD8_WRITE 7
1518 #define GEN8_URB_OPCODE_SIMD8_READ  8
1519
1520 #define BRW_URB_SWIZZLE_NONE          0
1521 #define BRW_URB_SWIZZLE_INTERLEAVE    1
1522 #define BRW_URB_SWIZZLE_TRANSPOSE     2
1523
1524 #define BRW_SCRATCH_SPACE_SIZE_1K     0
1525 #define BRW_SCRATCH_SPACE_SIZE_2K     1
1526 #define BRW_SCRATCH_SPACE_SIZE_4K     2
1527 #define BRW_SCRATCH_SPACE_SIZE_8K     3
1528 #define BRW_SCRATCH_SPACE_SIZE_16K    4
1529 #define BRW_SCRATCH_SPACE_SIZE_32K    5
1530 #define BRW_SCRATCH_SPACE_SIZE_64K    6
1531 #define BRW_SCRATCH_SPACE_SIZE_128K   7
1532 #define BRW_SCRATCH_SPACE_SIZE_256K   8
1533 #define BRW_SCRATCH_SPACE_SIZE_512K   9
1534 #define BRW_SCRATCH_SPACE_SIZE_1M     10
1535 #define BRW_SCRATCH_SPACE_SIZE_2M     11
1536
1537 #define BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY         0
1538 #define BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY        1
1539 #define BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG          2
1540 #define BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP        3
1541 #define BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG          4
1542 #define BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5
1543 #define BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE      6
1544
1545
1546 /* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1547  * is 2^9, or 512.  It's counted in multiples of 64 bytes.
1548  *
1549  * Identical for VS, DS, and HS.
1550  */
1551 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES                (512*64)
1552 #define GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES                (512*64)
1553 #define GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES                (512*64)
1554 #define GEN7_MAX_VS_URB_ENTRY_SIZE_BYTES                (512*64)
1555
1556 /* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
1557  * (128 bytes) URB rows and the maximum allowed value is 5 rows.
1558  */
1559 #define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES                (5*128)
1560
1561 /* GS Thread Payload
1562  */
1563
1564 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1565  * counted in multiples of 16 bytes.
1566  */
1567 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES            (62*16)
1568
1569
1570 /* R0 */
1571 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT              27
1572
1573 /* CR0.0[5:4] Floating-Point Rounding Modes
1574  *  Skylake PRM, Volume 7 Part 1, "Control Register", page 756
1575  */
1576
1577 #define BRW_CR0_RND_MODE_MASK     0x30
1578 #define BRW_CR0_RND_MODE_SHIFT    4
1579
1580 enum PACKED brw_rnd_mode {
1581    BRW_RND_MODE_RTNE = 0,  /* Round to Nearest or Even */
1582    BRW_RND_MODE_RU = 1,    /* Round Up, toward +inf */
1583    BRW_RND_MODE_RD = 2,    /* Round Down, toward -inf */
1584    BRW_RND_MODE_RTZ = 3,   /* Round Toward Zero */
1585    BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
1586 };
1587
1588 #define BRW_CR0_FP64_DENORM_PRESERVE (1 << 6)
1589 #define BRW_CR0_FP32_DENORM_PRESERVE (1 << 7)
1590 #define BRW_CR0_FP16_DENORM_PRESERVE (1 << 10)
1591
1592 #define BRW_CR0_FP_MODE_MASK (BRW_CR0_FP64_DENORM_PRESERVE | \
1593                               BRW_CR0_FP32_DENORM_PRESERVE | \
1594                               BRW_CR0_FP16_DENORM_PRESERVE | \
1595                               BRW_CR0_RND_MODE_MASK)
1596
1597 /* MDC_DS - Data Size Message Descriptor Control Field
1598  * Skylake PRM, Volume 2d, page 129
1599  *
1600  * Specifies the number of Bytes to be read or written per Dword used at
1601  * byte_scattered read/write and byte_scaled read/write messages.
1602  */
1603 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE     0
1604 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD     1
1605 #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD    2
1606
1607 #endif /* BRW_EU_DEFINES_H */