2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_eu_validate.c
26 * This file implements a pass that validates shader assembly.
31 /* We're going to do lots of string concatenation, so this should help. */
38 cat(struct string
*dest
, const struct string src
)
40 dest
->str
= realloc(dest
->str
, dest
->len
+ src
.len
+ 1);
41 memcpy(dest
->str
+ dest
->len
, src
.str
, src
.len
);
42 dest
->str
[dest
->len
+ src
.len
] = '\0';
43 dest
->len
= dest
->len
+ src
.len
;
45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
47 #define error(str) "\tERROR: " str "\n"
48 #define ERROR_INDENT "\t "
50 #define ERROR(msg) ERROR_IF(true, msg)
51 #define ERROR_IF(cond, msg) \
54 CAT(error_msg, error(msg)); \
58 #define CHECK(func, args...) \
60 struct string __msg = func(devinfo, inst, ##args); \
62 cat(&error_msg, __msg); \
68 inst_is_send(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
70 switch (brw_inst_opcode(devinfo
, inst
)) {
72 case BRW_OPCODE_SENDC
:
73 case BRW_OPCODE_SENDS
:
74 case BRW_OPCODE_SENDSC
:
82 signed_type(unsigned type
)
85 case BRW_HW_REG_TYPE_UD
: return BRW_HW_REG_TYPE_D
;
86 case BRW_HW_REG_TYPE_UW
: return BRW_HW_REG_TYPE_W
;
87 case BRW_HW_REG_NON_IMM_TYPE_UB
: return BRW_HW_REG_NON_IMM_TYPE_B
;
88 case GEN8_HW_REG_TYPE_UQ
: return GEN8_HW_REG_TYPE_Q
;
94 inst_is_raw_move(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
96 unsigned dst_type
= signed_type(brw_inst_dst_reg_type(devinfo
, inst
));
97 unsigned src_type
= signed_type(brw_inst_src0_reg_type(devinfo
, inst
));
99 if (brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
100 (brw_inst_src0_negate(devinfo
, inst
) ||
101 brw_inst_src0_abs(devinfo
, inst
)))
104 return brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MOV
&&
105 brw_inst_saturate(devinfo
, inst
) == 0 &&
106 dst_type
== src_type
;
110 dst_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
112 return brw_inst_dst_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
113 brw_inst_dst_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
117 src0_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
119 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
120 brw_inst_src0_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
124 src1_is_null(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
126 return brw_inst_src1_reg_file(devinfo
, inst
) == BRW_ARCHITECTURE_REGISTER_FILE
&&
127 brw_inst_src1_da_reg_nr(devinfo
, inst
) == BRW_ARF_NULL
;
131 src0_is_grf(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
133 return brw_inst_src0_reg_file(devinfo
, inst
) == BRW_GENERAL_REGISTER_FILE
;
137 src0_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
139 return brw_inst_src0_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
140 brw_inst_src0_width(devinfo
, inst
) == BRW_WIDTH_1
&&
141 brw_inst_src0_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
145 src1_has_scalar_region(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
147 return brw_inst_src1_vstride(devinfo
, inst
) == BRW_VERTICAL_STRIDE_0
&&
148 brw_inst_src1_width(devinfo
, inst
) == BRW_WIDTH_1
&&
149 brw_inst_src1_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
;
153 num_sources_from_inst(const struct gen_device_info
*devinfo
,
154 const brw_inst
*inst
)
156 const struct opcode_desc
*desc
=
157 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
158 unsigned math_function
;
160 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
161 math_function
= brw_inst_math_function(devinfo
, inst
);
162 } else if (devinfo
->gen
< 6 &&
163 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
164 if (brw_inst_sfid(devinfo
, inst
) == BRW_SFID_MATH
) {
165 /* src1 must be a descriptor (including the information to determine
166 * that the SEND is doing an extended math operation), but src0 can
167 * actually be null since it serves as the source of the implicit GRF
170 * If we stop using that functionality, we'll have to revisit this.
174 /* Send instructions are allowed to have null sources since they use
175 * the base_mrf field to specify which message register source.
180 assert(desc
->nsrc
< 4);
184 switch (math_function
) {
185 case BRW_MATH_FUNCTION_INV
:
186 case BRW_MATH_FUNCTION_LOG
:
187 case BRW_MATH_FUNCTION_EXP
:
188 case BRW_MATH_FUNCTION_SQRT
:
189 case BRW_MATH_FUNCTION_RSQ
:
190 case BRW_MATH_FUNCTION_SIN
:
191 case BRW_MATH_FUNCTION_COS
:
192 case BRW_MATH_FUNCTION_SINCOS
:
193 case GEN8_MATH_FUNCTION_INVM
:
194 case GEN8_MATH_FUNCTION_RSQRTM
:
196 case BRW_MATH_FUNCTION_FDIV
:
197 case BRW_MATH_FUNCTION_POW
:
198 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
:
199 case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
:
200 case BRW_MATH_FUNCTION_INT_DIV_REMAINDER
:
203 unreachable("not reached");
208 sources_not_null(const struct gen_device_info
*devinfo
,
209 const brw_inst
*inst
)
211 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
212 struct string error_msg
= { .str
= NULL
, .len
= 0 };
214 /* Nothing to test. 3-src instructions can only have GRF sources, and
215 * there's no bit to control the file.
217 if (num_sources
== 3)
218 return (struct string
){};
220 if (num_sources
>= 1)
221 ERROR_IF(src0_is_null(devinfo
, inst
), "src0 is null");
223 if (num_sources
== 2)
224 ERROR_IF(src1_is_null(devinfo
, inst
), "src1 is null");
230 send_restrictions(const struct gen_device_info
*devinfo
,
231 const brw_inst
*inst
)
233 struct string error_msg
= { .str
= NULL
, .len
= 0 };
235 if (brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_SEND
) {
236 ERROR_IF(brw_inst_src0_address_mode(devinfo
, inst
) != BRW_ADDRESS_DIRECT
,
237 "send must use direct addressing");
239 if (devinfo
->gen
>= 7) {
240 ERROR_IF(!src0_is_grf(devinfo
, inst
), "send from non-GRF");
241 ERROR_IF(brw_inst_eot(devinfo
, inst
) &&
242 brw_inst_src0_da_reg_nr(devinfo
, inst
) < 112,
243 "send with EOT must use g112-g127");
251 is_unsupported_inst(const struct gen_device_info
*devinfo
,
252 const brw_inst
*inst
)
254 return brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
)) == NULL
;
258 execution_type_for_type(unsigned type
, bool is_immediate
)
260 /* The meaning of the type bits is dependent on whether the operand is an
261 * immediate, so normalize them first.
265 case BRW_HW_REG_IMM_TYPE_UV
:
266 case BRW_HW_REG_IMM_TYPE_V
:
267 type
= BRW_HW_REG_TYPE_W
;
269 case BRW_HW_REG_IMM_TYPE_VF
:
270 type
= BRW_HW_REG_TYPE_F
;
272 case GEN8_HW_REG_IMM_TYPE_DF
:
273 type
= GEN7_HW_REG_NON_IMM_TYPE_DF
;
275 case GEN8_HW_REG_IMM_TYPE_HF
:
276 type
= GEN8_HW_REG_NON_IMM_TYPE_HF
;
284 case BRW_HW_REG_TYPE_UD
:
285 case BRW_HW_REG_TYPE_D
:
286 return BRW_HW_REG_TYPE_D
;
287 case BRW_HW_REG_TYPE_UW
:
288 case BRW_HW_REG_TYPE_W
:
289 case BRW_HW_REG_NON_IMM_TYPE_UB
:
290 case BRW_HW_REG_NON_IMM_TYPE_B
:
291 return BRW_HW_REG_TYPE_W
;
292 case GEN8_HW_REG_TYPE_UQ
:
293 case GEN8_HW_REG_TYPE_Q
:
294 return GEN8_HW_REG_TYPE_Q
;
295 case BRW_HW_REG_TYPE_F
:
296 case GEN7_HW_REG_NON_IMM_TYPE_DF
:
297 case GEN8_HW_REG_NON_IMM_TYPE_HF
:
300 unreachable("not reached");
305 * Returns the execution type of an instruction \p inst
308 execution_type(const struct gen_device_info
*devinfo
, const brw_inst
*inst
)
310 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
311 unsigned src0_exec_type
, src1_exec_type
;
312 unsigned src0_type
= brw_inst_src0_reg_type(devinfo
, inst
);
313 unsigned src1_type
= brw_inst_src1_reg_type(devinfo
, inst
);
315 bool src0_is_immediate
=
316 brw_inst_src0_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
;
317 bool src1_is_immediate
=
318 brw_inst_src1_reg_file(devinfo
, inst
) == BRW_IMMEDIATE_VALUE
;
320 /* Execution data type is independent of destination data type, except in
321 * mixed F/HF instructions on CHV and SKL+.
323 unsigned dst_exec_type
= brw_inst_dst_reg_type(devinfo
, inst
);
325 src0_exec_type
= execution_type_for_type(src0_type
, src0_is_immediate
);
326 if (num_sources
== 1) {
327 if ((devinfo
->gen
>= 9 || devinfo
->is_cherryview
) &&
328 src0_exec_type
== GEN8_HW_REG_NON_IMM_TYPE_HF
) {
329 return dst_exec_type
;
331 return src0_exec_type
;
334 src1_exec_type
= execution_type_for_type(src1_type
, src1_is_immediate
);
335 if (src0_exec_type
== src1_exec_type
)
336 return src0_exec_type
;
338 /* Mixed operand types where one is float is float on Gen < 6
339 * (and not allowed on later platforms)
341 if (devinfo
->gen
< 6 &&
342 (src0_exec_type
== BRW_HW_REG_TYPE_F
||
343 src1_exec_type
== BRW_HW_REG_TYPE_F
))
344 return BRW_HW_REG_TYPE_F
;
346 if (src0_exec_type
== GEN8_HW_REG_TYPE_Q
||
347 src1_exec_type
== GEN8_HW_REG_TYPE_Q
)
348 return GEN8_HW_REG_TYPE_Q
;
350 if (src0_exec_type
== BRW_HW_REG_TYPE_D
||
351 src1_exec_type
== BRW_HW_REG_TYPE_D
)
352 return BRW_HW_REG_TYPE_D
;
354 if (src0_exec_type
== BRW_HW_REG_TYPE_W
||
355 src1_exec_type
== BRW_HW_REG_TYPE_W
)
356 return BRW_HW_REG_TYPE_W
;
358 if (src0_exec_type
== GEN7_HW_REG_NON_IMM_TYPE_DF
||
359 src1_exec_type
== GEN7_HW_REG_NON_IMM_TYPE_DF
)
360 return GEN7_HW_REG_NON_IMM_TYPE_DF
;
362 if (devinfo
->gen
>= 9 || devinfo
->is_cherryview
) {
363 if (dst_exec_type
== BRW_HW_REG_TYPE_F
||
364 src0_exec_type
== BRW_HW_REG_TYPE_F
||
365 src1_exec_type
== BRW_HW_REG_TYPE_F
) {
366 return BRW_HW_REG_TYPE_F
;
368 return GEN8_HW_REG_NON_IMM_TYPE_HF
;
372 assert(src0_exec_type
== BRW_HW_REG_TYPE_F
);
373 return BRW_HW_REG_TYPE_F
;
377 * Returns whether a region is packed
379 * A region is packed if its elements are adjacent in memory, with no
380 * intervening space, no overlap, and no replicated values.
383 is_packed(unsigned vstride
, unsigned width
, unsigned hstride
)
385 if (vstride
== width
) {
397 * Checks restrictions listed in "General Restrictions Based on Operand Types"
398 * in the "Register Region Restrictions" section.
401 general_restrictions_based_on_operand_types(const struct gen_device_info
*devinfo
,
402 const brw_inst
*inst
)
404 const struct opcode_desc
*desc
=
405 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
406 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
407 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
408 struct string error_msg
= { .str
= NULL
, .len
= 0 };
410 if (num_sources
== 3)
411 return (struct string
){};
413 if (inst_is_send(devinfo
, inst
))
414 return (struct string
){};
417 return (struct string
){};
420 return (struct string
){};
424 * Where n is the largest element size in bytes for any source or
425 * destination operand type, ExecSize * n must be <= 64.
427 * But we do not attempt to enforce it, because it is implied by other
430 * - that the destination stride must match the execution data type
431 * - sources may not span more than two adjacent GRF registers
432 * - destination may not span more than two adjacent GRF registers
434 * In fact, checking it would weaken testing of the other rules.
437 if (num_sources
== 3)
438 return (struct string
){};
441 return (struct string
){};
443 if (inst_is_send(devinfo
, inst
))
444 return (struct string
){};
447 return (struct string
){};
449 unsigned dst_stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
450 bool dst_type_is_byte
=
451 brw_inst_dst_reg_type(devinfo
, inst
) == BRW_HW_REG_NON_IMM_TYPE_B
||
452 brw_inst_dst_reg_type(devinfo
, inst
) == BRW_HW_REG_NON_IMM_TYPE_UB
;
454 if (dst_type_is_byte
) {
455 if (is_packed(exec_size
* dst_stride
, exec_size
, dst_stride
)) {
456 if (!inst_is_raw_move(devinfo
, inst
)) {
457 ERROR("Only raw MOV supports a packed-byte destination");
460 return (struct string
){};
465 unsigned exec_type
= execution_type(devinfo
, inst
);
466 unsigned exec_type_size
=
467 brw_hw_reg_type_to_size(devinfo
, exec_type
, BRW_GENERAL_REGISTER_FILE
);
468 unsigned dst_type_size
= brw_element_size(devinfo
, inst
, dst
);
470 if (exec_type_size
> dst_type_size
) {
471 ERROR_IF(dst_stride
* dst_type_size
!= exec_type_size
,
472 "Destination stride must be equal to the ratio of the sizes of "
473 "the execution data type to the destination type");
475 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
477 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_1
&&
478 brw_inst_dst_address_mode(devinfo
, inst
) == BRW_ADDRESS_DIRECT
) {
479 /* The i965 PRM says:
481 * Implementation Restriction: The relaxed alignment rule for byte
482 * destination (#10.5) is not supported.
484 if ((devinfo
->gen
> 4 || devinfo
->is_g4x
) && dst_type_is_byte
) {
485 ERROR_IF(subreg
% exec_type_size
!= 0 &&
486 subreg
% exec_type_size
!= 1,
487 "Destination subreg must be aligned to the size of the "
488 "execution data type (or to the next lowest byte for byte "
491 ERROR_IF(subreg
% exec_type_size
!= 0,
492 "Destination subreg must be aligned to the size of the "
493 "execution data type");
502 * Checks restrictions listed in "General Restrictions on Regioning Parameters"
503 * in the "Register Region Restrictions" section.
506 general_restrictions_on_region_parameters(const struct gen_device_info
*devinfo
,
507 const brw_inst
*inst
)
509 const struct opcode_desc
*desc
=
510 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
511 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
512 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
513 struct string error_msg
= { .str
= NULL
, .len
= 0 };
515 if (num_sources
== 3)
516 return (struct string
){};
518 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
) {
519 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
))
520 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) != BRW_HORIZONTAL_STRIDE_1
,
521 "Destination Horizontal Stride must be 1");
523 if (num_sources
>= 1) {
524 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
525 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
526 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
527 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
528 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
529 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
531 ERROR_IF(brw_inst_src0_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
532 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
533 brw_inst_src0_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
534 "In Align16 mode, only VertStride of 0 or 4 is allowed");
538 if (num_sources
== 2) {
539 if (devinfo
->is_haswell
|| devinfo
->gen
>= 8) {
540 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
541 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
542 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_2
&&
543 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
544 "In Align16 mode, only VertStride of 0, 2, or 4 is allowed");
546 ERROR_IF(brw_inst_src1_reg_file(devinfo
, inst
) != BRW_IMMEDIATE_VALUE
&&
547 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_0
&&
548 brw_inst_src1_vstride(devinfo
, inst
) != BRW_VERTICAL_STRIDE_4
,
549 "In Align16 mode, only VertStride of 0 or 4 is allowed");
556 for (unsigned i
= 0; i
< num_sources
; i
++) {
557 unsigned vstride
, width
, hstride
, element_size
, subreg
;
560 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
561 BRW_IMMEDIATE_VALUE) \
564 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
565 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
566 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
567 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
568 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
569 element_size = brw_element_size(devinfo, inst, src ## n); \
570 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst)
579 /* ExecSize must be greater than or equal to Width. */
580 ERROR_IF(exec_size
< width
, "ExecSize must be greater than or equal "
583 /* If ExecSize = Width and HorzStride ≠ 0,
584 * VertStride must be set to Width * HorzStride.
586 if (exec_size
== width
&& hstride
!= 0) {
587 ERROR_IF(vstride
!= width
* hstride
,
588 "If ExecSize = Width and HorzStride ≠ 0, "
589 "VertStride must be set to Width * HorzStride");
592 /* If Width = 1, HorzStride must be 0 regardless of the values of
593 * ExecSize and VertStride.
596 ERROR_IF(hstride
!= 0,
597 "If Width = 1, HorzStride must be 0 regardless "
598 "of the values of ExecSize and VertStride");
601 /* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
602 if (exec_size
== 1 && width
== 1) {
603 ERROR_IF(vstride
!= 0 || hstride
!= 0,
604 "If ExecSize = Width = 1, both VertStride "
605 "and HorzStride must be 0");
608 /* If VertStride = HorzStride = 0, Width must be 1 regardless of the
611 if (vstride
== 0 && hstride
== 0) {
613 "If VertStride = HorzStride = 0, Width must be "
614 "1 regardless of the value of ExecSize");
617 /* VertStride must be used to cross GRF register boundaries. This rule
618 * implies that elements within a 'Width' cannot cross GRF boundaries.
620 const uint64_t mask
= (1 << element_size
) - 1;
621 unsigned rowbase
= subreg
;
623 for (int y
= 0; y
< exec_size
/ width
; y
++) {
624 uint64_t access_mask
= 0;
625 unsigned offset
= rowbase
;
627 for (int x
= 0; x
< width
; x
++) {
628 access_mask
|= mask
<< offset
;
629 offset
+= hstride
* element_size
;
632 rowbase
+= vstride
* element_size
;
634 if ((uint32_t)access_mask
!= 0 && (access_mask
>> 32) != 0) {
635 ERROR("VertStride must be used to cross GRF register boundaries");
641 /* Dst.HorzStride must not be 0. */
642 if (desc
->ndst
!= 0 && !dst_is_null(devinfo
, inst
)) {
643 ERROR_IF(brw_inst_dst_hstride(devinfo
, inst
) == BRW_HORIZONTAL_STRIDE_0
,
644 "Destination Horizontal Stride must not be 0");
651 * Creates an \p access_mask for an \p exec_size, \p element_size, and a region
653 * An \p access_mask is a 32-element array of uint64_t, where each uint64_t is
654 * a bitmask of bytes accessed by the region.
656 * For instance the access mask of the source gX.1<4,2,2>F in an exec_size = 4
657 * instruction would be
659 * access_mask[0] = 0x00000000000000F0
660 * access_mask[1] = 0x000000000000F000
661 * access_mask[2] = 0x0000000000F00000
662 * access_mask[3] = 0x00000000F0000000
663 * access_mask[4-31] = 0
665 * because the first execution channel accesses bytes 7-4 and the second
666 * execution channel accesses bytes 15-12, etc.
669 align1_access_mask(uint64_t access_mask
[static 32],
670 unsigned exec_size
, unsigned element_size
, unsigned subreg
,
671 unsigned vstride
, unsigned width
, unsigned hstride
)
673 const uint64_t mask
= (1 << element_size
) - 1;
674 unsigned rowbase
= subreg
;
675 unsigned element
= 0;
677 for (int y
= 0; y
< exec_size
/ width
; y
++) {
678 unsigned offset
= rowbase
;
680 for (int x
= 0; x
< width
; x
++) {
681 access_mask
[element
++] = mask
<< offset
;
682 offset
+= hstride
* element_size
;
685 rowbase
+= vstride
* element_size
;
688 assert(element
== 0 || element
== exec_size
);
692 * Returns the number of registers accessed according to the \p access_mask
695 registers_read(const uint64_t access_mask
[static 32])
699 for (unsigned i
= 0; i
< 32; i
++) {
700 if (access_mask
[i
] > 0xFFFFFFFF) {
702 } else if (access_mask
[i
]) {
711 * Checks restrictions listed in "Region Alignment Rules" in the "Register
712 * Region Restrictions" section.
715 region_alignment_rules(const struct gen_device_info
*devinfo
,
716 const brw_inst
*inst
)
718 const struct opcode_desc
*desc
=
719 brw_opcode_desc(devinfo
, brw_inst_opcode(devinfo
, inst
));
720 unsigned num_sources
= num_sources_from_inst(devinfo
, inst
);
721 unsigned exec_size
= 1 << brw_inst_exec_size(devinfo
, inst
);
722 uint64_t dst_access_mask
[32], src0_access_mask
[32], src1_access_mask
[32];
723 struct string error_msg
= { .str
= NULL
, .len
= 0 };
725 if (num_sources
== 3)
726 return (struct string
){};
728 if (brw_inst_access_mode(devinfo
, inst
) == BRW_ALIGN_16
)
729 return (struct string
){};
731 if (inst_is_send(devinfo
, inst
))
732 return (struct string
){};
734 memset(dst_access_mask
, 0, sizeof(dst_access_mask
));
735 memset(src0_access_mask
, 0, sizeof(src0_access_mask
));
736 memset(src1_access_mask
, 0, sizeof(src1_access_mask
));
738 for (unsigned i
= 0; i
< num_sources
; i
++) {
739 unsigned vstride
, width
, hstride
, element_size
, subreg
;
741 /* In Direct Addressing mode, a source cannot span more than 2 adjacent
746 if (brw_inst_src ## n ## _address_mode(devinfo, inst) != \
747 BRW_ADDRESS_DIRECT) \
750 if (brw_inst_src ## n ## _reg_file(devinfo, inst) == \
751 BRW_IMMEDIATE_VALUE) \
754 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
755 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
756 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
757 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
758 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
759 element_size = brw_element_size(devinfo, inst, src ## n); \
760 subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
761 align1_access_mask(src ## n ## _access_mask, \
762 exec_size, element_size, subreg, \
763 vstride, width, hstride)
772 unsigned num_vstride
= exec_size
/ width
;
773 unsigned num_hstride
= width
;
774 unsigned vstride_elements
= (num_vstride
- 1) * vstride
;
775 unsigned hstride_elements
= (num_hstride
- 1) * hstride
;
776 unsigned offset
= (vstride_elements
+ hstride_elements
) * element_size
+
778 ERROR_IF(offset
>= 64,
779 "A source cannot span more than 2 adjacent GRF registers");
782 if (desc
->ndst
== 0 || dst_is_null(devinfo
, inst
))
785 unsigned stride
= 1 << (brw_inst_dst_hstride(devinfo
, inst
) - 1);
786 unsigned element_size
= brw_element_size(devinfo
, inst
, dst
);
787 unsigned subreg
= brw_inst_dst_da1_subreg_nr(devinfo
, inst
);
788 unsigned offset
= ((exec_size
- 1) * stride
* element_size
) + subreg
;
789 ERROR_IF(offset
>= 64,
790 "A destination cannot span more than 2 adjacent GRF registers");
795 align1_access_mask(dst_access_mask
, exec_size
, element_size
, subreg
,
796 exec_size
== 1 ? 0 : exec_size
* stride
,
797 exec_size
== 1 ? 1 : exec_size
,
798 exec_size
== 1 ? 0 : stride
);
800 unsigned dst_regs
= registers_read(dst_access_mask
);
801 unsigned src0_regs
= registers_read(src0_access_mask
);
802 unsigned src1_regs
= registers_read(src1_access_mask
);
804 /* The SNB, IVB, HSW, BDW, and CHV PRMs say:
806 * When an instruction has a source region spanning two registers and a
807 * destination region contained in one register, the number of elements
808 * must be the same between two sources and one of the following must be
811 * 1. The destination region is entirely contained in the lower OWord
813 * 2. The destination region is entirely contained in the upper OWord
815 * 3. The destination elements are evenly split between the two OWords
818 if (devinfo
->gen
<= 8) {
819 if (dst_regs
== 1 && (src0_regs
== 2 || src1_regs
== 2)) {
820 unsigned upper_oword_writes
= 0, lower_oword_writes
= 0;
822 for (unsigned i
= 0; i
< exec_size
; i
++) {
823 if (dst_access_mask
[i
] > 0x0000FFFF) {
824 upper_oword_writes
++;
826 assert(dst_access_mask
[i
] != 0);
827 lower_oword_writes
++;
831 ERROR_IF(lower_oword_writes
!= 0 &&
832 upper_oword_writes
!= 0 &&
833 upper_oword_writes
!= lower_oword_writes
,
834 "Writes must be to only one OWord or "
835 "evenly split between OWords");
839 /* The IVB and HSW PRMs say:
841 * When an instruction has a source region that spans two registers and
842 * the destination spans two registers, the destination elements must be
843 * evenly split between the two registers [...]
845 * The SNB PRM contains similar wording (but written in a much more
850 * When destination spans two registers, the source may be one or two
851 * registers. The destination elements must be evenly split between the
856 * When destination of MATH instruction spans two registers, the
857 * destination elements must be evenly split between the two registers.
859 * It is not known whether this restriction applies to KBL other Gens after
862 if (devinfo
->gen
<= 8 ||
863 brw_inst_opcode(devinfo
, inst
) == BRW_OPCODE_MATH
) {
865 /* Nothing explicitly states that on Gen < 8 elements must be evenly
866 * split between two destination registers in the two exceptional
867 * source-region-spans-one-register cases, but since Broadwell requires
868 * evenly split writes regardless of source region, we assume that it was
869 * an oversight and require it.
872 unsigned upper_reg_writes
= 0, lower_reg_writes
= 0;
874 for (unsigned i
= 0; i
< exec_size
; i
++) {
875 if (dst_access_mask
[i
] > 0xFFFFFFFF) {
878 assert(dst_access_mask
[i
] != 0);
883 ERROR_IF(upper_reg_writes
!= lower_reg_writes
,
884 "Writes must be evenly split between the two "
885 "destination registers");
889 /* The IVB and HSW PRMs say:
891 * When an instruction has a source region that spans two registers and
892 * the destination spans two registers, the destination elements must be
893 * evenly split between the two registers and each destination register
894 * must be entirely derived from one source register.
896 * Note: In such cases, the regioning parameters must ensure that the
897 * offset from the two source registers is the same.
899 * The SNB PRM contains similar wording (but written in a much more
902 * There are effectively three rules stated here:
904 * For an instruction with a source and a destination spanning two
907 * (1) destination elements must be evenly split between the two
909 * (2) all destination elements in a register must be derived
910 * from one source register
911 * (3) the offset (i.e. the starting location in each of the two
912 * registers spanned by a region) must be the same in the two
913 * registers spanned by a region
915 * It is impossible to violate rule (1) without violating (2) or (3), so we
916 * do not attempt to validate it.
918 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
919 for (unsigned i
= 0; i
< num_sources
; i
++) {
921 if (src ## n ## _regs <= 1) \
924 for (unsigned i = 0; i < exec_size; i++) { \
925 if ((dst_access_mask[i] > 0xFFFFFFFF) != \
926 (src ## n ## _access_mask[i] > 0xFFFFFFFF)) { \
927 ERROR("Each destination register must be entirely derived " \
928 "from one source register"); \
933 unsigned offset_0 = \
934 brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst); \
935 unsigned offset_1 = offset_0; \
937 for (unsigned i = 0; i < exec_size; i++) { \
938 if (src ## n ## _access_mask[i] > 0xFFFFFFFF) { \
939 offset_1 = __builtin_ctzll(src ## n ## _access_mask[i]) - 32; \
944 ERROR_IF(offset_0 != offset_1, \
945 "The offset from the two source registers " \
957 /* The IVB and HSW PRMs say:
959 * When destination spans two registers, the source MUST span two
960 * registers. The exception to the above rule:
961 * 1. When source is scalar, the source registers are not
963 * 2. When source is packed integer Word and destination is packed
964 * integer DWord, the source register is not incremented by the
965 * source sub register is incremented.
967 * The SNB PRM does not contain this rule, but the internal documentation
968 * indicates that it applies to SNB as well. We assume that the rule applies
969 * to Gen <= 5 although their PRMs do not state it.
971 * While the documentation explicitly says in exception (2) that the
972 * destination must be an integer DWord, the hardware allows at least a
973 * float destination type as well. We emit such instructions from
975 * fs_visitor::emit_interpolation_setup_gen6
976 * fs_visitor::emit_fragcoord_interpolation
978 * and have for years with no ill effects.
980 * Additionally the simulator source code indicates that the real condition
981 * is that the size of the destination type is 4 bytes.
983 if (devinfo
->gen
<= 7 && dst_regs
== 2) {
984 bool dst_is_packed_dword
=
985 is_packed(exec_size
* stride
, exec_size
, stride
) &&
986 brw_element_size(devinfo
, inst
, dst
) == 4;
988 for (unsigned i
= 0; i
< num_sources
; i
++) {
990 unsigned vstride, width, hstride; \
991 vstride = brw_inst_src ## n ## _vstride(devinfo, inst) ? \
992 (1 << (brw_inst_src ## n ## _vstride(devinfo, inst) - 1)) : 0; \
993 width = 1 << brw_inst_src ## n ## _width(devinfo, inst); \
994 hstride = brw_inst_src ## n ## _hstride(devinfo, inst) ? \
995 (1 << (brw_inst_src ## n ## _hstride(devinfo, inst) - 1)) : 0; \
996 bool src ## n ## _is_packed_word = \
997 is_packed(vstride, width, hstride) && \
998 (brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_W || \
999 brw_inst_src ## n ## _reg_type(devinfo, inst) == BRW_HW_REG_TYPE_UW); \
1001 ERROR_IF(src ## n ## _regs == 1 && \
1002 !src ## n ## _has_scalar_region(devinfo, inst) && \
1003 !(dst_is_packed_dword && src ## n ## _is_packed_word), \
1004 "When the destination spans two registers, the source must " \
1005 "span two registers\n" ERROR_INDENT "(exceptions for scalar " \
1006 "source and packed-word to packed-dword expansion)")
1010 } else if (i
== 1) {
1021 brw_validate_instructions(const struct brw_codegen
*p
, int start_offset
,
1022 struct annotation_info
*annotation
)
1024 const struct gen_device_info
*devinfo
= p
->devinfo
;
1025 const void *store
= p
->store
;
1028 for (int src_offset
= start_offset
; src_offset
< p
->next_insn_offset
;
1029 src_offset
+= sizeof(brw_inst
)) {
1030 struct string error_msg
= { .str
= NULL
, .len
= 0 };
1031 const brw_inst
*inst
= store
+ src_offset
;
1033 if (is_unsupported_inst(devinfo
, inst
)) {
1034 ERROR("Instruction not supported on this Gen");
1036 CHECK(sources_not_null
);
1037 CHECK(send_restrictions
);
1038 CHECK(general_restrictions_based_on_operand_types
);
1039 CHECK(general_restrictions_on_region_parameters
);
1040 CHECK(region_alignment_rules
);
1043 if (error_msg
.str
&& annotation
) {
1044 annotation_insert_error(annotation
, src_offset
, error_msg
.str
);
1046 valid
= valid
&& error_msg
.len
== 0;
1047 free(error_msg
.str
);