2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
34 #include "brw_fs_live_variables.h"
36 #include "brw_vec4_gs_visitor.h"
38 #include "brw_dead_control_flow.h"
39 #include "dev/gen_debug.h"
40 #include "compiler/glsl_types.h"
41 #include "compiler/nir/nir_builder.h"
42 #include "program/prog_parameter.h"
43 #include "util/u_math.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset((void*)this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy((void*)this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
197 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
201 * A helper for MOV generation for fixing up broken hardware SEND dependency
205 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
207 /* The caller always wants uncompressed to emit the minimal extra
208 * dependencies, and to avoid having to deal with aligning its regs to 2.
210 const fs_builder ubld
= bld
.annotate("send dependency resolve")
213 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
217 fs_inst::is_send_from_grf() const
220 case SHADER_OPCODE_SEND
:
221 case SHADER_OPCODE_SHADER_TIME_ADD
:
222 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
223 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
224 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
228 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
229 case SHADER_OPCODE_URB_READ_SIMD8
:
230 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
231 case SHADER_OPCODE_INTERLOCK
:
232 case SHADER_OPCODE_MEMORY_FENCE
:
233 case SHADER_OPCODE_BARRIER
:
235 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
236 return src
[1].file
== VGRF
;
237 case FS_OPCODE_FB_WRITE
:
238 case FS_OPCODE_FB_READ
:
239 return src
[0].file
== VGRF
;
242 return src
[0].file
== VGRF
;
249 fs_inst::is_control_source(unsigned arg
) const
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
253 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
257 case SHADER_OPCODE_BROADCAST
:
258 case SHADER_OPCODE_SHUFFLE
:
259 case SHADER_OPCODE_QUAD_SWIZZLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
261 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
262 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
263 case SHADER_OPCODE_GET_BUFFER_SIZE
:
266 case SHADER_OPCODE_MOV_INDIRECT
:
267 case SHADER_OPCODE_CLUSTER_BROADCAST
:
268 case SHADER_OPCODE_TEX
:
270 case SHADER_OPCODE_TXD
:
271 case SHADER_OPCODE_TXF
:
272 case SHADER_OPCODE_TXF_LZ
:
273 case SHADER_OPCODE_TXF_CMS
:
274 case SHADER_OPCODE_TXF_CMS_W
:
275 case SHADER_OPCODE_TXF_UMS
:
276 case SHADER_OPCODE_TXF_MCS
:
277 case SHADER_OPCODE_TXL
:
278 case SHADER_OPCODE_TXL_LZ
:
279 case SHADER_OPCODE_TXS
:
280 case SHADER_OPCODE_LOD
:
281 case SHADER_OPCODE_TG4
:
282 case SHADER_OPCODE_TG4_OFFSET
:
283 case SHADER_OPCODE_SAMPLEINFO
:
284 return arg
== 1 || arg
== 2;
286 case SHADER_OPCODE_SEND
:
287 return arg
== 0 || arg
== 1;
295 fs_inst::is_payload(unsigned arg
) const
298 case FS_OPCODE_FB_WRITE
:
299 case FS_OPCODE_FB_READ
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
303 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
304 case SHADER_OPCODE_URB_READ_SIMD8
:
305 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
306 case VEC4_OPCODE_UNTYPED_ATOMIC
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
308 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
309 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
310 case SHADER_OPCODE_SHADER_TIME_ADD
:
311 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
312 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
313 case SHADER_OPCODE_INTERLOCK
:
314 case SHADER_OPCODE_MEMORY_FENCE
:
315 case SHADER_OPCODE_BARRIER
:
318 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SEND
:
322 return arg
== 2 || arg
== 3;
333 * Returns true if this instruction's sources and destinations cannot
334 * safely be the same register.
336 * In most cases, a register can be written over safely by the same
337 * instruction that is its last use. For a single instruction, the
338 * sources are dereferenced before writing of the destination starts
341 * However, there are a few cases where this can be problematic:
343 * - Virtual opcodes that translate to multiple instructions in the
344 * code generator: if src == dst and one instruction writes the
345 * destination before a later instruction reads the source, then
346 * src will have been clobbered.
348 * - SIMD16 compressed instructions with certain regioning (see below).
350 * The register allocator uses this information to set up conflicts between
351 * GRF sources and the destination.
354 fs_inst::has_source_and_destination_hazard() const
357 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
358 /* Multiple partial writes to the destination */
360 case SHADER_OPCODE_SHUFFLE
:
361 /* This instruction returns an arbitrary channel from the source and
362 * gets split into smaller instructions in the generator. It's possible
363 * that one of the instructions will read from a channel corresponding
364 * to an earlier instruction.
366 case SHADER_OPCODE_SEL_EXEC
:
367 /* This is implemented as
369 * mov(16) g4<1>D 0D { align1 WE_all 1H };
370 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
372 * Because the source is only read in the second instruction, the first
373 * may stomp all over it.
376 case SHADER_OPCODE_QUAD_SWIZZLE
:
378 case BRW_SWIZZLE_XXXX
:
379 case BRW_SWIZZLE_YYYY
:
380 case BRW_SWIZZLE_ZZZZ
:
381 case BRW_SWIZZLE_WWWW
:
382 case BRW_SWIZZLE_XXZZ
:
383 case BRW_SWIZZLE_YYWW
:
384 case BRW_SWIZZLE_XYXY
:
385 case BRW_SWIZZLE_ZWZW
:
386 /* These can be implemented as a single Align1 region on all
387 * platforms, so there's never a hazard between source and
388 * destination. C.f. fs_generator::generate_quad_swizzle().
392 return !is_uniform(src
[0]);
395 /* The SIMD16 compressed instruction
397 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
399 * is actually decoded in hardware as:
401 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
402 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
404 * Which is safe. However, if we have uniform accesses
405 * happening, we get into trouble:
407 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
408 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
410 * Now our destination for the first instruction overwrote the
411 * second instruction's src0, and we get garbage for those 8
412 * pixels. There's a similar issue for the pre-gen6
413 * pixel_x/pixel_y, which are registers of 16-bit values and thus
414 * would get stomped by the first decode as well.
416 if (exec_size
== 16) {
417 for (int i
= 0; i
< sources
; i
++) {
418 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
419 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
420 src
[i
].type
== BRW_REGISTER_TYPE_W
||
421 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
422 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
432 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
434 if (devinfo
->gen
== 6 && is_math())
437 if (is_send_from_grf())
440 /* From GEN:BUG:1604601757:
442 * "When multiplying a DW and any lower precision integer, source modifier
445 if (devinfo
->gen
>= 12 && (opcode
== BRW_OPCODE_MUL
||
446 opcode
== BRW_OPCODE_MAD
)) {
447 const brw_reg_type exec_type
= get_exec_type(this);
448 const unsigned min_type_sz
= opcode
== BRW_OPCODE_MAD
?
449 MIN2(type_sz(src
[1].type
), type_sz(src
[2].type
)) :
450 MIN2(type_sz(src
[0].type
), type_sz(src
[1].type
));
452 if (brw_reg_type_is_integer(exec_type
) &&
453 type_sz(exec_type
) >= 4 &&
454 type_sz(exec_type
) != min_type_sz
)
458 if (!backend_instruction::can_do_source_mods())
465 fs_inst::can_do_cmod()
467 if (!backend_instruction::can_do_cmod())
470 /* The accumulator result appears to get used for the conditional modifier
471 * generation. When negating a UD value, there is a 33rd bit generated for
472 * the sign in the accumulator value, so now you can't check, for example,
473 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
475 for (unsigned i
= 0; i
< sources
; i
++) {
476 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
484 fs_inst::can_change_types() const
486 return dst
.type
== src
[0].type
&&
487 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
488 (opcode
== BRW_OPCODE_MOV
||
489 (opcode
== BRW_OPCODE_SEL
&&
490 dst
.type
== src
[1].type
&&
491 predicate
!= BRW_PREDICATE_NONE
&&
492 !src
[1].abs
&& !src
[1].negate
));
498 memset((void*)this, 0, sizeof(*this));
499 type
= BRW_REGISTER_TYPE_UD
;
503 /** Generic unset register constructor. */
507 this->file
= BAD_FILE
;
510 fs_reg::fs_reg(struct ::brw_reg reg
) :
515 if (this->file
== IMM
&&
516 (this->type
!= BRW_REGISTER_TYPE_V
&&
517 this->type
!= BRW_REGISTER_TYPE_UV
&&
518 this->type
!= BRW_REGISTER_TYPE_VF
)) {
524 fs_reg::equals(const fs_reg
&r
) const
526 return (this->backend_reg::equals(r
) &&
531 fs_reg::negative_equals(const fs_reg
&r
) const
533 return (this->backend_reg::negative_equals(r
) &&
538 fs_reg::is_contiguous() const
543 return hstride
== BRW_HORIZONTAL_STRIDE_1
&&
544 vstride
== width
+ hstride
;
555 unreachable("Invalid register file");
559 fs_reg::component_size(unsigned width
) const
561 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
564 return MAX2(width
* stride
, 1) * type_sz(type
);
568 * Create a MOV to read the timestamp register.
571 fs_visitor::get_timestamp(const fs_builder
&bld
)
573 assert(devinfo
->gen
>= 7);
575 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
578 BRW_REGISTER_TYPE_UD
));
580 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
582 /* We want to read the 3 fields we care about even if it's not enabled in
585 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
591 fs_visitor::emit_shader_time_begin()
593 /* We want only the low 32 bits of the timestamp. Since it's running
594 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
595 * which is plenty of time for our purposes. It is identical across the
596 * EUs, but since it's tracking GPU core speed it will increment at a
597 * varying rate as render P-states change.
599 shader_start_time
= component(
600 get_timestamp(bld
.annotate("shader time start")), 0);
604 fs_visitor::emit_shader_time_end()
606 /* Insert our code just before the final SEND with EOT. */
607 exec_node
*end
= this->instructions
.get_tail();
608 assert(end
&& ((fs_inst
*) end
)->eot
);
609 const fs_builder ibld
= bld
.annotate("shader time end")
610 .exec_all().at(NULL
, end
);
611 const fs_reg timestamp
= get_timestamp(ibld
);
613 /* We only use the low 32 bits of the timestamp - see
614 * emit_shader_time_begin()).
616 * We could also check if render P-states have changed (or anything
617 * else that might disrupt timing) by setting smear to 2 and checking if
618 * that field is != 0.
620 const fs_reg shader_end_time
= component(timestamp
, 0);
622 /* Check that there weren't any timestamp reset events (assuming these
623 * were the only two timestamp reads that happened).
625 const fs_reg reset
= component(timestamp
, 2);
626 set_condmod(BRW_CONDITIONAL_Z
,
627 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
628 ibld
.IF(BRW_PREDICATE_NORMAL
);
630 fs_reg start
= shader_start_time
;
632 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
633 BRW_REGISTER_TYPE_UD
),
635 const fs_builder cbld
= ibld
.group(1, 0);
636 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
638 /* If there were no instructions between the two timestamp gets, the diff
639 * is 2 cycles. Remove that overhead, so I can forget about that when
640 * trying to determine the time taken for single instructions.
642 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
643 SHADER_TIME_ADD(cbld
, 0, diff
);
644 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
645 ibld
.emit(BRW_OPCODE_ELSE
);
646 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
647 ibld
.emit(BRW_OPCODE_ENDIF
);
651 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
652 int shader_time_subindex
,
655 int index
= shader_time_index
* 3 + shader_time_subindex
;
656 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
659 if (dispatch_width
== 8)
660 payload
= vgrf(glsl_type::uvec2_type
);
662 payload
= vgrf(glsl_type::uint_type
);
664 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
668 fs_visitor::vfail(const char *format
, va_list va
)
677 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
678 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
680 this->fail_msg
= msg
;
683 fprintf(stderr
, "%s", msg
);
688 fs_visitor::fail(const char *format
, ...)
692 va_start(va
, format
);
698 * Mark this program as impossible to compile with dispatch width greater
701 * During the SIMD8 compile (which happens first), we can detect and flag
702 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
703 * SIMD16+ compile altogether.
705 * During a compile of dispatch width greater than n (if one happens anyway),
706 * this just calls fail().
709 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
711 if (dispatch_width
> n
) {
714 max_dispatch_width
= n
;
715 compiler
->shader_perf_log(log_data
,
716 "Shader dispatch width limited to SIMD%d: %s",
722 * Returns true if the instruction has a flag that means it won't
723 * update an entire destination register.
725 * For example, dead code elimination and live variable analysis want to know
726 * when a write to a variable screens off any preceding values that were in
730 fs_inst::is_partial_write() const
732 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
733 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
734 !this->dst
.is_contiguous() ||
735 this->dst
.offset
% REG_SIZE
!= 0);
739 fs_inst::components_read(unsigned i
) const
741 /* Return zero if the source is not present. */
742 if (src
[i
].file
== BAD_FILE
)
746 case FS_OPCODE_LINTERP
:
752 case FS_OPCODE_PIXEL_X
:
753 case FS_OPCODE_PIXEL_Y
:
757 case FS_OPCODE_FB_WRITE_LOGICAL
:
758 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
759 /* First/second FB write color. */
761 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
765 case SHADER_OPCODE_TEX_LOGICAL
:
766 case SHADER_OPCODE_TXD_LOGICAL
:
767 case SHADER_OPCODE_TXF_LOGICAL
:
768 case SHADER_OPCODE_TXL_LOGICAL
:
769 case SHADER_OPCODE_TXS_LOGICAL
:
770 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
771 case FS_OPCODE_TXB_LOGICAL
:
772 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
773 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
774 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
775 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
776 case SHADER_OPCODE_LOD_LOGICAL
:
777 case SHADER_OPCODE_TG4_LOGICAL
:
778 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
779 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
780 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
781 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
782 /* Texture coordinates. */
783 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
784 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
785 /* Texture derivatives. */
786 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
787 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
788 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
789 /* Texture offset. */
790 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
793 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
798 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
799 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
800 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
801 /* Surface coordinates. */
802 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
803 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
804 /* Surface operation source (ignored for reads). */
805 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
810 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
811 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
812 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
813 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
814 /* Surface coordinates. */
815 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
816 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
817 /* Surface operation source. */
818 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
819 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
823 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
824 assert(src
[2].file
== IMM
);
827 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
828 assert(src
[2].file
== IMM
);
829 return i
== 1 ? src
[2].ud
: 1;
831 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
832 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
833 assert(src
[2].file
== IMM
);
836 const unsigned op
= src
[2].ud
;
851 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
852 assert(src
[2].file
== IMM
);
855 const unsigned op
= src
[2].ud
;
856 return op
== BRW_AOP_FCMPWR
? 2 : 1;
861 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
862 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
863 /* Scattered logical opcodes use the following params:
864 * src[0] Surface coordinates
865 * src[1] Surface operation source (ignored for reads)
867 * src[3] IMM with always 1 dimension.
868 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
870 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
871 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
872 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
874 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
875 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
876 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
877 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
880 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
881 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
882 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
883 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
884 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
885 /* Surface coordinates. */
886 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
887 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
888 /* Surface operation source. */
889 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
891 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
892 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
897 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
898 return (i
== 0 ? 2 : 1);
900 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
901 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
902 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
903 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
904 /* Surface coordinates. */
905 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
906 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
907 /* Surface operation source. */
908 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
920 fs_inst::size_read(int arg
) const
923 case SHADER_OPCODE_SEND
:
925 return mlen
* REG_SIZE
;
926 } else if (arg
== 3) {
927 return ex_mlen
* REG_SIZE
;
931 case FS_OPCODE_FB_WRITE
:
932 case FS_OPCODE_REP_FB_WRITE
:
935 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
937 return mlen
* REG_SIZE
;
941 case FS_OPCODE_FB_READ
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
945 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
946 case SHADER_OPCODE_URB_READ_SIMD8
:
947 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
948 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
949 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
951 return mlen
* REG_SIZE
;
954 case FS_OPCODE_SET_SAMPLE_ID
:
959 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
960 /* The payload is actually stored in src1 */
962 return mlen
* REG_SIZE
;
965 case FS_OPCODE_LINTERP
:
970 case SHADER_OPCODE_LOAD_PAYLOAD
:
971 if (arg
< this->header_size
)
975 case CS_OPCODE_CS_TERMINATE
:
976 case SHADER_OPCODE_BARRIER
:
979 case SHADER_OPCODE_MOV_INDIRECT
:
981 assert(src
[2].file
== IMM
);
987 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
988 return mlen
* REG_SIZE
;
992 switch (src
[arg
].file
) {
995 return components_read(arg
) * type_sz(src
[arg
].type
);
1001 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1003 unreachable("MRF registers are not allowed as sources");
1010 predicate_width(brw_predicate predicate
)
1012 switch (predicate
) {
1013 case BRW_PREDICATE_NONE
: return 1;
1014 case BRW_PREDICATE_NORMAL
: return 1;
1015 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1016 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1017 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1018 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1019 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1020 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1021 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1022 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1023 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1024 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1025 default: unreachable("Unsupported predicate");
1029 /* Return the subset of flag registers that an instruction could
1030 * potentially read or write based on the execution controls and flag
1031 * subregister number of the instruction.
1034 flag_mask(const fs_inst
*inst
, unsigned width
)
1036 assert(util_is_power_of_two_nonzero(width
));
1037 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1039 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1040 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1044 bit_mask(unsigned n
)
1046 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1050 flag_mask(const fs_reg
&r
, unsigned sz
)
1052 if (r
.file
== ARF
) {
1053 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1054 const unsigned end
= start
+ sz
;
1055 return bit_mask(end
) & ~bit_mask(start
);
1063 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1065 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1066 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1067 /* The vertical predication modes combine corresponding bits from
1068 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1070 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1071 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1072 } else if (predicate
) {
1073 return flag_mask(this, predicate_width(predicate
));
1076 for (int i
= 0; i
< sources
; i
++) {
1077 mask
|= flag_mask(src
[i
], size_read(i
));
1084 fs_inst::flags_written() const
1086 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1087 opcode
!= BRW_OPCODE_CSEL
&&
1088 opcode
!= BRW_OPCODE_IF
&&
1089 opcode
!= BRW_OPCODE_WHILE
)) ||
1090 opcode
== FS_OPCODE_FB_WRITE
) {
1091 return flag_mask(this, 1);
1092 } else if (opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1093 opcode
== FS_OPCODE_LOAD_LIVE_CHANNELS
) {
1094 return flag_mask(this, 32);
1096 return flag_mask(dst
, size_written
);
1101 * Returns how many MRFs an FS opcode will write over.
1103 * Note that this is not the 0 or 1 implied writes in an actual gen
1104 * instruction -- the FS opcodes often generate MOVs in addition.
1107 fs_inst::implied_mrf_writes() const
1116 case SHADER_OPCODE_RCP
:
1117 case SHADER_OPCODE_RSQ
:
1118 case SHADER_OPCODE_SQRT
:
1119 case SHADER_OPCODE_EXP2
:
1120 case SHADER_OPCODE_LOG2
:
1121 case SHADER_OPCODE_SIN
:
1122 case SHADER_OPCODE_COS
:
1123 return 1 * exec_size
/ 8;
1124 case SHADER_OPCODE_POW
:
1125 case SHADER_OPCODE_INT_QUOTIENT
:
1126 case SHADER_OPCODE_INT_REMAINDER
:
1127 return 2 * exec_size
/ 8;
1128 case SHADER_OPCODE_TEX
:
1130 case SHADER_OPCODE_TXD
:
1131 case SHADER_OPCODE_TXF
:
1132 case SHADER_OPCODE_TXF_CMS
:
1133 case SHADER_OPCODE_TXF_MCS
:
1134 case SHADER_OPCODE_TG4
:
1135 case SHADER_OPCODE_TG4_OFFSET
:
1136 case SHADER_OPCODE_TXL
:
1137 case SHADER_OPCODE_TXS
:
1138 case SHADER_OPCODE_LOD
:
1139 case SHADER_OPCODE_SAMPLEINFO
:
1141 case FS_OPCODE_FB_WRITE
:
1142 case FS_OPCODE_REP_FB_WRITE
:
1143 return src
[0].file
== BAD_FILE
? 0 : 2;
1144 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1145 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1147 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1149 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1152 unreachable("not reached");
1157 fs_visitor::vgrf(const glsl_type
*const type
)
1159 int reg_width
= dispatch_width
/ 8;
1161 alloc
.allocate(glsl_count_dword_slots(type
, false) * reg_width
),
1162 brw_type_for_base_type(type
));
1165 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1170 this->type
= BRW_REGISTER_TYPE_F
;
1171 this->stride
= (file
== UNIFORM
? 0 : 1);
1174 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1180 this->stride
= (file
== UNIFORM
? 0 : 1);
1183 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1184 * This brings in those uniform definitions
1187 fs_visitor::import_uniforms(fs_visitor
*v
)
1189 this->push_constant_loc
= v
->push_constant_loc
;
1190 this->pull_constant_loc
= v
->pull_constant_loc
;
1191 this->uniforms
= v
->uniforms
;
1192 this->subgroup_id
= v
->subgroup_id
;
1196 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1198 assert(stage
== MESA_SHADER_FRAGMENT
);
1200 /* gl_FragCoord.x */
1201 bld
.MOV(wpos
, this->pixel_x
);
1202 wpos
= offset(wpos
, bld
, 1);
1204 /* gl_FragCoord.y */
1205 bld
.MOV(wpos
, this->pixel_y
);
1206 wpos
= offset(wpos
, bld
, 1);
1208 /* gl_FragCoord.z */
1209 if (devinfo
->gen
>= 6) {
1210 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1212 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1213 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1214 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1216 wpos
= offset(wpos
, bld
, 1);
1218 /* gl_FragCoord.w: Already set up in emit_interpolation */
1219 bld
.MOV(wpos
, this->wpos_w
);
1222 enum brw_barycentric_mode
1223 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1225 /* Barycentric modes don't make sense for flat inputs. */
1226 assert(mode
!= INTERP_MODE_FLAT
);
1230 case nir_intrinsic_load_barycentric_pixel
:
1231 case nir_intrinsic_load_barycentric_at_offset
:
1232 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1234 case nir_intrinsic_load_barycentric_centroid
:
1235 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1237 case nir_intrinsic_load_barycentric_sample
:
1238 case nir_intrinsic_load_barycentric_at_sample
:
1239 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1242 unreachable("invalid intrinsic");
1245 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1248 return (enum brw_barycentric_mode
) bary
;
1252 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1254 static enum brw_barycentric_mode
1255 centroid_to_pixel(enum brw_barycentric_mode bary
)
1257 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1258 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1259 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1263 fs_visitor::emit_frontfacing_interpolation()
1265 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1267 if (devinfo
->gen
>= 12) {
1268 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
1270 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1271 bld
.ASR(tmp
, g1
, brw_imm_d(15));
1273 } else if (devinfo
->gen
>= 6) {
1274 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1275 * a boolean result from this (~0/true or 0/false).
1277 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1278 * this task in only one instruction:
1279 * - a negation source modifier will flip the bit; and
1280 * - a W -> D type conversion will sign extend the bit into the high
1281 * word of the destination.
1283 * An ASR 15 fills the low word of the destination.
1285 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1288 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1290 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1291 * a boolean result from this (1/true or 0/false).
1293 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1294 * the negation source modifier to flip it. Unfortunately the SHR
1295 * instruction only operates on UD (or D with an abs source modifier)
1296 * sources without negation.
1298 * Instead, use ASR (which will give ~0/true or 0/false).
1300 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1303 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1310 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1312 assert(stage
== MESA_SHADER_FRAGMENT
);
1313 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1314 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1316 if (wm_prog_data
->persample_dispatch
) {
1317 /* Convert int_sample_pos to floating point */
1318 bld
.MOV(dst
, int_sample_pos
);
1319 /* Scale to the range [0, 1] */
1320 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1323 /* From ARB_sample_shading specification:
1324 * "When rendering to a non-multisample buffer, or if multisample
1325 * rasterization is disabled, gl_SamplePosition will always be
1328 bld
.MOV(dst
, brw_imm_f(0.5f
));
1333 fs_visitor::emit_samplepos_setup()
1335 assert(devinfo
->gen
>= 6);
1337 const fs_builder abld
= bld
.annotate("compute sample position");
1338 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1340 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1341 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1343 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1344 * mode will be enabled.
1346 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1347 * R31.1:0 Position Offset X/Y for Slot[3:0]
1348 * R31.3:2 Position Offset X/Y for Slot[7:4]
1351 * The X, Y sample positions come in as bytes in thread payload. So, read
1352 * the positions using vstride=16, width=8, hstride=2.
1354 const fs_reg sample_pos_reg
=
1355 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1357 /* Compute gl_SamplePosition.x */
1358 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1359 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1361 /* Compute gl_SamplePosition.y */
1362 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1363 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1368 fs_visitor::emit_sampleid_setup()
1370 assert(stage
== MESA_SHADER_FRAGMENT
);
1371 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1372 assert(devinfo
->gen
>= 6);
1374 const fs_builder abld
= bld
.annotate("compute sample id");
1375 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1377 if (!key
->multisample_fbo
) {
1378 /* As per GL_ARB_sample_shading specification:
1379 * "When rendering to a non-multisample buffer, or if multisample
1380 * rasterization is disabled, gl_SampleID will always be zero."
1382 abld
.MOV(*reg
, brw_imm_d(0));
1383 } else if (devinfo
->gen
>= 8) {
1384 /* Sample ID comes in as 4-bit numbers in g1.0:
1386 * 15:12 Slot 3 SampleID (only used in SIMD16)
1387 * 11:8 Slot 2 SampleID (only used in SIMD16)
1388 * 7:4 Slot 1 SampleID
1389 * 3:0 Slot 0 SampleID
1391 * Each slot corresponds to four channels, so we want to replicate each
1392 * half-byte value to 4 channels in a row:
1394 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1395 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1397 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1398 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1400 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1401 * channels to read the first byte (7:0), and the second group of 8
1402 * channels to read the second byte (15:8). Then, we shift right by
1403 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1404 * values into place. Finally, we AND with 0xf to keep the low nibble.
1406 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1407 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1409 * TODO: These payload bits exist on Gen7 too, but they appear to always
1410 * be zero, so this code fails to work. We should find out why.
1412 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1414 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1415 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1416 hbld
.SHR(offset(tmp
, hbld
, i
),
1417 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1419 brw_imm_v(0x44440000));
1422 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1424 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1425 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1427 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1428 * 8x multisampling, subspan 0 will represent sample N (where N
1429 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1430 * 7. We can find the value of N by looking at R0.0 bits 7:6
1431 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1432 * (since samples are always delivered in pairs). That is, we
1433 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1434 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1435 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1436 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1437 * populating a temporary variable with the sequence (0, 1, 2, 3),
1438 * and then reading from it using vstride=1, width=4, hstride=0.
1439 * These computations hold good for 4x multisampling as well.
1441 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1442 * the first four slots are sample 0 of subspan 0; the next four
1443 * are sample 1 of subspan 0; the third group is sample 0 of
1444 * subspan 1, and finally sample 1 of subspan 1.
1447 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1448 * accomodate 16x MSAA.
1450 abld
.exec_all().group(1, 0)
1451 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1453 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1455 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1456 * can assume 4x MSAA. Disallow it on IVB+
1458 * FINISHME: One day, we could come up with a way to do this that
1459 * actually works on gen7.
1461 if (devinfo
->gen
>= 7)
1462 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1463 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1465 /* This special instruction takes care of setting vstride=1,
1466 * width=4, hstride=0 of t2 during an ADD instruction.
1468 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1475 fs_visitor::emit_samplemaskin_setup()
1477 assert(stage
== MESA_SHADER_FRAGMENT
);
1478 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1479 assert(devinfo
->gen
>= 6);
1481 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1483 fs_reg coverage_mask
=
1484 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1486 if (wm_prog_data
->persample_dispatch
) {
1487 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1488 * and a mask representing which sample is being processed by the
1489 * current shader invocation.
1491 * From the OES_sample_variables specification:
1492 * "When per-sample shading is active due to the use of a fragment input
1493 * qualified by "sample" or due to the use of the gl_SampleID or
1494 * gl_SamplePosition variables, only the bit for the current sample is
1495 * set in gl_SampleMaskIn."
1497 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1499 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1500 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1502 fs_reg one
= vgrf(glsl_type::int_type
);
1503 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1504 abld
.MOV(one
, brw_imm_d(1));
1505 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1506 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1508 /* In per-pixel mode, the coverage mask is sufficient. */
1509 *reg
= coverage_mask
;
1515 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1517 if (!src
.abs
&& !src
.negate
)
1520 fs_reg temp
= bld
.vgrf(src
.type
);
1527 fs_visitor::emit_discard_jump()
1529 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1531 /* For performance, after a discard, jump to the end of the
1532 * shader if all relevant channels have been discarded.
1534 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1535 discard_jump
->flag_subreg
= sample_mask_flag_subreg(this);
1537 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1538 discard_jump
->predicate_inverse
= true;
1542 fs_visitor::emit_gs_thread_end()
1544 assert(stage
== MESA_SHADER_GEOMETRY
);
1546 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1548 if (gs_compile
->control_data_header_size_bits
> 0) {
1549 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1552 const fs_builder abld
= bld
.annotate("thread end");
1555 if (gs_prog_data
->static_vertex_count
!= -1) {
1556 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1557 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1558 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1559 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1560 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1563 /* Delete now dead instructions. */
1564 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1570 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1574 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1575 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1576 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1579 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1580 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1581 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1582 sources
[1] = this->final_gs_vertex_count
;
1583 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1584 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1592 fs_visitor::assign_curb_setup()
1594 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1596 unsigned ubo_push_length
= 0;
1597 unsigned ubo_push_start
[4];
1598 for (int i
= 0; i
< 4; i
++) {
1599 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1600 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1603 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1605 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1606 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1607 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1608 if (inst
->src
[i
].file
== UNIFORM
) {
1609 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1611 if (inst
->src
[i
].nr
>= UBO_START
) {
1612 /* constant_nr is in 32-bit units, the rest are in bytes */
1613 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1614 inst
->src
[i
].offset
/ 4;
1615 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1616 constant_nr
= push_constant_loc
[uniform_nr
];
1618 /* Section 5.11 of the OpenGL 4.1 spec says:
1619 * "Out-of-bounds reads return undefined values, which include
1620 * values from other variables of the active program or zero."
1621 * Just return the first push constant.
1626 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1629 brw_reg
.abs
= inst
->src
[i
].abs
;
1630 brw_reg
.negate
= inst
->src
[i
].negate
;
1632 assert(inst
->src
[i
].stride
== 0);
1633 inst
->src
[i
] = byte_offset(
1634 retype(brw_reg
, inst
->src
[i
].type
),
1635 inst
->src
[i
].offset
% 4);
1640 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1641 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1645 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1646 const struct brw_wm_prog_key
*key
,
1647 struct brw_wm_prog_data
*prog_data
,
1648 const nir_shader
*nir
)
1650 memset(prog_data
->urb_setup
, -1,
1651 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1654 /* Figure out where each of the incoming setup attributes lands. */
1655 if (devinfo
->gen
>= 6) {
1656 if (util_bitcount64(nir
->info
.inputs_read
&
1657 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1658 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1659 * first 16 varying inputs, so we can put them wherever we want.
1660 * Just put them in order.
1662 * This is useful because it means that (a) inputs not used by the
1663 * fragment shader won't take up valuable register space, and (b) we
1664 * won't have to recompile the fragment shader if it gets paired with
1665 * a different vertex (or geometry) shader.
1667 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1668 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1669 BITFIELD64_BIT(i
)) {
1670 prog_data
->urb_setup
[i
] = urb_next
++;
1674 /* We have enough input varyings that the SF/SBE pipeline stage can't
1675 * arbitrarily rearrange them to suit our whim; we have to put them
1676 * in an order that matches the output of the previous pipeline stage
1677 * (geometry or vertex shader).
1679 struct brw_vue_map prev_stage_vue_map
;
1680 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1681 key
->input_slots_valid
,
1682 nir
->info
.separate_shader
);
1685 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1686 &prev_stage_vue_map
);
1688 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1689 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1691 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1692 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1693 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1694 BITFIELD64_BIT(varying
))) {
1695 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1698 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1701 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1702 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1703 /* Point size is packed into the header, not as a general attribute */
1704 if (i
== VARYING_SLOT_PSIZ
)
1707 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1708 /* The back color slot is skipped when the front color is
1709 * also written to. In addition, some slots can be
1710 * written in the vertex shader and not read in the
1711 * fragment shader. So the register number must always be
1712 * incremented, mapped or not.
1714 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1715 prog_data
->urb_setup
[i
] = urb_next
;
1721 * It's a FS only attribute, and we did interpolation for this attribute
1722 * in SF thread. So, count it here, too.
1724 * See compile_sf_prog() for more info.
1726 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1727 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1730 prog_data
->num_varying_inputs
= urb_next
;
1734 fs_visitor::assign_urb_setup()
1736 assert(stage
== MESA_SHADER_FRAGMENT
);
1737 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1739 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1741 /* Offset all the urb_setup[] index by the actual position of the
1742 * setup regs, now that the location of the constants has been chosen.
1744 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1745 for (int i
= 0; i
< inst
->sources
; i
++) {
1746 if (inst
->src
[i
].file
== ATTR
) {
1747 /* ATTR regs in the FS are in units of logical scalar inputs each
1748 * of which consumes half of a GRF register.
1750 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1751 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1752 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1753 inst
->src
[i
].offset
;
1754 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1755 1 : MIN2(inst
->exec_size
, 8);
1756 struct brw_reg reg
= stride(
1757 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1759 width
* inst
->src
[i
].stride
,
1760 width
, inst
->src
[i
].stride
);
1761 reg
.abs
= inst
->src
[i
].abs
;
1762 reg
.negate
= inst
->src
[i
].negate
;
1768 /* Each attribute is 4 setup channels, each of which is half a reg. */
1769 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1773 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1775 for (int i
= 0; i
< inst
->sources
; i
++) {
1776 if (inst
->src
[i
].file
== ATTR
) {
1777 int grf
= payload
.num_regs
+
1778 prog_data
->curb_read_length
+
1780 inst
->src
[i
].offset
/ REG_SIZE
;
1782 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1784 * VertStride must be used to cross GRF register boundaries. This
1785 * rule implies that elements within a 'Width' cannot cross GRF
1788 * So, for registers that are large enough, we have to split the exec
1789 * size in two and trust the compression state to sort it out.
1791 unsigned total_size
= inst
->exec_size
*
1792 inst
->src
[i
].stride
*
1793 type_sz(inst
->src
[i
].type
);
1795 assert(total_size
<= 2 * REG_SIZE
);
1796 const unsigned exec_size
=
1797 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1799 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1800 struct brw_reg reg
=
1801 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1802 inst
->src
[i
].offset
% REG_SIZE
),
1803 exec_size
* inst
->src
[i
].stride
,
1804 width
, inst
->src
[i
].stride
);
1805 reg
.abs
= inst
->src
[i
].abs
;
1806 reg
.negate
= inst
->src
[i
].negate
;
1814 fs_visitor::assign_vs_urb_setup()
1816 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1818 assert(stage
== MESA_SHADER_VERTEX
);
1820 /* Each attribute is 4 regs. */
1821 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1823 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1825 /* Rewrite all ATTR file references to the hw grf that they land in. */
1826 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1827 convert_attr_sources_to_hw_regs(inst
);
1832 fs_visitor::assign_tcs_urb_setup()
1834 assert(stage
== MESA_SHADER_TESS_CTRL
);
1836 /* Rewrite all ATTR file references to HW_REGs. */
1837 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1838 convert_attr_sources_to_hw_regs(inst
);
1843 fs_visitor::assign_tes_urb_setup()
1845 assert(stage
== MESA_SHADER_TESS_EVAL
);
1847 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1849 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1851 /* Rewrite all ATTR file references to HW_REGs. */
1852 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1853 convert_attr_sources_to_hw_regs(inst
);
1858 fs_visitor::assign_gs_urb_setup()
1860 assert(stage
== MESA_SHADER_GEOMETRY
);
1862 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1864 first_non_payload_grf
+=
1865 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1867 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1868 /* Rewrite all ATTR file references to GRFs. */
1869 convert_attr_sources_to_hw_regs(inst
);
1875 * Split large virtual GRFs into separate components if we can.
1877 * This is mostly duplicated with what brw_fs_vector_splitting does,
1878 * but that's really conservative because it's afraid of doing
1879 * splitting that doesn't result in real progress after the rest of
1880 * the optimization phases, which would cause infinite looping in
1881 * optimization. We can do it once here, safely. This also has the
1882 * opportunity to split interpolated values, or maybe even uniforms,
1883 * which we don't have at the IR level.
1885 * We want to split, because virtual GRFs are what we register
1886 * allocate and spill (due to contiguousness requirements for some
1887 * instructions), and they're what we naturally generate in the
1888 * codegen process, but most virtual GRFs don't actually need to be
1889 * contiguous sets of GRFs. If we split, we'll end up with reduced
1890 * live intervals and better dead code elimination and coalescing.
1893 fs_visitor::split_virtual_grfs()
1895 /* Compact the register file so we eliminate dead vgrfs. This
1896 * only defines split points for live registers, so if we have
1897 * too large dead registers they will hit assertions later.
1899 compact_virtual_grfs();
1901 int num_vars
= this->alloc
.count
;
1903 /* Count the total number of registers */
1905 int vgrf_to_reg
[num_vars
];
1906 for (int i
= 0; i
< num_vars
; i
++) {
1907 vgrf_to_reg
[i
] = reg_count
;
1908 reg_count
+= alloc
.sizes
[i
];
1911 /* An array of "split points". For each register slot, this indicates
1912 * if this slot can be separated from the previous slot. Every time an
1913 * instruction uses multiple elements of a register (as a source or
1914 * destination), we mark the used slots as inseparable. Then we go
1915 * through and split the registers into the smallest pieces we can.
1917 bool *split_points
= new bool[reg_count
];
1918 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1920 /* Mark all used registers as fully splittable */
1921 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1922 if (inst
->dst
.file
== VGRF
) {
1923 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1924 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1925 split_points
[reg
+ j
] = true;
1928 for (int i
= 0; i
< inst
->sources
; i
++) {
1929 if (inst
->src
[i
].file
== VGRF
) {
1930 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1931 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1932 split_points
[reg
+ j
] = true;
1937 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1938 /* We fix up undef instructions later */
1939 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
1940 /* UNDEF instructions are currently only used to undef entire
1941 * registers. We need this invariant later when we split them.
1943 assert(inst
->dst
.file
== VGRF
);
1944 assert(inst
->dst
.offset
== 0);
1945 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
1949 if (inst
->dst
.file
== VGRF
) {
1950 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1951 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1952 split_points
[reg
+ j
] = false;
1954 for (int i
= 0; i
< inst
->sources
; i
++) {
1955 if (inst
->src
[i
].file
== VGRF
) {
1956 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1957 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1958 split_points
[reg
+ j
] = false;
1963 int *new_virtual_grf
= new int[reg_count
];
1964 int *new_reg_offset
= new int[reg_count
];
1967 for (int i
= 0; i
< num_vars
; i
++) {
1968 /* The first one should always be 0 as a quick sanity check. */
1969 assert(split_points
[reg
] == false);
1972 new_reg_offset
[reg
] = 0;
1977 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1978 /* If this is a split point, reset the offset to 0 and allocate a
1979 * new virtual GRF for the previous offset many registers
1981 if (split_points
[reg
]) {
1982 assert(offset
<= MAX_VGRF_SIZE
);
1983 int grf
= alloc
.allocate(offset
);
1984 for (int k
= reg
- offset
; k
< reg
; k
++)
1985 new_virtual_grf
[k
] = grf
;
1988 new_reg_offset
[reg
] = offset
;
1993 /* The last one gets the original register number */
1994 assert(offset
<= MAX_VGRF_SIZE
);
1995 alloc
.sizes
[i
] = offset
;
1996 for (int k
= reg
- offset
; k
< reg
; k
++)
1997 new_virtual_grf
[k
] = i
;
1999 assert(reg
== reg_count
);
2001 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2002 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2003 const fs_builder
ibld(this, block
, inst
);
2004 assert(inst
->size_written
% REG_SIZE
== 0);
2005 unsigned reg_offset
= 0;
2006 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2007 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2008 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2009 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2011 inst
->remove(block
);
2015 if (inst
->dst
.file
== VGRF
) {
2016 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2017 inst
->dst
.nr
= new_virtual_grf
[reg
];
2018 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2019 inst
->dst
.offset
% REG_SIZE
;
2020 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2022 for (int i
= 0; i
< inst
->sources
; i
++) {
2023 if (inst
->src
[i
].file
== VGRF
) {
2024 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2025 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2026 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2027 inst
->src
[i
].offset
% REG_SIZE
;
2028 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2032 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2034 delete[] split_points
;
2035 delete[] new_virtual_grf
;
2036 delete[] new_reg_offset
;
2040 * Remove unused virtual GRFs and compact the vgrf_* arrays.
2042 * During code generation, we create tons of temporary variables, many of
2043 * which get immediately killed and are never used again. Yet, in later
2044 * optimization and analysis passes, such as compute_live_intervals, we need
2045 * to loop over all the virtual GRFs. Compacting them can save a lot of
2049 fs_visitor::compact_virtual_grfs()
2051 bool progress
= false;
2052 int *remap_table
= new int[this->alloc
.count
];
2053 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2055 /* Mark which virtual GRFs are used. */
2056 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2057 if (inst
->dst
.file
== VGRF
)
2058 remap_table
[inst
->dst
.nr
] = 0;
2060 for (int i
= 0; i
< inst
->sources
; i
++) {
2061 if (inst
->src
[i
].file
== VGRF
)
2062 remap_table
[inst
->src
[i
].nr
] = 0;
2066 /* Compact the GRF arrays. */
2068 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2069 if (remap_table
[i
] == -1) {
2070 /* We just found an unused register. This means that we are
2071 * actually going to compact something.
2075 remap_table
[i
] = new_index
;
2076 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2077 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2082 this->alloc
.count
= new_index
;
2084 /* Patch all the instructions to use the newly renumbered registers */
2085 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2086 if (inst
->dst
.file
== VGRF
)
2087 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2089 for (int i
= 0; i
< inst
->sources
; i
++) {
2090 if (inst
->src
[i
].file
== VGRF
)
2091 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2095 /* Patch all the references to delta_xy, since they're used in register
2096 * allocation. If they're unused, switch them to BAD_FILE so we don't
2097 * think some random VGRF is delta_xy.
2099 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2100 if (delta_xy
[i
].file
== VGRF
) {
2101 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2102 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2104 delta_xy
[i
].file
= BAD_FILE
;
2109 delete[] remap_table
;
2115 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2117 if (prog_data
->nr_params
== 0)
2120 /* The local thread id is always the last parameter in the list */
2121 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2122 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2123 return prog_data
->nr_params
- 1;
2129 * Struct for handling complex alignments.
2131 * A complex alignment is stored as multiplier and an offset. A value is
2132 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2133 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2136 * N | cplx_align_apply({8, 2}, N)
2137 * ----+-----------------------------
2151 #define CPLX_ALIGN_MAX_MUL 8
2154 cplx_align_assert_sane(struct cplx_align a
)
2156 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2157 assert(a
.offset
< a
.mul
);
2161 * Combines two alignments to produce a least multiple of sorts.
2163 * The returned alignment is the smallest (in terms of multiplier) such that
2164 * anything aligned to both a and b will be aligned to the new alignment.
2165 * This function will assert-fail if a and b are not compatible, i.e. if the
2166 * offset parameters are such that no common alignment is possible.
2168 static struct cplx_align
2169 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2171 cplx_align_assert_sane(a
);
2172 cplx_align_assert_sane(b
);
2174 /* Assert that the alignments agree. */
2175 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2177 return a
.mul
> b
.mul
? a
: b
;
2181 * Apply a complex alignment
2183 * This function will return the smallest number greater than or equal to
2184 * offset that is aligned to align.
2187 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2189 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2192 #define UNIFORM_SLOT_SIZE 4
2194 struct uniform_slot_info
{
2195 /** True if the given uniform slot is live */
2198 /** True if this slot and the next slot must remain contiguous */
2199 unsigned contiguous
:1;
2201 struct cplx_align align
;
2205 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2206 unsigned num_slots
, unsigned alignment
)
2208 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2209 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2211 /* We can't align a slot to anything less than the slot size */
2212 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2214 struct cplx_align align
= {alignment
, 0};
2215 cplx_align_assert_sane(align
);
2217 for (unsigned i
= 0; i
< num_slots
; i
++) {
2218 slots
[i
].is_live
= true;
2219 if (i
< num_slots
- 1)
2220 slots
[i
].contiguous
= true;
2222 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2223 if (slots
[i
].align
.mul
== 0) {
2224 slots
[i
].align
= align
;
2226 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2232 * Assign UNIFORM file registers to either push constants or pull constants.
2234 * We allow a fragment shader to have more than the specified minimum
2235 * maximum number of fragment shader uniform components (64). If
2236 * there are too many of these, they'd fill up all of register space.
2237 * So, this will push some of them out to the pull constant buffer and
2238 * update the program to load them.
2241 fs_visitor::assign_constant_locations()
2243 /* Only the first compile gets to decide on locations. */
2244 if (push_constant_loc
) {
2245 assert(pull_constant_loc
);
2249 if (compiler
->compact_params
) {
2250 struct uniform_slot_info slots
[uniforms
+ 1];
2251 memset(slots
, 0, sizeof(slots
));
2253 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2254 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2255 if (inst
->src
[i
].file
!= UNIFORM
)
2258 /* NIR tightly packs things so the uniform number might not be
2259 * aligned (if we have a double right after a float, for
2260 * instance). This is fine because the process of re-arranging
2261 * them will ensure that things are properly aligned. The offset
2262 * into that uniform, however, must be aligned.
2264 * In Vulkan, we have explicit offsets but everything is crammed
2265 * into a single "variable" so inst->src[i].nr will always be 0.
2266 * Everything will be properly aligned relative to that one base.
2268 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2270 unsigned u
= inst
->src
[i
].nr
+
2271 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2276 unsigned slots_read
;
2277 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2278 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2280 unsigned bytes_read
= inst
->components_read(i
) *
2281 type_sz(inst
->src
[i
].type
);
2282 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2285 assert(u
+ slots_read
<= uniforms
);
2286 mark_uniform_slots_read(&slots
[u
], slots_read
,
2287 type_sz(inst
->src
[i
].type
));
2291 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2293 /* Only allow 16 registers (128 uniform components) as push constants.
2295 * Just demote the end of the list. We could probably do better
2296 * here, demoting things that are rarely used in the program first.
2298 * If changing this value, note the limitation about total_regs in
2301 unsigned int max_push_components
= 16 * 8;
2302 if (subgroup_id_index
>= 0)
2303 max_push_components
--; /* Save a slot for the thread ID */
2305 /* We push small arrays, but no bigger than 16 floats. This is big
2306 * enough for a vec4 but hopefully not large enough to push out other
2307 * stuff. We should probably use a better heuristic at some point.
2309 const unsigned int max_chunk_size
= 16;
2311 unsigned int num_push_constants
= 0;
2312 unsigned int num_pull_constants
= 0;
2314 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2315 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2317 /* Default to -1 meaning no location */
2318 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2319 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2321 int chunk_start
= -1;
2322 struct cplx_align align
;
2323 for (unsigned u
= 0; u
< uniforms
; u
++) {
2324 if (!slots
[u
].is_live
) {
2325 assert(chunk_start
== -1);
2329 /* Skip subgroup_id_index to put it in the last push register. */
2330 if (subgroup_id_index
== (int)u
)
2333 if (chunk_start
== -1) {
2335 align
= slots
[u
].align
;
2337 /* Offset into the chunk */
2338 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2340 /* Shift the slot alignment down by the chunk offset so it is
2341 * comparable with the base chunk alignment.
2343 struct cplx_align slot_align
= slots
[u
].align
;
2345 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2347 align
= cplx_align_combine(align
, slot_align
);
2350 /* Sanity check the alignment */
2351 cplx_align_assert_sane(align
);
2353 if (slots
[u
].contiguous
)
2356 /* Adjust the alignment to be in terms of slots, not bytes */
2357 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2358 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2359 align
.mul
/= UNIFORM_SLOT_SIZE
;
2360 align
.offset
/= UNIFORM_SLOT_SIZE
;
2362 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2363 unsigned chunk_size
= u
- chunk_start
+ 1;
2364 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2365 (chunk_size
< max_chunk_size
&&
2366 push_start_align
+ chunk_size
<= max_push_components
)) {
2367 /* Align up the number of push constants */
2368 num_push_constants
= push_start_align
;
2369 for (unsigned i
= 0; i
< chunk_size
; i
++)
2370 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2372 /* We need to pull this one */
2373 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2374 for (unsigned i
= 0; i
< chunk_size
; i
++)
2375 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2378 /* Reset the chunk and start again */
2382 /* Add the CS local thread ID uniform at the end of the push constants */
2383 if (subgroup_id_index
>= 0)
2384 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2386 /* As the uniforms are going to be reordered, stash the old array and
2387 * create two new arrays for push/pull params.
2389 uint32_t *param
= stage_prog_data
->param
;
2390 stage_prog_data
->nr_params
= num_push_constants
;
2391 if (num_push_constants
) {
2392 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2393 num_push_constants
);
2395 stage_prog_data
->param
= NULL
;
2397 assert(stage_prog_data
->nr_pull_params
== 0);
2398 assert(stage_prog_data
->pull_param
== NULL
);
2399 if (num_pull_constants
> 0) {
2400 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2401 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2402 num_pull_constants
);
2405 /* Up until now, the param[] array has been indexed by reg + offset
2406 * of UNIFORM registers. Move pull constants into pull_param[] and
2407 * condense param[] to only contain the uniforms we chose to push.
2409 * NOTE: Because we are condensing the params[] array, we know that
2410 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2411 * having to make a copy.
2413 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2414 uint32_t value
= param
[i
];
2415 if (pull_constant_loc
[i
] != -1) {
2416 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2417 } else if (push_constant_loc
[i
] != -1) {
2418 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2423 /* If we don't want to compact anything, just set up dummy push/pull
2424 * arrays. All the rest of the compiler cares about are these arrays.
2426 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2427 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2429 for (unsigned u
= 0; u
< uniforms
; u
++)
2430 push_constant_loc
[u
] = u
;
2432 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2435 /* Now that we know how many regular uniforms we'll push, reduce the
2436 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2438 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2439 for (int i
= 0; i
< 4; i
++) {
2440 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2442 if (push_length
+ range
->length
> 64)
2443 range
->length
= 64 - push_length
;
2445 push_length
+= range
->length
;
2447 assert(push_length
<= 64);
2451 fs_visitor::get_pull_locs(const fs_reg
&src
,
2452 unsigned *out_surf_index
,
2453 unsigned *out_pull_index
)
2455 assert(src
.file
== UNIFORM
);
2457 if (src
.nr
>= UBO_START
) {
2458 const struct brw_ubo_range
*range
=
2459 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2461 /* If this access is in our (reduced) range, use the push data. */
2462 if (src
.offset
/ 32 < range
->length
)
2465 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2466 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2468 prog_data
->has_ubo_pull
= true;
2472 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2474 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2475 /* A regular uniform push constant */
2476 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2477 *out_pull_index
= pull_constant_loc
[location
];
2479 prog_data
->has_ubo_pull
= true;
2487 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2488 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2491 fs_visitor::lower_constant_loads()
2493 unsigned index
, pull_index
;
2495 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2496 /* Set up the annotation tracking for new generated instructions. */
2497 const fs_builder
ibld(this, block
, inst
);
2499 for (int i
= 0; i
< inst
->sources
; i
++) {
2500 if (inst
->src
[i
].file
!= UNIFORM
)
2503 /* We'll handle this case later */
2504 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2507 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2510 assert(inst
->src
[i
].stride
== 0);
2512 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2513 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2514 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2515 const unsigned base
= pull_index
* 4;
2517 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2518 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2520 /* Rewrite the instruction to use the temporary VGRF. */
2521 inst
->src
[i
].file
= VGRF
;
2522 inst
->src
[i
].nr
= dst
.nr
;
2523 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2524 inst
->src
[i
].offset
% 4;
2527 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2528 inst
->src
[0].file
== UNIFORM
) {
2530 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2533 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2537 inst
->remove(block
);
2540 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
2544 fs_visitor::opt_algebraic()
2546 bool progress
= false;
2548 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2549 switch (inst
->opcode
) {
2550 case BRW_OPCODE_MOV
:
2551 if (!devinfo
->has_64bit_float
&&
2552 !devinfo
->has_64bit_int
&&
2553 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2554 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2555 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2556 assert(inst
->dst
.type
== inst
->src
[0].type
);
2557 assert(!inst
->saturate
);
2558 assert(!inst
->src
[0].abs
);
2559 assert(!inst
->src
[0].negate
);
2560 const brw::fs_builder
ibld(this, block
, inst
);
2562 if (inst
->src
[0].file
== IMM
) {
2563 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2564 brw_imm_ud(inst
->src
[0].u64
>> 32));
2565 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2566 brw_imm_ud(inst
->src
[0].u64
));
2568 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2569 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2570 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2571 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2574 inst
->remove(block
);
2578 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2579 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2580 inst
->dst
.is_null() &&
2581 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2582 inst
->src
[0].abs
= false;
2583 inst
->src
[0].negate
= false;
2588 if (inst
->src
[0].file
!= IMM
)
2591 if (inst
->saturate
) {
2592 /* Full mixed-type saturates don't happen. However, we can end up
2595 * mov.sat(8) g21<1>DF -1F
2597 * Other mixed-size-but-same-base-type cases may also be possible.
2599 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2600 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2601 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2602 assert(!"unimplemented: saturate mixed types");
2604 if (brw_saturate_immediate(inst
->src
[0].type
,
2605 &inst
->src
[0].as_brw_reg())) {
2606 inst
->saturate
= false;
2612 case BRW_OPCODE_MUL
:
2613 if (inst
->src
[1].file
!= IMM
)
2617 if (inst
->src
[1].is_one()) {
2618 inst
->opcode
= BRW_OPCODE_MOV
;
2619 inst
->src
[1] = reg_undef
;
2625 if (inst
->src
[1].is_negative_one()) {
2626 inst
->opcode
= BRW_OPCODE_MOV
;
2627 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2628 inst
->src
[1] = reg_undef
;
2633 if (inst
->src
[0].file
== IMM
) {
2634 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2635 inst
->opcode
= BRW_OPCODE_MOV
;
2636 inst
->src
[0].f
*= inst
->src
[1].f
;
2637 inst
->src
[1] = reg_undef
;
2642 case BRW_OPCODE_ADD
:
2643 if (inst
->src
[1].file
!= IMM
)
2646 if (inst
->src
[0].file
== IMM
) {
2647 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2648 inst
->opcode
= BRW_OPCODE_MOV
;
2649 inst
->src
[0].f
+= inst
->src
[1].f
;
2650 inst
->src
[1] = reg_undef
;
2656 if (inst
->src
[0].equals(inst
->src
[1]) ||
2657 inst
->src
[1].is_zero()) {
2658 /* On Gen8+, the OR instruction can have a source modifier that
2659 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2660 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2662 if (inst
->src
[0].negate
) {
2663 inst
->opcode
= BRW_OPCODE_NOT
;
2664 inst
->src
[0].negate
= false;
2666 inst
->opcode
= BRW_OPCODE_MOV
;
2668 inst
->src
[1] = reg_undef
;
2673 case BRW_OPCODE_CMP
:
2674 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2675 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2676 inst
->src
[1].is_zero() &&
2677 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2678 inst
->src
[0].abs
= false;
2679 inst
->src
[0].negate
= false;
2684 case BRW_OPCODE_SEL
:
2685 if (!devinfo
->has_64bit_float
&&
2686 !devinfo
->has_64bit_int
&&
2687 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2688 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2689 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2690 assert(inst
->dst
.type
== inst
->src
[0].type
);
2691 assert(!inst
->saturate
);
2692 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2693 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2694 const brw::fs_builder
ibld(this, block
, inst
);
2696 set_predicate(inst
->predicate
,
2697 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2698 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2699 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2700 set_predicate(inst
->predicate
,
2701 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2702 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2703 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2705 inst
->remove(block
);
2708 if (inst
->src
[0].equals(inst
->src
[1])) {
2709 inst
->opcode
= BRW_OPCODE_MOV
;
2710 inst
->src
[1] = reg_undef
;
2711 inst
->predicate
= BRW_PREDICATE_NONE
;
2712 inst
->predicate_inverse
= false;
2714 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2715 switch (inst
->conditional_mod
) {
2716 case BRW_CONDITIONAL_LE
:
2717 case BRW_CONDITIONAL_L
:
2718 switch (inst
->src
[1].type
) {
2719 case BRW_REGISTER_TYPE_F
:
2720 if (inst
->src
[1].f
>= 1.0f
) {
2721 inst
->opcode
= BRW_OPCODE_MOV
;
2722 inst
->src
[1] = reg_undef
;
2723 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2731 case BRW_CONDITIONAL_GE
:
2732 case BRW_CONDITIONAL_G
:
2733 switch (inst
->src
[1].type
) {
2734 case BRW_REGISTER_TYPE_F
:
2735 if (inst
->src
[1].f
<= 0.0f
) {
2736 inst
->opcode
= BRW_OPCODE_MOV
;
2737 inst
->src
[1] = reg_undef
;
2738 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2750 case BRW_OPCODE_MAD
:
2751 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2752 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2753 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2755 if (inst
->src
[1].is_one()) {
2756 inst
->opcode
= BRW_OPCODE_ADD
;
2757 inst
->src
[1] = inst
->src
[2];
2758 inst
->src
[2] = reg_undef
;
2760 } else if (inst
->src
[2].is_one()) {
2761 inst
->opcode
= BRW_OPCODE_ADD
;
2762 inst
->src
[2] = reg_undef
;
2766 case SHADER_OPCODE_BROADCAST
:
2767 if (is_uniform(inst
->src
[0])) {
2768 inst
->opcode
= BRW_OPCODE_MOV
;
2770 inst
->force_writemask_all
= true;
2772 } else if (inst
->src
[1].file
== IMM
) {
2773 inst
->opcode
= BRW_OPCODE_MOV
;
2774 /* It's possible that the selected component will be too large and
2775 * overflow the register. This can happen if someone does a
2776 * readInvocation() from GLSL or SPIR-V and provides an OOB
2777 * invocationIndex. If this happens and we some how manage
2778 * to constant fold it in and get here, then component() may cause
2779 * us to start reading outside of the VGRF which will lead to an
2780 * assert later. Instead, just let it wrap around if it goes over
2783 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2784 inst
->src
[0] = component(inst
->src
[0], comp
);
2786 inst
->force_writemask_all
= true;
2791 case SHADER_OPCODE_SHUFFLE
:
2792 if (is_uniform(inst
->src
[0])) {
2793 inst
->opcode
= BRW_OPCODE_MOV
;
2796 } else if (inst
->src
[1].file
== IMM
) {
2797 inst
->opcode
= BRW_OPCODE_MOV
;
2798 inst
->src
[0] = component(inst
->src
[0],
2809 /* Swap if src[0] is immediate. */
2810 if (progress
&& inst
->is_commutative()) {
2811 if (inst
->src
[0].file
== IMM
) {
2812 fs_reg tmp
= inst
->src
[1];
2813 inst
->src
[1] = inst
->src
[0];
2820 invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW
|
2821 DEPENDENCY_INSTRUCTION_DETAIL
);
2827 * Optimize sample messages that have constant zero values for the trailing
2828 * texture coordinates. We can just reduce the message length for these
2829 * instructions instead of reserving a register for it. Trailing parameters
2830 * that aren't sent default to zero anyway. This will cause the dead code
2831 * eliminator to remove the MOV instruction that would otherwise be emitted to
2832 * set up the zero value.
2835 fs_visitor::opt_zero_samples()
2837 /* Gen4 infers the texturing opcode based on the message length so we can't
2840 if (devinfo
->gen
< 5)
2843 bool progress
= false;
2845 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2846 if (!inst
->is_tex())
2849 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2851 if (load_payload
->is_head_sentinel() ||
2852 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2855 /* We don't want to remove the message header or the first parameter.
2856 * Removing the first parameter is not allowed, see the Haswell PRM
2857 * volume 7, page 149:
2859 * "Parameter 0 is required except for the sampleinfo message, which
2860 * has no parameter 0"
2862 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2863 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2864 (inst
->exec_size
/ 8) +
2865 inst
->header_size
- 1].is_zero()) {
2866 inst
->mlen
-= inst
->exec_size
/ 8;
2872 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
2878 * Optimize sample messages which are followed by the final RT write.
2880 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2881 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2882 * final texturing results copied to the framebuffer write payload and modify
2883 * them to write to the framebuffer directly.
2886 fs_visitor::opt_sampler_eot()
2888 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2890 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2893 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2896 /* FINISHME: It should be possible to implement this optimization when there
2897 * are multiple drawbuffers.
2899 if (key
->nr_color_regions
!= 1)
2902 /* Requires emitting a bunch of saturating MOV instructions during logical
2903 * send lowering to clamp the color payload, which the sampler unit isn't
2904 * going to do for us.
2906 if (key
->clamp_fragment_color
)
2909 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2910 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2911 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2912 assert(fb_write
->eot
);
2913 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2915 /* There wasn't one; nothing to do. */
2916 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2919 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2921 /* 3D Sampler » Messages » Message Format
2923 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2924 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2926 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2927 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2928 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2929 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2930 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2931 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2932 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2933 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2936 /* XXX - This shouldn't be necessary. */
2937 if (tex_inst
->prev
->is_head_sentinel())
2940 /* Check that the FB write sources are fully initialized by the single
2941 * texturing instruction.
2943 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2944 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2945 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2946 fb_write
->size_read(i
) != tex_inst
->size_written
)
2948 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2949 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2954 assert(!tex_inst
->eot
); /* We can't get here twice */
2955 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2957 const fs_builder
ibld(this, block
, tex_inst
);
2959 tex_inst
->offset
|= fb_write
->target
<< 24;
2960 tex_inst
->eot
= true;
2961 tex_inst
->dst
= ibld
.null_reg_ud();
2962 tex_inst
->size_written
= 0;
2963 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2965 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2966 * flag and submit a header together with the sampler message as required
2969 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
2974 fs_visitor::opt_register_renaming()
2976 bool progress
= false;
2979 unsigned remap
[alloc
.count
];
2980 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
2982 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2983 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2985 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2986 inst
->opcode
== BRW_OPCODE_WHILE
) {
2990 /* Rewrite instruction sources. */
2991 for (int i
= 0; i
< inst
->sources
; i
++) {
2992 if (inst
->src
[i
].file
== VGRF
&&
2993 remap
[inst
->src
[i
].nr
] != ~0u &&
2994 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2995 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
3000 const unsigned dst
= inst
->dst
.nr
;
3003 inst
->dst
.file
== VGRF
&&
3004 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
3005 !inst
->is_partial_write()) {
3006 if (remap
[dst
] == ~0u) {
3009 remap
[dst
] = alloc
.allocate(regs_written(inst
));
3010 inst
->dst
.nr
= remap
[dst
];
3013 } else if (inst
->dst
.file
== VGRF
&&
3014 remap
[dst
] != ~0u &&
3015 remap
[dst
] != dst
) {
3016 inst
->dst
.nr
= remap
[dst
];
3022 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
3023 DEPENDENCY_VARIABLES
);
3025 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3026 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3027 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3036 * Remove redundant or useless discard jumps.
3038 * For example, we can eliminate jumps in the following sequence:
3040 * discard-jump (redundant with the next jump)
3041 * discard-jump (useless; jumps to the next instruction)
3045 fs_visitor::opt_redundant_discard_jumps()
3047 bool progress
= false;
3049 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3051 fs_inst
*placeholder_halt
= NULL
;
3052 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3053 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3054 placeholder_halt
= inst
;
3059 if (!placeholder_halt
)
3062 /* Delete any HALTs immediately before the placeholder halt. */
3063 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3064 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3065 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3066 prev
->remove(last_bblock
);
3071 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3077 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3078 * from \p r.offset which overlaps the region starting at \p s.offset and
3079 * spanning \p ds bytes.
3081 static inline unsigned
3082 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3084 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3085 const int shift
= rel_offset
/ REG_SIZE
;
3086 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3087 assert(reg_space(r
) == reg_space(s
) &&
3088 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3089 return ((1 << n
) - 1) << shift
;
3093 fs_visitor::compute_to_mrf()
3095 bool progress
= false;
3098 /* No MRFs on Gen >= 7. */
3099 if (devinfo
->gen
>= 7)
3102 const fs_live_variables
&live
= live_analysis
.require();
3104 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3108 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3109 inst
->is_partial_write() ||
3110 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3111 inst
->dst
.type
!= inst
->src
[0].type
||
3112 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3113 !inst
->src
[0].is_contiguous() ||
3114 inst
->src
[0].offset
% REG_SIZE
!= 0)
3117 /* Can't compute-to-MRF this GRF if someone else was going to
3120 if (live
.vgrf_end
[inst
->src
[0].nr
] > ip
)
3123 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3124 * things that computed the value of all GRFs of the source region. The
3125 * regs_left bitset keeps track of the registers we haven't yet found a
3126 * generating instruction for.
3128 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3130 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3131 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3132 inst
->src
[0], inst
->size_read(0))) {
3133 /* Found the last thing to write our reg we want to turn
3134 * into a compute-to-MRF.
3137 /* If this one instruction didn't populate all the
3138 * channels, bail. We might be able to rewrite everything
3139 * that writes that reg, but it would require smarter
3142 if (scan_inst
->is_partial_write())
3145 /* Handling things not fully contained in the source of the copy
3146 * would need us to understand coalescing out more than one MOV at
3149 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3150 inst
->src
[0], inst
->size_read(0)))
3153 /* SEND instructions can't have MRF as a destination. */
3154 if (scan_inst
->mlen
)
3157 if (devinfo
->gen
== 6) {
3158 /* gen6 math instructions must have the destination be
3159 * GRF, so no compute-to-MRF for them.
3161 if (scan_inst
->is_math()) {
3166 /* Clear the bits for any registers this instruction overwrites. */
3167 regs_left
&= ~mask_relative_to(
3168 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3173 /* We don't handle control flow here. Most computation of
3174 * values that end up in MRFs are shortly before the MRF
3177 if (block
->start() == scan_inst
)
3180 /* You can't read from an MRF, so if someone else reads our
3181 * MRF's source GRF that we wanted to rewrite, that stops us.
3183 bool interfered
= false;
3184 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3185 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3186 inst
->src
[0], inst
->size_read(0))) {
3193 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3194 inst
->dst
, inst
->size_written
)) {
3195 /* If somebody else writes our MRF here, we can't
3196 * compute-to-MRF before that.
3201 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3202 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3203 inst
->dst
, inst
->size_written
)) {
3204 /* Found a SEND instruction, which means that there are
3205 * live values in MRFs from base_mrf to base_mrf +
3206 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3216 /* Found all generating instructions of our MRF's source value, so it
3217 * should be safe to rewrite them to point to the MRF directly.
3219 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3221 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3222 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3223 inst
->src
[0], inst
->size_read(0))) {
3224 /* Clear the bits for any registers this instruction overwrites. */
3225 regs_left
&= ~mask_relative_to(
3226 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3228 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3229 reg_offset(inst
->src
[0]);
3231 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3232 /* Apply the same address transformation done by the hardware
3233 * for COMPR4 MRF writes.
3235 assert(rel_offset
< 2 * REG_SIZE
);
3236 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3238 /* Clear the COMPR4 bit if the generating instruction is not
3241 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3242 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3245 /* Calculate the MRF number the result of this instruction is
3246 * ultimately written to.
3248 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3251 scan_inst
->dst
.file
= MRF
;
3252 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3253 scan_inst
->saturate
|= inst
->saturate
;
3260 inst
->remove(block
);
3265 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3271 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3272 * flow. We could probably do better here with some form of divergence
3276 fs_visitor::eliminate_find_live_channel()
3278 bool progress
= false;
3281 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3282 /* The optimization below assumes that channel zero is live on thread
3283 * dispatch, which may not be the case if the fixed function dispatches
3289 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3290 switch (inst
->opcode
) {
3296 case BRW_OPCODE_ENDIF
:
3297 case BRW_OPCODE_WHILE
:
3301 case FS_OPCODE_DISCARD_JUMP
:
3302 /* This can potentially make control flow non-uniform until the end
3307 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3309 inst
->opcode
= BRW_OPCODE_MOV
;
3310 inst
->src
[0] = brw_imm_ud(0u);
3312 inst
->force_writemask_all
= true;
3323 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
3329 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3330 * instructions to FS_OPCODE_REP_FB_WRITE.
3333 fs_visitor::emit_repclear_shader()
3335 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3337 int color_mrf
= base_mrf
+ 2;
3341 mov
= bld
.exec_all().group(4, 0)
3342 .MOV(brw_message_reg(color_mrf
),
3343 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3345 struct brw_reg reg
=
3346 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3347 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3348 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3350 mov
= bld
.exec_all().group(4, 0)
3351 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3354 fs_inst
*write
= NULL
;
3355 if (key
->nr_color_regions
== 1) {
3356 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3357 write
->saturate
= key
->clamp_fragment_color
;
3358 write
->base_mrf
= color_mrf
;
3360 write
->header_size
= 0;
3363 assume(key
->nr_color_regions
> 0);
3365 struct brw_reg header
=
3366 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3367 bld
.exec_all().group(16, 0)
3368 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3370 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3372 bld
.exec_all().group(1, 0)
3373 .MOV(component(header
, 2), brw_imm_ud(i
));
3376 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3377 write
->saturate
= key
->clamp_fragment_color
;
3378 write
->base_mrf
= base_mrf
;
3380 write
->header_size
= 2;
3385 write
->last_rt
= true;
3389 assign_constant_locations();
3390 assign_curb_setup();
3392 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3394 assert(mov
->src
[0].file
== FIXED_GRF
);
3395 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3402 * Walks through basic blocks, looking for repeated MRF writes and
3403 * removing the later ones.
3406 fs_visitor::remove_duplicate_mrf_writes()
3408 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3409 bool progress
= false;
3411 /* Need to update the MRF tracking for compressed instructions. */
3412 if (dispatch_width
>= 16)
3415 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3417 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3418 if (inst
->is_control_flow()) {
3419 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3422 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3423 inst
->dst
.file
== MRF
) {
3424 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3425 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3426 inst
->dst
.equals(prev_inst
->dst
) &&
3427 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3428 inst
->saturate
== prev_inst
->saturate
&&
3429 inst
->predicate
== prev_inst
->predicate
&&
3430 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3431 inst
->exec_size
== prev_inst
->exec_size
) {
3432 inst
->remove(block
);
3438 /* Clear out the last-write records for MRFs that were overwritten. */
3439 if (inst
->dst
.file
== MRF
) {
3440 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3443 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3444 /* Found a SEND instruction, which will include two or fewer
3445 * implied MRF writes. We could do better here.
3447 for (unsigned i
= 0; i
< inst
->implied_mrf_writes(); i
++) {
3448 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3452 /* Clear out any MRF move records whose sources got overwritten. */
3453 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3454 if (last_mrf_move
[i
] &&
3455 regions_overlap(inst
->dst
, inst
->size_written
,
3456 last_mrf_move
[i
]->src
[0],
3457 last_mrf_move
[i
]->size_read(0))) {
3458 last_mrf_move
[i
] = NULL
;
3462 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3463 inst
->dst
.file
== MRF
&&
3464 inst
->src
[0].file
!= ARF
&&
3465 !inst
->is_partial_write()) {
3466 last_mrf_move
[inst
->dst
.nr
] = inst
;
3471 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3477 * Rounding modes for conversion instructions are included for each
3478 * conversion, but right now it is a state. So once it is set,
3479 * we don't need to call it again for subsequent calls.
3481 * This is useful for vector/matrices conversions, as setting the
3482 * mode once is enough for the full vector/matrix
3485 fs_visitor::remove_extra_rounding_modes()
3487 bool progress
= false;
3488 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3490 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3491 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3492 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3493 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3495 base_mode
= BRW_RND_MODE_RTNE
;
3496 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3497 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3498 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3500 base_mode
= BRW_RND_MODE_RTZ
;
3502 foreach_block (block
, cfg
) {
3503 brw_rnd_mode prev_mode
= base_mode
;
3505 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3506 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3507 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3508 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3509 if (mode
== prev_mode
) {
3510 inst
->remove(block
);
3520 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3526 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3528 /* Clear the flag for registers that actually got read (as expected). */
3529 for (int i
= 0; i
< inst
->sources
; i
++) {
3531 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3532 grf
= inst
->src
[i
].nr
;
3537 if (grf
>= first_grf
&&
3538 grf
< first_grf
+ grf_len
) {
3539 deps
[grf
- first_grf
] = false;
3540 if (inst
->exec_size
== 16)
3541 deps
[grf
- first_grf
+ 1] = false;
3547 * Implements this workaround for the original 965:
3549 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3550 * check for post destination dependencies on this instruction, software
3551 * must ensure that there is no destination hazard for the case of ‘write
3552 * followed by a posted write’ shown in the following example.
3555 * 2. send r3.xy <rest of send instruction>
3558 * Due to no post-destination dependency check on the ‘send’, the above
3559 * code sequence could have two instructions (1 and 2) in flight at the
3560 * same time that both consider ‘r3’ as the target of their final writes.
3563 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3566 int write_len
= regs_written(inst
);
3567 int first_write_grf
= inst
->dst
.nr
;
3568 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3569 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3571 memset(needs_dep
, false, sizeof(needs_dep
));
3572 memset(needs_dep
, true, write_len
);
3574 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3576 /* Walk backwards looking for writes to registers we're writing which
3577 * aren't read since being written. If we hit the start of the program,
3578 * we assume that there are no outstanding dependencies on entry to the
3581 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3582 /* If we hit control flow, assume that there *are* outstanding
3583 * dependencies, and force their cleanup before our instruction.
3585 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3586 for (int i
= 0; i
< write_len
; i
++) {
3588 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3589 first_write_grf
+ i
);
3594 /* We insert our reads as late as possible on the assumption that any
3595 * instruction but a MOV that might have left us an outstanding
3596 * dependency has more latency than a MOV.
3598 if (scan_inst
->dst
.file
== VGRF
) {
3599 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3600 int reg
= scan_inst
->dst
.nr
+ i
;
3602 if (reg
>= first_write_grf
&&
3603 reg
< first_write_grf
+ write_len
&&
3604 needs_dep
[reg
- first_write_grf
]) {
3605 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3606 needs_dep
[reg
- first_write_grf
] = false;
3607 if (scan_inst
->exec_size
== 16)
3608 needs_dep
[reg
- first_write_grf
+ 1] = false;
3613 /* Clear the flag for registers that actually got read (as expected). */
3614 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3616 /* Continue the loop only if we haven't resolved all the dependencies */
3618 for (i
= 0; i
< write_len
; i
++) {
3628 * Implements this workaround for the original 965:
3630 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3631 * used as a destination register until after it has been sourced by an
3632 * instruction with a different destination register.
3635 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3637 int write_len
= regs_written(inst
);
3638 unsigned first_write_grf
= inst
->dst
.nr
;
3639 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3640 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3642 memset(needs_dep
, false, sizeof(needs_dep
));
3643 memset(needs_dep
, true, write_len
);
3644 /* Walk forwards looking for writes to registers we're writing which aren't
3645 * read before being written.
3647 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3648 /* If we hit control flow, force resolve all remaining dependencies. */
3649 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3650 for (int i
= 0; i
< write_len
; i
++) {
3652 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3653 first_write_grf
+ i
);
3658 /* Clear the flag for registers that actually got read (as expected). */
3659 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3661 /* We insert our reads as late as possible since they're reading the
3662 * result of a SEND, which has massive latency.
3664 if (scan_inst
->dst
.file
== VGRF
&&
3665 scan_inst
->dst
.nr
>= first_write_grf
&&
3666 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3667 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3668 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3670 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3673 /* Continue the loop only if we haven't resolved all the dependencies */
3675 for (i
= 0; i
< write_len
; i
++) {
3685 fs_visitor::insert_gen4_send_dependency_workarounds()
3687 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3690 bool progress
= false;
3692 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3693 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3694 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3695 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3701 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3705 * Turns the generic expression-style uniform pull constant load instruction
3706 * into a hardware-specific series of instructions for loading a pull
3709 * The expression style allows the CSE pass before this to optimize out
3710 * repeated loads from the same offset, and gives the pre-register-allocation
3711 * scheduling full flexibility, while the conversion to native instructions
3712 * allows the post-register-allocation scheduler the best information
3715 * Note that execution masking for setting up pull constant loads is special:
3716 * the channels that need to be written are unrelated to the current execution
3717 * mask, since a later instruction will use one of the result channels as a
3718 * source operand for all 8 or 16 of its channels.
3721 fs_visitor::lower_uniform_pull_constant_loads()
3723 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3724 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3727 if (devinfo
->gen
>= 7) {
3728 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3729 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3731 ubld
.group(8, 0).MOV(payload
,
3732 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3733 ubld
.group(1, 0).MOV(component(payload
, 2),
3734 brw_imm_ud(inst
->src
[1].ud
/ 16));
3736 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3737 inst
->src
[1] = payload
;
3738 inst
->header_size
= 1;
3741 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
3743 /* Before register allocation, we didn't tell the scheduler about the
3744 * MRF we use. We know it's safe to use this MRF because nothing
3745 * else does except for register spill/unspill, which generates and
3746 * uses its MRF within a single IR instruction.
3748 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3755 fs_visitor::lower_load_payload()
3757 bool progress
= false;
3759 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3760 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3763 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3764 assert(inst
->saturate
== false);
3765 fs_reg dst
= inst
->dst
;
3767 /* Get rid of COMPR4. We'll add it back in if we need it */
3768 if (dst
.file
== MRF
)
3769 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3771 const fs_builder
ibld(this, block
, inst
);
3772 const fs_builder ubld
= ibld
.exec_all();
3774 for (uint8_t i
= 0; i
< inst
->header_size
;) {
3775 /* Number of header GRFs to initialize at once with a single MOV
3779 (i
+ 1 < inst
->header_size
&& inst
->src
[i
].stride
== 1 &&
3780 inst
->src
[i
+ 1].equals(byte_offset(inst
->src
[i
], REG_SIZE
))) ?
3783 if (inst
->src
[i
].file
!= BAD_FILE
)
3784 ubld
.group(8 * n
, 0).MOV(retype(dst
, BRW_REGISTER_TYPE_UD
),
3785 retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
));
3787 dst
= byte_offset(dst
, n
* REG_SIZE
);
3791 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3792 inst
->exec_size
> 8) {
3793 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3794 * a straightforward copy. Instead, the result of the
3795 * LOAD_PAYLOAD is treated as interleaved and the first four
3796 * non-header sources are unpacked as:
3807 * This is used for gen <= 5 fb writes.
3809 assert(inst
->exec_size
== 16);
3810 assert(inst
->header_size
+ 4 <= inst
->sources
);
3811 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3812 if (inst
->src
[i
].file
!= BAD_FILE
) {
3813 if (devinfo
->has_compr4
) {
3814 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3815 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3816 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3818 /* Platform doesn't have COMPR4. We have to fake it */
3819 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3820 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3822 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3829 /* The loop above only ever incremented us through the first set
3830 * of 4 registers. However, thanks to the magic of COMPR4, we
3831 * actually wrote to the first 8 registers, so we need to take
3832 * that into account now.
3836 /* The COMPR4 code took care of the first 4 sources. We'll let
3837 * the regular path handle any remaining sources. Yes, we are
3838 * modifying the instruction but we're about to delete it so
3839 * this really doesn't hurt anything.
3841 inst
->header_size
+= 4;
3844 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3845 if (inst
->src
[i
].file
!= BAD_FILE
) {
3846 dst
.type
= inst
->src
[i
].type
;
3847 ibld
.MOV(dst
, inst
->src
[i
]);
3849 dst
.type
= BRW_REGISTER_TYPE_UD
;
3851 dst
= offset(dst
, ibld
, 1);
3854 inst
->remove(block
);
3859 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3865 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3867 const fs_builder
ibld(this, block
, inst
);
3869 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3870 if (inst
->src
[1].file
== IMM
&&
3871 (( ud
&& inst
->src
[1].ud
<= UINT16_MAX
) ||
3872 (!ud
&& inst
->src
[1].d
<= INT16_MAX
&& inst
->src
[1].d
>= INT16_MIN
))) {
3873 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3874 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3877 * If multiplying by an immediate value that fits in 16-bits, do a
3878 * single MUL instruction with that value in the proper location.
3880 if (devinfo
->gen
< 7) {
3881 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3882 ibld
.MOV(imm
, inst
->src
[1]);
3883 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3885 ibld
.MUL(inst
->dst
, inst
->src
[0],
3886 ud
? brw_imm_uw(inst
->src
[1].ud
)
3887 : brw_imm_w(inst
->src
[1].d
));
3890 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3891 * do 32-bit integer multiplication in one instruction, but instead
3892 * must do a sequence (which actually calculates a 64-bit result):
3894 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3895 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3896 * mov(8) g2<1>D acc0<8,8,1>D
3898 * But on Gen > 6, the ability to use second accumulator register
3899 * (acc1) for non-float data types was removed, preventing a simple
3900 * implementation in SIMD16. A 16-channel result can be calculated by
3901 * executing the three instructions twice in SIMD8, once with quarter
3902 * control of 1Q for the first eight channels and again with 2Q for
3903 * the second eight channels.
3905 * Which accumulator register is implicitly accessed (by AccWrEnable
3906 * for instance) is determined by the quarter control. Unfortunately
3907 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3908 * implicit accumulator access by an instruction with 2Q will access
3909 * acc1 regardless of whether the data type is usable in acc1.
3911 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3912 * integer data types.
3914 * Since we only want the low 32-bits of the result, we can do two
3915 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3916 * adjust the high result and add them (like the mach is doing):
3918 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3919 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3920 * shl(8) g9<1>D g8<8,8,1>D 16D
3921 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3923 * We avoid the shl instruction by realizing that we only want to add
3924 * the low 16-bits of the "high" result to the high 16-bits of the
3925 * "low" result and using proper regioning on the add:
3927 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3928 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3929 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3931 * Since it does not use the (single) accumulator register, we can
3932 * schedule multi-component multiplications much better.
3935 bool needs_mov
= false;
3936 fs_reg orig_dst
= inst
->dst
;
3938 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
3939 * reusing the original destination is impossible due to hardware
3940 * restrictions, source/destination overlap, or it being the null
3943 fs_reg low
= inst
->dst
;
3944 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3945 regions_overlap(inst
->dst
, inst
->size_written
,
3946 inst
->src
[0], inst
->size_read(0)) ||
3947 regions_overlap(inst
->dst
, inst
->size_written
,
3948 inst
->src
[1], inst
->size_read(1)) ||
3949 inst
->dst
.stride
>= 4) {
3951 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3955 /* Get a new VGRF but keep the same stride as inst->dst */
3956 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
3957 high
.stride
= inst
->dst
.stride
;
3958 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3960 if (devinfo
->gen
>= 7) {
3961 if (inst
->src
[1].abs
)
3962 lower_src_modifiers(this, block
, inst
, 1);
3964 if (inst
->src
[1].file
== IMM
) {
3965 ibld
.MUL(low
, inst
->src
[0],
3966 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3967 ibld
.MUL(high
, inst
->src
[0],
3968 brw_imm_uw(inst
->src
[1].ud
>> 16));
3970 ibld
.MUL(low
, inst
->src
[0],
3971 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3972 ibld
.MUL(high
, inst
->src
[0],
3973 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3976 if (inst
->src
[0].abs
)
3977 lower_src_modifiers(this, block
, inst
, 0);
3979 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3981 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3985 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3986 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3987 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3989 if (needs_mov
|| inst
->conditional_mod
)
3990 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
3995 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
3997 const fs_builder
ibld(this, block
, inst
);
3999 /* Considering two 64-bit integers ab and cd where each letter ab
4000 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
4001 * only need to provide the YZ part of the result. -------
4003 * Only BD needs to be 64 bits. For AD and BC we only care + AD
4004 * about the lower 32 bits (since they are part of the upper + BC
4005 * 32 bits of our result). AC is not needed since it starts + AC
4006 * on the 65th bit of the result. -------
4009 unsigned int q_regs
= regs_written(inst
);
4010 unsigned int d_regs
= (q_regs
+ 1) / 2;
4012 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
4013 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4014 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4016 /* Here we need the full 64 bit result for 32b * 32b. */
4017 if (devinfo
->has_integer_dword_mul
) {
4018 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4019 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4021 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4022 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4023 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4025 fs_inst
*mul
= ibld
.MUL(acc
,
4026 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4027 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4028 mul
->writes_accumulator
= true;
4030 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4031 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4032 ibld
.MOV(bd_low
, acc
);
4034 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4035 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4038 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4039 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4040 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4041 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4043 ibld
.ADD(ad
, ad
, bc
);
4044 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4045 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4047 ibld
.MOV(inst
->dst
, bd
);
4051 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4053 const fs_builder
ibld(this, block
, inst
);
4055 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4056 * High" instruction:
4058 * "An added preliminary mov is required for source modification on
4060 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4061 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4062 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4064 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4065 lower_src_modifiers(this, block
, inst
, 1);
4067 /* Should have been lowered to 8-wide. */
4068 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4069 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4070 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4071 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4073 if (devinfo
->gen
>= 8) {
4074 /* Until Gen8, integer multiplies read 32-bits from one source,
4075 * and 16-bits from the other, and relying on the MACH instruction
4076 * to generate the high bits of the result.
4078 * On Gen8, the multiply instruction does a full 32x32-bit
4079 * multiply, but in order to do a 64-bit multiply we can simulate
4080 * the previous behavior and then use a MACH instruction.
4082 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4083 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4084 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4085 mul
->src
[1].stride
*= 2;
4087 if (mul
->src
[1].file
== IMM
) {
4088 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4090 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4092 /* Among other things the quarter control bits influence which
4093 * accumulator register is used by the hardware for instructions
4094 * that access the accumulator implicitly (e.g. MACH). A
4095 * second-half instruction would normally map to acc1, which
4096 * doesn't exist on Gen7 and up (the hardware does emulate it for
4097 * floating-point instructions *only* by taking advantage of the
4098 * extra precision of acc0 not normally used for floating point
4101 * HSW and up are careful enough not to try to access an
4102 * accumulator register that doesn't exist, but on earlier Gen7
4103 * hardware we need to make sure that the quarter control bits are
4104 * zero to avoid non-deterministic behaviour and emit an extra MOV
4105 * to get the result masked correctly according to the current
4109 mach
->force_writemask_all
= true;
4110 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4111 ibld
.MOV(inst
->dst
, mach
->dst
);
4116 fs_visitor::lower_integer_multiplication()
4118 bool progress
= false;
4120 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4121 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4122 /* If the instruction is already in a form that does not need lowering,
4125 if (devinfo
->gen
>= 7) {
4126 if (type_sz(inst
->src
[1].type
) < 4 && type_sz(inst
->src
[0].type
) <= 4)
4129 if (type_sz(inst
->src
[0].type
) < 4 && type_sz(inst
->src
[1].type
) <= 4)
4133 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4134 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4135 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4136 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4137 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4138 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4139 lower_mul_qword_inst(inst
, block
);
4140 inst
->remove(block
);
4142 } else if (!inst
->dst
.is_accumulator() &&
4143 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4144 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4145 !devinfo
->has_integer_dword_mul
) {
4146 lower_mul_dword_inst(inst
, block
);
4147 inst
->remove(block
);
4150 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4151 lower_mulh_inst(inst
, block
);
4152 inst
->remove(block
);
4159 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4165 fs_visitor::lower_minmax()
4167 assert(devinfo
->gen
< 6);
4169 bool progress
= false;
4171 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4172 const fs_builder
ibld(this, block
, inst
);
4174 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4175 inst
->predicate
== BRW_PREDICATE_NONE
) {
4176 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4177 * the original SEL.L/GE instruction
4179 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4180 inst
->conditional_mod
);
4181 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4182 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4189 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
4195 fs_visitor::lower_sub_sat()
4197 bool progress
= false;
4199 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4200 const fs_builder
ibld(this, block
, inst
);
4202 if (inst
->opcode
== SHADER_OPCODE_USUB_SAT
||
4203 inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4204 /* The fundamental problem is the hardware performs source negation
4205 * at the bit width of the source. If the source is 0x80000000D, the
4206 * negation is 0x80000000D. As a result, subtractSaturate(0,
4207 * 0x80000000) will produce 0x80000000 instead of 0x7fffffff. There
4208 * are at least three ways to resolve this:
4210 * 1. Use the accumulator for the negated source. The accumulator is
4211 * 33 bits, so our source 0x80000000 is sign-extended to
4212 * 0x1800000000. The negation of which is 0x080000000. This
4213 * doesn't help for 64-bit integers (which are already bigger than
4214 * 33 bits). There are also only 8 accumulators, so SIMD16 or
4215 * SIMD32 instructions would have to be split into multiple SIMD8
4218 * 2. Use slightly different math. For any n-bit value x, we know (x
4219 * >> 1) != -(x >> 1). We can use this fact to only do
4220 * subtractions involving (x >> 1). subtractSaturate(a, b) ==
4221 * subtractSaturate(subtractSaturate(a, (b >> 1)), b - (b >> 1)).
4223 * 3. For unsigned sources, it is sufficient to replace the
4224 * subtractSaturate with (a > b) ? a - b : 0.
4226 * It may also be possible to use the SUBB instruction. This
4227 * implicitly writes the accumulator, so it could only be used in the
4228 * same situations as #1 above. It is further limited by only
4229 * allowing UD sources.
4231 if (inst
->exec_size
== 8 && inst
->src
[0].type
!= BRW_REGISTER_TYPE_Q
&&
4232 inst
->src
[0].type
!= BRW_REGISTER_TYPE_UQ
) {
4233 fs_reg
acc(ARF
, BRW_ARF_ACCUMULATOR
, inst
->src
[1].type
);
4235 ibld
.MOV(acc
, inst
->src
[1]);
4236 fs_inst
*add
= ibld
.ADD(inst
->dst
, acc
, inst
->src
[0]);
4237 add
->saturate
= true;
4238 add
->src
[0].negate
= true;
4239 } else if (inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4241 * dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp));
4243 fs_reg tmp1
= ibld
.vgrf(inst
->src
[0].type
);
4244 fs_reg tmp2
= ibld
.vgrf(inst
->src
[0].type
);
4245 fs_reg tmp3
= ibld
.vgrf(inst
->src
[0].type
);
4248 ibld
.SHR(tmp1
, inst
->src
[1], brw_imm_d(1));
4250 add
= ibld
.ADD(tmp2
, inst
->src
[1], tmp1
);
4251 add
->src
[1].negate
= true;
4253 add
= ibld
.ADD(tmp3
, inst
->src
[0], tmp1
);
4254 add
->src
[1].negate
= true;
4255 add
->saturate
= true;
4257 add
= ibld
.ADD(inst
->dst
, tmp3
, tmp2
);
4258 add
->src
[1].negate
= true;
4259 add
->saturate
= true;
4261 /* a > b ? a - b : 0 */
4262 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4265 fs_inst
*add
= ibld
.ADD(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4266 add
->src
[1].negate
= !add
->src
[1].negate
;
4268 ibld
.SEL(inst
->dst
, inst
->dst
, brw_imm_ud(0))
4269 ->predicate
= BRW_PREDICATE_NORMAL
;
4272 inst
->remove(block
);
4278 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4284 * Get the mask of SIMD channels enabled during dispatch and not yet disabled
4285 * by discard. Due to the layout of the sample mask in the fragment shader
4286 * thread payload, \p bld is required to have a dispatch_width() not greater
4287 * than 16 for fragment shaders.
4290 sample_mask_reg(const fs_builder
&bld
)
4292 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
4294 if (v
->stage
!= MESA_SHADER_FRAGMENT
) {
4295 return brw_imm_ud(0xffffffff);
4296 } else if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
4297 assert(bld
.dispatch_width() <= 16);
4298 return brw_flag_subreg(sample_mask_flag_subreg(v
) + bld
.group() / 16);
4300 assert(v
->devinfo
->gen
>= 6 && bld
.dispatch_width() <= 16);
4301 return retype(brw_vec1_grf((bld
.group() >= 16 ? 2 : 1), 7),
4302 BRW_REGISTER_TYPE_UW
);
4307 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4308 fs_reg
*dst
, fs_reg color
, unsigned components
)
4310 if (key
->clamp_fragment_color
) {
4311 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4312 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4314 for (unsigned i
= 0; i
< components
; i
++)
4316 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4321 for (unsigned i
= 0; i
< components
; i
++)
4322 dst
[i
] = offset(color
, bld
, i
);
4326 brw_fb_write_msg_control(const fs_inst
*inst
,
4327 const struct brw_wm_prog_data
*prog_data
)
4331 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4332 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4333 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4334 } else if (prog_data
->dual_src_blend
) {
4335 assert(inst
->exec_size
== 8);
4337 if (inst
->group
% 16 == 0)
4338 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4339 else if (inst
->group
% 16 == 8)
4340 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4342 unreachable("Invalid dual-source FB write instruction group");
4344 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4346 if (inst
->exec_size
== 16)
4347 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4348 else if (inst
->exec_size
== 8)
4349 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4351 unreachable("Invalid FB write execution size");
4358 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4359 const struct brw_wm_prog_data
*prog_data
,
4360 const brw_wm_prog_key
*key
,
4361 const fs_visitor::thread_payload
&payload
)
4363 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4364 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4365 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4366 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4367 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4368 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4369 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4370 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4371 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4372 const unsigned components
=
4373 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4375 assert(inst
->target
!= 0 || src0_alpha
.file
== BAD_FILE
);
4377 /* We can potentially have a message length of up to 15, so we have to set
4378 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4381 int header_size
= 2, payload_header_size
;
4382 unsigned length
= 0;
4384 if (devinfo
->gen
< 6) {
4385 /* TODO: Support SIMD32 on gen4-5 */
4386 assert(bld
.group() < 16);
4388 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4389 * an implied MOV from g0,g1 to the start of the message. The MOV from
4390 * g0 is handled by the hardware and the MOV from g1 is provided by the
4391 * generator. This is required because, on gen4-5, the generator may
4392 * generate two write messages with different message lengths in order
4393 * to handle AA data properly.
4395 * Also, since the pixel mask goes in the g0 portion of the message and
4396 * since render target writes are the last thing in the shader, we write
4397 * the pixel mask directly into g0 and it will get copied as part of the
4400 if (prog_data
->uses_kill
) {
4401 bld
.exec_all().group(1, 0)
4402 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4403 sample_mask_reg(bld
));
4406 assert(length
== 0);
4408 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4409 prog_data
->uses_kill
) ||
4410 (devinfo
->gen
< 11 &&
4411 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4412 /* From the Sandy Bridge PRM, volume 4, page 198:
4414 * "Dispatched Pixel Enables. One bit per pixel indicating
4415 * which pixels were originally enabled when the thread was
4416 * dispatched. This field is only required for the end-of-
4417 * thread message and on all dual-source messages."
4419 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4421 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4422 if (bld
.group() < 16) {
4423 /* The header starts off as g0 and g1 for the first half */
4424 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4425 BRW_REGISTER_TYPE_UD
));
4427 /* The header starts off as g0 and g2 for the second half */
4428 assert(bld
.group() < 32);
4429 const fs_reg header_sources
[2] = {
4430 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4431 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4433 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4436 uint32_t g00_bits
= 0;
4438 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4441 if (src0_alpha
.file
!= BAD_FILE
)
4442 g00_bits
|= 1 << 11;
4444 /* Set computes stencil to render target */
4445 if (prog_data
->computed_stencil
)
4446 g00_bits
|= 1 << 14;
4449 /* OR extra bits into g0.0 */
4450 ubld
.group(1, 0).OR(component(header
, 0),
4451 retype(brw_vec1_grf(0, 0),
4452 BRW_REGISTER_TYPE_UD
),
4453 brw_imm_ud(g00_bits
));
4456 /* Set the render target index for choosing BLEND_STATE. */
4457 if (inst
->target
> 0) {
4458 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4461 if (prog_data
->uses_kill
) {
4462 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4463 BRW_REGISTER_TYPE_UW
),
4464 sample_mask_reg(bld
));
4467 assert(length
== 0);
4468 sources
[0] = header
;
4469 sources
[1] = horiz_offset(header
, 8);
4472 assert(length
== 0 || length
== 2);
4473 header_size
= length
;
4475 if (payload
.aa_dest_stencil_reg
[0]) {
4476 assert(inst
->group
< 16);
4477 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4478 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4479 .MOV(sources
[length
],
4480 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4484 if (src0_alpha
.file
!= BAD_FILE
) {
4485 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4486 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4487 .annotate("FB write src0 alpha");
4488 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4489 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4490 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4495 if (sample_mask
.file
!= BAD_FILE
) {
4496 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4497 BRW_REGISTER_TYPE_UD
);
4499 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4500 * relevant. Since it's unsigned single words one vgrf is always
4501 * 16-wide, but only the lower or higher 8 channels will be used by the
4502 * hardware when doing a SIMD8 write depending on whether we have
4503 * selected the subspans for the first or second half respectively.
4505 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4506 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4507 sample_mask
.stride
*= 2;
4509 bld
.exec_all().annotate("FB write oMask")
4510 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4516 payload_header_size
= length
;
4518 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4521 if (color1
.file
!= BAD_FILE
) {
4522 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4526 if (src_depth
.file
!= BAD_FILE
) {
4527 sources
[length
] = src_depth
;
4531 if (dst_depth
.file
!= BAD_FILE
) {
4532 sources
[length
] = dst_depth
;
4536 if (src_stencil
.file
!= BAD_FILE
) {
4537 assert(devinfo
->gen
>= 9);
4538 assert(bld
.dispatch_width() == 8);
4540 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4541 * available on gen9+. As such it's impossible to have both enabled at the
4542 * same time and therefore length cannot overrun the array.
4544 assert(length
< 15);
4546 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4547 bld
.exec_all().annotate("FB write OS")
4548 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4549 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4554 if (devinfo
->gen
>= 7) {
4555 /* Send from the GRF */
4556 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4557 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4558 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4559 load
->dst
= payload
;
4561 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4562 uint32_t ex_desc
= 0;
4565 (inst
->group
/ 16) << 11 | /* rt slot group */
4566 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4567 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4568 inst
->last_rt
, false);
4570 if (devinfo
->gen
>= 11) {
4571 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4572 * in the extended message descriptor, in lieu of using a header.
4574 ex_desc
= inst
->target
<< 12 | (src0_alpha
.file
!= BAD_FILE
) << 15;
4576 if (key
->nr_color_regions
== 0)
4577 ex_desc
|= 1 << 20; /* Null Render Target */
4580 inst
->opcode
= SHADER_OPCODE_SEND
;
4581 inst
->resize_sources(3);
4582 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4583 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4584 inst
->src
[1] = brw_imm_ud(ex_desc
);
4585 inst
->src
[2] = payload
;
4586 inst
->mlen
= regs_written(load
);
4588 inst
->header_size
= header_size
;
4589 inst
->check_tdr
= true;
4590 inst
->send_has_side_effects
= true;
4592 /* Send from the MRF */
4593 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4594 sources
, length
, payload_header_size
);
4596 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4597 * will do this for us if we just give it a COMPR4 destination.
4599 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4600 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4602 if (devinfo
->gen
< 6) {
4603 /* Set up src[0] for the implied MOV from grf0-1 */
4604 inst
->resize_sources(1);
4605 inst
->src
[0] = brw_vec8_grf(0, 0);
4607 inst
->resize_sources(0);
4610 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4611 inst
->mlen
= regs_written(load
);
4612 inst
->header_size
= header_size
;
4617 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4619 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4620 const unsigned length
= 2;
4621 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4623 if (bld
.group() < 16) {
4624 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4625 BRW_REGISTER_TYPE_UD
));
4627 assert(bld
.group() < 32);
4628 const fs_reg header_sources
[] = {
4629 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4630 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4632 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4635 inst
->resize_sources(1);
4636 inst
->src
[0] = header
;
4637 inst
->opcode
= FS_OPCODE_FB_READ
;
4638 inst
->mlen
= length
;
4639 inst
->header_size
= length
;
4643 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4644 const fs_reg
&coordinate
,
4645 const fs_reg
&shadow_c
,
4646 const fs_reg
&lod
, const fs_reg
&lod2
,
4647 const fs_reg
&surface
,
4648 const fs_reg
&sampler
,
4649 unsigned coord_components
,
4650 unsigned grad_components
)
4652 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4653 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4654 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4655 fs_reg msg_end
= msg_begin
;
4658 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4660 for (unsigned i
= 0; i
< coord_components
; i
++)
4661 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4662 offset(coordinate
, bld
, i
));
4664 msg_end
= offset(msg_end
, bld
, coord_components
);
4666 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4667 * require all three components to be present and zero if they are unused.
4669 if (coord_components
> 0 &&
4670 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4671 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4672 for (unsigned i
= coord_components
; i
< 3; i
++)
4673 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4675 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4678 if (op
== SHADER_OPCODE_TXD
) {
4679 /* TXD unsupported in SIMD16 mode. */
4680 assert(bld
.dispatch_width() == 8);
4682 /* the slots for u and v are always present, but r is optional */
4683 if (coord_components
< 2)
4684 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4687 * dPdx = dudx, dvdx, drdx
4688 * dPdy = dudy, dvdy, drdy
4690 * 1-arg: Does not exist.
4692 * 2-arg: dudx dvdx dudy dvdy
4693 * dPdx.x dPdx.y dPdy.x dPdy.y
4696 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4697 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4698 * m5 m6 m7 m8 m9 m10
4700 for (unsigned i
= 0; i
< grad_components
; i
++)
4701 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4703 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4705 for (unsigned i
= 0; i
< grad_components
; i
++)
4706 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4708 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4712 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4713 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4715 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4716 bld
.dispatch_width() == 16);
4718 const brw_reg_type type
=
4719 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4720 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4721 bld
.MOV(retype(msg_end
, type
), lod
);
4722 msg_end
= offset(msg_end
, bld
, 1);
4725 if (shadow_c
.file
!= BAD_FILE
) {
4726 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4727 /* There's no plain shadow compare message, so we use shadow
4728 * compare with a bias of 0.0.
4730 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4731 msg_end
= offset(msg_end
, bld
, 1);
4734 bld
.MOV(msg_end
, shadow_c
);
4735 msg_end
= offset(msg_end
, bld
, 1);
4739 inst
->src
[0] = reg_undef
;
4740 inst
->src
[1] = surface
;
4741 inst
->src
[2] = sampler
;
4742 inst
->resize_sources(3);
4743 inst
->base_mrf
= msg_begin
.nr
;
4744 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4745 inst
->header_size
= 1;
4749 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4750 const fs_reg
&coordinate
,
4751 const fs_reg
&shadow_c
,
4752 const fs_reg
&lod
, const fs_reg
&lod2
,
4753 const fs_reg
&sample_index
,
4754 const fs_reg
&surface
,
4755 const fs_reg
&sampler
,
4756 unsigned coord_components
,
4757 unsigned grad_components
)
4759 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4760 fs_reg msg_coords
= message
;
4761 unsigned header_size
= 0;
4763 if (inst
->offset
!= 0) {
4764 /* The offsets set up by the visitor are in the m1 header, so we can't
4771 for (unsigned i
= 0; i
< coord_components
; i
++)
4772 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4773 offset(coordinate
, bld
, i
));
4775 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4776 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4778 if (shadow_c
.file
!= BAD_FILE
) {
4779 fs_reg msg_shadow
= msg_lod
;
4780 bld
.MOV(msg_shadow
, shadow_c
);
4781 msg_lod
= offset(msg_shadow
, bld
, 1);
4786 case SHADER_OPCODE_TXL
:
4788 bld
.MOV(msg_lod
, lod
);
4789 msg_end
= offset(msg_lod
, bld
, 1);
4791 case SHADER_OPCODE_TXD
:
4794 * dPdx = dudx, dvdx, drdx
4795 * dPdy = dudy, dvdy, drdy
4797 * Load up these values:
4798 * - dudx dudy dvdx dvdy drdx drdy
4799 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4802 for (unsigned i
= 0; i
< grad_components
; i
++) {
4803 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4804 msg_end
= offset(msg_end
, bld
, 1);
4806 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4807 msg_end
= offset(msg_end
, bld
, 1);
4810 case SHADER_OPCODE_TXS
:
4811 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4812 bld
.MOV(msg_lod
, lod
);
4813 msg_end
= offset(msg_lod
, bld
, 1);
4815 case SHADER_OPCODE_TXF
:
4816 msg_lod
= offset(msg_coords
, bld
, 3);
4817 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4818 msg_end
= offset(msg_lod
, bld
, 1);
4820 case SHADER_OPCODE_TXF_CMS
:
4821 msg_lod
= offset(msg_coords
, bld
, 3);
4823 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4825 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4826 msg_end
= offset(msg_lod
, bld
, 2);
4833 inst
->src
[0] = reg_undef
;
4834 inst
->src
[1] = surface
;
4835 inst
->src
[2] = sampler
;
4836 inst
->resize_sources(3);
4837 inst
->base_mrf
= message
.nr
;
4838 inst
->mlen
= msg_end
.nr
- message
.nr
;
4839 inst
->header_size
= header_size
;
4841 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4842 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4846 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4848 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4851 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4855 sampler_msg_type(const gen_device_info
*devinfo
,
4856 opcode opcode
, bool shadow_compare
)
4858 assert(devinfo
->gen
>= 5);
4860 case SHADER_OPCODE_TEX
:
4861 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4862 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4864 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4865 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4866 case SHADER_OPCODE_TXL
:
4867 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4868 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4869 case SHADER_OPCODE_TXL_LZ
:
4870 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4871 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4872 case SHADER_OPCODE_TXS
:
4873 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4874 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4875 case SHADER_OPCODE_TXD
:
4876 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4877 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4878 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4879 case SHADER_OPCODE_TXF
:
4880 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4881 case SHADER_OPCODE_TXF_LZ
:
4882 assert(devinfo
->gen
>= 9);
4883 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4884 case SHADER_OPCODE_TXF_CMS_W
:
4885 assert(devinfo
->gen
>= 9);
4886 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4887 case SHADER_OPCODE_TXF_CMS
:
4888 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4889 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4890 case SHADER_OPCODE_TXF_UMS
:
4891 assert(devinfo
->gen
>= 7);
4892 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4893 case SHADER_OPCODE_TXF_MCS
:
4894 assert(devinfo
->gen
>= 7);
4895 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4896 case SHADER_OPCODE_LOD
:
4897 return GEN5_SAMPLER_MESSAGE_LOD
;
4898 case SHADER_OPCODE_TG4
:
4899 assert(devinfo
->gen
>= 7);
4900 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4901 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4903 case SHADER_OPCODE_TG4_OFFSET
:
4904 assert(devinfo
->gen
>= 7);
4905 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4906 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4907 case SHADER_OPCODE_SAMPLEINFO
:
4908 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4910 unreachable("not reached");
4915 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4916 const fs_reg
&coordinate
,
4917 const fs_reg
&shadow_c
,
4918 fs_reg lod
, const fs_reg
&lod2
,
4919 const fs_reg
&min_lod
,
4920 const fs_reg
&sample_index
,
4922 const fs_reg
&surface
,
4923 const fs_reg
&sampler
,
4924 const fs_reg
&surface_handle
,
4925 const fs_reg
&sampler_handle
,
4926 const fs_reg
&tg4_offset
,
4927 unsigned coord_components
,
4928 unsigned grad_components
)
4930 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4931 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4932 unsigned reg_width
= bld
.dispatch_width() / 8;
4933 unsigned header_size
= 0, length
= 0;
4934 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4935 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4936 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4938 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4939 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4940 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4942 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4943 inst
->offset
!= 0 || inst
->eot
||
4944 op
== SHADER_OPCODE_SAMPLEINFO
||
4945 sampler_handle
.file
!= BAD_FILE
||
4946 is_high_sampler(devinfo
, sampler
)) {
4947 /* For general texture offsets (no txf workaround), we need a header to
4950 * TG4 needs to place its channel select in the header, for interaction
4951 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4952 * larger sampler numbers we need to offset the Sampler State Pointer in
4955 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4959 /* If we're requesting fewer than four channels worth of response,
4960 * and we have an explicit header, we need to set up the sampler
4961 * writemask. It's reversed from normal: 1 means "don't write".
4963 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4964 assert(regs_written(inst
) % reg_width
== 0);
4965 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4966 inst
->offset
|= mask
<< 12;
4969 /* Build the actual header */
4970 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4971 const fs_builder ubld1
= ubld
.group(1, 0);
4972 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4974 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4975 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4976 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4977 /* The vertex and fragment stages have g0.2 set to 0, so
4978 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4979 * must set it to 0 to avoid setting undesirable bits in the
4982 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4985 if (sampler_handle
.file
!= BAD_FILE
) {
4986 /* Bindless sampler handles aren't relative to the sampler state
4987 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
4988 * Instead, it's an absolute pointer relative to dynamic state base
4991 * Sampler states are 16 bytes each and the pointer we give here has
4992 * to be 32-byte aligned. In order to avoid more indirect messages
4993 * than required, we assume that all bindless sampler states are
4994 * 32-byte aligned. This sacrifices a bit of general state base
4995 * address space but means we can do something more efficient in the
4998 ubld1
.MOV(component(header
, 3), sampler_handle
);
4999 } else if (is_high_sampler(devinfo
, sampler
)) {
5000 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
5001 assert(sampler
.ud
>= 16);
5002 const int sampler_state_size
= 16; /* 16 bytes */
5004 ubld1
.ADD(component(header
, 3),
5005 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5006 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
5008 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
5009 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
5010 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
5011 ubld1
.ADD(component(header
, 3),
5012 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5018 if (shadow_c
.file
!= BAD_FILE
) {
5019 bld
.MOV(sources
[length
], shadow_c
);
5023 bool coordinate_done
= false;
5025 /* Set up the LOD info */
5028 case SHADER_OPCODE_TXL
:
5029 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
5030 op
= SHADER_OPCODE_TXL_LZ
;
5033 bld
.MOV(sources
[length
], lod
);
5036 case SHADER_OPCODE_TXD
:
5037 /* TXD should have been lowered in SIMD16 mode. */
5038 assert(bld
.dispatch_width() == 8);
5040 /* Load dPdx and the coordinate together:
5041 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5043 for (unsigned i
= 0; i
< coord_components
; i
++) {
5044 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5046 /* For cube map array, the coordinate is (u,v,r,ai) but there are
5047 * only derivatives for (u, v, r).
5049 if (i
< grad_components
) {
5050 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
5051 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
5055 coordinate_done
= true;
5057 case SHADER_OPCODE_TXS
:
5058 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
5061 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5062 /* We need an LOD; just use 0 */
5063 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
5066 case SHADER_OPCODE_TXF
:
5067 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5068 * On Gen9 they are u, v, lod, r
5070 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
5072 if (devinfo
->gen
>= 9) {
5073 if (coord_components
>= 2) {
5074 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
5075 offset(coordinate
, bld
, 1));
5077 sources
[length
] = brw_imm_d(0);
5082 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
5083 op
= SHADER_OPCODE_TXF_LZ
;
5085 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
5089 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
5090 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5091 offset(coordinate
, bld
, i
));
5093 coordinate_done
= true;
5096 case SHADER_OPCODE_TXF_CMS
:
5097 case SHADER_OPCODE_TXF_CMS_W
:
5098 case SHADER_OPCODE_TXF_UMS
:
5099 case SHADER_OPCODE_TXF_MCS
:
5100 if (op
== SHADER_OPCODE_TXF_UMS
||
5101 op
== SHADER_OPCODE_TXF_CMS
||
5102 op
== SHADER_OPCODE_TXF_CMS_W
) {
5103 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
5107 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
5108 /* Data from the multisample control surface. */
5109 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
5112 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
5115 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
5116 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
5119 offset(mcs
, bld
, 1));
5124 /* There is no offsetting for this message; just copy in the integer
5125 * texture coordinates.
5127 for (unsigned i
= 0; i
< coord_components
; i
++)
5128 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5129 offset(coordinate
, bld
, i
));
5131 coordinate_done
= true;
5133 case SHADER_OPCODE_TG4_OFFSET
:
5134 /* More crazy intermixing */
5135 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5136 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5138 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5139 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5140 offset(tg4_offset
, bld
, i
));
5142 if (coord_components
== 3) /* r if present */
5143 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5145 coordinate_done
= true;
5151 /* Set up the coordinate (except for cases where it was done above) */
5152 if (!coordinate_done
) {
5153 for (unsigned i
= 0; i
< coord_components
; i
++)
5154 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5157 if (min_lod
.file
!= BAD_FILE
) {
5158 /* Account for all of the missing coordinate sources */
5159 length
+= 4 - coord_components
;
5160 if (op
== SHADER_OPCODE_TXD
)
5161 length
+= (3 - grad_components
) * 2;
5163 bld
.MOV(sources
[length
++], min_lod
);
5168 mlen
= length
* reg_width
- header_size
;
5170 mlen
= length
* reg_width
;
5172 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5173 BRW_REGISTER_TYPE_F
);
5174 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5176 /* Generate the SEND. */
5177 inst
->opcode
= SHADER_OPCODE_SEND
;
5179 inst
->header_size
= header_size
;
5181 const unsigned msg_type
=
5182 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5183 const unsigned simd_mode
=
5184 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5185 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5187 uint32_t base_binding_table_index
;
5189 case SHADER_OPCODE_TG4
:
5190 case SHADER_OPCODE_TG4_OFFSET
:
5191 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5193 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5194 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5197 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5201 inst
->sfid
= BRW_SFID_SAMPLER
;
5202 if (surface
.file
== IMM
&&
5203 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5204 inst
->desc
= brw_sampler_desc(devinfo
,
5205 surface
.ud
+ base_binding_table_index
,
5206 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5209 0 /* return_format unused on gen7+ */);
5210 inst
->src
[0] = brw_imm_ud(0);
5211 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5212 } else if (surface_handle
.file
!= BAD_FILE
) {
5213 /* Bindless surface */
5214 assert(devinfo
->gen
>= 9);
5215 inst
->desc
= brw_sampler_desc(devinfo
,
5217 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5220 0 /* return_format unused on gen7+ */);
5222 /* For bindless samplers, the entire address is included in the message
5223 * header so we can leave the portion in the message descriptor 0.
5225 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5226 inst
->src
[0] = brw_imm_ud(0);
5228 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5229 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5230 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5231 inst
->src
[0] = desc
;
5234 /* We assume that the driver provided the handle in the top 20 bits so
5235 * we can use the surface handle directly as the extended descriptor.
5237 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5239 /* Immediate portion of the descriptor */
5240 inst
->desc
= brw_sampler_desc(devinfo
,
5245 0 /* return_format unused on gen7+ */);
5246 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5247 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5248 if (surface
.equals(sampler
)) {
5249 /* This case is common in GL */
5250 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5252 if (sampler_handle
.file
!= BAD_FILE
) {
5253 ubld
.MOV(desc
, surface
);
5254 } else if (sampler
.file
== IMM
) {
5255 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5257 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5258 ubld
.OR(desc
, desc
, surface
);
5261 if (base_binding_table_index
)
5262 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5263 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5265 inst
->src
[0] = component(desc
, 0);
5266 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5269 inst
->src
[2] = src_payload
;
5270 inst
->resize_sources(3);
5273 /* EOT sampler messages don't make sense to split because it would
5274 * involve ending half of the thread early.
5276 assert(inst
->group
== 0);
5277 /* We need to use SENDC for EOT sampler messages */
5278 inst
->check_tdr
= true;
5279 inst
->send_has_side_effects
= true;
5282 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5283 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5287 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5289 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5290 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5291 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5292 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5293 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5294 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5295 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5296 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5297 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5298 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5299 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5300 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5301 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5302 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5303 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5304 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5305 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5307 if (devinfo
->gen
>= 7) {
5308 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5309 shadow_c
, lod
, lod2
, min_lod
,
5311 mcs
, surface
, sampler
,
5312 surface_handle
, sampler_handle
,
5314 coord_components
, grad_components
);
5315 } else if (devinfo
->gen
>= 5) {
5316 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5317 shadow_c
, lod
, lod2
, sample_index
,
5319 coord_components
, grad_components
);
5321 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5322 shadow_c
, lod
, lod2
,
5324 coord_components
, grad_components
);
5329 * Predicate the specified instruction on the sample mask.
5332 emit_predicate_on_sample_mask(const fs_builder
&bld
, fs_inst
*inst
)
5334 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
&&
5335 bld
.group() == inst
->group
&&
5336 bld
.dispatch_width() == inst
->exec_size
);
5338 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
5339 const fs_reg sample_mask
= sample_mask_reg(bld
);
5340 const unsigned subreg
= sample_mask_flag_subreg(v
);
5342 if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
5343 assert(sample_mask
.file
== ARF
&&
5344 sample_mask
.nr
== brw_flag_subreg(subreg
).nr
&&
5345 sample_mask
.subnr
== brw_flag_subreg(
5346 subreg
+ inst
->group
/ 16).subnr
);
5348 bld
.group(1, 0).exec_all()
5349 .MOV(brw_flag_subreg(subreg
+ inst
->group
/ 16), sample_mask
);
5352 if (inst
->predicate
) {
5353 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5354 assert(!inst
->predicate_inverse
);
5355 assert(inst
->flag_subreg
== 0);
5356 /* Combine the sample mask with the existing predicate by using a
5357 * vertical predication mode.
5359 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5361 inst
->flag_subreg
= subreg
;
5362 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5363 inst
->predicate_inverse
= false;
5368 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5370 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5372 /* Get the logical send arguments. */
5373 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5374 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5375 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5376 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5377 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5378 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5379 assert(arg
.file
== IMM
);
5381 /* We must have exactly one of surface and surface_handle */
5382 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5384 /* Calculate the total number of components of the payload. */
5385 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5386 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5388 const bool is_typed_access
=
5389 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5390 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5391 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5393 const bool is_surface_access
= is_typed_access
||
5394 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
||
5395 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
||
5396 inst
->opcode
== SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
;
5398 const bool is_stateless
=
5399 surface
.file
== IMM
&& (surface
.ud
== BRW_BTI_STATELESS
||
5400 surface
.ud
== GEN8_BTI_STATELESS_NON_COHERENT
);
5402 const bool has_side_effects
= inst
->has_side_effects();
5403 fs_reg sample_mask
= has_side_effects
? sample_mask_reg(bld
) :
5404 fs_reg(brw_imm_d(0xffff));
5406 /* From the BDW PRM Volume 7, page 147:
5408 * "For the Data Cache Data Port*, the header must be present for the
5409 * following message types: [...] Typed read/write/atomics"
5411 * Earlier generations have a similar wording. Because of this restriction
5412 * we don't attempt to implement sample masks via predication for such
5413 * messages prior to Gen9, since we have to provide a header anyway. On
5414 * Gen11+ the header has been removed so we can only use predication.
5416 * For all stateless A32 messages, we also need a header
5419 if ((devinfo
->gen
< 9 && is_typed_access
) || is_stateless
) {
5420 fs_builder ubld
= bld
.exec_all().group(8, 0);
5421 header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5422 ubld
.MOV(header
, brw_imm_d(0));
5424 /* Both the typed and scattered byte/dword A32 messages take a buffer
5425 * base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
5426 * MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
5427 * for more details.) This is conveniently where the HW places the
5428 * scratch surface base address.
5430 * From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
5432 * "When a thread becomes 'active' it is allocated a portion of
5433 * scratch space, sized according to PerThreadScratchSpace. The
5434 * starting location of each thread’s scratch space allocation,
5435 * ScratchSpaceOffset, is passed in the thread payload in
5436 * R0.5[31:10] and is specified as a 1KB-granular offset from the
5437 * GeneralStateBaseAddress. The computation of ScratchSpaceOffset
5438 * includes the starting address of the stage’s scratch space
5439 * allocation, as programmed by ScratchSpaceBasePointer."
5441 * The base address is passed in bits R0.5[31:10] and the bottom 10
5442 * bits of R0.5 are used for other things. Therefore, we have to
5443 * mask off the bottom 10 bits so that we don't get a garbage base
5446 ubld
.group(1, 0).AND(component(header
, 5),
5447 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
5448 brw_imm_ud(0xfffffc00));
5450 if (is_surface_access
)
5451 ubld
.group(1, 0).MOV(component(header
, 7), sample_mask
);
5453 const unsigned header_sz
= header
.file
!= BAD_FILE
? 1 : 0;
5455 fs_reg payload
, payload2
;
5456 unsigned mlen
, ex_mlen
= 0;
5457 if (devinfo
->gen
>= 9 &&
5458 (src
.file
== BAD_FILE
|| header
.file
== BAD_FILE
)) {
5459 /* We have split sends on gen9 and above */
5460 if (header
.file
== BAD_FILE
) {
5461 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5462 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5463 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5464 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5466 assert(src
.file
== BAD_FILE
);
5468 payload2
= bld
.move_to_vgrf(addr
, addr_sz
);
5470 ex_mlen
= addr_sz
* (inst
->exec_size
/ 8);
5473 /* Allocate space for the payload. */
5474 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5475 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5476 fs_reg
*const components
= new fs_reg
[sz
];
5479 /* Construct the payload. */
5480 if (header
.file
!= BAD_FILE
)
5481 components
[n
++] = header
;
5483 for (unsigned i
= 0; i
< addr_sz
; i
++)
5484 components
[n
++] = offset(addr
, bld
, i
);
5486 for (unsigned i
= 0; i
< src_sz
; i
++)
5487 components
[n
++] = offset(src
, bld
, i
);
5489 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5490 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5492 delete[] components
;
5495 /* Predicate the instruction on the sample mask if no header is
5498 if ((header
.file
== BAD_FILE
|| !is_surface_access
) &&
5499 sample_mask
.file
!= BAD_FILE
&& sample_mask
.file
!= IMM
)
5500 emit_predicate_on_sample_mask(bld
, inst
);
5503 switch (inst
->opcode
) {
5504 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5505 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5506 /* Byte scattered opcodes go through the normal data cache */
5507 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5510 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5511 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5512 sfid
= devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
5513 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
5514 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
5517 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5518 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5519 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5520 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5521 /* Untyped Surface messages go through the data cache but the SFID value
5522 * changed on Haswell.
5524 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5525 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5526 GEN7_SFID_DATAPORT_DATA_CACHE
);
5529 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5530 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5531 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5532 /* Typed surface messages go through the render cache on IVB and the
5533 * data cache on HSW+.
5535 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5536 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5537 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5541 unreachable("Unsupported surface opcode");
5545 switch (inst
->opcode
) {
5546 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5547 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5548 arg
.ud
, /* num_channels */
5552 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5553 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5554 arg
.ud
, /* num_channels */
5558 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5559 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5560 arg
.ud
, /* bit_size */
5564 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5565 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5566 arg
.ud
, /* bit_size */
5570 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5571 assert(arg
.ud
== 32); /* bit_size */
5572 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5576 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5577 assert(arg
.ud
== 32); /* bit_size */
5578 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5582 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5583 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5584 arg
.ud
, /* atomic_op */
5585 !inst
->dst
.is_null());
5588 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5589 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5590 arg
.ud
, /* atomic_op */
5591 !inst
->dst
.is_null());
5594 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5595 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5596 arg
.ud
, /* num_channels */
5600 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5601 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5602 arg
.ud
, /* num_channels */
5606 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5607 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5608 arg
.ud
, /* atomic_op */
5609 !inst
->dst
.is_null());
5613 unreachable("Unknown surface logical instruction");
5616 /* Update the original instruction. */
5617 inst
->opcode
= SHADER_OPCODE_SEND
;
5619 inst
->ex_mlen
= ex_mlen
;
5620 inst
->header_size
= header_sz
;
5621 inst
->send_has_side_effects
= has_side_effects
;
5622 inst
->send_is_volatile
= !has_side_effects
;
5624 /* Set up SFID and descriptors */
5627 if (surface
.file
== IMM
) {
5628 inst
->desc
|= surface
.ud
& 0xff;
5629 inst
->src
[0] = brw_imm_ud(0);
5630 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5631 } else if (surface_handle
.file
!= BAD_FILE
) {
5632 /* Bindless surface */
5633 assert(devinfo
->gen
>= 9);
5634 inst
->desc
|= GEN9_BTI_BINDLESS
;
5635 inst
->src
[0] = brw_imm_ud(0);
5637 /* We assume that the driver provided the handle in the top 20 bits so
5638 * we can use the surface handle directly as the extended descriptor.
5640 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5642 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5643 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5644 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5645 inst
->src
[0] = component(tmp
, 0);
5646 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5649 /* Finally, the payload */
5650 inst
->src
[2] = payload
;
5651 inst
->src
[3] = payload2
;
5653 inst
->resize_sources(4);
5657 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5659 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5661 const fs_reg
&addr
= inst
->src
[0];
5662 const fs_reg
&src
= inst
->src
[1];
5663 const unsigned src_comps
= inst
->components_read(1);
5664 assert(inst
->src
[2].file
== IMM
);
5665 const unsigned arg
= inst
->src
[2].ud
;
5666 const bool has_side_effects
= inst
->has_side_effects();
5668 /* If the surface message has side effects and we're a fragment shader, we
5669 * have to predicate with the sample mask to avoid helper invocations.
5671 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
)
5672 emit_predicate_on_sample_mask(bld
, inst
);
5674 fs_reg payload
, payload2
;
5675 unsigned mlen
, ex_mlen
= 0;
5676 if (devinfo
->gen
>= 9) {
5677 /* On Skylake and above, we have SENDS */
5678 mlen
= 2 * (inst
->exec_size
/ 8);
5679 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5680 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5681 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5682 BRW_REGISTER_TYPE_UD
);
5684 /* Add two because the address is 64-bit */
5685 const unsigned dwords
= 2 + src_comps
;
5686 mlen
= dwords
* (inst
->exec_size
/ 8);
5692 for (unsigned i
= 0; i
< src_comps
; i
++)
5693 sources
[1 + i
] = offset(src
, bld
, i
);
5695 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5696 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5700 switch (inst
->opcode
) {
5701 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5702 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5703 arg
, /* num_channels */
5707 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5708 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5709 arg
, /* num_channels */
5713 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5714 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5719 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5720 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5725 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5726 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5727 arg
, /* atomic_op */
5728 !inst
->dst
.is_null());
5731 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5732 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5733 arg
, /* atomic_op */
5734 !inst
->dst
.is_null());
5738 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5739 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5740 arg
, /* atomic_op */
5741 !inst
->dst
.is_null());
5745 unreachable("Unknown A64 logical instruction");
5748 /* Update the original instruction. */
5749 inst
->opcode
= SHADER_OPCODE_SEND
;
5751 inst
->ex_mlen
= ex_mlen
;
5752 inst
->header_size
= 0;
5753 inst
->send_has_side_effects
= has_side_effects
;
5754 inst
->send_is_volatile
= !has_side_effects
;
5756 /* Set up SFID and descriptors */
5757 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5759 inst
->resize_sources(4);
5760 inst
->src
[0] = brw_imm_ud(0); /* desc */
5761 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5762 inst
->src
[2] = payload
;
5763 inst
->src
[3] = payload2
;
5767 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5769 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5771 if (devinfo
->gen
>= 7) {
5772 fs_reg index
= inst
->src
[0];
5773 /* We are switching the instruction from an ALU-like instruction to a
5774 * send-from-grf instruction. Since sends can't handle strides or
5775 * source modifiers, we have to make a copy of the offset source.
5777 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5778 bld
.MOV(offset
, inst
->src
[1]);
5780 const unsigned simd_mode
=
5781 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5782 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5784 inst
->opcode
= SHADER_OPCODE_SEND
;
5785 inst
->mlen
= inst
->exec_size
/ 8;
5786 inst
->resize_sources(3);
5788 inst
->sfid
= BRW_SFID_SAMPLER
;
5789 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5790 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5792 if (index
.file
== IMM
) {
5793 inst
->desc
|= index
.ud
& 0xff;
5794 inst
->src
[0] = brw_imm_ud(0);
5796 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5797 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5798 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5799 inst
->src
[0] = component(tmp
, 0);
5801 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5802 inst
->src
[2] = offset
; /* payload */
5804 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5805 BRW_REGISTER_TYPE_UD
);
5807 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5809 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5810 inst
->resize_sources(1);
5811 inst
->base_mrf
= payload
.nr
;
5812 inst
->header_size
= 1;
5813 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5818 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5820 assert(bld
.shader
->devinfo
->gen
< 6);
5823 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5825 if (inst
->sources
> 1) {
5826 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5827 * "Message Payload":
5829 * "Operand0[7]. For the INT DIV functions, this operand is the
5832 * "Operand1[7]. For the INT DIV functions, this operand is the
5835 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5836 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5837 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5839 inst
->resize_sources(1);
5840 inst
->src
[0] = src0
;
5842 assert(inst
->exec_size
== 8);
5843 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5848 fs_visitor::lower_logical_sends()
5850 bool progress
= false;
5852 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5853 const fs_builder
ibld(this, block
, inst
);
5855 switch (inst
->opcode
) {
5856 case FS_OPCODE_FB_WRITE_LOGICAL
:
5857 assert(stage
== MESA_SHADER_FRAGMENT
);
5858 lower_fb_write_logical_send(ibld
, inst
,
5859 brw_wm_prog_data(prog_data
),
5860 (const brw_wm_prog_key
*)key
,
5864 case FS_OPCODE_FB_READ_LOGICAL
:
5865 lower_fb_read_logical_send(ibld
, inst
);
5868 case SHADER_OPCODE_TEX_LOGICAL
:
5869 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5872 case SHADER_OPCODE_TXD_LOGICAL
:
5873 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5876 case SHADER_OPCODE_TXF_LOGICAL
:
5877 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5880 case SHADER_OPCODE_TXL_LOGICAL
:
5881 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5884 case SHADER_OPCODE_TXS_LOGICAL
:
5885 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5888 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5889 lower_sampler_logical_send(ibld
, inst
,
5890 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5893 case FS_OPCODE_TXB_LOGICAL
:
5894 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5897 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5898 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5901 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5902 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5905 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5906 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5909 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5910 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5913 case SHADER_OPCODE_LOD_LOGICAL
:
5914 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5917 case SHADER_OPCODE_TG4_LOGICAL
:
5918 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5921 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5922 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5925 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5926 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5929 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5930 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5931 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5932 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5933 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5934 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5935 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5936 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5937 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5938 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5939 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5940 lower_surface_logical_send(ibld
, inst
);
5943 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5944 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5945 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5946 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5947 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5948 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5949 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5950 lower_a64_logical_send(ibld
, inst
);
5953 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5954 lower_varying_pull_constant_logical_send(ibld
, inst
);
5957 case SHADER_OPCODE_RCP
:
5958 case SHADER_OPCODE_RSQ
:
5959 case SHADER_OPCODE_SQRT
:
5960 case SHADER_OPCODE_EXP2
:
5961 case SHADER_OPCODE_LOG2
:
5962 case SHADER_OPCODE_SIN
:
5963 case SHADER_OPCODE_COS
:
5964 case SHADER_OPCODE_POW
:
5965 case SHADER_OPCODE_INT_QUOTIENT
:
5966 case SHADER_OPCODE_INT_REMAINDER
:
5967 /* The math opcodes are overloaded for the send-like and
5968 * expression-like instructions which seems kind of icky. Gen6+ has
5969 * a native (but rather quirky) MATH instruction so we don't need to
5970 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5971 * logical instructions (which we can easily recognize because they
5972 * have mlen = 0) into send-like virtual instructions.
5974 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5975 lower_math_logical_send(ibld
, inst
);
5990 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
5996 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
5998 /* This opcode sometimes uses :W type on the source even if the operand is
5999 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
6001 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
6004 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
6007 for (int i
= 0; i
< inst
->sources
; i
++) {
6008 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
6016 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
6018 /* This opcode sometimes uses :W type on the destination even if the
6019 * destination is a :HF, because in gen7 there is no support for :HF, and
6022 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
6023 inst
->dst
.stride
== 1)
6026 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
6027 inst
->dst
.stride
!= 1)
6030 for (int i
= 0; i
< inst
->sources
; i
++) {
6031 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
6039 * Get the closest allowed SIMD width for instruction \p inst accounting for
6040 * some common regioning and execution control restrictions that apply to FPU
6041 * instructions. These restrictions don't necessarily have any relevance to
6042 * instructions not executed by the FPU pipeline like extended math, control
6043 * flow or send message instructions.
6045 * For virtual opcodes it's really up to the instruction -- In some cases
6046 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
6047 * instructions) it may simplify virtual instruction lowering if we can
6048 * enforce FPU-like regioning restrictions already on the virtual instruction,
6049 * in other cases (e.g. virtual send-like instructions) this may be
6050 * excessively restrictive.
6053 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
6054 const fs_inst
*inst
)
6056 /* Maximum execution size representable in the instruction controls. */
6057 unsigned max_width
= MIN2(32, inst
->exec_size
);
6059 /* According to the PRMs:
6060 * "A. In Direct Addressing mode, a source cannot span more than 2
6061 * adjacent GRF registers.
6062 * B. A destination cannot span more than 2 adjacent GRF registers."
6064 * Look for the source or destination with the largest register region
6065 * which is the one that is going to limit the overall execution size of
6066 * the instruction due to this rule.
6068 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6070 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6071 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
6073 /* Calculate the maximum execution size of the instruction based on the
6074 * factor by which it goes over the hardware limit of 2 GRFs.
6077 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
6079 /* According to the IVB PRMs:
6080 * "When destination spans two registers, the source MUST span two
6081 * registers. The exception to the above rule:
6083 * - When source is scalar, the source registers are not incremented.
6084 * - When source is packed integer Word and destination is packed
6085 * integer DWord, the source register is not incremented but the
6086 * source sub register is incremented."
6088 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
6089 * restrictions. The code below intentionally doesn't check whether the
6090 * destination type is integer because empirically the hardware doesn't
6091 * seem to care what the actual type is as long as it's dword-aligned.
6093 if (devinfo
->gen
< 8) {
6094 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6095 /* IVB implements DF scalars as <0;2,1> regions. */
6096 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
6097 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
6098 const bool is_packed_word_exception
=
6099 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
6100 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
6102 /* We check size_read(i) against size_written instead of REG_SIZE
6103 * because we want to properly handle SIMD32. In SIMD32, you can end
6104 * up with writes to 4 registers and a source that reads 2 registers
6105 * and we may still need to lower all the way to SIMD8 in that case.
6107 if (inst
->size_written
> REG_SIZE
&&
6108 inst
->size_read(i
) != 0 &&
6109 inst
->size_read(i
) < inst
->size_written
&&
6110 !is_scalar_exception
&& !is_packed_word_exception
) {
6111 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6112 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6117 if (devinfo
->gen
< 6) {
6118 /* From the G45 PRM, Volume 4 Page 361:
6120 * "Operand Alignment Rule: With the exceptions listed below, a
6121 * source/destination operand in general should be aligned to even
6122 * 256-bit physical register with a region size equal to two 256-bit
6123 * physical registers."
6125 * Normally we enforce this by allocating virtual registers to the
6126 * even-aligned class. But we need to handle payload registers.
6128 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6129 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
6130 inst
->size_read(i
) > REG_SIZE
) {
6131 max_width
= MIN2(max_width
, 8);
6136 /* From the IVB PRMs:
6137 * "When an instruction is SIMD32, the low 16 bits of the execution mask
6138 * are applied for both halves of the SIMD32 instruction. If different
6139 * execution mask channels are required, split the instruction into two
6140 * SIMD16 instructions."
6142 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6143 * 32-wide control flow support in hardware and will behave similarly.
6145 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6146 max_width
= MIN2(max_width
, 16);
6148 /* From the IVB PRMs (applies to HSW too):
6149 * "Instructions with condition modifiers must not use SIMD32."
6151 * From the BDW PRMs (applies to later hardware too):
6152 * "Ternary instruction with condition modifiers must not use SIMD32."
6154 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6155 max_width
= MIN2(max_width
, 16);
6157 /* From the IVB PRMs (applies to other devices that don't have the
6158 * gen_device_info::supports_simd16_3src flag set):
6159 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6160 * SIMD8 is not allowed for DF operations."
6162 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6163 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6165 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6166 * the 8-bit quarter of the execution mask signals specified in the
6167 * instruction control fields) for the second compressed half of any
6168 * single-precision instruction (for double-precision instructions
6169 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6170 * the EU will apply the wrong execution controls for the second
6171 * sequential GRF write if the number of channels per GRF is not exactly
6172 * eight in single-precision mode (or four in double-float mode).
6174 * In this situation we calculate the maximum size of the split
6175 * instructions so they only ever write to a single register.
6177 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6178 !inst
->force_writemask_all
) {
6179 const unsigned channels_per_grf
= inst
->exec_size
/
6180 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6181 const unsigned exec_type_size
= get_exec_type_size(inst
);
6182 assert(exec_type_size
);
6184 /* The hardware shifts exactly 8 channels per compressed half of the
6185 * instruction in single-precision mode and exactly 4 in double-precision.
6187 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6188 max_width
= MIN2(max_width
, channels_per_grf
);
6190 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6191 * because HW applies the same channel enable signals to both halves of
6192 * the compressed instruction which will be just wrong under
6193 * non-uniform control flow.
6195 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6196 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6197 max_width
= MIN2(max_width
, 4);
6200 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6203 * "No SIMD16 in mixed mode when destination is f32. Instruction
6204 * execution size must be no more than 8."
6206 * FIXME: the simulator doesn't seem to complain if we don't do this and
6207 * empirical testing with existing CTS tests show that they pass just fine
6208 * without implementing this, however, since our interpretation of the PRM
6209 * is that conversion MOVs between HF and F are still mixed-float
6210 * instructions (and therefore subject to this restriction) we decided to
6211 * split them to be safe. Might be useful to do additional investigation to
6212 * lift the restriction if we can ensure that it is safe though, since these
6213 * conversions are common when half-float types are involved since many
6214 * instructions do not support HF types and conversions from/to F are
6217 if (is_mixed_float_with_fp32_dst(inst
))
6218 max_width
= MIN2(max_width
, 8);
6220 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6223 * "No SIMD16 in mixed mode when destination is packed f16 for both
6224 * Align1 and Align16."
6226 if (is_mixed_float_with_packed_fp16_dst(inst
))
6227 max_width
= MIN2(max_width
, 8);
6229 /* Only power-of-two execution sizes are representable in the instruction
6232 return 1 << _mesa_logbase2(max_width
);
6236 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6237 * various payload size restrictions that apply to sampler message
6240 * This is only intended to provide a maximum theoretical bound for the
6241 * execution size of the message based on the number of argument components
6242 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6243 * variant of the message can be used, though some messages may have
6244 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6245 * the message length to determine the exact SIMD width and argument count,
6246 * which makes a number of sampler message combinations impossible to
6250 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6251 const fs_inst
*inst
)
6253 /* If we have a min_lod parameter on anything other than a simple sample
6254 * message, it will push it over 5 arguments and we have to fall back to
6257 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6258 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6261 /* Calculate the number of coordinate components that have to be present
6262 * assuming that additional arguments follow the texel coordinates in the
6263 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6264 * need to pad to four or three components depending on the message,
6265 * pre-ILK we need to pad to at most three components.
6267 const unsigned req_coord_components
=
6268 (devinfo
->gen
>= 7 ||
6269 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6270 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6271 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6274 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6275 * variant of the TXL or TXF message.
6277 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6278 (inst
->opcode
== SHADER_OPCODE_TXL
||
6279 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6280 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6282 /* Calculate the total number of argument components that need to be passed
6283 * to the sampler unit.
6285 const unsigned num_payload_components
=
6286 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6287 req_coord_components
) +
6288 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6289 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6290 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6291 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6292 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6293 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6294 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6296 /* SIMD16 messages with more than five arguments exceed the maximum message
6297 * size supported by the sampler, regardless of whether a header is
6300 return MIN2(inst
->exec_size
,
6301 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6305 * Get the closest native SIMD width supported by the hardware for instruction
6306 * \p inst. The instruction will be left untouched by
6307 * fs_visitor::lower_simd_width() if the returned value is equal to the
6308 * original execution size.
6311 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6312 const fs_inst
*inst
)
6314 switch (inst
->opcode
) {
6315 case BRW_OPCODE_MOV
:
6316 case BRW_OPCODE_SEL
:
6317 case BRW_OPCODE_NOT
:
6318 case BRW_OPCODE_AND
:
6320 case BRW_OPCODE_XOR
:
6321 case BRW_OPCODE_SHR
:
6322 case BRW_OPCODE_SHL
:
6323 case BRW_OPCODE_ASR
:
6324 case BRW_OPCODE_ROR
:
6325 case BRW_OPCODE_ROL
:
6326 case BRW_OPCODE_CMPN
:
6327 case BRW_OPCODE_CSEL
:
6328 case BRW_OPCODE_F32TO16
:
6329 case BRW_OPCODE_F16TO32
:
6330 case BRW_OPCODE_BFREV
:
6331 case BRW_OPCODE_BFE
:
6332 case BRW_OPCODE_ADD
:
6333 case BRW_OPCODE_MUL
:
6334 case BRW_OPCODE_AVG
:
6335 case BRW_OPCODE_FRC
:
6336 case BRW_OPCODE_RNDU
:
6337 case BRW_OPCODE_RNDD
:
6338 case BRW_OPCODE_RNDE
:
6339 case BRW_OPCODE_RNDZ
:
6340 case BRW_OPCODE_LZD
:
6341 case BRW_OPCODE_FBH
:
6342 case BRW_OPCODE_FBL
:
6343 case BRW_OPCODE_CBIT
:
6344 case BRW_OPCODE_SAD2
:
6345 case BRW_OPCODE_MAD
:
6346 case BRW_OPCODE_LRP
:
6347 case FS_OPCODE_PACK
:
6348 case SHADER_OPCODE_SEL_EXEC
:
6349 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6350 return get_fpu_lowered_simd_width(devinfo
, inst
);
6352 case BRW_OPCODE_CMP
: {
6353 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6354 * when the destination is a GRF the dependency-clear bit on the flag
6355 * register is cleared early.
6357 * Suggested workarounds are to disable coissuing CMP instructions
6358 * or to split CMP(16) instructions into two CMP(8) instructions.
6360 * We choose to split into CMP(8) instructions since disabling
6361 * coissuing would affect CMP instructions not otherwise affected by
6364 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6365 !inst
->dst
.is_null() ? 8 : ~0);
6366 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6368 case BRW_OPCODE_BFI1
:
6369 case BRW_OPCODE_BFI2
:
6370 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6372 * "Force BFI instructions to be executed always in SIMD8."
6374 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6375 get_fpu_lowered_simd_width(devinfo
, inst
));
6378 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6379 return inst
->exec_size
;
6381 case SHADER_OPCODE_RCP
:
6382 case SHADER_OPCODE_RSQ
:
6383 case SHADER_OPCODE_SQRT
:
6384 case SHADER_OPCODE_EXP2
:
6385 case SHADER_OPCODE_LOG2
:
6386 case SHADER_OPCODE_SIN
:
6387 case SHADER_OPCODE_COS
: {
6388 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6389 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6391 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6392 return MIN2(8, inst
->exec_size
);
6393 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6394 return MIN2(8, inst
->exec_size
);
6395 return MIN2(16, inst
->exec_size
);
6398 case SHADER_OPCODE_POW
: {
6399 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6400 * to SIMD8 with half-float
6402 if (devinfo
->gen
< 7)
6403 return MIN2(8, inst
->exec_size
);
6404 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6405 return MIN2(8, inst
->exec_size
);
6406 return MIN2(16, inst
->exec_size
);
6409 case SHADER_OPCODE_USUB_SAT
:
6410 case SHADER_OPCODE_ISUB_SAT
:
6411 return get_fpu_lowered_simd_width(devinfo
, inst
);
6413 case SHADER_OPCODE_INT_QUOTIENT
:
6414 case SHADER_OPCODE_INT_REMAINDER
:
6415 /* Integer division is limited to SIMD8 on all generations. */
6416 return MIN2(8, inst
->exec_size
);
6418 case FS_OPCODE_LINTERP
:
6419 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6420 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6421 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6422 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6423 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6424 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6425 return MIN2(16, inst
->exec_size
);
6427 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6428 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6429 * message used to implement varying pull constant loads, so expand it
6430 * to SIMD16. An alternative with longer message payload length but
6431 * shorter return payload would be to use the SIMD8 sampler message that
6432 * takes (header, u, v, r) as parameters instead of (header, u).
6434 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6436 case FS_OPCODE_DDX_COARSE
:
6437 case FS_OPCODE_DDX_FINE
:
6438 case FS_OPCODE_DDY_COARSE
:
6439 case FS_OPCODE_DDY_FINE
:
6440 /* The implementation of this virtual opcode may require emitting
6441 * compressed Align16 instructions, which are severely limited on some
6444 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6445 * Region Restrictions):
6447 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6448 * and SIMD8 is not allowed for DF operations."
6450 * In this context, "DW operations" means "operations acting on 32-bit
6451 * values", so it includes operations on floats.
6453 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6454 * (Instruction Compression -> Rules and Restrictions):
6456 * "A compressed instruction must be in Align1 access mode. Align16
6457 * mode instructions cannot be compressed."
6459 * Similar text exists in the g45 PRM.
6461 * Empirically, compressed align16 instructions using odd register
6462 * numbers don't appear to work on Sandybridge either.
6464 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6465 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6466 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6468 case SHADER_OPCODE_MULH
:
6469 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6470 * is 8-wide on Gen7+.
6472 return (devinfo
->gen
>= 7 ? 8 :
6473 get_fpu_lowered_simd_width(devinfo
, inst
));
6475 case FS_OPCODE_FB_WRITE_LOGICAL
:
6476 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6479 assert(devinfo
->gen
!= 6 ||
6480 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6481 inst
->exec_size
== 8);
6482 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6483 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6484 8 : MIN2(16, inst
->exec_size
));
6486 case FS_OPCODE_FB_READ_LOGICAL
:
6487 return MIN2(16, inst
->exec_size
);
6489 case SHADER_OPCODE_TEX_LOGICAL
:
6490 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6491 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6492 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6493 case SHADER_OPCODE_LOD_LOGICAL
:
6494 case SHADER_OPCODE_TG4_LOGICAL
:
6495 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6496 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6497 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6498 return get_sampler_lowered_simd_width(devinfo
, inst
);
6500 case SHADER_OPCODE_TXD_LOGICAL
:
6501 /* TXD is unsupported in SIMD16 mode. */
6504 case SHADER_OPCODE_TXL_LOGICAL
:
6505 case FS_OPCODE_TXB_LOGICAL
:
6506 /* Only one execution size is representable pre-ILK depending on whether
6507 * the shadow reference argument is present.
6509 if (devinfo
->gen
== 4)
6510 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6512 return get_sampler_lowered_simd_width(devinfo
, inst
);
6514 case SHADER_OPCODE_TXF_LOGICAL
:
6515 case SHADER_OPCODE_TXS_LOGICAL
:
6516 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6517 * messages. Use SIMD16 instead.
6519 if (devinfo
->gen
== 4)
6522 return get_sampler_lowered_simd_width(devinfo
, inst
);
6524 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6525 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6526 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6529 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6530 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6531 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6532 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6533 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6534 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6535 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6536 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6537 return MIN2(16, inst
->exec_size
);
6539 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6540 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6541 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6542 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6543 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6545 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6546 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6547 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6550 case SHADER_OPCODE_URB_READ_SIMD8
:
6551 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6552 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6553 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6554 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6555 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6556 return MIN2(8, inst
->exec_size
);
6558 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6559 const unsigned swiz
= inst
->src
[1].ud
;
6560 return (is_uniform(inst
->src
[0]) ?
6561 get_fpu_lowered_simd_width(devinfo
, inst
) :
6562 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6563 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6564 get_fpu_lowered_simd_width(devinfo
, inst
));
6566 case SHADER_OPCODE_MOV_INDIRECT
: {
6567 /* From IVB and HSW PRMs:
6569 * "2.When the destination requires two registers and the sources are
6570 * indirect, the sources must use 1x1 regioning mode.
6572 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6573 * the EU decompression logic not handling VxH indirect addressing
6576 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6577 /* Prior to Broadwell, we only have 8 address subregisters. */
6578 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6579 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6583 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6584 const unsigned reg_count
=
6585 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6587 if (reg_count
> 2) {
6588 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6589 * can be easily lowered (which excludes headers and heterogeneous
6592 assert(!inst
->header_size
);
6593 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6594 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6595 inst
->src
[i
].file
== BAD_FILE
);
6597 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6599 return inst
->exec_size
;
6603 return inst
->exec_size
;
6608 * Return true if splitting out the group of channels of instruction \p inst
6609 * given by lbld.group() requires allocating a temporary for the i-th source
6610 * of the lowered instruction.
6613 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6615 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6616 (inst
->components_read(i
) == 1 &&
6617 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6618 (inst
->flags_written() &
6619 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6623 * Extract the data that would be consumed by the channel group given by
6624 * lbld.group() from the i-th source region of instruction \p inst and return
6625 * it as result in packed form.
6628 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6630 assert(lbld
.group() >= inst
->group
);
6632 /* Specified channel group from the source region. */
6633 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6635 if (needs_src_copy(lbld
, inst
, i
)) {
6636 /* Builder of the right width to perform the copy avoiding uninitialized
6637 * data if the lowered execution size is greater than the original
6638 * execution size of the instruction.
6640 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6641 inst
->exec_size
), 0);
6642 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6644 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6645 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6649 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6650 /* The source is invariant for all dispatch_width-wide groups of the
6653 return inst
->src
[i
];
6656 /* We can just point the lowered instruction at the right channel group
6657 * from the original region.
6664 * Return true if splitting out the group of channels of instruction \p inst
6665 * given by lbld.group() requires allocating a temporary for the destination
6666 * of the lowered instruction and copying the data back to the original
6667 * destination region.
6670 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6672 /* If the instruction writes more than one component we'll have to shuffle
6673 * the results of multiple lowered instructions in order to make sure that
6674 * they end up arranged correctly in the original destination region.
6676 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6679 /* If the lowered execution size is larger than the original the result of
6680 * the instruction won't fit in the original destination, so we'll have to
6681 * allocate a temporary in any case.
6683 if (lbld
.dispatch_width() > inst
->exec_size
)
6686 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6687 /* If we already made a copy of the source for other reasons there won't
6688 * be any overlap with the destination.
6690 if (needs_src_copy(lbld
, inst
, i
))
6693 /* In order to keep the logic simple we emit a copy whenever the
6694 * destination region doesn't exactly match an overlapping source, which
6695 * may point at the source and destination not being aligned group by
6696 * group which could cause one of the lowered instructions to overwrite
6697 * the data read from the same source by other lowered instructions.
6699 if (regions_overlap(inst
->dst
, inst
->size_written
,
6700 inst
->src
[i
], inst
->size_read(i
)) &&
6701 !inst
->dst
.equals(inst
->src
[i
]))
6709 * Insert data from a packed temporary into the channel group given by
6710 * lbld.group() of the destination region of instruction \p inst and return
6711 * the temporary as result. Any copy instructions that are required for
6712 * unzipping the previous value (in the case of partial writes) will be
6713 * inserted using \p lbld_before and any copy instructions required for
6714 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6717 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6720 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6721 assert(lbld_before
.group() == lbld_after
.group());
6722 assert(lbld_after
.group() >= inst
->group
);
6724 /* Specified channel group from the destination region. */
6725 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6726 const unsigned dst_size
= inst
->size_written
/
6727 inst
->dst
.component_size(inst
->exec_size
);
6729 if (needs_dst_copy(lbld_after
, inst
)) {
6730 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6732 if (inst
->predicate
) {
6733 /* Handle predication by copying the original contents of
6734 * the destination into the temporary before emitting the
6735 * lowered instruction.
6737 const fs_builder gbld_before
=
6738 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6739 inst
->exec_size
), 0);
6740 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6741 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6742 offset(dst
, inst
->exec_size
, k
));
6746 const fs_builder gbld_after
=
6747 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6748 inst
->exec_size
), 0);
6749 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6750 /* Use a builder of the right width to perform the copy avoiding
6751 * uninitialized data if the lowered execution size is greater than
6752 * the original execution size of the instruction.
6754 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6755 offset(tmp
, lbld_after
, k
));
6761 /* No need to allocate a temporary for the lowered instruction, just
6762 * take the right group of channels from the original region.
6769 fs_visitor::lower_simd_width()
6771 bool progress
= false;
6773 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6774 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6776 if (lower_width
!= inst
->exec_size
) {
6777 /* Builder matching the original instruction. We may also need to
6778 * emit an instruction of width larger than the original, set the
6779 * execution size of the builder to the highest of both for now so
6780 * we're sure that both cases can be handled.
6782 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6783 const fs_builder ibld
= bld
.at(block
, inst
)
6784 .exec_all(inst
->force_writemask_all
)
6785 .group(max_width
, inst
->group
/ max_width
);
6787 /* Split the copies in chunks of the execution width of either the
6788 * original or the lowered instruction, whichever is lower.
6790 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6791 const unsigned dst_size
= inst
->size_written
/
6792 inst
->dst
.component_size(inst
->exec_size
);
6794 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6796 /* Inserting the zip, unzip, and duplicated instructions in all of
6797 * the right spots is somewhat tricky. All of the unzip and any
6798 * instructions from the zip which unzip the destination prior to
6799 * writing need to happen before all of the per-group instructions
6800 * and the zip instructions need to happen after. In order to sort
6801 * this all out, we insert the unzip instructions before \p inst,
6802 * insert the per-group instructions after \p inst (i.e. before
6803 * inst->next), and insert the zip instructions before the
6804 * instruction after \p inst. Since we are inserting instructions
6805 * after \p inst, inst->next is a moving target and we need to save
6806 * it off here so that we insert the zip instructions in the right
6809 * Since we're inserting split instructions after after_inst, the
6810 * instructions will end up in the reverse order that we insert them.
6811 * However, certain render target writes require that the low group
6812 * instructions come before the high group. From the Ivy Bridge PRM
6813 * Vol. 4, Pt. 1, Section 3.9.11:
6815 * "If multiple SIMD8 Dual Source messages are delivered by the
6816 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6817 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6818 * Group Select setting."
6820 * And, from Section 3.9.11.1 of the same PRM:
6822 * "When SIMD32 or SIMD16 PS threads send render target writes
6823 * with multiple SIMD8 and SIMD16 messages, the following must
6826 * All the slots (as described above) must have a corresponding
6827 * render target write irrespective of the slot's validity. A slot
6828 * is considered valid when at least one sample is enabled. For
6829 * example, a SIMD16 PS thread must send two SIMD8 render target
6830 * writes to cover all the slots.
6832 * PS thread must send SIMD render target write messages with
6833 * increasing slot numbers. For example, SIMD16 thread has
6834 * Slot[15:0] and if two SIMD8 render target writes are used, the
6835 * first SIMD8 render target write must send Slot[7:0] and the
6836 * next one must send Slot[15:8]."
6838 * In order to make low group instructions come before high group
6839 * instructions (this is required for some render target writes), we
6840 * split from the highest group to lowest.
6842 exec_node
*const after_inst
= inst
->next
;
6843 for (int i
= n
- 1; i
>= 0; i
--) {
6844 /* Emit a copy of the original instruction with the lowered width.
6845 * If the EOT flag was set throw it away except for the last
6846 * instruction to avoid killing the thread prematurely.
6848 fs_inst split_inst
= *inst
;
6849 split_inst
.exec_size
= lower_width
;
6850 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6852 /* Select the correct channel enables for the i-th group, then
6853 * transform the sources and destination and emit the lowered
6856 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6858 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6859 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6861 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6862 lbld
.at(block
, after_inst
), inst
);
6863 split_inst
.size_written
=
6864 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6866 lbld
.at(block
, inst
->next
).emit(split_inst
);
6869 inst
->remove(block
);
6875 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6881 * Transform barycentric vectors into the interleaved form expected by the PLN
6882 * instruction and returned by the Gen7+ PI shared function.
6884 * For channels 0-15 in SIMD16 mode they are expected to be laid out as
6885 * follows in the register file:
6892 * There is no need to handle SIMD32 here -- This is expected to be run after
6893 * SIMD lowering, since SIMD lowering relies on vectors having the standard
6897 fs_visitor::lower_barycentrics()
6899 const bool has_interleaved_layout
= devinfo
->has_pln
|| devinfo
->gen
>= 7;
6900 bool progress
= false;
6902 if (stage
!= MESA_SHADER_FRAGMENT
|| !has_interleaved_layout
)
6905 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6906 if (inst
->exec_size
< 16)
6909 const fs_builder
ibld(this, block
, inst
);
6910 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
6912 switch (inst
->opcode
) {
6913 case FS_OPCODE_LINTERP
: {
6914 assert(inst
->exec_size
== 16);
6915 const fs_reg tmp
= ibld
.vgrf(inst
->src
[0].type
, 2);
6918 for (unsigned i
= 0; i
< ARRAY_SIZE(srcs
); i
++)
6919 srcs
[i
] = horiz_offset(offset(inst
->src
[0], ibld
, i
% 2),
6922 ubld
.LOAD_PAYLOAD(tmp
, srcs
, ARRAY_SIZE(srcs
), ARRAY_SIZE(srcs
));
6928 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6929 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6930 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
: {
6931 assert(inst
->exec_size
== 16);
6932 const fs_reg tmp
= ibld
.vgrf(inst
->dst
.type
, 2);
6934 for (unsigned i
= 0; i
< 2; i
++) {
6935 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
6936 fs_inst
*mov
= ibld
.at(block
, inst
->next
).group(8, g
)
6937 .MOV(horiz_offset(offset(inst
->dst
, ibld
, i
),
6939 offset(tmp
, ubld
, 2 * g
+ i
));
6940 mov
->predicate
= inst
->predicate
;
6941 mov
->predicate_inverse
= inst
->predicate_inverse
;
6942 mov
->flag_subreg
= inst
->flag_subreg
;
6956 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6962 fs_visitor::dump_instructions()
6964 dump_instructions(NULL
);
6968 fs_visitor::dump_instructions(const char *name
)
6970 FILE *file
= stderr
;
6971 if (name
&& geteuid() != 0) {
6972 file
= fopen(name
, "w");
6978 const register_pressure
&rp
= regpressure_analysis
.require();
6979 unsigned ip
= 0, max_pressure
= 0;
6980 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
6981 max_pressure
= MAX2(max_pressure
, rp
.regs_live_at_ip
[ip
]);
6982 fprintf(file
, "{%3d} %4d: ", rp
.regs_live_at_ip
[ip
], ip
);
6983 dump_instruction(inst
, file
);
6986 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
6989 foreach_in_list(backend_instruction
, inst
, &instructions
) {
6990 fprintf(file
, "%4d: ", ip
++);
6991 dump_instruction(inst
, file
);
6995 if (file
!= stderr
) {
7001 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
7003 dump_instruction(be_inst
, stderr
);
7007 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
7009 fs_inst
*inst
= (fs_inst
*)be_inst
;
7011 if (inst
->predicate
) {
7012 fprintf(file
, "(%cf%d.%d) ",
7013 inst
->predicate_inverse
? '-' : '+',
7014 inst
->flag_subreg
/ 2,
7015 inst
->flag_subreg
% 2);
7018 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
7020 fprintf(file
, ".sat");
7021 if (inst
->conditional_mod
) {
7022 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
7023 if (!inst
->predicate
&&
7024 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
7025 inst
->opcode
!= BRW_OPCODE_CSEL
&&
7026 inst
->opcode
!= BRW_OPCODE_IF
&&
7027 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
7028 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
7029 inst
->flag_subreg
% 2);
7032 fprintf(file
, "(%d) ", inst
->exec_size
);
7035 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
7038 if (inst
->ex_mlen
) {
7039 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
7043 fprintf(file
, "(EOT) ");
7046 switch (inst
->dst
.file
) {
7048 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
7051 fprintf(file
, "g%d", inst
->dst
.nr
);
7054 fprintf(file
, "m%d", inst
->dst
.nr
);
7057 fprintf(file
, "(null)");
7060 fprintf(file
, "***u%d***", inst
->dst
.nr
);
7063 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
7066 switch (inst
->dst
.nr
) {
7068 fprintf(file
, "null");
7070 case BRW_ARF_ADDRESS
:
7071 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
7073 case BRW_ARF_ACCUMULATOR
:
7074 fprintf(file
, "acc%d", inst
->dst
.subnr
);
7077 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7080 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7085 unreachable("not reached");
7088 if (inst
->dst
.offset
||
7089 (inst
->dst
.file
== VGRF
&&
7090 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
7091 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
7092 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
7093 inst
->dst
.offset
% reg_size
);
7096 if (inst
->dst
.stride
!= 1)
7097 fprintf(file
, "<%u>", inst
->dst
.stride
);
7098 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
7100 for (int i
= 0; i
< inst
->sources
; i
++) {
7101 if (inst
->src
[i
].negate
)
7103 if (inst
->src
[i
].abs
)
7105 switch (inst
->src
[i
].file
) {
7107 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
7110 fprintf(file
, "g%d", inst
->src
[i
].nr
);
7113 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
7116 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
7119 fprintf(file
, "u%d", inst
->src
[i
].nr
);
7122 fprintf(file
, "(null)");
7125 switch (inst
->src
[i
].type
) {
7126 case BRW_REGISTER_TYPE_F
:
7127 fprintf(file
, "%-gf", inst
->src
[i
].f
);
7129 case BRW_REGISTER_TYPE_DF
:
7130 fprintf(file
, "%fdf", inst
->src
[i
].df
);
7132 case BRW_REGISTER_TYPE_W
:
7133 case BRW_REGISTER_TYPE_D
:
7134 fprintf(file
, "%dd", inst
->src
[i
].d
);
7136 case BRW_REGISTER_TYPE_UW
:
7137 case BRW_REGISTER_TYPE_UD
:
7138 fprintf(file
, "%uu", inst
->src
[i
].ud
);
7140 case BRW_REGISTER_TYPE_Q
:
7141 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
7143 case BRW_REGISTER_TYPE_UQ
:
7144 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
7146 case BRW_REGISTER_TYPE_VF
:
7147 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
7148 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
7149 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
7150 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
7151 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
7153 case BRW_REGISTER_TYPE_V
:
7154 case BRW_REGISTER_TYPE_UV
:
7155 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
7156 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
7159 fprintf(file
, "???");
7164 switch (inst
->src
[i
].nr
) {
7166 fprintf(file
, "null");
7168 case BRW_ARF_ADDRESS
:
7169 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
7171 case BRW_ARF_ACCUMULATOR
:
7172 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7175 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7178 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7184 if (inst
->src
[i
].offset
||
7185 (inst
->src
[i
].file
== VGRF
&&
7186 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7187 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7188 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7189 inst
->src
[i
].offset
% reg_size
);
7192 if (inst
->src
[i
].abs
)
7195 if (inst
->src
[i
].file
!= IMM
) {
7197 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7198 unsigned hstride
= inst
->src
[i
].hstride
;
7199 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7201 stride
= inst
->src
[i
].stride
;
7204 fprintf(file
, "<%u>", stride
);
7206 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7209 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7210 fprintf(file
, ", ");
7215 if (inst
->force_writemask_all
)
7216 fprintf(file
, "NoMask ");
7218 if (inst
->exec_size
!= dispatch_width
)
7219 fprintf(file
, "group%d ", inst
->group
);
7221 fprintf(file
, "\n");
7225 fs_visitor::setup_fs_payload_gen6()
7227 assert(stage
== MESA_SHADER_FRAGMENT
);
7228 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7229 const unsigned payload_width
= MIN2(16, dispatch_width
);
7230 assert(dispatch_width
% payload_width
== 0);
7231 assert(devinfo
->gen
>= 6);
7233 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7234 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7236 prog_data
->uses_sample_mask
=
7237 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7239 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7241 * "MSDISPMODE_PERSAMPLE is required in order to select
7244 * So we can only really get sample positions if we are doing real
7245 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7246 * persample dispatch, we hard-code it to 0.5.
7248 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7249 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7251 /* R0: PS thread payload header. */
7254 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7255 /* R1: masks, pixel X/Y coordinates. */
7256 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7259 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7260 /* R3-26: barycentric interpolation coordinates. These appear in the
7261 * same order that they appear in the brw_barycentric_mode enum. Each
7262 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7263 * registers if dispatch width == 16. Coordinates only appear if they
7264 * were enabled using the "Barycentric Interpolation Mode" bits in
7267 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7268 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7269 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7270 payload
.num_regs
+= payload_width
/ 4;
7274 /* R27-28: interpolated depth if uses source depth */
7275 if (prog_data
->uses_src_depth
) {
7276 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7277 payload
.num_regs
+= payload_width
/ 8;
7280 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7281 if (prog_data
->uses_src_w
) {
7282 payload
.source_w_reg
[j
] = payload
.num_regs
;
7283 payload
.num_regs
+= payload_width
/ 8;
7286 /* R31: MSAA position offsets. */
7287 if (prog_data
->uses_pos_offset
) {
7288 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7292 /* R32-33: MSAA input coverage mask */
7293 if (prog_data
->uses_sample_mask
) {
7294 assert(devinfo
->gen
>= 7);
7295 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7296 payload
.num_regs
+= payload_width
/ 8;
7300 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7301 source_depth_to_render_target
= true;
7306 fs_visitor::setup_vs_payload()
7308 /* R0: thread header, R1: urb handles */
7309 payload
.num_regs
= 2;
7313 fs_visitor::setup_gs_payload()
7315 assert(stage
== MESA_SHADER_GEOMETRY
);
7317 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7318 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7320 /* R0: thread header, R1: output URB handles */
7321 payload
.num_regs
= 2;
7323 if (gs_prog_data
->include_primitive_id
) {
7324 /* R2: Primitive ID 0..7 */
7328 /* Always enable VUE handles so we can safely use pull model if needed.
7330 * The push model for a GS uses a ton of register space even for trivial
7331 * scenarios with just a few inputs, so just make things easier and a bit
7332 * safer by always having pull model available.
7334 gs_prog_data
->base
.include_vue_handles
= true;
7336 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7337 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7339 /* Use a maximum of 24 registers for push-model inputs. */
7340 const unsigned max_push_components
= 24;
7342 /* If pushing our inputs would take too many registers, reduce the URB read
7343 * length (which is in HWords, or 8 registers), and resort to pulling.
7345 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7346 * have to multiply by VerticesIn to obtain the total storage requirement.
7348 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7349 max_push_components
) {
7350 vue_prog_data
->urb_read_length
=
7351 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7356 fs_visitor::setup_cs_payload()
7358 assert(devinfo
->gen
>= 7);
7359 payload
.num_regs
= 1;
7362 brw::register_pressure::register_pressure(const fs_visitor
*v
)
7364 const fs_live_variables
&live
= v
->live_analysis
.require();
7365 const unsigned num_instructions
= v
->cfg
->num_blocks
?
7366 v
->cfg
->blocks
[v
->cfg
->num_blocks
- 1]->end_ip
+ 1 : 0;
7368 regs_live_at_ip
= new unsigned[num_instructions
]();
7370 for (unsigned reg
= 0; reg
< v
->alloc
.count
; reg
++) {
7371 for (int ip
= live
.vgrf_start
[reg
]; ip
<= live
.vgrf_end
[reg
]; ip
++)
7372 regs_live_at_ip
[ip
] += v
->alloc
.sizes
[reg
];
7376 brw::register_pressure::~register_pressure()
7378 delete[] regs_live_at_ip
;
7382 fs_visitor::invalidate_analysis(brw::analysis_dependency_class c
)
7384 backend_shader::invalidate_analysis(c
);
7385 live_analysis
.invalidate(c
);
7386 regpressure_analysis
.invalidate(c
);
7390 fs_visitor::optimize()
7392 /* Start by validating the shader we currently have. */
7395 /* bld is the common builder object pointing at the end of the program we
7396 * used to translate it into i965 IR. For the optimization and lowering
7397 * passes coming next, any code added after the end of the program without
7398 * having explicitly called fs_builder::at() clearly points at a mistake.
7399 * Ideally optimization passes wouldn't be part of the visitor so they
7400 * wouldn't have access to bld at all, but they do, so just in case some
7401 * pass forgets to ask for a location explicitly set it to NULL here to
7402 * make it trip. The dispatch width is initialized to a bogus value to
7403 * make sure that optimizations set the execution controls explicitly to
7404 * match the code they are manipulating instead of relying on the defaults.
7406 bld
= fs_builder(this, 64);
7408 assign_constant_locations();
7409 lower_constant_loads();
7413 split_virtual_grfs();
7416 #define OPT(pass, args...) ({ \
7418 bool this_progress = pass(args); \
7420 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7421 char filename[64]; \
7422 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7423 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7425 backend_shader::dump_instructions(filename); \
7430 progress = progress || this_progress; \
7434 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7436 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7437 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7439 backend_shader::dump_instructions(filename
);
7442 bool progress
= false;
7446 /* Before anything else, eliminate dead code. The results of some NIR
7447 * instructions may effectively be calculated twice. Once when the
7448 * instruction is encountered, and again when the user of that result is
7449 * encountered. Wipe those away before algebraic optimizations and
7450 * especially copy propagation can mix things up.
7452 OPT(dead_code_eliminate
);
7454 OPT(remove_extra_rounding_modes
);
7461 OPT(remove_duplicate_mrf_writes
);
7465 OPT(opt_copy_propagation
);
7466 OPT(opt_predicated_break
, this);
7467 OPT(opt_cmod_propagation
);
7468 OPT(dead_code_eliminate
);
7469 OPT(opt_peephole_sel
);
7470 OPT(dead_control_flow_eliminate
, this);
7471 OPT(opt_register_renaming
);
7472 OPT(opt_saturate_propagation
);
7473 OPT(register_coalesce
);
7474 OPT(compute_to_mrf
);
7475 OPT(eliminate_find_live_channel
);
7477 OPT(compact_virtual_grfs
);
7483 if (OPT(lower_pack
)) {
7484 OPT(register_coalesce
);
7485 OPT(dead_code_eliminate
);
7488 OPT(lower_simd_width
);
7489 OPT(lower_barycentrics
);
7491 /* After SIMD lowering just in case we had to unroll the EOT send. */
7492 OPT(opt_sampler_eot
);
7494 OPT(lower_logical_sends
);
7496 /* After logical SEND lowering. */
7497 OPT(fixup_nomask_control_flow
);
7500 OPT(opt_copy_propagation
);
7501 /* Only run after logical send lowering because it's easier to implement
7502 * in terms of physical sends.
7504 if (OPT(opt_zero_samples
))
7505 OPT(opt_copy_propagation
);
7506 /* Run after logical send lowering to give it a chance to CSE the
7507 * LOAD_PAYLOAD instructions created to construct the payloads of
7508 * e.g. texturing messages in cases where it wasn't possible to CSE the
7509 * whole logical instruction.
7512 OPT(register_coalesce
);
7513 OPT(compute_to_mrf
);
7514 OPT(dead_code_eliminate
);
7515 OPT(remove_duplicate_mrf_writes
);
7516 OPT(opt_peephole_sel
);
7519 OPT(opt_redundant_discard_jumps
);
7521 if (OPT(lower_load_payload
)) {
7522 split_virtual_grfs();
7524 /* Lower 64 bit MOVs generated by payload lowering. */
7525 if (!devinfo
->has_64bit_float
&& !devinfo
->has_64bit_int
)
7528 OPT(register_coalesce
);
7529 OPT(lower_simd_width
);
7530 OPT(compute_to_mrf
);
7531 OPT(dead_code_eliminate
);
7534 OPT(opt_combine_constants
);
7535 OPT(lower_integer_multiplication
);
7538 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7539 OPT(opt_cmod_propagation
);
7541 OPT(opt_copy_propagation
);
7542 OPT(dead_code_eliminate
);
7545 if (OPT(lower_regioning
)) {
7546 OPT(opt_copy_propagation
);
7547 OPT(dead_code_eliminate
);
7548 OPT(lower_simd_width
);
7551 OPT(fixup_sends_duplicate_payload
);
7553 lower_uniform_pull_constant_loads();
7559 * From the Skylake PRM Vol. 2a docs for sends:
7561 * "It is required that the second block of GRFs does not overlap with the
7564 * There are plenty of cases where we may accidentally violate this due to
7565 * having, for instance, both sources be the constant 0. This little pass
7566 * just adds a new vgrf for the second payload and copies it over.
7569 fs_visitor::fixup_sends_duplicate_payload()
7571 bool progress
= false;
7573 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7574 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7575 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7576 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7577 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7578 BRW_REGISTER_TYPE_UD
);
7579 /* Sadly, we've lost all notion of channels and bit sizes at this
7580 * point. Just WE_all it.
7582 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7583 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7584 fs_reg copy_dst
= tmp
;
7585 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7586 if (inst
->ex_mlen
== i
+ 1) {
7587 /* Only one register left; do SIMD8 */
7588 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7590 ibld
.MOV(copy_dst
, copy_src
);
7592 copy_src
= offset(copy_src
, ibld
, 1);
7593 copy_dst
= offset(copy_dst
, ibld
, 1);
7601 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7607 * Three source instruction must have a GRF/MRF destination register.
7608 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7611 fs_visitor::fixup_3src_null_dest()
7613 bool progress
= false;
7615 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7616 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7617 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7624 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
7625 DEPENDENCY_VARIABLES
);
7629 * Find the first instruction in the program that might start a region of
7630 * divergent control flow due to a HALT jump. There is no
7631 * find_halt_control_flow_region_end(), the region of divergence extends until
7632 * the only FS_OPCODE_PLACEHOLDER_HALT in the program.
7634 static const fs_inst
*
7635 find_halt_control_flow_region_start(const fs_visitor
*v
)
7637 if (brw_wm_prog_data(v
->prog_data
)->uses_kill
) {
7638 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
7639 if (inst
->opcode
== FS_OPCODE_DISCARD_JUMP
||
7640 inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
)
7649 * Work around the Gen12 hardware bug filed as GEN:BUG:1407528679. EU fusion
7650 * can cause a BB to be executed with all channels disabled, which will lead
7651 * to the execution of any NoMask instructions in it, even though any
7652 * execution-masked instructions will be correctly shot down. This may break
7653 * assumptions of some NoMask SEND messages whose descriptor depends on data
7654 * generated by live invocations of the shader.
7656 * This avoids the problem by predicating certain instructions on an ANY
7657 * horizontal predicate that makes sure that their execution is omitted when
7658 * all channels of the program are disabled.
7661 fs_visitor::fixup_nomask_control_flow()
7663 if (devinfo
->gen
!= 12)
7666 const brw_predicate pred
= dispatch_width
> 16 ? BRW_PREDICATE_ALIGN1_ANY32H
:
7667 dispatch_width
> 8 ? BRW_PREDICATE_ALIGN1_ANY16H
:
7668 BRW_PREDICATE_ALIGN1_ANY8H
;
7669 const fs_inst
*halt_start
= find_halt_control_flow_region_start(this);
7671 bool progress
= false;
7673 const fs_live_variables
&live_vars
= live_analysis
.require();
7675 /* Scan the program backwards in order to be able to easily determine
7676 * whether the flag register is live at any point.
7678 foreach_block_reverse_safe(block
, cfg
) {
7679 BITSET_WORD flag_liveout
= live_vars
.block_data
[block
->num
]
7681 STATIC_ASSERT(ARRAY_SIZE(live_vars
.block_data
[0].flag_liveout
) == 1);
7683 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
7684 if (!inst
->predicate
&& inst
->exec_size
>= 8)
7685 flag_liveout
&= ~inst
->flags_written();
7687 switch (inst
->opcode
) {
7690 /* Note that this doesn't handle FS_OPCODE_DISCARD_JUMP since only
7691 * the first one in the program closes the region of divergent
7692 * control flow due to any HALT instructions -- Instead this is
7693 * handled with the halt_start check below.
7698 case BRW_OPCODE_WHILE
:
7699 case BRW_OPCODE_ENDIF
:
7700 case FS_OPCODE_PLACEHOLDER_HALT
:
7705 /* Note that the vast majority of NoMask SEND instructions in the
7706 * program are harmless while executed in a block with all
7707 * channels disabled, since any instructions with side effects we
7708 * could hit here should be execution-masked.
7710 * The main concern is NoMask SEND instructions where the message
7711 * descriptor or header depends on data generated by live
7712 * invocations of the shader (RESINFO and
7713 * FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically
7714 * computed surface index seem to be the only examples right now
7715 * where this could easily lead to GPU hangs). Unfortunately we
7716 * have no straightforward way to detect that currently, so just
7717 * predicate any NoMask SEND instructions we find under control
7720 * If this proves to have a measurable performance impact it can
7721 * be easily extended with a whitelist of messages we know we can
7722 * safely omit the predication for.
7724 if (depth
&& inst
->force_writemask_all
&&
7725 is_send(inst
) && !inst
->predicate
) {
7726 /* We need to load the execution mask into the flag register by
7727 * using a builder with channel group matching the whole shader
7728 * (rather than the default which is derived from the original
7729 * instruction), in order to avoid getting a right-shifted
7732 const fs_builder ubld
= fs_builder(this, block
, inst
)
7733 .exec_all().group(dispatch_width
, 0);
7734 const fs_reg flag
= retype(brw_flag_reg(0, 0),
7735 BRW_REGISTER_TYPE_UD
);
7737 /* Due to the lack of flag register allocation we need to save
7738 * and restore the flag register if it's live.
7740 const bool save_flag
= flag_liveout
&
7741 flag_mask(flag
, dispatch_width
/ 8);
7742 const fs_reg tmp
= ubld
.group(1, 0).vgrf(flag
.type
);
7745 ubld
.group(1, 0).MOV(tmp
, flag
);
7747 ubld
.emit(FS_OPCODE_LOAD_LIVE_CHANNELS
);
7749 set_predicate(pred
, inst
);
7750 inst
->flag_subreg
= 0;
7753 ubld
.group(1, 0).at(block
, inst
->next
).MOV(flag
, tmp
);
7760 if (inst
== halt_start
)
7763 flag_liveout
|= inst
->flags_read(devinfo
);
7768 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7774 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
7778 static const enum instruction_scheduler_mode pre_modes
[] = {
7780 SCHEDULE_PRE_NON_LIFO
,
7784 static const char *scheduler_mode_name
[] = {
7790 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7792 /* Try each scheduling heuristic to see if it can successfully register
7793 * allocate without spilling. They should be ordered by decreasing
7794 * performance but increasing likelihood of allocating.
7796 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7797 schedule_instructions(pre_modes
[i
]);
7798 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7801 assign_regs_trivial();
7806 /* We only allow spilling for the last schedule mode and only if the
7807 * allow_spilling parameter and dispatch width work out ok.
7809 bool can_spill
= allow_spilling
&&
7810 (i
== ARRAY_SIZE(pre_modes
) - 1) &&
7811 dispatch_width
== min_dispatch_width
;
7813 /* We should only spill registers on the last scheduling. */
7814 assert(!spilled_any_registers
);
7816 allocated
= assign_regs(can_spill
, spill_all
);
7822 if (!allow_spilling
)
7823 fail("Failure to register allocate and spilling is not allowed.");
7825 /* We assume that any spilling is worse than just dropping back to
7826 * SIMD8. There's probably actually some intermediate point where
7827 * SIMD16 with a couple of spills is still better.
7829 if (dispatch_width
> min_dispatch_width
) {
7830 fail("Failure to register allocate. Reduce number of "
7831 "live scalar values to avoid this.");
7834 /* If we failed to allocate, we must have a reason */
7836 } else if (spilled_any_registers
) {
7837 compiler
->shader_perf_log(log_data
,
7838 "%s shader triggered register spilling. "
7839 "Try reducing the number of live scalar "
7840 "values to improve performance.\n",
7844 /* This must come after all optimization and register allocation, since
7845 * it inserts dead code that happens to have side effects, and it does
7846 * so based on the actual physical registers in use.
7848 insert_gen4_send_dependency_workarounds();
7853 opt_bank_conflicts();
7855 schedule_instructions(SCHEDULE_POST
);
7857 if (last_scratch
> 0) {
7858 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7860 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7862 if (stage
== MESA_SHADER_COMPUTE
) {
7863 if (devinfo
->is_haswell
) {
7864 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7865 * field documentation, Haswell supports a minimum of 2kB of
7866 * scratch space for compute shaders, unlike every other stage
7869 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7870 } else if (devinfo
->gen
<= 7) {
7871 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7872 * field documentation, platforms prior to Haswell measure scratch
7873 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7875 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7876 max_scratch_size
= 12 * 1024;
7880 /* We currently only support up to 2MB of scratch space. If we
7881 * need to support more eventually, the documentation suggests
7882 * that we could allocate a larger buffer, and partition it out
7883 * ourselves. We'd just have to undo the hardware's address
7884 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7885 * and then add FFTID * (Larger Per Thread Scratch Space).
7887 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7888 * Thread Group Tracking > Local Memory/Scratch Space.
7890 assert(prog_data
->total_scratch
< max_scratch_size
);
7897 fs_visitor::run_vs()
7899 assert(stage
== MESA_SHADER_VERTEX
);
7903 if (shader_time_index
>= 0)
7904 emit_shader_time_begin();
7913 if (shader_time_index
>= 0)
7914 emit_shader_time_end();
7920 assign_curb_setup();
7921 assign_vs_urb_setup();
7923 fixup_3src_null_dest();
7924 allocate_registers(8, true);
7930 fs_visitor::set_tcs_invocation_id()
7932 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7933 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7935 const unsigned instance_id_mask
=
7936 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7937 const unsigned instance_id_shift
=
7938 devinfo
->gen
>= 11 ? 16 : 17;
7940 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7941 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7942 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7943 brw_imm_ud(instance_id_mask
));
7945 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7947 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7948 /* gl_InvocationID is just the thread number */
7949 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7953 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7955 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7956 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7957 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7958 bld
.MOV(channels_ud
, channels_uw
);
7960 if (tcs_prog_data
->instances
== 1) {
7961 invocation_id
= channels_ud
;
7963 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7964 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
7965 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
7970 fs_visitor::run_tcs()
7972 assert(stage
== MESA_SHADER_TESS_CTRL
);
7974 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7975 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7976 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
7978 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
7979 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7981 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
7982 /* r1-r4 contain the ICP handles. */
7983 payload
.num_regs
= 5;
7985 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7986 assert(tcs_key
->input_vertices
> 0);
7987 /* r1 contains output handles, r2 may contain primitive ID, then the
7988 * ICP handles occupy the next 1-32 registers.
7990 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
7991 tcs_key
->input_vertices
;
7994 if (shader_time_index
>= 0)
7995 emit_shader_time_begin();
7997 /* Initialize gl_InvocationID */
7998 set_tcs_invocation_id();
8000 const bool fix_dispatch_mask
=
8001 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
8002 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
8004 /* Fix the disptach mask */
8005 if (fix_dispatch_mask
) {
8006 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
8007 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
8008 bld
.IF(BRW_PREDICATE_NORMAL
);
8013 if (fix_dispatch_mask
) {
8014 bld
.emit(BRW_OPCODE_ENDIF
);
8017 /* Emit EOT write; set TR DS Cache bit */
8019 fs_reg(get_tcs_output_urb_handle()),
8020 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
8021 fs_reg(brw_imm_ud(0)),
8023 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
8024 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
8026 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
8027 bld
.null_reg_ud(), payload
);
8031 if (shader_time_index
>= 0)
8032 emit_shader_time_end();
8041 assign_curb_setup();
8042 assign_tcs_urb_setup();
8044 fixup_3src_null_dest();
8045 allocate_registers(8, true);
8051 fs_visitor::run_tes()
8053 assert(stage
== MESA_SHADER_TESS_EVAL
);
8055 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
8056 payload
.num_regs
= 5;
8058 if (shader_time_index
>= 0)
8059 emit_shader_time_begin();
8068 if (shader_time_index
>= 0)
8069 emit_shader_time_end();
8075 assign_curb_setup();
8076 assign_tes_urb_setup();
8078 fixup_3src_null_dest();
8079 allocate_registers(8, true);
8085 fs_visitor::run_gs()
8087 assert(stage
== MESA_SHADER_GEOMETRY
);
8091 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
8093 if (gs_compile
->control_data_header_size_bits
> 0) {
8094 /* Create a VGRF to store accumulated control data bits. */
8095 this->control_data_bits
= vgrf(glsl_type::uint_type
);
8097 /* If we're outputting more than 32 control data bits, then EmitVertex()
8098 * will set control_data_bits to 0 after emitting the first vertex.
8099 * Otherwise, we need to initialize it to 0 here.
8101 if (gs_compile
->control_data_header_size_bits
<= 32) {
8102 const fs_builder abld
= bld
.annotate("initialize control data bits");
8103 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
8107 if (shader_time_index
>= 0)
8108 emit_shader_time_begin();
8112 emit_gs_thread_end();
8114 if (shader_time_index
>= 0)
8115 emit_shader_time_end();
8124 assign_curb_setup();
8125 assign_gs_urb_setup();
8127 fixup_3src_null_dest();
8128 allocate_registers(8, true);
8133 /* From the SKL PRM, Volume 16, Workarounds:
8135 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
8136 * only header phases (R0-R2)
8138 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
8139 * have been header only.
8141 * Instead of enabling push constants one can alternatively enable one of the
8142 * inputs. Here one simply chooses "layer" which shouldn't impose much
8146 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
8148 if (wm_prog_data
->num_varying_inputs
)
8151 if (wm_prog_data
->base
.curb_read_length
)
8154 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
8155 wm_prog_data
->num_varying_inputs
= 1;
8159 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
8161 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
8162 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
8164 assert(stage
== MESA_SHADER_FRAGMENT
);
8166 if (devinfo
->gen
>= 6)
8167 setup_fs_payload_gen6();
8169 setup_fs_payload_gen4();
8173 } else if (do_rep_send
) {
8174 assert(dispatch_width
== 16);
8175 emit_repclear_shader();
8177 if (shader_time_index
>= 0)
8178 emit_shader_time_begin();
8180 if (nir
->info
.inputs_read
> 0 ||
8181 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
8182 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
8183 if (devinfo
->gen
< 6)
8184 emit_interpolation_setup_gen4();
8186 emit_interpolation_setup_gen6();
8189 /* We handle discards by keeping track of the still-live pixels in f0.1.
8190 * Initialize it with the dispatched pixels.
8192 if (wm_prog_data
->uses_kill
) {
8193 const unsigned lower_width
= MIN2(dispatch_width
, 16);
8194 for (unsigned i
= 0; i
< dispatch_width
/ lower_width
; i
++) {
8195 const fs_reg dispatch_mask
=
8196 devinfo
->gen
>= 6 ? brw_vec1_grf((i
? 2 : 1), 7) :
8198 bld
.exec_all().group(1, 0)
8199 .MOV(sample_mask_reg(bld
.group(lower_width
, i
)),
8200 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
8209 if (wm_prog_data
->uses_kill
)
8210 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
8212 if (wm_key
->alpha_test_func
)
8217 if (shader_time_index
>= 0)
8218 emit_shader_time_end();
8224 assign_curb_setup();
8226 if (devinfo
->gen
>= 9)
8227 gen9_ps_header_only_workaround(wm_prog_data
);
8231 fixup_3src_null_dest();
8232 allocate_registers(8, allow_spilling
);
8242 fs_visitor::run_cs(unsigned min_dispatch_width
)
8244 assert(stage
== MESA_SHADER_COMPUTE
);
8245 assert(dispatch_width
>= min_dispatch_width
);
8249 if (shader_time_index
>= 0)
8250 emit_shader_time_begin();
8252 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
8253 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
8254 const fs_builder abld
= bld
.exec_all().group(1, 0);
8255 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
8256 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
8264 emit_cs_terminate();
8266 if (shader_time_index
>= 0)
8267 emit_shader_time_end();
8273 assign_curb_setup();
8275 fixup_3src_null_dest();
8276 allocate_registers(min_dispatch_width
, true);
8285 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
8287 nir_foreach_use(src
, def
) {
8288 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
8291 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
8292 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
8296 nir_foreach_if_use(src
, def
)
8303 * Return a bitfield where bit n is set if barycentric interpolation mode n
8304 * (see enum brw_barycentric_mode) is needed by the fragment shader.
8306 * We examine the load_barycentric intrinsics rather than looking at input
8307 * variables so that we catch interpolateAtCentroid() messages too, which
8308 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
8311 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
8312 const nir_shader
*shader
)
8314 unsigned barycentric_interp_modes
= 0;
8316 nir_foreach_function(f
, shader
) {
8320 nir_foreach_block(block
, f
->impl
) {
8321 nir_foreach_instr(instr
, block
) {
8322 if (instr
->type
!= nir_instr_type_intrinsic
)
8325 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8326 switch (intrin
->intrinsic
) {
8327 case nir_intrinsic_load_barycentric_pixel
:
8328 case nir_intrinsic_load_barycentric_centroid
:
8329 case nir_intrinsic_load_barycentric_sample
:
8335 /* Ignore WPOS; it doesn't require interpolation. */
8336 assert(intrin
->dest
.is_ssa
);
8337 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8340 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8341 nir_intrinsic_interp_mode(intrin
);
8342 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8343 enum brw_barycentric_mode bary
=
8344 brw_barycentric_mode(interp
, bary_op
);
8346 barycentric_interp_modes
|= 1 << bary
;
8348 if (devinfo
->needs_unlit_centroid_workaround
&&
8349 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8350 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8355 return barycentric_interp_modes
;
8359 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8360 const nir_shader
*shader
)
8362 prog_data
->flat_inputs
= 0;
8364 nir_foreach_variable(var
, &shader
->inputs
) {
8365 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8366 for (unsigned s
= 0; s
< slots
; s
++) {
8367 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8369 if (input_index
< 0)
8373 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8374 prog_data
->flat_inputs
|= 1 << input_index
;
8380 computed_depth_mode(const nir_shader
*shader
)
8382 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8383 switch (shader
->info
.fs
.depth_layout
) {
8384 case FRAG_DEPTH_LAYOUT_NONE
:
8385 case FRAG_DEPTH_LAYOUT_ANY
:
8386 return BRW_PSCDEPTH_ON
;
8387 case FRAG_DEPTH_LAYOUT_GREATER
:
8388 return BRW_PSCDEPTH_ON_GE
;
8389 case FRAG_DEPTH_LAYOUT_LESS
:
8390 return BRW_PSCDEPTH_ON_LE
;
8391 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8392 return BRW_PSCDEPTH_OFF
;
8395 return BRW_PSCDEPTH_OFF
;
8399 * Move load_interpolated_input with simple (payload-based) barycentric modes
8400 * to the top of the program so we don't emit multiple PLNs for the same input.
8402 * This works around CSE not being able to handle non-dominating cases
8408 * interpolate the same exact input
8411 * This should be replaced by global value numbering someday.
8414 move_interpolation_to_top(nir_shader
*nir
)
8416 bool progress
= false;
8418 nir_foreach_function(f
, nir
) {
8422 nir_block
*top
= nir_start_block(f
->impl
);
8423 exec_node
*cursor_node
= NULL
;
8425 nir_foreach_block(block
, f
->impl
) {
8429 nir_foreach_instr_safe(instr
, block
) {
8430 if (instr
->type
!= nir_instr_type_intrinsic
)
8433 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8434 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8436 nir_intrinsic_instr
*bary_intrinsic
=
8437 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8438 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8440 /* Leave interpolateAtSample/Offset() where they are. */
8441 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8442 op
== nir_intrinsic_load_barycentric_at_offset
)
8445 nir_instr
*move
[3] = {
8446 &bary_intrinsic
->instr
,
8447 intrin
->src
[1].ssa
->parent_instr
,
8451 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8452 if (move
[i
]->block
!= top
) {
8453 move
[i
]->block
= top
;
8454 exec_node_remove(&move
[i
]->node
);
8456 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8458 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8460 cursor_node
= &move
[i
]->node
;
8466 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8467 ((unsigned) nir_metadata_block_index
|
8468 (unsigned) nir_metadata_dominance
));
8475 * Demote per-sample barycentric intrinsics to centroid.
8477 * Useful when rendering to a non-multisampled buffer.
8480 demote_sample_qualifiers(nir_shader
*nir
)
8482 bool progress
= true;
8484 nir_foreach_function(f
, nir
) {
8489 nir_builder_init(&b
, f
->impl
);
8491 nir_foreach_block(block
, f
->impl
) {
8492 nir_foreach_instr_safe(instr
, block
) {
8493 if (instr
->type
!= nir_instr_type_intrinsic
)
8496 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8497 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8498 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8501 b
.cursor
= nir_before_instr(instr
);
8502 nir_ssa_def
*centroid
=
8503 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8504 nir_intrinsic_interp_mode(intrin
));
8505 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8506 nir_src_for_ssa(centroid
));
8507 nir_instr_remove(instr
);
8512 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8513 ((unsigned) nir_metadata_block_index
|
8514 (unsigned) nir_metadata_dominance
));
8521 * Pre-gen6, the register file of the EUs was shared between threads,
8522 * and each thread used some subset allocated on a 16-register block
8523 * granularity. The unit states wanted these block counts.
8526 brw_register_blocks(int reg_count
)
8528 return ALIGN(reg_count
, 16) / 16 - 1;
8532 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8534 const struct brw_wm_prog_key
*key
,
8535 struct brw_wm_prog_data
*prog_data
,
8537 int shader_time_index8
, int shader_time_index16
,
8538 int shader_time_index32
, bool allow_spilling
,
8539 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8540 struct brw_compile_stats
*stats
,
8543 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8545 unsigned max_subgroup_size
= unlikely(INTEL_DEBUG
& DEBUG_DO32
) ? 32 : 16;
8547 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8548 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8549 brw_nir_lower_fs_outputs(shader
);
8551 if (devinfo
->gen
< 6)
8552 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8554 /* From the SKL PRM, Volume 7, "Alpha Coverage":
8555 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
8556 * hardware, regardless of the state setting for this feature."
8558 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
) {
8559 /* Run constant fold optimization in order to get the correct source
8560 * offset to determine render target 0 store instruction in
8561 * emit_alpha_to_coverage pass.
8563 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8564 NIR_PASS_V(shader
, brw_nir_lower_alpha_to_coverage
);
8567 if (!key
->multisample_fbo
)
8568 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8569 NIR_PASS_V(shader
, move_interpolation_to_top
);
8570 brw_postprocess_nir(shader
, compiler
, true);
8572 /* key->alpha_test_func means simulating alpha testing via discards,
8573 * so the shader definitely kills pixels.
8575 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8576 key
->alpha_test_func
;
8577 prog_data
->uses_omask
= key
->multisample_fbo
&&
8578 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8579 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8580 prog_data
->computed_stencil
=
8581 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8583 prog_data
->persample_dispatch
=
8584 key
->multisample_fbo
&&
8585 (key
->persample_interp
||
8586 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8587 SYSTEM_BIT_SAMPLE_POS
)) ||
8588 shader
->info
.fs
.uses_sample_qualifier
||
8589 shader
->info
.outputs_read
);
8591 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8593 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8594 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8595 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8597 prog_data
->barycentric_interp_modes
=
8598 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8600 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8601 brw_compute_flat_inputs(prog_data
, shader
);
8603 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8605 fs_visitor
v8(compiler
, log_data
, mem_ctx
, &key
->base
,
8606 &prog_data
->base
, shader
, 8,
8607 shader_time_index8
);
8608 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
8610 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
8613 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8615 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
8616 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
8619 /* Limit dispatch width to simd8 with dual source blending on gen8.
8620 * See: https://gitlab.freedesktop.org/mesa/mesa/issues/1917
8622 if (devinfo
->gen
== 8 && prog_data
->dual_src_blend
&&
8623 !(INTEL_DEBUG
& DEBUG_NO8
)) {
8624 assert(!use_rep_send
);
8625 v8
.limit_dispatch_width(8, "gen8 workaround: "
8626 "using SIMD8 when dual src blending.\n");
8629 if (v8
.max_dispatch_width
>= 16 &&
8630 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8631 /* Try a SIMD16 compile */
8632 fs_visitor
v16(compiler
, log_data
, mem_ctx
, &key
->base
,
8633 &prog_data
->base
, shader
, 16,
8634 shader_time_index16
);
8635 v16
.import_uniforms(&v8
);
8636 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
8637 compiler
->shader_perf_log(log_data
,
8638 "SIMD16 shader failed to compile: %s",
8641 simd16_cfg
= v16
.cfg
;
8642 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
8643 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
8647 /* Currently, the compiler only supports SIMD32 on SNB+ */
8648 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
8649 compiler
->devinfo
->gen
>= 6 &&
8650 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
8651 /* Try a SIMD32 compile */
8652 fs_visitor
v32(compiler
, log_data
, mem_ctx
, &key
->base
,
8653 &prog_data
->base
, shader
, 32,
8654 shader_time_index32
);
8655 v32
.import_uniforms(&v8
);
8656 if (!v32
.run_fs(allow_spilling
, false)) {
8657 compiler
->shader_perf_log(log_data
,
8658 "SIMD32 shader failed to compile: %s",
8661 simd32_cfg
= v32
.cfg
;
8662 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
8663 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
8667 /* When the caller requests a repclear shader, they want SIMD16-only */
8671 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8672 * at the top to select the shader. We've never implemented that.
8673 * Instead, we just give them exactly one shader and we pick the widest one
8676 if (compiler
->devinfo
->gen
< 5) {
8677 if (simd32_cfg
|| simd16_cfg
)
8683 /* If computed depth is enabled SNB only allows SIMD8. */
8684 if (compiler
->devinfo
->gen
== 6 &&
8685 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8686 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8688 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8689 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8690 * the data available in the base prog data struct for convenience.
8693 prog_data
->base
.dispatch_grf_start_reg
=
8694 prog_data
->dispatch_grf_start_reg_16
;
8695 } else if (simd32_cfg
) {
8696 prog_data
->base
.dispatch_grf_start_reg
=
8697 prog_data
->dispatch_grf_start_reg_32
;
8701 if (prog_data
->persample_dispatch
) {
8702 /* Starting with SandyBridge (where we first get MSAA), the different
8703 * pixel dispatch combinations are grouped into classifications A
8704 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
8705 * generations, the only configurations supporting persample dispatch
8706 * are are this in which only one dispatch width is enabled.
8708 if (simd32_cfg
|| simd16_cfg
)
8714 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8715 v8
.shader_stats
, v8
.runtime_check_aads_emit
,
8716 MESA_SHADER_FRAGMENT
);
8718 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8719 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8720 shader
->info
.label
?
8721 shader
->info
.label
: "unnamed",
8722 shader
->info
.name
));
8726 prog_data
->dispatch_8
= true;
8727 g
.generate_code(simd8_cfg
, 8, stats
);
8728 stats
= stats
? stats
+ 1 : NULL
;
8732 prog_data
->dispatch_16
= true;
8733 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16, stats
);
8734 stats
= stats
? stats
+ 1 : NULL
;
8738 prog_data
->dispatch_32
= true;
8739 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32, stats
);
8740 stats
= stats
? stats
+ 1 : NULL
;
8743 return g
.get_assembly();
8747 fs_visitor::emit_cs_work_group_id_setup()
8749 assert(stage
== MESA_SHADER_COMPUTE
);
8751 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8753 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8754 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8755 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8757 bld
.MOV(*reg
, r0_1
);
8758 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8759 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8765 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8767 block
->dwords
= dwords
;
8768 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8769 block
->size
= block
->regs
* 32;
8773 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8774 struct brw_cs_prog_data
*cs_prog_data
)
8776 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8777 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8778 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8780 /* The thread ID should be stored in the last param dword */
8781 assert(subgroup_id_index
== -1 ||
8782 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8784 unsigned cross_thread_dwords
, per_thread_dwords
;
8785 if (!cross_thread_supported
) {
8786 cross_thread_dwords
= 0u;
8787 per_thread_dwords
= prog_data
->nr_params
;
8788 } else if (subgroup_id_index
>= 0) {
8789 /* Fill all but the last register with cross-thread payload */
8790 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8791 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8792 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8794 /* Fill all data using cross-thread payload */
8795 cross_thread_dwords
= prog_data
->nr_params
;
8796 per_thread_dwords
= 0u;
8799 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8800 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8802 unsigned total_dwords
=
8803 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
8804 cs_prog_data
->push
.cross_thread
.size
) / 4;
8805 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
8807 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8808 cs_prog_data
->push
.per_thread
.size
== 0);
8809 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8810 cs_prog_data
->push
.per_thread
.dwords
==
8811 prog_data
->nr_params
);
8815 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
8817 cs_prog_data
->simd_size
= size
;
8818 unsigned group_size
= cs_prog_data
->local_size
[0] *
8819 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
8820 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
8824 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8826 const struct brw_cs_prog_key
*key
,
8827 const nir_shader
*src_shader
,
8828 unsigned dispatch_width
)
8830 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8831 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8833 NIR_PASS_V(shader
, brw_nir_lower_cs_intrinsics
, dispatch_width
);
8835 /* Clean up after the local index and ID calculations. */
8836 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8837 NIR_PASS_V(shader
, nir_opt_dce
);
8839 brw_postprocess_nir(shader
, compiler
, true);
8845 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8847 const struct brw_cs_prog_key
*key
,
8848 struct brw_cs_prog_data
*prog_data
,
8849 const nir_shader
*src_shader
,
8850 int shader_time_index
,
8851 struct brw_compile_stats
*stats
,
8854 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8855 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8856 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8857 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8858 prog_data
->slm_size
= src_shader
->num_shared
;
8859 unsigned local_workgroup_size
=
8860 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
8861 src_shader
->info
.cs
.local_size
[2];
8863 /* Limit max_threads to 64 for the GPGPU_WALKER command */
8864 const uint32_t max_threads
= MIN2(64, compiler
->devinfo
->max_cs_threads
);
8865 unsigned min_dispatch_width
=
8866 DIV_ROUND_UP(local_workgroup_size
, max_threads
);
8867 min_dispatch_width
= MAX2(8, min_dispatch_width
);
8868 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
8869 assert(min_dispatch_width
<= 32);
8870 unsigned max_dispatch_width
= 32;
8872 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8873 fs_visitor
*v
= NULL
;
8874 const char *fail_msg
= NULL
;
8876 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8877 /* These enum values are expressly chosen to be equal to the subgroup
8878 * size that they require.
8880 const unsigned required_dispatch_width
=
8881 (unsigned)key
->base
.subgroup_size_type
;
8882 assert(required_dispatch_width
== 8 ||
8883 required_dispatch_width
== 16 ||
8884 required_dispatch_width
== 32);
8885 if (required_dispatch_width
< min_dispatch_width
||
8886 required_dispatch_width
> max_dispatch_width
) {
8887 fail_msg
= "Cannot satisfy explicit subgroup size";
8889 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8893 /* Now the main event: Visit the shader IR and generate our CS IR for it.
8895 if (!fail_msg
&& min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8896 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8898 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8900 nir8
, 8, shader_time_index
);
8901 if (!v8
->run_cs(min_dispatch_width
)) {
8902 fail_msg
= v8
->fail_msg
;
8904 /* We should always be able to do SIMD32 for compute shaders */
8905 assert(v8
->max_dispatch_width
>= 32);
8908 cs_set_simd_size(prog_data
, 8);
8909 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8913 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
8914 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
8915 /* Try a SIMD16 compile */
8916 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8918 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8920 nir16
, 16, shader_time_index
);
8922 v16
->import_uniforms(v8
);
8924 if (!v16
->run_cs(min_dispatch_width
)) {
8925 compiler
->shader_perf_log(log_data
,
8926 "SIMD16 shader failed to compile: %s",
8930 "Couldn't generate SIMD16 program and not "
8931 "enough threads for SIMD8";
8934 /* We should always be able to do SIMD32 for compute shaders */
8935 assert(v16
->max_dispatch_width
>= 32);
8938 cs_set_simd_size(prog_data
, 16);
8939 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8943 /* We should always be able to do SIMD32 for compute shaders */
8944 assert(!v16
|| v16
->max_dispatch_width
>= 32);
8946 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
8947 max_dispatch_width
>= 32) {
8948 /* Try a SIMD32 compile */
8949 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8951 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8953 nir32
, 32, shader_time_index
);
8955 v32
->import_uniforms(v8
);
8957 v32
->import_uniforms(v16
);
8959 if (!v32
->run_cs(min_dispatch_width
)) {
8960 compiler
->shader_perf_log(log_data
,
8961 "SIMD32 shader failed to compile: %s",
8965 "Couldn't generate SIMD32 program and not "
8966 "enough threads for SIMD16";
8970 cs_set_simd_size(prog_data
, 32);
8971 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8975 const unsigned *ret
= NULL
;
8976 if (unlikely(v
== NULL
)) {
8979 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
8981 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8982 v
->shader_stats
, v
->runtime_check_aads_emit
,
8983 MESA_SHADER_COMPUTE
);
8984 if (INTEL_DEBUG
& DEBUG_CS
) {
8985 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
8986 src_shader
->info
.label
?
8987 src_shader
->info
.label
: "unnamed",
8988 src_shader
->info
.name
);
8989 g
.enable_debug(name
);
8992 g
.generate_code(v
->cfg
, prog_data
->simd_size
, stats
);
8994 ret
= g
.get_assembly();
9005 * Test the dispatch mask packing assumptions of
9006 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
9007 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
9008 * executed with an unexpected dispatch mask.
9011 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
9013 const gl_shader_stage stage
= bld
.shader
->stage
;
9015 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
9016 bld
.shader
->stage_prog_data
)) {
9017 const fs_builder ubld
= bld
.exec_all().group(1, 0);
9018 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
9019 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
9022 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
9023 ubld
.AND(tmp
, mask
, tmp
);
9025 /* This will loop forever if the dispatch mask doesn't have the expected
9026 * form '2^n-1', in which case tmp will be non-zero.
9028 bld
.emit(BRW_OPCODE_DO
);
9029 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
9030 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));
9035 fs_visitor::workgroup_size() const
9037 assert(stage
== MESA_SHADER_COMPUTE
);
9038 const struct brw_cs_prog_data
*cs
= brw_cs_prog_data(prog_data
);
9039 return cs
->local_size
[0] * cs
->local_size
[1] * cs
->local_size
[2];