2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "dev/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
42 #include "util/u_math.h"
46 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
50 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
51 const fs_reg
*src
, unsigned sources
)
53 memset((void*)this, 0, sizeof(*this));
55 this->src
= new fs_reg
[MAX2(sources
, 3)];
56 for (unsigned i
= 0; i
< sources
; i
++)
57 this->src
[i
] = src
[i
];
59 this->opcode
= opcode
;
61 this->sources
= sources
;
62 this->exec_size
= exec_size
;
65 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
67 assert(this->exec_size
!= 0);
69 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
71 /* This will be the case for almost all instructions. */
78 this->size_written
= dst
.component_size(exec_size
);
81 this->size_written
= 0;
85 unreachable("Invalid destination register file");
88 this->writes_accumulator
= false;
93 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
96 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
98 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
101 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
103 init(opcode
, exec_size
, dst
, NULL
, 0);
106 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
109 const fs_reg src
[1] = { src0
};
110 init(opcode
, exec_size
, dst
, src
, 1);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
114 const fs_reg
&src0
, const fs_reg
&src1
)
116 const fs_reg src
[2] = { src0
, src1
};
117 init(opcode
, exec_size
, dst
, src
, 2);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
123 const fs_reg src
[3] = { src0
, src1
, src2
};
124 init(opcode
, exec_size
, dst
, src
, 3);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
128 const fs_reg src
[], unsigned sources
)
130 init(opcode
, exec_width
, dst
, src
, sources
);
133 fs_inst::fs_inst(const fs_inst
&that
)
135 memcpy((void*)this, &that
, sizeof(that
));
137 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
139 for (unsigned i
= 0; i
< that
.sources
; i
++)
140 this->src
[i
] = that
.src
[i
];
149 fs_inst::resize_sources(uint8_t num_sources
)
151 if (this->sources
!= num_sources
) {
152 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
154 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
155 src
[i
] = this->src
[i
];
159 this->sources
= num_sources
;
164 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
166 const fs_reg
&surf_index
,
167 const fs_reg
&varying_offset
,
168 uint32_t const_offset
)
170 /* We have our constant surface use a pitch of 4 bytes, so our index can
171 * be any component of a vector, and then we load 4 contiguous
172 * components starting from that.
174 * We break down the const_offset to a portion added to the variable offset
175 * and a portion done using fs_reg::offset, which means that if you have
176 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
177 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
178 * later notice that those loads are all the same and eliminate the
181 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
182 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
184 /* The pull load message will load a vec4 (16 bytes). If we are loading
185 * a double this means we are only loading 2 elements worth of data.
186 * We also want to use a 32-bit data type for the dst of the load operation
187 * so other parts of the driver don't get confused about the size of the
190 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
191 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
192 vec4_result
, surf_index
, vec4_offset
);
193 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
195 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
196 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
200 * A helper for MOV generation for fixing up broken hardware SEND dependency
204 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
206 /* The caller always wants uncompressed to emit the minimal extra
207 * dependencies, and to avoid having to deal with aligning its regs to 2.
209 const fs_builder ubld
= bld
.annotate("send dependency resolve")
212 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
216 fs_inst::is_send_from_grf() const
219 case SHADER_OPCODE_SEND
:
220 case SHADER_OPCODE_SHADER_TIME_ADD
:
221 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
222 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
223 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
224 case SHADER_OPCODE_URB_WRITE_SIMD8
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
228 case SHADER_OPCODE_URB_READ_SIMD8
:
229 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
230 case SHADER_OPCODE_INTERLOCK
:
231 case SHADER_OPCODE_MEMORY_FENCE
:
232 case SHADER_OPCODE_BARRIER
:
234 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
235 return src
[1].file
== VGRF
;
236 case FS_OPCODE_FB_WRITE
:
237 case FS_OPCODE_FB_READ
:
238 return src
[0].file
== VGRF
;
241 return src
[0].file
== VGRF
;
248 fs_inst::is_control_source(unsigned arg
) const
251 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
253 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
256 case SHADER_OPCODE_BROADCAST
:
257 case SHADER_OPCODE_SHUFFLE
:
258 case SHADER_OPCODE_QUAD_SWIZZLE
:
259 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
261 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
262 case SHADER_OPCODE_GET_BUFFER_SIZE
:
265 case SHADER_OPCODE_MOV_INDIRECT
:
266 case SHADER_OPCODE_CLUSTER_BROADCAST
:
267 case SHADER_OPCODE_TEX
:
269 case SHADER_OPCODE_TXD
:
270 case SHADER_OPCODE_TXF
:
271 case SHADER_OPCODE_TXF_LZ
:
272 case SHADER_OPCODE_TXF_CMS
:
273 case SHADER_OPCODE_TXF_CMS_W
:
274 case SHADER_OPCODE_TXF_UMS
:
275 case SHADER_OPCODE_TXF_MCS
:
276 case SHADER_OPCODE_TXL
:
277 case SHADER_OPCODE_TXL_LZ
:
278 case SHADER_OPCODE_TXS
:
279 case SHADER_OPCODE_LOD
:
280 case SHADER_OPCODE_TG4
:
281 case SHADER_OPCODE_TG4_OFFSET
:
282 case SHADER_OPCODE_SAMPLEINFO
:
283 return arg
== 1 || arg
== 2;
285 case SHADER_OPCODE_SEND
:
286 return arg
== 0 || arg
== 1;
294 fs_inst::is_payload(unsigned arg
) const
297 case FS_OPCODE_FB_WRITE
:
298 case FS_OPCODE_FB_READ
:
299 case SHADER_OPCODE_URB_WRITE_SIMD8
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
303 case SHADER_OPCODE_URB_READ_SIMD8
:
304 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
305 case VEC4_OPCODE_UNTYPED_ATOMIC
:
306 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
308 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
309 case SHADER_OPCODE_SHADER_TIME_ADD
:
310 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
311 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
312 case SHADER_OPCODE_INTERLOCK
:
313 case SHADER_OPCODE_MEMORY_FENCE
:
314 case SHADER_OPCODE_BARRIER
:
317 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
320 case SHADER_OPCODE_SEND
:
321 return arg
== 2 || arg
== 3;
332 * Returns true if this instruction's sources and destinations cannot
333 * safely be the same register.
335 * In most cases, a register can be written over safely by the same
336 * instruction that is its last use. For a single instruction, the
337 * sources are dereferenced before writing of the destination starts
340 * However, there are a few cases where this can be problematic:
342 * - Virtual opcodes that translate to multiple instructions in the
343 * code generator: if src == dst and one instruction writes the
344 * destination before a later instruction reads the source, then
345 * src will have been clobbered.
347 * - SIMD16 compressed instructions with certain regioning (see below).
349 * The register allocator uses this information to set up conflicts between
350 * GRF sources and the destination.
353 fs_inst::has_source_and_destination_hazard() const
356 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
357 /* Multiple partial writes to the destination */
359 case SHADER_OPCODE_SHUFFLE
:
360 /* This instruction returns an arbitrary channel from the source and
361 * gets split into smaller instructions in the generator. It's possible
362 * that one of the instructions will read from a channel corresponding
363 * to an earlier instruction.
365 case SHADER_OPCODE_SEL_EXEC
:
366 /* This is implemented as
368 * mov(16) g4<1>D 0D { align1 WE_all 1H };
369 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
371 * Because the source is only read in the second instruction, the first
372 * may stomp all over it.
375 case SHADER_OPCODE_QUAD_SWIZZLE
:
377 case BRW_SWIZZLE_XXXX
:
378 case BRW_SWIZZLE_YYYY
:
379 case BRW_SWIZZLE_ZZZZ
:
380 case BRW_SWIZZLE_WWWW
:
381 case BRW_SWIZZLE_XXZZ
:
382 case BRW_SWIZZLE_YYWW
:
383 case BRW_SWIZZLE_XYXY
:
384 case BRW_SWIZZLE_ZWZW
:
385 /* These can be implemented as a single Align1 region on all
386 * platforms, so there's never a hazard between source and
387 * destination. C.f. fs_generator::generate_quad_swizzle().
391 return !is_uniform(src
[0]);
394 /* The SIMD16 compressed instruction
396 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
398 * is actually decoded in hardware as:
400 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
401 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
403 * Which is safe. However, if we have uniform accesses
404 * happening, we get into trouble:
406 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
407 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
409 * Now our destination for the first instruction overwrote the
410 * second instruction's src0, and we get garbage for those 8
411 * pixels. There's a similar issue for the pre-gen6
412 * pixel_x/pixel_y, which are registers of 16-bit values and thus
413 * would get stomped by the first decode as well.
415 if (exec_size
== 16) {
416 for (int i
= 0; i
< sources
; i
++) {
417 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
418 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
419 src
[i
].type
== BRW_REGISTER_TYPE_W
||
420 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
421 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
431 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
433 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
436 fs_reg reg
= this->src
[0];
437 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
440 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
443 for (int i
= 0; i
< this->sources
; i
++) {
444 reg
.type
= this->src
[i
].type
;
445 if (!this->src
[i
].equals(reg
))
448 if (i
< this->header_size
) {
449 reg
.offset
+= REG_SIZE
;
451 reg
= horiz_offset(reg
, this->exec_size
);
459 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
461 if (devinfo
->gen
== 6 && is_math())
464 if (is_send_from_grf())
467 if (!backend_instruction::can_do_source_mods())
474 fs_inst::can_do_cmod()
476 if (!backend_instruction::can_do_cmod())
479 /* The accumulator result appears to get used for the conditional modifier
480 * generation. When negating a UD value, there is a 33rd bit generated for
481 * the sign in the accumulator value, so now you can't check, for example,
482 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
484 for (unsigned i
= 0; i
< sources
; i
++) {
485 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
493 fs_inst::can_change_types() const
495 return dst
.type
== src
[0].type
&&
496 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
497 (opcode
== BRW_OPCODE_MOV
||
498 (opcode
== BRW_OPCODE_SEL
&&
499 dst
.type
== src
[1].type
&&
500 predicate
!= BRW_PREDICATE_NONE
&&
501 !src
[1].abs
&& !src
[1].negate
));
507 memset((void*)this, 0, sizeof(*this));
508 type
= BRW_REGISTER_TYPE_UD
;
512 /** Generic unset register constructor. */
516 this->file
= BAD_FILE
;
519 fs_reg::fs_reg(struct ::brw_reg reg
) :
524 if (this->file
== IMM
&&
525 (this->type
!= BRW_REGISTER_TYPE_V
&&
526 this->type
!= BRW_REGISTER_TYPE_UV
&&
527 this->type
!= BRW_REGISTER_TYPE_VF
)) {
533 fs_reg::equals(const fs_reg
&r
) const
535 return (this->backend_reg::equals(r
) &&
540 fs_reg::negative_equals(const fs_reg
&r
) const
542 return (this->backend_reg::negative_equals(r
) &&
547 fs_reg::is_contiguous() const
553 fs_reg::component_size(unsigned width
) const
555 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
558 return MAX2(width
* stride
, 1) * type_sz(type
);
562 type_size_scalar(const struct glsl_type
*type
, bool bindless
)
564 unsigned int size
, i
;
566 switch (type
->base_type
) {
569 case GLSL_TYPE_FLOAT
:
571 return type
->components();
572 case GLSL_TYPE_UINT16
:
573 case GLSL_TYPE_INT16
:
574 case GLSL_TYPE_FLOAT16
:
575 return DIV_ROUND_UP(type
->components(), 2);
576 case GLSL_TYPE_UINT8
:
578 return DIV_ROUND_UP(type
->components(), 4);
579 case GLSL_TYPE_DOUBLE
:
580 case GLSL_TYPE_UINT64
:
581 case GLSL_TYPE_INT64
:
582 return type
->components() * 2;
583 case GLSL_TYPE_ARRAY
:
584 return type_size_scalar(type
->fields
.array
, bindless
) * type
->length
;
585 case GLSL_TYPE_STRUCT
:
586 case GLSL_TYPE_INTERFACE
:
588 for (i
= 0; i
< type
->length
; i
++) {
589 size
+= type_size_scalar(type
->fields
.structure
[i
].type
, bindless
);
592 case GLSL_TYPE_SAMPLER
:
593 case GLSL_TYPE_IMAGE
:
595 return type
->components() * 2;
596 case GLSL_TYPE_ATOMIC_UINT
:
597 /* Samplers, atomics, and images take up no register space, since
598 * they're baked in at link time.
601 case GLSL_TYPE_SUBROUTINE
:
604 case GLSL_TYPE_ERROR
:
605 case GLSL_TYPE_FUNCTION
:
606 unreachable("not reached");
613 * Create a MOV to read the timestamp register.
615 * The caller is responsible for emitting the MOV. The return value is
616 * the destination of the MOV, with extra parameters set.
619 fs_visitor::get_timestamp(const fs_builder
&bld
)
621 assert(devinfo
->gen
>= 7);
623 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
626 BRW_REGISTER_TYPE_UD
));
628 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
630 /* We want to read the 3 fields we care about even if it's not enabled in
633 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
639 fs_visitor::emit_shader_time_begin()
641 /* We want only the low 32 bits of the timestamp. Since it's running
642 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
643 * which is plenty of time for our purposes. It is identical across the
644 * EUs, but since it's tracking GPU core speed it will increment at a
645 * varying rate as render P-states change.
647 shader_start_time
= component(
648 get_timestamp(bld
.annotate("shader time start")), 0);
652 fs_visitor::emit_shader_time_end()
654 /* Insert our code just before the final SEND with EOT. */
655 exec_node
*end
= this->instructions
.get_tail();
656 assert(end
&& ((fs_inst
*) end
)->eot
);
657 const fs_builder ibld
= bld
.annotate("shader time end")
658 .exec_all().at(NULL
, end
);
659 const fs_reg timestamp
= get_timestamp(ibld
);
661 /* We only use the low 32 bits of the timestamp - see
662 * emit_shader_time_begin()).
664 * We could also check if render P-states have changed (or anything
665 * else that might disrupt timing) by setting smear to 2 and checking if
666 * that field is != 0.
668 const fs_reg shader_end_time
= component(timestamp
, 0);
670 /* Check that there weren't any timestamp reset events (assuming these
671 * were the only two timestamp reads that happened).
673 const fs_reg reset
= component(timestamp
, 2);
674 set_condmod(BRW_CONDITIONAL_Z
,
675 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
676 ibld
.IF(BRW_PREDICATE_NORMAL
);
678 fs_reg start
= shader_start_time
;
680 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
681 BRW_REGISTER_TYPE_UD
),
683 const fs_builder cbld
= ibld
.group(1, 0);
684 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
686 /* If there were no instructions between the two timestamp gets, the diff
687 * is 2 cycles. Remove that overhead, so I can forget about that when
688 * trying to determine the time taken for single instructions.
690 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
691 SHADER_TIME_ADD(cbld
, 0, diff
);
692 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
693 ibld
.emit(BRW_OPCODE_ELSE
);
694 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
695 ibld
.emit(BRW_OPCODE_ENDIF
);
699 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
700 int shader_time_subindex
,
703 int index
= shader_time_index
* 3 + shader_time_subindex
;
704 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
707 if (dispatch_width
== 8)
708 payload
= vgrf(glsl_type::uvec2_type
);
710 payload
= vgrf(glsl_type::uint_type
);
712 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
716 fs_visitor::vfail(const char *format
, va_list va
)
725 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
726 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
728 this->fail_msg
= msg
;
731 fprintf(stderr
, "%s", msg
);
736 fs_visitor::fail(const char *format
, ...)
740 va_start(va
, format
);
746 * Mark this program as impossible to compile with dispatch width greater
749 * During the SIMD8 compile (which happens first), we can detect and flag
750 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
751 * SIMD16+ compile altogether.
753 * During a compile of dispatch width greater than n (if one happens anyway),
754 * this just calls fail().
757 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
759 if (dispatch_width
> n
) {
762 max_dispatch_width
= n
;
763 compiler
->shader_perf_log(log_data
,
764 "Shader dispatch width limited to SIMD%d: %s",
770 * Returns true if the instruction has a flag that means it won't
771 * update an entire destination register.
773 * For example, dead code elimination and live variable analysis want to know
774 * when a write to a variable screens off any preceding values that were in
778 fs_inst::is_partial_write() const
780 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
781 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
782 !this->dst
.is_contiguous() ||
783 this->dst
.offset
% REG_SIZE
!= 0);
787 fs_inst::components_read(unsigned i
) const
789 /* Return zero if the source is not present. */
790 if (src
[i
].file
== BAD_FILE
)
794 case FS_OPCODE_LINTERP
:
800 case FS_OPCODE_PIXEL_X
:
801 case FS_OPCODE_PIXEL_Y
:
805 case FS_OPCODE_FB_WRITE_LOGICAL
:
806 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
807 /* First/second FB write color. */
809 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
813 case SHADER_OPCODE_TEX_LOGICAL
:
814 case SHADER_OPCODE_TXD_LOGICAL
:
815 case SHADER_OPCODE_TXF_LOGICAL
:
816 case SHADER_OPCODE_TXL_LOGICAL
:
817 case SHADER_OPCODE_TXS_LOGICAL
:
818 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
819 case FS_OPCODE_TXB_LOGICAL
:
820 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
821 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
822 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
823 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
824 case SHADER_OPCODE_LOD_LOGICAL
:
825 case SHADER_OPCODE_TG4_LOGICAL
:
826 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
827 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
828 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
829 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
830 /* Texture coordinates. */
831 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
832 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
833 /* Texture derivatives. */
834 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
835 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
836 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
837 /* Texture offset. */
838 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
841 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
846 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
847 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
848 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
849 /* Surface coordinates. */
850 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
851 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
852 /* Surface operation source (ignored for reads). */
853 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
858 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
859 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
860 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
861 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
862 /* Surface coordinates. */
863 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
864 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
865 /* Surface operation source. */
866 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
867 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
871 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
872 assert(src
[2].file
== IMM
);
875 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
876 assert(src
[2].file
== IMM
);
877 return i
== 1 ? src
[2].ud
: 1;
879 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
880 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
881 assert(src
[2].file
== IMM
);
884 const unsigned op
= src
[2].ud
;
899 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
900 assert(src
[2].file
== IMM
);
903 const unsigned op
= src
[2].ud
;
904 return op
== BRW_AOP_FCMPWR
? 2 : 1;
909 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
910 /* Scattered logical opcodes use the following params:
911 * src[0] Surface coordinates
912 * src[1] Surface operation source (ignored for reads)
914 * src[3] IMM with always 1 dimension.
915 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
917 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
918 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
919 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
921 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
922 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
923 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
926 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
927 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
928 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
929 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
930 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
931 /* Surface coordinates. */
932 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
933 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
934 /* Surface operation source. */
935 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
937 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
938 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
943 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
944 return (i
== 0 ? 2 : 1);
946 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
947 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
948 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
949 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
950 /* Surface coordinates. */
951 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
952 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
953 /* Surface operation source. */
954 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
966 fs_inst::size_read(int arg
) const
969 case SHADER_OPCODE_SEND
:
971 return mlen
* REG_SIZE
;
972 } else if (arg
== 3) {
973 return ex_mlen
* REG_SIZE
;
977 case FS_OPCODE_FB_WRITE
:
978 case FS_OPCODE_REP_FB_WRITE
:
981 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
983 return mlen
* REG_SIZE
;
987 case FS_OPCODE_FB_READ
:
988 case SHADER_OPCODE_URB_WRITE_SIMD8
:
989 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
990 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
991 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
992 case SHADER_OPCODE_URB_READ_SIMD8
:
993 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
994 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
995 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
997 return mlen
* REG_SIZE
;
1000 case FS_OPCODE_SET_SAMPLE_ID
:
1005 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
1006 /* The payload is actually stored in src1 */
1008 return mlen
* REG_SIZE
;
1011 case FS_OPCODE_LINTERP
:
1016 case SHADER_OPCODE_LOAD_PAYLOAD
:
1017 if (arg
< this->header_size
)
1021 case CS_OPCODE_CS_TERMINATE
:
1022 case SHADER_OPCODE_BARRIER
:
1025 case SHADER_OPCODE_MOV_INDIRECT
:
1027 assert(src
[2].file
== IMM
);
1033 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
1034 return mlen
* REG_SIZE
;
1038 switch (src
[arg
].file
) {
1041 return components_read(arg
) * type_sz(src
[arg
].type
);
1047 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1049 unreachable("MRF registers are not allowed as sources");
1056 predicate_width(brw_predicate predicate
)
1058 switch (predicate
) {
1059 case BRW_PREDICATE_NONE
: return 1;
1060 case BRW_PREDICATE_NORMAL
: return 1;
1061 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1062 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1063 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1064 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1065 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1066 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1067 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1068 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1069 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1070 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1071 default: unreachable("Unsupported predicate");
1075 /* Return the subset of flag registers that an instruction could
1076 * potentially read or write based on the execution controls and flag
1077 * subregister number of the instruction.
1080 flag_mask(const fs_inst
*inst
, unsigned width
)
1082 assert(util_is_power_of_two_nonzero(width
));
1083 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1085 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1086 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1090 bit_mask(unsigned n
)
1092 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1096 flag_mask(const fs_reg
&r
, unsigned sz
)
1098 if (r
.file
== ARF
) {
1099 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1100 const unsigned end
= start
+ sz
;
1101 return bit_mask(end
) & ~bit_mask(start
);
1109 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1111 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1112 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1113 /* The vertical predication modes combine corresponding bits from
1114 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1116 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1117 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1118 } else if (predicate
) {
1119 return flag_mask(this, predicate_width(predicate
));
1122 for (int i
= 0; i
< sources
; i
++) {
1123 mask
|= flag_mask(src
[i
], size_read(i
));
1130 fs_inst::flags_written() const
1132 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1133 opcode
!= BRW_OPCODE_CSEL
&&
1134 opcode
!= BRW_OPCODE_IF
&&
1135 opcode
!= BRW_OPCODE_WHILE
)) ||
1136 opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1137 opcode
== FS_OPCODE_FB_WRITE
) {
1138 return flag_mask(this, 1);
1140 return flag_mask(dst
, size_written
);
1145 * Returns how many MRFs an FS opcode will write over.
1147 * Note that this is not the 0 or 1 implied writes in an actual gen
1148 * instruction -- the FS opcodes often generate MOVs in addition.
1151 fs_visitor::implied_mrf_writes(const fs_inst
*inst
) const
1153 if (inst
->mlen
== 0)
1156 if (inst
->base_mrf
== -1)
1159 switch (inst
->opcode
) {
1160 case SHADER_OPCODE_RCP
:
1161 case SHADER_OPCODE_RSQ
:
1162 case SHADER_OPCODE_SQRT
:
1163 case SHADER_OPCODE_EXP2
:
1164 case SHADER_OPCODE_LOG2
:
1165 case SHADER_OPCODE_SIN
:
1166 case SHADER_OPCODE_COS
:
1167 return 1 * dispatch_width
/ 8;
1168 case SHADER_OPCODE_POW
:
1169 case SHADER_OPCODE_INT_QUOTIENT
:
1170 case SHADER_OPCODE_INT_REMAINDER
:
1171 return 2 * dispatch_width
/ 8;
1172 case SHADER_OPCODE_TEX
:
1174 case SHADER_OPCODE_TXD
:
1175 case SHADER_OPCODE_TXF
:
1176 case SHADER_OPCODE_TXF_CMS
:
1177 case SHADER_OPCODE_TXF_MCS
:
1178 case SHADER_OPCODE_TG4
:
1179 case SHADER_OPCODE_TG4_OFFSET
:
1180 case SHADER_OPCODE_TXL
:
1181 case SHADER_OPCODE_TXS
:
1182 case SHADER_OPCODE_LOD
:
1183 case SHADER_OPCODE_SAMPLEINFO
:
1185 case FS_OPCODE_FB_WRITE
:
1186 case FS_OPCODE_REP_FB_WRITE
:
1187 return inst
->src
[0].file
== BAD_FILE
? 0 : 2;
1188 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1189 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1191 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1193 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1196 unreachable("not reached");
1201 fs_visitor::vgrf(const glsl_type
*const type
)
1203 int reg_width
= dispatch_width
/ 8;
1205 alloc
.allocate(type_size_scalar(type
, false) * reg_width
),
1206 brw_type_for_base_type(type
));
1209 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1214 this->type
= BRW_REGISTER_TYPE_F
;
1215 this->stride
= (file
== UNIFORM
? 0 : 1);
1218 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1224 this->stride
= (file
== UNIFORM
? 0 : 1);
1227 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1228 * This brings in those uniform definitions
1231 fs_visitor::import_uniforms(fs_visitor
*v
)
1233 this->push_constant_loc
= v
->push_constant_loc
;
1234 this->pull_constant_loc
= v
->pull_constant_loc
;
1235 this->uniforms
= v
->uniforms
;
1236 this->subgroup_id
= v
->subgroup_id
;
1240 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1242 assert(stage
== MESA_SHADER_FRAGMENT
);
1244 /* gl_FragCoord.x */
1245 bld
.MOV(wpos
, this->pixel_x
);
1246 wpos
= offset(wpos
, bld
, 1);
1248 /* gl_FragCoord.y */
1249 bld
.MOV(wpos
, this->pixel_y
);
1250 wpos
= offset(wpos
, bld
, 1);
1252 /* gl_FragCoord.z */
1253 if (devinfo
->gen
>= 6) {
1254 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1256 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1257 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1258 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1260 wpos
= offset(wpos
, bld
, 1);
1262 /* gl_FragCoord.w: Already set up in emit_interpolation */
1263 bld
.MOV(wpos
, this->wpos_w
);
1266 enum brw_barycentric_mode
1267 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1269 /* Barycentric modes don't make sense for flat inputs. */
1270 assert(mode
!= INTERP_MODE_FLAT
);
1274 case nir_intrinsic_load_barycentric_pixel
:
1275 case nir_intrinsic_load_barycentric_at_offset
:
1276 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1278 case nir_intrinsic_load_barycentric_centroid
:
1279 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1281 case nir_intrinsic_load_barycentric_sample
:
1282 case nir_intrinsic_load_barycentric_at_sample
:
1283 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1286 unreachable("invalid intrinsic");
1289 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1292 return (enum brw_barycentric_mode
) bary
;
1296 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1298 static enum brw_barycentric_mode
1299 centroid_to_pixel(enum brw_barycentric_mode bary
)
1301 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1302 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1303 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1307 fs_visitor::emit_frontfacing_interpolation()
1309 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1311 if (devinfo
->gen
>= 6) {
1312 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1313 * a boolean result from this (~0/true or 0/false).
1315 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1316 * this task in only one instruction:
1317 * - a negation source modifier will flip the bit; and
1318 * - a W -> D type conversion will sign extend the bit into the high
1319 * word of the destination.
1321 * An ASR 15 fills the low word of the destination.
1323 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1326 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1328 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1329 * a boolean result from this (1/true or 0/false).
1331 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1332 * the negation source modifier to flip it. Unfortunately the SHR
1333 * instruction only operates on UD (or D with an abs source modifier)
1334 * sources without negation.
1336 * Instead, use ASR (which will give ~0/true or 0/false).
1338 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1341 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1348 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1350 assert(stage
== MESA_SHADER_FRAGMENT
);
1351 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1352 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1354 if (wm_prog_data
->persample_dispatch
) {
1355 /* Convert int_sample_pos to floating point */
1356 bld
.MOV(dst
, int_sample_pos
);
1357 /* Scale to the range [0, 1] */
1358 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1361 /* From ARB_sample_shading specification:
1362 * "When rendering to a non-multisample buffer, or if multisample
1363 * rasterization is disabled, gl_SamplePosition will always be
1366 bld
.MOV(dst
, brw_imm_f(0.5f
));
1371 fs_visitor::emit_samplepos_setup()
1373 assert(devinfo
->gen
>= 6);
1375 const fs_builder abld
= bld
.annotate("compute sample position");
1376 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1378 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1379 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1381 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1382 * mode will be enabled.
1384 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1385 * R31.1:0 Position Offset X/Y for Slot[3:0]
1386 * R31.3:2 Position Offset X/Y for Slot[7:4]
1389 * The X, Y sample positions come in as bytes in thread payload. So, read
1390 * the positions using vstride=16, width=8, hstride=2.
1392 const fs_reg sample_pos_reg
=
1393 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1395 /* Compute gl_SamplePosition.x */
1396 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1397 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1399 /* Compute gl_SamplePosition.y */
1400 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1401 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1406 fs_visitor::emit_sampleid_setup()
1408 assert(stage
== MESA_SHADER_FRAGMENT
);
1409 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1410 assert(devinfo
->gen
>= 6);
1412 const fs_builder abld
= bld
.annotate("compute sample id");
1413 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1415 if (!key
->multisample_fbo
) {
1416 /* As per GL_ARB_sample_shading specification:
1417 * "When rendering to a non-multisample buffer, or if multisample
1418 * rasterization is disabled, gl_SampleID will always be zero."
1420 abld
.MOV(*reg
, brw_imm_d(0));
1421 } else if (devinfo
->gen
>= 8) {
1422 /* Sample ID comes in as 4-bit numbers in g1.0:
1424 * 15:12 Slot 3 SampleID (only used in SIMD16)
1425 * 11:8 Slot 2 SampleID (only used in SIMD16)
1426 * 7:4 Slot 1 SampleID
1427 * 3:0 Slot 0 SampleID
1429 * Each slot corresponds to four channels, so we want to replicate each
1430 * half-byte value to 4 channels in a row:
1432 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1433 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1435 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1436 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1438 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1439 * channels to read the first byte (7:0), and the second group of 8
1440 * channels to read the second byte (15:8). Then, we shift right by
1441 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1442 * values into place. Finally, we AND with 0xf to keep the low nibble.
1444 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1445 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1447 * TODO: These payload bits exist on Gen7 too, but they appear to always
1448 * be zero, so this code fails to work. We should find out why.
1450 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1452 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1453 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1454 hbld
.SHR(offset(tmp
, hbld
, i
),
1455 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1457 brw_imm_v(0x44440000));
1460 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1462 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1463 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1465 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1466 * 8x multisampling, subspan 0 will represent sample N (where N
1467 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1468 * 7. We can find the value of N by looking at R0.0 bits 7:6
1469 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1470 * (since samples are always delivered in pairs). That is, we
1471 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1472 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1473 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1474 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1475 * populating a temporary variable with the sequence (0, 1, 2, 3),
1476 * and then reading from it using vstride=1, width=4, hstride=0.
1477 * These computations hold good for 4x multisampling as well.
1479 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1480 * the first four slots are sample 0 of subspan 0; the next four
1481 * are sample 1 of subspan 0; the third group is sample 0 of
1482 * subspan 1, and finally sample 1 of subspan 1.
1485 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1486 * accomodate 16x MSAA.
1488 abld
.exec_all().group(1, 0)
1489 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1491 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1493 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1494 * can assume 4x MSAA. Disallow it on IVB+
1496 * FINISHME: One day, we could come up with a way to do this that
1497 * actually works on gen7.
1499 if (devinfo
->gen
>= 7)
1500 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1501 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1503 /* This special instruction takes care of setting vstride=1,
1504 * width=4, hstride=0 of t2 during an ADD instruction.
1506 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1513 fs_visitor::emit_samplemaskin_setup()
1515 assert(stage
== MESA_SHADER_FRAGMENT
);
1516 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1517 assert(devinfo
->gen
>= 6);
1519 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1521 fs_reg coverage_mask
=
1522 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1524 if (wm_prog_data
->persample_dispatch
) {
1525 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1526 * and a mask representing which sample is being processed by the
1527 * current shader invocation.
1529 * From the OES_sample_variables specification:
1530 * "When per-sample shading is active due to the use of a fragment input
1531 * qualified by "sample" or due to the use of the gl_SampleID or
1532 * gl_SamplePosition variables, only the bit for the current sample is
1533 * set in gl_SampleMaskIn."
1535 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1537 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1538 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1540 fs_reg one
= vgrf(glsl_type::int_type
);
1541 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1542 abld
.MOV(one
, brw_imm_d(1));
1543 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1544 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1546 /* In per-pixel mode, the coverage mask is sufficient. */
1547 *reg
= coverage_mask
;
1553 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1555 if (!src
.abs
&& !src
.negate
)
1558 fs_reg temp
= bld
.vgrf(src
.type
);
1565 fs_visitor::emit_discard_jump()
1567 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1569 /* For performance, after a discard, jump to the end of the
1570 * shader if all relevant channels have been discarded.
1572 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1573 discard_jump
->flag_subreg
= 1;
1575 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1576 discard_jump
->predicate_inverse
= true;
1580 fs_visitor::emit_gs_thread_end()
1582 assert(stage
== MESA_SHADER_GEOMETRY
);
1584 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1586 if (gs_compile
->control_data_header_size_bits
> 0) {
1587 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1590 const fs_builder abld
= bld
.annotate("thread end");
1593 if (gs_prog_data
->static_vertex_count
!= -1) {
1594 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1595 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1596 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1597 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1598 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1601 /* Delete now dead instructions. */
1602 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1608 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1612 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1613 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1614 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1617 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1618 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1619 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1620 sources
[1] = this->final_gs_vertex_count
;
1621 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1622 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1630 fs_visitor::assign_curb_setup()
1632 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1634 unsigned ubo_push_length
= 0;
1635 unsigned ubo_push_start
[4];
1636 for (int i
= 0; i
< 4; i
++) {
1637 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1638 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1641 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1643 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1644 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1645 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1646 if (inst
->src
[i
].file
== UNIFORM
) {
1647 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1649 if (inst
->src
[i
].nr
>= UBO_START
) {
1650 /* constant_nr is in 32-bit units, the rest are in bytes */
1651 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1652 inst
->src
[i
].offset
/ 4;
1653 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1654 constant_nr
= push_constant_loc
[uniform_nr
];
1656 /* Section 5.11 of the OpenGL 4.1 spec says:
1657 * "Out-of-bounds reads return undefined values, which include
1658 * values from other variables of the active program or zero."
1659 * Just return the first push constant.
1664 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1667 brw_reg
.abs
= inst
->src
[i
].abs
;
1668 brw_reg
.negate
= inst
->src
[i
].negate
;
1670 assert(inst
->src
[i
].stride
== 0);
1671 inst
->src
[i
] = byte_offset(
1672 retype(brw_reg
, inst
->src
[i
].type
),
1673 inst
->src
[i
].offset
% 4);
1678 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1679 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1683 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1684 const struct brw_wm_prog_key
*key
,
1685 struct brw_wm_prog_data
*prog_data
,
1686 const nir_shader
*nir
)
1688 memset(prog_data
->urb_setup
, -1,
1689 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1692 /* Figure out where each of the incoming setup attributes lands. */
1693 if (devinfo
->gen
>= 6) {
1694 if (util_bitcount64(nir
->info
.inputs_read
&
1695 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1696 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1697 * first 16 varying inputs, so we can put them wherever we want.
1698 * Just put them in order.
1700 * This is useful because it means that (a) inputs not used by the
1701 * fragment shader won't take up valuable register space, and (b) we
1702 * won't have to recompile the fragment shader if it gets paired with
1703 * a different vertex (or geometry) shader.
1705 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1706 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1707 BITFIELD64_BIT(i
)) {
1708 prog_data
->urb_setup
[i
] = urb_next
++;
1712 /* We have enough input varyings that the SF/SBE pipeline stage can't
1713 * arbitrarily rearrange them to suit our whim; we have to put them
1714 * in an order that matches the output of the previous pipeline stage
1715 * (geometry or vertex shader).
1717 struct brw_vue_map prev_stage_vue_map
;
1718 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1719 key
->input_slots_valid
,
1720 nir
->info
.separate_shader
);
1723 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1724 &prev_stage_vue_map
);
1726 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1727 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1729 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1730 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1731 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1732 BITFIELD64_BIT(varying
))) {
1733 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1736 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1739 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1740 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1741 /* Point size is packed into the header, not as a general attribute */
1742 if (i
== VARYING_SLOT_PSIZ
)
1745 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1746 /* The back color slot is skipped when the front color is
1747 * also written to. In addition, some slots can be
1748 * written in the vertex shader and not read in the
1749 * fragment shader. So the register number must always be
1750 * incremented, mapped or not.
1752 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1753 prog_data
->urb_setup
[i
] = urb_next
;
1759 * It's a FS only attribute, and we did interpolation for this attribute
1760 * in SF thread. So, count it here, too.
1762 * See compile_sf_prog() for more info.
1764 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1765 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1768 prog_data
->num_varying_inputs
= urb_next
;
1772 fs_visitor::assign_urb_setup()
1774 assert(stage
== MESA_SHADER_FRAGMENT
);
1775 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1777 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1779 /* Offset all the urb_setup[] index by the actual position of the
1780 * setup regs, now that the location of the constants has been chosen.
1782 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1783 for (int i
= 0; i
< inst
->sources
; i
++) {
1784 if (inst
->src
[i
].file
== ATTR
) {
1785 /* ATTR regs in the FS are in units of logical scalar inputs each
1786 * of which consumes half of a GRF register.
1788 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1789 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1790 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1791 inst
->src
[i
].offset
;
1792 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1793 1 : MIN2(inst
->exec_size
, 8);
1794 struct brw_reg reg
= stride(
1795 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1797 width
* inst
->src
[i
].stride
,
1798 width
, inst
->src
[i
].stride
);
1799 reg
.abs
= inst
->src
[i
].abs
;
1800 reg
.negate
= inst
->src
[i
].negate
;
1806 /* Each attribute is 4 setup channels, each of which is half a reg. */
1807 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1811 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1813 for (int i
= 0; i
< inst
->sources
; i
++) {
1814 if (inst
->src
[i
].file
== ATTR
) {
1815 int grf
= payload
.num_regs
+
1816 prog_data
->curb_read_length
+
1818 inst
->src
[i
].offset
/ REG_SIZE
;
1820 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1822 * VertStride must be used to cross GRF register boundaries. This
1823 * rule implies that elements within a 'Width' cannot cross GRF
1826 * So, for registers that are large enough, we have to split the exec
1827 * size in two and trust the compression state to sort it out.
1829 unsigned total_size
= inst
->exec_size
*
1830 inst
->src
[i
].stride
*
1831 type_sz(inst
->src
[i
].type
);
1833 assert(total_size
<= 2 * REG_SIZE
);
1834 const unsigned exec_size
=
1835 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1837 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1838 struct brw_reg reg
=
1839 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1840 inst
->src
[i
].offset
% REG_SIZE
),
1841 exec_size
* inst
->src
[i
].stride
,
1842 width
, inst
->src
[i
].stride
);
1843 reg
.abs
= inst
->src
[i
].abs
;
1844 reg
.negate
= inst
->src
[i
].negate
;
1852 fs_visitor::assign_vs_urb_setup()
1854 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1856 assert(stage
== MESA_SHADER_VERTEX
);
1858 /* Each attribute is 4 regs. */
1859 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1861 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1863 /* Rewrite all ATTR file references to the hw grf that they land in. */
1864 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1865 convert_attr_sources_to_hw_regs(inst
);
1870 fs_visitor::assign_tcs_urb_setup()
1872 assert(stage
== MESA_SHADER_TESS_CTRL
);
1874 /* Rewrite all ATTR file references to HW_REGs. */
1875 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1876 convert_attr_sources_to_hw_regs(inst
);
1881 fs_visitor::assign_tes_urb_setup()
1883 assert(stage
== MESA_SHADER_TESS_EVAL
);
1885 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1887 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1889 /* Rewrite all ATTR file references to HW_REGs. */
1890 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1891 convert_attr_sources_to_hw_regs(inst
);
1896 fs_visitor::assign_gs_urb_setup()
1898 assert(stage
== MESA_SHADER_GEOMETRY
);
1900 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1902 first_non_payload_grf
+=
1903 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1905 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1906 /* Rewrite all ATTR file references to GRFs. */
1907 convert_attr_sources_to_hw_regs(inst
);
1913 * Split large virtual GRFs into separate components if we can.
1915 * This is mostly duplicated with what brw_fs_vector_splitting does,
1916 * but that's really conservative because it's afraid of doing
1917 * splitting that doesn't result in real progress after the rest of
1918 * the optimization phases, which would cause infinite looping in
1919 * optimization. We can do it once here, safely. This also has the
1920 * opportunity to split interpolated values, or maybe even uniforms,
1921 * which we don't have at the IR level.
1923 * We want to split, because virtual GRFs are what we register
1924 * allocate and spill (due to contiguousness requirements for some
1925 * instructions), and they're what we naturally generate in the
1926 * codegen process, but most virtual GRFs don't actually need to be
1927 * contiguous sets of GRFs. If we split, we'll end up with reduced
1928 * live intervals and better dead code elimination and coalescing.
1931 fs_visitor::split_virtual_grfs()
1933 /* Compact the register file so we eliminate dead vgrfs. This
1934 * only defines split points for live registers, so if we have
1935 * too large dead registers they will hit assertions later.
1937 compact_virtual_grfs();
1939 int num_vars
= this->alloc
.count
;
1941 /* Count the total number of registers */
1943 int vgrf_to_reg
[num_vars
];
1944 for (int i
= 0; i
< num_vars
; i
++) {
1945 vgrf_to_reg
[i
] = reg_count
;
1946 reg_count
+= alloc
.sizes
[i
];
1949 /* An array of "split points". For each register slot, this indicates
1950 * if this slot can be separated from the previous slot. Every time an
1951 * instruction uses multiple elements of a register (as a source or
1952 * destination), we mark the used slots as inseparable. Then we go
1953 * through and split the registers into the smallest pieces we can.
1955 bool *split_points
= new bool[reg_count
];
1956 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1958 /* Mark all used registers as fully splittable */
1959 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1960 if (inst
->dst
.file
== VGRF
) {
1961 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1962 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1963 split_points
[reg
+ j
] = true;
1966 for (int i
= 0; i
< inst
->sources
; i
++) {
1967 if (inst
->src
[i
].file
== VGRF
) {
1968 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1969 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1970 split_points
[reg
+ j
] = true;
1975 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1976 /* We fix up undef instructions later */
1977 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
1978 /* UNDEF instructions are currently only used to undef entire
1979 * registers. We need this invariant later when we split them.
1981 assert(inst
->dst
.file
== VGRF
);
1982 assert(inst
->dst
.offset
== 0);
1983 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
1987 if (inst
->dst
.file
== VGRF
) {
1988 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1989 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1990 split_points
[reg
+ j
] = false;
1992 for (int i
= 0; i
< inst
->sources
; i
++) {
1993 if (inst
->src
[i
].file
== VGRF
) {
1994 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1995 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1996 split_points
[reg
+ j
] = false;
2001 int *new_virtual_grf
= new int[reg_count
];
2002 int *new_reg_offset
= new int[reg_count
];
2005 for (int i
= 0; i
< num_vars
; i
++) {
2006 /* The first one should always be 0 as a quick sanity check. */
2007 assert(split_points
[reg
] == false);
2010 new_reg_offset
[reg
] = 0;
2015 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2016 /* If this is a split point, reset the offset to 0 and allocate a
2017 * new virtual GRF for the previous offset many registers
2019 if (split_points
[reg
]) {
2020 assert(offset
<= MAX_VGRF_SIZE
);
2021 int grf
= alloc
.allocate(offset
);
2022 for (int k
= reg
- offset
; k
< reg
; k
++)
2023 new_virtual_grf
[k
] = grf
;
2026 new_reg_offset
[reg
] = offset
;
2031 /* The last one gets the original register number */
2032 assert(offset
<= MAX_VGRF_SIZE
);
2033 alloc
.sizes
[i
] = offset
;
2034 for (int k
= reg
- offset
; k
< reg
; k
++)
2035 new_virtual_grf
[k
] = i
;
2037 assert(reg
== reg_count
);
2039 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2040 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2041 const fs_builder
ibld(this, block
, inst
);
2042 assert(inst
->size_written
% REG_SIZE
== 0);
2043 unsigned reg_offset
= 0;
2044 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2045 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2046 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2047 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2049 inst
->remove(block
);
2053 if (inst
->dst
.file
== VGRF
) {
2054 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2055 inst
->dst
.nr
= new_virtual_grf
[reg
];
2056 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2057 inst
->dst
.offset
% REG_SIZE
;
2058 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2060 for (int i
= 0; i
< inst
->sources
; i
++) {
2061 if (inst
->src
[i
].file
== VGRF
) {
2062 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2063 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2064 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2065 inst
->src
[i
].offset
% REG_SIZE
;
2066 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2070 invalidate_live_intervals();
2072 delete[] split_points
;
2073 delete[] new_virtual_grf
;
2074 delete[] new_reg_offset
;
2078 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2080 * During code generation, we create tons of temporary variables, many of
2081 * which get immediately killed and are never used again. Yet, in later
2082 * optimization and analysis passes, such as compute_live_intervals, we need
2083 * to loop over all the virtual GRFs. Compacting them can save a lot of
2087 fs_visitor::compact_virtual_grfs()
2089 bool progress
= false;
2090 int *remap_table
= new int[this->alloc
.count
];
2091 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2093 /* Mark which virtual GRFs are used. */
2094 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2095 if (inst
->dst
.file
== VGRF
)
2096 remap_table
[inst
->dst
.nr
] = 0;
2098 for (int i
= 0; i
< inst
->sources
; i
++) {
2099 if (inst
->src
[i
].file
== VGRF
)
2100 remap_table
[inst
->src
[i
].nr
] = 0;
2104 /* Compact the GRF arrays. */
2106 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2107 if (remap_table
[i
] == -1) {
2108 /* We just found an unused register. This means that we are
2109 * actually going to compact something.
2113 remap_table
[i
] = new_index
;
2114 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2115 invalidate_live_intervals();
2120 this->alloc
.count
= new_index
;
2122 /* Patch all the instructions to use the newly renumbered registers */
2123 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2124 if (inst
->dst
.file
== VGRF
)
2125 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2127 for (int i
= 0; i
< inst
->sources
; i
++) {
2128 if (inst
->src
[i
].file
== VGRF
)
2129 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2133 /* Patch all the references to delta_xy, since they're used in register
2134 * allocation. If they're unused, switch them to BAD_FILE so we don't
2135 * think some random VGRF is delta_xy.
2137 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2138 if (delta_xy
[i
].file
== VGRF
) {
2139 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2140 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2142 delta_xy
[i
].file
= BAD_FILE
;
2147 delete[] remap_table
;
2153 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2155 if (prog_data
->nr_params
== 0)
2158 /* The local thread id is always the last parameter in the list */
2159 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2160 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2161 return prog_data
->nr_params
- 1;
2167 * Struct for handling complex alignments.
2169 * A complex alignment is stored as multiplier and an offset. A value is
2170 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2171 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2174 * N | cplx_align_apply({8, 2}, N)
2175 * ----+-----------------------------
2189 #define CPLX_ALIGN_MAX_MUL 8
2192 cplx_align_assert_sane(struct cplx_align a
)
2194 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2195 assert(a
.offset
< a
.mul
);
2199 * Combines two alignments to produce a least multiple of sorts.
2201 * The returned alignment is the smallest (in terms of multiplier) such that
2202 * anything aligned to both a and b will be aligned to the new alignment.
2203 * This function will assert-fail if a and b are not compatible, i.e. if the
2204 * offset parameters are such that no common alignment is possible.
2206 static struct cplx_align
2207 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2209 cplx_align_assert_sane(a
);
2210 cplx_align_assert_sane(b
);
2212 /* Assert that the alignments agree. */
2213 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2215 return a
.mul
> b
.mul
? a
: b
;
2219 * Apply a complex alignment
2221 * This function will return the smallest number greater than or equal to
2222 * offset that is aligned to align.
2225 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2227 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2230 #define UNIFORM_SLOT_SIZE 4
2232 struct uniform_slot_info
{
2233 /** True if the given uniform slot is live */
2236 /** True if this slot and the next slot must remain contiguous */
2237 unsigned contiguous
:1;
2239 struct cplx_align align
;
2243 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2244 unsigned num_slots
, unsigned alignment
)
2246 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2247 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2249 /* We can't align a slot to anything less than the slot size */
2250 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2252 struct cplx_align align
= {alignment
, 0};
2253 cplx_align_assert_sane(align
);
2255 for (unsigned i
= 0; i
< num_slots
; i
++) {
2256 slots
[i
].is_live
= true;
2257 if (i
< num_slots
- 1)
2258 slots
[i
].contiguous
= true;
2260 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2261 if (slots
[i
].align
.mul
== 0) {
2262 slots
[i
].align
= align
;
2264 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2270 * Assign UNIFORM file registers to either push constants or pull constants.
2272 * We allow a fragment shader to have more than the specified minimum
2273 * maximum number of fragment shader uniform components (64). If
2274 * there are too many of these, they'd fill up all of register space.
2275 * So, this will push some of them out to the pull constant buffer and
2276 * update the program to load them.
2279 fs_visitor::assign_constant_locations()
2281 /* Only the first compile gets to decide on locations. */
2282 if (push_constant_loc
) {
2283 assert(pull_constant_loc
);
2287 struct uniform_slot_info slots
[uniforms
];
2288 memset(slots
, 0, sizeof(slots
));
2290 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2291 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2292 if (inst
->src
[i
].file
!= UNIFORM
)
2295 /* NIR tightly packs things so the uniform number might not be
2296 * aligned (if we have a double right after a float, for instance).
2297 * This is fine because the process of re-arranging them will ensure
2298 * that things are properly aligned. The offset into that uniform,
2299 * however, must be aligned.
2301 * In Vulkan, we have explicit offsets but everything is crammed
2302 * into a single "variable" so inst->src[i].nr will always be 0.
2303 * Everything will be properly aligned relative to that one base.
2305 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2307 unsigned u
= inst
->src
[i
].nr
+
2308 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2313 unsigned slots_read
;
2314 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2315 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2317 unsigned bytes_read
= inst
->components_read(i
) *
2318 type_sz(inst
->src
[i
].type
);
2319 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2322 assert(u
+ slots_read
<= uniforms
);
2323 mark_uniform_slots_read(&slots
[u
], slots_read
,
2324 type_sz(inst
->src
[i
].type
));
2328 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2330 /* Only allow 16 registers (128 uniform components) as push constants.
2332 * Just demote the end of the list. We could probably do better
2333 * here, demoting things that are rarely used in the program first.
2335 * If changing this value, note the limitation about total_regs in
2338 unsigned int max_push_components
= 16 * 8;
2339 if (subgroup_id_index
>= 0)
2340 max_push_components
--; /* Save a slot for the thread ID */
2342 /* We push small arrays, but no bigger than 16 floats. This is big enough
2343 * for a vec4 but hopefully not large enough to push out other stuff. We
2344 * should probably use a better heuristic at some point.
2346 const unsigned int max_chunk_size
= 16;
2348 unsigned int num_push_constants
= 0;
2349 unsigned int num_pull_constants
= 0;
2351 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2352 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2354 /* Default to -1 meaning no location */
2355 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2356 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2358 int chunk_start
= -1;
2359 struct cplx_align align
;
2360 for (unsigned u
= 0; u
< uniforms
; u
++) {
2361 if (!slots
[u
].is_live
) {
2362 assert(chunk_start
== -1);
2366 /* Skip subgroup_id_index to put it in the last push register. */
2367 if (subgroup_id_index
== (int)u
)
2370 if (chunk_start
== -1) {
2372 align
= slots
[u
].align
;
2374 /* Offset into the chunk */
2375 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2377 /* Shift the slot alignment down by the chunk offset so it is
2378 * comparable with the base chunk alignment.
2380 struct cplx_align slot_align
= slots
[u
].align
;
2382 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2384 align
= cplx_align_combine(align
, slot_align
);
2387 /* Sanity check the alignment */
2388 cplx_align_assert_sane(align
);
2390 if (slots
[u
].contiguous
)
2393 /* Adjust the alignment to be in terms of slots, not bytes */
2394 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2395 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2396 align
.mul
/= UNIFORM_SLOT_SIZE
;
2397 align
.offset
/= UNIFORM_SLOT_SIZE
;
2399 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2400 unsigned chunk_size
= u
- chunk_start
+ 1;
2401 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2402 (chunk_size
< max_chunk_size
&&
2403 push_start_align
+ chunk_size
<= max_push_components
)) {
2404 /* Align up the number of push constants */
2405 num_push_constants
= push_start_align
;
2406 for (unsigned i
= 0; i
< chunk_size
; i
++)
2407 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2409 /* We need to pull this one */
2410 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2411 for (unsigned i
= 0; i
< chunk_size
; i
++)
2412 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2415 /* Reset the chunk and start again */
2419 /* Add the CS local thread ID uniform at the end of the push constants */
2420 if (subgroup_id_index
>= 0)
2421 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2423 /* As the uniforms are going to be reordered, stash the old array and
2424 * create two new arrays for push/pull params.
2426 uint32_t *param
= stage_prog_data
->param
;
2427 stage_prog_data
->nr_params
= num_push_constants
;
2428 if (num_push_constants
) {
2429 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2430 num_push_constants
);
2432 stage_prog_data
->param
= NULL
;
2434 assert(stage_prog_data
->nr_pull_params
== 0);
2435 assert(stage_prog_data
->pull_param
== NULL
);
2436 if (num_pull_constants
> 0) {
2437 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2438 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2439 num_pull_constants
);
2442 /* Now that we know how many regular uniforms we'll push, reduce the
2443 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2445 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2446 for (int i
= 0; i
< 4; i
++) {
2447 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2449 if (push_length
+ range
->length
> 64)
2450 range
->length
= 64 - push_length
;
2452 push_length
+= range
->length
;
2454 assert(push_length
<= 64);
2456 /* Up until now, the param[] array has been indexed by reg + offset
2457 * of UNIFORM registers. Move pull constants into pull_param[] and
2458 * condense param[] to only contain the uniforms we chose to push.
2460 * NOTE: Because we are condensing the params[] array, we know that
2461 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2462 * having to make a copy.
2464 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2465 uint32_t value
= param
[i
];
2466 if (pull_constant_loc
[i
] != -1) {
2467 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2468 } else if (push_constant_loc
[i
] != -1) {
2469 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2476 fs_visitor::get_pull_locs(const fs_reg
&src
,
2477 unsigned *out_surf_index
,
2478 unsigned *out_pull_index
)
2480 assert(src
.file
== UNIFORM
);
2482 if (src
.nr
>= UBO_START
) {
2483 const struct brw_ubo_range
*range
=
2484 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2486 /* If this access is in our (reduced) range, use the push data. */
2487 if (src
.offset
/ 32 < range
->length
)
2490 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2491 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2493 prog_data
->has_ubo_pull
= true;
2497 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2499 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2500 /* A regular uniform push constant */
2501 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2502 *out_pull_index
= pull_constant_loc
[location
];
2504 prog_data
->has_ubo_pull
= true;
2512 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2513 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2516 fs_visitor::lower_constant_loads()
2518 unsigned index
, pull_index
;
2520 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2521 /* Set up the annotation tracking for new generated instructions. */
2522 const fs_builder
ibld(this, block
, inst
);
2524 for (int i
= 0; i
< inst
->sources
; i
++) {
2525 if (inst
->src
[i
].file
!= UNIFORM
)
2528 /* We'll handle this case later */
2529 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2532 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2535 assert(inst
->src
[i
].stride
== 0);
2537 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2538 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2539 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2540 const unsigned base
= pull_index
* 4;
2542 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2543 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2545 /* Rewrite the instruction to use the temporary VGRF. */
2546 inst
->src
[i
].file
= VGRF
;
2547 inst
->src
[i
].nr
= dst
.nr
;
2548 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2549 inst
->src
[i
].offset
% 4;
2552 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2553 inst
->src
[0].file
== UNIFORM
) {
2555 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2558 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2562 inst
->remove(block
);
2565 invalidate_live_intervals();
2569 fs_visitor::opt_algebraic()
2571 bool progress
= false;
2573 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2574 switch (inst
->opcode
) {
2575 case BRW_OPCODE_MOV
:
2576 if (!devinfo
->has_64bit_types
&&
2577 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2578 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2579 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2580 assert(inst
->dst
.type
== inst
->src
[0].type
);
2581 assert(!inst
->saturate
);
2582 assert(!inst
->src
[0].abs
);
2583 assert(!inst
->src
[0].negate
);
2584 const brw::fs_builder
ibld(this, block
, inst
);
2586 if (inst
->src
[0].file
== IMM
) {
2587 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2588 brw_imm_ud(inst
->src
[0].u64
>> 32));
2589 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2590 brw_imm_ud(inst
->src
[0].u64
));
2592 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2593 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2594 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2595 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2598 inst
->remove(block
);
2602 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2603 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2604 inst
->dst
.is_null() &&
2605 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2606 inst
->src
[0].abs
= false;
2607 inst
->src
[0].negate
= false;
2612 if (inst
->src
[0].file
!= IMM
)
2615 if (inst
->saturate
) {
2616 /* Full mixed-type saturates don't happen. However, we can end up
2619 * mov.sat(8) g21<1>DF -1F
2621 * Other mixed-size-but-same-base-type cases may also be possible.
2623 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2624 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2625 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2626 assert(!"unimplemented: saturate mixed types");
2628 if (brw_saturate_immediate(inst
->src
[0].type
,
2629 &inst
->src
[0].as_brw_reg())) {
2630 inst
->saturate
= false;
2636 case BRW_OPCODE_MUL
:
2637 if (inst
->src
[1].file
!= IMM
)
2641 if (inst
->src
[1].is_one()) {
2642 inst
->opcode
= BRW_OPCODE_MOV
;
2643 inst
->src
[1] = reg_undef
;
2649 if (inst
->src
[1].is_negative_one()) {
2650 inst
->opcode
= BRW_OPCODE_MOV
;
2651 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2652 inst
->src
[1] = reg_undef
;
2657 if (inst
->src
[0].file
== IMM
) {
2658 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2659 inst
->opcode
= BRW_OPCODE_MOV
;
2660 inst
->src
[0].f
*= inst
->src
[1].f
;
2661 inst
->src
[1] = reg_undef
;
2666 case BRW_OPCODE_ADD
:
2667 if (inst
->src
[1].file
!= IMM
)
2670 if (inst
->src
[0].file
== IMM
) {
2671 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2672 inst
->opcode
= BRW_OPCODE_MOV
;
2673 inst
->src
[0].f
+= inst
->src
[1].f
;
2674 inst
->src
[1] = reg_undef
;
2680 if (inst
->src
[0].equals(inst
->src
[1]) ||
2681 inst
->src
[1].is_zero()) {
2682 /* On Gen8+, the OR instruction can have a source modifier that
2683 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2684 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2686 if (inst
->src
[0].negate
) {
2687 inst
->opcode
= BRW_OPCODE_NOT
;
2688 inst
->src
[0].negate
= false;
2690 inst
->opcode
= BRW_OPCODE_MOV
;
2692 inst
->src
[1] = reg_undef
;
2697 case BRW_OPCODE_CMP
:
2698 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2699 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2700 inst
->src
[1].is_zero() &&
2701 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2702 inst
->src
[0].abs
= false;
2703 inst
->src
[0].negate
= false;
2708 case BRW_OPCODE_SEL
:
2709 if (!devinfo
->has_64bit_types
&&
2710 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2711 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2712 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2713 assert(inst
->dst
.type
== inst
->src
[0].type
);
2714 assert(!inst
->saturate
);
2715 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2716 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2717 const brw::fs_builder
ibld(this, block
, inst
);
2719 set_predicate(inst
->predicate
,
2720 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2721 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2722 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2723 set_predicate(inst
->predicate
,
2724 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2725 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2726 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2728 inst
->remove(block
);
2731 if (inst
->src
[0].equals(inst
->src
[1])) {
2732 inst
->opcode
= BRW_OPCODE_MOV
;
2733 inst
->src
[1] = reg_undef
;
2734 inst
->predicate
= BRW_PREDICATE_NONE
;
2735 inst
->predicate_inverse
= false;
2737 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2738 switch (inst
->conditional_mod
) {
2739 case BRW_CONDITIONAL_LE
:
2740 case BRW_CONDITIONAL_L
:
2741 switch (inst
->src
[1].type
) {
2742 case BRW_REGISTER_TYPE_F
:
2743 if (inst
->src
[1].f
>= 1.0f
) {
2744 inst
->opcode
= BRW_OPCODE_MOV
;
2745 inst
->src
[1] = reg_undef
;
2746 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2754 case BRW_CONDITIONAL_GE
:
2755 case BRW_CONDITIONAL_G
:
2756 switch (inst
->src
[1].type
) {
2757 case BRW_REGISTER_TYPE_F
:
2758 if (inst
->src
[1].f
<= 0.0f
) {
2759 inst
->opcode
= BRW_OPCODE_MOV
;
2760 inst
->src
[1] = reg_undef
;
2761 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2773 case BRW_OPCODE_MAD
:
2774 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2775 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2776 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2778 if (inst
->src
[1].is_one()) {
2779 inst
->opcode
= BRW_OPCODE_ADD
;
2780 inst
->src
[1] = inst
->src
[2];
2781 inst
->src
[2] = reg_undef
;
2783 } else if (inst
->src
[2].is_one()) {
2784 inst
->opcode
= BRW_OPCODE_ADD
;
2785 inst
->src
[2] = reg_undef
;
2789 case SHADER_OPCODE_BROADCAST
:
2790 if (is_uniform(inst
->src
[0])) {
2791 inst
->opcode
= BRW_OPCODE_MOV
;
2793 inst
->force_writemask_all
= true;
2795 } else if (inst
->src
[1].file
== IMM
) {
2796 inst
->opcode
= BRW_OPCODE_MOV
;
2797 /* It's possible that the selected component will be too large and
2798 * overflow the register. This can happen if someone does a
2799 * readInvocation() from GLSL or SPIR-V and provides an OOB
2800 * invocationIndex. If this happens and we some how manage
2801 * to constant fold it in and get here, then component() may cause
2802 * us to start reading outside of the VGRF which will lead to an
2803 * assert later. Instead, just let it wrap around if it goes over
2806 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2807 inst
->src
[0] = component(inst
->src
[0], comp
);
2809 inst
->force_writemask_all
= true;
2814 case SHADER_OPCODE_SHUFFLE
:
2815 if (is_uniform(inst
->src
[0])) {
2816 inst
->opcode
= BRW_OPCODE_MOV
;
2819 } else if (inst
->src
[1].file
== IMM
) {
2820 inst
->opcode
= BRW_OPCODE_MOV
;
2821 inst
->src
[0] = component(inst
->src
[0],
2832 /* Swap if src[0] is immediate. */
2833 if (progress
&& inst
->is_commutative()) {
2834 if (inst
->src
[0].file
== IMM
) {
2835 fs_reg tmp
= inst
->src
[1];
2836 inst
->src
[1] = inst
->src
[0];
2845 * Optimize sample messages that have constant zero values for the trailing
2846 * texture coordinates. We can just reduce the message length for these
2847 * instructions instead of reserving a register for it. Trailing parameters
2848 * that aren't sent default to zero anyway. This will cause the dead code
2849 * eliminator to remove the MOV instruction that would otherwise be emitted to
2850 * set up the zero value.
2853 fs_visitor::opt_zero_samples()
2855 /* Gen4 infers the texturing opcode based on the message length so we can't
2858 if (devinfo
->gen
< 5)
2861 bool progress
= false;
2863 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2864 if (!inst
->is_tex())
2867 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2869 if (load_payload
->is_head_sentinel() ||
2870 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2873 /* We don't want to remove the message header or the first parameter.
2874 * Removing the first parameter is not allowed, see the Haswell PRM
2875 * volume 7, page 149:
2877 * "Parameter 0 is required except for the sampleinfo message, which
2878 * has no parameter 0"
2880 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2881 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2882 (inst
->exec_size
/ 8) +
2883 inst
->header_size
- 1].is_zero()) {
2884 inst
->mlen
-= inst
->exec_size
/ 8;
2890 invalidate_live_intervals();
2896 * Optimize sample messages which are followed by the final RT write.
2898 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2899 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2900 * final texturing results copied to the framebuffer write payload and modify
2901 * them to write to the framebuffer directly.
2904 fs_visitor::opt_sampler_eot()
2906 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2908 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2911 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2914 /* FINISHME: It should be possible to implement this optimization when there
2915 * are multiple drawbuffers.
2917 if (key
->nr_color_regions
!= 1)
2920 /* Requires emitting a bunch of saturating MOV instructions during logical
2921 * send lowering to clamp the color payload, which the sampler unit isn't
2922 * going to do for us.
2924 if (key
->clamp_fragment_color
)
2927 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2928 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2929 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2930 assert(fb_write
->eot
);
2931 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2933 /* There wasn't one; nothing to do. */
2934 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2937 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2939 /* 3D Sampler » Messages » Message Format
2941 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2942 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2944 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2945 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2946 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2947 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2948 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2949 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2950 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2951 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2954 /* XXX - This shouldn't be necessary. */
2955 if (tex_inst
->prev
->is_head_sentinel())
2958 /* Check that the FB write sources are fully initialized by the single
2959 * texturing instruction.
2961 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2962 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2963 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2964 fb_write
->size_read(i
) != tex_inst
->size_written
)
2966 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2967 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2972 assert(!tex_inst
->eot
); /* We can't get here twice */
2973 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2975 const fs_builder
ibld(this, block
, tex_inst
);
2977 tex_inst
->offset
|= fb_write
->target
<< 24;
2978 tex_inst
->eot
= true;
2979 tex_inst
->dst
= ibld
.null_reg_ud();
2980 tex_inst
->size_written
= 0;
2981 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2983 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2984 * flag and submit a header together with the sampler message as required
2987 invalidate_live_intervals();
2992 fs_visitor::opt_register_renaming()
2994 bool progress
= false;
2997 unsigned remap
[alloc
.count
];
2998 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
3000 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3001 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
3003 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
3004 inst
->opcode
== BRW_OPCODE_WHILE
) {
3008 /* Rewrite instruction sources. */
3009 for (int i
= 0; i
< inst
->sources
; i
++) {
3010 if (inst
->src
[i
].file
== VGRF
&&
3011 remap
[inst
->src
[i
].nr
] != ~0u &&
3012 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
3013 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
3018 const unsigned dst
= inst
->dst
.nr
;
3021 inst
->dst
.file
== VGRF
&&
3022 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
3023 !inst
->is_partial_write()) {
3024 if (remap
[dst
] == ~0u) {
3027 remap
[dst
] = alloc
.allocate(regs_written(inst
));
3028 inst
->dst
.nr
= remap
[dst
];
3031 } else if (inst
->dst
.file
== VGRF
&&
3032 remap
[dst
] != ~0u &&
3033 remap
[dst
] != dst
) {
3034 inst
->dst
.nr
= remap
[dst
];
3040 invalidate_live_intervals();
3042 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3043 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3044 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3053 * Remove redundant or useless discard jumps.
3055 * For example, we can eliminate jumps in the following sequence:
3057 * discard-jump (redundant with the next jump)
3058 * discard-jump (useless; jumps to the next instruction)
3062 fs_visitor::opt_redundant_discard_jumps()
3064 bool progress
= false;
3066 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3068 fs_inst
*placeholder_halt
= NULL
;
3069 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3070 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3071 placeholder_halt
= inst
;
3076 if (!placeholder_halt
)
3079 /* Delete any HALTs immediately before the placeholder halt. */
3080 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3081 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3082 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3083 prev
->remove(last_bblock
);
3088 invalidate_live_intervals();
3094 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3095 * from \p r.offset which overlaps the region starting at \p s.offset and
3096 * spanning \p ds bytes.
3098 static inline unsigned
3099 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3101 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3102 const int shift
= rel_offset
/ REG_SIZE
;
3103 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3104 assert(reg_space(r
) == reg_space(s
) &&
3105 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3106 return ((1 << n
) - 1) << shift
;
3110 fs_visitor::opt_peephole_csel()
3112 if (devinfo
->gen
< 8)
3115 bool progress
= false;
3117 foreach_block_reverse(block
, cfg
) {
3118 int ip
= block
->end_ip
+ 1;
3120 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
3123 if (inst
->opcode
!= BRW_OPCODE_SEL
||
3124 inst
->predicate
!= BRW_PREDICATE_NORMAL
||
3125 (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
&&
3126 inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3127 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3130 /* Because it is a 3-src instruction, CSEL cannot have an immediate
3131 * value as a source, but we can sometimes handle zero.
3133 if ((inst
->src
[0].file
!= VGRF
&& inst
->src
[0].file
!= ATTR
&&
3134 inst
->src
[0].file
!= UNIFORM
) ||
3135 (inst
->src
[1].file
!= VGRF
&& inst
->src
[1].file
!= ATTR
&&
3136 inst
->src
[1].file
!= UNIFORM
&& !inst
->src
[1].is_zero()))
3139 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3140 if (!scan_inst
->flags_written())
3143 if ((scan_inst
->opcode
!= BRW_OPCODE_CMP
&&
3144 scan_inst
->opcode
!= BRW_OPCODE_MOV
) ||
3145 scan_inst
->predicate
!= BRW_PREDICATE_NONE
||
3146 (scan_inst
->src
[0].file
!= VGRF
&&
3147 scan_inst
->src
[0].file
!= ATTR
&&
3148 scan_inst
->src
[0].file
!= UNIFORM
) ||
3149 scan_inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
3152 if (scan_inst
->opcode
== BRW_OPCODE_CMP
&& !scan_inst
->src
[1].is_zero())
3155 const brw::fs_builder
ibld(this, block
, inst
);
3157 const enum brw_conditional_mod cond
=
3158 inst
->predicate_inverse
3159 ? brw_negate_cmod(scan_inst
->conditional_mod
)
3160 : scan_inst
->conditional_mod
;
3162 fs_inst
*csel_inst
= NULL
;
3164 if (inst
->src
[1].file
!= IMM
) {
3165 csel_inst
= ibld
.CSEL(inst
->dst
,
3170 } else if (cond
== BRW_CONDITIONAL_NZ
) {
3171 /* Consider the sequence
3173 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3174 * (+f0) sel g124<1>UD g2<8,8,1>UD 0x00000000UD
3176 * The sel will pick the immediate value 0 if r0 is ±0.0.
3177 * Therefore, this sequence is equivalent:
3179 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
3180 * (+f0) sel g124<1>F g2<8,8,1>F (abs)g3<8,8,1>F
3182 * The abs is ensures that the result is 0UD when g3 is -0.0F.
3183 * By normal cmp-sel merging, this is also equivalent:
3185 * csel.nz g124<1>F g2<4,4,1>F (abs)g3<4,4,1>F g3<4,4,1>F
3187 csel_inst
= ibld
.CSEL(inst
->dst
,
3193 csel_inst
->src
[1].abs
= true;
3196 if (csel_inst
!= NULL
) {
3198 csel_inst
->saturate
= inst
->saturate
;
3199 inst
->remove(block
);
3211 fs_visitor::compute_to_mrf()
3213 bool progress
= false;
3216 /* No MRFs on Gen >= 7. */
3217 if (devinfo
->gen
>= 7)
3220 calculate_live_intervals();
3222 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3226 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3227 inst
->is_partial_write() ||
3228 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3229 inst
->dst
.type
!= inst
->src
[0].type
||
3230 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3231 !inst
->src
[0].is_contiguous() ||
3232 inst
->src
[0].offset
% REG_SIZE
!= 0)
3235 /* Can't compute-to-MRF this GRF if someone else was going to
3238 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
3241 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3242 * things that computed the value of all GRFs of the source region. The
3243 * regs_left bitset keeps track of the registers we haven't yet found a
3244 * generating instruction for.
3246 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3248 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3249 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3250 inst
->src
[0], inst
->size_read(0))) {
3251 /* Found the last thing to write our reg we want to turn
3252 * into a compute-to-MRF.
3255 /* If this one instruction didn't populate all the
3256 * channels, bail. We might be able to rewrite everything
3257 * that writes that reg, but it would require smarter
3260 if (scan_inst
->is_partial_write())
3263 /* Handling things not fully contained in the source of the copy
3264 * would need us to understand coalescing out more than one MOV at
3267 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3268 inst
->src
[0], inst
->size_read(0)))
3271 /* SEND instructions can't have MRF as a destination. */
3272 if (scan_inst
->mlen
)
3275 if (devinfo
->gen
== 6) {
3276 /* gen6 math instructions must have the destination be
3277 * GRF, so no compute-to-MRF for them.
3279 if (scan_inst
->is_math()) {
3284 /* Clear the bits for any registers this instruction overwrites. */
3285 regs_left
&= ~mask_relative_to(
3286 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3291 /* We don't handle control flow here. Most computation of
3292 * values that end up in MRFs are shortly before the MRF
3295 if (block
->start() == scan_inst
)
3298 /* You can't read from an MRF, so if someone else reads our
3299 * MRF's source GRF that we wanted to rewrite, that stops us.
3301 bool interfered
= false;
3302 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3303 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3304 inst
->src
[0], inst
->size_read(0))) {
3311 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3312 inst
->dst
, inst
->size_written
)) {
3313 /* If somebody else writes our MRF here, we can't
3314 * compute-to-MRF before that.
3319 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3320 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3321 inst
->dst
, inst
->size_written
)) {
3322 /* Found a SEND instruction, which means that there are
3323 * live values in MRFs from base_mrf to base_mrf +
3324 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3334 /* Found all generating instructions of our MRF's source value, so it
3335 * should be safe to rewrite them to point to the MRF directly.
3337 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3339 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3340 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3341 inst
->src
[0], inst
->size_read(0))) {
3342 /* Clear the bits for any registers this instruction overwrites. */
3343 regs_left
&= ~mask_relative_to(
3344 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3346 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3347 reg_offset(inst
->src
[0]);
3349 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3350 /* Apply the same address transformation done by the hardware
3351 * for COMPR4 MRF writes.
3353 assert(rel_offset
< 2 * REG_SIZE
);
3354 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3356 /* Clear the COMPR4 bit if the generating instruction is not
3359 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3360 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3363 /* Calculate the MRF number the result of this instruction is
3364 * ultimately written to.
3366 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3369 scan_inst
->dst
.file
= MRF
;
3370 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3371 scan_inst
->saturate
|= inst
->saturate
;
3378 inst
->remove(block
);
3383 invalidate_live_intervals();
3389 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3390 * flow. We could probably do better here with some form of divergence
3394 fs_visitor::eliminate_find_live_channel()
3396 bool progress
= false;
3399 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3400 /* The optimization below assumes that channel zero is live on thread
3401 * dispatch, which may not be the case if the fixed function dispatches
3407 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3408 switch (inst
->opcode
) {
3414 case BRW_OPCODE_ENDIF
:
3415 case BRW_OPCODE_WHILE
:
3419 case FS_OPCODE_DISCARD_JUMP
:
3420 /* This can potentially make control flow non-uniform until the end
3425 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3427 inst
->opcode
= BRW_OPCODE_MOV
;
3428 inst
->src
[0] = brw_imm_ud(0u);
3430 inst
->force_writemask_all
= true;
3444 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3445 * instructions to FS_OPCODE_REP_FB_WRITE.
3448 fs_visitor::emit_repclear_shader()
3450 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3452 int color_mrf
= base_mrf
+ 2;
3456 mov
= bld
.exec_all().group(4, 0)
3457 .MOV(brw_message_reg(color_mrf
),
3458 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3460 struct brw_reg reg
=
3461 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3462 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3463 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3465 mov
= bld
.exec_all().group(4, 0)
3466 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3469 fs_inst
*write
= NULL
;
3470 if (key
->nr_color_regions
== 1) {
3471 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3472 write
->saturate
= key
->clamp_fragment_color
;
3473 write
->base_mrf
= color_mrf
;
3475 write
->header_size
= 0;
3478 assume(key
->nr_color_regions
> 0);
3480 struct brw_reg header
=
3481 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3482 bld
.exec_all().group(16, 0)
3483 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3485 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3487 bld
.exec_all().group(1, 0)
3488 .MOV(component(header
, 2), brw_imm_ud(i
));
3491 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3492 write
->saturate
= key
->clamp_fragment_color
;
3493 write
->base_mrf
= base_mrf
;
3495 write
->header_size
= 2;
3500 write
->last_rt
= true;
3504 assign_constant_locations();
3505 assign_curb_setup();
3507 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3509 assert(mov
->src
[0].file
== FIXED_GRF
);
3510 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3515 * Walks through basic blocks, looking for repeated MRF writes and
3516 * removing the later ones.
3519 fs_visitor::remove_duplicate_mrf_writes()
3521 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3522 bool progress
= false;
3524 /* Need to update the MRF tracking for compressed instructions. */
3525 if (dispatch_width
>= 16)
3528 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3530 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3531 if (inst
->is_control_flow()) {
3532 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3535 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3536 inst
->dst
.file
== MRF
) {
3537 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3538 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3539 inst
->dst
.equals(prev_inst
->dst
) &&
3540 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3541 inst
->saturate
== prev_inst
->saturate
&&
3542 inst
->predicate
== prev_inst
->predicate
&&
3543 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3544 inst
->exec_size
== prev_inst
->exec_size
) {
3545 inst
->remove(block
);
3551 /* Clear out the last-write records for MRFs that were overwritten. */
3552 if (inst
->dst
.file
== MRF
) {
3553 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3556 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3557 /* Found a SEND instruction, which will include two or fewer
3558 * implied MRF writes. We could do better here.
3560 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3561 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3565 /* Clear out any MRF move records whose sources got overwritten. */
3566 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3567 if (last_mrf_move
[i
] &&
3568 regions_overlap(inst
->dst
, inst
->size_written
,
3569 last_mrf_move
[i
]->src
[0],
3570 last_mrf_move
[i
]->size_read(0))) {
3571 last_mrf_move
[i
] = NULL
;
3575 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3576 inst
->dst
.file
== MRF
&&
3577 inst
->src
[0].file
!= ARF
&&
3578 !inst
->is_partial_write()) {
3579 last_mrf_move
[inst
->dst
.nr
] = inst
;
3584 invalidate_live_intervals();
3590 * Rounding modes for conversion instructions are included for each
3591 * conversion, but right now it is a state. So once it is set,
3592 * we don't need to call it again for subsequent calls.
3594 * This is useful for vector/matrices conversions, as setting the
3595 * mode once is enough for the full vector/matrix
3598 fs_visitor::remove_extra_rounding_modes()
3600 bool progress
= false;
3601 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3603 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3604 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3605 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3606 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3608 base_mode
= BRW_RND_MODE_RTNE
;
3609 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3610 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3611 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3613 base_mode
= BRW_RND_MODE_RTZ
;
3615 foreach_block (block
, cfg
) {
3616 brw_rnd_mode prev_mode
= base_mode
;
3618 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3619 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3620 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3621 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3622 if (mode
== prev_mode
) {
3623 inst
->remove(block
);
3633 invalidate_live_intervals();
3639 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3641 /* Clear the flag for registers that actually got read (as expected). */
3642 for (int i
= 0; i
< inst
->sources
; i
++) {
3644 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3645 grf
= inst
->src
[i
].nr
;
3650 if (grf
>= first_grf
&&
3651 grf
< first_grf
+ grf_len
) {
3652 deps
[grf
- first_grf
] = false;
3653 if (inst
->exec_size
== 16)
3654 deps
[grf
- first_grf
+ 1] = false;
3660 * Implements this workaround for the original 965:
3662 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3663 * check for post destination dependencies on this instruction, software
3664 * must ensure that there is no destination hazard for the case of ‘write
3665 * followed by a posted write’ shown in the following example.
3668 * 2. send r3.xy <rest of send instruction>
3671 * Due to no post-destination dependency check on the ‘send’, the above
3672 * code sequence could have two instructions (1 and 2) in flight at the
3673 * same time that both consider ‘r3’ as the target of their final writes.
3676 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3679 int write_len
= regs_written(inst
);
3680 int first_write_grf
= inst
->dst
.nr
;
3681 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3682 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3684 memset(needs_dep
, false, sizeof(needs_dep
));
3685 memset(needs_dep
, true, write_len
);
3687 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3689 /* Walk backwards looking for writes to registers we're writing which
3690 * aren't read since being written. If we hit the start of the program,
3691 * we assume that there are no outstanding dependencies on entry to the
3694 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3695 /* If we hit control flow, assume that there *are* outstanding
3696 * dependencies, and force their cleanup before our instruction.
3698 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3699 for (int i
= 0; i
< write_len
; i
++) {
3701 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3702 first_write_grf
+ i
);
3707 /* We insert our reads as late as possible on the assumption that any
3708 * instruction but a MOV that might have left us an outstanding
3709 * dependency has more latency than a MOV.
3711 if (scan_inst
->dst
.file
== VGRF
) {
3712 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3713 int reg
= scan_inst
->dst
.nr
+ i
;
3715 if (reg
>= first_write_grf
&&
3716 reg
< first_write_grf
+ write_len
&&
3717 needs_dep
[reg
- first_write_grf
]) {
3718 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3719 needs_dep
[reg
- first_write_grf
] = false;
3720 if (scan_inst
->exec_size
== 16)
3721 needs_dep
[reg
- first_write_grf
+ 1] = false;
3726 /* Clear the flag for registers that actually got read (as expected). */
3727 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3729 /* Continue the loop only if we haven't resolved all the dependencies */
3731 for (i
= 0; i
< write_len
; i
++) {
3741 * Implements this workaround for the original 965:
3743 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3744 * used as a destination register until after it has been sourced by an
3745 * instruction with a different destination register.
3748 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3750 int write_len
= regs_written(inst
);
3751 unsigned first_write_grf
= inst
->dst
.nr
;
3752 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3753 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3755 memset(needs_dep
, false, sizeof(needs_dep
));
3756 memset(needs_dep
, true, write_len
);
3757 /* Walk forwards looking for writes to registers we're writing which aren't
3758 * read before being written.
3760 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3761 /* If we hit control flow, force resolve all remaining dependencies. */
3762 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3763 for (int i
= 0; i
< write_len
; i
++) {
3765 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3766 first_write_grf
+ i
);
3771 /* Clear the flag for registers that actually got read (as expected). */
3772 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3774 /* We insert our reads as late as possible since they're reading the
3775 * result of a SEND, which has massive latency.
3777 if (scan_inst
->dst
.file
== VGRF
&&
3778 scan_inst
->dst
.nr
>= first_write_grf
&&
3779 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3780 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3781 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3783 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3786 /* Continue the loop only if we haven't resolved all the dependencies */
3788 for (i
= 0; i
< write_len
; i
++) {
3798 fs_visitor::insert_gen4_send_dependency_workarounds()
3800 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3803 bool progress
= false;
3805 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3806 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3807 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3808 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3814 invalidate_live_intervals();
3818 * Turns the generic expression-style uniform pull constant load instruction
3819 * into a hardware-specific series of instructions for loading a pull
3822 * The expression style allows the CSE pass before this to optimize out
3823 * repeated loads from the same offset, and gives the pre-register-allocation
3824 * scheduling full flexibility, while the conversion to native instructions
3825 * allows the post-register-allocation scheduler the best information
3828 * Note that execution masking for setting up pull constant loads is special:
3829 * the channels that need to be written are unrelated to the current execution
3830 * mask, since a later instruction will use one of the result channels as a
3831 * source operand for all 8 or 16 of its channels.
3834 fs_visitor::lower_uniform_pull_constant_loads()
3836 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3837 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3840 if (devinfo
->gen
>= 7) {
3841 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3842 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3844 ubld
.group(8, 0).MOV(payload
,
3845 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3846 ubld
.group(1, 0).MOV(component(payload
, 2),
3847 brw_imm_ud(inst
->src
[1].ud
/ 16));
3849 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3850 inst
->src
[1] = payload
;
3851 inst
->header_size
= 1;
3854 invalidate_live_intervals();
3856 /* Before register allocation, we didn't tell the scheduler about the
3857 * MRF we use. We know it's safe to use this MRF because nothing
3858 * else does except for register spill/unspill, which generates and
3859 * uses its MRF within a single IR instruction.
3861 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3868 fs_visitor::lower_load_payload()
3870 bool progress
= false;
3872 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3873 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3876 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3877 assert(inst
->saturate
== false);
3878 fs_reg dst
= inst
->dst
;
3880 /* Get rid of COMPR4. We'll add it back in if we need it */
3881 if (dst
.file
== MRF
)
3882 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3884 const fs_builder
ibld(this, block
, inst
);
3885 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3887 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3888 if (inst
->src
[i
].file
!= BAD_FILE
) {
3889 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3890 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3891 hbld
.MOV(mov_dst
, mov_src
);
3893 dst
= offset(dst
, hbld
, 1);
3896 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3897 inst
->exec_size
> 8) {
3898 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3899 * a straightforward copy. Instead, the result of the
3900 * LOAD_PAYLOAD is treated as interleaved and the first four
3901 * non-header sources are unpacked as:
3912 * This is used for gen <= 5 fb writes.
3914 assert(inst
->exec_size
== 16);
3915 assert(inst
->header_size
+ 4 <= inst
->sources
);
3916 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3917 if (inst
->src
[i
].file
!= BAD_FILE
) {
3918 if (devinfo
->has_compr4
) {
3919 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3920 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3921 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3923 /* Platform doesn't have COMPR4. We have to fake it */
3924 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3925 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3927 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3934 /* The loop above only ever incremented us through the first set
3935 * of 4 registers. However, thanks to the magic of COMPR4, we
3936 * actually wrote to the first 8 registers, so we need to take
3937 * that into account now.
3941 /* The COMPR4 code took care of the first 4 sources. We'll let
3942 * the regular path handle any remaining sources. Yes, we are
3943 * modifying the instruction but we're about to delete it so
3944 * this really doesn't hurt anything.
3946 inst
->header_size
+= 4;
3949 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3950 if (inst
->src
[i
].file
!= BAD_FILE
) {
3951 dst
.type
= inst
->src
[i
].type
;
3952 ibld
.MOV(dst
, inst
->src
[i
]);
3954 dst
.type
= BRW_REGISTER_TYPE_UD
;
3956 dst
= offset(dst
, ibld
, 1);
3959 inst
->remove(block
);
3964 invalidate_live_intervals();
3970 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3972 const fs_builder
ibld(this, block
, inst
);
3974 if (inst
->src
[1].file
== IMM
&& inst
->src
[1].ud
< (1 << 16)) {
3975 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3976 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3979 * If multiplying by an immediate value that fits in 16-bits, do a
3980 * single MUL instruction with that value in the proper location.
3982 if (devinfo
->gen
< 7) {
3983 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3984 ibld
.MOV(imm
, inst
->src
[1]);
3985 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3987 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3988 ibld
.MUL(inst
->dst
, inst
->src
[0],
3989 ud
? brw_imm_uw(inst
->src
[1].ud
)
3990 : brw_imm_w(inst
->src
[1].d
));
3993 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3994 * do 32-bit integer multiplication in one instruction, but instead
3995 * must do a sequence (which actually calculates a 64-bit result):
3997 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3998 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3999 * mov(8) g2<1>D acc0<8,8,1>D
4001 * But on Gen > 6, the ability to use second accumulator register
4002 * (acc1) for non-float data types was removed, preventing a simple
4003 * implementation in SIMD16. A 16-channel result can be calculated by
4004 * executing the three instructions twice in SIMD8, once with quarter
4005 * control of 1Q for the first eight channels and again with 2Q for
4006 * the second eight channels.
4008 * Which accumulator register is implicitly accessed (by AccWrEnable
4009 * for instance) is determined by the quarter control. Unfortunately
4010 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
4011 * implicit accumulator access by an instruction with 2Q will access
4012 * acc1 regardless of whether the data type is usable in acc1.
4014 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
4015 * integer data types.
4017 * Since we only want the low 32-bits of the result, we can do two
4018 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
4019 * adjust the high result and add them (like the mach is doing):
4021 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
4022 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
4023 * shl(8) g9<1>D g8<8,8,1>D 16D
4024 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
4026 * We avoid the shl instruction by realizing that we only want to add
4027 * the low 16-bits of the "high" result to the high 16-bits of the
4028 * "low" result and using proper regioning on the add:
4030 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
4031 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
4032 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
4034 * Since it does not use the (single) accumulator register, we can
4035 * schedule multi-component multiplications much better.
4038 bool needs_mov
= false;
4039 fs_reg orig_dst
= inst
->dst
;
4041 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
4042 * reusing the original destination is impossible due to hardware
4043 * restrictions, source/destination overlap, or it being the null
4046 fs_reg low
= inst
->dst
;
4047 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
4048 regions_overlap(inst
->dst
, inst
->size_written
,
4049 inst
->src
[0], inst
->size_read(0)) ||
4050 regions_overlap(inst
->dst
, inst
->size_written
,
4051 inst
->src
[1], inst
->size_read(1)) ||
4052 inst
->dst
.stride
>= 4) {
4054 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
4058 /* Get a new VGRF but keep the same stride as inst->dst */
4059 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
4060 high
.stride
= inst
->dst
.stride
;
4061 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
4063 if (devinfo
->gen
>= 7) {
4064 if (inst
->src
[1].abs
)
4065 lower_src_modifiers(this, block
, inst
, 1);
4067 if (inst
->src
[1].file
== IMM
) {
4068 ibld
.MUL(low
, inst
->src
[0],
4069 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
4070 ibld
.MUL(high
, inst
->src
[0],
4071 brw_imm_uw(inst
->src
[1].ud
>> 16));
4073 ibld
.MUL(low
, inst
->src
[0],
4074 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4075 ibld
.MUL(high
, inst
->src
[0],
4076 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
4079 if (inst
->src
[0].abs
)
4080 lower_src_modifiers(this, block
, inst
, 0);
4082 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
4084 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
4088 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4089 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4090 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
4092 if (needs_mov
|| inst
->conditional_mod
)
4093 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
4098 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
4100 const fs_builder
ibld(this, block
, inst
);
4102 /* Considering two 64-bit integers ab and cd where each letter ab
4103 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
4104 * only need to provide the YZ part of the result. -------
4106 * Only BD needs to be 64 bits. For AD and BC we only care + AD
4107 * about the lower 32 bits (since they are part of the upper + BC
4108 * 32 bits of our result). AC is not needed since it starts + AC
4109 * on the 65th bit of the result. -------
4112 unsigned int q_regs
= regs_written(inst
);
4113 unsigned int d_regs
= (q_regs
+ 1) / 2;
4115 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
4116 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4117 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4119 /* Here we need the full 64 bit result for 32b * 32b. */
4120 if (devinfo
->has_integer_dword_mul
) {
4121 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4122 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4124 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4125 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4126 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4128 fs_inst
*mul
= ibld
.MUL(acc
,
4129 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4130 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4131 mul
->writes_accumulator
= true;
4133 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4134 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4135 ibld
.MOV(bd_low
, acc
);
4137 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4138 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4141 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4142 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4143 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4144 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4146 ibld
.ADD(ad
, ad
, bc
);
4147 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4148 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4150 ibld
.MOV(inst
->dst
, bd
);
4154 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4156 const fs_builder
ibld(this, block
, inst
);
4158 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4159 * High" instruction:
4161 * "An added preliminary mov is required for source modification on
4163 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4164 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4165 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4167 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4168 lower_src_modifiers(this, block
, inst
, 1);
4170 /* Should have been lowered to 8-wide. */
4171 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4172 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4173 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4174 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4176 if (devinfo
->gen
>= 8) {
4177 /* Until Gen8, integer multiplies read 32-bits from one source,
4178 * and 16-bits from the other, and relying on the MACH instruction
4179 * to generate the high bits of the result.
4181 * On Gen8, the multiply instruction does a full 32x32-bit
4182 * multiply, but in order to do a 64-bit multiply we can simulate
4183 * the previous behavior and then use a MACH instruction.
4185 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4186 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4187 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4188 mul
->src
[1].stride
*= 2;
4190 if (mul
->src
[1].file
== IMM
) {
4191 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4193 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4195 /* Among other things the quarter control bits influence which
4196 * accumulator register is used by the hardware for instructions
4197 * that access the accumulator implicitly (e.g. MACH). A
4198 * second-half instruction would normally map to acc1, which
4199 * doesn't exist on Gen7 and up (the hardware does emulate it for
4200 * floating-point instructions *only* by taking advantage of the
4201 * extra precision of acc0 not normally used for floating point
4204 * HSW and up are careful enough not to try to access an
4205 * accumulator register that doesn't exist, but on earlier Gen7
4206 * hardware we need to make sure that the quarter control bits are
4207 * zero to avoid non-deterministic behaviour and emit an extra MOV
4208 * to get the result masked correctly according to the current
4212 mach
->force_writemask_all
= true;
4213 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4214 ibld
.MOV(inst
->dst
, mach
->dst
);
4219 fs_visitor::lower_integer_multiplication()
4221 bool progress
= false;
4223 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4224 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4225 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4226 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4227 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4228 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4229 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4230 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4231 lower_mul_qword_inst(inst
, block
);
4232 inst
->remove(block
);
4234 } else if (!inst
->dst
.is_accumulator() &&
4235 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4236 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4237 !devinfo
->has_integer_dword_mul
) {
4238 lower_mul_dword_inst(inst
, block
);
4239 inst
->remove(block
);
4242 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4243 lower_mulh_inst(inst
, block
);
4244 inst
->remove(block
);
4251 invalidate_live_intervals();
4257 fs_visitor::lower_minmax()
4259 assert(devinfo
->gen
< 6);
4261 bool progress
= false;
4263 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4264 const fs_builder
ibld(this, block
, inst
);
4266 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4267 inst
->predicate
== BRW_PREDICATE_NONE
) {
4268 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4269 * the original SEL.L/GE instruction
4271 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4272 inst
->conditional_mod
);
4273 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4274 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4281 invalidate_live_intervals();
4287 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4288 fs_reg
*dst
, fs_reg color
, unsigned components
)
4290 if (key
->clamp_fragment_color
) {
4291 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4292 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4294 for (unsigned i
= 0; i
< components
; i
++)
4296 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4301 for (unsigned i
= 0; i
< components
; i
++)
4302 dst
[i
] = offset(color
, bld
, i
);
4306 brw_fb_write_msg_control(const fs_inst
*inst
,
4307 const struct brw_wm_prog_data
*prog_data
)
4311 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4312 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4313 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4314 } else if (prog_data
->dual_src_blend
) {
4315 assert(inst
->exec_size
== 8);
4317 if (inst
->group
% 16 == 0)
4318 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4319 else if (inst
->group
% 16 == 8)
4320 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4322 unreachable("Invalid dual-source FB write instruction group");
4324 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4326 if (inst
->exec_size
== 16)
4327 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4328 else if (inst
->exec_size
== 8)
4329 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4331 unreachable("Invalid FB write execution size");
4338 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4339 const struct brw_wm_prog_data
*prog_data
,
4340 const brw_wm_prog_key
*key
,
4341 const fs_visitor::thread_payload
&payload
)
4343 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4344 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4345 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4346 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4347 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4348 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4349 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4350 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4351 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4352 const unsigned components
=
4353 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4355 /* We can potentially have a message length of up to 15, so we have to set
4356 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4359 int header_size
= 2, payload_header_size
;
4360 unsigned length
= 0;
4362 if (devinfo
->gen
< 6) {
4363 /* TODO: Support SIMD32 on gen4-5 */
4364 assert(bld
.group() < 16);
4366 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4367 * an implied MOV from g0,g1 to the start of the message. The MOV from
4368 * g0 is handled by the hardware and the MOV from g1 is provided by the
4369 * generator. This is required because, on gen4-5, the generator may
4370 * generate two write messages with different message lengths in order
4371 * to handle AA data properly.
4373 * Also, since the pixel mask goes in the g0 portion of the message and
4374 * since render target writes are the last thing in the shader, we write
4375 * the pixel mask directly into g0 and it will get copied as part of the
4378 if (prog_data
->uses_kill
) {
4379 bld
.exec_all().group(1, 0)
4380 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4381 brw_flag_reg(0, 1));
4384 assert(length
== 0);
4386 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4387 prog_data
->uses_kill
) ||
4388 (devinfo
->gen
< 11 &&
4389 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4390 /* From the Sandy Bridge PRM, volume 4, page 198:
4392 * "Dispatched Pixel Enables. One bit per pixel indicating
4393 * which pixels were originally enabled when the thread was
4394 * dispatched. This field is only required for the end-of-
4395 * thread message and on all dual-source messages."
4397 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4399 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4400 if (bld
.group() < 16) {
4401 /* The header starts off as g0 and g1 for the first half */
4402 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4403 BRW_REGISTER_TYPE_UD
));
4405 /* The header starts off as g0 and g2 for the second half */
4406 assert(bld
.group() < 32);
4407 const fs_reg header_sources
[2] = {
4408 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4409 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4411 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4414 uint32_t g00_bits
= 0;
4416 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4419 if (inst
->target
> 0 && prog_data
->replicate_alpha
)
4420 g00_bits
|= 1 << 11;
4422 /* Set computes stencil to render target */
4423 if (prog_data
->computed_stencil
)
4424 g00_bits
|= 1 << 14;
4427 /* OR extra bits into g0.0 */
4428 ubld
.group(1, 0).OR(component(header
, 0),
4429 retype(brw_vec1_grf(0, 0),
4430 BRW_REGISTER_TYPE_UD
),
4431 brw_imm_ud(g00_bits
));
4434 /* Set the render target index for choosing BLEND_STATE. */
4435 if (inst
->target
> 0) {
4436 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4439 if (prog_data
->uses_kill
) {
4440 assert(bld
.group() < 16);
4441 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4442 BRW_REGISTER_TYPE_UW
),
4443 brw_flag_reg(0, 1));
4446 assert(length
== 0);
4447 sources
[0] = header
;
4448 sources
[1] = horiz_offset(header
, 8);
4451 assert(length
== 0 || length
== 2);
4452 header_size
= length
;
4454 if (payload
.aa_dest_stencil_reg
[0]) {
4455 assert(inst
->group
< 16);
4456 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4457 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4458 .MOV(sources
[length
],
4459 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4463 bool src0_alpha_present
= false;
4465 if (src0_alpha
.file
!= BAD_FILE
) {
4466 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4467 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4468 .annotate("FB write src0 alpha");
4469 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4470 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4471 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4474 src0_alpha_present
= true;
4475 } else if (prog_data
->replicate_alpha
&& inst
->target
!= 0) {
4476 /* Handle the case when fragment shader doesn't write to draw buffer
4477 * zero. No need to call setup_color_payload() for src0_alpha because
4478 * alpha value will be undefined.
4480 length
+= bld
.dispatch_width() / 8;
4481 src0_alpha_present
= true;
4484 if (sample_mask
.file
!= BAD_FILE
) {
4485 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4486 BRW_REGISTER_TYPE_UD
);
4488 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4489 * relevant. Since it's unsigned single words one vgrf is always
4490 * 16-wide, but only the lower or higher 8 channels will be used by the
4491 * hardware when doing a SIMD8 write depending on whether we have
4492 * selected the subspans for the first or second half respectively.
4494 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4495 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4496 sample_mask
.stride
*= 2;
4498 bld
.exec_all().annotate("FB write oMask")
4499 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4505 payload_header_size
= length
;
4507 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4510 if (color1
.file
!= BAD_FILE
) {
4511 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4515 if (src_depth
.file
!= BAD_FILE
) {
4516 sources
[length
] = src_depth
;
4520 if (dst_depth
.file
!= BAD_FILE
) {
4521 sources
[length
] = dst_depth
;
4525 if (src_stencil
.file
!= BAD_FILE
) {
4526 assert(devinfo
->gen
>= 9);
4527 assert(bld
.dispatch_width() == 8);
4529 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4530 * available on gen9+. As such it's impossible to have both enabled at the
4531 * same time and therefore length cannot overrun the array.
4533 assert(length
< 15);
4535 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4536 bld
.exec_all().annotate("FB write OS")
4537 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4538 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4543 if (devinfo
->gen
>= 7) {
4544 /* Send from the GRF */
4545 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4546 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4547 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4548 load
->dst
= payload
;
4550 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4551 uint32_t ex_desc
= 0;
4554 (inst
->group
/ 16) << 11 | /* rt slot group */
4555 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4556 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4557 inst
->last_rt
, false);
4559 if (devinfo
->gen
>= 11) {
4560 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4561 * in the extended message descriptor, in lieu of using a header.
4563 ex_desc
= inst
->target
<< 12 | src0_alpha_present
<< 15;
4565 if (key
->nr_color_regions
== 0)
4566 ex_desc
|= 1 << 20; /* Null Render Target */
4569 inst
->opcode
= SHADER_OPCODE_SEND
;
4570 inst
->resize_sources(3);
4571 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4572 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4573 inst
->src
[1] = brw_imm_ud(ex_desc
);
4574 inst
->src
[2] = payload
;
4575 inst
->mlen
= regs_written(load
);
4577 inst
->header_size
= header_size
;
4578 inst
->check_tdr
= true;
4579 inst
->send_has_side_effects
= true;
4581 /* Send from the MRF */
4582 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4583 sources
, length
, payload_header_size
);
4585 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4586 * will do this for us if we just give it a COMPR4 destination.
4588 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4589 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4591 if (devinfo
->gen
< 6) {
4592 /* Set up src[0] for the implied MOV from grf0-1 */
4593 inst
->resize_sources(1);
4594 inst
->src
[0] = brw_vec8_grf(0, 0);
4596 inst
->resize_sources(0);
4599 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4600 inst
->mlen
= regs_written(load
);
4601 inst
->header_size
= header_size
;
4606 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4608 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4609 const unsigned length
= 2;
4610 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4612 if (bld
.group() < 16) {
4613 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4614 BRW_REGISTER_TYPE_UD
));
4616 assert(bld
.group() < 32);
4617 const fs_reg header_sources
[] = {
4618 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4619 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4621 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4624 inst
->resize_sources(1);
4625 inst
->src
[0] = header
;
4626 inst
->opcode
= FS_OPCODE_FB_READ
;
4627 inst
->mlen
= length
;
4628 inst
->header_size
= length
;
4632 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4633 const fs_reg
&coordinate
,
4634 const fs_reg
&shadow_c
,
4635 const fs_reg
&lod
, const fs_reg
&lod2
,
4636 const fs_reg
&surface
,
4637 const fs_reg
&sampler
,
4638 unsigned coord_components
,
4639 unsigned grad_components
)
4641 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4642 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4643 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4644 fs_reg msg_end
= msg_begin
;
4647 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4649 for (unsigned i
= 0; i
< coord_components
; i
++)
4650 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4651 offset(coordinate
, bld
, i
));
4653 msg_end
= offset(msg_end
, bld
, coord_components
);
4655 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4656 * require all three components to be present and zero if they are unused.
4658 if (coord_components
> 0 &&
4659 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4660 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4661 for (unsigned i
= coord_components
; i
< 3; i
++)
4662 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4664 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4667 if (op
== SHADER_OPCODE_TXD
) {
4668 /* TXD unsupported in SIMD16 mode. */
4669 assert(bld
.dispatch_width() == 8);
4671 /* the slots for u and v are always present, but r is optional */
4672 if (coord_components
< 2)
4673 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4676 * dPdx = dudx, dvdx, drdx
4677 * dPdy = dudy, dvdy, drdy
4679 * 1-arg: Does not exist.
4681 * 2-arg: dudx dvdx dudy dvdy
4682 * dPdx.x dPdx.y dPdy.x dPdy.y
4685 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4686 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4687 * m5 m6 m7 m8 m9 m10
4689 for (unsigned i
= 0; i
< grad_components
; i
++)
4690 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4692 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4694 for (unsigned i
= 0; i
< grad_components
; i
++)
4695 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4697 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4701 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4702 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4704 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4705 bld
.dispatch_width() == 16);
4707 const brw_reg_type type
=
4708 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4709 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4710 bld
.MOV(retype(msg_end
, type
), lod
);
4711 msg_end
= offset(msg_end
, bld
, 1);
4714 if (shadow_c
.file
!= BAD_FILE
) {
4715 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4716 /* There's no plain shadow compare message, so we use shadow
4717 * compare with a bias of 0.0.
4719 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4720 msg_end
= offset(msg_end
, bld
, 1);
4723 bld
.MOV(msg_end
, shadow_c
);
4724 msg_end
= offset(msg_end
, bld
, 1);
4728 inst
->src
[0] = reg_undef
;
4729 inst
->src
[1] = surface
;
4730 inst
->src
[2] = sampler
;
4731 inst
->resize_sources(3);
4732 inst
->base_mrf
= msg_begin
.nr
;
4733 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4734 inst
->header_size
= 1;
4738 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4739 const fs_reg
&coordinate
,
4740 const fs_reg
&shadow_c
,
4741 const fs_reg
&lod
, const fs_reg
&lod2
,
4742 const fs_reg
&sample_index
,
4743 const fs_reg
&surface
,
4744 const fs_reg
&sampler
,
4745 unsigned coord_components
,
4746 unsigned grad_components
)
4748 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4749 fs_reg msg_coords
= message
;
4750 unsigned header_size
= 0;
4752 if (inst
->offset
!= 0) {
4753 /* The offsets set up by the visitor are in the m1 header, so we can't
4760 for (unsigned i
= 0; i
< coord_components
; i
++)
4761 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4762 offset(coordinate
, bld
, i
));
4764 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4765 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4767 if (shadow_c
.file
!= BAD_FILE
) {
4768 fs_reg msg_shadow
= msg_lod
;
4769 bld
.MOV(msg_shadow
, shadow_c
);
4770 msg_lod
= offset(msg_shadow
, bld
, 1);
4775 case SHADER_OPCODE_TXL
:
4777 bld
.MOV(msg_lod
, lod
);
4778 msg_end
= offset(msg_lod
, bld
, 1);
4780 case SHADER_OPCODE_TXD
:
4783 * dPdx = dudx, dvdx, drdx
4784 * dPdy = dudy, dvdy, drdy
4786 * Load up these values:
4787 * - dudx dudy dvdx dvdy drdx drdy
4788 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4791 for (unsigned i
= 0; i
< grad_components
; i
++) {
4792 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4793 msg_end
= offset(msg_end
, bld
, 1);
4795 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4796 msg_end
= offset(msg_end
, bld
, 1);
4799 case SHADER_OPCODE_TXS
:
4800 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4801 bld
.MOV(msg_lod
, lod
);
4802 msg_end
= offset(msg_lod
, bld
, 1);
4804 case SHADER_OPCODE_TXF
:
4805 msg_lod
= offset(msg_coords
, bld
, 3);
4806 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4807 msg_end
= offset(msg_lod
, bld
, 1);
4809 case SHADER_OPCODE_TXF_CMS
:
4810 msg_lod
= offset(msg_coords
, bld
, 3);
4812 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4814 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4815 msg_end
= offset(msg_lod
, bld
, 2);
4822 inst
->src
[0] = reg_undef
;
4823 inst
->src
[1] = surface
;
4824 inst
->src
[2] = sampler
;
4825 inst
->resize_sources(3);
4826 inst
->base_mrf
= message
.nr
;
4827 inst
->mlen
= msg_end
.nr
- message
.nr
;
4828 inst
->header_size
= header_size
;
4830 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4831 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4835 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4837 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4840 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4844 sampler_msg_type(const gen_device_info
*devinfo
,
4845 opcode opcode
, bool shadow_compare
)
4847 assert(devinfo
->gen
>= 5);
4849 case SHADER_OPCODE_TEX
:
4850 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4851 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4853 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4854 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4855 case SHADER_OPCODE_TXL
:
4856 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4857 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4858 case SHADER_OPCODE_TXL_LZ
:
4859 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4860 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4861 case SHADER_OPCODE_TXS
:
4862 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4863 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4864 case SHADER_OPCODE_TXD
:
4865 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4866 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4867 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4868 case SHADER_OPCODE_TXF
:
4869 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4870 case SHADER_OPCODE_TXF_LZ
:
4871 assert(devinfo
->gen
>= 9);
4872 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4873 case SHADER_OPCODE_TXF_CMS_W
:
4874 assert(devinfo
->gen
>= 9);
4875 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4876 case SHADER_OPCODE_TXF_CMS
:
4877 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4878 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4879 case SHADER_OPCODE_TXF_UMS
:
4880 assert(devinfo
->gen
>= 7);
4881 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4882 case SHADER_OPCODE_TXF_MCS
:
4883 assert(devinfo
->gen
>= 7);
4884 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4885 case SHADER_OPCODE_LOD
:
4886 return GEN5_SAMPLER_MESSAGE_LOD
;
4887 case SHADER_OPCODE_TG4
:
4888 assert(devinfo
->gen
>= 7);
4889 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4890 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4892 case SHADER_OPCODE_TG4_OFFSET
:
4893 assert(devinfo
->gen
>= 7);
4894 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4895 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4896 case SHADER_OPCODE_SAMPLEINFO
:
4897 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4899 unreachable("not reached");
4904 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4905 const fs_reg
&coordinate
,
4906 const fs_reg
&shadow_c
,
4907 fs_reg lod
, const fs_reg
&lod2
,
4908 const fs_reg
&min_lod
,
4909 const fs_reg
&sample_index
,
4911 const fs_reg
&surface
,
4912 const fs_reg
&sampler
,
4913 const fs_reg
&surface_handle
,
4914 const fs_reg
&sampler_handle
,
4915 const fs_reg
&tg4_offset
,
4916 unsigned coord_components
,
4917 unsigned grad_components
)
4919 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4920 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4921 unsigned reg_width
= bld
.dispatch_width() / 8;
4922 unsigned header_size
= 0, length
= 0;
4923 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4924 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4925 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4927 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4928 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4929 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4931 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4932 inst
->offset
!= 0 || inst
->eot
||
4933 op
== SHADER_OPCODE_SAMPLEINFO
||
4934 sampler_handle
.file
!= BAD_FILE
||
4935 is_high_sampler(devinfo
, sampler
)) {
4936 /* For general texture offsets (no txf workaround), we need a header to
4939 * TG4 needs to place its channel select in the header, for interaction
4940 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4941 * larger sampler numbers we need to offset the Sampler State Pointer in
4944 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4948 /* If we're requesting fewer than four channels worth of response,
4949 * and we have an explicit header, we need to set up the sampler
4950 * writemask. It's reversed from normal: 1 means "don't write".
4952 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4953 assert(regs_written(inst
) % reg_width
== 0);
4954 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4955 inst
->offset
|= mask
<< 12;
4958 /* Build the actual header */
4959 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4960 const fs_builder ubld1
= ubld
.group(1, 0);
4961 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4963 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4964 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4965 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4966 /* The vertex and fragment stages have g0.2 set to 0, so
4967 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4968 * must set it to 0 to avoid setting undesirable bits in the
4971 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4974 if (sampler_handle
.file
!= BAD_FILE
) {
4975 /* Bindless sampler handles aren't relative to the sampler state
4976 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
4977 * Instead, it's an absolute pointer relative to dynamic state base
4980 * Sampler states are 16 bytes each and the pointer we give here has
4981 * to be 32-byte aligned. In order to avoid more indirect messages
4982 * than required, we assume that all bindless sampler states are
4983 * 32-byte aligned. This sacrifices a bit of general state base
4984 * address space but means we can do something more efficient in the
4987 ubld1
.MOV(component(header
, 3), sampler_handle
);
4988 } else if (is_high_sampler(devinfo
, sampler
)) {
4989 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4990 assert(sampler
.ud
>= 16);
4991 const int sampler_state_size
= 16; /* 16 bytes */
4993 ubld1
.ADD(component(header
, 3),
4994 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4995 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
4997 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
4998 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
4999 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
5000 ubld1
.ADD(component(header
, 3),
5001 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5007 if (shadow_c
.file
!= BAD_FILE
) {
5008 bld
.MOV(sources
[length
], shadow_c
);
5012 bool coordinate_done
= false;
5014 /* Set up the LOD info */
5017 case SHADER_OPCODE_TXL
:
5018 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
5019 op
= SHADER_OPCODE_TXL_LZ
;
5022 bld
.MOV(sources
[length
], lod
);
5025 case SHADER_OPCODE_TXD
:
5026 /* TXD should have been lowered in SIMD16 mode. */
5027 assert(bld
.dispatch_width() == 8);
5029 /* Load dPdx and the coordinate together:
5030 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5032 for (unsigned i
= 0; i
< coord_components
; i
++) {
5033 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5035 /* For cube map array, the coordinate is (u,v,r,ai) but there are
5036 * only derivatives for (u, v, r).
5038 if (i
< grad_components
) {
5039 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
5040 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
5044 coordinate_done
= true;
5046 case SHADER_OPCODE_TXS
:
5047 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
5050 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5051 /* We need an LOD; just use 0 */
5052 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
5055 case SHADER_OPCODE_TXF
:
5056 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5057 * On Gen9 they are u, v, lod, r
5059 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
5061 if (devinfo
->gen
>= 9) {
5062 if (coord_components
>= 2) {
5063 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
5064 offset(coordinate
, bld
, 1));
5066 sources
[length
] = brw_imm_d(0);
5071 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
5072 op
= SHADER_OPCODE_TXF_LZ
;
5074 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
5078 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
5079 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5080 offset(coordinate
, bld
, i
));
5082 coordinate_done
= true;
5085 case SHADER_OPCODE_TXF_CMS
:
5086 case SHADER_OPCODE_TXF_CMS_W
:
5087 case SHADER_OPCODE_TXF_UMS
:
5088 case SHADER_OPCODE_TXF_MCS
:
5089 if (op
== SHADER_OPCODE_TXF_UMS
||
5090 op
== SHADER_OPCODE_TXF_CMS
||
5091 op
== SHADER_OPCODE_TXF_CMS_W
) {
5092 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
5096 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
5097 /* Data from the multisample control surface. */
5098 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
5101 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
5104 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
5105 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
5108 offset(mcs
, bld
, 1));
5113 /* There is no offsetting for this message; just copy in the integer
5114 * texture coordinates.
5116 for (unsigned i
= 0; i
< coord_components
; i
++)
5117 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5118 offset(coordinate
, bld
, i
));
5120 coordinate_done
= true;
5122 case SHADER_OPCODE_TG4_OFFSET
:
5123 /* More crazy intermixing */
5124 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5125 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5127 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5128 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5129 offset(tg4_offset
, bld
, i
));
5131 if (coord_components
== 3) /* r if present */
5132 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5134 coordinate_done
= true;
5140 /* Set up the coordinate (except for cases where it was done above) */
5141 if (!coordinate_done
) {
5142 for (unsigned i
= 0; i
< coord_components
; i
++)
5143 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5146 if (min_lod
.file
!= BAD_FILE
) {
5147 /* Account for all of the missing coordinate sources */
5148 length
+= 4 - coord_components
;
5149 if (op
== SHADER_OPCODE_TXD
)
5150 length
+= (3 - grad_components
) * 2;
5152 bld
.MOV(sources
[length
++], min_lod
);
5157 mlen
= length
* reg_width
- header_size
;
5159 mlen
= length
* reg_width
;
5161 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5162 BRW_REGISTER_TYPE_F
);
5163 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5165 /* Generate the SEND. */
5166 inst
->opcode
= SHADER_OPCODE_SEND
;
5168 inst
->header_size
= header_size
;
5170 const unsigned msg_type
=
5171 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5172 const unsigned simd_mode
=
5173 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5174 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5176 uint32_t base_binding_table_index
;
5178 case SHADER_OPCODE_TG4
:
5179 case SHADER_OPCODE_TG4_OFFSET
:
5180 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5182 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5183 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5186 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5190 inst
->sfid
= BRW_SFID_SAMPLER
;
5191 if (surface
.file
== IMM
&&
5192 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5193 inst
->desc
= brw_sampler_desc(devinfo
,
5194 surface
.ud
+ base_binding_table_index
,
5195 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5198 0 /* return_format unused on gen7+ */);
5199 inst
->src
[0] = brw_imm_ud(0);
5200 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5201 } else if (surface_handle
.file
!= BAD_FILE
) {
5202 /* Bindless surface */
5203 assert(devinfo
->gen
>= 9);
5204 inst
->desc
= brw_sampler_desc(devinfo
,
5206 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5209 0 /* return_format unused on gen7+ */);
5211 /* For bindless samplers, the entire address is included in the message
5212 * header so we can leave the portion in the message descriptor 0.
5214 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5215 inst
->src
[0] = brw_imm_ud(0);
5217 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5218 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5219 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5220 inst
->src
[0] = desc
;
5223 /* We assume that the driver provided the handle in the top 20 bits so
5224 * we can use the surface handle directly as the extended descriptor.
5226 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5228 /* Immediate portion of the descriptor */
5229 inst
->desc
= brw_sampler_desc(devinfo
,
5234 0 /* return_format unused on gen7+ */);
5235 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5236 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5237 if (surface
.equals(sampler
)) {
5238 /* This case is common in GL */
5239 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5241 if (sampler_handle
.file
!= BAD_FILE
) {
5242 ubld
.MOV(desc
, surface
);
5243 } else if (sampler
.file
== IMM
) {
5244 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5246 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5247 ubld
.OR(desc
, desc
, surface
);
5250 if (base_binding_table_index
)
5251 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5252 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5254 inst
->src
[0] = component(desc
, 0);
5255 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5258 inst
->src
[2] = src_payload
;
5259 inst
->resize_sources(3);
5262 /* EOT sampler messages don't make sense to split because it would
5263 * involve ending half of the thread early.
5265 assert(inst
->group
== 0);
5266 /* We need to use SENDC for EOT sampler messages */
5267 inst
->check_tdr
= true;
5268 inst
->send_has_side_effects
= true;
5271 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5272 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5276 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5278 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5279 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5280 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5281 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5282 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5283 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5284 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5285 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5286 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5287 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5288 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5289 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5290 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5291 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5292 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5293 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5294 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5296 if (devinfo
->gen
>= 7) {
5297 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5298 shadow_c
, lod
, lod2
, min_lod
,
5300 mcs
, surface
, sampler
,
5301 surface_handle
, sampler_handle
,
5303 coord_components
, grad_components
);
5304 } else if (devinfo
->gen
>= 5) {
5305 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5306 shadow_c
, lod
, lod2
, sample_index
,
5308 coord_components
, grad_components
);
5310 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5311 shadow_c
, lod
, lod2
,
5313 coord_components
, grad_components
);
5318 * Initialize the header present in some typed and untyped surface
5322 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
5324 fs_builder ubld
= bld
.exec_all().group(8, 0);
5325 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5326 ubld
.MOV(dst
, brw_imm_d(0));
5327 ubld
.group(1, 0).MOV(component(dst
, 7), sample_mask
);
5332 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5334 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5336 /* Get the logical send arguments. */
5337 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5338 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5339 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5340 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5341 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5342 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5343 assert(arg
.file
== IMM
);
5345 /* We must have exactly one of surface and surface_handle */
5346 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5348 /* Calculate the total number of components of the payload. */
5349 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5350 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5352 const bool is_typed_access
=
5353 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5354 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5355 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5357 /* From the BDW PRM Volume 7, page 147:
5359 * "For the Data Cache Data Port*, the header must be present for the
5360 * following message types: [...] Typed read/write/atomics"
5362 * Earlier generations have a similar wording. Because of this restriction
5363 * we don't attempt to implement sample masks via predication for such
5364 * messages prior to Gen9, since we have to provide a header anyway. On
5365 * Gen11+ the header has been removed so we can only use predication.
5367 const unsigned header_sz
= devinfo
->gen
< 9 && is_typed_access
? 1 : 0;
5369 const bool has_side_effects
= inst
->has_side_effects();
5370 fs_reg sample_mask
= has_side_effects
? bld
.sample_mask_reg() :
5371 fs_reg(brw_imm_d(0xffff));
5373 fs_reg payload
, payload2
;
5374 unsigned mlen
, ex_mlen
= 0;
5375 if (devinfo
->gen
>= 9) {
5376 /* We have split sends on gen9 and above */
5377 assert(header_sz
== 0);
5378 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5379 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5380 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5381 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5383 /* Allocate space for the payload. */
5384 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5385 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5386 fs_reg
*const components
= new fs_reg
[sz
];
5389 /* Construct the payload. */
5391 components
[n
++] = emit_surface_header(bld
, sample_mask
);
5393 for (unsigned i
= 0; i
< addr_sz
; i
++)
5394 components
[n
++] = offset(addr
, bld
, i
);
5396 for (unsigned i
= 0; i
< src_sz
; i
++)
5397 components
[n
++] = offset(src
, bld
, i
);
5399 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5400 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5402 delete[] components
;
5405 /* Predicate the instruction on the sample mask if no header is
5408 if (!header_sz
&& sample_mask
.file
!= BAD_FILE
&&
5409 sample_mask
.file
!= IMM
) {
5410 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5411 if (inst
->predicate
) {
5412 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5413 assert(!inst
->predicate_inverse
);
5414 assert(inst
->flag_subreg
< 2);
5415 /* Combine the sample mask with the existing predicate by using a
5416 * vertical predication mode.
5418 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5419 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
5423 inst
->flag_subreg
= 2;
5424 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5425 inst
->predicate_inverse
= false;
5426 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5432 switch (inst
->opcode
) {
5433 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5434 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5435 /* Byte scattered opcodes go through the normal data cache */
5436 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5439 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5440 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5441 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5442 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5443 /* Untyped Surface messages go through the data cache but the SFID value
5444 * changed on Haswell.
5446 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5447 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5448 GEN7_SFID_DATAPORT_DATA_CACHE
);
5451 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5452 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5453 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5454 /* Typed surface messages go through the render cache on IVB and the
5455 * data cache on HSW+.
5457 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5458 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5459 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5463 unreachable("Unsupported surface opcode");
5467 switch (inst
->opcode
) {
5468 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5469 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5470 arg
.ud
, /* num_channels */
5474 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5475 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5476 arg
.ud
, /* num_channels */
5480 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5481 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5482 arg
.ud
, /* bit_size */
5486 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5487 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5488 arg
.ud
, /* bit_size */
5492 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5493 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5494 arg
.ud
, /* atomic_op */
5495 !inst
->dst
.is_null());
5498 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5499 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5500 arg
.ud
, /* atomic_op */
5501 !inst
->dst
.is_null());
5504 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5505 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5506 arg
.ud
, /* num_channels */
5510 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5511 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5512 arg
.ud
, /* num_channels */
5516 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5517 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5518 arg
.ud
, /* atomic_op */
5519 !inst
->dst
.is_null());
5523 unreachable("Unknown surface logical instruction");
5526 /* Update the original instruction. */
5527 inst
->opcode
= SHADER_OPCODE_SEND
;
5529 inst
->ex_mlen
= ex_mlen
;
5530 inst
->header_size
= header_sz
;
5531 inst
->send_has_side_effects
= has_side_effects
;
5532 inst
->send_is_volatile
= !has_side_effects
;
5534 /* Set up SFID and descriptors */
5537 if (surface
.file
== IMM
) {
5538 inst
->desc
|= surface
.ud
& 0xff;
5539 inst
->src
[0] = brw_imm_ud(0);
5540 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5541 } else if (surface_handle
.file
!= BAD_FILE
) {
5542 /* Bindless surface */
5543 assert(devinfo
->gen
>= 9);
5544 inst
->desc
|= GEN9_BTI_BINDLESS
;
5545 inst
->src
[0] = brw_imm_ud(0);
5547 /* We assume that the driver provided the handle in the top 20 bits so
5548 * we can use the surface handle directly as the extended descriptor.
5550 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5552 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5553 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5554 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5555 inst
->src
[0] = component(tmp
, 0);
5556 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5559 /* Finally, the payload */
5560 inst
->src
[2] = payload
;
5561 inst
->src
[3] = payload2
;
5563 inst
->resize_sources(4);
5567 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5569 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5571 const fs_reg
&addr
= inst
->src
[0];
5572 const fs_reg
&src
= inst
->src
[1];
5573 const unsigned src_comps
= inst
->components_read(1);
5574 assert(inst
->src
[2].file
== IMM
);
5575 const unsigned arg
= inst
->src
[2].ud
;
5576 const bool has_side_effects
= inst
->has_side_effects();
5578 /* If the surface message has side effects and we're a fragment shader, we
5579 * have to predicate with the sample mask to avoid helper invocations.
5581 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
) {
5582 inst
->flag_subreg
= 2;
5583 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5584 inst
->predicate_inverse
= false;
5586 fs_reg sample_mask
= bld
.sample_mask_reg();
5587 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5588 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5592 fs_reg payload
, payload2
;
5593 unsigned mlen
, ex_mlen
= 0;
5594 if (devinfo
->gen
>= 9) {
5595 /* On Skylake and above, we have SENDS */
5596 mlen
= 2 * (inst
->exec_size
/ 8);
5597 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5598 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5599 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5600 BRW_REGISTER_TYPE_UD
);
5602 /* Add two because the address is 64-bit */
5603 const unsigned dwords
= 2 + src_comps
;
5604 mlen
= dwords
* (inst
->exec_size
/ 8);
5610 for (unsigned i
= 0; i
< src_comps
; i
++)
5611 sources
[1 + i
] = offset(src
, bld
, i
);
5613 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5614 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5618 switch (inst
->opcode
) {
5619 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5620 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5621 arg
, /* num_channels */
5625 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5626 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5627 arg
, /* num_channels */
5631 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5632 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5637 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5638 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5643 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5644 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5645 arg
, /* atomic_op */
5646 !inst
->dst
.is_null());
5649 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5650 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5651 arg
, /* atomic_op */
5652 !inst
->dst
.is_null());
5656 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5657 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5658 arg
, /* atomic_op */
5659 !inst
->dst
.is_null());
5663 unreachable("Unknown A64 logical instruction");
5666 /* Update the original instruction. */
5667 inst
->opcode
= SHADER_OPCODE_SEND
;
5669 inst
->ex_mlen
= ex_mlen
;
5670 inst
->header_size
= 0;
5671 inst
->send_has_side_effects
= has_side_effects
;
5672 inst
->send_is_volatile
= !has_side_effects
;
5674 /* Set up SFID and descriptors */
5675 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5677 inst
->resize_sources(4);
5678 inst
->src
[0] = brw_imm_ud(0); /* desc */
5679 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5680 inst
->src
[2] = payload
;
5681 inst
->src
[3] = payload2
;
5685 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5687 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5689 if (devinfo
->gen
>= 7) {
5690 fs_reg index
= inst
->src
[0];
5691 /* We are switching the instruction from an ALU-like instruction to a
5692 * send-from-grf instruction. Since sends can't handle strides or
5693 * source modifiers, we have to make a copy of the offset source.
5695 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5696 bld
.MOV(offset
, inst
->src
[1]);
5698 const unsigned simd_mode
=
5699 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5700 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5702 inst
->opcode
= SHADER_OPCODE_SEND
;
5703 inst
->mlen
= inst
->exec_size
/ 8;
5704 inst
->resize_sources(3);
5706 inst
->sfid
= BRW_SFID_SAMPLER
;
5707 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5708 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5710 if (index
.file
== IMM
) {
5711 inst
->desc
|= index
.ud
& 0xff;
5712 inst
->src
[0] = brw_imm_ud(0);
5714 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5715 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5716 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5717 inst
->src
[0] = component(tmp
, 0);
5719 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5720 inst
->src
[2] = offset
; /* payload */
5722 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5723 BRW_REGISTER_TYPE_UD
);
5725 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5727 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5728 inst
->resize_sources(1);
5729 inst
->base_mrf
= payload
.nr
;
5730 inst
->header_size
= 1;
5731 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5736 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5738 assert(bld
.shader
->devinfo
->gen
< 6);
5741 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5743 if (inst
->sources
> 1) {
5744 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5745 * "Message Payload":
5747 * "Operand0[7]. For the INT DIV functions, this operand is the
5750 * "Operand1[7]. For the INT DIV functions, this operand is the
5753 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5754 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5755 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5757 inst
->resize_sources(1);
5758 inst
->src
[0] = src0
;
5760 assert(inst
->exec_size
== 8);
5761 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5766 fs_visitor::lower_logical_sends()
5768 bool progress
= false;
5770 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5771 const fs_builder
ibld(this, block
, inst
);
5773 switch (inst
->opcode
) {
5774 case FS_OPCODE_FB_WRITE_LOGICAL
:
5775 assert(stage
== MESA_SHADER_FRAGMENT
);
5776 lower_fb_write_logical_send(ibld
, inst
,
5777 brw_wm_prog_data(prog_data
),
5778 (const brw_wm_prog_key
*)key
,
5782 case FS_OPCODE_FB_READ_LOGICAL
:
5783 lower_fb_read_logical_send(ibld
, inst
);
5786 case SHADER_OPCODE_TEX_LOGICAL
:
5787 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5790 case SHADER_OPCODE_TXD_LOGICAL
:
5791 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5794 case SHADER_OPCODE_TXF_LOGICAL
:
5795 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5798 case SHADER_OPCODE_TXL_LOGICAL
:
5799 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5802 case SHADER_OPCODE_TXS_LOGICAL
:
5803 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5806 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5807 lower_sampler_logical_send(ibld
, inst
,
5808 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5811 case FS_OPCODE_TXB_LOGICAL
:
5812 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5815 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5816 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5819 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5820 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5823 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5824 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5827 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5828 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5831 case SHADER_OPCODE_LOD_LOGICAL
:
5832 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5835 case SHADER_OPCODE_TG4_LOGICAL
:
5836 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5839 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5840 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5843 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5844 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5847 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5848 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5849 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5850 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5851 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5852 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5853 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5854 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5855 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5856 lower_surface_logical_send(ibld
, inst
);
5859 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5860 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5861 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5862 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5863 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5864 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5865 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5866 lower_a64_logical_send(ibld
, inst
);
5869 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5870 lower_varying_pull_constant_logical_send(ibld
, inst
);
5873 case SHADER_OPCODE_RCP
:
5874 case SHADER_OPCODE_RSQ
:
5875 case SHADER_OPCODE_SQRT
:
5876 case SHADER_OPCODE_EXP2
:
5877 case SHADER_OPCODE_LOG2
:
5878 case SHADER_OPCODE_SIN
:
5879 case SHADER_OPCODE_COS
:
5880 case SHADER_OPCODE_POW
:
5881 case SHADER_OPCODE_INT_QUOTIENT
:
5882 case SHADER_OPCODE_INT_REMAINDER
:
5883 /* The math opcodes are overloaded for the send-like and
5884 * expression-like instructions which seems kind of icky. Gen6+ has
5885 * a native (but rather quirky) MATH instruction so we don't need to
5886 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5887 * logical instructions (which we can easily recognize because they
5888 * have mlen = 0) into send-like virtual instructions.
5890 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5891 lower_math_logical_send(ibld
, inst
);
5906 invalidate_live_intervals();
5912 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
5914 /* This opcode sometimes uses :W type on the source even if the operand is
5915 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
5917 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
5920 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
5923 for (int i
= 0; i
< inst
->sources
; i
++) {
5924 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
5932 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
5934 /* This opcode sometimes uses :W type on the destination even if the
5935 * destination is a :HF, because in gen7 there is no support for :HF, and
5938 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
5939 inst
->dst
.stride
== 1)
5942 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
5943 inst
->dst
.stride
!= 1)
5946 for (int i
= 0; i
< inst
->sources
; i
++) {
5947 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
5955 * Get the closest allowed SIMD width for instruction \p inst accounting for
5956 * some common regioning and execution control restrictions that apply to FPU
5957 * instructions. These restrictions don't necessarily have any relevance to
5958 * instructions not executed by the FPU pipeline like extended math, control
5959 * flow or send message instructions.
5961 * For virtual opcodes it's really up to the instruction -- In some cases
5962 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
5963 * instructions) it may simplify virtual instruction lowering if we can
5964 * enforce FPU-like regioning restrictions already on the virtual instruction,
5965 * in other cases (e.g. virtual send-like instructions) this may be
5966 * excessively restrictive.
5969 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
5970 const fs_inst
*inst
)
5972 /* Maximum execution size representable in the instruction controls. */
5973 unsigned max_width
= MIN2(32, inst
->exec_size
);
5975 /* According to the PRMs:
5976 * "A. In Direct Addressing mode, a source cannot span more than 2
5977 * adjacent GRF registers.
5978 * B. A destination cannot span more than 2 adjacent GRF registers."
5980 * Look for the source or destination with the largest register region
5981 * which is the one that is going to limit the overall execution size of
5982 * the instruction due to this rule.
5984 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5986 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5987 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
5989 /* Calculate the maximum execution size of the instruction based on the
5990 * factor by which it goes over the hardware limit of 2 GRFs.
5993 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
5995 /* According to the IVB PRMs:
5996 * "When destination spans two registers, the source MUST span two
5997 * registers. The exception to the above rule:
5999 * - When source is scalar, the source registers are not incremented.
6000 * - When source is packed integer Word and destination is packed
6001 * integer DWord, the source register is not incremented but the
6002 * source sub register is incremented."
6004 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
6005 * restrictions. The code below intentionally doesn't check whether the
6006 * destination type is integer because empirically the hardware doesn't
6007 * seem to care what the actual type is as long as it's dword-aligned.
6009 if (devinfo
->gen
< 8) {
6010 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6011 /* IVB implements DF scalars as <0;2,1> regions. */
6012 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
6013 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
6014 const bool is_packed_word_exception
=
6015 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
6016 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
6018 /* We check size_read(i) against size_written instead of REG_SIZE
6019 * because we want to properly handle SIMD32. In SIMD32, you can end
6020 * up with writes to 4 registers and a source that reads 2 registers
6021 * and we may still need to lower all the way to SIMD8 in that case.
6023 if (inst
->size_written
> REG_SIZE
&&
6024 inst
->size_read(i
) != 0 &&
6025 inst
->size_read(i
) < inst
->size_written
&&
6026 !is_scalar_exception
&& !is_packed_word_exception
) {
6027 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6028 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6033 if (devinfo
->gen
< 6) {
6034 /* From the G45 PRM, Volume 4 Page 361:
6036 * "Operand Alignment Rule: With the exceptions listed below, a
6037 * source/destination operand in general should be aligned to even
6038 * 256-bit physical register with a region size equal to two 256-bit
6039 * physical registers."
6041 * Normally we enforce this by allocating virtual registers to the
6042 * even-aligned class. But we need to handle payload registers.
6044 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6045 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
6046 inst
->size_read(i
) > REG_SIZE
) {
6047 max_width
= MIN2(max_width
, 8);
6052 /* From the IVB PRMs:
6053 * "When an instruction is SIMD32, the low 16 bits of the execution mask
6054 * are applied for both halves of the SIMD32 instruction. If different
6055 * execution mask channels are required, split the instruction into two
6056 * SIMD16 instructions."
6058 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6059 * 32-wide control flow support in hardware and will behave similarly.
6061 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6062 max_width
= MIN2(max_width
, 16);
6064 /* From the IVB PRMs (applies to HSW too):
6065 * "Instructions with condition modifiers must not use SIMD32."
6067 * From the BDW PRMs (applies to later hardware too):
6068 * "Ternary instruction with condition modifiers must not use SIMD32."
6070 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6071 max_width
= MIN2(max_width
, 16);
6073 /* From the IVB PRMs (applies to other devices that don't have the
6074 * gen_device_info::supports_simd16_3src flag set):
6075 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6076 * SIMD8 is not allowed for DF operations."
6078 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6079 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6081 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6082 * the 8-bit quarter of the execution mask signals specified in the
6083 * instruction control fields) for the second compressed half of any
6084 * single-precision instruction (for double-precision instructions
6085 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6086 * the EU will apply the wrong execution controls for the second
6087 * sequential GRF write if the number of channels per GRF is not exactly
6088 * eight in single-precision mode (or four in double-float mode).
6090 * In this situation we calculate the maximum size of the split
6091 * instructions so they only ever write to a single register.
6093 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6094 !inst
->force_writemask_all
) {
6095 const unsigned channels_per_grf
= inst
->exec_size
/
6096 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6097 const unsigned exec_type_size
= get_exec_type_size(inst
);
6098 assert(exec_type_size
);
6100 /* The hardware shifts exactly 8 channels per compressed half of the
6101 * instruction in single-precision mode and exactly 4 in double-precision.
6103 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6104 max_width
= MIN2(max_width
, channels_per_grf
);
6106 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6107 * because HW applies the same channel enable signals to both halves of
6108 * the compressed instruction which will be just wrong under
6109 * non-uniform control flow.
6111 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6112 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6113 max_width
= MIN2(max_width
, 4);
6116 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6119 * "No SIMD16 in mixed mode when destination is f32. Instruction
6120 * execution size must be no more than 8."
6122 * FIXME: the simulator doesn't seem to complain if we don't do this and
6123 * empirical testing with existing CTS tests show that they pass just fine
6124 * without implementing this, however, since our interpretation of the PRM
6125 * is that conversion MOVs between HF and F are still mixed-float
6126 * instructions (and therefore subject to this restriction) we decided to
6127 * split them to be safe. Might be useful to do additional investigation to
6128 * lift the restriction if we can ensure that it is safe though, since these
6129 * conversions are common when half-float types are involved since many
6130 * instructions do not support HF types and conversions from/to F are
6133 if (is_mixed_float_with_fp32_dst(inst
))
6134 max_width
= MIN2(max_width
, 8);
6136 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6139 * "No SIMD16 in mixed mode when destination is packed f16 for both
6140 * Align1 and Align16."
6142 if (is_mixed_float_with_packed_fp16_dst(inst
))
6143 max_width
= MIN2(max_width
, 8);
6145 /* Only power-of-two execution sizes are representable in the instruction
6148 return 1 << _mesa_logbase2(max_width
);
6152 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6153 * various payload size restrictions that apply to sampler message
6156 * This is only intended to provide a maximum theoretical bound for the
6157 * execution size of the message based on the number of argument components
6158 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6159 * variant of the message can be used, though some messages may have
6160 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6161 * the message length to determine the exact SIMD width and argument count,
6162 * which makes a number of sampler message combinations impossible to
6166 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6167 const fs_inst
*inst
)
6169 /* If we have a min_lod parameter on anything other than a simple sample
6170 * message, it will push it over 5 arguments and we have to fall back to
6173 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6174 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6177 /* Calculate the number of coordinate components that have to be present
6178 * assuming that additional arguments follow the texel coordinates in the
6179 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6180 * need to pad to four or three components depending on the message,
6181 * pre-ILK we need to pad to at most three components.
6183 const unsigned req_coord_components
=
6184 (devinfo
->gen
>= 7 ||
6185 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6186 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6187 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6190 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6191 * variant of the TXL or TXF message.
6193 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6194 (inst
->opcode
== SHADER_OPCODE_TXL
||
6195 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6196 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6198 /* Calculate the total number of argument components that need to be passed
6199 * to the sampler unit.
6201 const unsigned num_payload_components
=
6202 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6203 req_coord_components
) +
6204 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6205 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6206 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6207 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6208 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6209 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6210 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6212 /* SIMD16 messages with more than five arguments exceed the maximum message
6213 * size supported by the sampler, regardless of whether a header is
6216 return MIN2(inst
->exec_size
,
6217 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6221 * Get the closest native SIMD width supported by the hardware for instruction
6222 * \p inst. The instruction will be left untouched by
6223 * fs_visitor::lower_simd_width() if the returned value is equal to the
6224 * original execution size.
6227 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6228 const fs_inst
*inst
)
6230 switch (inst
->opcode
) {
6231 case BRW_OPCODE_MOV
:
6232 case BRW_OPCODE_SEL
:
6233 case BRW_OPCODE_NOT
:
6234 case BRW_OPCODE_AND
:
6236 case BRW_OPCODE_XOR
:
6237 case BRW_OPCODE_SHR
:
6238 case BRW_OPCODE_SHL
:
6239 case BRW_OPCODE_ASR
:
6240 case BRW_OPCODE_CMPN
:
6241 case BRW_OPCODE_CSEL
:
6242 case BRW_OPCODE_F32TO16
:
6243 case BRW_OPCODE_F16TO32
:
6244 case BRW_OPCODE_BFREV
:
6245 case BRW_OPCODE_BFE
:
6246 case BRW_OPCODE_ADD
:
6247 case BRW_OPCODE_MUL
:
6248 case BRW_OPCODE_AVG
:
6249 case BRW_OPCODE_FRC
:
6250 case BRW_OPCODE_RNDU
:
6251 case BRW_OPCODE_RNDD
:
6252 case BRW_OPCODE_RNDE
:
6253 case BRW_OPCODE_RNDZ
:
6254 case BRW_OPCODE_LZD
:
6255 case BRW_OPCODE_FBH
:
6256 case BRW_OPCODE_FBL
:
6257 case BRW_OPCODE_CBIT
:
6258 case BRW_OPCODE_SAD2
:
6259 case BRW_OPCODE_MAD
:
6260 case BRW_OPCODE_LRP
:
6261 case FS_OPCODE_PACK
:
6262 case SHADER_OPCODE_SEL_EXEC
:
6263 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6264 return get_fpu_lowered_simd_width(devinfo
, inst
);
6266 case BRW_OPCODE_CMP
: {
6267 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6268 * when the destination is a GRF the dependency-clear bit on the flag
6269 * register is cleared early.
6271 * Suggested workarounds are to disable coissuing CMP instructions
6272 * or to split CMP(16) instructions into two CMP(8) instructions.
6274 * We choose to split into CMP(8) instructions since disabling
6275 * coissuing would affect CMP instructions not otherwise affected by
6278 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6279 !inst
->dst
.is_null() ? 8 : ~0);
6280 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6282 case BRW_OPCODE_BFI1
:
6283 case BRW_OPCODE_BFI2
:
6284 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6286 * "Force BFI instructions to be executed always in SIMD8."
6288 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6289 get_fpu_lowered_simd_width(devinfo
, inst
));
6292 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6293 return inst
->exec_size
;
6295 case SHADER_OPCODE_RCP
:
6296 case SHADER_OPCODE_RSQ
:
6297 case SHADER_OPCODE_SQRT
:
6298 case SHADER_OPCODE_EXP2
:
6299 case SHADER_OPCODE_LOG2
:
6300 case SHADER_OPCODE_SIN
:
6301 case SHADER_OPCODE_COS
: {
6302 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6303 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6305 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6306 return MIN2(8, inst
->exec_size
);
6307 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6308 return MIN2(8, inst
->exec_size
);
6309 return MIN2(16, inst
->exec_size
);
6312 case SHADER_OPCODE_POW
: {
6313 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6314 * to SIMD8 with half-float
6316 if (devinfo
->gen
< 7)
6317 return MIN2(8, inst
->exec_size
);
6318 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6319 return MIN2(8, inst
->exec_size
);
6320 return MIN2(16, inst
->exec_size
);
6323 case SHADER_OPCODE_INT_QUOTIENT
:
6324 case SHADER_OPCODE_INT_REMAINDER
:
6325 /* Integer division is limited to SIMD8 on all generations. */
6326 return MIN2(8, inst
->exec_size
);
6328 case FS_OPCODE_LINTERP
:
6329 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6330 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6331 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6332 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6333 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6334 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6335 return MIN2(16, inst
->exec_size
);
6337 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6338 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6339 * message used to implement varying pull constant loads, so expand it
6340 * to SIMD16. An alternative with longer message payload length but
6341 * shorter return payload would be to use the SIMD8 sampler message that
6342 * takes (header, u, v, r) as parameters instead of (header, u).
6344 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6346 case FS_OPCODE_DDX_COARSE
:
6347 case FS_OPCODE_DDX_FINE
:
6348 case FS_OPCODE_DDY_COARSE
:
6349 case FS_OPCODE_DDY_FINE
:
6350 /* The implementation of this virtual opcode may require emitting
6351 * compressed Align16 instructions, which are severely limited on some
6354 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6355 * Region Restrictions):
6357 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6358 * and SIMD8 is not allowed for DF operations."
6360 * In this context, "DW operations" means "operations acting on 32-bit
6361 * values", so it includes operations on floats.
6363 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6364 * (Instruction Compression -> Rules and Restrictions):
6366 * "A compressed instruction must be in Align1 access mode. Align16
6367 * mode instructions cannot be compressed."
6369 * Similar text exists in the g45 PRM.
6371 * Empirically, compressed align16 instructions using odd register
6372 * numbers don't appear to work on Sandybridge either.
6374 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6375 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6376 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6378 case SHADER_OPCODE_MULH
:
6379 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6380 * is 8-wide on Gen7+.
6382 return (devinfo
->gen
>= 7 ? 8 :
6383 get_fpu_lowered_simd_width(devinfo
, inst
));
6385 case FS_OPCODE_FB_WRITE_LOGICAL
:
6386 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6389 assert(devinfo
->gen
!= 6 ||
6390 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6391 inst
->exec_size
== 8);
6392 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6393 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6394 8 : MIN2(16, inst
->exec_size
));
6396 case FS_OPCODE_FB_READ_LOGICAL
:
6397 return MIN2(16, inst
->exec_size
);
6399 case SHADER_OPCODE_TEX_LOGICAL
:
6400 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6401 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6402 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6403 case SHADER_OPCODE_LOD_LOGICAL
:
6404 case SHADER_OPCODE_TG4_LOGICAL
:
6405 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6406 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6407 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6408 return get_sampler_lowered_simd_width(devinfo
, inst
);
6410 case SHADER_OPCODE_TXD_LOGICAL
:
6411 /* TXD is unsupported in SIMD16 mode. */
6414 case SHADER_OPCODE_TXL_LOGICAL
:
6415 case FS_OPCODE_TXB_LOGICAL
:
6416 /* Only one execution size is representable pre-ILK depending on whether
6417 * the shadow reference argument is present.
6419 if (devinfo
->gen
== 4)
6420 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6422 return get_sampler_lowered_simd_width(devinfo
, inst
);
6424 case SHADER_OPCODE_TXF_LOGICAL
:
6425 case SHADER_OPCODE_TXS_LOGICAL
:
6426 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6427 * messages. Use SIMD16 instead.
6429 if (devinfo
->gen
== 4)
6432 return get_sampler_lowered_simd_width(devinfo
, inst
);
6434 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6435 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6436 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6439 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6440 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6441 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6442 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6443 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6444 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6445 return MIN2(16, inst
->exec_size
);
6447 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6448 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6449 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6450 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6451 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6453 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6454 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6455 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6458 case SHADER_OPCODE_URB_READ_SIMD8
:
6459 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6460 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6461 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6462 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6463 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6464 return MIN2(8, inst
->exec_size
);
6466 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6467 const unsigned swiz
= inst
->src
[1].ud
;
6468 return (is_uniform(inst
->src
[0]) ?
6469 get_fpu_lowered_simd_width(devinfo
, inst
) :
6470 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6471 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6472 get_fpu_lowered_simd_width(devinfo
, inst
));
6474 case SHADER_OPCODE_MOV_INDIRECT
: {
6475 /* From IVB and HSW PRMs:
6477 * "2.When the destination requires two registers and the sources are
6478 * indirect, the sources must use 1x1 regioning mode.
6480 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6481 * the EU decompression logic not handling VxH indirect addressing
6484 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6485 /* Prior to Broadwell, we only have 8 address subregisters. */
6486 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6487 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6491 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6492 const unsigned reg_count
=
6493 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6495 if (reg_count
> 2) {
6496 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6497 * can be easily lowered (which excludes headers and heterogeneous
6500 assert(!inst
->header_size
);
6501 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6502 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6503 inst
->src
[i
].file
== BAD_FILE
);
6505 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6507 return inst
->exec_size
;
6511 return inst
->exec_size
;
6516 * Return true if splitting out the group of channels of instruction \p inst
6517 * given by lbld.group() requires allocating a temporary for the i-th source
6518 * of the lowered instruction.
6521 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6523 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6524 (inst
->components_read(i
) == 1 &&
6525 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6526 (inst
->flags_written() &
6527 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6531 * Extract the data that would be consumed by the channel group given by
6532 * lbld.group() from the i-th source region of instruction \p inst and return
6533 * it as result in packed form.
6536 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6538 assert(lbld
.group() >= inst
->group
);
6540 /* Specified channel group from the source region. */
6541 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6543 if (needs_src_copy(lbld
, inst
, i
)) {
6544 /* Builder of the right width to perform the copy avoiding uninitialized
6545 * data if the lowered execution size is greater than the original
6546 * execution size of the instruction.
6548 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6549 inst
->exec_size
), 0);
6550 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6552 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6553 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6557 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6558 /* The source is invariant for all dispatch_width-wide groups of the
6561 return inst
->src
[i
];
6564 /* We can just point the lowered instruction at the right channel group
6565 * from the original region.
6572 * Return true if splitting out the group of channels of instruction \p inst
6573 * given by lbld.group() requires allocating a temporary for the destination
6574 * of the lowered instruction and copying the data back to the original
6575 * destination region.
6578 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6580 /* If the instruction writes more than one component we'll have to shuffle
6581 * the results of multiple lowered instructions in order to make sure that
6582 * they end up arranged correctly in the original destination region.
6584 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6587 /* If the lowered execution size is larger than the original the result of
6588 * the instruction won't fit in the original destination, so we'll have to
6589 * allocate a temporary in any case.
6591 if (lbld
.dispatch_width() > inst
->exec_size
)
6594 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6595 /* If we already made a copy of the source for other reasons there won't
6596 * be any overlap with the destination.
6598 if (needs_src_copy(lbld
, inst
, i
))
6601 /* In order to keep the logic simple we emit a copy whenever the
6602 * destination region doesn't exactly match an overlapping source, which
6603 * may point at the source and destination not being aligned group by
6604 * group which could cause one of the lowered instructions to overwrite
6605 * the data read from the same source by other lowered instructions.
6607 if (regions_overlap(inst
->dst
, inst
->size_written
,
6608 inst
->src
[i
], inst
->size_read(i
)) &&
6609 !inst
->dst
.equals(inst
->src
[i
]))
6617 * Insert data from a packed temporary into the channel group given by
6618 * lbld.group() of the destination region of instruction \p inst and return
6619 * the temporary as result. Any copy instructions that are required for
6620 * unzipping the previous value (in the case of partial writes) will be
6621 * inserted using \p lbld_before and any copy instructions required for
6622 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6625 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6628 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6629 assert(lbld_before
.group() == lbld_after
.group());
6630 assert(lbld_after
.group() >= inst
->group
);
6632 /* Specified channel group from the destination region. */
6633 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6634 const unsigned dst_size
= inst
->size_written
/
6635 inst
->dst
.component_size(inst
->exec_size
);
6637 if (needs_dst_copy(lbld_after
, inst
)) {
6638 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6640 if (inst
->predicate
) {
6641 /* Handle predication by copying the original contents of
6642 * the destination into the temporary before emitting the
6643 * lowered instruction.
6645 const fs_builder gbld_before
=
6646 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6647 inst
->exec_size
), 0);
6648 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6649 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6650 offset(dst
, inst
->exec_size
, k
));
6654 const fs_builder gbld_after
=
6655 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6656 inst
->exec_size
), 0);
6657 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6658 /* Use a builder of the right width to perform the copy avoiding
6659 * uninitialized data if the lowered execution size is greater than
6660 * the original execution size of the instruction.
6662 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6663 offset(tmp
, lbld_after
, k
));
6669 /* No need to allocate a temporary for the lowered instruction, just
6670 * take the right group of channels from the original region.
6677 fs_visitor::lower_simd_width()
6679 bool progress
= false;
6681 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6682 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6684 if (lower_width
!= inst
->exec_size
) {
6685 /* Builder matching the original instruction. We may also need to
6686 * emit an instruction of width larger than the original, set the
6687 * execution size of the builder to the highest of both for now so
6688 * we're sure that both cases can be handled.
6690 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6691 const fs_builder ibld
= bld
.at(block
, inst
)
6692 .exec_all(inst
->force_writemask_all
)
6693 .group(max_width
, inst
->group
/ max_width
);
6695 /* Split the copies in chunks of the execution width of either the
6696 * original or the lowered instruction, whichever is lower.
6698 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6699 const unsigned dst_size
= inst
->size_written
/
6700 inst
->dst
.component_size(inst
->exec_size
);
6702 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6704 /* Inserting the zip, unzip, and duplicated instructions in all of
6705 * the right spots is somewhat tricky. All of the unzip and any
6706 * instructions from the zip which unzip the destination prior to
6707 * writing need to happen before all of the per-group instructions
6708 * and the zip instructions need to happen after. In order to sort
6709 * this all out, we insert the unzip instructions before \p inst,
6710 * insert the per-group instructions after \p inst (i.e. before
6711 * inst->next), and insert the zip instructions before the
6712 * instruction after \p inst. Since we are inserting instructions
6713 * after \p inst, inst->next is a moving target and we need to save
6714 * it off here so that we insert the zip instructions in the right
6717 * Since we're inserting split instructions after after_inst, the
6718 * instructions will end up in the reverse order that we insert them.
6719 * However, certain render target writes require that the low group
6720 * instructions come before the high group. From the Ivy Bridge PRM
6721 * Vol. 4, Pt. 1, Section 3.9.11:
6723 * "If multiple SIMD8 Dual Source messages are delivered by the
6724 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6725 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6726 * Group Select setting."
6728 * And, from Section 3.9.11.1 of the same PRM:
6730 * "When SIMD32 or SIMD16 PS threads send render target writes
6731 * with multiple SIMD8 and SIMD16 messages, the following must
6734 * All the slots (as described above) must have a corresponding
6735 * render target write irrespective of the slot's validity. A slot
6736 * is considered valid when at least one sample is enabled. For
6737 * example, a SIMD16 PS thread must send two SIMD8 render target
6738 * writes to cover all the slots.
6740 * PS thread must send SIMD render target write messages with
6741 * increasing slot numbers. For example, SIMD16 thread has
6742 * Slot[15:0] and if two SIMD8 render target writes are used, the
6743 * first SIMD8 render target write must send Slot[7:0] and the
6744 * next one must send Slot[15:8]."
6746 * In order to make low group instructions come before high group
6747 * instructions (this is required for some render target writes), we
6748 * split from the highest group to lowest.
6750 exec_node
*const after_inst
= inst
->next
;
6751 for (int i
= n
- 1; i
>= 0; i
--) {
6752 /* Emit a copy of the original instruction with the lowered width.
6753 * If the EOT flag was set throw it away except for the last
6754 * instruction to avoid killing the thread prematurely.
6756 fs_inst split_inst
= *inst
;
6757 split_inst
.exec_size
= lower_width
;
6758 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6760 /* Select the correct channel enables for the i-th group, then
6761 * transform the sources and destination and emit the lowered
6764 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6766 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6767 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6769 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6770 lbld
.at(block
, after_inst
), inst
);
6771 split_inst
.size_written
=
6772 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6774 lbld
.at(block
, inst
->next
).emit(split_inst
);
6777 inst
->remove(block
);
6783 invalidate_live_intervals();
6789 fs_visitor::dump_instructions()
6791 dump_instructions(NULL
);
6795 fs_visitor::dump_instructions(const char *name
)
6797 FILE *file
= stderr
;
6798 if (name
&& geteuid() != 0) {
6799 file
= fopen(name
, "w");
6805 calculate_register_pressure();
6806 int ip
= 0, max_pressure
= 0;
6807 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
6808 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
6809 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
6810 dump_instruction(inst
, file
);
6813 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
6816 foreach_in_list(backend_instruction
, inst
, &instructions
) {
6817 fprintf(file
, "%4d: ", ip
++);
6818 dump_instruction(inst
, file
);
6822 if (file
!= stderr
) {
6828 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
6830 dump_instruction(be_inst
, stderr
);
6834 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
6836 fs_inst
*inst
= (fs_inst
*)be_inst
;
6838 if (inst
->predicate
) {
6839 fprintf(file
, "(%cf%d.%d) ",
6840 inst
->predicate_inverse
? '-' : '+',
6841 inst
->flag_subreg
/ 2,
6842 inst
->flag_subreg
% 2);
6845 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
6847 fprintf(file
, ".sat");
6848 if (inst
->conditional_mod
) {
6849 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
6850 if (!inst
->predicate
&&
6851 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
6852 inst
->opcode
!= BRW_OPCODE_CSEL
&&
6853 inst
->opcode
!= BRW_OPCODE_IF
&&
6854 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
6855 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
6856 inst
->flag_subreg
% 2);
6859 fprintf(file
, "(%d) ", inst
->exec_size
);
6862 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
6865 if (inst
->ex_mlen
) {
6866 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
6870 fprintf(file
, "(EOT) ");
6873 switch (inst
->dst
.file
) {
6875 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
6878 fprintf(file
, "g%d", inst
->dst
.nr
);
6881 fprintf(file
, "m%d", inst
->dst
.nr
);
6884 fprintf(file
, "(null)");
6887 fprintf(file
, "***u%d***", inst
->dst
.nr
);
6890 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
6893 switch (inst
->dst
.nr
) {
6895 fprintf(file
, "null");
6897 case BRW_ARF_ADDRESS
:
6898 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
6900 case BRW_ARF_ACCUMULATOR
:
6901 fprintf(file
, "acc%d", inst
->dst
.subnr
);
6904 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6907 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6912 unreachable("not reached");
6915 if (inst
->dst
.offset
||
6916 (inst
->dst
.file
== VGRF
&&
6917 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
6918 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
6919 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
6920 inst
->dst
.offset
% reg_size
);
6923 if (inst
->dst
.stride
!= 1)
6924 fprintf(file
, "<%u>", inst
->dst
.stride
);
6925 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
6927 for (int i
= 0; i
< inst
->sources
; i
++) {
6928 if (inst
->src
[i
].negate
)
6930 if (inst
->src
[i
].abs
)
6932 switch (inst
->src
[i
].file
) {
6934 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
6937 fprintf(file
, "g%d", inst
->src
[i
].nr
);
6940 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
6943 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
6946 fprintf(file
, "u%d", inst
->src
[i
].nr
);
6949 fprintf(file
, "(null)");
6952 switch (inst
->src
[i
].type
) {
6953 case BRW_REGISTER_TYPE_F
:
6954 fprintf(file
, "%-gf", inst
->src
[i
].f
);
6956 case BRW_REGISTER_TYPE_DF
:
6957 fprintf(file
, "%fdf", inst
->src
[i
].df
);
6959 case BRW_REGISTER_TYPE_W
:
6960 case BRW_REGISTER_TYPE_D
:
6961 fprintf(file
, "%dd", inst
->src
[i
].d
);
6963 case BRW_REGISTER_TYPE_UW
:
6964 case BRW_REGISTER_TYPE_UD
:
6965 fprintf(file
, "%uu", inst
->src
[i
].ud
);
6967 case BRW_REGISTER_TYPE_Q
:
6968 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
6970 case BRW_REGISTER_TYPE_UQ
:
6971 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
6973 case BRW_REGISTER_TYPE_VF
:
6974 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
6975 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
6976 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
6977 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
6978 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
6980 case BRW_REGISTER_TYPE_V
:
6981 case BRW_REGISTER_TYPE_UV
:
6982 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
6983 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
6986 fprintf(file
, "???");
6991 switch (inst
->src
[i
].nr
) {
6993 fprintf(file
, "null");
6995 case BRW_ARF_ADDRESS
:
6996 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
6998 case BRW_ARF_ACCUMULATOR
:
6999 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7002 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7005 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7011 if (inst
->src
[i
].offset
||
7012 (inst
->src
[i
].file
== VGRF
&&
7013 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7014 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7015 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7016 inst
->src
[i
].offset
% reg_size
);
7019 if (inst
->src
[i
].abs
)
7022 if (inst
->src
[i
].file
!= IMM
) {
7024 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7025 unsigned hstride
= inst
->src
[i
].hstride
;
7026 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7028 stride
= inst
->src
[i
].stride
;
7031 fprintf(file
, "<%u>", stride
);
7033 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7036 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7037 fprintf(file
, ", ");
7042 if (inst
->force_writemask_all
)
7043 fprintf(file
, "NoMask ");
7045 if (inst
->exec_size
!= dispatch_width
)
7046 fprintf(file
, "group%d ", inst
->group
);
7048 fprintf(file
, "\n");
7052 fs_visitor::setup_fs_payload_gen6()
7054 assert(stage
== MESA_SHADER_FRAGMENT
);
7055 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7056 const unsigned payload_width
= MIN2(16, dispatch_width
);
7057 assert(dispatch_width
% payload_width
== 0);
7058 assert(devinfo
->gen
>= 6);
7060 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7061 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7063 prog_data
->uses_sample_mask
=
7064 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7066 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7068 * "MSDISPMODE_PERSAMPLE is required in order to select
7071 * So we can only really get sample positions if we are doing real
7072 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7073 * persample dispatch, we hard-code it to 0.5.
7075 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7076 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7078 /* R0: PS thread payload header. */
7081 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7082 /* R1: masks, pixel X/Y coordinates. */
7083 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7086 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7087 /* R3-26: barycentric interpolation coordinates. These appear in the
7088 * same order that they appear in the brw_barycentric_mode enum. Each
7089 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7090 * registers if dispatch width == 16. Coordinates only appear if they
7091 * were enabled using the "Barycentric Interpolation Mode" bits in
7094 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7095 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7096 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7097 payload
.num_regs
+= payload_width
/ 4;
7101 /* R27-28: interpolated depth if uses source depth */
7102 if (prog_data
->uses_src_depth
) {
7103 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7104 payload
.num_regs
+= payload_width
/ 8;
7107 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7108 if (prog_data
->uses_src_w
) {
7109 payload
.source_w_reg
[j
] = payload
.num_regs
;
7110 payload
.num_regs
+= payload_width
/ 8;
7113 /* R31: MSAA position offsets. */
7114 if (prog_data
->uses_pos_offset
) {
7115 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7119 /* R32-33: MSAA input coverage mask */
7120 if (prog_data
->uses_sample_mask
) {
7121 assert(devinfo
->gen
>= 7);
7122 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7123 payload
.num_regs
+= payload_width
/ 8;
7127 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7128 source_depth_to_render_target
= true;
7133 fs_visitor::setup_vs_payload()
7135 /* R0: thread header, R1: urb handles */
7136 payload
.num_regs
= 2;
7140 fs_visitor::setup_gs_payload()
7142 assert(stage
== MESA_SHADER_GEOMETRY
);
7144 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7145 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7147 /* R0: thread header, R1: output URB handles */
7148 payload
.num_regs
= 2;
7150 if (gs_prog_data
->include_primitive_id
) {
7151 /* R2: Primitive ID 0..7 */
7155 /* Always enable VUE handles so we can safely use pull model if needed.
7157 * The push model for a GS uses a ton of register space even for trivial
7158 * scenarios with just a few inputs, so just make things easier and a bit
7159 * safer by always having pull model available.
7161 gs_prog_data
->base
.include_vue_handles
= true;
7163 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7164 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7166 /* Use a maximum of 24 registers for push-model inputs. */
7167 const unsigned max_push_components
= 24;
7169 /* If pushing our inputs would take too many registers, reduce the URB read
7170 * length (which is in HWords, or 8 registers), and resort to pulling.
7172 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7173 * have to multiply by VerticesIn to obtain the total storage requirement.
7175 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7176 max_push_components
) {
7177 vue_prog_data
->urb_read_length
=
7178 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7183 fs_visitor::setup_cs_payload()
7185 assert(devinfo
->gen
>= 7);
7186 payload
.num_regs
= 1;
7190 fs_visitor::calculate_register_pressure()
7192 invalidate_live_intervals();
7193 calculate_live_intervals();
7195 unsigned num_instructions
= 0;
7196 foreach_block(block
, cfg
)
7197 num_instructions
+= block
->instructions
.length();
7199 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
7201 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
7202 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
7203 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
7208 fs_visitor::optimize()
7210 /* Start by validating the shader we currently have. */
7213 /* bld is the common builder object pointing at the end of the program we
7214 * used to translate it into i965 IR. For the optimization and lowering
7215 * passes coming next, any code added after the end of the program without
7216 * having explicitly called fs_builder::at() clearly points at a mistake.
7217 * Ideally optimization passes wouldn't be part of the visitor so they
7218 * wouldn't have access to bld at all, but they do, so just in case some
7219 * pass forgets to ask for a location explicitly set it to NULL here to
7220 * make it trip. The dispatch width is initialized to a bogus value to
7221 * make sure that optimizations set the execution controls explicitly to
7222 * match the code they are manipulating instead of relying on the defaults.
7224 bld
= fs_builder(this, 64);
7226 assign_constant_locations();
7227 lower_constant_loads();
7231 split_virtual_grfs();
7234 #define OPT(pass, args...) ({ \
7236 bool this_progress = pass(args); \
7238 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7239 char filename[64]; \
7240 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7241 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7243 backend_shader::dump_instructions(filename); \
7248 progress = progress || this_progress; \
7252 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7254 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7255 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7257 backend_shader::dump_instructions(filename
);
7260 bool progress
= false;
7264 /* Before anything else, eliminate dead code. The results of some NIR
7265 * instructions may effectively be calculated twice. Once when the
7266 * instruction is encountered, and again when the user of that result is
7267 * encountered. Wipe those away before algebraic optimizations and
7268 * especially copy propagation can mix things up.
7270 OPT(dead_code_eliminate
);
7272 OPT(remove_extra_rounding_modes
);
7279 OPT(remove_duplicate_mrf_writes
);
7283 OPT(opt_copy_propagation
);
7284 OPT(opt_predicated_break
, this);
7285 OPT(opt_cmod_propagation
);
7286 OPT(dead_code_eliminate
);
7287 OPT(opt_peephole_sel
);
7288 OPT(dead_control_flow_eliminate
, this);
7289 OPT(opt_register_renaming
);
7290 OPT(opt_saturate_propagation
);
7291 OPT(register_coalesce
);
7292 OPT(compute_to_mrf
);
7293 OPT(eliminate_find_live_channel
);
7295 OPT(compact_virtual_grfs
);
7298 /* Do this after cmod propagation has had every possible opportunity to
7299 * propagate results into SEL instructions.
7301 if (OPT(opt_peephole_csel
))
7302 OPT(dead_code_eliminate
);
7307 if (OPT(lower_pack
)) {
7308 OPT(register_coalesce
);
7309 OPT(dead_code_eliminate
);
7312 OPT(lower_simd_width
);
7314 /* After SIMD lowering just in case we had to unroll the EOT send. */
7315 OPT(opt_sampler_eot
);
7317 OPT(lower_logical_sends
);
7320 OPT(opt_copy_propagation
);
7321 /* Only run after logical send lowering because it's easier to implement
7322 * in terms of physical sends.
7324 if (OPT(opt_zero_samples
))
7325 OPT(opt_copy_propagation
);
7326 /* Run after logical send lowering to give it a chance to CSE the
7327 * LOAD_PAYLOAD instructions created to construct the payloads of
7328 * e.g. texturing messages in cases where it wasn't possible to CSE the
7329 * whole logical instruction.
7332 OPT(register_coalesce
);
7333 OPT(compute_to_mrf
);
7334 OPT(dead_code_eliminate
);
7335 OPT(remove_duplicate_mrf_writes
);
7336 OPT(opt_peephole_sel
);
7339 OPT(opt_redundant_discard_jumps
);
7341 if (OPT(lower_load_payload
)) {
7342 split_virtual_grfs();
7343 OPT(register_coalesce
);
7344 OPT(lower_simd_width
);
7345 OPT(compute_to_mrf
);
7346 OPT(dead_code_eliminate
);
7349 OPT(opt_combine_constants
);
7350 OPT(lower_integer_multiplication
);
7352 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7353 OPT(opt_cmod_propagation
);
7355 OPT(opt_copy_propagation
);
7356 OPT(dead_code_eliminate
);
7359 if (OPT(lower_regioning
)) {
7360 OPT(opt_copy_propagation
);
7361 OPT(dead_code_eliminate
);
7362 OPT(lower_simd_width
);
7365 OPT(fixup_sends_duplicate_payload
);
7367 lower_uniform_pull_constant_loads();
7373 * From the Skylake PRM Vol. 2a docs for sends:
7375 * "It is required that the second block of GRFs does not overlap with the
7378 * There are plenty of cases where we may accidentally violate this due to
7379 * having, for instance, both sources be the constant 0. This little pass
7380 * just adds a new vgrf for the second payload and copies it over.
7383 fs_visitor::fixup_sends_duplicate_payload()
7385 bool progress
= false;
7387 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7388 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7389 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7390 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7391 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7392 BRW_REGISTER_TYPE_UD
);
7393 /* Sadly, we've lost all notion of channels and bit sizes at this
7394 * point. Just WE_all it.
7396 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7397 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7398 fs_reg copy_dst
= tmp
;
7399 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7400 if (inst
->ex_mlen
== i
+ 1) {
7401 /* Only one register left; do SIMD8 */
7402 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7404 ibld
.MOV(copy_dst
, copy_src
);
7406 copy_src
= offset(copy_src
, ibld
, 1);
7407 copy_dst
= offset(copy_dst
, ibld
, 1);
7415 invalidate_live_intervals();
7421 * Three source instruction must have a GRF/MRF destination register.
7422 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7425 fs_visitor::fixup_3src_null_dest()
7427 bool progress
= false;
7429 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7430 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7431 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7438 invalidate_live_intervals();
7442 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
7446 static const enum instruction_scheduler_mode pre_modes
[] = {
7448 SCHEDULE_PRE_NON_LIFO
,
7452 static const char *scheduler_mode_name
[] = {
7458 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7460 /* Try each scheduling heuristic to see if it can successfully register
7461 * allocate without spilling. They should be ordered by decreasing
7462 * performance but increasing likelihood of allocating.
7464 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7465 schedule_instructions(pre_modes
[i
]);
7466 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7469 assign_regs_trivial();
7474 /* We only allow spilling for the last schedule mode and only if the
7475 * allow_spilling parameter and dispatch width work out ok.
7477 bool can_spill
= allow_spilling
&&
7478 (i
== ARRAY_SIZE(pre_modes
) - 1) &&
7479 dispatch_width
== min_dispatch_width
;
7481 /* We should only spill registers on the last scheduling. */
7482 assert(!spilled_any_registers
);
7484 allocated
= assign_regs(can_spill
, spill_all
);
7490 if (!allow_spilling
)
7491 fail("Failure to register allocate and spilling is not allowed.");
7493 /* We assume that any spilling is worse than just dropping back to
7494 * SIMD8. There's probably actually some intermediate point where
7495 * SIMD16 with a couple of spills is still better.
7497 if (dispatch_width
> min_dispatch_width
) {
7498 fail("Failure to register allocate. Reduce number of "
7499 "live scalar values to avoid this.");
7502 /* If we failed to allocate, we must have a reason */
7504 } else if (spilled_any_registers
) {
7505 compiler
->shader_perf_log(log_data
,
7506 "%s shader triggered register spilling. "
7507 "Try reducing the number of live scalar "
7508 "values to improve performance.\n",
7512 /* This must come after all optimization and register allocation, since
7513 * it inserts dead code that happens to have side effects, and it does
7514 * so based on the actual physical registers in use.
7516 insert_gen4_send_dependency_workarounds();
7521 opt_bank_conflicts();
7523 schedule_instructions(SCHEDULE_POST
);
7525 if (last_scratch
> 0) {
7526 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7528 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7530 if (stage
== MESA_SHADER_COMPUTE
) {
7531 if (devinfo
->is_haswell
) {
7532 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7533 * field documentation, Haswell supports a minimum of 2kB of
7534 * scratch space for compute shaders, unlike every other stage
7537 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7538 } else if (devinfo
->gen
<= 7) {
7539 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7540 * field documentation, platforms prior to Haswell measure scratch
7541 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7543 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7544 max_scratch_size
= 12 * 1024;
7548 /* We currently only support up to 2MB of scratch space. If we
7549 * need to support more eventually, the documentation suggests
7550 * that we could allocate a larger buffer, and partition it out
7551 * ourselves. We'd just have to undo the hardware's address
7552 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7553 * and then add FFTID * (Larger Per Thread Scratch Space).
7555 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7556 * Thread Group Tracking > Local Memory/Scratch Space.
7558 assert(prog_data
->total_scratch
< max_scratch_size
);
7563 fs_visitor::run_vs()
7565 assert(stage
== MESA_SHADER_VERTEX
);
7569 if (shader_time_index
>= 0)
7570 emit_shader_time_begin();
7579 if (shader_time_index
>= 0)
7580 emit_shader_time_end();
7586 assign_curb_setup();
7587 assign_vs_urb_setup();
7589 fixup_3src_null_dest();
7590 allocate_registers(8, true);
7596 fs_visitor::set_tcs_invocation_id()
7598 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7599 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7601 const unsigned instance_id_mask
=
7602 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7603 const unsigned instance_id_shift
=
7604 devinfo
->gen
>= 11 ? 16 : 17;
7606 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7607 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7608 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7609 brw_imm_ud(instance_id_mask
));
7611 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7613 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7614 /* gl_InvocationID is just the thread number */
7615 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7619 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7621 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7622 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7623 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7624 bld
.MOV(channels_ud
, channels_uw
);
7626 if (tcs_prog_data
->instances
== 1) {
7627 invocation_id
= channels_ud
;
7629 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7630 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
7631 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
7636 fs_visitor::run_tcs()
7638 assert(stage
== MESA_SHADER_TESS_CTRL
);
7640 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7641 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7642 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
7644 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
7645 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7647 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
7648 /* r1-r4 contain the ICP handles. */
7649 payload
.num_regs
= 5;
7651 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7652 assert(tcs_key
->input_vertices
> 0);
7653 /* r1 contains output handles, r2 may contain primitive ID, then the
7654 * ICP handles occupy the next 1-32 registers.
7656 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
7657 tcs_key
->input_vertices
;
7660 if (shader_time_index
>= 0)
7661 emit_shader_time_begin();
7663 /* Initialize gl_InvocationID */
7664 set_tcs_invocation_id();
7666 const bool fix_dispatch_mask
=
7667 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
7668 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
7670 /* Fix the disptach mask */
7671 if (fix_dispatch_mask
) {
7672 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
7673 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
7674 bld
.IF(BRW_PREDICATE_NORMAL
);
7679 if (fix_dispatch_mask
) {
7680 bld
.emit(BRW_OPCODE_ENDIF
);
7683 /* Emit EOT write; set TR DS Cache bit */
7685 fs_reg(get_tcs_output_urb_handle()),
7686 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
7687 fs_reg(brw_imm_ud(0)),
7689 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
7690 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
7692 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
7693 bld
.null_reg_ud(), payload
);
7697 if (shader_time_index
>= 0)
7698 emit_shader_time_end();
7707 assign_curb_setup();
7708 assign_tcs_urb_setup();
7710 fixup_3src_null_dest();
7711 allocate_registers(8, true);
7717 fs_visitor::run_tes()
7719 assert(stage
== MESA_SHADER_TESS_EVAL
);
7721 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
7722 payload
.num_regs
= 5;
7724 if (shader_time_index
>= 0)
7725 emit_shader_time_begin();
7734 if (shader_time_index
>= 0)
7735 emit_shader_time_end();
7741 assign_curb_setup();
7742 assign_tes_urb_setup();
7744 fixup_3src_null_dest();
7745 allocate_registers(8, true);
7751 fs_visitor::run_gs()
7753 assert(stage
== MESA_SHADER_GEOMETRY
);
7757 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
7759 if (gs_compile
->control_data_header_size_bits
> 0) {
7760 /* Create a VGRF to store accumulated control data bits. */
7761 this->control_data_bits
= vgrf(glsl_type::uint_type
);
7763 /* If we're outputting more than 32 control data bits, then EmitVertex()
7764 * will set control_data_bits to 0 after emitting the first vertex.
7765 * Otherwise, we need to initialize it to 0 here.
7767 if (gs_compile
->control_data_header_size_bits
<= 32) {
7768 const fs_builder abld
= bld
.annotate("initialize control data bits");
7769 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
7773 if (shader_time_index
>= 0)
7774 emit_shader_time_begin();
7778 emit_gs_thread_end();
7780 if (shader_time_index
>= 0)
7781 emit_shader_time_end();
7790 assign_curb_setup();
7791 assign_gs_urb_setup();
7793 fixup_3src_null_dest();
7794 allocate_registers(8, true);
7799 /* From the SKL PRM, Volume 16, Workarounds:
7801 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
7802 * only header phases (R0-R2)
7804 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
7805 * have been header only.
7807 * Instead of enabling push constants one can alternatively enable one of the
7808 * inputs. Here one simply chooses "layer" which shouldn't impose much
7812 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
7814 if (wm_prog_data
->num_varying_inputs
)
7817 if (wm_prog_data
->base
.curb_read_length
)
7820 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
7821 wm_prog_data
->num_varying_inputs
= 1;
7825 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
7827 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
7828 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
7830 assert(stage
== MESA_SHADER_FRAGMENT
);
7832 if (devinfo
->gen
>= 6)
7833 setup_fs_payload_gen6();
7835 setup_fs_payload_gen4();
7839 } else if (do_rep_send
) {
7840 assert(dispatch_width
== 16);
7841 emit_repclear_shader();
7843 if (shader_time_index
>= 0)
7844 emit_shader_time_begin();
7846 if (nir
->info
.inputs_read
> 0 ||
7847 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
7848 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
7849 if (devinfo
->gen
< 6)
7850 emit_interpolation_setup_gen4();
7852 emit_interpolation_setup_gen6();
7855 /* We handle discards by keeping track of the still-live pixels in f0.1.
7856 * Initialize it with the dispatched pixels.
7858 if (wm_prog_data
->uses_kill
) {
7859 const fs_reg dispatch_mask
=
7860 devinfo
->gen
>= 6 ? brw_vec1_grf(1, 7) : brw_vec1_grf(0, 0);
7861 bld
.exec_all().group(1, 0)
7862 .MOV(retype(brw_flag_reg(0, 1), BRW_REGISTER_TYPE_UW
),
7863 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
7871 if (wm_prog_data
->uses_kill
)
7872 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
7874 if (wm_key
->alpha_test_func
)
7879 if (shader_time_index
>= 0)
7880 emit_shader_time_end();
7886 assign_curb_setup();
7888 if (devinfo
->gen
>= 9)
7889 gen9_ps_header_only_workaround(wm_prog_data
);
7893 fixup_3src_null_dest();
7894 allocate_registers(8, allow_spilling
);
7904 fs_visitor::run_cs(unsigned min_dispatch_width
)
7906 assert(stage
== MESA_SHADER_COMPUTE
);
7907 assert(dispatch_width
>= min_dispatch_width
);
7911 if (shader_time_index
>= 0)
7912 emit_shader_time_begin();
7914 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
7915 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
7916 const fs_builder abld
= bld
.exec_all().group(1, 0);
7917 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
7918 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
7926 emit_cs_terminate();
7928 if (shader_time_index
>= 0)
7929 emit_shader_time_end();
7935 assign_curb_setup();
7937 fixup_3src_null_dest();
7938 allocate_registers(min_dispatch_width
, true);
7947 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
7949 nir_foreach_use(src
, def
) {
7950 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
7953 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
7954 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
7958 nir_foreach_if_use(src
, def
)
7965 * Return a bitfield where bit n is set if barycentric interpolation mode n
7966 * (see enum brw_barycentric_mode) is needed by the fragment shader.
7968 * We examine the load_barycentric intrinsics rather than looking at input
7969 * variables so that we catch interpolateAtCentroid() messages too, which
7970 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
7973 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
7974 const nir_shader
*shader
)
7976 unsigned barycentric_interp_modes
= 0;
7978 nir_foreach_function(f
, shader
) {
7982 nir_foreach_block(block
, f
->impl
) {
7983 nir_foreach_instr(instr
, block
) {
7984 if (instr
->type
!= nir_instr_type_intrinsic
)
7987 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
7988 switch (intrin
->intrinsic
) {
7989 case nir_intrinsic_load_barycentric_pixel
:
7990 case nir_intrinsic_load_barycentric_centroid
:
7991 case nir_intrinsic_load_barycentric_sample
:
7997 /* Ignore WPOS; it doesn't require interpolation. */
7998 assert(intrin
->dest
.is_ssa
);
7999 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8002 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8003 nir_intrinsic_interp_mode(intrin
);
8004 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8005 enum brw_barycentric_mode bary
=
8006 brw_barycentric_mode(interp
, bary_op
);
8008 barycentric_interp_modes
|= 1 << bary
;
8010 if (devinfo
->needs_unlit_centroid_workaround
&&
8011 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8012 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8017 return barycentric_interp_modes
;
8021 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8022 const nir_shader
*shader
)
8024 prog_data
->flat_inputs
= 0;
8026 nir_foreach_variable(var
, &shader
->inputs
) {
8027 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8028 for (unsigned s
= 0; s
< slots
; s
++) {
8029 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8031 if (input_index
< 0)
8035 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8036 prog_data
->flat_inputs
|= 1 << input_index
;
8042 computed_depth_mode(const nir_shader
*shader
)
8044 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8045 switch (shader
->info
.fs
.depth_layout
) {
8046 case FRAG_DEPTH_LAYOUT_NONE
:
8047 case FRAG_DEPTH_LAYOUT_ANY
:
8048 return BRW_PSCDEPTH_ON
;
8049 case FRAG_DEPTH_LAYOUT_GREATER
:
8050 return BRW_PSCDEPTH_ON_GE
;
8051 case FRAG_DEPTH_LAYOUT_LESS
:
8052 return BRW_PSCDEPTH_ON_LE
;
8053 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8054 return BRW_PSCDEPTH_OFF
;
8057 return BRW_PSCDEPTH_OFF
;
8061 * Move load_interpolated_input with simple (payload-based) barycentric modes
8062 * to the top of the program so we don't emit multiple PLNs for the same input.
8064 * This works around CSE not being able to handle non-dominating cases
8070 * interpolate the same exact input
8073 * This should be replaced by global value numbering someday.
8076 move_interpolation_to_top(nir_shader
*nir
)
8078 bool progress
= false;
8080 nir_foreach_function(f
, nir
) {
8084 nir_block
*top
= nir_start_block(f
->impl
);
8085 exec_node
*cursor_node
= NULL
;
8087 nir_foreach_block(block
, f
->impl
) {
8091 nir_foreach_instr_safe(instr
, block
) {
8092 if (instr
->type
!= nir_instr_type_intrinsic
)
8095 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8096 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8098 nir_intrinsic_instr
*bary_intrinsic
=
8099 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8100 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8102 /* Leave interpolateAtSample/Offset() where they are. */
8103 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8104 op
== nir_intrinsic_load_barycentric_at_offset
)
8107 nir_instr
*move
[3] = {
8108 &bary_intrinsic
->instr
,
8109 intrin
->src
[1].ssa
->parent_instr
,
8113 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8114 if (move
[i
]->block
!= top
) {
8115 move
[i
]->block
= top
;
8116 exec_node_remove(&move
[i
]->node
);
8118 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8120 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8122 cursor_node
= &move
[i
]->node
;
8128 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8129 ((unsigned) nir_metadata_block_index
|
8130 (unsigned) nir_metadata_dominance
));
8137 * Demote per-sample barycentric intrinsics to centroid.
8139 * Useful when rendering to a non-multisampled buffer.
8142 demote_sample_qualifiers(nir_shader
*nir
)
8144 bool progress
= true;
8146 nir_foreach_function(f
, nir
) {
8151 nir_builder_init(&b
, f
->impl
);
8153 nir_foreach_block(block
, f
->impl
) {
8154 nir_foreach_instr_safe(instr
, block
) {
8155 if (instr
->type
!= nir_instr_type_intrinsic
)
8158 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8159 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8160 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8163 b
.cursor
= nir_before_instr(instr
);
8164 nir_ssa_def
*centroid
=
8165 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8166 nir_intrinsic_interp_mode(intrin
));
8167 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8168 nir_src_for_ssa(centroid
));
8169 nir_instr_remove(instr
);
8174 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8175 ((unsigned) nir_metadata_block_index
|
8176 (unsigned) nir_metadata_dominance
));
8183 * Pre-gen6, the register file of the EUs was shared between threads,
8184 * and each thread used some subset allocated on a 16-register block
8185 * granularity. The unit states wanted these block counts.
8188 brw_register_blocks(int reg_count
)
8190 return ALIGN(reg_count
, 16) / 16 - 1;
8194 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8196 const struct brw_wm_prog_key
*key
,
8197 struct brw_wm_prog_data
*prog_data
,
8199 int shader_time_index8
, int shader_time_index16
,
8200 int shader_time_index32
, bool allow_spilling
,
8201 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8202 struct brw_compile_stats
*stats
,
8205 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8207 unsigned max_subgroup_size
= unlikely(INTEL_DEBUG
& DEBUG_DO32
) ? 32 : 16;
8209 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8210 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8211 brw_nir_lower_fs_outputs(shader
);
8213 if (devinfo
->gen
< 6)
8214 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8216 if (!key
->multisample_fbo
)
8217 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8218 NIR_PASS_V(shader
, move_interpolation_to_top
);
8219 brw_postprocess_nir(shader
, compiler
, true);
8221 /* key->alpha_test_func means simulating alpha testing via discards,
8222 * so the shader definitely kills pixels.
8224 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8225 key
->alpha_test_func
;
8226 prog_data
->uses_omask
= key
->multisample_fbo
&&
8227 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8228 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8229 prog_data
->computed_stencil
=
8230 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8232 prog_data
->persample_dispatch
=
8233 key
->multisample_fbo
&&
8234 (key
->persample_interp
||
8235 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8236 SYSTEM_BIT_SAMPLE_POS
)) ||
8237 shader
->info
.fs
.uses_sample_qualifier
||
8238 shader
->info
.outputs_read
);
8240 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8242 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8243 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8244 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8246 prog_data
->barycentric_interp_modes
=
8247 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8249 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8250 brw_compute_flat_inputs(prog_data
, shader
);
8252 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8254 fs_visitor
v8(compiler
, log_data
, mem_ctx
, &key
->base
,
8255 &prog_data
->base
, shader
, 8,
8256 shader_time_index8
);
8257 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
8259 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
8262 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8264 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
8265 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
8268 if (v8
.max_dispatch_width
>= 16 &&
8269 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8270 /* Try a SIMD16 compile */
8271 fs_visitor
v16(compiler
, log_data
, mem_ctx
, &key
->base
,
8272 &prog_data
->base
, shader
, 16,
8273 shader_time_index16
);
8274 v16
.import_uniforms(&v8
);
8275 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
8276 compiler
->shader_perf_log(log_data
,
8277 "SIMD16 shader failed to compile: %s",
8280 simd16_cfg
= v16
.cfg
;
8281 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
8282 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
8286 /* Currently, the compiler only supports SIMD32 on SNB+ */
8287 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
8288 compiler
->devinfo
->gen
>= 6 &&
8289 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
8290 /* Try a SIMD32 compile */
8291 fs_visitor
v32(compiler
, log_data
, mem_ctx
, &key
->base
,
8292 &prog_data
->base
, shader
, 32,
8293 shader_time_index32
);
8294 v32
.import_uniforms(&v8
);
8295 if (!v32
.run_fs(allow_spilling
, false)) {
8296 compiler
->shader_perf_log(log_data
,
8297 "SIMD32 shader failed to compile: %s",
8300 simd32_cfg
= v32
.cfg
;
8301 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
8302 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
8306 /* When the caller requests a repclear shader, they want SIMD16-only */
8310 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8311 * at the top to select the shader. We've never implemented that.
8312 * Instead, we just give them exactly one shader and we pick the widest one
8315 if (compiler
->devinfo
->gen
< 5) {
8316 if (simd32_cfg
|| simd16_cfg
)
8322 /* If computed depth is enabled SNB only allows SIMD8. */
8323 if (compiler
->devinfo
->gen
== 6 &&
8324 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8325 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8327 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8328 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8329 * the data available in the base prog data struct for convenience.
8332 prog_data
->base
.dispatch_grf_start_reg
=
8333 prog_data
->dispatch_grf_start_reg_16
;
8334 } else if (simd32_cfg
) {
8335 prog_data
->base
.dispatch_grf_start_reg
=
8336 prog_data
->dispatch_grf_start_reg_32
;
8340 if (prog_data
->persample_dispatch
) {
8341 /* Starting with SandyBridge (where we first get MSAA), the different
8342 * pixel dispatch combinations are grouped into classifications A
8343 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
8344 * generations, the only configurations supporting persample dispatch
8345 * are are this in which only one dispatch width is enabled.
8347 if (simd32_cfg
|| simd16_cfg
)
8353 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8354 v8
.shader_stats
, v8
.runtime_check_aads_emit
,
8355 MESA_SHADER_FRAGMENT
);
8357 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8358 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8359 shader
->info
.label
?
8360 shader
->info
.label
: "unnamed",
8361 shader
->info
.name
));
8365 prog_data
->dispatch_8
= true;
8366 g
.generate_code(simd8_cfg
, 8, stats
);
8367 stats
= stats
? stats
+ 1 : NULL
;
8371 prog_data
->dispatch_16
= true;
8372 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16, stats
);
8373 stats
= stats
? stats
+ 1 : NULL
;
8377 prog_data
->dispatch_32
= true;
8378 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32, stats
);
8379 stats
= stats
? stats
+ 1 : NULL
;
8382 return g
.get_assembly();
8386 fs_visitor::emit_cs_work_group_id_setup()
8388 assert(stage
== MESA_SHADER_COMPUTE
);
8390 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8392 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8393 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8394 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8396 bld
.MOV(*reg
, r0_1
);
8397 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8398 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8404 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8406 block
->dwords
= dwords
;
8407 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8408 block
->size
= block
->regs
* 32;
8412 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8413 struct brw_cs_prog_data
*cs_prog_data
)
8415 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8416 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8417 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8419 /* The thread ID should be stored in the last param dword */
8420 assert(subgroup_id_index
== -1 ||
8421 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8423 unsigned cross_thread_dwords
, per_thread_dwords
;
8424 if (!cross_thread_supported
) {
8425 cross_thread_dwords
= 0u;
8426 per_thread_dwords
= prog_data
->nr_params
;
8427 } else if (subgroup_id_index
>= 0) {
8428 /* Fill all but the last register with cross-thread payload */
8429 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8430 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8431 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8433 /* Fill all data using cross-thread payload */
8434 cross_thread_dwords
= prog_data
->nr_params
;
8435 per_thread_dwords
= 0u;
8438 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8439 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8441 unsigned total_dwords
=
8442 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
8443 cs_prog_data
->push
.cross_thread
.size
) / 4;
8444 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
8446 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8447 cs_prog_data
->push
.per_thread
.size
== 0);
8448 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8449 cs_prog_data
->push
.per_thread
.dwords
==
8450 prog_data
->nr_params
);
8454 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
8456 cs_prog_data
->simd_size
= size
;
8457 unsigned group_size
= cs_prog_data
->local_size
[0] *
8458 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
8459 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
8463 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8465 const struct brw_cs_prog_key
*key
,
8466 const nir_shader
*src_shader
,
8467 unsigned dispatch_width
)
8469 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8470 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8472 NIR_PASS_V(shader
, brw_nir_lower_cs_intrinsics
, dispatch_width
);
8474 /* Clean up after the local index and ID calculations. */
8475 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8476 NIR_PASS_V(shader
, nir_opt_dce
);
8478 brw_postprocess_nir(shader
, compiler
, true);
8484 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8486 const struct brw_cs_prog_key
*key
,
8487 struct brw_cs_prog_data
*prog_data
,
8488 const nir_shader
*src_shader
,
8489 int shader_time_index
,
8490 struct brw_compile_stats
*stats
,
8493 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8494 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8495 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8496 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8497 prog_data
->slm_size
= src_shader
->num_shared
;
8498 unsigned local_workgroup_size
=
8499 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
8500 src_shader
->info
.cs
.local_size
[2];
8502 unsigned min_dispatch_width
=
8503 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
8504 min_dispatch_width
= MAX2(8, min_dispatch_width
);
8505 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
8506 assert(min_dispatch_width
<= 32);
8507 unsigned max_dispatch_width
= 32;
8509 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8510 fs_visitor
*v
= NULL
;
8511 const char *fail_msg
= NULL
;
8513 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8514 /* These enum values are expressly chosen to be equal to the subgroup
8515 * size that they require.
8517 const unsigned required_dispatch_width
=
8518 (unsigned)key
->base
.subgroup_size_type
;
8519 assert(required_dispatch_width
== 8 ||
8520 required_dispatch_width
== 16 ||
8521 required_dispatch_width
== 32);
8522 if (required_dispatch_width
< min_dispatch_width
||
8523 required_dispatch_width
> max_dispatch_width
) {
8524 fail_msg
= "Cannot satisfy explicit subgroup size";
8526 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8530 /* Now the main event: Visit the shader IR and generate our CS IR for it.
8532 if (!fail_msg
&& min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8533 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8535 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8537 nir8
, 8, shader_time_index
);
8538 if (!v8
->run_cs(min_dispatch_width
)) {
8539 fail_msg
= v8
->fail_msg
;
8541 /* We should always be able to do SIMD32 for compute shaders */
8542 assert(v8
->max_dispatch_width
>= 32);
8545 cs_set_simd_size(prog_data
, 8);
8546 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8550 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
8551 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
8552 /* Try a SIMD16 compile */
8553 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8555 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8557 nir16
, 16, shader_time_index
);
8559 v16
->import_uniforms(v8
);
8561 if (!v16
->run_cs(min_dispatch_width
)) {
8562 compiler
->shader_perf_log(log_data
,
8563 "SIMD16 shader failed to compile: %s",
8567 "Couldn't generate SIMD16 program and not "
8568 "enough threads for SIMD8";
8571 /* We should always be able to do SIMD32 for compute shaders */
8572 assert(v16
->max_dispatch_width
>= 32);
8575 cs_set_simd_size(prog_data
, 16);
8576 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8580 /* We should always be able to do SIMD32 for compute shaders */
8581 assert(!v16
|| v16
->max_dispatch_width
>= 32);
8583 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
8584 max_dispatch_width
>= 32) {
8585 /* Try a SIMD32 compile */
8586 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8588 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8590 nir32
, 32, shader_time_index
);
8592 v32
->import_uniforms(v8
);
8594 v32
->import_uniforms(v16
);
8596 if (!v32
->run_cs(min_dispatch_width
)) {
8597 compiler
->shader_perf_log(log_data
,
8598 "SIMD32 shader failed to compile: %s",
8602 "Couldn't generate SIMD32 program and not "
8603 "enough threads for SIMD16";
8607 cs_set_simd_size(prog_data
, 32);
8608 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8612 const unsigned *ret
= NULL
;
8613 if (unlikely(v
== NULL
)) {
8616 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
8618 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8619 v
->shader_stats
, v
->runtime_check_aads_emit
,
8620 MESA_SHADER_COMPUTE
);
8621 if (INTEL_DEBUG
& DEBUG_CS
) {
8622 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
8623 src_shader
->info
.label
?
8624 src_shader
->info
.label
: "unnamed",
8625 src_shader
->info
.name
);
8626 g
.enable_debug(name
);
8629 g
.generate_code(v
->cfg
, prog_data
->simd_size
, stats
);
8631 ret
= g
.get_assembly();
8642 * Test the dispatch mask packing assumptions of
8643 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
8644 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
8645 * executed with an unexpected dispatch mask.
8648 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
8650 const gl_shader_stage stage
= bld
.shader
->stage
;
8652 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
8653 bld
.shader
->stage_prog_data
)) {
8654 const fs_builder ubld
= bld
.exec_all().group(1, 0);
8655 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
8656 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
8659 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
8660 ubld
.AND(tmp
, mask
, tmp
);
8662 /* This will loop forever if the dispatch mask doesn't have the expected
8663 * form '2^n-1', in which case tmp will be non-zero.
8665 bld
.emit(BRW_OPCODE_DO
);
8666 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
8667 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));