2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "dev/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
42 #include "util/u_math.h"
46 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
50 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
51 const fs_reg
*src
, unsigned sources
)
53 memset((void*)this, 0, sizeof(*this));
55 this->src
= new fs_reg
[MAX2(sources
, 3)];
56 for (unsigned i
= 0; i
< sources
; i
++)
57 this->src
[i
] = src
[i
];
59 this->opcode
= opcode
;
61 this->sources
= sources
;
62 this->exec_size
= exec_size
;
65 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
67 assert(this->exec_size
!= 0);
69 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
71 /* This will be the case for almost all instructions. */
78 this->size_written
= dst
.component_size(exec_size
);
81 this->size_written
= 0;
85 unreachable("Invalid destination register file");
88 this->writes_accumulator
= false;
93 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
96 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
98 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
101 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
103 init(opcode
, exec_size
, dst
, NULL
, 0);
106 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
109 const fs_reg src
[1] = { src0
};
110 init(opcode
, exec_size
, dst
, src
, 1);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
114 const fs_reg
&src0
, const fs_reg
&src1
)
116 const fs_reg src
[2] = { src0
, src1
};
117 init(opcode
, exec_size
, dst
, src
, 2);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
123 const fs_reg src
[3] = { src0
, src1
, src2
};
124 init(opcode
, exec_size
, dst
, src
, 3);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
128 const fs_reg src
[], unsigned sources
)
130 init(opcode
, exec_width
, dst
, src
, sources
);
133 fs_inst::fs_inst(const fs_inst
&that
)
135 memcpy((void*)this, &that
, sizeof(that
));
137 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
139 for (unsigned i
= 0; i
< that
.sources
; i
++)
140 this->src
[i
] = that
.src
[i
];
149 fs_inst::resize_sources(uint8_t num_sources
)
151 if (this->sources
!= num_sources
) {
152 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
154 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
155 src
[i
] = this->src
[i
];
159 this->sources
= num_sources
;
164 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
166 const fs_reg
&surf_index
,
167 const fs_reg
&varying_offset
,
168 uint32_t const_offset
)
170 /* We have our constant surface use a pitch of 4 bytes, so our index can
171 * be any component of a vector, and then we load 4 contiguous
172 * components starting from that.
174 * We break down the const_offset to a portion added to the variable offset
175 * and a portion done using fs_reg::offset, which means that if you have
176 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
177 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
178 * later notice that those loads are all the same and eliminate the
181 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
182 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
184 /* The pull load message will load a vec4 (16 bytes). If we are loading
185 * a double this means we are only loading 2 elements worth of data.
186 * We also want to use a 32-bit data type for the dst of the load operation
187 * so other parts of the driver don't get confused about the size of the
190 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
191 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
192 vec4_result
, surf_index
, vec4_offset
);
193 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
195 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
196 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
200 * A helper for MOV generation for fixing up broken hardware SEND dependency
204 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
206 /* The caller always wants uncompressed to emit the minimal extra
207 * dependencies, and to avoid having to deal with aligning its regs to 2.
209 const fs_builder ubld
= bld
.annotate("send dependency resolve")
212 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
216 fs_inst::is_send_from_grf() const
219 case SHADER_OPCODE_SEND
:
220 case SHADER_OPCODE_SHADER_TIME_ADD
:
221 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
222 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
223 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
224 case SHADER_OPCODE_URB_WRITE_SIMD8
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
228 case SHADER_OPCODE_URB_READ_SIMD8
:
229 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
230 case SHADER_OPCODE_INTERLOCK
:
231 case SHADER_OPCODE_MEMORY_FENCE
:
232 case SHADER_OPCODE_BARRIER
:
234 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
235 return src
[1].file
== VGRF
;
236 case FS_OPCODE_FB_WRITE
:
237 case FS_OPCODE_FB_READ
:
238 return src
[0].file
== VGRF
;
241 return src
[0].file
== VGRF
;
248 fs_inst::is_control_source(unsigned arg
) const
251 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
253 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
256 case SHADER_OPCODE_BROADCAST
:
257 case SHADER_OPCODE_SHUFFLE
:
258 case SHADER_OPCODE_QUAD_SWIZZLE
:
259 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
261 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
262 case SHADER_OPCODE_GET_BUFFER_SIZE
:
265 case SHADER_OPCODE_MOV_INDIRECT
:
266 case SHADER_OPCODE_CLUSTER_BROADCAST
:
267 case SHADER_OPCODE_TEX
:
269 case SHADER_OPCODE_TXD
:
270 case SHADER_OPCODE_TXF
:
271 case SHADER_OPCODE_TXF_LZ
:
272 case SHADER_OPCODE_TXF_CMS
:
273 case SHADER_OPCODE_TXF_CMS_W
:
274 case SHADER_OPCODE_TXF_UMS
:
275 case SHADER_OPCODE_TXF_MCS
:
276 case SHADER_OPCODE_TXL
:
277 case SHADER_OPCODE_TXL_LZ
:
278 case SHADER_OPCODE_TXS
:
279 case SHADER_OPCODE_LOD
:
280 case SHADER_OPCODE_TG4
:
281 case SHADER_OPCODE_TG4_OFFSET
:
282 case SHADER_OPCODE_SAMPLEINFO
:
283 return arg
== 1 || arg
== 2;
285 case SHADER_OPCODE_SEND
:
286 return arg
== 0 || arg
== 1;
294 fs_inst::is_payload(unsigned arg
) const
297 case FS_OPCODE_FB_WRITE
:
298 case FS_OPCODE_FB_READ
:
299 case SHADER_OPCODE_URB_WRITE_SIMD8
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
303 case SHADER_OPCODE_URB_READ_SIMD8
:
304 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
305 case VEC4_OPCODE_UNTYPED_ATOMIC
:
306 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
308 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
309 case SHADER_OPCODE_SHADER_TIME_ADD
:
310 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
311 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
312 case SHADER_OPCODE_INTERLOCK
:
313 case SHADER_OPCODE_MEMORY_FENCE
:
314 case SHADER_OPCODE_BARRIER
:
317 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
320 case SHADER_OPCODE_SEND
:
321 return arg
== 2 || arg
== 3;
332 * Returns true if this instruction's sources and destinations cannot
333 * safely be the same register.
335 * In most cases, a register can be written over safely by the same
336 * instruction that is its last use. For a single instruction, the
337 * sources are dereferenced before writing of the destination starts
340 * However, there are a few cases where this can be problematic:
342 * - Virtual opcodes that translate to multiple instructions in the
343 * code generator: if src == dst and one instruction writes the
344 * destination before a later instruction reads the source, then
345 * src will have been clobbered.
347 * - SIMD16 compressed instructions with certain regioning (see below).
349 * The register allocator uses this information to set up conflicts between
350 * GRF sources and the destination.
353 fs_inst::has_source_and_destination_hazard() const
356 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
357 /* Multiple partial writes to the destination */
359 case SHADER_OPCODE_SHUFFLE
:
360 /* This instruction returns an arbitrary channel from the source and
361 * gets split into smaller instructions in the generator. It's possible
362 * that one of the instructions will read from a channel corresponding
363 * to an earlier instruction.
365 case SHADER_OPCODE_SEL_EXEC
:
366 /* This is implemented as
368 * mov(16) g4<1>D 0D { align1 WE_all 1H };
369 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
371 * Because the source is only read in the second instruction, the first
372 * may stomp all over it.
375 case SHADER_OPCODE_QUAD_SWIZZLE
:
377 case BRW_SWIZZLE_XXXX
:
378 case BRW_SWIZZLE_YYYY
:
379 case BRW_SWIZZLE_ZZZZ
:
380 case BRW_SWIZZLE_WWWW
:
381 case BRW_SWIZZLE_XXZZ
:
382 case BRW_SWIZZLE_YYWW
:
383 case BRW_SWIZZLE_XYXY
:
384 case BRW_SWIZZLE_ZWZW
:
385 /* These can be implemented as a single Align1 region on all
386 * platforms, so there's never a hazard between source and
387 * destination. C.f. fs_generator::generate_quad_swizzle().
391 return !is_uniform(src
[0]);
394 /* The SIMD16 compressed instruction
396 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
398 * is actually decoded in hardware as:
400 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
401 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
403 * Which is safe. However, if we have uniform accesses
404 * happening, we get into trouble:
406 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
407 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
409 * Now our destination for the first instruction overwrote the
410 * second instruction's src0, and we get garbage for those 8
411 * pixels. There's a similar issue for the pre-gen6
412 * pixel_x/pixel_y, which are registers of 16-bit values and thus
413 * would get stomped by the first decode as well.
415 if (exec_size
== 16) {
416 for (int i
= 0; i
< sources
; i
++) {
417 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
418 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
419 src
[i
].type
== BRW_REGISTER_TYPE_W
||
420 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
421 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
431 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
433 if (devinfo
->gen
== 6 && is_math())
436 if (is_send_from_grf())
439 /* From GEN:BUG:1604601757:
441 * "When multiplying a DW and any lower precision integer, source modifier
444 if (devinfo
->gen
>= 12 && (opcode
== BRW_OPCODE_MUL
||
445 opcode
== BRW_OPCODE_MAD
)) {
446 const brw_reg_type exec_type
= get_exec_type(this);
447 const unsigned min_type_sz
= opcode
== BRW_OPCODE_MAD
?
448 MIN2(type_sz(src
[1].type
), type_sz(src
[2].type
)) :
449 MIN2(type_sz(src
[0].type
), type_sz(src
[1].type
));
451 if (brw_reg_type_is_integer(exec_type
) &&
452 type_sz(exec_type
) >= 4 &&
453 type_sz(exec_type
) != min_type_sz
)
457 if (!backend_instruction::can_do_source_mods())
464 fs_inst::can_do_cmod()
466 if (!backend_instruction::can_do_cmod())
469 /* The accumulator result appears to get used for the conditional modifier
470 * generation. When negating a UD value, there is a 33rd bit generated for
471 * the sign in the accumulator value, so now you can't check, for example,
472 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
474 for (unsigned i
= 0; i
< sources
; i
++) {
475 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
483 fs_inst::can_change_types() const
485 return dst
.type
== src
[0].type
&&
486 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
487 (opcode
== BRW_OPCODE_MOV
||
488 (opcode
== BRW_OPCODE_SEL
&&
489 dst
.type
== src
[1].type
&&
490 predicate
!= BRW_PREDICATE_NONE
&&
491 !src
[1].abs
&& !src
[1].negate
));
497 memset((void*)this, 0, sizeof(*this));
498 type
= BRW_REGISTER_TYPE_UD
;
502 /** Generic unset register constructor. */
506 this->file
= BAD_FILE
;
509 fs_reg::fs_reg(struct ::brw_reg reg
) :
514 if (this->file
== IMM
&&
515 (this->type
!= BRW_REGISTER_TYPE_V
&&
516 this->type
!= BRW_REGISTER_TYPE_UV
&&
517 this->type
!= BRW_REGISTER_TYPE_VF
)) {
523 fs_reg::equals(const fs_reg
&r
) const
525 return (this->backend_reg::equals(r
) &&
530 fs_reg::negative_equals(const fs_reg
&r
) const
532 return (this->backend_reg::negative_equals(r
) &&
537 fs_reg::is_contiguous() const
542 return hstride
== BRW_HORIZONTAL_STRIDE_1
&&
543 vstride
== width
+ hstride
;
554 unreachable("Invalid register file");
558 fs_reg::component_size(unsigned width
) const
560 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
563 return MAX2(width
* stride
, 1) * type_sz(type
);
567 * Create a MOV to read the timestamp register.
570 fs_visitor::get_timestamp(const fs_builder
&bld
)
572 assert(devinfo
->gen
>= 7);
574 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
577 BRW_REGISTER_TYPE_UD
));
579 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
581 /* We want to read the 3 fields we care about even if it's not enabled in
584 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
590 fs_visitor::emit_shader_time_begin()
592 /* We want only the low 32 bits of the timestamp. Since it's running
593 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
594 * which is plenty of time for our purposes. It is identical across the
595 * EUs, but since it's tracking GPU core speed it will increment at a
596 * varying rate as render P-states change.
598 shader_start_time
= component(
599 get_timestamp(bld
.annotate("shader time start")), 0);
603 fs_visitor::emit_shader_time_end()
605 /* Insert our code just before the final SEND with EOT. */
606 exec_node
*end
= this->instructions
.get_tail();
607 assert(end
&& ((fs_inst
*) end
)->eot
);
608 const fs_builder ibld
= bld
.annotate("shader time end")
609 .exec_all().at(NULL
, end
);
610 const fs_reg timestamp
= get_timestamp(ibld
);
612 /* We only use the low 32 bits of the timestamp - see
613 * emit_shader_time_begin()).
615 * We could also check if render P-states have changed (or anything
616 * else that might disrupt timing) by setting smear to 2 and checking if
617 * that field is != 0.
619 const fs_reg shader_end_time
= component(timestamp
, 0);
621 /* Check that there weren't any timestamp reset events (assuming these
622 * were the only two timestamp reads that happened).
624 const fs_reg reset
= component(timestamp
, 2);
625 set_condmod(BRW_CONDITIONAL_Z
,
626 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
627 ibld
.IF(BRW_PREDICATE_NORMAL
);
629 fs_reg start
= shader_start_time
;
631 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
632 BRW_REGISTER_TYPE_UD
),
634 const fs_builder cbld
= ibld
.group(1, 0);
635 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
637 /* If there were no instructions between the two timestamp gets, the diff
638 * is 2 cycles. Remove that overhead, so I can forget about that when
639 * trying to determine the time taken for single instructions.
641 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
642 SHADER_TIME_ADD(cbld
, 0, diff
);
643 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
644 ibld
.emit(BRW_OPCODE_ELSE
);
645 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
646 ibld
.emit(BRW_OPCODE_ENDIF
);
650 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
651 int shader_time_subindex
,
654 int index
= shader_time_index
* 3 + shader_time_subindex
;
655 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
658 if (dispatch_width
== 8)
659 payload
= vgrf(glsl_type::uvec2_type
);
661 payload
= vgrf(glsl_type::uint_type
);
663 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
667 fs_visitor::vfail(const char *format
, va_list va
)
676 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
677 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
679 this->fail_msg
= msg
;
682 fprintf(stderr
, "%s", msg
);
687 fs_visitor::fail(const char *format
, ...)
691 va_start(va
, format
);
697 * Mark this program as impossible to compile with dispatch width greater
700 * During the SIMD8 compile (which happens first), we can detect and flag
701 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
702 * SIMD16+ compile altogether.
704 * During a compile of dispatch width greater than n (if one happens anyway),
705 * this just calls fail().
708 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
710 if (dispatch_width
> n
) {
713 max_dispatch_width
= n
;
714 compiler
->shader_perf_log(log_data
,
715 "Shader dispatch width limited to SIMD%d: %s",
721 * Returns true if the instruction has a flag that means it won't
722 * update an entire destination register.
724 * For example, dead code elimination and live variable analysis want to know
725 * when a write to a variable screens off any preceding values that were in
729 fs_inst::is_partial_write() const
731 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
732 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
733 !this->dst
.is_contiguous() ||
734 this->dst
.offset
% REG_SIZE
!= 0);
738 fs_inst::components_read(unsigned i
) const
740 /* Return zero if the source is not present. */
741 if (src
[i
].file
== BAD_FILE
)
745 case FS_OPCODE_LINTERP
:
751 case FS_OPCODE_PIXEL_X
:
752 case FS_OPCODE_PIXEL_Y
:
756 case FS_OPCODE_FB_WRITE_LOGICAL
:
757 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
758 /* First/second FB write color. */
760 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
764 case SHADER_OPCODE_TEX_LOGICAL
:
765 case SHADER_OPCODE_TXD_LOGICAL
:
766 case SHADER_OPCODE_TXF_LOGICAL
:
767 case SHADER_OPCODE_TXL_LOGICAL
:
768 case SHADER_OPCODE_TXS_LOGICAL
:
769 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
770 case FS_OPCODE_TXB_LOGICAL
:
771 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
772 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
773 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
774 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
775 case SHADER_OPCODE_LOD_LOGICAL
:
776 case SHADER_OPCODE_TG4_LOGICAL
:
777 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
778 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
779 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
780 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
781 /* Texture coordinates. */
782 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
783 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
784 /* Texture derivatives. */
785 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
786 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
787 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
788 /* Texture offset. */
789 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
792 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
797 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
798 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
799 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
800 /* Surface coordinates. */
801 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
802 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
803 /* Surface operation source (ignored for reads). */
804 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
809 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
810 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
811 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
812 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
813 /* Surface coordinates. */
814 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
815 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
816 /* Surface operation source. */
817 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
818 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
822 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
823 assert(src
[2].file
== IMM
);
826 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
827 assert(src
[2].file
== IMM
);
828 return i
== 1 ? src
[2].ud
: 1;
830 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
831 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
832 assert(src
[2].file
== IMM
);
835 const unsigned op
= src
[2].ud
;
850 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
851 assert(src
[2].file
== IMM
);
854 const unsigned op
= src
[2].ud
;
855 return op
== BRW_AOP_FCMPWR
? 2 : 1;
860 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
861 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
862 /* Scattered logical opcodes use the following params:
863 * src[0] Surface coordinates
864 * src[1] Surface operation source (ignored for reads)
866 * src[3] IMM with always 1 dimension.
867 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
869 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
870 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
871 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
873 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
874 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
875 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
876 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
879 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
880 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
881 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
882 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
883 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
884 /* Surface coordinates. */
885 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
886 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
887 /* Surface operation source. */
888 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
890 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
891 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
896 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
897 return (i
== 0 ? 2 : 1);
899 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
900 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
901 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
902 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
903 /* Surface coordinates. */
904 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
905 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
906 /* Surface operation source. */
907 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
919 fs_inst::size_read(int arg
) const
922 case SHADER_OPCODE_SEND
:
924 return mlen
* REG_SIZE
;
925 } else if (arg
== 3) {
926 return ex_mlen
* REG_SIZE
;
930 case FS_OPCODE_FB_WRITE
:
931 case FS_OPCODE_REP_FB_WRITE
:
934 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
936 return mlen
* REG_SIZE
;
940 case FS_OPCODE_FB_READ
:
941 case SHADER_OPCODE_URB_WRITE_SIMD8
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
945 case SHADER_OPCODE_URB_READ_SIMD8
:
946 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
947 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
948 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
950 return mlen
* REG_SIZE
;
953 case FS_OPCODE_SET_SAMPLE_ID
:
958 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
959 /* The payload is actually stored in src1 */
961 return mlen
* REG_SIZE
;
964 case FS_OPCODE_LINTERP
:
969 case SHADER_OPCODE_LOAD_PAYLOAD
:
970 if (arg
< this->header_size
)
974 case CS_OPCODE_CS_TERMINATE
:
975 case SHADER_OPCODE_BARRIER
:
978 case SHADER_OPCODE_MOV_INDIRECT
:
980 assert(src
[2].file
== IMM
);
986 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
987 return mlen
* REG_SIZE
;
991 switch (src
[arg
].file
) {
994 return components_read(arg
) * type_sz(src
[arg
].type
);
1000 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1002 unreachable("MRF registers are not allowed as sources");
1009 predicate_width(brw_predicate predicate
)
1011 switch (predicate
) {
1012 case BRW_PREDICATE_NONE
: return 1;
1013 case BRW_PREDICATE_NORMAL
: return 1;
1014 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1015 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1016 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1017 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1018 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1019 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1020 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1021 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1022 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1023 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1024 default: unreachable("Unsupported predicate");
1028 /* Return the subset of flag registers that an instruction could
1029 * potentially read or write based on the execution controls and flag
1030 * subregister number of the instruction.
1033 flag_mask(const fs_inst
*inst
, unsigned width
)
1035 assert(util_is_power_of_two_nonzero(width
));
1036 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1038 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1039 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1043 bit_mask(unsigned n
)
1045 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1049 flag_mask(const fs_reg
&r
, unsigned sz
)
1051 if (r
.file
== ARF
) {
1052 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1053 const unsigned end
= start
+ sz
;
1054 return bit_mask(end
) & ~bit_mask(start
);
1062 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1064 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1065 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1066 /* The vertical predication modes combine corresponding bits from
1067 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1069 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1070 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1071 } else if (predicate
) {
1072 return flag_mask(this, predicate_width(predicate
));
1075 for (int i
= 0; i
< sources
; i
++) {
1076 mask
|= flag_mask(src
[i
], size_read(i
));
1083 fs_inst::flags_written() const
1085 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1086 opcode
!= BRW_OPCODE_CSEL
&&
1087 opcode
!= BRW_OPCODE_IF
&&
1088 opcode
!= BRW_OPCODE_WHILE
)) ||
1089 opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1090 opcode
== FS_OPCODE_FB_WRITE
) {
1091 return flag_mask(this, 1);
1093 return flag_mask(dst
, size_written
);
1098 * Returns how many MRFs an FS opcode will write over.
1100 * Note that this is not the 0 or 1 implied writes in an actual gen
1101 * instruction -- the FS opcodes often generate MOVs in addition.
1104 fs_inst::implied_mrf_writes() const
1113 case SHADER_OPCODE_RCP
:
1114 case SHADER_OPCODE_RSQ
:
1115 case SHADER_OPCODE_SQRT
:
1116 case SHADER_OPCODE_EXP2
:
1117 case SHADER_OPCODE_LOG2
:
1118 case SHADER_OPCODE_SIN
:
1119 case SHADER_OPCODE_COS
:
1120 return 1 * exec_size
/ 8;
1121 case SHADER_OPCODE_POW
:
1122 case SHADER_OPCODE_INT_QUOTIENT
:
1123 case SHADER_OPCODE_INT_REMAINDER
:
1124 return 2 * exec_size
/ 8;
1125 case SHADER_OPCODE_TEX
:
1127 case SHADER_OPCODE_TXD
:
1128 case SHADER_OPCODE_TXF
:
1129 case SHADER_OPCODE_TXF_CMS
:
1130 case SHADER_OPCODE_TXF_MCS
:
1131 case SHADER_OPCODE_TG4
:
1132 case SHADER_OPCODE_TG4_OFFSET
:
1133 case SHADER_OPCODE_TXL
:
1134 case SHADER_OPCODE_TXS
:
1135 case SHADER_OPCODE_LOD
:
1136 case SHADER_OPCODE_SAMPLEINFO
:
1138 case FS_OPCODE_FB_WRITE
:
1139 case FS_OPCODE_REP_FB_WRITE
:
1140 return src
[0].file
== BAD_FILE
? 0 : 2;
1141 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1142 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1144 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1146 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1149 unreachable("not reached");
1154 fs_visitor::vgrf(const glsl_type
*const type
)
1156 int reg_width
= dispatch_width
/ 8;
1158 alloc
.allocate(glsl_count_dword_slots(type
, false) * reg_width
),
1159 brw_type_for_base_type(type
));
1162 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1167 this->type
= BRW_REGISTER_TYPE_F
;
1168 this->stride
= (file
== UNIFORM
? 0 : 1);
1171 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1177 this->stride
= (file
== UNIFORM
? 0 : 1);
1180 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1181 * This brings in those uniform definitions
1184 fs_visitor::import_uniforms(fs_visitor
*v
)
1186 this->push_constant_loc
= v
->push_constant_loc
;
1187 this->pull_constant_loc
= v
->pull_constant_loc
;
1188 this->uniforms
= v
->uniforms
;
1189 this->subgroup_id
= v
->subgroup_id
;
1193 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1195 assert(stage
== MESA_SHADER_FRAGMENT
);
1197 /* gl_FragCoord.x */
1198 bld
.MOV(wpos
, this->pixel_x
);
1199 wpos
= offset(wpos
, bld
, 1);
1201 /* gl_FragCoord.y */
1202 bld
.MOV(wpos
, this->pixel_y
);
1203 wpos
= offset(wpos
, bld
, 1);
1205 /* gl_FragCoord.z */
1206 if (devinfo
->gen
>= 6) {
1207 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1209 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1210 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1211 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1213 wpos
= offset(wpos
, bld
, 1);
1215 /* gl_FragCoord.w: Already set up in emit_interpolation */
1216 bld
.MOV(wpos
, this->wpos_w
);
1219 enum brw_barycentric_mode
1220 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1222 /* Barycentric modes don't make sense for flat inputs. */
1223 assert(mode
!= INTERP_MODE_FLAT
);
1227 case nir_intrinsic_load_barycentric_pixel
:
1228 case nir_intrinsic_load_barycentric_at_offset
:
1229 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1231 case nir_intrinsic_load_barycentric_centroid
:
1232 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1234 case nir_intrinsic_load_barycentric_sample
:
1235 case nir_intrinsic_load_barycentric_at_sample
:
1236 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1239 unreachable("invalid intrinsic");
1242 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1245 return (enum brw_barycentric_mode
) bary
;
1249 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1251 static enum brw_barycentric_mode
1252 centroid_to_pixel(enum brw_barycentric_mode bary
)
1254 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1255 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1256 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1260 fs_visitor::emit_frontfacing_interpolation()
1262 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1264 if (devinfo
->gen
>= 12) {
1265 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
1267 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1268 bld
.ASR(tmp
, g1
, brw_imm_d(15));
1270 } else if (devinfo
->gen
>= 6) {
1271 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1272 * a boolean result from this (~0/true or 0/false).
1274 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1275 * this task in only one instruction:
1276 * - a negation source modifier will flip the bit; and
1277 * - a W -> D type conversion will sign extend the bit into the high
1278 * word of the destination.
1280 * An ASR 15 fills the low word of the destination.
1282 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1285 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1287 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1288 * a boolean result from this (1/true or 0/false).
1290 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1291 * the negation source modifier to flip it. Unfortunately the SHR
1292 * instruction only operates on UD (or D with an abs source modifier)
1293 * sources without negation.
1295 * Instead, use ASR (which will give ~0/true or 0/false).
1297 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1300 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1307 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1309 assert(stage
== MESA_SHADER_FRAGMENT
);
1310 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1311 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1313 if (wm_prog_data
->persample_dispatch
) {
1314 /* Convert int_sample_pos to floating point */
1315 bld
.MOV(dst
, int_sample_pos
);
1316 /* Scale to the range [0, 1] */
1317 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1320 /* From ARB_sample_shading specification:
1321 * "When rendering to a non-multisample buffer, or if multisample
1322 * rasterization is disabled, gl_SamplePosition will always be
1325 bld
.MOV(dst
, brw_imm_f(0.5f
));
1330 fs_visitor::emit_samplepos_setup()
1332 assert(devinfo
->gen
>= 6);
1334 const fs_builder abld
= bld
.annotate("compute sample position");
1335 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1337 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1338 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1340 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1341 * mode will be enabled.
1343 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1344 * R31.1:0 Position Offset X/Y for Slot[3:0]
1345 * R31.3:2 Position Offset X/Y for Slot[7:4]
1348 * The X, Y sample positions come in as bytes in thread payload. So, read
1349 * the positions using vstride=16, width=8, hstride=2.
1351 const fs_reg sample_pos_reg
=
1352 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1354 /* Compute gl_SamplePosition.x */
1355 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1356 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1358 /* Compute gl_SamplePosition.y */
1359 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1360 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1365 fs_visitor::emit_sampleid_setup()
1367 assert(stage
== MESA_SHADER_FRAGMENT
);
1368 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1369 assert(devinfo
->gen
>= 6);
1371 const fs_builder abld
= bld
.annotate("compute sample id");
1372 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1374 if (!key
->multisample_fbo
) {
1375 /* As per GL_ARB_sample_shading specification:
1376 * "When rendering to a non-multisample buffer, or if multisample
1377 * rasterization is disabled, gl_SampleID will always be zero."
1379 abld
.MOV(*reg
, brw_imm_d(0));
1380 } else if (devinfo
->gen
>= 8) {
1381 /* Sample ID comes in as 4-bit numbers in g1.0:
1383 * 15:12 Slot 3 SampleID (only used in SIMD16)
1384 * 11:8 Slot 2 SampleID (only used in SIMD16)
1385 * 7:4 Slot 1 SampleID
1386 * 3:0 Slot 0 SampleID
1388 * Each slot corresponds to four channels, so we want to replicate each
1389 * half-byte value to 4 channels in a row:
1391 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1392 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1394 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1395 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1397 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1398 * channels to read the first byte (7:0), and the second group of 8
1399 * channels to read the second byte (15:8). Then, we shift right by
1400 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1401 * values into place. Finally, we AND with 0xf to keep the low nibble.
1403 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1404 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1406 * TODO: These payload bits exist on Gen7 too, but they appear to always
1407 * be zero, so this code fails to work. We should find out why.
1409 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1411 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1412 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1413 hbld
.SHR(offset(tmp
, hbld
, i
),
1414 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1416 brw_imm_v(0x44440000));
1419 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1421 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1422 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1424 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1425 * 8x multisampling, subspan 0 will represent sample N (where N
1426 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1427 * 7. We can find the value of N by looking at R0.0 bits 7:6
1428 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1429 * (since samples are always delivered in pairs). That is, we
1430 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1431 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1432 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1433 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1434 * populating a temporary variable with the sequence (0, 1, 2, 3),
1435 * and then reading from it using vstride=1, width=4, hstride=0.
1436 * These computations hold good for 4x multisampling as well.
1438 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1439 * the first four slots are sample 0 of subspan 0; the next four
1440 * are sample 1 of subspan 0; the third group is sample 0 of
1441 * subspan 1, and finally sample 1 of subspan 1.
1444 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1445 * accomodate 16x MSAA.
1447 abld
.exec_all().group(1, 0)
1448 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1450 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1452 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1453 * can assume 4x MSAA. Disallow it on IVB+
1455 * FINISHME: One day, we could come up with a way to do this that
1456 * actually works on gen7.
1458 if (devinfo
->gen
>= 7)
1459 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1460 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1462 /* This special instruction takes care of setting vstride=1,
1463 * width=4, hstride=0 of t2 during an ADD instruction.
1465 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1472 fs_visitor::emit_samplemaskin_setup()
1474 assert(stage
== MESA_SHADER_FRAGMENT
);
1475 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1476 assert(devinfo
->gen
>= 6);
1478 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1480 fs_reg coverage_mask
=
1481 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1483 if (wm_prog_data
->persample_dispatch
) {
1484 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1485 * and a mask representing which sample is being processed by the
1486 * current shader invocation.
1488 * From the OES_sample_variables specification:
1489 * "When per-sample shading is active due to the use of a fragment input
1490 * qualified by "sample" or due to the use of the gl_SampleID or
1491 * gl_SamplePosition variables, only the bit for the current sample is
1492 * set in gl_SampleMaskIn."
1494 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1496 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1497 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1499 fs_reg one
= vgrf(glsl_type::int_type
);
1500 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1501 abld
.MOV(one
, brw_imm_d(1));
1502 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1503 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1505 /* In per-pixel mode, the coverage mask is sufficient. */
1506 *reg
= coverage_mask
;
1512 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1514 if (!src
.abs
&& !src
.negate
)
1517 fs_reg temp
= bld
.vgrf(src
.type
);
1524 fs_visitor::emit_discard_jump()
1526 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1528 /* For performance, after a discard, jump to the end of the
1529 * shader if all relevant channels have been discarded.
1531 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1532 discard_jump
->flag_subreg
= 1;
1534 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1535 discard_jump
->predicate_inverse
= true;
1539 fs_visitor::emit_gs_thread_end()
1541 assert(stage
== MESA_SHADER_GEOMETRY
);
1543 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1545 if (gs_compile
->control_data_header_size_bits
> 0) {
1546 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1549 const fs_builder abld
= bld
.annotate("thread end");
1552 if (gs_prog_data
->static_vertex_count
!= -1) {
1553 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1554 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1555 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1556 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1557 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1560 /* Delete now dead instructions. */
1561 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1567 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1571 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1572 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1573 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1576 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1577 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1578 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1579 sources
[1] = this->final_gs_vertex_count
;
1580 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1581 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1589 fs_visitor::assign_curb_setup()
1591 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1593 unsigned ubo_push_length
= 0;
1594 unsigned ubo_push_start
[4];
1595 for (int i
= 0; i
< 4; i
++) {
1596 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1597 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1600 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1602 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1603 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1604 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1605 if (inst
->src
[i
].file
== UNIFORM
) {
1606 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1608 if (inst
->src
[i
].nr
>= UBO_START
) {
1609 /* constant_nr is in 32-bit units, the rest are in bytes */
1610 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1611 inst
->src
[i
].offset
/ 4;
1612 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1613 constant_nr
= push_constant_loc
[uniform_nr
];
1615 /* Section 5.11 of the OpenGL 4.1 spec says:
1616 * "Out-of-bounds reads return undefined values, which include
1617 * values from other variables of the active program or zero."
1618 * Just return the first push constant.
1623 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1626 brw_reg
.abs
= inst
->src
[i
].abs
;
1627 brw_reg
.negate
= inst
->src
[i
].negate
;
1629 assert(inst
->src
[i
].stride
== 0);
1630 inst
->src
[i
] = byte_offset(
1631 retype(brw_reg
, inst
->src
[i
].type
),
1632 inst
->src
[i
].offset
% 4);
1637 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1638 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1642 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1643 const struct brw_wm_prog_key
*key
,
1644 struct brw_wm_prog_data
*prog_data
,
1645 const nir_shader
*nir
)
1647 memset(prog_data
->urb_setup
, -1,
1648 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1651 /* Figure out where each of the incoming setup attributes lands. */
1652 if (devinfo
->gen
>= 6) {
1653 if (util_bitcount64(nir
->info
.inputs_read
&
1654 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1655 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1656 * first 16 varying inputs, so we can put them wherever we want.
1657 * Just put them in order.
1659 * This is useful because it means that (a) inputs not used by the
1660 * fragment shader won't take up valuable register space, and (b) we
1661 * won't have to recompile the fragment shader if it gets paired with
1662 * a different vertex (or geometry) shader.
1664 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1665 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1666 BITFIELD64_BIT(i
)) {
1667 prog_data
->urb_setup
[i
] = urb_next
++;
1671 /* We have enough input varyings that the SF/SBE pipeline stage can't
1672 * arbitrarily rearrange them to suit our whim; we have to put them
1673 * in an order that matches the output of the previous pipeline stage
1674 * (geometry or vertex shader).
1676 struct brw_vue_map prev_stage_vue_map
;
1677 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1678 key
->input_slots_valid
,
1679 nir
->info
.separate_shader
);
1682 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1683 &prev_stage_vue_map
);
1685 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1686 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1688 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1689 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1690 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1691 BITFIELD64_BIT(varying
))) {
1692 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1695 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1698 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1699 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1700 /* Point size is packed into the header, not as a general attribute */
1701 if (i
== VARYING_SLOT_PSIZ
)
1704 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1705 /* The back color slot is skipped when the front color is
1706 * also written to. In addition, some slots can be
1707 * written in the vertex shader and not read in the
1708 * fragment shader. So the register number must always be
1709 * incremented, mapped or not.
1711 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1712 prog_data
->urb_setup
[i
] = urb_next
;
1718 * It's a FS only attribute, and we did interpolation for this attribute
1719 * in SF thread. So, count it here, too.
1721 * See compile_sf_prog() for more info.
1723 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1724 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1727 prog_data
->num_varying_inputs
= urb_next
;
1731 fs_visitor::assign_urb_setup()
1733 assert(stage
== MESA_SHADER_FRAGMENT
);
1734 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1736 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1738 /* Offset all the urb_setup[] index by the actual position of the
1739 * setup regs, now that the location of the constants has been chosen.
1741 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1742 for (int i
= 0; i
< inst
->sources
; i
++) {
1743 if (inst
->src
[i
].file
== ATTR
) {
1744 /* ATTR regs in the FS are in units of logical scalar inputs each
1745 * of which consumes half of a GRF register.
1747 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1748 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1749 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1750 inst
->src
[i
].offset
;
1751 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1752 1 : MIN2(inst
->exec_size
, 8);
1753 struct brw_reg reg
= stride(
1754 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1756 width
* inst
->src
[i
].stride
,
1757 width
, inst
->src
[i
].stride
);
1758 reg
.abs
= inst
->src
[i
].abs
;
1759 reg
.negate
= inst
->src
[i
].negate
;
1765 /* Each attribute is 4 setup channels, each of which is half a reg. */
1766 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1770 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1772 for (int i
= 0; i
< inst
->sources
; i
++) {
1773 if (inst
->src
[i
].file
== ATTR
) {
1774 int grf
= payload
.num_regs
+
1775 prog_data
->curb_read_length
+
1777 inst
->src
[i
].offset
/ REG_SIZE
;
1779 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1781 * VertStride must be used to cross GRF register boundaries. This
1782 * rule implies that elements within a 'Width' cannot cross GRF
1785 * So, for registers that are large enough, we have to split the exec
1786 * size in two and trust the compression state to sort it out.
1788 unsigned total_size
= inst
->exec_size
*
1789 inst
->src
[i
].stride
*
1790 type_sz(inst
->src
[i
].type
);
1792 assert(total_size
<= 2 * REG_SIZE
);
1793 const unsigned exec_size
=
1794 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1796 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1797 struct brw_reg reg
=
1798 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1799 inst
->src
[i
].offset
% REG_SIZE
),
1800 exec_size
* inst
->src
[i
].stride
,
1801 width
, inst
->src
[i
].stride
);
1802 reg
.abs
= inst
->src
[i
].abs
;
1803 reg
.negate
= inst
->src
[i
].negate
;
1811 fs_visitor::assign_vs_urb_setup()
1813 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1815 assert(stage
== MESA_SHADER_VERTEX
);
1817 /* Each attribute is 4 regs. */
1818 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1820 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1822 /* Rewrite all ATTR file references to the hw grf that they land in. */
1823 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1824 convert_attr_sources_to_hw_regs(inst
);
1829 fs_visitor::assign_tcs_urb_setup()
1831 assert(stage
== MESA_SHADER_TESS_CTRL
);
1833 /* Rewrite all ATTR file references to HW_REGs. */
1834 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1835 convert_attr_sources_to_hw_regs(inst
);
1840 fs_visitor::assign_tes_urb_setup()
1842 assert(stage
== MESA_SHADER_TESS_EVAL
);
1844 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1846 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1848 /* Rewrite all ATTR file references to HW_REGs. */
1849 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1850 convert_attr_sources_to_hw_regs(inst
);
1855 fs_visitor::assign_gs_urb_setup()
1857 assert(stage
== MESA_SHADER_GEOMETRY
);
1859 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1861 first_non_payload_grf
+=
1862 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1864 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1865 /* Rewrite all ATTR file references to GRFs. */
1866 convert_attr_sources_to_hw_regs(inst
);
1872 * Split large virtual GRFs into separate components if we can.
1874 * This is mostly duplicated with what brw_fs_vector_splitting does,
1875 * but that's really conservative because it's afraid of doing
1876 * splitting that doesn't result in real progress after the rest of
1877 * the optimization phases, which would cause infinite looping in
1878 * optimization. We can do it once here, safely. This also has the
1879 * opportunity to split interpolated values, or maybe even uniforms,
1880 * which we don't have at the IR level.
1882 * We want to split, because virtual GRFs are what we register
1883 * allocate and spill (due to contiguousness requirements for some
1884 * instructions), and they're what we naturally generate in the
1885 * codegen process, but most virtual GRFs don't actually need to be
1886 * contiguous sets of GRFs. If we split, we'll end up with reduced
1887 * live intervals and better dead code elimination and coalescing.
1890 fs_visitor::split_virtual_grfs()
1892 /* Compact the register file so we eliminate dead vgrfs. This
1893 * only defines split points for live registers, so if we have
1894 * too large dead registers they will hit assertions later.
1896 compact_virtual_grfs();
1898 int num_vars
= this->alloc
.count
;
1900 /* Count the total number of registers */
1902 int vgrf_to_reg
[num_vars
];
1903 for (int i
= 0; i
< num_vars
; i
++) {
1904 vgrf_to_reg
[i
] = reg_count
;
1905 reg_count
+= alloc
.sizes
[i
];
1908 /* An array of "split points". For each register slot, this indicates
1909 * if this slot can be separated from the previous slot. Every time an
1910 * instruction uses multiple elements of a register (as a source or
1911 * destination), we mark the used slots as inseparable. Then we go
1912 * through and split the registers into the smallest pieces we can.
1914 bool *split_points
= new bool[reg_count
];
1915 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1917 /* Mark all used registers as fully splittable */
1918 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1919 if (inst
->dst
.file
== VGRF
) {
1920 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1921 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1922 split_points
[reg
+ j
] = true;
1925 for (int i
= 0; i
< inst
->sources
; i
++) {
1926 if (inst
->src
[i
].file
== VGRF
) {
1927 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1928 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1929 split_points
[reg
+ j
] = true;
1934 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1935 /* We fix up undef instructions later */
1936 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
1937 /* UNDEF instructions are currently only used to undef entire
1938 * registers. We need this invariant later when we split them.
1940 assert(inst
->dst
.file
== VGRF
);
1941 assert(inst
->dst
.offset
== 0);
1942 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
1946 if (inst
->dst
.file
== VGRF
) {
1947 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1948 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1949 split_points
[reg
+ j
] = false;
1951 for (int i
= 0; i
< inst
->sources
; i
++) {
1952 if (inst
->src
[i
].file
== VGRF
) {
1953 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1954 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1955 split_points
[reg
+ j
] = false;
1960 int *new_virtual_grf
= new int[reg_count
];
1961 int *new_reg_offset
= new int[reg_count
];
1964 for (int i
= 0; i
< num_vars
; i
++) {
1965 /* The first one should always be 0 as a quick sanity check. */
1966 assert(split_points
[reg
] == false);
1969 new_reg_offset
[reg
] = 0;
1974 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1975 /* If this is a split point, reset the offset to 0 and allocate a
1976 * new virtual GRF for the previous offset many registers
1978 if (split_points
[reg
]) {
1979 assert(offset
<= MAX_VGRF_SIZE
);
1980 int grf
= alloc
.allocate(offset
);
1981 for (int k
= reg
- offset
; k
< reg
; k
++)
1982 new_virtual_grf
[k
] = grf
;
1985 new_reg_offset
[reg
] = offset
;
1990 /* The last one gets the original register number */
1991 assert(offset
<= MAX_VGRF_SIZE
);
1992 alloc
.sizes
[i
] = offset
;
1993 for (int k
= reg
- offset
; k
< reg
; k
++)
1994 new_virtual_grf
[k
] = i
;
1996 assert(reg
== reg_count
);
1998 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1999 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2000 const fs_builder
ibld(this, block
, inst
);
2001 assert(inst
->size_written
% REG_SIZE
== 0);
2002 unsigned reg_offset
= 0;
2003 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2004 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2005 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2006 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2008 inst
->remove(block
);
2012 if (inst
->dst
.file
== VGRF
) {
2013 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2014 inst
->dst
.nr
= new_virtual_grf
[reg
];
2015 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2016 inst
->dst
.offset
% REG_SIZE
;
2017 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2019 for (int i
= 0; i
< inst
->sources
; i
++) {
2020 if (inst
->src
[i
].file
== VGRF
) {
2021 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2022 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2023 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2024 inst
->src
[i
].offset
% REG_SIZE
;
2025 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2029 invalidate_live_intervals();
2031 delete[] split_points
;
2032 delete[] new_virtual_grf
;
2033 delete[] new_reg_offset
;
2037 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2039 * During code generation, we create tons of temporary variables, many of
2040 * which get immediately killed and are never used again. Yet, in later
2041 * optimization and analysis passes, such as compute_live_intervals, we need
2042 * to loop over all the virtual GRFs. Compacting them can save a lot of
2046 fs_visitor::compact_virtual_grfs()
2048 bool progress
= false;
2049 int *remap_table
= new int[this->alloc
.count
];
2050 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2052 /* Mark which virtual GRFs are used. */
2053 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2054 if (inst
->dst
.file
== VGRF
)
2055 remap_table
[inst
->dst
.nr
] = 0;
2057 for (int i
= 0; i
< inst
->sources
; i
++) {
2058 if (inst
->src
[i
].file
== VGRF
)
2059 remap_table
[inst
->src
[i
].nr
] = 0;
2063 /* Compact the GRF arrays. */
2065 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2066 if (remap_table
[i
] == -1) {
2067 /* We just found an unused register. This means that we are
2068 * actually going to compact something.
2072 remap_table
[i
] = new_index
;
2073 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2074 invalidate_live_intervals();
2079 this->alloc
.count
= new_index
;
2081 /* Patch all the instructions to use the newly renumbered registers */
2082 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2083 if (inst
->dst
.file
== VGRF
)
2084 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2086 for (int i
= 0; i
< inst
->sources
; i
++) {
2087 if (inst
->src
[i
].file
== VGRF
)
2088 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2092 /* Patch all the references to delta_xy, since they're used in register
2093 * allocation. If they're unused, switch them to BAD_FILE so we don't
2094 * think some random VGRF is delta_xy.
2096 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2097 if (delta_xy
[i
].file
== VGRF
) {
2098 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2099 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2101 delta_xy
[i
].file
= BAD_FILE
;
2106 delete[] remap_table
;
2112 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2114 if (prog_data
->nr_params
== 0)
2117 /* The local thread id is always the last parameter in the list */
2118 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2119 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2120 return prog_data
->nr_params
- 1;
2126 * Struct for handling complex alignments.
2128 * A complex alignment is stored as multiplier and an offset. A value is
2129 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2130 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2133 * N | cplx_align_apply({8, 2}, N)
2134 * ----+-----------------------------
2148 #define CPLX_ALIGN_MAX_MUL 8
2151 cplx_align_assert_sane(struct cplx_align a
)
2153 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2154 assert(a
.offset
< a
.mul
);
2158 * Combines two alignments to produce a least multiple of sorts.
2160 * The returned alignment is the smallest (in terms of multiplier) such that
2161 * anything aligned to both a and b will be aligned to the new alignment.
2162 * This function will assert-fail if a and b are not compatible, i.e. if the
2163 * offset parameters are such that no common alignment is possible.
2165 static struct cplx_align
2166 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2168 cplx_align_assert_sane(a
);
2169 cplx_align_assert_sane(b
);
2171 /* Assert that the alignments agree. */
2172 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2174 return a
.mul
> b
.mul
? a
: b
;
2178 * Apply a complex alignment
2180 * This function will return the smallest number greater than or equal to
2181 * offset that is aligned to align.
2184 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2186 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2189 #define UNIFORM_SLOT_SIZE 4
2191 struct uniform_slot_info
{
2192 /** True if the given uniform slot is live */
2195 /** True if this slot and the next slot must remain contiguous */
2196 unsigned contiguous
:1;
2198 struct cplx_align align
;
2202 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2203 unsigned num_slots
, unsigned alignment
)
2205 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2206 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2208 /* We can't align a slot to anything less than the slot size */
2209 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2211 struct cplx_align align
= {alignment
, 0};
2212 cplx_align_assert_sane(align
);
2214 for (unsigned i
= 0; i
< num_slots
; i
++) {
2215 slots
[i
].is_live
= true;
2216 if (i
< num_slots
- 1)
2217 slots
[i
].contiguous
= true;
2219 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2220 if (slots
[i
].align
.mul
== 0) {
2221 slots
[i
].align
= align
;
2223 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2229 * Assign UNIFORM file registers to either push constants or pull constants.
2231 * We allow a fragment shader to have more than the specified minimum
2232 * maximum number of fragment shader uniform components (64). If
2233 * there are too many of these, they'd fill up all of register space.
2234 * So, this will push some of them out to the pull constant buffer and
2235 * update the program to load them.
2238 fs_visitor::assign_constant_locations()
2240 /* Only the first compile gets to decide on locations. */
2241 if (push_constant_loc
) {
2242 assert(pull_constant_loc
);
2246 if (compiler
->compact_params
) {
2247 struct uniform_slot_info slots
[uniforms
];
2248 memset(slots
, 0, sizeof(slots
));
2250 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2251 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2252 if (inst
->src
[i
].file
!= UNIFORM
)
2255 /* NIR tightly packs things so the uniform number might not be
2256 * aligned (if we have a double right after a float, for
2257 * instance). This is fine because the process of re-arranging
2258 * them will ensure that things are properly aligned. The offset
2259 * into that uniform, however, must be aligned.
2261 * In Vulkan, we have explicit offsets but everything is crammed
2262 * into a single "variable" so inst->src[i].nr will always be 0.
2263 * Everything will be properly aligned relative to that one base.
2265 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2267 unsigned u
= inst
->src
[i
].nr
+
2268 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2273 unsigned slots_read
;
2274 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2275 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2277 unsigned bytes_read
= inst
->components_read(i
) *
2278 type_sz(inst
->src
[i
].type
);
2279 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2282 assert(u
+ slots_read
<= uniforms
);
2283 mark_uniform_slots_read(&slots
[u
], slots_read
,
2284 type_sz(inst
->src
[i
].type
));
2288 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2290 /* Only allow 16 registers (128 uniform components) as push constants.
2292 * Just demote the end of the list. We could probably do better
2293 * here, demoting things that are rarely used in the program first.
2295 * If changing this value, note the limitation about total_regs in
2298 unsigned int max_push_components
= 16 * 8;
2299 if (subgroup_id_index
>= 0)
2300 max_push_components
--; /* Save a slot for the thread ID */
2302 /* We push small arrays, but no bigger than 16 floats. This is big
2303 * enough for a vec4 but hopefully not large enough to push out other
2304 * stuff. We should probably use a better heuristic at some point.
2306 const unsigned int max_chunk_size
= 16;
2308 unsigned int num_push_constants
= 0;
2309 unsigned int num_pull_constants
= 0;
2311 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2312 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2314 /* Default to -1 meaning no location */
2315 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2316 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2318 int chunk_start
= -1;
2319 struct cplx_align align
;
2320 for (unsigned u
= 0; u
< uniforms
; u
++) {
2321 if (!slots
[u
].is_live
) {
2322 assert(chunk_start
== -1);
2326 /* Skip subgroup_id_index to put it in the last push register. */
2327 if (subgroup_id_index
== (int)u
)
2330 if (chunk_start
== -1) {
2332 align
= slots
[u
].align
;
2334 /* Offset into the chunk */
2335 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2337 /* Shift the slot alignment down by the chunk offset so it is
2338 * comparable with the base chunk alignment.
2340 struct cplx_align slot_align
= slots
[u
].align
;
2342 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2344 align
= cplx_align_combine(align
, slot_align
);
2347 /* Sanity check the alignment */
2348 cplx_align_assert_sane(align
);
2350 if (slots
[u
].contiguous
)
2353 /* Adjust the alignment to be in terms of slots, not bytes */
2354 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2355 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2356 align
.mul
/= UNIFORM_SLOT_SIZE
;
2357 align
.offset
/= UNIFORM_SLOT_SIZE
;
2359 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2360 unsigned chunk_size
= u
- chunk_start
+ 1;
2361 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2362 (chunk_size
< max_chunk_size
&&
2363 push_start_align
+ chunk_size
<= max_push_components
)) {
2364 /* Align up the number of push constants */
2365 num_push_constants
= push_start_align
;
2366 for (unsigned i
= 0; i
< chunk_size
; i
++)
2367 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2369 /* We need to pull this one */
2370 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2371 for (unsigned i
= 0; i
< chunk_size
; i
++)
2372 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2375 /* Reset the chunk and start again */
2379 /* Add the CS local thread ID uniform at the end of the push constants */
2380 if (subgroup_id_index
>= 0)
2381 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2383 /* As the uniforms are going to be reordered, stash the old array and
2384 * create two new arrays for push/pull params.
2386 uint32_t *param
= stage_prog_data
->param
;
2387 stage_prog_data
->nr_params
= num_push_constants
;
2388 if (num_push_constants
) {
2389 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2390 num_push_constants
);
2392 stage_prog_data
->param
= NULL
;
2394 assert(stage_prog_data
->nr_pull_params
== 0);
2395 assert(stage_prog_data
->pull_param
== NULL
);
2396 if (num_pull_constants
> 0) {
2397 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2398 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2399 num_pull_constants
);
2402 /* Up until now, the param[] array has been indexed by reg + offset
2403 * of UNIFORM registers. Move pull constants into pull_param[] and
2404 * condense param[] to only contain the uniforms we chose to push.
2406 * NOTE: Because we are condensing the params[] array, we know that
2407 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2408 * having to make a copy.
2410 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2411 uint32_t value
= param
[i
];
2412 if (pull_constant_loc
[i
] != -1) {
2413 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2414 } else if (push_constant_loc
[i
] != -1) {
2415 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2420 /* If we don't want to compact anything, just set up dummy push/pull
2421 * arrays. All the rest of the compiler cares about are these arrays.
2423 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2424 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2426 for (unsigned u
= 0; u
< uniforms
; u
++)
2427 push_constant_loc
[u
] = u
;
2429 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2432 /* Now that we know how many regular uniforms we'll push, reduce the
2433 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2435 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2436 for (int i
= 0; i
< 4; i
++) {
2437 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2439 if (push_length
+ range
->length
> 64)
2440 range
->length
= 64 - push_length
;
2442 push_length
+= range
->length
;
2444 assert(push_length
<= 64);
2448 fs_visitor::get_pull_locs(const fs_reg
&src
,
2449 unsigned *out_surf_index
,
2450 unsigned *out_pull_index
)
2452 assert(src
.file
== UNIFORM
);
2454 if (src
.nr
>= UBO_START
) {
2455 const struct brw_ubo_range
*range
=
2456 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2458 /* If this access is in our (reduced) range, use the push data. */
2459 if (src
.offset
/ 32 < range
->length
)
2462 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2463 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2465 prog_data
->has_ubo_pull
= true;
2469 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2471 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2472 /* A regular uniform push constant */
2473 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2474 *out_pull_index
= pull_constant_loc
[location
];
2476 prog_data
->has_ubo_pull
= true;
2484 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2485 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2488 fs_visitor::lower_constant_loads()
2490 unsigned index
, pull_index
;
2492 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2493 /* Set up the annotation tracking for new generated instructions. */
2494 const fs_builder
ibld(this, block
, inst
);
2496 for (int i
= 0; i
< inst
->sources
; i
++) {
2497 if (inst
->src
[i
].file
!= UNIFORM
)
2500 /* We'll handle this case later */
2501 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2504 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2507 assert(inst
->src
[i
].stride
== 0);
2509 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2510 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2511 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2512 const unsigned base
= pull_index
* 4;
2514 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2515 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2517 /* Rewrite the instruction to use the temporary VGRF. */
2518 inst
->src
[i
].file
= VGRF
;
2519 inst
->src
[i
].nr
= dst
.nr
;
2520 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2521 inst
->src
[i
].offset
% 4;
2524 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2525 inst
->src
[0].file
== UNIFORM
) {
2527 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2530 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2534 inst
->remove(block
);
2537 invalidate_live_intervals();
2541 fs_visitor::opt_algebraic()
2543 bool progress
= false;
2545 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2546 switch (inst
->opcode
) {
2547 case BRW_OPCODE_MOV
:
2548 if (!devinfo
->has_64bit_types
&&
2549 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2550 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2551 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2552 assert(inst
->dst
.type
== inst
->src
[0].type
);
2553 assert(!inst
->saturate
);
2554 assert(!inst
->src
[0].abs
);
2555 assert(!inst
->src
[0].negate
);
2556 const brw::fs_builder
ibld(this, block
, inst
);
2558 if (inst
->src
[0].file
== IMM
) {
2559 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2560 brw_imm_ud(inst
->src
[0].u64
>> 32));
2561 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2562 brw_imm_ud(inst
->src
[0].u64
));
2564 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2565 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2566 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2567 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2570 inst
->remove(block
);
2574 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2575 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2576 inst
->dst
.is_null() &&
2577 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2578 inst
->src
[0].abs
= false;
2579 inst
->src
[0].negate
= false;
2584 if (inst
->src
[0].file
!= IMM
)
2587 if (inst
->saturate
) {
2588 /* Full mixed-type saturates don't happen. However, we can end up
2591 * mov.sat(8) g21<1>DF -1F
2593 * Other mixed-size-but-same-base-type cases may also be possible.
2595 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2596 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2597 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2598 assert(!"unimplemented: saturate mixed types");
2600 if (brw_saturate_immediate(inst
->src
[0].type
,
2601 &inst
->src
[0].as_brw_reg())) {
2602 inst
->saturate
= false;
2608 case BRW_OPCODE_MUL
:
2609 if (inst
->src
[1].file
!= IMM
)
2613 if (inst
->src
[1].is_one()) {
2614 inst
->opcode
= BRW_OPCODE_MOV
;
2615 inst
->src
[1] = reg_undef
;
2621 if (inst
->src
[1].is_negative_one()) {
2622 inst
->opcode
= BRW_OPCODE_MOV
;
2623 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2624 inst
->src
[1] = reg_undef
;
2629 if (inst
->src
[0].file
== IMM
) {
2630 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2631 inst
->opcode
= BRW_OPCODE_MOV
;
2632 inst
->src
[0].f
*= inst
->src
[1].f
;
2633 inst
->src
[1] = reg_undef
;
2638 case BRW_OPCODE_ADD
:
2639 if (inst
->src
[1].file
!= IMM
)
2642 if (inst
->src
[0].file
== IMM
) {
2643 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2644 inst
->opcode
= BRW_OPCODE_MOV
;
2645 inst
->src
[0].f
+= inst
->src
[1].f
;
2646 inst
->src
[1] = reg_undef
;
2652 if (inst
->src
[0].equals(inst
->src
[1]) ||
2653 inst
->src
[1].is_zero()) {
2654 /* On Gen8+, the OR instruction can have a source modifier that
2655 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2656 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2658 if (inst
->src
[0].negate
) {
2659 inst
->opcode
= BRW_OPCODE_NOT
;
2660 inst
->src
[0].negate
= false;
2662 inst
->opcode
= BRW_OPCODE_MOV
;
2664 inst
->src
[1] = reg_undef
;
2669 case BRW_OPCODE_CMP
:
2670 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2671 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2672 inst
->src
[1].is_zero() &&
2673 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2674 inst
->src
[0].abs
= false;
2675 inst
->src
[0].negate
= false;
2680 case BRW_OPCODE_SEL
:
2681 if (!devinfo
->has_64bit_types
&&
2682 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2683 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2684 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2685 assert(inst
->dst
.type
== inst
->src
[0].type
);
2686 assert(!inst
->saturate
);
2687 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2688 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2689 const brw::fs_builder
ibld(this, block
, inst
);
2691 set_predicate(inst
->predicate
,
2692 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2693 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2694 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2695 set_predicate(inst
->predicate
,
2696 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2697 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2698 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2700 inst
->remove(block
);
2703 if (inst
->src
[0].equals(inst
->src
[1])) {
2704 inst
->opcode
= BRW_OPCODE_MOV
;
2705 inst
->src
[1] = reg_undef
;
2706 inst
->predicate
= BRW_PREDICATE_NONE
;
2707 inst
->predicate_inverse
= false;
2709 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2710 switch (inst
->conditional_mod
) {
2711 case BRW_CONDITIONAL_LE
:
2712 case BRW_CONDITIONAL_L
:
2713 switch (inst
->src
[1].type
) {
2714 case BRW_REGISTER_TYPE_F
:
2715 if (inst
->src
[1].f
>= 1.0f
) {
2716 inst
->opcode
= BRW_OPCODE_MOV
;
2717 inst
->src
[1] = reg_undef
;
2718 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2726 case BRW_CONDITIONAL_GE
:
2727 case BRW_CONDITIONAL_G
:
2728 switch (inst
->src
[1].type
) {
2729 case BRW_REGISTER_TYPE_F
:
2730 if (inst
->src
[1].f
<= 0.0f
) {
2731 inst
->opcode
= BRW_OPCODE_MOV
;
2732 inst
->src
[1] = reg_undef
;
2733 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2745 case BRW_OPCODE_MAD
:
2746 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2747 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2748 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2750 if (inst
->src
[1].is_one()) {
2751 inst
->opcode
= BRW_OPCODE_ADD
;
2752 inst
->src
[1] = inst
->src
[2];
2753 inst
->src
[2] = reg_undef
;
2755 } else if (inst
->src
[2].is_one()) {
2756 inst
->opcode
= BRW_OPCODE_ADD
;
2757 inst
->src
[2] = reg_undef
;
2761 case SHADER_OPCODE_BROADCAST
:
2762 if (is_uniform(inst
->src
[0])) {
2763 inst
->opcode
= BRW_OPCODE_MOV
;
2765 inst
->force_writemask_all
= true;
2767 } else if (inst
->src
[1].file
== IMM
) {
2768 inst
->opcode
= BRW_OPCODE_MOV
;
2769 /* It's possible that the selected component will be too large and
2770 * overflow the register. This can happen if someone does a
2771 * readInvocation() from GLSL or SPIR-V and provides an OOB
2772 * invocationIndex. If this happens and we some how manage
2773 * to constant fold it in and get here, then component() may cause
2774 * us to start reading outside of the VGRF which will lead to an
2775 * assert later. Instead, just let it wrap around if it goes over
2778 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2779 inst
->src
[0] = component(inst
->src
[0], comp
);
2781 inst
->force_writemask_all
= true;
2786 case SHADER_OPCODE_SHUFFLE
:
2787 if (is_uniform(inst
->src
[0])) {
2788 inst
->opcode
= BRW_OPCODE_MOV
;
2791 } else if (inst
->src
[1].file
== IMM
) {
2792 inst
->opcode
= BRW_OPCODE_MOV
;
2793 inst
->src
[0] = component(inst
->src
[0],
2804 /* Swap if src[0] is immediate. */
2805 if (progress
&& inst
->is_commutative()) {
2806 if (inst
->src
[0].file
== IMM
) {
2807 fs_reg tmp
= inst
->src
[1];
2808 inst
->src
[1] = inst
->src
[0];
2817 * Optimize sample messages that have constant zero values for the trailing
2818 * texture coordinates. We can just reduce the message length for these
2819 * instructions instead of reserving a register for it. Trailing parameters
2820 * that aren't sent default to zero anyway. This will cause the dead code
2821 * eliminator to remove the MOV instruction that would otherwise be emitted to
2822 * set up the zero value.
2825 fs_visitor::opt_zero_samples()
2827 /* Gen4 infers the texturing opcode based on the message length so we can't
2830 if (devinfo
->gen
< 5)
2833 bool progress
= false;
2835 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2836 if (!inst
->is_tex())
2839 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2841 if (load_payload
->is_head_sentinel() ||
2842 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2845 /* We don't want to remove the message header or the first parameter.
2846 * Removing the first parameter is not allowed, see the Haswell PRM
2847 * volume 7, page 149:
2849 * "Parameter 0 is required except for the sampleinfo message, which
2850 * has no parameter 0"
2852 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2853 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2854 (inst
->exec_size
/ 8) +
2855 inst
->header_size
- 1].is_zero()) {
2856 inst
->mlen
-= inst
->exec_size
/ 8;
2862 invalidate_live_intervals();
2868 * Optimize sample messages which are followed by the final RT write.
2870 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2871 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2872 * final texturing results copied to the framebuffer write payload and modify
2873 * them to write to the framebuffer directly.
2876 fs_visitor::opt_sampler_eot()
2878 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2880 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2883 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2886 /* FINISHME: It should be possible to implement this optimization when there
2887 * are multiple drawbuffers.
2889 if (key
->nr_color_regions
!= 1)
2892 /* Requires emitting a bunch of saturating MOV instructions during logical
2893 * send lowering to clamp the color payload, which the sampler unit isn't
2894 * going to do for us.
2896 if (key
->clamp_fragment_color
)
2899 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2900 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2901 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2902 assert(fb_write
->eot
);
2903 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2905 /* There wasn't one; nothing to do. */
2906 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2909 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2911 /* 3D Sampler » Messages » Message Format
2913 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2914 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2916 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2917 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2918 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2919 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2920 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2921 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2922 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2923 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2926 /* XXX - This shouldn't be necessary. */
2927 if (tex_inst
->prev
->is_head_sentinel())
2930 /* Check that the FB write sources are fully initialized by the single
2931 * texturing instruction.
2933 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2934 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2935 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2936 fb_write
->size_read(i
) != tex_inst
->size_written
)
2938 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2939 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2944 assert(!tex_inst
->eot
); /* We can't get here twice */
2945 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2947 const fs_builder
ibld(this, block
, tex_inst
);
2949 tex_inst
->offset
|= fb_write
->target
<< 24;
2950 tex_inst
->eot
= true;
2951 tex_inst
->dst
= ibld
.null_reg_ud();
2952 tex_inst
->size_written
= 0;
2953 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2955 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2956 * flag and submit a header together with the sampler message as required
2959 invalidate_live_intervals();
2964 fs_visitor::opt_register_renaming()
2966 bool progress
= false;
2969 unsigned remap
[alloc
.count
];
2970 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
2972 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2973 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2975 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2976 inst
->opcode
== BRW_OPCODE_WHILE
) {
2980 /* Rewrite instruction sources. */
2981 for (int i
= 0; i
< inst
->sources
; i
++) {
2982 if (inst
->src
[i
].file
== VGRF
&&
2983 remap
[inst
->src
[i
].nr
] != ~0u &&
2984 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2985 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2990 const unsigned dst
= inst
->dst
.nr
;
2993 inst
->dst
.file
== VGRF
&&
2994 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2995 !inst
->is_partial_write()) {
2996 if (remap
[dst
] == ~0u) {
2999 remap
[dst
] = alloc
.allocate(regs_written(inst
));
3000 inst
->dst
.nr
= remap
[dst
];
3003 } else if (inst
->dst
.file
== VGRF
&&
3004 remap
[dst
] != ~0u &&
3005 remap
[dst
] != dst
) {
3006 inst
->dst
.nr
= remap
[dst
];
3012 invalidate_live_intervals();
3014 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3015 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3016 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3025 * Remove redundant or useless discard jumps.
3027 * For example, we can eliminate jumps in the following sequence:
3029 * discard-jump (redundant with the next jump)
3030 * discard-jump (useless; jumps to the next instruction)
3034 fs_visitor::opt_redundant_discard_jumps()
3036 bool progress
= false;
3038 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3040 fs_inst
*placeholder_halt
= NULL
;
3041 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3042 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3043 placeholder_halt
= inst
;
3048 if (!placeholder_halt
)
3051 /* Delete any HALTs immediately before the placeholder halt. */
3052 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3053 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3054 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3055 prev
->remove(last_bblock
);
3060 invalidate_live_intervals();
3066 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3067 * from \p r.offset which overlaps the region starting at \p s.offset and
3068 * spanning \p ds bytes.
3070 static inline unsigned
3071 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3073 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3074 const int shift
= rel_offset
/ REG_SIZE
;
3075 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3076 assert(reg_space(r
) == reg_space(s
) &&
3077 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3078 return ((1 << n
) - 1) << shift
;
3082 fs_visitor::compute_to_mrf()
3084 bool progress
= false;
3087 /* No MRFs on Gen >= 7. */
3088 if (devinfo
->gen
>= 7)
3091 calculate_live_intervals();
3093 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3097 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3098 inst
->is_partial_write() ||
3099 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3100 inst
->dst
.type
!= inst
->src
[0].type
||
3101 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3102 !inst
->src
[0].is_contiguous() ||
3103 inst
->src
[0].offset
% REG_SIZE
!= 0)
3106 /* Can't compute-to-MRF this GRF if someone else was going to
3109 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
3112 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3113 * things that computed the value of all GRFs of the source region. The
3114 * regs_left bitset keeps track of the registers we haven't yet found a
3115 * generating instruction for.
3117 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3119 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3120 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3121 inst
->src
[0], inst
->size_read(0))) {
3122 /* Found the last thing to write our reg we want to turn
3123 * into a compute-to-MRF.
3126 /* If this one instruction didn't populate all the
3127 * channels, bail. We might be able to rewrite everything
3128 * that writes that reg, but it would require smarter
3131 if (scan_inst
->is_partial_write())
3134 /* Handling things not fully contained in the source of the copy
3135 * would need us to understand coalescing out more than one MOV at
3138 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3139 inst
->src
[0], inst
->size_read(0)))
3142 /* SEND instructions can't have MRF as a destination. */
3143 if (scan_inst
->mlen
)
3146 if (devinfo
->gen
== 6) {
3147 /* gen6 math instructions must have the destination be
3148 * GRF, so no compute-to-MRF for them.
3150 if (scan_inst
->is_math()) {
3155 /* Clear the bits for any registers this instruction overwrites. */
3156 regs_left
&= ~mask_relative_to(
3157 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3162 /* We don't handle control flow here. Most computation of
3163 * values that end up in MRFs are shortly before the MRF
3166 if (block
->start() == scan_inst
)
3169 /* You can't read from an MRF, so if someone else reads our
3170 * MRF's source GRF that we wanted to rewrite, that stops us.
3172 bool interfered
= false;
3173 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3174 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3175 inst
->src
[0], inst
->size_read(0))) {
3182 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3183 inst
->dst
, inst
->size_written
)) {
3184 /* If somebody else writes our MRF here, we can't
3185 * compute-to-MRF before that.
3190 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3191 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3192 inst
->dst
, inst
->size_written
)) {
3193 /* Found a SEND instruction, which means that there are
3194 * live values in MRFs from base_mrf to base_mrf +
3195 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3205 /* Found all generating instructions of our MRF's source value, so it
3206 * should be safe to rewrite them to point to the MRF directly.
3208 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3210 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3211 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3212 inst
->src
[0], inst
->size_read(0))) {
3213 /* Clear the bits for any registers this instruction overwrites. */
3214 regs_left
&= ~mask_relative_to(
3215 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3217 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3218 reg_offset(inst
->src
[0]);
3220 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3221 /* Apply the same address transformation done by the hardware
3222 * for COMPR4 MRF writes.
3224 assert(rel_offset
< 2 * REG_SIZE
);
3225 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3227 /* Clear the COMPR4 bit if the generating instruction is not
3230 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3231 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3234 /* Calculate the MRF number the result of this instruction is
3235 * ultimately written to.
3237 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3240 scan_inst
->dst
.file
= MRF
;
3241 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3242 scan_inst
->saturate
|= inst
->saturate
;
3249 inst
->remove(block
);
3254 invalidate_live_intervals();
3260 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3261 * flow. We could probably do better here with some form of divergence
3265 fs_visitor::eliminate_find_live_channel()
3267 bool progress
= false;
3270 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3271 /* The optimization below assumes that channel zero is live on thread
3272 * dispatch, which may not be the case if the fixed function dispatches
3278 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3279 switch (inst
->opcode
) {
3285 case BRW_OPCODE_ENDIF
:
3286 case BRW_OPCODE_WHILE
:
3290 case FS_OPCODE_DISCARD_JUMP
:
3291 /* This can potentially make control flow non-uniform until the end
3296 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3298 inst
->opcode
= BRW_OPCODE_MOV
;
3299 inst
->src
[0] = brw_imm_ud(0u);
3301 inst
->force_writemask_all
= true;
3315 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3316 * instructions to FS_OPCODE_REP_FB_WRITE.
3319 fs_visitor::emit_repclear_shader()
3321 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3323 int color_mrf
= base_mrf
+ 2;
3327 mov
= bld
.exec_all().group(4, 0)
3328 .MOV(brw_message_reg(color_mrf
),
3329 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3331 struct brw_reg reg
=
3332 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3333 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3334 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3336 mov
= bld
.exec_all().group(4, 0)
3337 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3340 fs_inst
*write
= NULL
;
3341 if (key
->nr_color_regions
== 1) {
3342 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3343 write
->saturate
= key
->clamp_fragment_color
;
3344 write
->base_mrf
= color_mrf
;
3346 write
->header_size
= 0;
3349 assume(key
->nr_color_regions
> 0);
3351 struct brw_reg header
=
3352 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3353 bld
.exec_all().group(16, 0)
3354 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3356 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3358 bld
.exec_all().group(1, 0)
3359 .MOV(component(header
, 2), brw_imm_ud(i
));
3362 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3363 write
->saturate
= key
->clamp_fragment_color
;
3364 write
->base_mrf
= base_mrf
;
3366 write
->header_size
= 2;
3371 write
->last_rt
= true;
3375 assign_constant_locations();
3376 assign_curb_setup();
3378 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3380 assert(mov
->src
[0].file
== FIXED_GRF
);
3381 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3388 * Walks through basic blocks, looking for repeated MRF writes and
3389 * removing the later ones.
3392 fs_visitor::remove_duplicate_mrf_writes()
3394 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3395 bool progress
= false;
3397 /* Need to update the MRF tracking for compressed instructions. */
3398 if (dispatch_width
>= 16)
3401 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3403 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3404 if (inst
->is_control_flow()) {
3405 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3408 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3409 inst
->dst
.file
== MRF
) {
3410 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3411 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3412 inst
->dst
.equals(prev_inst
->dst
) &&
3413 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3414 inst
->saturate
== prev_inst
->saturate
&&
3415 inst
->predicate
== prev_inst
->predicate
&&
3416 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3417 inst
->exec_size
== prev_inst
->exec_size
) {
3418 inst
->remove(block
);
3424 /* Clear out the last-write records for MRFs that were overwritten. */
3425 if (inst
->dst
.file
== MRF
) {
3426 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3429 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3430 /* Found a SEND instruction, which will include two or fewer
3431 * implied MRF writes. We could do better here.
3433 for (unsigned i
= 0; i
< inst
->implied_mrf_writes(); i
++) {
3434 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3438 /* Clear out any MRF move records whose sources got overwritten. */
3439 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3440 if (last_mrf_move
[i
] &&
3441 regions_overlap(inst
->dst
, inst
->size_written
,
3442 last_mrf_move
[i
]->src
[0],
3443 last_mrf_move
[i
]->size_read(0))) {
3444 last_mrf_move
[i
] = NULL
;
3448 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3449 inst
->dst
.file
== MRF
&&
3450 inst
->src
[0].file
!= ARF
&&
3451 !inst
->is_partial_write()) {
3452 last_mrf_move
[inst
->dst
.nr
] = inst
;
3457 invalidate_live_intervals();
3463 * Rounding modes for conversion instructions are included for each
3464 * conversion, but right now it is a state. So once it is set,
3465 * we don't need to call it again for subsequent calls.
3467 * This is useful for vector/matrices conversions, as setting the
3468 * mode once is enough for the full vector/matrix
3471 fs_visitor::remove_extra_rounding_modes()
3473 bool progress
= false;
3474 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3476 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3477 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3478 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3479 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3481 base_mode
= BRW_RND_MODE_RTNE
;
3482 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3483 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3484 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3486 base_mode
= BRW_RND_MODE_RTZ
;
3488 foreach_block (block
, cfg
) {
3489 brw_rnd_mode prev_mode
= base_mode
;
3491 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3492 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3493 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3494 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3495 if (mode
== prev_mode
) {
3496 inst
->remove(block
);
3506 invalidate_live_intervals();
3512 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3514 /* Clear the flag for registers that actually got read (as expected). */
3515 for (int i
= 0; i
< inst
->sources
; i
++) {
3517 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3518 grf
= inst
->src
[i
].nr
;
3523 if (grf
>= first_grf
&&
3524 grf
< first_grf
+ grf_len
) {
3525 deps
[grf
- first_grf
] = false;
3526 if (inst
->exec_size
== 16)
3527 deps
[grf
- first_grf
+ 1] = false;
3533 * Implements this workaround for the original 965:
3535 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3536 * check for post destination dependencies on this instruction, software
3537 * must ensure that there is no destination hazard for the case of ‘write
3538 * followed by a posted write’ shown in the following example.
3541 * 2. send r3.xy <rest of send instruction>
3544 * Due to no post-destination dependency check on the ‘send’, the above
3545 * code sequence could have two instructions (1 and 2) in flight at the
3546 * same time that both consider ‘r3’ as the target of their final writes.
3549 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3552 int write_len
= regs_written(inst
);
3553 int first_write_grf
= inst
->dst
.nr
;
3554 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3555 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3557 memset(needs_dep
, false, sizeof(needs_dep
));
3558 memset(needs_dep
, true, write_len
);
3560 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3562 /* Walk backwards looking for writes to registers we're writing which
3563 * aren't read since being written. If we hit the start of the program,
3564 * we assume that there are no outstanding dependencies on entry to the
3567 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3568 /* If we hit control flow, assume that there *are* outstanding
3569 * dependencies, and force their cleanup before our instruction.
3571 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3572 for (int i
= 0; i
< write_len
; i
++) {
3574 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3575 first_write_grf
+ i
);
3580 /* We insert our reads as late as possible on the assumption that any
3581 * instruction but a MOV that might have left us an outstanding
3582 * dependency has more latency than a MOV.
3584 if (scan_inst
->dst
.file
== VGRF
) {
3585 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3586 int reg
= scan_inst
->dst
.nr
+ i
;
3588 if (reg
>= first_write_grf
&&
3589 reg
< first_write_grf
+ write_len
&&
3590 needs_dep
[reg
- first_write_grf
]) {
3591 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3592 needs_dep
[reg
- first_write_grf
] = false;
3593 if (scan_inst
->exec_size
== 16)
3594 needs_dep
[reg
- first_write_grf
+ 1] = false;
3599 /* Clear the flag for registers that actually got read (as expected). */
3600 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3602 /* Continue the loop only if we haven't resolved all the dependencies */
3604 for (i
= 0; i
< write_len
; i
++) {
3614 * Implements this workaround for the original 965:
3616 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3617 * used as a destination register until after it has been sourced by an
3618 * instruction with a different destination register.
3621 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3623 int write_len
= regs_written(inst
);
3624 unsigned first_write_grf
= inst
->dst
.nr
;
3625 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3626 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3628 memset(needs_dep
, false, sizeof(needs_dep
));
3629 memset(needs_dep
, true, write_len
);
3630 /* Walk forwards looking for writes to registers we're writing which aren't
3631 * read before being written.
3633 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3634 /* If we hit control flow, force resolve all remaining dependencies. */
3635 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3636 for (int i
= 0; i
< write_len
; i
++) {
3638 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3639 first_write_grf
+ i
);
3644 /* Clear the flag for registers that actually got read (as expected). */
3645 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3647 /* We insert our reads as late as possible since they're reading the
3648 * result of a SEND, which has massive latency.
3650 if (scan_inst
->dst
.file
== VGRF
&&
3651 scan_inst
->dst
.nr
>= first_write_grf
&&
3652 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3653 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3654 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3656 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3659 /* Continue the loop only if we haven't resolved all the dependencies */
3661 for (i
= 0; i
< write_len
; i
++) {
3671 fs_visitor::insert_gen4_send_dependency_workarounds()
3673 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3676 bool progress
= false;
3678 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3679 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3680 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3681 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3687 invalidate_live_intervals();
3691 * Turns the generic expression-style uniform pull constant load instruction
3692 * into a hardware-specific series of instructions for loading a pull
3695 * The expression style allows the CSE pass before this to optimize out
3696 * repeated loads from the same offset, and gives the pre-register-allocation
3697 * scheduling full flexibility, while the conversion to native instructions
3698 * allows the post-register-allocation scheduler the best information
3701 * Note that execution masking for setting up pull constant loads is special:
3702 * the channels that need to be written are unrelated to the current execution
3703 * mask, since a later instruction will use one of the result channels as a
3704 * source operand for all 8 or 16 of its channels.
3707 fs_visitor::lower_uniform_pull_constant_loads()
3709 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3710 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3713 if (devinfo
->gen
>= 7) {
3714 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3715 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3717 ubld
.group(8, 0).MOV(payload
,
3718 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3719 ubld
.group(1, 0).MOV(component(payload
, 2),
3720 brw_imm_ud(inst
->src
[1].ud
/ 16));
3722 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3723 inst
->src
[1] = payload
;
3724 inst
->header_size
= 1;
3727 invalidate_live_intervals();
3729 /* Before register allocation, we didn't tell the scheduler about the
3730 * MRF we use. We know it's safe to use this MRF because nothing
3731 * else does except for register spill/unspill, which generates and
3732 * uses its MRF within a single IR instruction.
3734 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3741 fs_visitor::lower_load_payload()
3743 bool progress
= false;
3745 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3746 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3749 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3750 assert(inst
->saturate
== false);
3751 fs_reg dst
= inst
->dst
;
3753 /* Get rid of COMPR4. We'll add it back in if we need it */
3754 if (dst
.file
== MRF
)
3755 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3757 const fs_builder
ibld(this, block
, inst
);
3758 const fs_builder ubld
= ibld
.exec_all();
3760 for (uint8_t i
= 0; i
< inst
->header_size
;) {
3761 /* Number of header GRFs to initialize at once with a single MOV
3765 (i
+ 1 < inst
->header_size
&& inst
->src
[i
].stride
== 1 &&
3766 inst
->src
[i
+ 1].equals(byte_offset(inst
->src
[i
], REG_SIZE
))) ?
3769 if (inst
->src
[i
].file
!= BAD_FILE
)
3770 ubld
.group(8 * n
, 0).MOV(retype(dst
, BRW_REGISTER_TYPE_UD
),
3771 retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
));
3773 dst
= byte_offset(dst
, n
* REG_SIZE
);
3777 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3778 inst
->exec_size
> 8) {
3779 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3780 * a straightforward copy. Instead, the result of the
3781 * LOAD_PAYLOAD is treated as interleaved and the first four
3782 * non-header sources are unpacked as:
3793 * This is used for gen <= 5 fb writes.
3795 assert(inst
->exec_size
== 16);
3796 assert(inst
->header_size
+ 4 <= inst
->sources
);
3797 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3798 if (inst
->src
[i
].file
!= BAD_FILE
) {
3799 if (devinfo
->has_compr4
) {
3800 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3801 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3802 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3804 /* Platform doesn't have COMPR4. We have to fake it */
3805 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3806 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3808 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3815 /* The loop above only ever incremented us through the first set
3816 * of 4 registers. However, thanks to the magic of COMPR4, we
3817 * actually wrote to the first 8 registers, so we need to take
3818 * that into account now.
3822 /* The COMPR4 code took care of the first 4 sources. We'll let
3823 * the regular path handle any remaining sources. Yes, we are
3824 * modifying the instruction but we're about to delete it so
3825 * this really doesn't hurt anything.
3827 inst
->header_size
+= 4;
3830 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3831 if (inst
->src
[i
].file
!= BAD_FILE
) {
3832 dst
.type
= inst
->src
[i
].type
;
3833 ibld
.MOV(dst
, inst
->src
[i
]);
3835 dst
.type
= BRW_REGISTER_TYPE_UD
;
3837 dst
= offset(dst
, ibld
, 1);
3840 inst
->remove(block
);
3845 invalidate_live_intervals();
3851 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3853 const fs_builder
ibld(this, block
, inst
);
3855 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3856 if (inst
->src
[1].file
== IMM
&&
3857 (( ud
&& inst
->src
[1].ud
<= UINT16_MAX
) ||
3858 (!ud
&& inst
->src
[1].d
<= INT16_MAX
&& inst
->src
[1].d
>= INT16_MIN
))) {
3859 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3860 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3863 * If multiplying by an immediate value that fits in 16-bits, do a
3864 * single MUL instruction with that value in the proper location.
3866 if (devinfo
->gen
< 7) {
3867 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3868 ibld
.MOV(imm
, inst
->src
[1]);
3869 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3871 ibld
.MUL(inst
->dst
, inst
->src
[0],
3872 ud
? brw_imm_uw(inst
->src
[1].ud
)
3873 : brw_imm_w(inst
->src
[1].d
));
3876 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3877 * do 32-bit integer multiplication in one instruction, but instead
3878 * must do a sequence (which actually calculates a 64-bit result):
3880 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3881 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3882 * mov(8) g2<1>D acc0<8,8,1>D
3884 * But on Gen > 6, the ability to use second accumulator register
3885 * (acc1) for non-float data types was removed, preventing a simple
3886 * implementation in SIMD16. A 16-channel result can be calculated by
3887 * executing the three instructions twice in SIMD8, once with quarter
3888 * control of 1Q for the first eight channels and again with 2Q for
3889 * the second eight channels.
3891 * Which accumulator register is implicitly accessed (by AccWrEnable
3892 * for instance) is determined by the quarter control. Unfortunately
3893 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3894 * implicit accumulator access by an instruction with 2Q will access
3895 * acc1 regardless of whether the data type is usable in acc1.
3897 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3898 * integer data types.
3900 * Since we only want the low 32-bits of the result, we can do two
3901 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3902 * adjust the high result and add them (like the mach is doing):
3904 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3905 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3906 * shl(8) g9<1>D g8<8,8,1>D 16D
3907 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3909 * We avoid the shl instruction by realizing that we only want to add
3910 * the low 16-bits of the "high" result to the high 16-bits of the
3911 * "low" result and using proper regioning on the add:
3913 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3914 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3915 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3917 * Since it does not use the (single) accumulator register, we can
3918 * schedule multi-component multiplications much better.
3921 bool needs_mov
= false;
3922 fs_reg orig_dst
= inst
->dst
;
3924 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
3925 * reusing the original destination is impossible due to hardware
3926 * restrictions, source/destination overlap, or it being the null
3929 fs_reg low
= inst
->dst
;
3930 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3931 regions_overlap(inst
->dst
, inst
->size_written
,
3932 inst
->src
[0], inst
->size_read(0)) ||
3933 regions_overlap(inst
->dst
, inst
->size_written
,
3934 inst
->src
[1], inst
->size_read(1)) ||
3935 inst
->dst
.stride
>= 4) {
3937 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3941 /* Get a new VGRF but keep the same stride as inst->dst */
3942 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
3943 high
.stride
= inst
->dst
.stride
;
3944 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3946 if (devinfo
->gen
>= 7) {
3947 if (inst
->src
[1].abs
)
3948 lower_src_modifiers(this, block
, inst
, 1);
3950 if (inst
->src
[1].file
== IMM
) {
3951 ibld
.MUL(low
, inst
->src
[0],
3952 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3953 ibld
.MUL(high
, inst
->src
[0],
3954 brw_imm_uw(inst
->src
[1].ud
>> 16));
3956 ibld
.MUL(low
, inst
->src
[0],
3957 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3958 ibld
.MUL(high
, inst
->src
[0],
3959 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3962 if (inst
->src
[0].abs
)
3963 lower_src_modifiers(this, block
, inst
, 0);
3965 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3967 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3971 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3972 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3973 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3975 if (needs_mov
|| inst
->conditional_mod
)
3976 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
3981 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
3983 const fs_builder
ibld(this, block
, inst
);
3985 /* Considering two 64-bit integers ab and cd where each letter ab
3986 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
3987 * only need to provide the YZ part of the result. -------
3989 * Only BD needs to be 64 bits. For AD and BC we only care + AD
3990 * about the lower 32 bits (since they are part of the upper + BC
3991 * 32 bits of our result). AC is not needed since it starts + AC
3992 * on the 65th bit of the result. -------
3995 unsigned int q_regs
= regs_written(inst
);
3996 unsigned int d_regs
= (q_regs
+ 1) / 2;
3998 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
3999 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4000 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4002 /* Here we need the full 64 bit result for 32b * 32b. */
4003 if (devinfo
->has_integer_dword_mul
) {
4004 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4005 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4007 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4008 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4009 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4011 fs_inst
*mul
= ibld
.MUL(acc
,
4012 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4013 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4014 mul
->writes_accumulator
= true;
4016 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4017 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4018 ibld
.MOV(bd_low
, acc
);
4020 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4021 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4024 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4025 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4026 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4027 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4029 ibld
.ADD(ad
, ad
, bc
);
4030 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4031 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4033 ibld
.MOV(inst
->dst
, bd
);
4037 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4039 const fs_builder
ibld(this, block
, inst
);
4041 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4042 * High" instruction:
4044 * "An added preliminary mov is required for source modification on
4046 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4047 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4048 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4050 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4051 lower_src_modifiers(this, block
, inst
, 1);
4053 /* Should have been lowered to 8-wide. */
4054 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4055 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4056 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4057 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4059 if (devinfo
->gen
>= 8) {
4060 /* Until Gen8, integer multiplies read 32-bits from one source,
4061 * and 16-bits from the other, and relying on the MACH instruction
4062 * to generate the high bits of the result.
4064 * On Gen8, the multiply instruction does a full 32x32-bit
4065 * multiply, but in order to do a 64-bit multiply we can simulate
4066 * the previous behavior and then use a MACH instruction.
4068 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4069 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4070 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4071 mul
->src
[1].stride
*= 2;
4073 if (mul
->src
[1].file
== IMM
) {
4074 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4076 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4078 /* Among other things the quarter control bits influence which
4079 * accumulator register is used by the hardware for instructions
4080 * that access the accumulator implicitly (e.g. MACH). A
4081 * second-half instruction would normally map to acc1, which
4082 * doesn't exist on Gen7 and up (the hardware does emulate it for
4083 * floating-point instructions *only* by taking advantage of the
4084 * extra precision of acc0 not normally used for floating point
4087 * HSW and up are careful enough not to try to access an
4088 * accumulator register that doesn't exist, but on earlier Gen7
4089 * hardware we need to make sure that the quarter control bits are
4090 * zero to avoid non-deterministic behaviour and emit an extra MOV
4091 * to get the result masked correctly according to the current
4095 mach
->force_writemask_all
= true;
4096 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4097 ibld
.MOV(inst
->dst
, mach
->dst
);
4102 fs_visitor::lower_integer_multiplication()
4104 bool progress
= false;
4106 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4107 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4108 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4109 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4110 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4111 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4112 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4113 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4114 lower_mul_qword_inst(inst
, block
);
4115 inst
->remove(block
);
4117 } else if (!inst
->dst
.is_accumulator() &&
4118 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4119 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4120 !devinfo
->has_integer_dword_mul
) {
4121 lower_mul_dword_inst(inst
, block
);
4122 inst
->remove(block
);
4125 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4126 lower_mulh_inst(inst
, block
);
4127 inst
->remove(block
);
4134 invalidate_live_intervals();
4140 fs_visitor::lower_minmax()
4142 assert(devinfo
->gen
< 6);
4144 bool progress
= false;
4146 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4147 const fs_builder
ibld(this, block
, inst
);
4149 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4150 inst
->predicate
== BRW_PREDICATE_NONE
) {
4151 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4152 * the original SEL.L/GE instruction
4154 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4155 inst
->conditional_mod
);
4156 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4157 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4164 invalidate_live_intervals();
4170 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4171 fs_reg
*dst
, fs_reg color
, unsigned components
)
4173 if (key
->clamp_fragment_color
) {
4174 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4175 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4177 for (unsigned i
= 0; i
< components
; i
++)
4179 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4184 for (unsigned i
= 0; i
< components
; i
++)
4185 dst
[i
] = offset(color
, bld
, i
);
4189 brw_fb_write_msg_control(const fs_inst
*inst
,
4190 const struct brw_wm_prog_data
*prog_data
)
4194 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4195 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4196 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4197 } else if (prog_data
->dual_src_blend
) {
4198 assert(inst
->exec_size
== 8);
4200 if (inst
->group
% 16 == 0)
4201 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4202 else if (inst
->group
% 16 == 8)
4203 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4205 unreachable("Invalid dual-source FB write instruction group");
4207 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4209 if (inst
->exec_size
== 16)
4210 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4211 else if (inst
->exec_size
== 8)
4212 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4214 unreachable("Invalid FB write execution size");
4221 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4222 const struct brw_wm_prog_data
*prog_data
,
4223 const brw_wm_prog_key
*key
,
4224 const fs_visitor::thread_payload
&payload
)
4226 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4227 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4228 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4229 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4230 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4231 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4232 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4233 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4234 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4235 const unsigned components
=
4236 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4238 /* We can potentially have a message length of up to 15, so we have to set
4239 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4242 int header_size
= 2, payload_header_size
;
4243 unsigned length
= 0;
4245 if (devinfo
->gen
< 6) {
4246 /* TODO: Support SIMD32 on gen4-5 */
4247 assert(bld
.group() < 16);
4249 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4250 * an implied MOV from g0,g1 to the start of the message. The MOV from
4251 * g0 is handled by the hardware and the MOV from g1 is provided by the
4252 * generator. This is required because, on gen4-5, the generator may
4253 * generate two write messages with different message lengths in order
4254 * to handle AA data properly.
4256 * Also, since the pixel mask goes in the g0 portion of the message and
4257 * since render target writes are the last thing in the shader, we write
4258 * the pixel mask directly into g0 and it will get copied as part of the
4261 if (prog_data
->uses_kill
) {
4262 bld
.exec_all().group(1, 0)
4263 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4264 brw_flag_reg(0, 1));
4267 assert(length
== 0);
4269 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4270 prog_data
->uses_kill
) ||
4271 (devinfo
->gen
< 11 &&
4272 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4273 /* From the Sandy Bridge PRM, volume 4, page 198:
4275 * "Dispatched Pixel Enables. One bit per pixel indicating
4276 * which pixels were originally enabled when the thread was
4277 * dispatched. This field is only required for the end-of-
4278 * thread message and on all dual-source messages."
4280 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4282 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4283 if (bld
.group() < 16) {
4284 /* The header starts off as g0 and g1 for the first half */
4285 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4286 BRW_REGISTER_TYPE_UD
));
4288 /* The header starts off as g0 and g2 for the second half */
4289 assert(bld
.group() < 32);
4290 const fs_reg header_sources
[2] = {
4291 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4292 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4294 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4297 uint32_t g00_bits
= 0;
4299 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4302 if (inst
->target
> 0 && prog_data
->replicate_alpha
)
4303 g00_bits
|= 1 << 11;
4305 /* Set computes stencil to render target */
4306 if (prog_data
->computed_stencil
)
4307 g00_bits
|= 1 << 14;
4310 /* OR extra bits into g0.0 */
4311 ubld
.group(1, 0).OR(component(header
, 0),
4312 retype(brw_vec1_grf(0, 0),
4313 BRW_REGISTER_TYPE_UD
),
4314 brw_imm_ud(g00_bits
));
4317 /* Set the render target index for choosing BLEND_STATE. */
4318 if (inst
->target
> 0) {
4319 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4322 if (prog_data
->uses_kill
) {
4323 assert(bld
.group() < 16);
4324 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4325 BRW_REGISTER_TYPE_UW
),
4326 brw_flag_reg(0, 1));
4329 assert(length
== 0);
4330 sources
[0] = header
;
4331 sources
[1] = horiz_offset(header
, 8);
4334 assert(length
== 0 || length
== 2);
4335 header_size
= length
;
4337 if (payload
.aa_dest_stencil_reg
[0]) {
4338 assert(inst
->group
< 16);
4339 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4340 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4341 .MOV(sources
[length
],
4342 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4346 bool src0_alpha_present
= false;
4348 if (src0_alpha
.file
!= BAD_FILE
) {
4349 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4350 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4351 .annotate("FB write src0 alpha");
4352 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4353 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4354 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4357 src0_alpha_present
= true;
4358 } else if (prog_data
->replicate_alpha
&& inst
->target
!= 0) {
4359 /* Handle the case when fragment shader doesn't write to draw buffer
4360 * zero. No need to call setup_color_payload() for src0_alpha because
4361 * alpha value will be undefined.
4363 length
+= bld
.dispatch_width() / 8;
4364 src0_alpha_present
= true;
4367 if (sample_mask
.file
!= BAD_FILE
) {
4368 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4369 BRW_REGISTER_TYPE_UD
);
4371 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4372 * relevant. Since it's unsigned single words one vgrf is always
4373 * 16-wide, but only the lower or higher 8 channels will be used by the
4374 * hardware when doing a SIMD8 write depending on whether we have
4375 * selected the subspans for the first or second half respectively.
4377 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4378 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4379 sample_mask
.stride
*= 2;
4381 bld
.exec_all().annotate("FB write oMask")
4382 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4388 payload_header_size
= length
;
4390 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4393 if (color1
.file
!= BAD_FILE
) {
4394 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4398 if (src_depth
.file
!= BAD_FILE
) {
4399 sources
[length
] = src_depth
;
4403 if (dst_depth
.file
!= BAD_FILE
) {
4404 sources
[length
] = dst_depth
;
4408 if (src_stencil
.file
!= BAD_FILE
) {
4409 assert(devinfo
->gen
>= 9);
4410 assert(bld
.dispatch_width() == 8);
4412 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4413 * available on gen9+. As such it's impossible to have both enabled at the
4414 * same time and therefore length cannot overrun the array.
4416 assert(length
< 15);
4418 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4419 bld
.exec_all().annotate("FB write OS")
4420 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4421 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4426 if (devinfo
->gen
>= 7) {
4427 /* Send from the GRF */
4428 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4429 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4430 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4431 load
->dst
= payload
;
4433 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4434 uint32_t ex_desc
= 0;
4437 (inst
->group
/ 16) << 11 | /* rt slot group */
4438 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4439 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4440 inst
->last_rt
, false);
4442 if (devinfo
->gen
>= 11) {
4443 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4444 * in the extended message descriptor, in lieu of using a header.
4446 ex_desc
= inst
->target
<< 12 | src0_alpha_present
<< 15;
4448 if (key
->nr_color_regions
== 0)
4449 ex_desc
|= 1 << 20; /* Null Render Target */
4452 inst
->opcode
= SHADER_OPCODE_SEND
;
4453 inst
->resize_sources(3);
4454 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4455 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4456 inst
->src
[1] = brw_imm_ud(ex_desc
);
4457 inst
->src
[2] = payload
;
4458 inst
->mlen
= regs_written(load
);
4460 inst
->header_size
= header_size
;
4461 inst
->check_tdr
= true;
4462 inst
->send_has_side_effects
= true;
4464 /* Send from the MRF */
4465 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4466 sources
, length
, payload_header_size
);
4468 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4469 * will do this for us if we just give it a COMPR4 destination.
4471 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4472 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4474 if (devinfo
->gen
< 6) {
4475 /* Set up src[0] for the implied MOV from grf0-1 */
4476 inst
->resize_sources(1);
4477 inst
->src
[0] = brw_vec8_grf(0, 0);
4479 inst
->resize_sources(0);
4482 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4483 inst
->mlen
= regs_written(load
);
4484 inst
->header_size
= header_size
;
4489 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4491 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4492 const unsigned length
= 2;
4493 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4495 if (bld
.group() < 16) {
4496 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4497 BRW_REGISTER_TYPE_UD
));
4499 assert(bld
.group() < 32);
4500 const fs_reg header_sources
[] = {
4501 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4502 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4504 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4507 inst
->resize_sources(1);
4508 inst
->src
[0] = header
;
4509 inst
->opcode
= FS_OPCODE_FB_READ
;
4510 inst
->mlen
= length
;
4511 inst
->header_size
= length
;
4515 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4516 const fs_reg
&coordinate
,
4517 const fs_reg
&shadow_c
,
4518 const fs_reg
&lod
, const fs_reg
&lod2
,
4519 const fs_reg
&surface
,
4520 const fs_reg
&sampler
,
4521 unsigned coord_components
,
4522 unsigned grad_components
)
4524 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4525 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4526 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4527 fs_reg msg_end
= msg_begin
;
4530 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4532 for (unsigned i
= 0; i
< coord_components
; i
++)
4533 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4534 offset(coordinate
, bld
, i
));
4536 msg_end
= offset(msg_end
, bld
, coord_components
);
4538 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4539 * require all three components to be present and zero if they are unused.
4541 if (coord_components
> 0 &&
4542 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4543 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4544 for (unsigned i
= coord_components
; i
< 3; i
++)
4545 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4547 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4550 if (op
== SHADER_OPCODE_TXD
) {
4551 /* TXD unsupported in SIMD16 mode. */
4552 assert(bld
.dispatch_width() == 8);
4554 /* the slots for u and v are always present, but r is optional */
4555 if (coord_components
< 2)
4556 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4559 * dPdx = dudx, dvdx, drdx
4560 * dPdy = dudy, dvdy, drdy
4562 * 1-arg: Does not exist.
4564 * 2-arg: dudx dvdx dudy dvdy
4565 * dPdx.x dPdx.y dPdy.x dPdy.y
4568 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4569 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4570 * m5 m6 m7 m8 m9 m10
4572 for (unsigned i
= 0; i
< grad_components
; i
++)
4573 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4575 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4577 for (unsigned i
= 0; i
< grad_components
; i
++)
4578 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4580 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4584 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4585 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4587 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4588 bld
.dispatch_width() == 16);
4590 const brw_reg_type type
=
4591 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4592 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4593 bld
.MOV(retype(msg_end
, type
), lod
);
4594 msg_end
= offset(msg_end
, bld
, 1);
4597 if (shadow_c
.file
!= BAD_FILE
) {
4598 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4599 /* There's no plain shadow compare message, so we use shadow
4600 * compare with a bias of 0.0.
4602 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4603 msg_end
= offset(msg_end
, bld
, 1);
4606 bld
.MOV(msg_end
, shadow_c
);
4607 msg_end
= offset(msg_end
, bld
, 1);
4611 inst
->src
[0] = reg_undef
;
4612 inst
->src
[1] = surface
;
4613 inst
->src
[2] = sampler
;
4614 inst
->resize_sources(3);
4615 inst
->base_mrf
= msg_begin
.nr
;
4616 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4617 inst
->header_size
= 1;
4621 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4622 const fs_reg
&coordinate
,
4623 const fs_reg
&shadow_c
,
4624 const fs_reg
&lod
, const fs_reg
&lod2
,
4625 const fs_reg
&sample_index
,
4626 const fs_reg
&surface
,
4627 const fs_reg
&sampler
,
4628 unsigned coord_components
,
4629 unsigned grad_components
)
4631 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4632 fs_reg msg_coords
= message
;
4633 unsigned header_size
= 0;
4635 if (inst
->offset
!= 0) {
4636 /* The offsets set up by the visitor are in the m1 header, so we can't
4643 for (unsigned i
= 0; i
< coord_components
; i
++)
4644 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4645 offset(coordinate
, bld
, i
));
4647 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4648 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4650 if (shadow_c
.file
!= BAD_FILE
) {
4651 fs_reg msg_shadow
= msg_lod
;
4652 bld
.MOV(msg_shadow
, shadow_c
);
4653 msg_lod
= offset(msg_shadow
, bld
, 1);
4658 case SHADER_OPCODE_TXL
:
4660 bld
.MOV(msg_lod
, lod
);
4661 msg_end
= offset(msg_lod
, bld
, 1);
4663 case SHADER_OPCODE_TXD
:
4666 * dPdx = dudx, dvdx, drdx
4667 * dPdy = dudy, dvdy, drdy
4669 * Load up these values:
4670 * - dudx dudy dvdx dvdy drdx drdy
4671 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4674 for (unsigned i
= 0; i
< grad_components
; i
++) {
4675 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4676 msg_end
= offset(msg_end
, bld
, 1);
4678 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4679 msg_end
= offset(msg_end
, bld
, 1);
4682 case SHADER_OPCODE_TXS
:
4683 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4684 bld
.MOV(msg_lod
, lod
);
4685 msg_end
= offset(msg_lod
, bld
, 1);
4687 case SHADER_OPCODE_TXF
:
4688 msg_lod
= offset(msg_coords
, bld
, 3);
4689 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4690 msg_end
= offset(msg_lod
, bld
, 1);
4692 case SHADER_OPCODE_TXF_CMS
:
4693 msg_lod
= offset(msg_coords
, bld
, 3);
4695 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4697 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4698 msg_end
= offset(msg_lod
, bld
, 2);
4705 inst
->src
[0] = reg_undef
;
4706 inst
->src
[1] = surface
;
4707 inst
->src
[2] = sampler
;
4708 inst
->resize_sources(3);
4709 inst
->base_mrf
= message
.nr
;
4710 inst
->mlen
= msg_end
.nr
- message
.nr
;
4711 inst
->header_size
= header_size
;
4713 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4714 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4718 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4720 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4723 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4727 sampler_msg_type(const gen_device_info
*devinfo
,
4728 opcode opcode
, bool shadow_compare
)
4730 assert(devinfo
->gen
>= 5);
4732 case SHADER_OPCODE_TEX
:
4733 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4734 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4736 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4737 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4738 case SHADER_OPCODE_TXL
:
4739 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4740 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4741 case SHADER_OPCODE_TXL_LZ
:
4742 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4743 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4744 case SHADER_OPCODE_TXS
:
4745 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4746 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4747 case SHADER_OPCODE_TXD
:
4748 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4749 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4750 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4751 case SHADER_OPCODE_TXF
:
4752 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4753 case SHADER_OPCODE_TXF_LZ
:
4754 assert(devinfo
->gen
>= 9);
4755 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4756 case SHADER_OPCODE_TXF_CMS_W
:
4757 assert(devinfo
->gen
>= 9);
4758 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4759 case SHADER_OPCODE_TXF_CMS
:
4760 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4761 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4762 case SHADER_OPCODE_TXF_UMS
:
4763 assert(devinfo
->gen
>= 7);
4764 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4765 case SHADER_OPCODE_TXF_MCS
:
4766 assert(devinfo
->gen
>= 7);
4767 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4768 case SHADER_OPCODE_LOD
:
4769 return GEN5_SAMPLER_MESSAGE_LOD
;
4770 case SHADER_OPCODE_TG4
:
4771 assert(devinfo
->gen
>= 7);
4772 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4773 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4775 case SHADER_OPCODE_TG4_OFFSET
:
4776 assert(devinfo
->gen
>= 7);
4777 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4778 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4779 case SHADER_OPCODE_SAMPLEINFO
:
4780 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4782 unreachable("not reached");
4787 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4788 const fs_reg
&coordinate
,
4789 const fs_reg
&shadow_c
,
4790 fs_reg lod
, const fs_reg
&lod2
,
4791 const fs_reg
&min_lod
,
4792 const fs_reg
&sample_index
,
4794 const fs_reg
&surface
,
4795 const fs_reg
&sampler
,
4796 const fs_reg
&surface_handle
,
4797 const fs_reg
&sampler_handle
,
4798 const fs_reg
&tg4_offset
,
4799 unsigned coord_components
,
4800 unsigned grad_components
)
4802 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4803 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4804 unsigned reg_width
= bld
.dispatch_width() / 8;
4805 unsigned header_size
= 0, length
= 0;
4806 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4807 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4808 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4810 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4811 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4812 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4814 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4815 inst
->offset
!= 0 || inst
->eot
||
4816 op
== SHADER_OPCODE_SAMPLEINFO
||
4817 sampler_handle
.file
!= BAD_FILE
||
4818 is_high_sampler(devinfo
, sampler
)) {
4819 /* For general texture offsets (no txf workaround), we need a header to
4822 * TG4 needs to place its channel select in the header, for interaction
4823 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4824 * larger sampler numbers we need to offset the Sampler State Pointer in
4827 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4831 /* If we're requesting fewer than four channels worth of response,
4832 * and we have an explicit header, we need to set up the sampler
4833 * writemask. It's reversed from normal: 1 means "don't write".
4835 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4836 assert(regs_written(inst
) % reg_width
== 0);
4837 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4838 inst
->offset
|= mask
<< 12;
4841 /* Build the actual header */
4842 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4843 const fs_builder ubld1
= ubld
.group(1, 0);
4844 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4846 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4847 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4848 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4849 /* The vertex and fragment stages have g0.2 set to 0, so
4850 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4851 * must set it to 0 to avoid setting undesirable bits in the
4854 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4857 if (sampler_handle
.file
!= BAD_FILE
) {
4858 /* Bindless sampler handles aren't relative to the sampler state
4859 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
4860 * Instead, it's an absolute pointer relative to dynamic state base
4863 * Sampler states are 16 bytes each and the pointer we give here has
4864 * to be 32-byte aligned. In order to avoid more indirect messages
4865 * than required, we assume that all bindless sampler states are
4866 * 32-byte aligned. This sacrifices a bit of general state base
4867 * address space but means we can do something more efficient in the
4870 ubld1
.MOV(component(header
, 3), sampler_handle
);
4871 } else if (is_high_sampler(devinfo
, sampler
)) {
4872 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4873 assert(sampler
.ud
>= 16);
4874 const int sampler_state_size
= 16; /* 16 bytes */
4876 ubld1
.ADD(component(header
, 3),
4877 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4878 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
4880 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
4881 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
4882 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
4883 ubld1
.ADD(component(header
, 3),
4884 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4890 if (shadow_c
.file
!= BAD_FILE
) {
4891 bld
.MOV(sources
[length
], shadow_c
);
4895 bool coordinate_done
= false;
4897 /* Set up the LOD info */
4900 case SHADER_OPCODE_TXL
:
4901 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4902 op
= SHADER_OPCODE_TXL_LZ
;
4905 bld
.MOV(sources
[length
], lod
);
4908 case SHADER_OPCODE_TXD
:
4909 /* TXD should have been lowered in SIMD16 mode. */
4910 assert(bld
.dispatch_width() == 8);
4912 /* Load dPdx and the coordinate together:
4913 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4915 for (unsigned i
= 0; i
< coord_components
; i
++) {
4916 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4918 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4919 * only derivatives for (u, v, r).
4921 if (i
< grad_components
) {
4922 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4923 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4927 coordinate_done
= true;
4929 case SHADER_OPCODE_TXS
:
4930 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4933 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4934 /* We need an LOD; just use 0 */
4935 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
4938 case SHADER_OPCODE_TXF
:
4939 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4940 * On Gen9 they are u, v, lod, r
4942 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4944 if (devinfo
->gen
>= 9) {
4945 if (coord_components
>= 2) {
4946 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4947 offset(coordinate
, bld
, 1));
4949 sources
[length
] = brw_imm_d(0);
4954 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4955 op
= SHADER_OPCODE_TXF_LZ
;
4957 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4961 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4962 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4963 offset(coordinate
, bld
, i
));
4965 coordinate_done
= true;
4968 case SHADER_OPCODE_TXF_CMS
:
4969 case SHADER_OPCODE_TXF_CMS_W
:
4970 case SHADER_OPCODE_TXF_UMS
:
4971 case SHADER_OPCODE_TXF_MCS
:
4972 if (op
== SHADER_OPCODE_TXF_UMS
||
4973 op
== SHADER_OPCODE_TXF_CMS
||
4974 op
== SHADER_OPCODE_TXF_CMS_W
) {
4975 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4979 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4980 /* Data from the multisample control surface. */
4981 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4984 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4987 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4988 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4991 offset(mcs
, bld
, 1));
4996 /* There is no offsetting for this message; just copy in the integer
4997 * texture coordinates.
4999 for (unsigned i
= 0; i
< coord_components
; i
++)
5000 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5001 offset(coordinate
, bld
, i
));
5003 coordinate_done
= true;
5005 case SHADER_OPCODE_TG4_OFFSET
:
5006 /* More crazy intermixing */
5007 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5008 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5010 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5011 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5012 offset(tg4_offset
, bld
, i
));
5014 if (coord_components
== 3) /* r if present */
5015 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5017 coordinate_done
= true;
5023 /* Set up the coordinate (except for cases where it was done above) */
5024 if (!coordinate_done
) {
5025 for (unsigned i
= 0; i
< coord_components
; i
++)
5026 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5029 if (min_lod
.file
!= BAD_FILE
) {
5030 /* Account for all of the missing coordinate sources */
5031 length
+= 4 - coord_components
;
5032 if (op
== SHADER_OPCODE_TXD
)
5033 length
+= (3 - grad_components
) * 2;
5035 bld
.MOV(sources
[length
++], min_lod
);
5040 mlen
= length
* reg_width
- header_size
;
5042 mlen
= length
* reg_width
;
5044 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5045 BRW_REGISTER_TYPE_F
);
5046 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5048 /* Generate the SEND. */
5049 inst
->opcode
= SHADER_OPCODE_SEND
;
5051 inst
->header_size
= header_size
;
5053 const unsigned msg_type
=
5054 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5055 const unsigned simd_mode
=
5056 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5057 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5059 uint32_t base_binding_table_index
;
5061 case SHADER_OPCODE_TG4
:
5062 case SHADER_OPCODE_TG4_OFFSET
:
5063 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5065 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5066 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5069 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5073 inst
->sfid
= BRW_SFID_SAMPLER
;
5074 if (surface
.file
== IMM
&&
5075 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5076 inst
->desc
= brw_sampler_desc(devinfo
,
5077 surface
.ud
+ base_binding_table_index
,
5078 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5081 0 /* return_format unused on gen7+ */);
5082 inst
->src
[0] = brw_imm_ud(0);
5083 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5084 } else if (surface_handle
.file
!= BAD_FILE
) {
5085 /* Bindless surface */
5086 assert(devinfo
->gen
>= 9);
5087 inst
->desc
= brw_sampler_desc(devinfo
,
5089 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5092 0 /* return_format unused on gen7+ */);
5094 /* For bindless samplers, the entire address is included in the message
5095 * header so we can leave the portion in the message descriptor 0.
5097 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5098 inst
->src
[0] = brw_imm_ud(0);
5100 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5101 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5102 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5103 inst
->src
[0] = desc
;
5106 /* We assume that the driver provided the handle in the top 20 bits so
5107 * we can use the surface handle directly as the extended descriptor.
5109 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5111 /* Immediate portion of the descriptor */
5112 inst
->desc
= brw_sampler_desc(devinfo
,
5117 0 /* return_format unused on gen7+ */);
5118 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5119 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5120 if (surface
.equals(sampler
)) {
5121 /* This case is common in GL */
5122 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5124 if (sampler_handle
.file
!= BAD_FILE
) {
5125 ubld
.MOV(desc
, surface
);
5126 } else if (sampler
.file
== IMM
) {
5127 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5129 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5130 ubld
.OR(desc
, desc
, surface
);
5133 if (base_binding_table_index
)
5134 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5135 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5137 inst
->src
[0] = component(desc
, 0);
5138 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5141 inst
->src
[2] = src_payload
;
5142 inst
->resize_sources(3);
5145 /* EOT sampler messages don't make sense to split because it would
5146 * involve ending half of the thread early.
5148 assert(inst
->group
== 0);
5149 /* We need to use SENDC for EOT sampler messages */
5150 inst
->check_tdr
= true;
5151 inst
->send_has_side_effects
= true;
5154 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5155 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5159 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5161 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5162 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5163 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5164 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5165 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5166 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5167 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5168 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5169 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5170 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5171 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5172 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5173 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5174 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5175 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5176 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5177 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5179 if (devinfo
->gen
>= 7) {
5180 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5181 shadow_c
, lod
, lod2
, min_lod
,
5183 mcs
, surface
, sampler
,
5184 surface_handle
, sampler_handle
,
5186 coord_components
, grad_components
);
5187 } else if (devinfo
->gen
>= 5) {
5188 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5189 shadow_c
, lod
, lod2
, sample_index
,
5191 coord_components
, grad_components
);
5193 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5194 shadow_c
, lod
, lod2
,
5196 coord_components
, grad_components
);
5201 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5203 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5205 /* Get the logical send arguments. */
5206 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5207 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5208 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5209 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5210 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5211 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5212 assert(arg
.file
== IMM
);
5214 /* We must have exactly one of surface and surface_handle */
5215 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5217 /* Calculate the total number of components of the payload. */
5218 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5219 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5221 const bool is_typed_access
=
5222 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5223 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5224 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5226 const bool is_surface_access
= is_typed_access
||
5227 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
||
5228 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
||
5229 inst
->opcode
== SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
;
5231 const bool is_stateless
=
5232 surface
.file
== IMM
&& (surface
.ud
== BRW_BTI_STATELESS
||
5233 surface
.ud
== GEN8_BTI_STATELESS_NON_COHERENT
);
5235 const bool has_side_effects
= inst
->has_side_effects();
5236 fs_reg sample_mask
= has_side_effects
? bld
.sample_mask_reg() :
5237 fs_reg(brw_imm_d(0xffff));
5239 /* From the BDW PRM Volume 7, page 147:
5241 * "For the Data Cache Data Port*, the header must be present for the
5242 * following message types: [...] Typed read/write/atomics"
5244 * Earlier generations have a similar wording. Because of this restriction
5245 * we don't attempt to implement sample masks via predication for such
5246 * messages prior to Gen9, since we have to provide a header anyway. On
5247 * Gen11+ the header has been removed so we can only use predication.
5249 * For all stateless A32 messages, we also need a header
5252 if ((devinfo
->gen
< 9 && is_typed_access
) || is_stateless
) {
5253 fs_builder ubld
= bld
.exec_all().group(8, 0);
5254 header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5255 ubld
.MOV(header
, brw_imm_d(0));
5257 /* Both the typed and scattered byte/dword A32 messages take a buffer
5258 * base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
5259 * MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
5260 * for more details.) This is conveniently where the HW places the
5261 * scratch surface base address.
5263 * From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
5265 * "When a thread becomes 'active' it is allocated a portion of
5266 * scratch space, sized according to PerThreadScratchSpace. The
5267 * starting location of each thread’s scratch space allocation,
5268 * ScratchSpaceOffset, is passed in the thread payload in
5269 * R0.5[31:10] and is specified as a 1KB-granular offset from the
5270 * GeneralStateBaseAddress. The computation of ScratchSpaceOffset
5271 * includes the starting address of the stage’s scratch space
5272 * allocation, as programmed by ScratchSpaceBasePointer."
5274 * The base address is passed in bits R0.5[31:10] and the bottom 10
5275 * bits of R0.5 are used for other things. Therefore, we have to
5276 * mask off the bottom 10 bits so that we don't get a garbage base
5279 ubld
.group(1, 0).AND(component(header
, 5),
5280 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
5281 brw_imm_ud(0xfffffc00));
5283 if (is_surface_access
)
5284 ubld
.group(1, 0).MOV(component(header
, 7), sample_mask
);
5286 const unsigned header_sz
= header
.file
!= BAD_FILE
? 1 : 0;
5288 fs_reg payload
, payload2
;
5289 unsigned mlen
, ex_mlen
= 0;
5290 if (devinfo
->gen
>= 9 &&
5291 (src
.file
== BAD_FILE
|| header
.file
== BAD_FILE
)) {
5292 /* We have split sends on gen9 and above */
5293 if (header
.file
== BAD_FILE
) {
5294 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5295 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5296 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5297 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5299 assert(src
.file
== BAD_FILE
);
5301 payload2
= bld
.move_to_vgrf(addr
, addr_sz
);
5303 ex_mlen
= addr_sz
* (inst
->exec_size
/ 8);
5306 /* Allocate space for the payload. */
5307 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5308 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5309 fs_reg
*const components
= new fs_reg
[sz
];
5312 /* Construct the payload. */
5313 if (header
.file
!= BAD_FILE
)
5314 components
[n
++] = header
;
5316 for (unsigned i
= 0; i
< addr_sz
; i
++)
5317 components
[n
++] = offset(addr
, bld
, i
);
5319 for (unsigned i
= 0; i
< src_sz
; i
++)
5320 components
[n
++] = offset(src
, bld
, i
);
5322 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5323 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5325 delete[] components
;
5328 /* Predicate the instruction on the sample mask if no header is
5331 if ((header
.file
== BAD_FILE
|| !is_surface_access
) &&
5332 sample_mask
.file
!= BAD_FILE
&& sample_mask
.file
!= IMM
) {
5333 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5334 if (inst
->predicate
) {
5335 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5336 assert(!inst
->predicate_inverse
);
5337 assert(inst
->flag_subreg
< 2);
5338 /* Combine the sample mask with the existing predicate by using a
5339 * vertical predication mode.
5341 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5342 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
5346 inst
->flag_subreg
= 2;
5347 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5348 inst
->predicate_inverse
= false;
5349 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5355 switch (inst
->opcode
) {
5356 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5357 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5358 /* Byte scattered opcodes go through the normal data cache */
5359 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5362 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5363 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5364 sfid
= devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
5365 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
5366 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
5369 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5370 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5371 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5372 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5373 /* Untyped Surface messages go through the data cache but the SFID value
5374 * changed on Haswell.
5376 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5377 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5378 GEN7_SFID_DATAPORT_DATA_CACHE
);
5381 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5382 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5383 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5384 /* Typed surface messages go through the render cache on IVB and the
5385 * data cache on HSW+.
5387 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5388 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5389 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5393 unreachable("Unsupported surface opcode");
5397 switch (inst
->opcode
) {
5398 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5399 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5400 arg
.ud
, /* num_channels */
5404 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5405 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5406 arg
.ud
, /* num_channels */
5410 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5411 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5412 arg
.ud
, /* bit_size */
5416 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5417 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5418 arg
.ud
, /* bit_size */
5422 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5423 assert(arg
.ud
== 32); /* bit_size */
5424 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5428 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5429 assert(arg
.ud
== 32); /* bit_size */
5430 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5434 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5435 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5436 arg
.ud
, /* atomic_op */
5437 !inst
->dst
.is_null());
5440 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5441 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5442 arg
.ud
, /* atomic_op */
5443 !inst
->dst
.is_null());
5446 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5447 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5448 arg
.ud
, /* num_channels */
5452 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5453 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5454 arg
.ud
, /* num_channels */
5458 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5459 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5460 arg
.ud
, /* atomic_op */
5461 !inst
->dst
.is_null());
5465 unreachable("Unknown surface logical instruction");
5468 /* Update the original instruction. */
5469 inst
->opcode
= SHADER_OPCODE_SEND
;
5471 inst
->ex_mlen
= ex_mlen
;
5472 inst
->header_size
= header_sz
;
5473 inst
->send_has_side_effects
= has_side_effects
;
5474 inst
->send_is_volatile
= !has_side_effects
;
5476 /* Set up SFID and descriptors */
5479 if (surface
.file
== IMM
) {
5480 inst
->desc
|= surface
.ud
& 0xff;
5481 inst
->src
[0] = brw_imm_ud(0);
5482 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5483 } else if (surface_handle
.file
!= BAD_FILE
) {
5484 /* Bindless surface */
5485 assert(devinfo
->gen
>= 9);
5486 inst
->desc
|= GEN9_BTI_BINDLESS
;
5487 inst
->src
[0] = brw_imm_ud(0);
5489 /* We assume that the driver provided the handle in the top 20 bits so
5490 * we can use the surface handle directly as the extended descriptor.
5492 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5494 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5495 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5496 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5497 inst
->src
[0] = component(tmp
, 0);
5498 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5501 /* Finally, the payload */
5502 inst
->src
[2] = payload
;
5503 inst
->src
[3] = payload2
;
5505 inst
->resize_sources(4);
5509 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5511 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5513 const fs_reg
&addr
= inst
->src
[0];
5514 const fs_reg
&src
= inst
->src
[1];
5515 const unsigned src_comps
= inst
->components_read(1);
5516 assert(inst
->src
[2].file
== IMM
);
5517 const unsigned arg
= inst
->src
[2].ud
;
5518 const bool has_side_effects
= inst
->has_side_effects();
5520 /* If the surface message has side effects and we're a fragment shader, we
5521 * have to predicate with the sample mask to avoid helper invocations.
5523 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
) {
5524 inst
->flag_subreg
= 2;
5525 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5526 inst
->predicate_inverse
= false;
5528 fs_reg sample_mask
= bld
.sample_mask_reg();
5529 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5530 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5534 fs_reg payload
, payload2
;
5535 unsigned mlen
, ex_mlen
= 0;
5536 if (devinfo
->gen
>= 9) {
5537 /* On Skylake and above, we have SENDS */
5538 mlen
= 2 * (inst
->exec_size
/ 8);
5539 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5540 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5541 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5542 BRW_REGISTER_TYPE_UD
);
5544 /* Add two because the address is 64-bit */
5545 const unsigned dwords
= 2 + src_comps
;
5546 mlen
= dwords
* (inst
->exec_size
/ 8);
5552 for (unsigned i
= 0; i
< src_comps
; i
++)
5553 sources
[1 + i
] = offset(src
, bld
, i
);
5555 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5556 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5560 switch (inst
->opcode
) {
5561 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5562 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5563 arg
, /* num_channels */
5567 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5568 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5569 arg
, /* num_channels */
5573 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5574 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5579 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5580 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5585 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5586 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5587 arg
, /* atomic_op */
5588 !inst
->dst
.is_null());
5591 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5592 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5593 arg
, /* atomic_op */
5594 !inst
->dst
.is_null());
5598 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5599 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5600 arg
, /* atomic_op */
5601 !inst
->dst
.is_null());
5605 unreachable("Unknown A64 logical instruction");
5608 /* Update the original instruction. */
5609 inst
->opcode
= SHADER_OPCODE_SEND
;
5611 inst
->ex_mlen
= ex_mlen
;
5612 inst
->header_size
= 0;
5613 inst
->send_has_side_effects
= has_side_effects
;
5614 inst
->send_is_volatile
= !has_side_effects
;
5616 /* Set up SFID and descriptors */
5617 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5619 inst
->resize_sources(4);
5620 inst
->src
[0] = brw_imm_ud(0); /* desc */
5621 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5622 inst
->src
[2] = payload
;
5623 inst
->src
[3] = payload2
;
5627 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5629 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5631 if (devinfo
->gen
>= 7) {
5632 fs_reg index
= inst
->src
[0];
5633 /* We are switching the instruction from an ALU-like instruction to a
5634 * send-from-grf instruction. Since sends can't handle strides or
5635 * source modifiers, we have to make a copy of the offset source.
5637 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5638 bld
.MOV(offset
, inst
->src
[1]);
5640 const unsigned simd_mode
=
5641 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5642 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5644 inst
->opcode
= SHADER_OPCODE_SEND
;
5645 inst
->mlen
= inst
->exec_size
/ 8;
5646 inst
->resize_sources(3);
5648 inst
->sfid
= BRW_SFID_SAMPLER
;
5649 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5650 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5652 if (index
.file
== IMM
) {
5653 inst
->desc
|= index
.ud
& 0xff;
5654 inst
->src
[0] = brw_imm_ud(0);
5656 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5657 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5658 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5659 inst
->src
[0] = component(tmp
, 0);
5661 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5662 inst
->src
[2] = offset
; /* payload */
5664 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5665 BRW_REGISTER_TYPE_UD
);
5667 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5669 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5670 inst
->resize_sources(1);
5671 inst
->base_mrf
= payload
.nr
;
5672 inst
->header_size
= 1;
5673 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5678 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5680 assert(bld
.shader
->devinfo
->gen
< 6);
5683 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5685 if (inst
->sources
> 1) {
5686 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5687 * "Message Payload":
5689 * "Operand0[7]. For the INT DIV functions, this operand is the
5692 * "Operand1[7]. For the INT DIV functions, this operand is the
5695 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5696 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5697 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5699 inst
->resize_sources(1);
5700 inst
->src
[0] = src0
;
5702 assert(inst
->exec_size
== 8);
5703 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5708 fs_visitor::lower_logical_sends()
5710 bool progress
= false;
5712 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5713 const fs_builder
ibld(this, block
, inst
);
5715 switch (inst
->opcode
) {
5716 case FS_OPCODE_FB_WRITE_LOGICAL
:
5717 assert(stage
== MESA_SHADER_FRAGMENT
);
5718 lower_fb_write_logical_send(ibld
, inst
,
5719 brw_wm_prog_data(prog_data
),
5720 (const brw_wm_prog_key
*)key
,
5724 case FS_OPCODE_FB_READ_LOGICAL
:
5725 lower_fb_read_logical_send(ibld
, inst
);
5728 case SHADER_OPCODE_TEX_LOGICAL
:
5729 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5732 case SHADER_OPCODE_TXD_LOGICAL
:
5733 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5736 case SHADER_OPCODE_TXF_LOGICAL
:
5737 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5740 case SHADER_OPCODE_TXL_LOGICAL
:
5741 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5744 case SHADER_OPCODE_TXS_LOGICAL
:
5745 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5748 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5749 lower_sampler_logical_send(ibld
, inst
,
5750 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5753 case FS_OPCODE_TXB_LOGICAL
:
5754 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5757 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5758 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5761 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5762 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5765 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5766 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5769 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5770 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5773 case SHADER_OPCODE_LOD_LOGICAL
:
5774 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5777 case SHADER_OPCODE_TG4_LOGICAL
:
5778 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5781 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5782 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5785 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5786 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5789 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5790 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5791 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5792 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5793 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5794 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5795 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5796 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5797 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5798 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5799 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5800 lower_surface_logical_send(ibld
, inst
);
5803 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5804 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5805 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5806 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5807 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5808 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5809 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5810 lower_a64_logical_send(ibld
, inst
);
5813 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5814 lower_varying_pull_constant_logical_send(ibld
, inst
);
5817 case SHADER_OPCODE_RCP
:
5818 case SHADER_OPCODE_RSQ
:
5819 case SHADER_OPCODE_SQRT
:
5820 case SHADER_OPCODE_EXP2
:
5821 case SHADER_OPCODE_LOG2
:
5822 case SHADER_OPCODE_SIN
:
5823 case SHADER_OPCODE_COS
:
5824 case SHADER_OPCODE_POW
:
5825 case SHADER_OPCODE_INT_QUOTIENT
:
5826 case SHADER_OPCODE_INT_REMAINDER
:
5827 /* The math opcodes are overloaded for the send-like and
5828 * expression-like instructions which seems kind of icky. Gen6+ has
5829 * a native (but rather quirky) MATH instruction so we don't need to
5830 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5831 * logical instructions (which we can easily recognize because they
5832 * have mlen = 0) into send-like virtual instructions.
5834 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5835 lower_math_logical_send(ibld
, inst
);
5850 invalidate_live_intervals();
5856 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
5858 /* This opcode sometimes uses :W type on the source even if the operand is
5859 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
5861 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
5864 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
5867 for (int i
= 0; i
< inst
->sources
; i
++) {
5868 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
5876 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
5878 /* This opcode sometimes uses :W type on the destination even if the
5879 * destination is a :HF, because in gen7 there is no support for :HF, and
5882 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
5883 inst
->dst
.stride
== 1)
5886 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
5887 inst
->dst
.stride
!= 1)
5890 for (int i
= 0; i
< inst
->sources
; i
++) {
5891 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
5899 * Get the closest allowed SIMD width for instruction \p inst accounting for
5900 * some common regioning and execution control restrictions that apply to FPU
5901 * instructions. These restrictions don't necessarily have any relevance to
5902 * instructions not executed by the FPU pipeline like extended math, control
5903 * flow or send message instructions.
5905 * For virtual opcodes it's really up to the instruction -- In some cases
5906 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
5907 * instructions) it may simplify virtual instruction lowering if we can
5908 * enforce FPU-like regioning restrictions already on the virtual instruction,
5909 * in other cases (e.g. virtual send-like instructions) this may be
5910 * excessively restrictive.
5913 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
5914 const fs_inst
*inst
)
5916 /* Maximum execution size representable in the instruction controls. */
5917 unsigned max_width
= MIN2(32, inst
->exec_size
);
5919 /* According to the PRMs:
5920 * "A. In Direct Addressing mode, a source cannot span more than 2
5921 * adjacent GRF registers.
5922 * B. A destination cannot span more than 2 adjacent GRF registers."
5924 * Look for the source or destination with the largest register region
5925 * which is the one that is going to limit the overall execution size of
5926 * the instruction due to this rule.
5928 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5930 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5931 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
5933 /* Calculate the maximum execution size of the instruction based on the
5934 * factor by which it goes over the hardware limit of 2 GRFs.
5937 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
5939 /* According to the IVB PRMs:
5940 * "When destination spans two registers, the source MUST span two
5941 * registers. The exception to the above rule:
5943 * - When source is scalar, the source registers are not incremented.
5944 * - When source is packed integer Word and destination is packed
5945 * integer DWord, the source register is not incremented but the
5946 * source sub register is incremented."
5948 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
5949 * restrictions. The code below intentionally doesn't check whether the
5950 * destination type is integer because empirically the hardware doesn't
5951 * seem to care what the actual type is as long as it's dword-aligned.
5953 if (devinfo
->gen
< 8) {
5954 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5955 /* IVB implements DF scalars as <0;2,1> regions. */
5956 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
5957 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
5958 const bool is_packed_word_exception
=
5959 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
5960 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
5962 /* We check size_read(i) against size_written instead of REG_SIZE
5963 * because we want to properly handle SIMD32. In SIMD32, you can end
5964 * up with writes to 4 registers and a source that reads 2 registers
5965 * and we may still need to lower all the way to SIMD8 in that case.
5967 if (inst
->size_written
> REG_SIZE
&&
5968 inst
->size_read(i
) != 0 &&
5969 inst
->size_read(i
) < inst
->size_written
&&
5970 !is_scalar_exception
&& !is_packed_word_exception
) {
5971 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5972 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5977 if (devinfo
->gen
< 6) {
5978 /* From the G45 PRM, Volume 4 Page 361:
5980 * "Operand Alignment Rule: With the exceptions listed below, a
5981 * source/destination operand in general should be aligned to even
5982 * 256-bit physical register with a region size equal to two 256-bit
5983 * physical registers."
5985 * Normally we enforce this by allocating virtual registers to the
5986 * even-aligned class. But we need to handle payload registers.
5988 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5989 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
5990 inst
->size_read(i
) > REG_SIZE
) {
5991 max_width
= MIN2(max_width
, 8);
5996 /* From the IVB PRMs:
5997 * "When an instruction is SIMD32, the low 16 bits of the execution mask
5998 * are applied for both halves of the SIMD32 instruction. If different
5999 * execution mask channels are required, split the instruction into two
6000 * SIMD16 instructions."
6002 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6003 * 32-wide control flow support in hardware and will behave similarly.
6005 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6006 max_width
= MIN2(max_width
, 16);
6008 /* From the IVB PRMs (applies to HSW too):
6009 * "Instructions with condition modifiers must not use SIMD32."
6011 * From the BDW PRMs (applies to later hardware too):
6012 * "Ternary instruction with condition modifiers must not use SIMD32."
6014 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6015 max_width
= MIN2(max_width
, 16);
6017 /* From the IVB PRMs (applies to other devices that don't have the
6018 * gen_device_info::supports_simd16_3src flag set):
6019 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6020 * SIMD8 is not allowed for DF operations."
6022 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6023 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6025 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6026 * the 8-bit quarter of the execution mask signals specified in the
6027 * instruction control fields) for the second compressed half of any
6028 * single-precision instruction (for double-precision instructions
6029 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6030 * the EU will apply the wrong execution controls for the second
6031 * sequential GRF write if the number of channels per GRF is not exactly
6032 * eight in single-precision mode (or four in double-float mode).
6034 * In this situation we calculate the maximum size of the split
6035 * instructions so they only ever write to a single register.
6037 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6038 !inst
->force_writemask_all
) {
6039 const unsigned channels_per_grf
= inst
->exec_size
/
6040 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6041 const unsigned exec_type_size
= get_exec_type_size(inst
);
6042 assert(exec_type_size
);
6044 /* The hardware shifts exactly 8 channels per compressed half of the
6045 * instruction in single-precision mode and exactly 4 in double-precision.
6047 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6048 max_width
= MIN2(max_width
, channels_per_grf
);
6050 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6051 * because HW applies the same channel enable signals to both halves of
6052 * the compressed instruction which will be just wrong under
6053 * non-uniform control flow.
6055 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6056 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6057 max_width
= MIN2(max_width
, 4);
6060 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6063 * "No SIMD16 in mixed mode when destination is f32. Instruction
6064 * execution size must be no more than 8."
6066 * FIXME: the simulator doesn't seem to complain if we don't do this and
6067 * empirical testing with existing CTS tests show that they pass just fine
6068 * without implementing this, however, since our interpretation of the PRM
6069 * is that conversion MOVs between HF and F are still mixed-float
6070 * instructions (and therefore subject to this restriction) we decided to
6071 * split them to be safe. Might be useful to do additional investigation to
6072 * lift the restriction if we can ensure that it is safe though, since these
6073 * conversions are common when half-float types are involved since many
6074 * instructions do not support HF types and conversions from/to F are
6077 if (is_mixed_float_with_fp32_dst(inst
))
6078 max_width
= MIN2(max_width
, 8);
6080 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6083 * "No SIMD16 in mixed mode when destination is packed f16 for both
6084 * Align1 and Align16."
6086 if (is_mixed_float_with_packed_fp16_dst(inst
))
6087 max_width
= MIN2(max_width
, 8);
6089 /* Only power-of-two execution sizes are representable in the instruction
6092 return 1 << _mesa_logbase2(max_width
);
6096 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6097 * various payload size restrictions that apply to sampler message
6100 * This is only intended to provide a maximum theoretical bound for the
6101 * execution size of the message based on the number of argument components
6102 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6103 * variant of the message can be used, though some messages may have
6104 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6105 * the message length to determine the exact SIMD width and argument count,
6106 * which makes a number of sampler message combinations impossible to
6110 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6111 const fs_inst
*inst
)
6113 /* If we have a min_lod parameter on anything other than a simple sample
6114 * message, it will push it over 5 arguments and we have to fall back to
6117 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6118 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6121 /* Calculate the number of coordinate components that have to be present
6122 * assuming that additional arguments follow the texel coordinates in the
6123 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6124 * need to pad to four or three components depending on the message,
6125 * pre-ILK we need to pad to at most three components.
6127 const unsigned req_coord_components
=
6128 (devinfo
->gen
>= 7 ||
6129 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6130 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6131 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6134 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6135 * variant of the TXL or TXF message.
6137 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6138 (inst
->opcode
== SHADER_OPCODE_TXL
||
6139 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6140 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6142 /* Calculate the total number of argument components that need to be passed
6143 * to the sampler unit.
6145 const unsigned num_payload_components
=
6146 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6147 req_coord_components
) +
6148 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6149 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6150 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6151 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6152 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6153 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6154 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6156 /* SIMD16 messages with more than five arguments exceed the maximum message
6157 * size supported by the sampler, regardless of whether a header is
6160 return MIN2(inst
->exec_size
,
6161 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6165 * Get the closest native SIMD width supported by the hardware for instruction
6166 * \p inst. The instruction will be left untouched by
6167 * fs_visitor::lower_simd_width() if the returned value is equal to the
6168 * original execution size.
6171 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6172 const fs_inst
*inst
)
6174 switch (inst
->opcode
) {
6175 case BRW_OPCODE_MOV
:
6176 case BRW_OPCODE_SEL
:
6177 case BRW_OPCODE_NOT
:
6178 case BRW_OPCODE_AND
:
6180 case BRW_OPCODE_XOR
:
6181 case BRW_OPCODE_SHR
:
6182 case BRW_OPCODE_SHL
:
6183 case BRW_OPCODE_ASR
:
6184 case BRW_OPCODE_ROR
:
6185 case BRW_OPCODE_ROL
:
6186 case BRW_OPCODE_CMPN
:
6187 case BRW_OPCODE_CSEL
:
6188 case BRW_OPCODE_F32TO16
:
6189 case BRW_OPCODE_F16TO32
:
6190 case BRW_OPCODE_BFREV
:
6191 case BRW_OPCODE_BFE
:
6192 case BRW_OPCODE_ADD
:
6193 case BRW_OPCODE_MUL
:
6194 case BRW_OPCODE_AVG
:
6195 case BRW_OPCODE_FRC
:
6196 case BRW_OPCODE_RNDU
:
6197 case BRW_OPCODE_RNDD
:
6198 case BRW_OPCODE_RNDE
:
6199 case BRW_OPCODE_RNDZ
:
6200 case BRW_OPCODE_LZD
:
6201 case BRW_OPCODE_FBH
:
6202 case BRW_OPCODE_FBL
:
6203 case BRW_OPCODE_CBIT
:
6204 case BRW_OPCODE_SAD2
:
6205 case BRW_OPCODE_MAD
:
6206 case BRW_OPCODE_LRP
:
6207 case FS_OPCODE_PACK
:
6208 case SHADER_OPCODE_SEL_EXEC
:
6209 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6210 return get_fpu_lowered_simd_width(devinfo
, inst
);
6212 case BRW_OPCODE_CMP
: {
6213 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6214 * when the destination is a GRF the dependency-clear bit on the flag
6215 * register is cleared early.
6217 * Suggested workarounds are to disable coissuing CMP instructions
6218 * or to split CMP(16) instructions into two CMP(8) instructions.
6220 * We choose to split into CMP(8) instructions since disabling
6221 * coissuing would affect CMP instructions not otherwise affected by
6224 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6225 !inst
->dst
.is_null() ? 8 : ~0);
6226 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6228 case BRW_OPCODE_BFI1
:
6229 case BRW_OPCODE_BFI2
:
6230 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6232 * "Force BFI instructions to be executed always in SIMD8."
6234 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6235 get_fpu_lowered_simd_width(devinfo
, inst
));
6238 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6239 return inst
->exec_size
;
6241 case SHADER_OPCODE_RCP
:
6242 case SHADER_OPCODE_RSQ
:
6243 case SHADER_OPCODE_SQRT
:
6244 case SHADER_OPCODE_EXP2
:
6245 case SHADER_OPCODE_LOG2
:
6246 case SHADER_OPCODE_SIN
:
6247 case SHADER_OPCODE_COS
: {
6248 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6249 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6251 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6252 return MIN2(8, inst
->exec_size
);
6253 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6254 return MIN2(8, inst
->exec_size
);
6255 return MIN2(16, inst
->exec_size
);
6258 case SHADER_OPCODE_POW
: {
6259 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6260 * to SIMD8 with half-float
6262 if (devinfo
->gen
< 7)
6263 return MIN2(8, inst
->exec_size
);
6264 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6265 return MIN2(8, inst
->exec_size
);
6266 return MIN2(16, inst
->exec_size
);
6269 case SHADER_OPCODE_INT_QUOTIENT
:
6270 case SHADER_OPCODE_INT_REMAINDER
:
6271 /* Integer division is limited to SIMD8 on all generations. */
6272 return MIN2(8, inst
->exec_size
);
6274 case FS_OPCODE_LINTERP
:
6275 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6276 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6277 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6278 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6279 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6280 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6281 return MIN2(16, inst
->exec_size
);
6283 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6284 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6285 * message used to implement varying pull constant loads, so expand it
6286 * to SIMD16. An alternative with longer message payload length but
6287 * shorter return payload would be to use the SIMD8 sampler message that
6288 * takes (header, u, v, r) as parameters instead of (header, u).
6290 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6292 case FS_OPCODE_DDX_COARSE
:
6293 case FS_OPCODE_DDX_FINE
:
6294 case FS_OPCODE_DDY_COARSE
:
6295 case FS_OPCODE_DDY_FINE
:
6296 /* The implementation of this virtual opcode may require emitting
6297 * compressed Align16 instructions, which are severely limited on some
6300 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6301 * Region Restrictions):
6303 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6304 * and SIMD8 is not allowed for DF operations."
6306 * In this context, "DW operations" means "operations acting on 32-bit
6307 * values", so it includes operations on floats.
6309 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6310 * (Instruction Compression -> Rules and Restrictions):
6312 * "A compressed instruction must be in Align1 access mode. Align16
6313 * mode instructions cannot be compressed."
6315 * Similar text exists in the g45 PRM.
6317 * Empirically, compressed align16 instructions using odd register
6318 * numbers don't appear to work on Sandybridge either.
6320 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6321 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6322 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6324 case SHADER_OPCODE_MULH
:
6325 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6326 * is 8-wide on Gen7+.
6328 return (devinfo
->gen
>= 7 ? 8 :
6329 get_fpu_lowered_simd_width(devinfo
, inst
));
6331 case FS_OPCODE_FB_WRITE_LOGICAL
:
6332 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6335 assert(devinfo
->gen
!= 6 ||
6336 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6337 inst
->exec_size
== 8);
6338 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6339 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6340 8 : MIN2(16, inst
->exec_size
));
6342 case FS_OPCODE_FB_READ_LOGICAL
:
6343 return MIN2(16, inst
->exec_size
);
6345 case SHADER_OPCODE_TEX_LOGICAL
:
6346 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6347 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6348 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6349 case SHADER_OPCODE_LOD_LOGICAL
:
6350 case SHADER_OPCODE_TG4_LOGICAL
:
6351 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6352 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6353 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6354 return get_sampler_lowered_simd_width(devinfo
, inst
);
6356 case SHADER_OPCODE_TXD_LOGICAL
:
6357 /* TXD is unsupported in SIMD16 mode. */
6360 case SHADER_OPCODE_TXL_LOGICAL
:
6361 case FS_OPCODE_TXB_LOGICAL
:
6362 /* Only one execution size is representable pre-ILK depending on whether
6363 * the shadow reference argument is present.
6365 if (devinfo
->gen
== 4)
6366 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6368 return get_sampler_lowered_simd_width(devinfo
, inst
);
6370 case SHADER_OPCODE_TXF_LOGICAL
:
6371 case SHADER_OPCODE_TXS_LOGICAL
:
6372 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6373 * messages. Use SIMD16 instead.
6375 if (devinfo
->gen
== 4)
6378 return get_sampler_lowered_simd_width(devinfo
, inst
);
6380 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6381 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6382 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6385 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6386 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6387 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6388 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6389 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6390 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6391 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6392 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6393 return MIN2(16, inst
->exec_size
);
6395 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6396 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6397 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6398 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6399 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6401 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6402 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6403 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6406 case SHADER_OPCODE_URB_READ_SIMD8
:
6407 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6408 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6409 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6410 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6411 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6412 return MIN2(8, inst
->exec_size
);
6414 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6415 const unsigned swiz
= inst
->src
[1].ud
;
6416 return (is_uniform(inst
->src
[0]) ?
6417 get_fpu_lowered_simd_width(devinfo
, inst
) :
6418 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6419 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6420 get_fpu_lowered_simd_width(devinfo
, inst
));
6422 case SHADER_OPCODE_MOV_INDIRECT
: {
6423 /* From IVB and HSW PRMs:
6425 * "2.When the destination requires two registers and the sources are
6426 * indirect, the sources must use 1x1 regioning mode.
6428 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6429 * the EU decompression logic not handling VxH indirect addressing
6432 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6433 /* Prior to Broadwell, we only have 8 address subregisters. */
6434 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6435 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6439 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6440 const unsigned reg_count
=
6441 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6443 if (reg_count
> 2) {
6444 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6445 * can be easily lowered (which excludes headers and heterogeneous
6448 assert(!inst
->header_size
);
6449 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6450 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6451 inst
->src
[i
].file
== BAD_FILE
);
6453 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6455 return inst
->exec_size
;
6459 return inst
->exec_size
;
6464 * Return true if splitting out the group of channels of instruction \p inst
6465 * given by lbld.group() requires allocating a temporary for the i-th source
6466 * of the lowered instruction.
6469 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6471 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6472 (inst
->components_read(i
) == 1 &&
6473 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6474 (inst
->flags_written() &
6475 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6479 * Extract the data that would be consumed by the channel group given by
6480 * lbld.group() from the i-th source region of instruction \p inst and return
6481 * it as result in packed form.
6484 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6486 assert(lbld
.group() >= inst
->group
);
6488 /* Specified channel group from the source region. */
6489 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6491 if (needs_src_copy(lbld
, inst
, i
)) {
6492 /* Builder of the right width to perform the copy avoiding uninitialized
6493 * data if the lowered execution size is greater than the original
6494 * execution size of the instruction.
6496 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6497 inst
->exec_size
), 0);
6498 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6500 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6501 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6505 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6506 /* The source is invariant for all dispatch_width-wide groups of the
6509 return inst
->src
[i
];
6512 /* We can just point the lowered instruction at the right channel group
6513 * from the original region.
6520 * Return true if splitting out the group of channels of instruction \p inst
6521 * given by lbld.group() requires allocating a temporary for the destination
6522 * of the lowered instruction and copying the data back to the original
6523 * destination region.
6526 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6528 /* If the instruction writes more than one component we'll have to shuffle
6529 * the results of multiple lowered instructions in order to make sure that
6530 * they end up arranged correctly in the original destination region.
6532 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6535 /* If the lowered execution size is larger than the original the result of
6536 * the instruction won't fit in the original destination, so we'll have to
6537 * allocate a temporary in any case.
6539 if (lbld
.dispatch_width() > inst
->exec_size
)
6542 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6543 /* If we already made a copy of the source for other reasons there won't
6544 * be any overlap with the destination.
6546 if (needs_src_copy(lbld
, inst
, i
))
6549 /* In order to keep the logic simple we emit a copy whenever the
6550 * destination region doesn't exactly match an overlapping source, which
6551 * may point at the source and destination not being aligned group by
6552 * group which could cause one of the lowered instructions to overwrite
6553 * the data read from the same source by other lowered instructions.
6555 if (regions_overlap(inst
->dst
, inst
->size_written
,
6556 inst
->src
[i
], inst
->size_read(i
)) &&
6557 !inst
->dst
.equals(inst
->src
[i
]))
6565 * Insert data from a packed temporary into the channel group given by
6566 * lbld.group() of the destination region of instruction \p inst and return
6567 * the temporary as result. Any copy instructions that are required for
6568 * unzipping the previous value (in the case of partial writes) will be
6569 * inserted using \p lbld_before and any copy instructions required for
6570 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6573 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6576 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6577 assert(lbld_before
.group() == lbld_after
.group());
6578 assert(lbld_after
.group() >= inst
->group
);
6580 /* Specified channel group from the destination region. */
6581 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6582 const unsigned dst_size
= inst
->size_written
/
6583 inst
->dst
.component_size(inst
->exec_size
);
6585 if (needs_dst_copy(lbld_after
, inst
)) {
6586 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6588 if (inst
->predicate
) {
6589 /* Handle predication by copying the original contents of
6590 * the destination into the temporary before emitting the
6591 * lowered instruction.
6593 const fs_builder gbld_before
=
6594 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6595 inst
->exec_size
), 0);
6596 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6597 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6598 offset(dst
, inst
->exec_size
, k
));
6602 const fs_builder gbld_after
=
6603 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6604 inst
->exec_size
), 0);
6605 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6606 /* Use a builder of the right width to perform the copy avoiding
6607 * uninitialized data if the lowered execution size is greater than
6608 * the original execution size of the instruction.
6610 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6611 offset(tmp
, lbld_after
, k
));
6617 /* No need to allocate a temporary for the lowered instruction, just
6618 * take the right group of channels from the original region.
6625 fs_visitor::lower_simd_width()
6627 bool progress
= false;
6629 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6630 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6632 if (lower_width
!= inst
->exec_size
) {
6633 /* Builder matching the original instruction. We may also need to
6634 * emit an instruction of width larger than the original, set the
6635 * execution size of the builder to the highest of both for now so
6636 * we're sure that both cases can be handled.
6638 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6639 const fs_builder ibld
= bld
.at(block
, inst
)
6640 .exec_all(inst
->force_writemask_all
)
6641 .group(max_width
, inst
->group
/ max_width
);
6643 /* Split the copies in chunks of the execution width of either the
6644 * original or the lowered instruction, whichever is lower.
6646 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6647 const unsigned dst_size
= inst
->size_written
/
6648 inst
->dst
.component_size(inst
->exec_size
);
6650 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6652 /* Inserting the zip, unzip, and duplicated instructions in all of
6653 * the right spots is somewhat tricky. All of the unzip and any
6654 * instructions from the zip which unzip the destination prior to
6655 * writing need to happen before all of the per-group instructions
6656 * and the zip instructions need to happen after. In order to sort
6657 * this all out, we insert the unzip instructions before \p inst,
6658 * insert the per-group instructions after \p inst (i.e. before
6659 * inst->next), and insert the zip instructions before the
6660 * instruction after \p inst. Since we are inserting instructions
6661 * after \p inst, inst->next is a moving target and we need to save
6662 * it off here so that we insert the zip instructions in the right
6665 * Since we're inserting split instructions after after_inst, the
6666 * instructions will end up in the reverse order that we insert them.
6667 * However, certain render target writes require that the low group
6668 * instructions come before the high group. From the Ivy Bridge PRM
6669 * Vol. 4, Pt. 1, Section 3.9.11:
6671 * "If multiple SIMD8 Dual Source messages are delivered by the
6672 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6673 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6674 * Group Select setting."
6676 * And, from Section 3.9.11.1 of the same PRM:
6678 * "When SIMD32 or SIMD16 PS threads send render target writes
6679 * with multiple SIMD8 and SIMD16 messages, the following must
6682 * All the slots (as described above) must have a corresponding
6683 * render target write irrespective of the slot's validity. A slot
6684 * is considered valid when at least one sample is enabled. For
6685 * example, a SIMD16 PS thread must send two SIMD8 render target
6686 * writes to cover all the slots.
6688 * PS thread must send SIMD render target write messages with
6689 * increasing slot numbers. For example, SIMD16 thread has
6690 * Slot[15:0] and if two SIMD8 render target writes are used, the
6691 * first SIMD8 render target write must send Slot[7:0] and the
6692 * next one must send Slot[15:8]."
6694 * In order to make low group instructions come before high group
6695 * instructions (this is required for some render target writes), we
6696 * split from the highest group to lowest.
6698 exec_node
*const after_inst
= inst
->next
;
6699 for (int i
= n
- 1; i
>= 0; i
--) {
6700 /* Emit a copy of the original instruction with the lowered width.
6701 * If the EOT flag was set throw it away except for the last
6702 * instruction to avoid killing the thread prematurely.
6704 fs_inst split_inst
= *inst
;
6705 split_inst
.exec_size
= lower_width
;
6706 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6708 /* Select the correct channel enables for the i-th group, then
6709 * transform the sources and destination and emit the lowered
6712 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6714 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6715 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6717 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6718 lbld
.at(block
, after_inst
), inst
);
6719 split_inst
.size_written
=
6720 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6722 lbld
.at(block
, inst
->next
).emit(split_inst
);
6725 inst
->remove(block
);
6731 invalidate_live_intervals();
6737 * Transform barycentric vectors into the interleaved form expected by the PLN
6738 * instruction and returned by the Gen7+ PI shared function.
6740 * For channels 0-15 in SIMD16 mode they are expected to be laid out as
6741 * follows in the register file:
6748 * There is no need to handle SIMD32 here -- This is expected to be run after
6749 * SIMD lowering, since SIMD lowering relies on vectors having the standard
6753 fs_visitor::lower_barycentrics()
6755 const bool has_interleaved_layout
= devinfo
->has_pln
|| devinfo
->gen
>= 7;
6756 bool progress
= false;
6758 if (stage
!= MESA_SHADER_FRAGMENT
|| !has_interleaved_layout
)
6761 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6762 if (inst
->exec_size
< 16)
6765 const fs_builder
ibld(this, block
, inst
);
6766 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
6768 switch (inst
->opcode
) {
6769 case FS_OPCODE_LINTERP
: {
6770 assert(inst
->exec_size
== 16);
6771 const fs_reg tmp
= ibld
.vgrf(inst
->src
[0].type
, 2);
6774 for (unsigned i
= 0; i
< ARRAY_SIZE(srcs
); i
++)
6775 srcs
[i
] = horiz_offset(offset(inst
->src
[0], ibld
, i
% 2),
6778 ubld
.LOAD_PAYLOAD(tmp
, srcs
, ARRAY_SIZE(srcs
), ARRAY_SIZE(srcs
));
6784 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6785 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6786 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
: {
6787 assert(inst
->exec_size
== 16);
6788 const fs_reg tmp
= ibld
.vgrf(inst
->dst
.type
, 2);
6790 for (unsigned i
= 0; i
< 2; i
++) {
6791 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
6792 fs_inst
*mov
= ibld
.at(block
, inst
->next
).group(8, g
)
6793 .MOV(horiz_offset(offset(inst
->dst
, ibld
, i
),
6795 offset(tmp
, ubld
, 2 * g
+ i
));
6796 mov
->predicate
= inst
->predicate
;
6797 mov
->predicate_inverse
= inst
->predicate_inverse
;
6798 mov
->flag_subreg
= inst
->flag_subreg
;
6812 invalidate_live_intervals();
6818 fs_visitor::dump_instructions()
6820 dump_instructions(NULL
);
6824 fs_visitor::dump_instructions(const char *name
)
6826 FILE *file
= stderr
;
6827 if (name
&& geteuid() != 0) {
6828 file
= fopen(name
, "w");
6834 calculate_register_pressure();
6835 int ip
= 0, max_pressure
= 0;
6836 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
6837 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
6838 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
6839 dump_instruction(inst
, file
);
6842 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
6845 foreach_in_list(backend_instruction
, inst
, &instructions
) {
6846 fprintf(file
, "%4d: ", ip
++);
6847 dump_instruction(inst
, file
);
6851 if (file
!= stderr
) {
6857 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
6859 dump_instruction(be_inst
, stderr
);
6863 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
6865 fs_inst
*inst
= (fs_inst
*)be_inst
;
6867 if (inst
->predicate
) {
6868 fprintf(file
, "(%cf%d.%d) ",
6869 inst
->predicate_inverse
? '-' : '+',
6870 inst
->flag_subreg
/ 2,
6871 inst
->flag_subreg
% 2);
6874 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
6876 fprintf(file
, ".sat");
6877 if (inst
->conditional_mod
) {
6878 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
6879 if (!inst
->predicate
&&
6880 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
6881 inst
->opcode
!= BRW_OPCODE_CSEL
&&
6882 inst
->opcode
!= BRW_OPCODE_IF
&&
6883 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
6884 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
6885 inst
->flag_subreg
% 2);
6888 fprintf(file
, "(%d) ", inst
->exec_size
);
6891 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
6894 if (inst
->ex_mlen
) {
6895 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
6899 fprintf(file
, "(EOT) ");
6902 switch (inst
->dst
.file
) {
6904 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
6907 fprintf(file
, "g%d", inst
->dst
.nr
);
6910 fprintf(file
, "m%d", inst
->dst
.nr
);
6913 fprintf(file
, "(null)");
6916 fprintf(file
, "***u%d***", inst
->dst
.nr
);
6919 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
6922 switch (inst
->dst
.nr
) {
6924 fprintf(file
, "null");
6926 case BRW_ARF_ADDRESS
:
6927 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
6929 case BRW_ARF_ACCUMULATOR
:
6930 fprintf(file
, "acc%d", inst
->dst
.subnr
);
6933 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6936 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
6941 unreachable("not reached");
6944 if (inst
->dst
.offset
||
6945 (inst
->dst
.file
== VGRF
&&
6946 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
6947 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
6948 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
6949 inst
->dst
.offset
% reg_size
);
6952 if (inst
->dst
.stride
!= 1)
6953 fprintf(file
, "<%u>", inst
->dst
.stride
);
6954 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
6956 for (int i
= 0; i
< inst
->sources
; i
++) {
6957 if (inst
->src
[i
].negate
)
6959 if (inst
->src
[i
].abs
)
6961 switch (inst
->src
[i
].file
) {
6963 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
6966 fprintf(file
, "g%d", inst
->src
[i
].nr
);
6969 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
6972 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
6975 fprintf(file
, "u%d", inst
->src
[i
].nr
);
6978 fprintf(file
, "(null)");
6981 switch (inst
->src
[i
].type
) {
6982 case BRW_REGISTER_TYPE_F
:
6983 fprintf(file
, "%-gf", inst
->src
[i
].f
);
6985 case BRW_REGISTER_TYPE_DF
:
6986 fprintf(file
, "%fdf", inst
->src
[i
].df
);
6988 case BRW_REGISTER_TYPE_W
:
6989 case BRW_REGISTER_TYPE_D
:
6990 fprintf(file
, "%dd", inst
->src
[i
].d
);
6992 case BRW_REGISTER_TYPE_UW
:
6993 case BRW_REGISTER_TYPE_UD
:
6994 fprintf(file
, "%uu", inst
->src
[i
].ud
);
6996 case BRW_REGISTER_TYPE_Q
:
6997 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
6999 case BRW_REGISTER_TYPE_UQ
:
7000 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
7002 case BRW_REGISTER_TYPE_VF
:
7003 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
7004 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
7005 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
7006 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
7007 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
7009 case BRW_REGISTER_TYPE_V
:
7010 case BRW_REGISTER_TYPE_UV
:
7011 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
7012 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
7015 fprintf(file
, "???");
7020 switch (inst
->src
[i
].nr
) {
7022 fprintf(file
, "null");
7024 case BRW_ARF_ADDRESS
:
7025 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
7027 case BRW_ARF_ACCUMULATOR
:
7028 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7031 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7034 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7040 if (inst
->src
[i
].offset
||
7041 (inst
->src
[i
].file
== VGRF
&&
7042 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7043 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7044 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7045 inst
->src
[i
].offset
% reg_size
);
7048 if (inst
->src
[i
].abs
)
7051 if (inst
->src
[i
].file
!= IMM
) {
7053 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7054 unsigned hstride
= inst
->src
[i
].hstride
;
7055 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7057 stride
= inst
->src
[i
].stride
;
7060 fprintf(file
, "<%u>", stride
);
7062 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7065 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7066 fprintf(file
, ", ");
7071 if (inst
->force_writemask_all
)
7072 fprintf(file
, "NoMask ");
7074 if (inst
->exec_size
!= dispatch_width
)
7075 fprintf(file
, "group%d ", inst
->group
);
7077 fprintf(file
, "\n");
7081 fs_visitor::setup_fs_payload_gen6()
7083 assert(stage
== MESA_SHADER_FRAGMENT
);
7084 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7085 const unsigned payload_width
= MIN2(16, dispatch_width
);
7086 assert(dispatch_width
% payload_width
== 0);
7087 assert(devinfo
->gen
>= 6);
7089 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7090 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7092 prog_data
->uses_sample_mask
=
7093 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7095 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7097 * "MSDISPMODE_PERSAMPLE is required in order to select
7100 * So we can only really get sample positions if we are doing real
7101 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7102 * persample dispatch, we hard-code it to 0.5.
7104 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7105 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7107 /* R0: PS thread payload header. */
7110 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7111 /* R1: masks, pixel X/Y coordinates. */
7112 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7115 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7116 /* R3-26: barycentric interpolation coordinates. These appear in the
7117 * same order that they appear in the brw_barycentric_mode enum. Each
7118 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7119 * registers if dispatch width == 16. Coordinates only appear if they
7120 * were enabled using the "Barycentric Interpolation Mode" bits in
7123 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7124 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7125 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7126 payload
.num_regs
+= payload_width
/ 4;
7130 /* R27-28: interpolated depth if uses source depth */
7131 if (prog_data
->uses_src_depth
) {
7132 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7133 payload
.num_regs
+= payload_width
/ 8;
7136 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7137 if (prog_data
->uses_src_w
) {
7138 payload
.source_w_reg
[j
] = payload
.num_regs
;
7139 payload
.num_regs
+= payload_width
/ 8;
7142 /* R31: MSAA position offsets. */
7143 if (prog_data
->uses_pos_offset
) {
7144 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7148 /* R32-33: MSAA input coverage mask */
7149 if (prog_data
->uses_sample_mask
) {
7150 assert(devinfo
->gen
>= 7);
7151 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7152 payload
.num_regs
+= payload_width
/ 8;
7156 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7157 source_depth_to_render_target
= true;
7162 fs_visitor::setup_vs_payload()
7164 /* R0: thread header, R1: urb handles */
7165 payload
.num_regs
= 2;
7169 fs_visitor::setup_gs_payload()
7171 assert(stage
== MESA_SHADER_GEOMETRY
);
7173 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7174 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7176 /* R0: thread header, R1: output URB handles */
7177 payload
.num_regs
= 2;
7179 if (gs_prog_data
->include_primitive_id
) {
7180 /* R2: Primitive ID 0..7 */
7184 /* Always enable VUE handles so we can safely use pull model if needed.
7186 * The push model for a GS uses a ton of register space even for trivial
7187 * scenarios with just a few inputs, so just make things easier and a bit
7188 * safer by always having pull model available.
7190 gs_prog_data
->base
.include_vue_handles
= true;
7192 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7193 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7195 /* Use a maximum of 24 registers for push-model inputs. */
7196 const unsigned max_push_components
= 24;
7198 /* If pushing our inputs would take too many registers, reduce the URB read
7199 * length (which is in HWords, or 8 registers), and resort to pulling.
7201 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7202 * have to multiply by VerticesIn to obtain the total storage requirement.
7204 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7205 max_push_components
) {
7206 vue_prog_data
->urb_read_length
=
7207 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7212 fs_visitor::setup_cs_payload()
7214 assert(devinfo
->gen
>= 7);
7215 payload
.num_regs
= 1;
7219 fs_visitor::calculate_register_pressure()
7221 invalidate_live_intervals();
7222 calculate_live_intervals();
7224 unsigned num_instructions
= 0;
7225 foreach_block(block
, cfg
)
7226 num_instructions
+= block
->instructions
.length();
7228 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
7230 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
7231 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
7232 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
7237 fs_visitor::optimize()
7239 /* Start by validating the shader we currently have. */
7242 /* bld is the common builder object pointing at the end of the program we
7243 * used to translate it into i965 IR. For the optimization and lowering
7244 * passes coming next, any code added after the end of the program without
7245 * having explicitly called fs_builder::at() clearly points at a mistake.
7246 * Ideally optimization passes wouldn't be part of the visitor so they
7247 * wouldn't have access to bld at all, but they do, so just in case some
7248 * pass forgets to ask for a location explicitly set it to NULL here to
7249 * make it trip. The dispatch width is initialized to a bogus value to
7250 * make sure that optimizations set the execution controls explicitly to
7251 * match the code they are manipulating instead of relying on the defaults.
7253 bld
= fs_builder(this, 64);
7255 assign_constant_locations();
7256 lower_constant_loads();
7260 split_virtual_grfs();
7263 #define OPT(pass, args...) ({ \
7265 bool this_progress = pass(args); \
7267 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7268 char filename[64]; \
7269 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7270 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7272 backend_shader::dump_instructions(filename); \
7277 progress = progress || this_progress; \
7281 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7283 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7284 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7286 backend_shader::dump_instructions(filename
);
7289 bool progress
= false;
7293 /* Before anything else, eliminate dead code. The results of some NIR
7294 * instructions may effectively be calculated twice. Once when the
7295 * instruction is encountered, and again when the user of that result is
7296 * encountered. Wipe those away before algebraic optimizations and
7297 * especially copy propagation can mix things up.
7299 OPT(dead_code_eliminate
);
7301 OPT(remove_extra_rounding_modes
);
7308 OPT(remove_duplicate_mrf_writes
);
7312 OPT(opt_copy_propagation
);
7313 OPT(opt_predicated_break
, this);
7314 OPT(opt_cmod_propagation
);
7315 OPT(dead_code_eliminate
);
7316 OPT(opt_peephole_sel
);
7317 OPT(dead_control_flow_eliminate
, this);
7318 OPT(opt_register_renaming
);
7319 OPT(opt_saturate_propagation
);
7320 OPT(register_coalesce
);
7321 OPT(compute_to_mrf
);
7322 OPT(eliminate_find_live_channel
);
7324 OPT(compact_virtual_grfs
);
7330 if (OPT(lower_pack
)) {
7331 OPT(register_coalesce
);
7332 OPT(dead_code_eliminate
);
7335 OPT(lower_simd_width
);
7336 OPT(lower_barycentrics
);
7338 /* After SIMD lowering just in case we had to unroll the EOT send. */
7339 OPT(opt_sampler_eot
);
7341 OPT(lower_logical_sends
);
7344 OPT(opt_copy_propagation
);
7345 /* Only run after logical send lowering because it's easier to implement
7346 * in terms of physical sends.
7348 if (OPT(opt_zero_samples
))
7349 OPT(opt_copy_propagation
);
7350 /* Run after logical send lowering to give it a chance to CSE the
7351 * LOAD_PAYLOAD instructions created to construct the payloads of
7352 * e.g. texturing messages in cases where it wasn't possible to CSE the
7353 * whole logical instruction.
7356 OPT(register_coalesce
);
7357 OPT(compute_to_mrf
);
7358 OPT(dead_code_eliminate
);
7359 OPT(remove_duplicate_mrf_writes
);
7360 OPT(opt_peephole_sel
);
7363 OPT(opt_redundant_discard_jumps
);
7365 if (OPT(lower_load_payload
)) {
7366 split_virtual_grfs();
7368 /* Lower 64 bit MOVs generated by payload lowering. */
7369 if (!devinfo
->has_64bit_types
)
7372 OPT(register_coalesce
);
7373 OPT(lower_simd_width
);
7374 OPT(compute_to_mrf
);
7375 OPT(dead_code_eliminate
);
7378 OPT(opt_combine_constants
);
7379 OPT(lower_integer_multiplication
);
7381 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7382 OPT(opt_cmod_propagation
);
7384 OPT(opt_copy_propagation
);
7385 OPT(dead_code_eliminate
);
7388 if (OPT(lower_regioning
)) {
7389 OPT(opt_copy_propagation
);
7390 OPT(dead_code_eliminate
);
7391 OPT(lower_simd_width
);
7394 OPT(fixup_sends_duplicate_payload
);
7396 lower_uniform_pull_constant_loads();
7402 * From the Skylake PRM Vol. 2a docs for sends:
7404 * "It is required that the second block of GRFs does not overlap with the
7407 * There are plenty of cases where we may accidentally violate this due to
7408 * having, for instance, both sources be the constant 0. This little pass
7409 * just adds a new vgrf for the second payload and copies it over.
7412 fs_visitor::fixup_sends_duplicate_payload()
7414 bool progress
= false;
7416 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7417 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7418 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7419 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7420 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7421 BRW_REGISTER_TYPE_UD
);
7422 /* Sadly, we've lost all notion of channels and bit sizes at this
7423 * point. Just WE_all it.
7425 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7426 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7427 fs_reg copy_dst
= tmp
;
7428 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7429 if (inst
->ex_mlen
== i
+ 1) {
7430 /* Only one register left; do SIMD8 */
7431 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7433 ibld
.MOV(copy_dst
, copy_src
);
7435 copy_src
= offset(copy_src
, ibld
, 1);
7436 copy_dst
= offset(copy_dst
, ibld
, 1);
7444 invalidate_live_intervals();
7450 * Three source instruction must have a GRF/MRF destination register.
7451 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7454 fs_visitor::fixup_3src_null_dest()
7456 bool progress
= false;
7458 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7459 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7460 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7467 invalidate_live_intervals();
7471 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
7475 static const enum instruction_scheduler_mode pre_modes
[] = {
7477 SCHEDULE_PRE_NON_LIFO
,
7481 static const char *scheduler_mode_name
[] = {
7487 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7489 /* Try each scheduling heuristic to see if it can successfully register
7490 * allocate without spilling. They should be ordered by decreasing
7491 * performance but increasing likelihood of allocating.
7493 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7494 schedule_instructions(pre_modes
[i
]);
7495 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7498 assign_regs_trivial();
7503 /* We only allow spilling for the last schedule mode and only if the
7504 * allow_spilling parameter and dispatch width work out ok.
7506 bool can_spill
= allow_spilling
&&
7507 (i
== ARRAY_SIZE(pre_modes
) - 1) &&
7508 dispatch_width
== min_dispatch_width
;
7510 /* We should only spill registers on the last scheduling. */
7511 assert(!spilled_any_registers
);
7513 allocated
= assign_regs(can_spill
, spill_all
);
7519 if (!allow_spilling
)
7520 fail("Failure to register allocate and spilling is not allowed.");
7522 /* We assume that any spilling is worse than just dropping back to
7523 * SIMD8. There's probably actually some intermediate point where
7524 * SIMD16 with a couple of spills is still better.
7526 if (dispatch_width
> min_dispatch_width
) {
7527 fail("Failure to register allocate. Reduce number of "
7528 "live scalar values to avoid this.");
7531 /* If we failed to allocate, we must have a reason */
7533 } else if (spilled_any_registers
) {
7534 compiler
->shader_perf_log(log_data
,
7535 "%s shader triggered register spilling. "
7536 "Try reducing the number of live scalar "
7537 "values to improve performance.\n",
7541 /* This must come after all optimization and register allocation, since
7542 * it inserts dead code that happens to have side effects, and it does
7543 * so based on the actual physical registers in use.
7545 insert_gen4_send_dependency_workarounds();
7550 opt_bank_conflicts();
7552 schedule_instructions(SCHEDULE_POST
);
7554 if (last_scratch
> 0) {
7555 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7557 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7559 if (stage
== MESA_SHADER_COMPUTE
) {
7560 if (devinfo
->is_haswell
) {
7561 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7562 * field documentation, Haswell supports a minimum of 2kB of
7563 * scratch space for compute shaders, unlike every other stage
7566 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7567 } else if (devinfo
->gen
<= 7) {
7568 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7569 * field documentation, platforms prior to Haswell measure scratch
7570 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7572 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7573 max_scratch_size
= 12 * 1024;
7577 /* We currently only support up to 2MB of scratch space. If we
7578 * need to support more eventually, the documentation suggests
7579 * that we could allocate a larger buffer, and partition it out
7580 * ourselves. We'd just have to undo the hardware's address
7581 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7582 * and then add FFTID * (Larger Per Thread Scratch Space).
7584 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7585 * Thread Group Tracking > Local Memory/Scratch Space.
7587 assert(prog_data
->total_scratch
< max_scratch_size
);
7594 fs_visitor::run_vs()
7596 assert(stage
== MESA_SHADER_VERTEX
);
7600 if (shader_time_index
>= 0)
7601 emit_shader_time_begin();
7610 if (shader_time_index
>= 0)
7611 emit_shader_time_end();
7617 assign_curb_setup();
7618 assign_vs_urb_setup();
7620 fixup_3src_null_dest();
7621 allocate_registers(8, true);
7627 fs_visitor::set_tcs_invocation_id()
7629 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7630 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7632 const unsigned instance_id_mask
=
7633 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7634 const unsigned instance_id_shift
=
7635 devinfo
->gen
>= 11 ? 16 : 17;
7637 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7638 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7639 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7640 brw_imm_ud(instance_id_mask
));
7642 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7644 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7645 /* gl_InvocationID is just the thread number */
7646 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7650 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7652 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7653 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7654 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7655 bld
.MOV(channels_ud
, channels_uw
);
7657 if (tcs_prog_data
->instances
== 1) {
7658 invocation_id
= channels_ud
;
7660 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7661 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
7662 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
7667 fs_visitor::run_tcs()
7669 assert(stage
== MESA_SHADER_TESS_CTRL
);
7671 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7672 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7673 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
7675 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
7676 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7678 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
7679 /* r1-r4 contain the ICP handles. */
7680 payload
.num_regs
= 5;
7682 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7683 assert(tcs_key
->input_vertices
> 0);
7684 /* r1 contains output handles, r2 may contain primitive ID, then the
7685 * ICP handles occupy the next 1-32 registers.
7687 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
7688 tcs_key
->input_vertices
;
7691 if (shader_time_index
>= 0)
7692 emit_shader_time_begin();
7694 /* Initialize gl_InvocationID */
7695 set_tcs_invocation_id();
7697 const bool fix_dispatch_mask
=
7698 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
7699 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
7701 /* Fix the disptach mask */
7702 if (fix_dispatch_mask
) {
7703 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
7704 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
7705 bld
.IF(BRW_PREDICATE_NORMAL
);
7710 if (fix_dispatch_mask
) {
7711 bld
.emit(BRW_OPCODE_ENDIF
);
7714 /* Emit EOT write; set TR DS Cache bit */
7716 fs_reg(get_tcs_output_urb_handle()),
7717 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
7718 fs_reg(brw_imm_ud(0)),
7720 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
7721 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
7723 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
7724 bld
.null_reg_ud(), payload
);
7728 if (shader_time_index
>= 0)
7729 emit_shader_time_end();
7738 assign_curb_setup();
7739 assign_tcs_urb_setup();
7741 fixup_3src_null_dest();
7742 allocate_registers(8, true);
7748 fs_visitor::run_tes()
7750 assert(stage
== MESA_SHADER_TESS_EVAL
);
7752 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
7753 payload
.num_regs
= 5;
7755 if (shader_time_index
>= 0)
7756 emit_shader_time_begin();
7765 if (shader_time_index
>= 0)
7766 emit_shader_time_end();
7772 assign_curb_setup();
7773 assign_tes_urb_setup();
7775 fixup_3src_null_dest();
7776 allocate_registers(8, true);
7782 fs_visitor::run_gs()
7784 assert(stage
== MESA_SHADER_GEOMETRY
);
7788 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
7790 if (gs_compile
->control_data_header_size_bits
> 0) {
7791 /* Create a VGRF to store accumulated control data bits. */
7792 this->control_data_bits
= vgrf(glsl_type::uint_type
);
7794 /* If we're outputting more than 32 control data bits, then EmitVertex()
7795 * will set control_data_bits to 0 after emitting the first vertex.
7796 * Otherwise, we need to initialize it to 0 here.
7798 if (gs_compile
->control_data_header_size_bits
<= 32) {
7799 const fs_builder abld
= bld
.annotate("initialize control data bits");
7800 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
7804 if (shader_time_index
>= 0)
7805 emit_shader_time_begin();
7809 emit_gs_thread_end();
7811 if (shader_time_index
>= 0)
7812 emit_shader_time_end();
7821 assign_curb_setup();
7822 assign_gs_urb_setup();
7824 fixup_3src_null_dest();
7825 allocate_registers(8, true);
7830 /* From the SKL PRM, Volume 16, Workarounds:
7832 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
7833 * only header phases (R0-R2)
7835 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
7836 * have been header only.
7838 * Instead of enabling push constants one can alternatively enable one of the
7839 * inputs. Here one simply chooses "layer" which shouldn't impose much
7843 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
7845 if (wm_prog_data
->num_varying_inputs
)
7848 if (wm_prog_data
->base
.curb_read_length
)
7851 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
7852 wm_prog_data
->num_varying_inputs
= 1;
7856 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
7858 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
7859 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
7861 assert(stage
== MESA_SHADER_FRAGMENT
);
7863 if (devinfo
->gen
>= 6)
7864 setup_fs_payload_gen6();
7866 setup_fs_payload_gen4();
7870 } else if (do_rep_send
) {
7871 assert(dispatch_width
== 16);
7872 emit_repclear_shader();
7874 if (shader_time_index
>= 0)
7875 emit_shader_time_begin();
7877 if (nir
->info
.inputs_read
> 0 ||
7878 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
7879 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
7880 if (devinfo
->gen
< 6)
7881 emit_interpolation_setup_gen4();
7883 emit_interpolation_setup_gen6();
7886 /* We handle discards by keeping track of the still-live pixels in f0.1.
7887 * Initialize it with the dispatched pixels.
7889 if (wm_prog_data
->uses_kill
) {
7890 const fs_reg dispatch_mask
=
7891 devinfo
->gen
>= 6 ? brw_vec1_grf(1, 7) : brw_vec1_grf(0, 0);
7892 bld
.exec_all().group(1, 0)
7893 .MOV(retype(brw_flag_reg(0, 1), BRW_REGISTER_TYPE_UW
),
7894 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
7902 if (wm_prog_data
->uses_kill
)
7903 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
7905 if (wm_key
->alpha_test_func
)
7910 if (shader_time_index
>= 0)
7911 emit_shader_time_end();
7917 assign_curb_setup();
7919 if (devinfo
->gen
>= 9)
7920 gen9_ps_header_only_workaround(wm_prog_data
);
7924 fixup_3src_null_dest();
7925 allocate_registers(8, allow_spilling
);
7935 fs_visitor::run_cs(unsigned min_dispatch_width
)
7937 assert(stage
== MESA_SHADER_COMPUTE
);
7938 assert(dispatch_width
>= min_dispatch_width
);
7942 if (shader_time_index
>= 0)
7943 emit_shader_time_begin();
7945 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
7946 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
7947 const fs_builder abld
= bld
.exec_all().group(1, 0);
7948 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
7949 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
7957 emit_cs_terminate();
7959 if (shader_time_index
>= 0)
7960 emit_shader_time_end();
7966 assign_curb_setup();
7968 fixup_3src_null_dest();
7969 allocate_registers(min_dispatch_width
, true);
7978 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
7980 nir_foreach_use(src
, def
) {
7981 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
7984 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
7985 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
7989 nir_foreach_if_use(src
, def
)
7996 * Return a bitfield where bit n is set if barycentric interpolation mode n
7997 * (see enum brw_barycentric_mode) is needed by the fragment shader.
7999 * We examine the load_barycentric intrinsics rather than looking at input
8000 * variables so that we catch interpolateAtCentroid() messages too, which
8001 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
8004 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
8005 const nir_shader
*shader
)
8007 unsigned barycentric_interp_modes
= 0;
8009 nir_foreach_function(f
, shader
) {
8013 nir_foreach_block(block
, f
->impl
) {
8014 nir_foreach_instr(instr
, block
) {
8015 if (instr
->type
!= nir_instr_type_intrinsic
)
8018 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8019 switch (intrin
->intrinsic
) {
8020 case nir_intrinsic_load_barycentric_pixel
:
8021 case nir_intrinsic_load_barycentric_centroid
:
8022 case nir_intrinsic_load_barycentric_sample
:
8028 /* Ignore WPOS; it doesn't require interpolation. */
8029 assert(intrin
->dest
.is_ssa
);
8030 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8033 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8034 nir_intrinsic_interp_mode(intrin
);
8035 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8036 enum brw_barycentric_mode bary
=
8037 brw_barycentric_mode(interp
, bary_op
);
8039 barycentric_interp_modes
|= 1 << bary
;
8041 if (devinfo
->needs_unlit_centroid_workaround
&&
8042 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8043 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8048 return barycentric_interp_modes
;
8052 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8053 const nir_shader
*shader
)
8055 prog_data
->flat_inputs
= 0;
8057 nir_foreach_variable(var
, &shader
->inputs
) {
8058 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8059 for (unsigned s
= 0; s
< slots
; s
++) {
8060 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8062 if (input_index
< 0)
8066 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8067 prog_data
->flat_inputs
|= 1 << input_index
;
8073 computed_depth_mode(const nir_shader
*shader
)
8075 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8076 switch (shader
->info
.fs
.depth_layout
) {
8077 case FRAG_DEPTH_LAYOUT_NONE
:
8078 case FRAG_DEPTH_LAYOUT_ANY
:
8079 return BRW_PSCDEPTH_ON
;
8080 case FRAG_DEPTH_LAYOUT_GREATER
:
8081 return BRW_PSCDEPTH_ON_GE
;
8082 case FRAG_DEPTH_LAYOUT_LESS
:
8083 return BRW_PSCDEPTH_ON_LE
;
8084 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8085 return BRW_PSCDEPTH_OFF
;
8088 return BRW_PSCDEPTH_OFF
;
8092 * Move load_interpolated_input with simple (payload-based) barycentric modes
8093 * to the top of the program so we don't emit multiple PLNs for the same input.
8095 * This works around CSE not being able to handle non-dominating cases
8101 * interpolate the same exact input
8104 * This should be replaced by global value numbering someday.
8107 move_interpolation_to_top(nir_shader
*nir
)
8109 bool progress
= false;
8111 nir_foreach_function(f
, nir
) {
8115 nir_block
*top
= nir_start_block(f
->impl
);
8116 exec_node
*cursor_node
= NULL
;
8118 nir_foreach_block(block
, f
->impl
) {
8122 nir_foreach_instr_safe(instr
, block
) {
8123 if (instr
->type
!= nir_instr_type_intrinsic
)
8126 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8127 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8129 nir_intrinsic_instr
*bary_intrinsic
=
8130 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8131 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8133 /* Leave interpolateAtSample/Offset() where they are. */
8134 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8135 op
== nir_intrinsic_load_barycentric_at_offset
)
8138 nir_instr
*move
[3] = {
8139 &bary_intrinsic
->instr
,
8140 intrin
->src
[1].ssa
->parent_instr
,
8144 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8145 if (move
[i
]->block
!= top
) {
8146 move
[i
]->block
= top
;
8147 exec_node_remove(&move
[i
]->node
);
8149 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8151 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8153 cursor_node
= &move
[i
]->node
;
8159 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8160 ((unsigned) nir_metadata_block_index
|
8161 (unsigned) nir_metadata_dominance
));
8168 * Demote per-sample barycentric intrinsics to centroid.
8170 * Useful when rendering to a non-multisampled buffer.
8173 demote_sample_qualifiers(nir_shader
*nir
)
8175 bool progress
= true;
8177 nir_foreach_function(f
, nir
) {
8182 nir_builder_init(&b
, f
->impl
);
8184 nir_foreach_block(block
, f
->impl
) {
8185 nir_foreach_instr_safe(instr
, block
) {
8186 if (instr
->type
!= nir_instr_type_intrinsic
)
8189 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8190 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8191 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8194 b
.cursor
= nir_before_instr(instr
);
8195 nir_ssa_def
*centroid
=
8196 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8197 nir_intrinsic_interp_mode(intrin
));
8198 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8199 nir_src_for_ssa(centroid
));
8200 nir_instr_remove(instr
);
8205 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8206 ((unsigned) nir_metadata_block_index
|
8207 (unsigned) nir_metadata_dominance
));
8214 * Pre-gen6, the register file of the EUs was shared between threads,
8215 * and each thread used some subset allocated on a 16-register block
8216 * granularity. The unit states wanted these block counts.
8219 brw_register_blocks(int reg_count
)
8221 return ALIGN(reg_count
, 16) / 16 - 1;
8225 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8227 const struct brw_wm_prog_key
*key
,
8228 struct brw_wm_prog_data
*prog_data
,
8230 int shader_time_index8
, int shader_time_index16
,
8231 int shader_time_index32
, bool allow_spilling
,
8232 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8233 struct brw_compile_stats
*stats
,
8236 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8238 unsigned max_subgroup_size
= unlikely(INTEL_DEBUG
& DEBUG_DO32
) ? 32 : 16;
8240 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8241 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8242 brw_nir_lower_fs_outputs(shader
);
8244 if (devinfo
->gen
< 6)
8245 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8247 /* From the SKL PRM, Volume 7, "Alpha Coverage":
8248 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
8249 * hardware, regardless of the state setting for this feature."
8251 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
) {
8252 /* Run constant fold optimization in order to get the correct source
8253 * offset to determine render target 0 store instruction in
8254 * emit_alpha_to_coverage pass.
8256 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8257 NIR_PASS_V(shader
, brw_nir_lower_alpha_to_coverage
);
8260 if (!key
->multisample_fbo
)
8261 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8262 NIR_PASS_V(shader
, move_interpolation_to_top
);
8263 brw_postprocess_nir(shader
, compiler
, true);
8265 /* key->alpha_test_func means simulating alpha testing via discards,
8266 * so the shader definitely kills pixels.
8268 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8269 key
->alpha_test_func
;
8270 prog_data
->uses_omask
= key
->multisample_fbo
&&
8271 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8272 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8273 prog_data
->computed_stencil
=
8274 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8276 prog_data
->persample_dispatch
=
8277 key
->multisample_fbo
&&
8278 (key
->persample_interp
||
8279 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8280 SYSTEM_BIT_SAMPLE_POS
)) ||
8281 shader
->info
.fs
.uses_sample_qualifier
||
8282 shader
->info
.outputs_read
);
8284 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8286 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8287 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8288 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8290 prog_data
->barycentric_interp_modes
=
8291 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8293 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8294 brw_compute_flat_inputs(prog_data
, shader
);
8296 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8298 fs_visitor
v8(compiler
, log_data
, mem_ctx
, &key
->base
,
8299 &prog_data
->base
, shader
, 8,
8300 shader_time_index8
);
8301 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
8303 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
8306 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8308 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
8309 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
8312 /* Limit dispatch width to simd8 with dual source blending on gen8.
8313 * See: https://gitlab.freedesktop.org/mesa/mesa/issues/1917
8315 if (devinfo
->gen
== 8 && prog_data
->dual_src_blend
&&
8316 !(INTEL_DEBUG
& DEBUG_NO8
)) {
8317 assert(!use_rep_send
);
8318 v8
.limit_dispatch_width(8, "gen8 workaround: "
8319 "using SIMD8 when dual src blending.\n");
8322 if (v8
.max_dispatch_width
>= 16 &&
8323 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8324 /* Try a SIMD16 compile */
8325 fs_visitor
v16(compiler
, log_data
, mem_ctx
, &key
->base
,
8326 &prog_data
->base
, shader
, 16,
8327 shader_time_index16
);
8328 v16
.import_uniforms(&v8
);
8329 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
8330 compiler
->shader_perf_log(log_data
,
8331 "SIMD16 shader failed to compile: %s",
8334 simd16_cfg
= v16
.cfg
;
8335 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
8336 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
8340 /* Currently, the compiler only supports SIMD32 on SNB+ */
8341 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
8342 compiler
->devinfo
->gen
>= 6 &&
8343 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
8344 /* Try a SIMD32 compile */
8345 fs_visitor
v32(compiler
, log_data
, mem_ctx
, &key
->base
,
8346 &prog_data
->base
, shader
, 32,
8347 shader_time_index32
);
8348 v32
.import_uniforms(&v8
);
8349 if (!v32
.run_fs(allow_spilling
, false)) {
8350 compiler
->shader_perf_log(log_data
,
8351 "SIMD32 shader failed to compile: %s",
8354 simd32_cfg
= v32
.cfg
;
8355 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
8356 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
8360 /* When the caller requests a repclear shader, they want SIMD16-only */
8364 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8365 * at the top to select the shader. We've never implemented that.
8366 * Instead, we just give them exactly one shader and we pick the widest one
8369 if (compiler
->devinfo
->gen
< 5) {
8370 if (simd32_cfg
|| simd16_cfg
)
8376 /* If computed depth is enabled SNB only allows SIMD8. */
8377 if (compiler
->devinfo
->gen
== 6 &&
8378 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8379 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8381 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8382 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8383 * the data available in the base prog data struct for convenience.
8386 prog_data
->base
.dispatch_grf_start_reg
=
8387 prog_data
->dispatch_grf_start_reg_16
;
8388 } else if (simd32_cfg
) {
8389 prog_data
->base
.dispatch_grf_start_reg
=
8390 prog_data
->dispatch_grf_start_reg_32
;
8394 if (prog_data
->persample_dispatch
) {
8395 /* Starting with SandyBridge (where we first get MSAA), the different
8396 * pixel dispatch combinations are grouped into classifications A
8397 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
8398 * generations, the only configurations supporting persample dispatch
8399 * are are this in which only one dispatch width is enabled.
8401 if (simd32_cfg
|| simd16_cfg
)
8407 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8408 v8
.shader_stats
, v8
.runtime_check_aads_emit
,
8409 MESA_SHADER_FRAGMENT
);
8411 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8412 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8413 shader
->info
.label
?
8414 shader
->info
.label
: "unnamed",
8415 shader
->info
.name
));
8419 prog_data
->dispatch_8
= true;
8420 g
.generate_code(simd8_cfg
, 8, stats
);
8421 stats
= stats
? stats
+ 1 : NULL
;
8425 prog_data
->dispatch_16
= true;
8426 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16, stats
);
8427 stats
= stats
? stats
+ 1 : NULL
;
8431 prog_data
->dispatch_32
= true;
8432 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32, stats
);
8433 stats
= stats
? stats
+ 1 : NULL
;
8436 return g
.get_assembly();
8440 fs_visitor::emit_cs_work_group_id_setup()
8442 assert(stage
== MESA_SHADER_COMPUTE
);
8444 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8446 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8447 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8448 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8450 bld
.MOV(*reg
, r0_1
);
8451 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8452 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8458 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8460 block
->dwords
= dwords
;
8461 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8462 block
->size
= block
->regs
* 32;
8466 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8467 struct brw_cs_prog_data
*cs_prog_data
)
8469 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8470 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8471 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8473 /* The thread ID should be stored in the last param dword */
8474 assert(subgroup_id_index
== -1 ||
8475 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8477 unsigned cross_thread_dwords
, per_thread_dwords
;
8478 if (!cross_thread_supported
) {
8479 cross_thread_dwords
= 0u;
8480 per_thread_dwords
= prog_data
->nr_params
;
8481 } else if (subgroup_id_index
>= 0) {
8482 /* Fill all but the last register with cross-thread payload */
8483 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8484 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8485 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8487 /* Fill all data using cross-thread payload */
8488 cross_thread_dwords
= prog_data
->nr_params
;
8489 per_thread_dwords
= 0u;
8492 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8493 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8495 unsigned total_dwords
=
8496 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
8497 cs_prog_data
->push
.cross_thread
.size
) / 4;
8498 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
8500 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8501 cs_prog_data
->push
.per_thread
.size
== 0);
8502 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8503 cs_prog_data
->push
.per_thread
.dwords
==
8504 prog_data
->nr_params
);
8508 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
8510 cs_prog_data
->simd_size
= size
;
8511 unsigned group_size
= cs_prog_data
->local_size
[0] *
8512 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
8513 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
8517 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8519 const struct brw_cs_prog_key
*key
,
8520 const nir_shader
*src_shader
,
8521 unsigned dispatch_width
)
8523 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8524 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8526 NIR_PASS_V(shader
, brw_nir_lower_cs_intrinsics
, dispatch_width
);
8528 /* Clean up after the local index and ID calculations. */
8529 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8530 NIR_PASS_V(shader
, nir_opt_dce
);
8532 brw_postprocess_nir(shader
, compiler
, true);
8538 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8540 const struct brw_cs_prog_key
*key
,
8541 struct brw_cs_prog_data
*prog_data
,
8542 const nir_shader
*src_shader
,
8543 int shader_time_index
,
8544 struct brw_compile_stats
*stats
,
8547 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8548 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8549 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8550 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8551 prog_data
->slm_size
= src_shader
->num_shared
;
8552 unsigned local_workgroup_size
=
8553 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
8554 src_shader
->info
.cs
.local_size
[2];
8556 unsigned min_dispatch_width
=
8557 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
8558 min_dispatch_width
= MAX2(8, min_dispatch_width
);
8559 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
8560 assert(min_dispatch_width
<= 32);
8561 unsigned max_dispatch_width
= 32;
8563 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8564 fs_visitor
*v
= NULL
;
8565 const char *fail_msg
= NULL
;
8567 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8568 /* These enum values are expressly chosen to be equal to the subgroup
8569 * size that they require.
8571 const unsigned required_dispatch_width
=
8572 (unsigned)key
->base
.subgroup_size_type
;
8573 assert(required_dispatch_width
== 8 ||
8574 required_dispatch_width
== 16 ||
8575 required_dispatch_width
== 32);
8576 if (required_dispatch_width
< min_dispatch_width
||
8577 required_dispatch_width
> max_dispatch_width
) {
8578 fail_msg
= "Cannot satisfy explicit subgroup size";
8580 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8584 /* Now the main event: Visit the shader IR and generate our CS IR for it.
8586 if (!fail_msg
&& min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8587 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8589 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8591 nir8
, 8, shader_time_index
);
8592 if (!v8
->run_cs(min_dispatch_width
)) {
8593 fail_msg
= v8
->fail_msg
;
8595 /* We should always be able to do SIMD32 for compute shaders */
8596 assert(v8
->max_dispatch_width
>= 32);
8599 cs_set_simd_size(prog_data
, 8);
8600 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8604 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
8605 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
8606 /* Try a SIMD16 compile */
8607 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8609 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8611 nir16
, 16, shader_time_index
);
8613 v16
->import_uniforms(v8
);
8615 if (!v16
->run_cs(min_dispatch_width
)) {
8616 compiler
->shader_perf_log(log_data
,
8617 "SIMD16 shader failed to compile: %s",
8621 "Couldn't generate SIMD16 program and not "
8622 "enough threads for SIMD8";
8625 /* We should always be able to do SIMD32 for compute shaders */
8626 assert(v16
->max_dispatch_width
>= 32);
8629 cs_set_simd_size(prog_data
, 16);
8630 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8634 /* We should always be able to do SIMD32 for compute shaders */
8635 assert(!v16
|| v16
->max_dispatch_width
>= 32);
8637 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
8638 max_dispatch_width
>= 32) {
8639 /* Try a SIMD32 compile */
8640 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8642 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8644 nir32
, 32, shader_time_index
);
8646 v32
->import_uniforms(v8
);
8648 v32
->import_uniforms(v16
);
8650 if (!v32
->run_cs(min_dispatch_width
)) {
8651 compiler
->shader_perf_log(log_data
,
8652 "SIMD32 shader failed to compile: %s",
8656 "Couldn't generate SIMD32 program and not "
8657 "enough threads for SIMD16";
8661 cs_set_simd_size(prog_data
, 32);
8662 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8666 const unsigned *ret
= NULL
;
8667 if (unlikely(v
== NULL
)) {
8670 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
8672 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8673 v
->shader_stats
, v
->runtime_check_aads_emit
,
8674 MESA_SHADER_COMPUTE
);
8675 if (INTEL_DEBUG
& DEBUG_CS
) {
8676 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
8677 src_shader
->info
.label
?
8678 src_shader
->info
.label
: "unnamed",
8679 src_shader
->info
.name
);
8680 g
.enable_debug(name
);
8683 g
.generate_code(v
->cfg
, prog_data
->simd_size
, stats
);
8685 ret
= g
.get_assembly();
8696 * Test the dispatch mask packing assumptions of
8697 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
8698 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
8699 * executed with an unexpected dispatch mask.
8702 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
8704 const gl_shader_stage stage
= bld
.shader
->stage
;
8706 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
8707 bld
.shader
->stage_prog_data
)) {
8708 const fs_builder ubld
= bld
.exec_all().group(1, 0);
8709 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
8710 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
8713 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
8714 ubld
.AND(tmp
, mask
, tmp
);
8716 /* This will loop forever if the dispatch mask doesn't have the expected
8717 * form '2^n-1', in which case tmp will be non-zero.
8719 bld
.emit(BRW_OPCODE_DO
);
8720 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
8721 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));