2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
34 #include "brw_fs_live_variables.h"
36 #include "brw_vec4_gs_visitor.h"
38 #include "brw_dead_control_flow.h"
39 #include "dev/gen_debug.h"
40 #include "compiler/glsl_types.h"
41 #include "compiler/nir/nir_builder.h"
42 #include "program/prog_parameter.h"
43 #include "util/u_math.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset((void*)this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy((void*)this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
197 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
201 * A helper for MOV generation for fixing up broken hardware SEND dependency
205 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
207 /* The caller always wants uncompressed to emit the minimal extra
208 * dependencies, and to avoid having to deal with aligning its regs to 2.
210 const fs_builder ubld
= bld
.annotate("send dependency resolve")
213 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
217 fs_inst::is_send_from_grf() const
220 case SHADER_OPCODE_SEND
:
221 case SHADER_OPCODE_SHADER_TIME_ADD
:
222 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
223 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
224 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
228 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
229 case SHADER_OPCODE_URB_READ_SIMD8
:
230 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
231 case SHADER_OPCODE_INTERLOCK
:
232 case SHADER_OPCODE_MEMORY_FENCE
:
233 case SHADER_OPCODE_BARRIER
:
235 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
236 return src
[1].file
== VGRF
;
237 case FS_OPCODE_FB_WRITE
:
238 case FS_OPCODE_FB_READ
:
239 return src
[0].file
== VGRF
;
242 return src
[0].file
== VGRF
;
249 fs_inst::is_control_source(unsigned arg
) const
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
253 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
257 case SHADER_OPCODE_BROADCAST
:
258 case SHADER_OPCODE_SHUFFLE
:
259 case SHADER_OPCODE_QUAD_SWIZZLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
261 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
262 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
263 case SHADER_OPCODE_GET_BUFFER_SIZE
:
266 case SHADER_OPCODE_MOV_INDIRECT
:
267 case SHADER_OPCODE_CLUSTER_BROADCAST
:
268 case SHADER_OPCODE_TEX
:
270 case SHADER_OPCODE_TXD
:
271 case SHADER_OPCODE_TXF
:
272 case SHADER_OPCODE_TXF_LZ
:
273 case SHADER_OPCODE_TXF_CMS
:
274 case SHADER_OPCODE_TXF_CMS_W
:
275 case SHADER_OPCODE_TXF_UMS
:
276 case SHADER_OPCODE_TXF_MCS
:
277 case SHADER_OPCODE_TXL
:
278 case SHADER_OPCODE_TXL_LZ
:
279 case SHADER_OPCODE_TXS
:
280 case SHADER_OPCODE_LOD
:
281 case SHADER_OPCODE_TG4
:
282 case SHADER_OPCODE_TG4_OFFSET
:
283 case SHADER_OPCODE_SAMPLEINFO
:
284 return arg
== 1 || arg
== 2;
286 case SHADER_OPCODE_SEND
:
287 return arg
== 0 || arg
== 1;
295 fs_inst::is_payload(unsigned arg
) const
298 case FS_OPCODE_FB_WRITE
:
299 case FS_OPCODE_FB_READ
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
303 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
304 case SHADER_OPCODE_URB_READ_SIMD8
:
305 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
306 case VEC4_OPCODE_UNTYPED_ATOMIC
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
308 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
309 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
310 case SHADER_OPCODE_SHADER_TIME_ADD
:
311 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
312 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
313 case SHADER_OPCODE_INTERLOCK
:
314 case SHADER_OPCODE_MEMORY_FENCE
:
315 case SHADER_OPCODE_BARRIER
:
318 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SEND
:
322 return arg
== 2 || arg
== 3;
333 * Returns true if this instruction's sources and destinations cannot
334 * safely be the same register.
336 * In most cases, a register can be written over safely by the same
337 * instruction that is its last use. For a single instruction, the
338 * sources are dereferenced before writing of the destination starts
341 * However, there are a few cases where this can be problematic:
343 * - Virtual opcodes that translate to multiple instructions in the
344 * code generator: if src == dst and one instruction writes the
345 * destination before a later instruction reads the source, then
346 * src will have been clobbered.
348 * - SIMD16 compressed instructions with certain regioning (see below).
350 * The register allocator uses this information to set up conflicts between
351 * GRF sources and the destination.
354 fs_inst::has_source_and_destination_hazard() const
357 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
358 /* Multiple partial writes to the destination */
360 case SHADER_OPCODE_SHUFFLE
:
361 /* This instruction returns an arbitrary channel from the source and
362 * gets split into smaller instructions in the generator. It's possible
363 * that one of the instructions will read from a channel corresponding
364 * to an earlier instruction.
366 case SHADER_OPCODE_SEL_EXEC
:
367 /* This is implemented as
369 * mov(16) g4<1>D 0D { align1 WE_all 1H };
370 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
372 * Because the source is only read in the second instruction, the first
373 * may stomp all over it.
376 case SHADER_OPCODE_QUAD_SWIZZLE
:
378 case BRW_SWIZZLE_XXXX
:
379 case BRW_SWIZZLE_YYYY
:
380 case BRW_SWIZZLE_ZZZZ
:
381 case BRW_SWIZZLE_WWWW
:
382 case BRW_SWIZZLE_XXZZ
:
383 case BRW_SWIZZLE_YYWW
:
384 case BRW_SWIZZLE_XYXY
:
385 case BRW_SWIZZLE_ZWZW
:
386 /* These can be implemented as a single Align1 region on all
387 * platforms, so there's never a hazard between source and
388 * destination. C.f. fs_generator::generate_quad_swizzle().
392 return !is_uniform(src
[0]);
395 /* The SIMD16 compressed instruction
397 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
399 * is actually decoded in hardware as:
401 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
402 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
404 * Which is safe. However, if we have uniform accesses
405 * happening, we get into trouble:
407 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
408 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
410 * Now our destination for the first instruction overwrote the
411 * second instruction's src0, and we get garbage for those 8
412 * pixels. There's a similar issue for the pre-gen6
413 * pixel_x/pixel_y, which are registers of 16-bit values and thus
414 * would get stomped by the first decode as well.
416 if (exec_size
== 16) {
417 for (int i
= 0; i
< sources
; i
++) {
418 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
419 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
420 src
[i
].type
== BRW_REGISTER_TYPE_W
||
421 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
422 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
432 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
434 if (devinfo
->gen
== 6 && is_math())
437 if (is_send_from_grf())
440 /* From GEN:BUG:1604601757:
442 * "When multiplying a DW and any lower precision integer, source modifier
445 if (devinfo
->gen
>= 12 && (opcode
== BRW_OPCODE_MUL
||
446 opcode
== BRW_OPCODE_MAD
)) {
447 const brw_reg_type exec_type
= get_exec_type(this);
448 const unsigned min_type_sz
= opcode
== BRW_OPCODE_MAD
?
449 MIN2(type_sz(src
[1].type
), type_sz(src
[2].type
)) :
450 MIN2(type_sz(src
[0].type
), type_sz(src
[1].type
));
452 if (brw_reg_type_is_integer(exec_type
) &&
453 type_sz(exec_type
) >= 4 &&
454 type_sz(exec_type
) != min_type_sz
)
458 if (!backend_instruction::can_do_source_mods())
465 fs_inst::can_do_cmod()
467 if (!backend_instruction::can_do_cmod())
470 /* The accumulator result appears to get used for the conditional modifier
471 * generation. When negating a UD value, there is a 33rd bit generated for
472 * the sign in the accumulator value, so now you can't check, for example,
473 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
475 for (unsigned i
= 0; i
< sources
; i
++) {
476 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
484 fs_inst::can_change_types() const
486 return dst
.type
== src
[0].type
&&
487 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
488 (opcode
== BRW_OPCODE_MOV
||
489 (opcode
== BRW_OPCODE_SEL
&&
490 dst
.type
== src
[1].type
&&
491 predicate
!= BRW_PREDICATE_NONE
&&
492 !src
[1].abs
&& !src
[1].negate
));
498 memset((void*)this, 0, sizeof(*this));
499 type
= BRW_REGISTER_TYPE_UD
;
503 /** Generic unset register constructor. */
507 this->file
= BAD_FILE
;
510 fs_reg::fs_reg(struct ::brw_reg reg
) :
515 if (this->file
== IMM
&&
516 (this->type
!= BRW_REGISTER_TYPE_V
&&
517 this->type
!= BRW_REGISTER_TYPE_UV
&&
518 this->type
!= BRW_REGISTER_TYPE_VF
)) {
524 fs_reg::equals(const fs_reg
&r
) const
526 return (this->backend_reg::equals(r
) &&
531 fs_reg::negative_equals(const fs_reg
&r
) const
533 return (this->backend_reg::negative_equals(r
) &&
538 fs_reg::is_contiguous() const
543 return hstride
== BRW_HORIZONTAL_STRIDE_1
&&
544 vstride
== width
+ hstride
;
555 unreachable("Invalid register file");
559 fs_reg::component_size(unsigned width
) const
561 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
564 return MAX2(width
* stride
, 1) * type_sz(type
);
568 * Create a MOV to read the timestamp register.
571 fs_visitor::get_timestamp(const fs_builder
&bld
)
573 assert(devinfo
->gen
>= 7);
575 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
578 BRW_REGISTER_TYPE_UD
));
580 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
582 /* We want to read the 3 fields we care about even if it's not enabled in
585 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
591 fs_visitor::emit_shader_time_begin()
593 /* We want only the low 32 bits of the timestamp. Since it's running
594 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
595 * which is plenty of time for our purposes. It is identical across the
596 * EUs, but since it's tracking GPU core speed it will increment at a
597 * varying rate as render P-states change.
599 shader_start_time
= component(
600 get_timestamp(bld
.annotate("shader time start")), 0);
604 fs_visitor::emit_shader_time_end()
606 /* Insert our code just before the final SEND with EOT. */
607 exec_node
*end
= this->instructions
.get_tail();
608 assert(end
&& ((fs_inst
*) end
)->eot
);
609 const fs_builder ibld
= bld
.annotate("shader time end")
610 .exec_all().at(NULL
, end
);
611 const fs_reg timestamp
= get_timestamp(ibld
);
613 /* We only use the low 32 bits of the timestamp - see
614 * emit_shader_time_begin()).
616 * We could also check if render P-states have changed (or anything
617 * else that might disrupt timing) by setting smear to 2 and checking if
618 * that field is != 0.
620 const fs_reg shader_end_time
= component(timestamp
, 0);
622 /* Check that there weren't any timestamp reset events (assuming these
623 * were the only two timestamp reads that happened).
625 const fs_reg reset
= component(timestamp
, 2);
626 set_condmod(BRW_CONDITIONAL_Z
,
627 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
628 ibld
.IF(BRW_PREDICATE_NORMAL
);
630 fs_reg start
= shader_start_time
;
632 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
633 BRW_REGISTER_TYPE_UD
),
635 const fs_builder cbld
= ibld
.group(1, 0);
636 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
638 /* If there were no instructions between the two timestamp gets, the diff
639 * is 2 cycles. Remove that overhead, so I can forget about that when
640 * trying to determine the time taken for single instructions.
642 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
643 SHADER_TIME_ADD(cbld
, 0, diff
);
644 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
645 ibld
.emit(BRW_OPCODE_ELSE
);
646 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
647 ibld
.emit(BRW_OPCODE_ENDIF
);
651 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
652 int shader_time_subindex
,
655 int index
= shader_time_index
* 3 + shader_time_subindex
;
656 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
659 if (dispatch_width
== 8)
660 payload
= vgrf(glsl_type::uvec2_type
);
662 payload
= vgrf(glsl_type::uint_type
);
664 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
668 fs_visitor::vfail(const char *format
, va_list va
)
677 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
678 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
680 this->fail_msg
= msg
;
683 fprintf(stderr
, "%s", msg
);
688 fs_visitor::fail(const char *format
, ...)
692 va_start(va
, format
);
698 * Mark this program as impossible to compile with dispatch width greater
701 * During the SIMD8 compile (which happens first), we can detect and flag
702 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
703 * SIMD16+ compile altogether.
705 * During a compile of dispatch width greater than n (if one happens anyway),
706 * this just calls fail().
709 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
711 if (dispatch_width
> n
) {
714 max_dispatch_width
= n
;
715 compiler
->shader_perf_log(log_data
,
716 "Shader dispatch width limited to SIMD%d: %s",
722 * Returns true if the instruction has a flag that means it won't
723 * update an entire destination register.
725 * For example, dead code elimination and live variable analysis want to know
726 * when a write to a variable screens off any preceding values that were in
730 fs_inst::is_partial_write() const
732 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
733 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
734 !this->dst
.is_contiguous() ||
735 this->dst
.offset
% REG_SIZE
!= 0);
739 fs_inst::components_read(unsigned i
) const
741 /* Return zero if the source is not present. */
742 if (src
[i
].file
== BAD_FILE
)
746 case FS_OPCODE_LINTERP
:
752 case FS_OPCODE_PIXEL_X
:
753 case FS_OPCODE_PIXEL_Y
:
757 case FS_OPCODE_FB_WRITE_LOGICAL
:
758 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
759 /* First/second FB write color. */
761 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
765 case SHADER_OPCODE_TEX_LOGICAL
:
766 case SHADER_OPCODE_TXD_LOGICAL
:
767 case SHADER_OPCODE_TXF_LOGICAL
:
768 case SHADER_OPCODE_TXL_LOGICAL
:
769 case SHADER_OPCODE_TXS_LOGICAL
:
770 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
771 case FS_OPCODE_TXB_LOGICAL
:
772 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
773 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
774 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
775 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
776 case SHADER_OPCODE_LOD_LOGICAL
:
777 case SHADER_OPCODE_TG4_LOGICAL
:
778 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
779 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
780 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
781 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
782 /* Texture coordinates. */
783 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
784 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
785 /* Texture derivatives. */
786 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
787 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
788 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
789 /* Texture offset. */
790 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
793 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
798 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
799 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
800 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
801 /* Surface coordinates. */
802 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
803 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
804 /* Surface operation source (ignored for reads). */
805 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
810 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
811 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
812 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
813 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
814 /* Surface coordinates. */
815 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
816 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
817 /* Surface operation source. */
818 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
819 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
823 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
824 assert(src
[2].file
== IMM
);
827 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
828 assert(src
[2].file
== IMM
);
829 return i
== 1 ? src
[2].ud
: 1;
831 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
832 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
833 assert(src
[2].file
== IMM
);
836 const unsigned op
= src
[2].ud
;
851 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
852 assert(src
[2].file
== IMM
);
855 const unsigned op
= src
[2].ud
;
856 return op
== BRW_AOP_FCMPWR
? 2 : 1;
861 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
862 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
863 /* Scattered logical opcodes use the following params:
864 * src[0] Surface coordinates
865 * src[1] Surface operation source (ignored for reads)
867 * src[3] IMM with always 1 dimension.
868 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
870 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
871 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
872 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
874 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
875 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
876 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
877 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
880 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
881 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
882 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
883 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
884 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
885 /* Surface coordinates. */
886 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
887 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
888 /* Surface operation source. */
889 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
891 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
892 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
897 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
898 return (i
== 0 ? 2 : 1);
900 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
901 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
902 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
903 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
904 /* Surface coordinates. */
905 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
906 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
907 /* Surface operation source. */
908 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
920 fs_inst::size_read(int arg
) const
923 case SHADER_OPCODE_SEND
:
925 return mlen
* REG_SIZE
;
926 } else if (arg
== 3) {
927 return ex_mlen
* REG_SIZE
;
931 case FS_OPCODE_FB_WRITE
:
932 case FS_OPCODE_REP_FB_WRITE
:
935 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
937 return mlen
* REG_SIZE
;
941 case FS_OPCODE_FB_READ
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
945 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
946 case SHADER_OPCODE_URB_READ_SIMD8
:
947 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
948 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
949 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
951 return mlen
* REG_SIZE
;
954 case FS_OPCODE_SET_SAMPLE_ID
:
959 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
960 /* The payload is actually stored in src1 */
962 return mlen
* REG_SIZE
;
965 case FS_OPCODE_LINTERP
:
970 case SHADER_OPCODE_LOAD_PAYLOAD
:
971 if (arg
< this->header_size
)
975 case CS_OPCODE_CS_TERMINATE
:
976 case SHADER_OPCODE_BARRIER
:
979 case SHADER_OPCODE_MOV_INDIRECT
:
981 assert(src
[2].file
== IMM
);
987 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
988 return mlen
* REG_SIZE
;
992 switch (src
[arg
].file
) {
995 return components_read(arg
) * type_sz(src
[arg
].type
);
1001 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1003 unreachable("MRF registers are not allowed as sources");
1010 predicate_width(brw_predicate predicate
)
1012 switch (predicate
) {
1013 case BRW_PREDICATE_NONE
: return 1;
1014 case BRW_PREDICATE_NORMAL
: return 1;
1015 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1016 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1017 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1018 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1019 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1020 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1021 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1022 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1023 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1024 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1025 default: unreachable("Unsupported predicate");
1029 /* Return the subset of flag registers that an instruction could
1030 * potentially read or write based on the execution controls and flag
1031 * subregister number of the instruction.
1034 flag_mask(const fs_inst
*inst
, unsigned width
)
1036 assert(util_is_power_of_two_nonzero(width
));
1037 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1039 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1040 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1044 bit_mask(unsigned n
)
1046 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1050 flag_mask(const fs_reg
&r
, unsigned sz
)
1052 if (r
.file
== ARF
) {
1053 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1054 const unsigned end
= start
+ sz
;
1055 return bit_mask(end
) & ~bit_mask(start
);
1063 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1065 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1066 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1067 /* The vertical predication modes combine corresponding bits from
1068 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1070 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1071 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1072 } else if (predicate
) {
1073 return flag_mask(this, predicate_width(predicate
));
1076 for (int i
= 0; i
< sources
; i
++) {
1077 mask
|= flag_mask(src
[i
], size_read(i
));
1084 fs_inst::flags_written() const
1086 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1087 opcode
!= BRW_OPCODE_CSEL
&&
1088 opcode
!= BRW_OPCODE_IF
&&
1089 opcode
!= BRW_OPCODE_WHILE
)) ||
1090 opcode
== FS_OPCODE_FB_WRITE
) {
1091 return flag_mask(this, 1);
1092 } else if (opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1093 opcode
== FS_OPCODE_LOAD_LIVE_CHANNELS
) {
1094 return flag_mask(this, 32);
1096 return flag_mask(dst
, size_written
);
1101 * Returns how many MRFs an FS opcode will write over.
1103 * Note that this is not the 0 or 1 implied writes in an actual gen
1104 * instruction -- the FS opcodes often generate MOVs in addition.
1107 fs_inst::implied_mrf_writes() const
1116 case SHADER_OPCODE_RCP
:
1117 case SHADER_OPCODE_RSQ
:
1118 case SHADER_OPCODE_SQRT
:
1119 case SHADER_OPCODE_EXP2
:
1120 case SHADER_OPCODE_LOG2
:
1121 case SHADER_OPCODE_SIN
:
1122 case SHADER_OPCODE_COS
:
1123 return 1 * exec_size
/ 8;
1124 case SHADER_OPCODE_POW
:
1125 case SHADER_OPCODE_INT_QUOTIENT
:
1126 case SHADER_OPCODE_INT_REMAINDER
:
1127 return 2 * exec_size
/ 8;
1128 case SHADER_OPCODE_TEX
:
1130 case SHADER_OPCODE_TXD
:
1131 case SHADER_OPCODE_TXF
:
1132 case SHADER_OPCODE_TXF_CMS
:
1133 case SHADER_OPCODE_TXF_MCS
:
1134 case SHADER_OPCODE_TG4
:
1135 case SHADER_OPCODE_TG4_OFFSET
:
1136 case SHADER_OPCODE_TXL
:
1137 case SHADER_OPCODE_TXS
:
1138 case SHADER_OPCODE_LOD
:
1139 case SHADER_OPCODE_SAMPLEINFO
:
1141 case FS_OPCODE_FB_WRITE
:
1142 case FS_OPCODE_REP_FB_WRITE
:
1143 return src
[0].file
== BAD_FILE
? 0 : 2;
1144 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1145 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1147 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1149 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1152 unreachable("not reached");
1157 fs_visitor::vgrf(const glsl_type
*const type
)
1159 int reg_width
= dispatch_width
/ 8;
1161 alloc
.allocate(glsl_count_dword_slots(type
, false) * reg_width
),
1162 brw_type_for_base_type(type
));
1165 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1170 this->type
= BRW_REGISTER_TYPE_F
;
1171 this->stride
= (file
== UNIFORM
? 0 : 1);
1174 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1180 this->stride
= (file
== UNIFORM
? 0 : 1);
1183 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1184 * This brings in those uniform definitions
1187 fs_visitor::import_uniforms(fs_visitor
*v
)
1189 this->push_constant_loc
= v
->push_constant_loc
;
1190 this->pull_constant_loc
= v
->pull_constant_loc
;
1191 this->uniforms
= v
->uniforms
;
1192 this->subgroup_id
= v
->subgroup_id
;
1193 for (unsigned i
= 0; i
< ARRAY_SIZE(this->group_size
); i
++)
1194 this->group_size
[i
] = v
->group_size
[i
];
1198 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1200 assert(stage
== MESA_SHADER_FRAGMENT
);
1202 /* gl_FragCoord.x */
1203 bld
.MOV(wpos
, this->pixel_x
);
1204 wpos
= offset(wpos
, bld
, 1);
1206 /* gl_FragCoord.y */
1207 bld
.MOV(wpos
, this->pixel_y
);
1208 wpos
= offset(wpos
, bld
, 1);
1210 /* gl_FragCoord.z */
1211 if (devinfo
->gen
>= 6) {
1212 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1214 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1215 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1216 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1218 wpos
= offset(wpos
, bld
, 1);
1220 /* gl_FragCoord.w: Already set up in emit_interpolation */
1221 bld
.MOV(wpos
, this->wpos_w
);
1224 enum brw_barycentric_mode
1225 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1227 /* Barycentric modes don't make sense for flat inputs. */
1228 assert(mode
!= INTERP_MODE_FLAT
);
1232 case nir_intrinsic_load_barycentric_pixel
:
1233 case nir_intrinsic_load_barycentric_at_offset
:
1234 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1236 case nir_intrinsic_load_barycentric_centroid
:
1237 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1239 case nir_intrinsic_load_barycentric_sample
:
1240 case nir_intrinsic_load_barycentric_at_sample
:
1241 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1244 unreachable("invalid intrinsic");
1247 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1250 return (enum brw_barycentric_mode
) bary
;
1254 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1256 static enum brw_barycentric_mode
1257 centroid_to_pixel(enum brw_barycentric_mode bary
)
1259 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1260 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1261 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1265 fs_visitor::emit_frontfacing_interpolation()
1267 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1269 if (devinfo
->gen
>= 12) {
1270 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
1272 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1273 bld
.ASR(tmp
, g1
, brw_imm_d(15));
1275 } else if (devinfo
->gen
>= 6) {
1276 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1277 * a boolean result from this (~0/true or 0/false).
1279 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1280 * this task in only one instruction:
1281 * - a negation source modifier will flip the bit; and
1282 * - a W -> D type conversion will sign extend the bit into the high
1283 * word of the destination.
1285 * An ASR 15 fills the low word of the destination.
1287 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1290 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1292 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1293 * a boolean result from this (1/true or 0/false).
1295 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1296 * the negation source modifier to flip it. Unfortunately the SHR
1297 * instruction only operates on UD (or D with an abs source modifier)
1298 * sources without negation.
1300 * Instead, use ASR (which will give ~0/true or 0/false).
1302 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1305 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1312 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1314 assert(stage
== MESA_SHADER_FRAGMENT
);
1315 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1316 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1318 if (wm_prog_data
->persample_dispatch
) {
1319 /* Convert int_sample_pos to floating point */
1320 bld
.MOV(dst
, int_sample_pos
);
1321 /* Scale to the range [0, 1] */
1322 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1325 /* From ARB_sample_shading specification:
1326 * "When rendering to a non-multisample buffer, or if multisample
1327 * rasterization is disabled, gl_SamplePosition will always be
1330 bld
.MOV(dst
, brw_imm_f(0.5f
));
1335 fs_visitor::emit_samplepos_setup()
1337 assert(devinfo
->gen
>= 6);
1339 const fs_builder abld
= bld
.annotate("compute sample position");
1340 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1342 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1343 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1345 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1346 * mode will be enabled.
1348 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1349 * R31.1:0 Position Offset X/Y for Slot[3:0]
1350 * R31.3:2 Position Offset X/Y for Slot[7:4]
1353 * The X, Y sample positions come in as bytes in thread payload. So, read
1354 * the positions using vstride=16, width=8, hstride=2.
1356 const fs_reg sample_pos_reg
=
1357 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1359 /* Compute gl_SamplePosition.x */
1360 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1361 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1363 /* Compute gl_SamplePosition.y */
1364 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1365 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1370 fs_visitor::emit_sampleid_setup()
1372 assert(stage
== MESA_SHADER_FRAGMENT
);
1373 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1374 assert(devinfo
->gen
>= 6);
1376 const fs_builder abld
= bld
.annotate("compute sample id");
1377 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1379 if (!key
->multisample_fbo
) {
1380 /* As per GL_ARB_sample_shading specification:
1381 * "When rendering to a non-multisample buffer, or if multisample
1382 * rasterization is disabled, gl_SampleID will always be zero."
1384 abld
.MOV(*reg
, brw_imm_d(0));
1385 } else if (devinfo
->gen
>= 8) {
1386 /* Sample ID comes in as 4-bit numbers in g1.0:
1388 * 15:12 Slot 3 SampleID (only used in SIMD16)
1389 * 11:8 Slot 2 SampleID (only used in SIMD16)
1390 * 7:4 Slot 1 SampleID
1391 * 3:0 Slot 0 SampleID
1393 * Each slot corresponds to four channels, so we want to replicate each
1394 * half-byte value to 4 channels in a row:
1396 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1397 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1399 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1400 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1402 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1403 * channels to read the first byte (7:0), and the second group of 8
1404 * channels to read the second byte (15:8). Then, we shift right by
1405 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1406 * values into place. Finally, we AND with 0xf to keep the low nibble.
1408 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1409 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1411 * TODO: These payload bits exist on Gen7 too, but they appear to always
1412 * be zero, so this code fails to work. We should find out why.
1414 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1416 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1417 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1418 hbld
.SHR(offset(tmp
, hbld
, i
),
1419 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1421 brw_imm_v(0x44440000));
1424 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1426 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1427 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1429 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1430 * 8x multisampling, subspan 0 will represent sample N (where N
1431 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1432 * 7. We can find the value of N by looking at R0.0 bits 7:6
1433 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1434 * (since samples are always delivered in pairs). That is, we
1435 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1436 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1437 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1438 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1439 * populating a temporary variable with the sequence (0, 1, 2, 3),
1440 * and then reading from it using vstride=1, width=4, hstride=0.
1441 * These computations hold good for 4x multisampling as well.
1443 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1444 * the first four slots are sample 0 of subspan 0; the next four
1445 * are sample 1 of subspan 0; the third group is sample 0 of
1446 * subspan 1, and finally sample 1 of subspan 1.
1449 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1450 * accomodate 16x MSAA.
1452 abld
.exec_all().group(1, 0)
1453 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1455 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1457 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1458 * can assume 4x MSAA. Disallow it on IVB+
1460 * FINISHME: One day, we could come up with a way to do this that
1461 * actually works on gen7.
1463 if (devinfo
->gen
>= 7)
1464 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1465 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1467 /* This special instruction takes care of setting vstride=1,
1468 * width=4, hstride=0 of t2 during an ADD instruction.
1470 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1477 fs_visitor::emit_samplemaskin_setup()
1479 assert(stage
== MESA_SHADER_FRAGMENT
);
1480 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1481 assert(devinfo
->gen
>= 6);
1483 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1485 fs_reg coverage_mask
=
1486 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1488 if (wm_prog_data
->persample_dispatch
) {
1489 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1490 * and a mask representing which sample is being processed by the
1491 * current shader invocation.
1493 * From the OES_sample_variables specification:
1494 * "When per-sample shading is active due to the use of a fragment input
1495 * qualified by "sample" or due to the use of the gl_SampleID or
1496 * gl_SamplePosition variables, only the bit for the current sample is
1497 * set in gl_SampleMaskIn."
1499 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1501 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1502 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1504 fs_reg one
= vgrf(glsl_type::int_type
);
1505 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1506 abld
.MOV(one
, brw_imm_d(1));
1507 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1508 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1510 /* In per-pixel mode, the coverage mask is sufficient. */
1511 *reg
= coverage_mask
;
1517 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1519 if (!src
.abs
&& !src
.negate
)
1522 fs_reg temp
= bld
.vgrf(src
.type
);
1529 fs_visitor::emit_discard_jump()
1531 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1533 /* For performance, after a discard, jump to the end of the
1534 * shader if all relevant channels have been discarded.
1536 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1537 discard_jump
->flag_subreg
= sample_mask_flag_subreg(this);
1539 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1540 discard_jump
->predicate_inverse
= true;
1544 fs_visitor::emit_gs_thread_end()
1546 assert(stage
== MESA_SHADER_GEOMETRY
);
1548 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1550 if (gs_compile
->control_data_header_size_bits
> 0) {
1551 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1554 const fs_builder abld
= bld
.annotate("thread end");
1557 if (gs_prog_data
->static_vertex_count
!= -1) {
1558 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1559 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1560 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1561 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1562 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1565 /* Delete now dead instructions. */
1566 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1572 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1576 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1577 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1578 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1581 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1582 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1583 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1584 sources
[1] = this->final_gs_vertex_count
;
1585 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1586 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1594 fs_visitor::assign_curb_setup()
1596 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1598 unsigned ubo_push_length
= 0;
1599 unsigned ubo_push_start
[4];
1600 for (int i
= 0; i
< 4; i
++) {
1601 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1602 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1605 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1609 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1610 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1611 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1612 if (inst
->src
[i
].file
== UNIFORM
) {
1613 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1615 if (inst
->src
[i
].nr
>= UBO_START
) {
1616 /* constant_nr is in 32-bit units, the rest are in bytes */
1617 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1618 inst
->src
[i
].offset
/ 4;
1619 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1620 constant_nr
= push_constant_loc
[uniform_nr
];
1622 /* Section 5.11 of the OpenGL 4.1 spec says:
1623 * "Out-of-bounds reads return undefined values, which include
1624 * values from other variables of the active program or zero."
1625 * Just return the first push constant.
1630 assert(constant_nr
/ 8 < 64);
1631 used
|= BITFIELD64_BIT(constant_nr
/ 8);
1633 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1636 brw_reg
.abs
= inst
->src
[i
].abs
;
1637 brw_reg
.negate
= inst
->src
[i
].negate
;
1639 assert(inst
->src
[i
].stride
== 0);
1640 inst
->src
[i
] = byte_offset(
1641 retype(brw_reg
, inst
->src
[i
].type
),
1642 inst
->src
[i
].offset
% 4);
1647 uint64_t want_zero
= used
& stage_prog_data
->zero_push_reg
;
1649 assert(!compiler
->compact_params
);
1650 fs_builder ubld
= bld
.exec_all().group(8, 0).at(
1651 cfg
->first_block(), cfg
->first_block()->start());
1653 /* push_reg_mask_param is in 32-bit units */
1654 unsigned mask_param
= stage_prog_data
->push_reg_mask_param
;
1655 struct brw_reg mask
= brw_vec1_grf(payload
.num_regs
+ mask_param
/ 8,
1659 for (unsigned i
= 0; i
< 64; i
++) {
1660 if (i
% 16 == 0 && (want_zero
& BITFIELD64_RANGE(i
, 16))) {
1661 fs_reg shifted
= ubld
.vgrf(BRW_REGISTER_TYPE_W
, 2);
1662 ubld
.SHL(horiz_offset(shifted
, 8),
1663 byte_offset(retype(mask
, BRW_REGISTER_TYPE_W
), i
/ 8),
1664 brw_imm_v(0x01234567));
1665 ubld
.SHL(shifted
, horiz_offset(shifted
, 8), brw_imm_w(8));
1667 fs_builder ubld16
= ubld
.group(16, 0);
1668 b32
= ubld16
.vgrf(BRW_REGISTER_TYPE_D
);
1669 ubld16
.group(16, 0).ASR(b32
, shifted
, brw_imm_w(15));
1672 if (want_zero
& BITFIELD64_BIT(i
)) {
1673 assert(i
< prog_data
->curb_read_length
);
1674 struct brw_reg push_reg
=
1675 retype(brw_vec8_grf(payload
.num_regs
+ i
, 0),
1676 BRW_REGISTER_TYPE_D
);
1678 ubld
.AND(push_reg
, push_reg
, component(b32
, i
% 16));
1682 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
1685 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1686 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1690 * Build up an array of indices into the urb_setup array that
1691 * references the active entries of the urb_setup array.
1692 * Used to accelerate walking the active entries of the urb_setup array
1696 brw_compute_urb_setup_index(struct brw_wm_prog_data
*wm_prog_data
)
1698 /* Make sure uint8_t is sufficient */
1699 STATIC_ASSERT(VARYING_SLOT_MAX
<= 0xff);
1701 for (uint8_t attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1702 if (wm_prog_data
->urb_setup
[attr
] >= 0) {
1703 wm_prog_data
->urb_setup_attribs
[index
++] = attr
;
1706 wm_prog_data
->urb_setup_attribs_count
= index
;
1710 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1711 const struct brw_wm_prog_key
*key
,
1712 struct brw_wm_prog_data
*prog_data
,
1713 const nir_shader
*nir
)
1715 memset(prog_data
->urb_setup
, -1,
1716 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1719 /* Figure out where each of the incoming setup attributes lands. */
1720 if (devinfo
->gen
>= 6) {
1721 if (util_bitcount64(nir
->info
.inputs_read
&
1722 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1723 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1724 * first 16 varying inputs, so we can put them wherever we want.
1725 * Just put them in order.
1727 * This is useful because it means that (a) inputs not used by the
1728 * fragment shader won't take up valuable register space, and (b) we
1729 * won't have to recompile the fragment shader if it gets paired with
1730 * a different vertex (or geometry) shader.
1732 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1733 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1734 BITFIELD64_BIT(i
)) {
1735 prog_data
->urb_setup
[i
] = urb_next
++;
1739 /* We have enough input varyings that the SF/SBE pipeline stage can't
1740 * arbitrarily rearrange them to suit our whim; we have to put them
1741 * in an order that matches the output of the previous pipeline stage
1742 * (geometry or vertex shader).
1744 struct brw_vue_map prev_stage_vue_map
;
1745 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1746 key
->input_slots_valid
,
1747 nir
->info
.separate_shader
, 1);
1750 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1751 &prev_stage_vue_map
);
1753 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1754 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1756 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1757 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1758 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1759 BITFIELD64_BIT(varying
))) {
1760 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1763 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1766 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1767 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1768 /* Point size is packed into the header, not as a general attribute */
1769 if (i
== VARYING_SLOT_PSIZ
)
1772 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1773 /* The back color slot is skipped when the front color is
1774 * also written to. In addition, some slots can be
1775 * written in the vertex shader and not read in the
1776 * fragment shader. So the register number must always be
1777 * incremented, mapped or not.
1779 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1780 prog_data
->urb_setup
[i
] = urb_next
;
1786 * It's a FS only attribute, and we did interpolation for this attribute
1787 * in SF thread. So, count it here, too.
1789 * See compile_sf_prog() for more info.
1791 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1792 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1795 prog_data
->num_varying_inputs
= urb_next
;
1796 prog_data
->inputs
= nir
->info
.inputs_read
;
1798 brw_compute_urb_setup_index(prog_data
);
1802 fs_visitor::assign_urb_setup()
1804 assert(stage
== MESA_SHADER_FRAGMENT
);
1805 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1807 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1809 /* Offset all the urb_setup[] index by the actual position of the
1810 * setup regs, now that the location of the constants has been chosen.
1812 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1813 for (int i
= 0; i
< inst
->sources
; i
++) {
1814 if (inst
->src
[i
].file
== ATTR
) {
1815 /* ATTR regs in the FS are in units of logical scalar inputs each
1816 * of which consumes half of a GRF register.
1818 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1819 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1820 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1821 inst
->src
[i
].offset
;
1822 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1823 1 : MIN2(inst
->exec_size
, 8);
1824 struct brw_reg reg
= stride(
1825 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1827 width
* inst
->src
[i
].stride
,
1828 width
, inst
->src
[i
].stride
);
1829 reg
.abs
= inst
->src
[i
].abs
;
1830 reg
.negate
= inst
->src
[i
].negate
;
1836 /* Each attribute is 4 setup channels, each of which is half a reg. */
1837 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1841 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1843 for (int i
= 0; i
< inst
->sources
; i
++) {
1844 if (inst
->src
[i
].file
== ATTR
) {
1845 int grf
= payload
.num_regs
+
1846 prog_data
->curb_read_length
+
1848 inst
->src
[i
].offset
/ REG_SIZE
;
1850 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1852 * VertStride must be used to cross GRF register boundaries. This
1853 * rule implies that elements within a 'Width' cannot cross GRF
1856 * So, for registers that are large enough, we have to split the exec
1857 * size in two and trust the compression state to sort it out.
1859 unsigned total_size
= inst
->exec_size
*
1860 inst
->src
[i
].stride
*
1861 type_sz(inst
->src
[i
].type
);
1863 assert(total_size
<= 2 * REG_SIZE
);
1864 const unsigned exec_size
=
1865 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1867 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1868 struct brw_reg reg
=
1869 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1870 inst
->src
[i
].offset
% REG_SIZE
),
1871 exec_size
* inst
->src
[i
].stride
,
1872 width
, inst
->src
[i
].stride
);
1873 reg
.abs
= inst
->src
[i
].abs
;
1874 reg
.negate
= inst
->src
[i
].negate
;
1882 fs_visitor::assign_vs_urb_setup()
1884 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1886 assert(stage
== MESA_SHADER_VERTEX
);
1888 /* Each attribute is 4 regs. */
1889 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1891 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1893 /* Rewrite all ATTR file references to the hw grf that they land in. */
1894 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1895 convert_attr_sources_to_hw_regs(inst
);
1900 fs_visitor::assign_tcs_urb_setup()
1902 assert(stage
== MESA_SHADER_TESS_CTRL
);
1904 /* Rewrite all ATTR file references to HW_REGs. */
1905 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1906 convert_attr_sources_to_hw_regs(inst
);
1911 fs_visitor::assign_tes_urb_setup()
1913 assert(stage
== MESA_SHADER_TESS_EVAL
);
1915 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1917 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1919 /* Rewrite all ATTR file references to HW_REGs. */
1920 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1921 convert_attr_sources_to_hw_regs(inst
);
1926 fs_visitor::assign_gs_urb_setup()
1928 assert(stage
== MESA_SHADER_GEOMETRY
);
1930 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1932 first_non_payload_grf
+=
1933 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1935 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1936 /* Rewrite all ATTR file references to GRFs. */
1937 convert_attr_sources_to_hw_regs(inst
);
1943 * Split large virtual GRFs into separate components if we can.
1945 * This is mostly duplicated with what brw_fs_vector_splitting does,
1946 * but that's really conservative because it's afraid of doing
1947 * splitting that doesn't result in real progress after the rest of
1948 * the optimization phases, which would cause infinite looping in
1949 * optimization. We can do it once here, safely. This also has the
1950 * opportunity to split interpolated values, or maybe even uniforms,
1951 * which we don't have at the IR level.
1953 * We want to split, because virtual GRFs are what we register
1954 * allocate and spill (due to contiguousness requirements for some
1955 * instructions), and they're what we naturally generate in the
1956 * codegen process, but most virtual GRFs don't actually need to be
1957 * contiguous sets of GRFs. If we split, we'll end up with reduced
1958 * live intervals and better dead code elimination and coalescing.
1961 fs_visitor::split_virtual_grfs()
1963 /* Compact the register file so we eliminate dead vgrfs. This
1964 * only defines split points for live registers, so if we have
1965 * too large dead registers they will hit assertions later.
1967 compact_virtual_grfs();
1969 int num_vars
= this->alloc
.count
;
1971 /* Count the total number of registers */
1973 int vgrf_to_reg
[num_vars
];
1974 for (int i
= 0; i
< num_vars
; i
++) {
1975 vgrf_to_reg
[i
] = reg_count
;
1976 reg_count
+= alloc
.sizes
[i
];
1979 /* An array of "split points". For each register slot, this indicates
1980 * if this slot can be separated from the previous slot. Every time an
1981 * instruction uses multiple elements of a register (as a source or
1982 * destination), we mark the used slots as inseparable. Then we go
1983 * through and split the registers into the smallest pieces we can.
1985 bool *split_points
= new bool[reg_count
];
1986 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1988 /* Mark all used registers as fully splittable */
1989 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1990 if (inst
->dst
.file
== VGRF
) {
1991 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1992 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1993 split_points
[reg
+ j
] = true;
1996 for (int i
= 0; i
< inst
->sources
; i
++) {
1997 if (inst
->src
[i
].file
== VGRF
) {
1998 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1999 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
2000 split_points
[reg
+ j
] = true;
2005 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2006 /* We fix up undef instructions later */
2007 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2008 /* UNDEF instructions are currently only used to undef entire
2009 * registers. We need this invariant later when we split them.
2011 assert(inst
->dst
.file
== VGRF
);
2012 assert(inst
->dst
.offset
== 0);
2013 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
2017 if (inst
->dst
.file
== VGRF
) {
2018 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2019 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
2020 split_points
[reg
+ j
] = false;
2022 for (int i
= 0; i
< inst
->sources
; i
++) {
2023 if (inst
->src
[i
].file
== VGRF
) {
2024 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2025 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
2026 split_points
[reg
+ j
] = false;
2031 int *new_virtual_grf
= new int[reg_count
];
2032 int *new_reg_offset
= new int[reg_count
];
2035 for (int i
= 0; i
< num_vars
; i
++) {
2036 /* The first one should always be 0 as a quick sanity check. */
2037 assert(split_points
[reg
] == false);
2040 new_reg_offset
[reg
] = 0;
2045 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2046 /* If this is a split point, reset the offset to 0 and allocate a
2047 * new virtual GRF for the previous offset many registers
2049 if (split_points
[reg
]) {
2050 assert(offset
<= MAX_VGRF_SIZE
);
2051 int grf
= alloc
.allocate(offset
);
2052 for (int k
= reg
- offset
; k
< reg
; k
++)
2053 new_virtual_grf
[k
] = grf
;
2056 new_reg_offset
[reg
] = offset
;
2061 /* The last one gets the original register number */
2062 assert(offset
<= MAX_VGRF_SIZE
);
2063 alloc
.sizes
[i
] = offset
;
2064 for (int k
= reg
- offset
; k
< reg
; k
++)
2065 new_virtual_grf
[k
] = i
;
2067 assert(reg
== reg_count
);
2069 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2070 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2071 const fs_builder
ibld(this, block
, inst
);
2072 assert(inst
->size_written
% REG_SIZE
== 0);
2073 unsigned reg_offset
= 0;
2074 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2075 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2076 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2077 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2079 inst
->remove(block
);
2083 if (inst
->dst
.file
== VGRF
) {
2084 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2085 inst
->dst
.nr
= new_virtual_grf
[reg
];
2086 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2087 inst
->dst
.offset
% REG_SIZE
;
2088 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2090 for (int i
= 0; i
< inst
->sources
; i
++) {
2091 if (inst
->src
[i
].file
== VGRF
) {
2092 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2093 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2094 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2095 inst
->src
[i
].offset
% REG_SIZE
;
2096 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2100 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2102 delete[] split_points
;
2103 delete[] new_virtual_grf
;
2104 delete[] new_reg_offset
;
2108 * Remove unused virtual GRFs and compact the vgrf_* arrays.
2110 * During code generation, we create tons of temporary variables, many of
2111 * which get immediately killed and are never used again. Yet, in later
2112 * optimization and analysis passes, such as compute_live_intervals, we need
2113 * to loop over all the virtual GRFs. Compacting them can save a lot of
2117 fs_visitor::compact_virtual_grfs()
2119 bool progress
= false;
2120 int *remap_table
= new int[this->alloc
.count
];
2121 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2123 /* Mark which virtual GRFs are used. */
2124 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2125 if (inst
->dst
.file
== VGRF
)
2126 remap_table
[inst
->dst
.nr
] = 0;
2128 for (int i
= 0; i
< inst
->sources
; i
++) {
2129 if (inst
->src
[i
].file
== VGRF
)
2130 remap_table
[inst
->src
[i
].nr
] = 0;
2134 /* Compact the GRF arrays. */
2136 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2137 if (remap_table
[i
] == -1) {
2138 /* We just found an unused register. This means that we are
2139 * actually going to compact something.
2143 remap_table
[i
] = new_index
;
2144 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2145 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2150 this->alloc
.count
= new_index
;
2152 /* Patch all the instructions to use the newly renumbered registers */
2153 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2154 if (inst
->dst
.file
== VGRF
)
2155 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2157 for (int i
= 0; i
< inst
->sources
; i
++) {
2158 if (inst
->src
[i
].file
== VGRF
)
2159 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2163 /* Patch all the references to delta_xy, since they're used in register
2164 * allocation. If they're unused, switch them to BAD_FILE so we don't
2165 * think some random VGRF is delta_xy.
2167 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2168 if (delta_xy
[i
].file
== VGRF
) {
2169 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2170 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2172 delta_xy
[i
].file
= BAD_FILE
;
2177 delete[] remap_table
;
2183 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2185 if (prog_data
->nr_params
== 0)
2188 /* The local thread id is always the last parameter in the list */
2189 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2190 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2191 return prog_data
->nr_params
- 1;
2197 * Struct for handling complex alignments.
2199 * A complex alignment is stored as multiplier and an offset. A value is
2200 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2201 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2204 * N | cplx_align_apply({8, 2}, N)
2205 * ----+-----------------------------
2219 #define CPLX_ALIGN_MAX_MUL 8
2222 cplx_align_assert_sane(struct cplx_align a
)
2224 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2225 assert(a
.offset
< a
.mul
);
2229 * Combines two alignments to produce a least multiple of sorts.
2231 * The returned alignment is the smallest (in terms of multiplier) such that
2232 * anything aligned to both a and b will be aligned to the new alignment.
2233 * This function will assert-fail if a and b are not compatible, i.e. if the
2234 * offset parameters are such that no common alignment is possible.
2236 static struct cplx_align
2237 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2239 cplx_align_assert_sane(a
);
2240 cplx_align_assert_sane(b
);
2242 /* Assert that the alignments agree. */
2243 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2245 return a
.mul
> b
.mul
? a
: b
;
2249 * Apply a complex alignment
2251 * This function will return the smallest number greater than or equal to
2252 * offset that is aligned to align.
2255 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2257 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2260 #define UNIFORM_SLOT_SIZE 4
2262 struct uniform_slot_info
{
2263 /** True if the given uniform slot is live */
2266 /** True if this slot and the next slot must remain contiguous */
2267 unsigned contiguous
:1;
2269 struct cplx_align align
;
2273 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2274 unsigned num_slots
, unsigned alignment
)
2276 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2277 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2279 /* We can't align a slot to anything less than the slot size */
2280 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2282 struct cplx_align align
= {alignment
, 0};
2283 cplx_align_assert_sane(align
);
2285 for (unsigned i
= 0; i
< num_slots
; i
++) {
2286 slots
[i
].is_live
= true;
2287 if (i
< num_slots
- 1)
2288 slots
[i
].contiguous
= true;
2290 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2291 if (slots
[i
].align
.mul
== 0) {
2292 slots
[i
].align
= align
;
2294 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2300 * Assign UNIFORM file registers to either push constants or pull constants.
2302 * We allow a fragment shader to have more than the specified minimum
2303 * maximum number of fragment shader uniform components (64). If
2304 * there are too many of these, they'd fill up all of register space.
2305 * So, this will push some of them out to the pull constant buffer and
2306 * update the program to load them.
2309 fs_visitor::assign_constant_locations()
2311 /* Only the first compile gets to decide on locations. */
2312 if (push_constant_loc
) {
2313 assert(pull_constant_loc
);
2317 if (compiler
->compact_params
) {
2318 struct uniform_slot_info slots
[uniforms
+ 1];
2319 memset(slots
, 0, sizeof(slots
));
2321 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2322 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2323 if (inst
->src
[i
].file
!= UNIFORM
)
2326 /* NIR tightly packs things so the uniform number might not be
2327 * aligned (if we have a double right after a float, for
2328 * instance). This is fine because the process of re-arranging
2329 * them will ensure that things are properly aligned. The offset
2330 * into that uniform, however, must be aligned.
2332 * In Vulkan, we have explicit offsets but everything is crammed
2333 * into a single "variable" so inst->src[i].nr will always be 0.
2334 * Everything will be properly aligned relative to that one base.
2336 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2338 unsigned u
= inst
->src
[i
].nr
+
2339 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2344 unsigned slots_read
;
2345 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2346 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2348 unsigned bytes_read
= inst
->components_read(i
) *
2349 type_sz(inst
->src
[i
].type
);
2350 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2353 assert(u
+ slots_read
<= uniforms
);
2354 mark_uniform_slots_read(&slots
[u
], slots_read
,
2355 type_sz(inst
->src
[i
].type
));
2359 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2361 /* Only allow 16 registers (128 uniform components) as push constants.
2363 * Just demote the end of the list. We could probably do better
2364 * here, demoting things that are rarely used in the program first.
2366 * If changing this value, note the limitation about total_regs in
2369 unsigned int max_push_components
= 16 * 8;
2370 if (subgroup_id_index
>= 0)
2371 max_push_components
--; /* Save a slot for the thread ID */
2373 /* We push small arrays, but no bigger than 16 floats. This is big
2374 * enough for a vec4 but hopefully not large enough to push out other
2375 * stuff. We should probably use a better heuristic at some point.
2377 const unsigned int max_chunk_size
= 16;
2379 unsigned int num_push_constants
= 0;
2380 unsigned int num_pull_constants
= 0;
2382 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2383 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2385 /* Default to -1 meaning no location */
2386 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2387 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2389 int chunk_start
= -1;
2390 struct cplx_align align
;
2391 for (unsigned u
= 0; u
< uniforms
; u
++) {
2392 if (!slots
[u
].is_live
) {
2393 assert(chunk_start
== -1);
2397 /* Skip subgroup_id_index to put it in the last push register. */
2398 if (subgroup_id_index
== (int)u
)
2401 if (chunk_start
== -1) {
2403 align
= slots
[u
].align
;
2405 /* Offset into the chunk */
2406 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2408 /* Shift the slot alignment down by the chunk offset so it is
2409 * comparable with the base chunk alignment.
2411 struct cplx_align slot_align
= slots
[u
].align
;
2413 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2415 align
= cplx_align_combine(align
, slot_align
);
2418 /* Sanity check the alignment */
2419 cplx_align_assert_sane(align
);
2421 if (slots
[u
].contiguous
)
2424 /* Adjust the alignment to be in terms of slots, not bytes */
2425 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2426 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2427 align
.mul
/= UNIFORM_SLOT_SIZE
;
2428 align
.offset
/= UNIFORM_SLOT_SIZE
;
2430 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2431 unsigned chunk_size
= u
- chunk_start
+ 1;
2432 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2433 (chunk_size
< max_chunk_size
&&
2434 push_start_align
+ chunk_size
<= max_push_components
)) {
2435 /* Align up the number of push constants */
2436 num_push_constants
= push_start_align
;
2437 for (unsigned i
= 0; i
< chunk_size
; i
++)
2438 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2440 /* We need to pull this one */
2441 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2442 for (unsigned i
= 0; i
< chunk_size
; i
++)
2443 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2446 /* Reset the chunk and start again */
2450 /* Add the CS local thread ID uniform at the end of the push constants */
2451 if (subgroup_id_index
>= 0)
2452 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2454 /* As the uniforms are going to be reordered, stash the old array and
2455 * create two new arrays for push/pull params.
2457 uint32_t *param
= stage_prog_data
->param
;
2458 stage_prog_data
->nr_params
= num_push_constants
;
2459 if (num_push_constants
) {
2460 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2461 num_push_constants
);
2463 stage_prog_data
->param
= NULL
;
2465 assert(stage_prog_data
->nr_pull_params
== 0);
2466 assert(stage_prog_data
->pull_param
== NULL
);
2467 if (num_pull_constants
> 0) {
2468 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2469 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2470 num_pull_constants
);
2473 /* Up until now, the param[] array has been indexed by reg + offset
2474 * of UNIFORM registers. Move pull constants into pull_param[] and
2475 * condense param[] to only contain the uniforms we chose to push.
2477 * NOTE: Because we are condensing the params[] array, we know that
2478 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2479 * having to make a copy.
2481 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2482 uint32_t value
= param
[i
];
2483 if (pull_constant_loc
[i
] != -1) {
2484 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2485 } else if (push_constant_loc
[i
] != -1) {
2486 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2491 /* If we don't want to compact anything, just set up dummy push/pull
2492 * arrays. All the rest of the compiler cares about are these arrays.
2494 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2495 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2497 for (unsigned u
= 0; u
< uniforms
; u
++)
2498 push_constant_loc
[u
] = u
;
2500 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2503 /* Now that we know how many regular uniforms we'll push, reduce the
2504 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2506 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2507 for (int i
= 0; i
< 4; i
++) {
2508 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2510 if (push_length
+ range
->length
> 64)
2511 range
->length
= 64 - push_length
;
2513 push_length
+= range
->length
;
2515 assert(push_length
<= 64);
2519 fs_visitor::get_pull_locs(const fs_reg
&src
,
2520 unsigned *out_surf_index
,
2521 unsigned *out_pull_index
)
2523 assert(src
.file
== UNIFORM
);
2525 if (src
.nr
>= UBO_START
) {
2526 const struct brw_ubo_range
*range
=
2527 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2529 /* If this access is in our (reduced) range, use the push data. */
2530 if (src
.offset
/ 32 < range
->length
)
2533 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2534 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2536 prog_data
->has_ubo_pull
= true;
2540 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2542 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2543 /* A regular uniform push constant */
2544 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2545 *out_pull_index
= pull_constant_loc
[location
];
2547 prog_data
->has_ubo_pull
= true;
2555 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2556 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2559 fs_visitor::lower_constant_loads()
2561 unsigned index
, pull_index
;
2563 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2564 /* Set up the annotation tracking for new generated instructions. */
2565 const fs_builder
ibld(this, block
, inst
);
2567 for (int i
= 0; i
< inst
->sources
; i
++) {
2568 if (inst
->src
[i
].file
!= UNIFORM
)
2571 /* We'll handle this case later */
2572 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2575 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2578 assert(inst
->src
[i
].stride
== 0);
2580 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2581 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2582 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2583 const unsigned base
= pull_index
* 4;
2585 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2586 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2588 /* Rewrite the instruction to use the temporary VGRF. */
2589 inst
->src
[i
].file
= VGRF
;
2590 inst
->src
[i
].nr
= dst
.nr
;
2591 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2592 inst
->src
[i
].offset
% 4;
2595 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2596 inst
->src
[0].file
== UNIFORM
) {
2598 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2601 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2605 inst
->remove(block
);
2608 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
2612 fs_visitor::opt_algebraic()
2614 bool progress
= false;
2616 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2617 switch (inst
->opcode
) {
2618 case BRW_OPCODE_MOV
:
2619 if (!devinfo
->has_64bit_float
&&
2620 !devinfo
->has_64bit_int
&&
2621 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2622 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2623 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2624 assert(inst
->dst
.type
== inst
->src
[0].type
);
2625 assert(!inst
->saturate
);
2626 assert(!inst
->src
[0].abs
);
2627 assert(!inst
->src
[0].negate
);
2628 const brw::fs_builder
ibld(this, block
, inst
);
2630 if (inst
->src
[0].file
== IMM
) {
2631 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2632 brw_imm_ud(inst
->src
[0].u64
>> 32));
2633 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2634 brw_imm_ud(inst
->src
[0].u64
));
2636 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2637 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2638 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2639 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2642 inst
->remove(block
);
2646 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2647 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2648 inst
->dst
.is_null() &&
2649 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2650 inst
->src
[0].abs
= false;
2651 inst
->src
[0].negate
= false;
2656 if (inst
->src
[0].file
!= IMM
)
2659 if (inst
->saturate
) {
2660 /* Full mixed-type saturates don't happen. However, we can end up
2663 * mov.sat(8) g21<1>DF -1F
2665 * Other mixed-size-but-same-base-type cases may also be possible.
2667 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2668 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2669 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2670 assert(!"unimplemented: saturate mixed types");
2672 if (brw_saturate_immediate(inst
->src
[0].type
,
2673 &inst
->src
[0].as_brw_reg())) {
2674 inst
->saturate
= false;
2680 case BRW_OPCODE_MUL
:
2681 if (inst
->src
[1].file
!= IMM
)
2685 if (inst
->src
[1].is_one()) {
2686 inst
->opcode
= BRW_OPCODE_MOV
;
2687 inst
->src
[1] = reg_undef
;
2693 if (inst
->src
[1].is_negative_one()) {
2694 inst
->opcode
= BRW_OPCODE_MOV
;
2695 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2696 inst
->src
[1] = reg_undef
;
2701 if (inst
->src
[0].file
== IMM
) {
2702 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2703 inst
->opcode
= BRW_OPCODE_MOV
;
2704 inst
->src
[0].f
*= inst
->src
[1].f
;
2705 inst
->src
[1] = reg_undef
;
2710 case BRW_OPCODE_ADD
:
2711 if (inst
->src
[1].file
!= IMM
)
2714 if (inst
->src
[0].file
== IMM
) {
2715 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2716 inst
->opcode
= BRW_OPCODE_MOV
;
2717 inst
->src
[0].f
+= inst
->src
[1].f
;
2718 inst
->src
[1] = reg_undef
;
2724 if (inst
->src
[0].equals(inst
->src
[1]) ||
2725 inst
->src
[1].is_zero()) {
2726 /* On Gen8+, the OR instruction can have a source modifier that
2727 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2728 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2730 if (inst
->src
[0].negate
) {
2731 inst
->opcode
= BRW_OPCODE_NOT
;
2732 inst
->src
[0].negate
= false;
2734 inst
->opcode
= BRW_OPCODE_MOV
;
2736 inst
->src
[1] = reg_undef
;
2741 case BRW_OPCODE_CMP
:
2742 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2743 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2744 inst
->src
[1].is_zero() &&
2745 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2746 inst
->src
[0].abs
= false;
2747 inst
->src
[0].negate
= false;
2752 case BRW_OPCODE_SEL
:
2753 if (!devinfo
->has_64bit_float
&&
2754 !devinfo
->has_64bit_int
&&
2755 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2756 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2757 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2758 assert(inst
->dst
.type
== inst
->src
[0].type
);
2759 assert(!inst
->saturate
);
2760 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2761 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2762 const brw::fs_builder
ibld(this, block
, inst
);
2764 set_predicate(inst
->predicate
,
2765 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2766 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2767 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2768 set_predicate(inst
->predicate
,
2769 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2770 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2771 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2773 inst
->remove(block
);
2776 if (inst
->src
[0].equals(inst
->src
[1])) {
2777 inst
->opcode
= BRW_OPCODE_MOV
;
2778 inst
->src
[1] = reg_undef
;
2779 inst
->predicate
= BRW_PREDICATE_NONE
;
2780 inst
->predicate_inverse
= false;
2782 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2783 switch (inst
->conditional_mod
) {
2784 case BRW_CONDITIONAL_LE
:
2785 case BRW_CONDITIONAL_L
:
2786 switch (inst
->src
[1].type
) {
2787 case BRW_REGISTER_TYPE_F
:
2788 if (inst
->src
[1].f
>= 1.0f
) {
2789 inst
->opcode
= BRW_OPCODE_MOV
;
2790 inst
->src
[1] = reg_undef
;
2791 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2799 case BRW_CONDITIONAL_GE
:
2800 case BRW_CONDITIONAL_G
:
2801 switch (inst
->src
[1].type
) {
2802 case BRW_REGISTER_TYPE_F
:
2803 if (inst
->src
[1].f
<= 0.0f
) {
2804 inst
->opcode
= BRW_OPCODE_MOV
;
2805 inst
->src
[1] = reg_undef
;
2806 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2818 case BRW_OPCODE_MAD
:
2819 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2820 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2821 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2823 if (inst
->src
[1].is_one()) {
2824 inst
->opcode
= BRW_OPCODE_ADD
;
2825 inst
->src
[1] = inst
->src
[2];
2826 inst
->src
[2] = reg_undef
;
2828 } else if (inst
->src
[2].is_one()) {
2829 inst
->opcode
= BRW_OPCODE_ADD
;
2830 inst
->src
[2] = reg_undef
;
2834 case SHADER_OPCODE_BROADCAST
:
2835 if (is_uniform(inst
->src
[0])) {
2836 inst
->opcode
= BRW_OPCODE_MOV
;
2838 inst
->force_writemask_all
= true;
2840 } else if (inst
->src
[1].file
== IMM
) {
2841 inst
->opcode
= BRW_OPCODE_MOV
;
2842 /* It's possible that the selected component will be too large and
2843 * overflow the register. This can happen if someone does a
2844 * readInvocation() from GLSL or SPIR-V and provides an OOB
2845 * invocationIndex. If this happens and we some how manage
2846 * to constant fold it in and get here, then component() may cause
2847 * us to start reading outside of the VGRF which will lead to an
2848 * assert later. Instead, just let it wrap around if it goes over
2851 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2852 inst
->src
[0] = component(inst
->src
[0], comp
);
2854 inst
->force_writemask_all
= true;
2859 case SHADER_OPCODE_SHUFFLE
:
2860 if (is_uniform(inst
->src
[0])) {
2861 inst
->opcode
= BRW_OPCODE_MOV
;
2864 } else if (inst
->src
[1].file
== IMM
) {
2865 inst
->opcode
= BRW_OPCODE_MOV
;
2866 inst
->src
[0] = component(inst
->src
[0],
2877 /* Swap if src[0] is immediate. */
2878 if (progress
&& inst
->is_commutative()) {
2879 if (inst
->src
[0].file
== IMM
) {
2880 fs_reg tmp
= inst
->src
[1];
2881 inst
->src
[1] = inst
->src
[0];
2888 invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW
|
2889 DEPENDENCY_INSTRUCTION_DETAIL
);
2895 * Optimize sample messages that have constant zero values for the trailing
2896 * texture coordinates. We can just reduce the message length for these
2897 * instructions instead of reserving a register for it. Trailing parameters
2898 * that aren't sent default to zero anyway. This will cause the dead code
2899 * eliminator to remove the MOV instruction that would otherwise be emitted to
2900 * set up the zero value.
2903 fs_visitor::opt_zero_samples()
2905 /* Gen4 infers the texturing opcode based on the message length so we can't
2908 if (devinfo
->gen
< 5)
2911 bool progress
= false;
2913 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2914 if (!inst
->is_tex())
2917 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2919 if (load_payload
->is_head_sentinel() ||
2920 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2923 /* We don't want to remove the message header or the first parameter.
2924 * Removing the first parameter is not allowed, see the Haswell PRM
2925 * volume 7, page 149:
2927 * "Parameter 0 is required except for the sampleinfo message, which
2928 * has no parameter 0"
2930 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2931 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2932 (inst
->exec_size
/ 8) +
2933 inst
->header_size
- 1].is_zero()) {
2934 inst
->mlen
-= inst
->exec_size
/ 8;
2940 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
2946 * Optimize sample messages which are followed by the final RT write.
2948 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2949 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2950 * final texturing results copied to the framebuffer write payload and modify
2951 * them to write to the framebuffer directly.
2954 fs_visitor::opt_sampler_eot()
2956 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2958 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2961 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2964 /* FINISHME: It should be possible to implement this optimization when there
2965 * are multiple drawbuffers.
2967 if (key
->nr_color_regions
!= 1)
2970 /* Requires emitting a bunch of saturating MOV instructions during logical
2971 * send lowering to clamp the color payload, which the sampler unit isn't
2972 * going to do for us.
2974 if (key
->clamp_fragment_color
)
2977 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2978 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2979 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2980 assert(fb_write
->eot
);
2981 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2983 /* There wasn't one; nothing to do. */
2984 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2987 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2989 /* 3D Sampler » Messages » Message Format
2991 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2992 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2994 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2995 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2996 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2997 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2998 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2999 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
3000 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
3001 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
3004 /* XXX - This shouldn't be necessary. */
3005 if (tex_inst
->prev
->is_head_sentinel())
3008 /* Check that the FB write sources are fully initialized by the single
3009 * texturing instruction.
3011 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
3012 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
3013 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
3014 fb_write
->size_read(i
) != tex_inst
->size_written
)
3016 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
3017 if (fb_write
->src
[i
].file
!= BAD_FILE
)
3022 assert(!tex_inst
->eot
); /* We can't get here twice */
3023 assert((tex_inst
->offset
& (0xff << 24)) == 0);
3025 const fs_builder
ibld(this, block
, tex_inst
);
3027 tex_inst
->offset
|= fb_write
->target
<< 24;
3028 tex_inst
->eot
= true;
3029 tex_inst
->dst
= ibld
.null_reg_ud();
3030 tex_inst
->size_written
= 0;
3031 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
3033 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
3034 * flag and submit a header together with the sampler message as required
3037 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
3042 fs_visitor::opt_register_renaming()
3044 bool progress
= false;
3047 unsigned remap
[alloc
.count
];
3048 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
3050 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3051 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
3053 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
3054 inst
->opcode
== BRW_OPCODE_WHILE
) {
3058 /* Rewrite instruction sources. */
3059 for (int i
= 0; i
< inst
->sources
; i
++) {
3060 if (inst
->src
[i
].file
== VGRF
&&
3061 remap
[inst
->src
[i
].nr
] != ~0u &&
3062 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
3063 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
3068 const unsigned dst
= inst
->dst
.nr
;
3071 inst
->dst
.file
== VGRF
&&
3072 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
3073 !inst
->is_partial_write()) {
3074 if (remap
[dst
] == ~0u) {
3077 remap
[dst
] = alloc
.allocate(regs_written(inst
));
3078 inst
->dst
.nr
= remap
[dst
];
3081 } else if (inst
->dst
.file
== VGRF
&&
3082 remap
[dst
] != ~0u &&
3083 remap
[dst
] != dst
) {
3084 inst
->dst
.nr
= remap
[dst
];
3090 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
3091 DEPENDENCY_VARIABLES
);
3093 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3094 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3095 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3104 * Remove redundant or useless discard jumps.
3106 * For example, we can eliminate jumps in the following sequence:
3108 * discard-jump (redundant with the next jump)
3109 * discard-jump (useless; jumps to the next instruction)
3113 fs_visitor::opt_redundant_discard_jumps()
3115 bool progress
= false;
3117 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3119 fs_inst
*placeholder_halt
= NULL
;
3120 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3121 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3122 placeholder_halt
= inst
;
3127 if (!placeholder_halt
)
3130 /* Delete any HALTs immediately before the placeholder halt. */
3131 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3132 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3133 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3134 prev
->remove(last_bblock
);
3139 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3145 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3146 * from \p r.offset which overlaps the region starting at \p s.offset and
3147 * spanning \p ds bytes.
3149 static inline unsigned
3150 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3152 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3153 const int shift
= rel_offset
/ REG_SIZE
;
3154 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3155 assert(reg_space(r
) == reg_space(s
) &&
3156 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3157 return ((1 << n
) - 1) << shift
;
3161 fs_visitor::compute_to_mrf()
3163 bool progress
= false;
3166 /* No MRFs on Gen >= 7. */
3167 if (devinfo
->gen
>= 7)
3170 const fs_live_variables
&live
= live_analysis
.require();
3172 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3176 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3177 inst
->is_partial_write() ||
3178 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3179 inst
->dst
.type
!= inst
->src
[0].type
||
3180 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3181 !inst
->src
[0].is_contiguous() ||
3182 inst
->src
[0].offset
% REG_SIZE
!= 0)
3185 /* Can't compute-to-MRF this GRF if someone else was going to
3188 if (live
.vgrf_end
[inst
->src
[0].nr
] > ip
)
3191 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3192 * things that computed the value of all GRFs of the source region. The
3193 * regs_left bitset keeps track of the registers we haven't yet found a
3194 * generating instruction for.
3196 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3198 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3199 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3200 inst
->src
[0], inst
->size_read(0))) {
3201 /* Found the last thing to write our reg we want to turn
3202 * into a compute-to-MRF.
3205 /* If this one instruction didn't populate all the
3206 * channels, bail. We might be able to rewrite everything
3207 * that writes that reg, but it would require smarter
3210 if (scan_inst
->is_partial_write())
3213 /* Handling things not fully contained in the source of the copy
3214 * would need us to understand coalescing out more than one MOV at
3217 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3218 inst
->src
[0], inst
->size_read(0)))
3221 /* SEND instructions can't have MRF as a destination. */
3222 if (scan_inst
->mlen
)
3225 if (devinfo
->gen
== 6) {
3226 /* gen6 math instructions must have the destination be
3227 * GRF, so no compute-to-MRF for them.
3229 if (scan_inst
->is_math()) {
3234 /* Clear the bits for any registers this instruction overwrites. */
3235 regs_left
&= ~mask_relative_to(
3236 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3241 /* We don't handle control flow here. Most computation of
3242 * values that end up in MRFs are shortly before the MRF
3245 if (block
->start() == scan_inst
)
3248 /* You can't read from an MRF, so if someone else reads our
3249 * MRF's source GRF that we wanted to rewrite, that stops us.
3251 bool interfered
= false;
3252 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3253 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3254 inst
->src
[0], inst
->size_read(0))) {
3261 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3262 inst
->dst
, inst
->size_written
)) {
3263 /* If somebody else writes our MRF here, we can't
3264 * compute-to-MRF before that.
3269 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3270 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3271 inst
->dst
, inst
->size_written
)) {
3272 /* Found a SEND instruction, which means that there are
3273 * live values in MRFs from base_mrf to base_mrf +
3274 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3284 /* Found all generating instructions of our MRF's source value, so it
3285 * should be safe to rewrite them to point to the MRF directly.
3287 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3289 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3290 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3291 inst
->src
[0], inst
->size_read(0))) {
3292 /* Clear the bits for any registers this instruction overwrites. */
3293 regs_left
&= ~mask_relative_to(
3294 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3296 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3297 reg_offset(inst
->src
[0]);
3299 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3300 /* Apply the same address transformation done by the hardware
3301 * for COMPR4 MRF writes.
3303 assert(rel_offset
< 2 * REG_SIZE
);
3304 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3306 /* Clear the COMPR4 bit if the generating instruction is not
3309 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3310 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3313 /* Calculate the MRF number the result of this instruction is
3314 * ultimately written to.
3316 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3319 scan_inst
->dst
.file
= MRF
;
3320 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3321 scan_inst
->saturate
|= inst
->saturate
;
3328 inst
->remove(block
);
3333 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3339 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3340 * flow. We could probably do better here with some form of divergence
3344 fs_visitor::eliminate_find_live_channel()
3346 bool progress
= false;
3349 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3350 /* The optimization below assumes that channel zero is live on thread
3351 * dispatch, which may not be the case if the fixed function dispatches
3357 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3358 switch (inst
->opcode
) {
3364 case BRW_OPCODE_ENDIF
:
3365 case BRW_OPCODE_WHILE
:
3369 case FS_OPCODE_DISCARD_JUMP
:
3370 /* This can potentially make control flow non-uniform until the end
3375 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3377 inst
->opcode
= BRW_OPCODE_MOV
;
3378 inst
->src
[0] = brw_imm_ud(0u);
3380 inst
->force_writemask_all
= true;
3391 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
3397 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3398 * instructions to FS_OPCODE_REP_FB_WRITE.
3401 fs_visitor::emit_repclear_shader()
3403 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3405 int color_mrf
= base_mrf
+ 2;
3409 mov
= bld
.exec_all().group(4, 0)
3410 .MOV(brw_message_reg(color_mrf
),
3411 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3413 struct brw_reg reg
=
3414 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3415 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3416 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3418 mov
= bld
.exec_all().group(4, 0)
3419 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3422 fs_inst
*write
= NULL
;
3423 if (key
->nr_color_regions
== 1) {
3424 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3425 write
->saturate
= key
->clamp_fragment_color
;
3426 write
->base_mrf
= color_mrf
;
3428 write
->header_size
= 0;
3431 assume(key
->nr_color_regions
> 0);
3433 struct brw_reg header
=
3434 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3435 bld
.exec_all().group(16, 0)
3436 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3438 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3440 bld
.exec_all().group(1, 0)
3441 .MOV(component(header
, 2), brw_imm_ud(i
));
3444 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3445 write
->saturate
= key
->clamp_fragment_color
;
3446 write
->base_mrf
= base_mrf
;
3448 write
->header_size
= 2;
3453 write
->last_rt
= true;
3457 assign_constant_locations();
3458 assign_curb_setup();
3460 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3462 assert(mov
->src
[0].file
== FIXED_GRF
);
3463 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3470 * Walks through basic blocks, looking for repeated MRF writes and
3471 * removing the later ones.
3474 fs_visitor::remove_duplicate_mrf_writes()
3476 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3477 bool progress
= false;
3479 /* Need to update the MRF tracking for compressed instructions. */
3480 if (dispatch_width
>= 16)
3483 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3485 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3486 if (inst
->is_control_flow()) {
3487 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3490 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3491 inst
->dst
.file
== MRF
) {
3492 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3493 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3494 inst
->dst
.equals(prev_inst
->dst
) &&
3495 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3496 inst
->saturate
== prev_inst
->saturate
&&
3497 inst
->predicate
== prev_inst
->predicate
&&
3498 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3499 inst
->exec_size
== prev_inst
->exec_size
) {
3500 inst
->remove(block
);
3506 /* Clear out the last-write records for MRFs that were overwritten. */
3507 if (inst
->dst
.file
== MRF
) {
3508 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3511 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3512 /* Found a SEND instruction, which will include two or fewer
3513 * implied MRF writes. We could do better here.
3515 for (unsigned i
= 0; i
< inst
->implied_mrf_writes(); i
++) {
3516 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3520 /* Clear out any MRF move records whose sources got overwritten. */
3521 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3522 if (last_mrf_move
[i
] &&
3523 regions_overlap(inst
->dst
, inst
->size_written
,
3524 last_mrf_move
[i
]->src
[0],
3525 last_mrf_move
[i
]->size_read(0))) {
3526 last_mrf_move
[i
] = NULL
;
3530 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3531 inst
->dst
.file
== MRF
&&
3532 inst
->src
[0].file
!= ARF
&&
3533 !inst
->is_partial_write()) {
3534 last_mrf_move
[inst
->dst
.nr
] = inst
;
3539 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3545 * Rounding modes for conversion instructions are included for each
3546 * conversion, but right now it is a state. So once it is set,
3547 * we don't need to call it again for subsequent calls.
3549 * This is useful for vector/matrices conversions, as setting the
3550 * mode once is enough for the full vector/matrix
3553 fs_visitor::remove_extra_rounding_modes()
3555 bool progress
= false;
3556 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3558 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3559 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3560 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3561 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3563 base_mode
= BRW_RND_MODE_RTNE
;
3564 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3565 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3566 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3568 base_mode
= BRW_RND_MODE_RTZ
;
3570 foreach_block (block
, cfg
) {
3571 brw_rnd_mode prev_mode
= base_mode
;
3573 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3574 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3575 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3576 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3577 if (mode
== prev_mode
) {
3578 inst
->remove(block
);
3588 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3594 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3596 /* Clear the flag for registers that actually got read (as expected). */
3597 for (int i
= 0; i
< inst
->sources
; i
++) {
3599 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3600 grf
= inst
->src
[i
].nr
;
3605 if (grf
>= first_grf
&&
3606 grf
< first_grf
+ grf_len
) {
3607 deps
[grf
- first_grf
] = false;
3608 if (inst
->exec_size
== 16)
3609 deps
[grf
- first_grf
+ 1] = false;
3615 * Implements this workaround for the original 965:
3617 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3618 * check for post destination dependencies on this instruction, software
3619 * must ensure that there is no destination hazard for the case of ‘write
3620 * followed by a posted write’ shown in the following example.
3623 * 2. send r3.xy <rest of send instruction>
3626 * Due to no post-destination dependency check on the ‘send’, the above
3627 * code sequence could have two instructions (1 and 2) in flight at the
3628 * same time that both consider ‘r3’ as the target of their final writes.
3631 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3634 int write_len
= regs_written(inst
);
3635 int first_write_grf
= inst
->dst
.nr
;
3636 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3637 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3639 memset(needs_dep
, false, sizeof(needs_dep
));
3640 memset(needs_dep
, true, write_len
);
3642 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3644 /* Walk backwards looking for writes to registers we're writing which
3645 * aren't read since being written. If we hit the start of the program,
3646 * we assume that there are no outstanding dependencies on entry to the
3649 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3650 /* If we hit control flow, assume that there *are* outstanding
3651 * dependencies, and force their cleanup before our instruction.
3653 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3654 for (int i
= 0; i
< write_len
; i
++) {
3656 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3657 first_write_grf
+ i
);
3662 /* We insert our reads as late as possible on the assumption that any
3663 * instruction but a MOV that might have left us an outstanding
3664 * dependency has more latency than a MOV.
3666 if (scan_inst
->dst
.file
== VGRF
) {
3667 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3668 int reg
= scan_inst
->dst
.nr
+ i
;
3670 if (reg
>= first_write_grf
&&
3671 reg
< first_write_grf
+ write_len
&&
3672 needs_dep
[reg
- first_write_grf
]) {
3673 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3674 needs_dep
[reg
- first_write_grf
] = false;
3675 if (scan_inst
->exec_size
== 16)
3676 needs_dep
[reg
- first_write_grf
+ 1] = false;
3681 /* Clear the flag for registers that actually got read (as expected). */
3682 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3684 /* Continue the loop only if we haven't resolved all the dependencies */
3686 for (i
= 0; i
< write_len
; i
++) {
3696 * Implements this workaround for the original 965:
3698 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3699 * used as a destination register until after it has been sourced by an
3700 * instruction with a different destination register.
3703 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3705 int write_len
= regs_written(inst
);
3706 unsigned first_write_grf
= inst
->dst
.nr
;
3707 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3708 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3710 memset(needs_dep
, false, sizeof(needs_dep
));
3711 memset(needs_dep
, true, write_len
);
3712 /* Walk forwards looking for writes to registers we're writing which aren't
3713 * read before being written.
3715 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3716 /* If we hit control flow, force resolve all remaining dependencies. */
3717 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3718 for (int i
= 0; i
< write_len
; i
++) {
3720 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3721 first_write_grf
+ i
);
3726 /* Clear the flag for registers that actually got read (as expected). */
3727 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3729 /* We insert our reads as late as possible since they're reading the
3730 * result of a SEND, which has massive latency.
3732 if (scan_inst
->dst
.file
== VGRF
&&
3733 scan_inst
->dst
.nr
>= first_write_grf
&&
3734 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3735 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3736 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3738 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3741 /* Continue the loop only if we haven't resolved all the dependencies */
3743 for (i
= 0; i
< write_len
; i
++) {
3753 fs_visitor::insert_gen4_send_dependency_workarounds()
3755 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3758 bool progress
= false;
3760 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3761 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3762 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3763 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3769 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3773 * Turns the generic expression-style uniform pull constant load instruction
3774 * into a hardware-specific series of instructions for loading a pull
3777 * The expression style allows the CSE pass before this to optimize out
3778 * repeated loads from the same offset, and gives the pre-register-allocation
3779 * scheduling full flexibility, while the conversion to native instructions
3780 * allows the post-register-allocation scheduler the best information
3783 * Note that execution masking for setting up pull constant loads is special:
3784 * the channels that need to be written are unrelated to the current execution
3785 * mask, since a later instruction will use one of the result channels as a
3786 * source operand for all 8 or 16 of its channels.
3789 fs_visitor::lower_uniform_pull_constant_loads()
3791 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3792 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3795 if (devinfo
->gen
>= 7) {
3796 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3797 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3799 ubld
.group(8, 0).MOV(payload
,
3800 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3801 ubld
.group(1, 0).MOV(component(payload
, 2),
3802 brw_imm_ud(inst
->src
[1].ud
/ 16));
3804 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3805 inst
->src
[1] = payload
;
3806 inst
->header_size
= 1;
3809 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
3811 /* Before register allocation, we didn't tell the scheduler about the
3812 * MRF we use. We know it's safe to use this MRF because nothing
3813 * else does except for register spill/unspill, which generates and
3814 * uses its MRF within a single IR instruction.
3816 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3823 fs_visitor::lower_load_payload()
3825 bool progress
= false;
3827 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3828 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3831 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3832 assert(inst
->saturate
== false);
3833 fs_reg dst
= inst
->dst
;
3835 /* Get rid of COMPR4. We'll add it back in if we need it */
3836 if (dst
.file
== MRF
)
3837 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3839 const fs_builder
ibld(this, block
, inst
);
3840 const fs_builder ubld
= ibld
.exec_all();
3842 for (uint8_t i
= 0; i
< inst
->header_size
;) {
3843 /* Number of header GRFs to initialize at once with a single MOV
3847 (i
+ 1 < inst
->header_size
&& inst
->src
[i
].stride
== 1 &&
3848 inst
->src
[i
+ 1].equals(byte_offset(inst
->src
[i
], REG_SIZE
))) ?
3851 if (inst
->src
[i
].file
!= BAD_FILE
)
3852 ubld
.group(8 * n
, 0).MOV(retype(dst
, BRW_REGISTER_TYPE_UD
),
3853 retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
));
3855 dst
= byte_offset(dst
, n
* REG_SIZE
);
3859 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3860 inst
->exec_size
> 8) {
3861 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3862 * a straightforward copy. Instead, the result of the
3863 * LOAD_PAYLOAD is treated as interleaved and the first four
3864 * non-header sources are unpacked as:
3875 * This is used for gen <= 5 fb writes.
3877 assert(inst
->exec_size
== 16);
3878 assert(inst
->header_size
+ 4 <= inst
->sources
);
3879 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3880 if (inst
->src
[i
].file
!= BAD_FILE
) {
3881 if (devinfo
->has_compr4
) {
3882 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3883 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3884 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3886 /* Platform doesn't have COMPR4. We have to fake it */
3887 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3888 ibld
.quarter(0).MOV(mov_dst
, quarter(inst
->src
[i
], 0));
3890 ibld
.quarter(1).MOV(mov_dst
, quarter(inst
->src
[i
], 1));
3897 /* The loop above only ever incremented us through the first set
3898 * of 4 registers. However, thanks to the magic of COMPR4, we
3899 * actually wrote to the first 8 registers, so we need to take
3900 * that into account now.
3904 /* The COMPR4 code took care of the first 4 sources. We'll let
3905 * the regular path handle any remaining sources. Yes, we are
3906 * modifying the instruction but we're about to delete it so
3907 * this really doesn't hurt anything.
3909 inst
->header_size
+= 4;
3912 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3913 if (inst
->src
[i
].file
!= BAD_FILE
) {
3914 dst
.type
= inst
->src
[i
].type
;
3915 ibld
.MOV(dst
, inst
->src
[i
]);
3917 dst
.type
= BRW_REGISTER_TYPE_UD
;
3919 dst
= offset(dst
, ibld
, 1);
3922 inst
->remove(block
);
3927 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3933 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3935 const fs_builder
ibld(this, block
, inst
);
3937 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3938 if (inst
->src
[1].file
== IMM
&&
3939 (( ud
&& inst
->src
[1].ud
<= UINT16_MAX
) ||
3940 (!ud
&& inst
->src
[1].d
<= INT16_MAX
&& inst
->src
[1].d
>= INT16_MIN
))) {
3941 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3942 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3945 * If multiplying by an immediate value that fits in 16-bits, do a
3946 * single MUL instruction with that value in the proper location.
3948 if (devinfo
->gen
< 7) {
3949 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3950 ibld
.MOV(imm
, inst
->src
[1]);
3951 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3953 ibld
.MUL(inst
->dst
, inst
->src
[0],
3954 ud
? brw_imm_uw(inst
->src
[1].ud
)
3955 : brw_imm_w(inst
->src
[1].d
));
3958 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3959 * do 32-bit integer multiplication in one instruction, but instead
3960 * must do a sequence (which actually calculates a 64-bit result):
3962 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3963 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3964 * mov(8) g2<1>D acc0<8,8,1>D
3966 * But on Gen > 6, the ability to use second accumulator register
3967 * (acc1) for non-float data types was removed, preventing a simple
3968 * implementation in SIMD16. A 16-channel result can be calculated by
3969 * executing the three instructions twice in SIMD8, once with quarter
3970 * control of 1Q for the first eight channels and again with 2Q for
3971 * the second eight channels.
3973 * Which accumulator register is implicitly accessed (by AccWrEnable
3974 * for instance) is determined by the quarter control. Unfortunately
3975 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3976 * implicit accumulator access by an instruction with 2Q will access
3977 * acc1 regardless of whether the data type is usable in acc1.
3979 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3980 * integer data types.
3982 * Since we only want the low 32-bits of the result, we can do two
3983 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3984 * adjust the high result and add them (like the mach is doing):
3986 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3987 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3988 * shl(8) g9<1>D g8<8,8,1>D 16D
3989 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3991 * We avoid the shl instruction by realizing that we only want to add
3992 * the low 16-bits of the "high" result to the high 16-bits of the
3993 * "low" result and using proper regioning on the add:
3995 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3996 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3997 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3999 * Since it does not use the (single) accumulator register, we can
4000 * schedule multi-component multiplications much better.
4003 bool needs_mov
= false;
4004 fs_reg orig_dst
= inst
->dst
;
4006 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
4007 * reusing the original destination is impossible due to hardware
4008 * restrictions, source/destination overlap, or it being the null
4011 fs_reg low
= inst
->dst
;
4012 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
4013 regions_overlap(inst
->dst
, inst
->size_written
,
4014 inst
->src
[0], inst
->size_read(0)) ||
4015 regions_overlap(inst
->dst
, inst
->size_written
,
4016 inst
->src
[1], inst
->size_read(1)) ||
4017 inst
->dst
.stride
>= 4) {
4019 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
4023 /* Get a new VGRF but keep the same stride as inst->dst */
4024 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
4025 high
.stride
= inst
->dst
.stride
;
4026 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
4028 if (devinfo
->gen
>= 7) {
4029 if (inst
->src
[1].abs
)
4030 lower_src_modifiers(this, block
, inst
, 1);
4032 if (inst
->src
[1].file
== IMM
) {
4033 ibld
.MUL(low
, inst
->src
[0],
4034 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
4035 ibld
.MUL(high
, inst
->src
[0],
4036 brw_imm_uw(inst
->src
[1].ud
>> 16));
4038 ibld
.MUL(low
, inst
->src
[0],
4039 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4040 ibld
.MUL(high
, inst
->src
[0],
4041 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
4044 if (inst
->src
[0].abs
)
4045 lower_src_modifiers(this, block
, inst
, 0);
4047 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
4049 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
4053 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4054 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4055 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
4057 if (needs_mov
|| inst
->conditional_mod
)
4058 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
4063 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
4065 const fs_builder
ibld(this, block
, inst
);
4067 /* Considering two 64-bit integers ab and cd where each letter ab
4068 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
4069 * only need to provide the YZ part of the result. -------
4071 * Only BD needs to be 64 bits. For AD and BC we only care + AD
4072 * about the lower 32 bits (since they are part of the upper + BC
4073 * 32 bits of our result). AC is not needed since it starts + AC
4074 * on the 65th bit of the result. -------
4077 unsigned int q_regs
= regs_written(inst
);
4078 unsigned int d_regs
= (q_regs
+ 1) / 2;
4080 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
4081 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4082 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4084 /* Here we need the full 64 bit result for 32b * 32b. */
4085 if (devinfo
->has_integer_dword_mul
) {
4086 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4087 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4089 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4090 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4091 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4093 fs_inst
*mul
= ibld
.MUL(acc
,
4094 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4095 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4096 mul
->writes_accumulator
= true;
4098 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4099 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4100 ibld
.MOV(bd_low
, acc
);
4102 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4103 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4106 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4107 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4108 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4109 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4111 ibld
.ADD(ad
, ad
, bc
);
4112 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4113 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4115 ibld
.MOV(inst
->dst
, bd
);
4119 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4121 const fs_builder
ibld(this, block
, inst
);
4123 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4124 * High" instruction:
4126 * "An added preliminary mov is required for source modification on
4128 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4129 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4130 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4132 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4133 lower_src_modifiers(this, block
, inst
, 1);
4135 /* Should have been lowered to 8-wide. */
4136 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4137 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4138 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4139 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4141 if (devinfo
->gen
>= 8) {
4142 /* Until Gen8, integer multiplies read 32-bits from one source,
4143 * and 16-bits from the other, and relying on the MACH instruction
4144 * to generate the high bits of the result.
4146 * On Gen8, the multiply instruction does a full 32x32-bit
4147 * multiply, but in order to do a 64-bit multiply we can simulate
4148 * the previous behavior and then use a MACH instruction.
4150 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4151 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4152 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4153 mul
->src
[1].stride
*= 2;
4155 if (mul
->src
[1].file
== IMM
) {
4156 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4158 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4160 /* Among other things the quarter control bits influence which
4161 * accumulator register is used by the hardware for instructions
4162 * that access the accumulator implicitly (e.g. MACH). A
4163 * second-half instruction would normally map to acc1, which
4164 * doesn't exist on Gen7 and up (the hardware does emulate it for
4165 * floating-point instructions *only* by taking advantage of the
4166 * extra precision of acc0 not normally used for floating point
4169 * HSW and up are careful enough not to try to access an
4170 * accumulator register that doesn't exist, but on earlier Gen7
4171 * hardware we need to make sure that the quarter control bits are
4172 * zero to avoid non-deterministic behaviour and emit an extra MOV
4173 * to get the result masked correctly according to the current
4177 mach
->force_writemask_all
= true;
4178 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4179 ibld
.MOV(inst
->dst
, mach
->dst
);
4184 fs_visitor::lower_integer_multiplication()
4186 bool progress
= false;
4188 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4189 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4190 /* If the instruction is already in a form that does not need lowering,
4193 if (devinfo
->gen
>= 7) {
4194 if (type_sz(inst
->src
[1].type
) < 4 && type_sz(inst
->src
[0].type
) <= 4)
4197 if (type_sz(inst
->src
[0].type
) < 4 && type_sz(inst
->src
[1].type
) <= 4)
4201 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4202 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4203 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4204 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4205 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4206 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4207 lower_mul_qword_inst(inst
, block
);
4208 inst
->remove(block
);
4210 } else if (!inst
->dst
.is_accumulator() &&
4211 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4212 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4213 !devinfo
->has_integer_dword_mul
) {
4214 lower_mul_dword_inst(inst
, block
);
4215 inst
->remove(block
);
4218 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4219 lower_mulh_inst(inst
, block
);
4220 inst
->remove(block
);
4227 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4233 fs_visitor::lower_minmax()
4235 assert(devinfo
->gen
< 6);
4237 bool progress
= false;
4239 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4240 const fs_builder
ibld(this, block
, inst
);
4242 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4243 inst
->predicate
== BRW_PREDICATE_NONE
) {
4244 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4245 * the original SEL.L/GE instruction
4247 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4248 inst
->conditional_mod
);
4249 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4250 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4257 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
4263 fs_visitor::lower_sub_sat()
4265 bool progress
= false;
4267 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4268 const fs_builder
ibld(this, block
, inst
);
4270 if (inst
->opcode
== SHADER_OPCODE_USUB_SAT
||
4271 inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4272 /* The fundamental problem is the hardware performs source negation
4273 * at the bit width of the source. If the source is 0x80000000D, the
4274 * negation is 0x80000000D. As a result, subtractSaturate(0,
4275 * 0x80000000) will produce 0x80000000 instead of 0x7fffffff. There
4276 * are at least three ways to resolve this:
4278 * 1. Use the accumulator for the negated source. The accumulator is
4279 * 33 bits, so our source 0x80000000 is sign-extended to
4280 * 0x1800000000. The negation of which is 0x080000000. This
4281 * doesn't help for 64-bit integers (which are already bigger than
4282 * 33 bits). There are also only 8 accumulators, so SIMD16 or
4283 * SIMD32 instructions would have to be split into multiple SIMD8
4286 * 2. Use slightly different math. For any n-bit value x, we know (x
4287 * >> 1) != -(x >> 1). We can use this fact to only do
4288 * subtractions involving (x >> 1). subtractSaturate(a, b) ==
4289 * subtractSaturate(subtractSaturate(a, (b >> 1)), b - (b >> 1)).
4291 * 3. For unsigned sources, it is sufficient to replace the
4292 * subtractSaturate with (a > b) ? a - b : 0.
4294 * It may also be possible to use the SUBB instruction. This
4295 * implicitly writes the accumulator, so it could only be used in the
4296 * same situations as #1 above. It is further limited by only
4297 * allowing UD sources.
4299 if (inst
->exec_size
== 8 && inst
->src
[0].type
!= BRW_REGISTER_TYPE_Q
&&
4300 inst
->src
[0].type
!= BRW_REGISTER_TYPE_UQ
) {
4301 fs_reg
acc(ARF
, BRW_ARF_ACCUMULATOR
, inst
->src
[1].type
);
4303 ibld
.MOV(acc
, inst
->src
[1]);
4304 fs_inst
*add
= ibld
.ADD(inst
->dst
, acc
, inst
->src
[0]);
4305 add
->saturate
= true;
4306 add
->src
[0].negate
= true;
4307 } else if (inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4309 * dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp));
4311 fs_reg tmp1
= ibld
.vgrf(inst
->src
[0].type
);
4312 fs_reg tmp2
= ibld
.vgrf(inst
->src
[0].type
);
4313 fs_reg tmp3
= ibld
.vgrf(inst
->src
[0].type
);
4316 ibld
.SHR(tmp1
, inst
->src
[1], brw_imm_d(1));
4318 add
= ibld
.ADD(tmp2
, inst
->src
[1], tmp1
);
4319 add
->src
[1].negate
= true;
4321 add
= ibld
.ADD(tmp3
, inst
->src
[0], tmp1
);
4322 add
->src
[1].negate
= true;
4323 add
->saturate
= true;
4325 add
= ibld
.ADD(inst
->dst
, tmp3
, tmp2
);
4326 add
->src
[1].negate
= true;
4327 add
->saturate
= true;
4329 /* a > b ? a - b : 0 */
4330 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4333 fs_inst
*add
= ibld
.ADD(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4334 add
->src
[1].negate
= !add
->src
[1].negate
;
4336 ibld
.SEL(inst
->dst
, inst
->dst
, brw_imm_ud(0))
4337 ->predicate
= BRW_PREDICATE_NORMAL
;
4340 inst
->remove(block
);
4346 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4352 * Get the mask of SIMD channels enabled during dispatch and not yet disabled
4353 * by discard. Due to the layout of the sample mask in the fragment shader
4354 * thread payload, \p bld is required to have a dispatch_width() not greater
4355 * than 16 for fragment shaders.
4358 sample_mask_reg(const fs_builder
&bld
)
4360 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
4362 if (v
->stage
!= MESA_SHADER_FRAGMENT
) {
4363 return brw_imm_ud(0xffffffff);
4364 } else if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
4365 assert(bld
.dispatch_width() <= 16);
4366 return brw_flag_subreg(sample_mask_flag_subreg(v
) + bld
.group() / 16);
4368 assert(v
->devinfo
->gen
>= 6 && bld
.dispatch_width() <= 16);
4369 return retype(brw_vec1_grf((bld
.group() >= 16 ? 2 : 1), 7),
4370 BRW_REGISTER_TYPE_UW
);
4375 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4376 fs_reg
*dst
, fs_reg color
, unsigned components
)
4378 if (key
->clamp_fragment_color
) {
4379 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4380 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4382 for (unsigned i
= 0; i
< components
; i
++)
4384 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4389 for (unsigned i
= 0; i
< components
; i
++)
4390 dst
[i
] = offset(color
, bld
, i
);
4394 brw_fb_write_msg_control(const fs_inst
*inst
,
4395 const struct brw_wm_prog_data
*prog_data
)
4399 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4400 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4401 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4402 } else if (prog_data
->dual_src_blend
) {
4403 assert(inst
->exec_size
== 8);
4405 if (inst
->group
% 16 == 0)
4406 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4407 else if (inst
->group
% 16 == 8)
4408 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4410 unreachable("Invalid dual-source FB write instruction group");
4412 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4414 if (inst
->exec_size
== 16)
4415 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4416 else if (inst
->exec_size
== 8)
4417 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4419 unreachable("Invalid FB write execution size");
4426 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4427 const struct brw_wm_prog_data
*prog_data
,
4428 const brw_wm_prog_key
*key
,
4429 const fs_visitor::thread_payload
&payload
)
4431 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4432 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4433 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4434 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4435 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4436 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4437 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4438 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4439 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4440 const unsigned components
=
4441 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4443 assert(inst
->target
!= 0 || src0_alpha
.file
== BAD_FILE
);
4445 /* We can potentially have a message length of up to 15, so we have to set
4446 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4449 int header_size
= 2, payload_header_size
;
4450 unsigned length
= 0;
4452 if (devinfo
->gen
< 6) {
4453 /* TODO: Support SIMD32 on gen4-5 */
4454 assert(bld
.group() < 16);
4456 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4457 * an implied MOV from g0,g1 to the start of the message. The MOV from
4458 * g0 is handled by the hardware and the MOV from g1 is provided by the
4459 * generator. This is required because, on gen4-5, the generator may
4460 * generate two write messages with different message lengths in order
4461 * to handle AA data properly.
4463 * Also, since the pixel mask goes in the g0 portion of the message and
4464 * since render target writes are the last thing in the shader, we write
4465 * the pixel mask directly into g0 and it will get copied as part of the
4468 if (prog_data
->uses_kill
) {
4469 bld
.exec_all().group(1, 0)
4470 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4471 sample_mask_reg(bld
));
4474 assert(length
== 0);
4476 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4477 prog_data
->uses_kill
) ||
4478 (devinfo
->gen
< 11 &&
4479 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4480 /* From the Sandy Bridge PRM, volume 4, page 198:
4482 * "Dispatched Pixel Enables. One bit per pixel indicating
4483 * which pixels were originally enabled when the thread was
4484 * dispatched. This field is only required for the end-of-
4485 * thread message and on all dual-source messages."
4487 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4489 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4490 if (bld
.group() < 16) {
4491 /* The header starts off as g0 and g1 for the first half */
4492 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4493 BRW_REGISTER_TYPE_UD
));
4495 /* The header starts off as g0 and g2 for the second half */
4496 assert(bld
.group() < 32);
4497 const fs_reg header_sources
[2] = {
4498 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4499 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4501 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4503 /* Gen12 will require additional fix-ups if we ever hit this path. */
4504 assert(devinfo
->gen
< 12);
4507 uint32_t g00_bits
= 0;
4509 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4512 if (src0_alpha
.file
!= BAD_FILE
)
4513 g00_bits
|= 1 << 11;
4515 /* Set computes stencil to render target */
4516 if (prog_data
->computed_stencil
)
4517 g00_bits
|= 1 << 14;
4520 /* OR extra bits into g0.0 */
4521 ubld
.group(1, 0).OR(component(header
, 0),
4522 retype(brw_vec1_grf(0, 0),
4523 BRW_REGISTER_TYPE_UD
),
4524 brw_imm_ud(g00_bits
));
4527 /* Set the render target index for choosing BLEND_STATE. */
4528 if (inst
->target
> 0) {
4529 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4532 if (prog_data
->uses_kill
) {
4533 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4534 BRW_REGISTER_TYPE_UW
),
4535 sample_mask_reg(bld
));
4538 assert(length
== 0);
4539 sources
[0] = header
;
4540 sources
[1] = horiz_offset(header
, 8);
4543 assert(length
== 0 || length
== 2);
4544 header_size
= length
;
4546 if (payload
.aa_dest_stencil_reg
[0]) {
4547 assert(inst
->group
< 16);
4548 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4549 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4550 .MOV(sources
[length
],
4551 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4555 if (src0_alpha
.file
!= BAD_FILE
) {
4556 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4557 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4558 .annotate("FB write src0 alpha");
4559 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4560 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4561 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4566 if (sample_mask
.file
!= BAD_FILE
) {
4567 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4568 BRW_REGISTER_TYPE_UD
);
4570 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4571 * relevant. Since it's unsigned single words one vgrf is always
4572 * 16-wide, but only the lower or higher 8 channels will be used by the
4573 * hardware when doing a SIMD8 write depending on whether we have
4574 * selected the subspans for the first or second half respectively.
4576 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4577 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4578 sample_mask
.stride
*= 2;
4580 bld
.exec_all().annotate("FB write oMask")
4581 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4587 payload_header_size
= length
;
4589 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4592 if (color1
.file
!= BAD_FILE
) {
4593 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4597 if (src_depth
.file
!= BAD_FILE
) {
4598 sources
[length
] = src_depth
;
4602 if (dst_depth
.file
!= BAD_FILE
) {
4603 sources
[length
] = dst_depth
;
4607 if (src_stencil
.file
!= BAD_FILE
) {
4608 assert(devinfo
->gen
>= 9);
4609 assert(bld
.dispatch_width() == 8);
4611 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4612 * available on gen9+. As such it's impossible to have both enabled at the
4613 * same time and therefore length cannot overrun the array.
4615 assert(length
< 15);
4617 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4618 bld
.exec_all().annotate("FB write OS")
4619 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4620 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4625 if (devinfo
->gen
>= 7) {
4626 /* Send from the GRF */
4627 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4628 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4629 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4630 load
->dst
= payload
;
4632 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4633 uint32_t ex_desc
= 0;
4636 (inst
->group
/ 16) << 11 | /* rt slot group */
4637 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4638 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4639 inst
->last_rt
, false);
4641 if (devinfo
->gen
>= 11) {
4642 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4643 * in the extended message descriptor, in lieu of using a header.
4645 ex_desc
= inst
->target
<< 12 | (src0_alpha
.file
!= BAD_FILE
) << 15;
4647 if (key
->nr_color_regions
== 0)
4648 ex_desc
|= 1 << 20; /* Null Render Target */
4651 inst
->opcode
= SHADER_OPCODE_SEND
;
4652 inst
->resize_sources(3);
4653 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4654 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4655 inst
->src
[1] = brw_imm_ud(ex_desc
);
4656 inst
->src
[2] = payload
;
4657 inst
->mlen
= regs_written(load
);
4659 inst
->header_size
= header_size
;
4660 inst
->check_tdr
= true;
4661 inst
->send_has_side_effects
= true;
4663 /* Send from the MRF */
4664 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4665 sources
, length
, payload_header_size
);
4667 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4668 * will do this for us if we just give it a COMPR4 destination.
4670 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4671 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4673 if (devinfo
->gen
< 6) {
4674 /* Set up src[0] for the implied MOV from grf0-1 */
4675 inst
->resize_sources(1);
4676 inst
->src
[0] = brw_vec8_grf(0, 0);
4678 inst
->resize_sources(0);
4681 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4682 inst
->mlen
= regs_written(load
);
4683 inst
->header_size
= header_size
;
4688 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4690 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4691 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4692 const unsigned length
= 2;
4693 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4695 if (bld
.group() < 16) {
4696 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4697 BRW_REGISTER_TYPE_UD
));
4699 assert(bld
.group() < 32);
4700 const fs_reg header_sources
[] = {
4701 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4702 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4704 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4706 if (devinfo
->gen
>= 12) {
4707 /* On Gen12 the Viewport and Render Target Array Index fields (AKA
4708 * Poly 0 Info) are provided in r1.1 instead of r0.0, and the render
4709 * target message header format was updated accordingly -- However
4710 * the updated format only works for the lower 16 channels in a
4711 * SIMD32 thread, since the higher 16 channels want the subspan data
4712 * from r2 instead of r1, so we need to copy over the contents of
4713 * r1.1 in order to fix things up.
4715 ubld
.group(1, 0).MOV(component(header
, 9),
4716 retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_UD
));
4720 inst
->resize_sources(1);
4721 inst
->src
[0] = header
;
4722 inst
->opcode
= FS_OPCODE_FB_READ
;
4723 inst
->mlen
= length
;
4724 inst
->header_size
= length
;
4728 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4729 const fs_reg
&coordinate
,
4730 const fs_reg
&shadow_c
,
4731 const fs_reg
&lod
, const fs_reg
&lod2
,
4732 const fs_reg
&surface
,
4733 const fs_reg
&sampler
,
4734 unsigned coord_components
,
4735 unsigned grad_components
)
4737 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4738 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4739 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4740 fs_reg msg_end
= msg_begin
;
4743 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4745 for (unsigned i
= 0; i
< coord_components
; i
++)
4746 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4747 offset(coordinate
, bld
, i
));
4749 msg_end
= offset(msg_end
, bld
, coord_components
);
4751 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4752 * require all three components to be present and zero if they are unused.
4754 if (coord_components
> 0 &&
4755 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4756 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4757 for (unsigned i
= coord_components
; i
< 3; i
++)
4758 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4760 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4763 if (op
== SHADER_OPCODE_TXD
) {
4764 /* TXD unsupported in SIMD16 mode. */
4765 assert(bld
.dispatch_width() == 8);
4767 /* the slots for u and v are always present, but r is optional */
4768 if (coord_components
< 2)
4769 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4772 * dPdx = dudx, dvdx, drdx
4773 * dPdy = dudy, dvdy, drdy
4775 * 1-arg: Does not exist.
4777 * 2-arg: dudx dvdx dudy dvdy
4778 * dPdx.x dPdx.y dPdy.x dPdy.y
4781 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4782 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4783 * m5 m6 m7 m8 m9 m10
4785 for (unsigned i
= 0; i
< grad_components
; i
++)
4786 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4788 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4790 for (unsigned i
= 0; i
< grad_components
; i
++)
4791 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4793 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4797 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4798 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4800 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4801 bld
.dispatch_width() == 16);
4803 const brw_reg_type type
=
4804 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4805 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4806 bld
.MOV(retype(msg_end
, type
), lod
);
4807 msg_end
= offset(msg_end
, bld
, 1);
4810 if (shadow_c
.file
!= BAD_FILE
) {
4811 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4812 /* There's no plain shadow compare message, so we use shadow
4813 * compare with a bias of 0.0.
4815 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4816 msg_end
= offset(msg_end
, bld
, 1);
4819 bld
.MOV(msg_end
, shadow_c
);
4820 msg_end
= offset(msg_end
, bld
, 1);
4824 inst
->src
[0] = reg_undef
;
4825 inst
->src
[1] = surface
;
4826 inst
->src
[2] = sampler
;
4827 inst
->resize_sources(3);
4828 inst
->base_mrf
= msg_begin
.nr
;
4829 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4830 inst
->header_size
= 1;
4834 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4835 const fs_reg
&coordinate
,
4836 const fs_reg
&shadow_c
,
4837 const fs_reg
&lod
, const fs_reg
&lod2
,
4838 const fs_reg
&sample_index
,
4839 const fs_reg
&surface
,
4840 const fs_reg
&sampler
,
4841 unsigned coord_components
,
4842 unsigned grad_components
)
4844 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4845 fs_reg msg_coords
= message
;
4846 unsigned header_size
= 0;
4848 if (inst
->offset
!= 0) {
4849 /* The offsets set up by the visitor are in the m1 header, so we can't
4856 for (unsigned i
= 0; i
< coord_components
; i
++)
4857 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4858 offset(coordinate
, bld
, i
));
4860 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4861 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4863 if (shadow_c
.file
!= BAD_FILE
) {
4864 fs_reg msg_shadow
= msg_lod
;
4865 bld
.MOV(msg_shadow
, shadow_c
);
4866 msg_lod
= offset(msg_shadow
, bld
, 1);
4871 case SHADER_OPCODE_TXL
:
4873 bld
.MOV(msg_lod
, lod
);
4874 msg_end
= offset(msg_lod
, bld
, 1);
4876 case SHADER_OPCODE_TXD
:
4879 * dPdx = dudx, dvdx, drdx
4880 * dPdy = dudy, dvdy, drdy
4882 * Load up these values:
4883 * - dudx dudy dvdx dvdy drdx drdy
4884 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4887 for (unsigned i
= 0; i
< grad_components
; i
++) {
4888 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4889 msg_end
= offset(msg_end
, bld
, 1);
4891 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4892 msg_end
= offset(msg_end
, bld
, 1);
4895 case SHADER_OPCODE_TXS
:
4896 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4897 bld
.MOV(msg_lod
, lod
);
4898 msg_end
= offset(msg_lod
, bld
, 1);
4900 case SHADER_OPCODE_TXF
:
4901 msg_lod
= offset(msg_coords
, bld
, 3);
4902 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4903 msg_end
= offset(msg_lod
, bld
, 1);
4905 case SHADER_OPCODE_TXF_CMS
:
4906 msg_lod
= offset(msg_coords
, bld
, 3);
4908 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4910 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4911 msg_end
= offset(msg_lod
, bld
, 2);
4918 inst
->src
[0] = reg_undef
;
4919 inst
->src
[1] = surface
;
4920 inst
->src
[2] = sampler
;
4921 inst
->resize_sources(3);
4922 inst
->base_mrf
= message
.nr
;
4923 inst
->mlen
= msg_end
.nr
- message
.nr
;
4924 inst
->header_size
= header_size
;
4926 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4927 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4931 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4933 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4936 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4940 sampler_msg_type(const gen_device_info
*devinfo
,
4941 opcode opcode
, bool shadow_compare
)
4943 assert(devinfo
->gen
>= 5);
4945 case SHADER_OPCODE_TEX
:
4946 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4947 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4949 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4950 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4951 case SHADER_OPCODE_TXL
:
4952 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4953 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4954 case SHADER_OPCODE_TXL_LZ
:
4955 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4956 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4957 case SHADER_OPCODE_TXS
:
4958 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4959 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4960 case SHADER_OPCODE_TXD
:
4961 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4962 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4963 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4964 case SHADER_OPCODE_TXF
:
4965 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4966 case SHADER_OPCODE_TXF_LZ
:
4967 assert(devinfo
->gen
>= 9);
4968 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4969 case SHADER_OPCODE_TXF_CMS_W
:
4970 assert(devinfo
->gen
>= 9);
4971 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4972 case SHADER_OPCODE_TXF_CMS
:
4973 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4974 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4975 case SHADER_OPCODE_TXF_UMS
:
4976 assert(devinfo
->gen
>= 7);
4977 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4978 case SHADER_OPCODE_TXF_MCS
:
4979 assert(devinfo
->gen
>= 7);
4980 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4981 case SHADER_OPCODE_LOD
:
4982 return GEN5_SAMPLER_MESSAGE_LOD
;
4983 case SHADER_OPCODE_TG4
:
4984 assert(devinfo
->gen
>= 7);
4985 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4986 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4988 case SHADER_OPCODE_TG4_OFFSET
:
4989 assert(devinfo
->gen
>= 7);
4990 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4991 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4992 case SHADER_OPCODE_SAMPLEINFO
:
4993 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4995 unreachable("not reached");
5000 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
5001 const fs_reg
&coordinate
,
5002 const fs_reg
&shadow_c
,
5003 fs_reg lod
, const fs_reg
&lod2
,
5004 const fs_reg
&min_lod
,
5005 const fs_reg
&sample_index
,
5007 const fs_reg
&surface
,
5008 const fs_reg
&sampler
,
5009 const fs_reg
&surface_handle
,
5010 const fs_reg
&sampler_handle
,
5011 const fs_reg
&tg4_offset
,
5012 unsigned coord_components
,
5013 unsigned grad_components
)
5015 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5016 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
5017 unsigned reg_width
= bld
.dispatch_width() / 8;
5018 unsigned header_size
= 0, length
= 0;
5019 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
5020 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
5021 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
5023 /* We must have exactly one of surface/sampler and surface/sampler_handle */
5024 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5025 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
5027 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
5028 inst
->offset
!= 0 || inst
->eot
||
5029 op
== SHADER_OPCODE_SAMPLEINFO
||
5030 sampler_handle
.file
!= BAD_FILE
||
5031 is_high_sampler(devinfo
, sampler
)) {
5032 /* For general texture offsets (no txf workaround), we need a header to
5035 * TG4 needs to place its channel select in the header, for interaction
5036 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
5037 * larger sampler numbers we need to offset the Sampler State Pointer in
5040 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
5044 /* If we're requesting fewer than four channels worth of response,
5045 * and we have an explicit header, we need to set up the sampler
5046 * writemask. It's reversed from normal: 1 means "don't write".
5048 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
5049 assert(regs_written(inst
) % reg_width
== 0);
5050 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
5051 inst
->offset
|= mask
<< 12;
5054 /* Build the actual header */
5055 const fs_builder ubld
= bld
.exec_all().group(8, 0);
5056 const fs_builder ubld1
= ubld
.group(1, 0);
5057 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
5059 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
5060 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
5061 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
5062 /* The vertex and fragment stages have g0.2 set to 0, so
5063 * header0.2 is 0 when g0 is copied. Other stages may not, so we
5064 * must set it to 0 to avoid setting undesirable bits in the
5067 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
5070 if (sampler_handle
.file
!= BAD_FILE
) {
5071 /* Bindless sampler handles aren't relative to the sampler state
5072 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
5073 * Instead, it's an absolute pointer relative to dynamic state base
5076 * Sampler states are 16 bytes each and the pointer we give here has
5077 * to be 32-byte aligned. In order to avoid more indirect messages
5078 * than required, we assume that all bindless sampler states are
5079 * 32-byte aligned. This sacrifices a bit of general state base
5080 * address space but means we can do something more efficient in the
5083 ubld1
.MOV(component(header
, 3), sampler_handle
);
5084 } else if (is_high_sampler(devinfo
, sampler
)) {
5085 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
5086 assert(sampler
.ud
>= 16);
5087 const int sampler_state_size
= 16; /* 16 bytes */
5089 ubld1
.ADD(component(header
, 3),
5090 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5091 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
5093 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
5094 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
5095 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
5096 ubld1
.ADD(component(header
, 3),
5097 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5103 if (shadow_c
.file
!= BAD_FILE
) {
5104 bld
.MOV(sources
[length
], shadow_c
);
5108 bool coordinate_done
= false;
5110 /* Set up the LOD info */
5113 case SHADER_OPCODE_TXL
:
5114 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
5115 op
= SHADER_OPCODE_TXL_LZ
;
5118 bld
.MOV(sources
[length
], lod
);
5121 case SHADER_OPCODE_TXD
:
5122 /* TXD should have been lowered in SIMD16 mode. */
5123 assert(bld
.dispatch_width() == 8);
5125 /* Load dPdx and the coordinate together:
5126 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5128 for (unsigned i
= 0; i
< coord_components
; i
++) {
5129 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5131 /* For cube map array, the coordinate is (u,v,r,ai) but there are
5132 * only derivatives for (u, v, r).
5134 if (i
< grad_components
) {
5135 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
5136 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
5140 coordinate_done
= true;
5142 case SHADER_OPCODE_TXS
:
5143 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
5146 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5147 /* We need an LOD; just use 0 */
5148 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
5151 case SHADER_OPCODE_TXF
:
5152 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5153 * On Gen9 they are u, v, lod, r
5155 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
5157 if (devinfo
->gen
>= 9) {
5158 if (coord_components
>= 2) {
5159 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
5160 offset(coordinate
, bld
, 1));
5162 sources
[length
] = brw_imm_d(0);
5167 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
5168 op
= SHADER_OPCODE_TXF_LZ
;
5170 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
5174 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
5175 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5176 offset(coordinate
, bld
, i
));
5178 coordinate_done
= true;
5181 case SHADER_OPCODE_TXF_CMS
:
5182 case SHADER_OPCODE_TXF_CMS_W
:
5183 case SHADER_OPCODE_TXF_UMS
:
5184 case SHADER_OPCODE_TXF_MCS
:
5185 if (op
== SHADER_OPCODE_TXF_UMS
||
5186 op
== SHADER_OPCODE_TXF_CMS
||
5187 op
== SHADER_OPCODE_TXF_CMS_W
) {
5188 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
5192 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
5193 /* Data from the multisample control surface. */
5194 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
5197 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
5200 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
5201 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
5204 offset(mcs
, bld
, 1));
5209 /* There is no offsetting for this message; just copy in the integer
5210 * texture coordinates.
5212 for (unsigned i
= 0; i
< coord_components
; i
++)
5213 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5214 offset(coordinate
, bld
, i
));
5216 coordinate_done
= true;
5218 case SHADER_OPCODE_TG4_OFFSET
:
5219 /* More crazy intermixing */
5220 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5221 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5223 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5224 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5225 offset(tg4_offset
, bld
, i
));
5227 if (coord_components
== 3) /* r if present */
5228 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5230 coordinate_done
= true;
5236 /* Set up the coordinate (except for cases where it was done above) */
5237 if (!coordinate_done
) {
5238 for (unsigned i
= 0; i
< coord_components
; i
++)
5239 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5242 if (min_lod
.file
!= BAD_FILE
) {
5243 /* Account for all of the missing coordinate sources */
5244 length
+= 4 - coord_components
;
5245 if (op
== SHADER_OPCODE_TXD
)
5246 length
+= (3 - grad_components
) * 2;
5248 bld
.MOV(sources
[length
++], min_lod
);
5253 mlen
= length
* reg_width
- header_size
;
5255 mlen
= length
* reg_width
;
5257 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5258 BRW_REGISTER_TYPE_F
);
5259 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5261 /* Generate the SEND. */
5262 inst
->opcode
= SHADER_OPCODE_SEND
;
5264 inst
->header_size
= header_size
;
5266 const unsigned msg_type
=
5267 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5268 const unsigned simd_mode
=
5269 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5270 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5272 uint32_t base_binding_table_index
;
5274 case SHADER_OPCODE_TG4
:
5275 case SHADER_OPCODE_TG4_OFFSET
:
5276 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5278 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5279 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5282 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5286 inst
->sfid
= BRW_SFID_SAMPLER
;
5287 if (surface
.file
== IMM
&&
5288 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5289 inst
->desc
= brw_sampler_desc(devinfo
,
5290 surface
.ud
+ base_binding_table_index
,
5291 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5294 0 /* return_format unused on gen7+ */);
5295 inst
->src
[0] = brw_imm_ud(0);
5296 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5297 } else if (surface_handle
.file
!= BAD_FILE
) {
5298 /* Bindless surface */
5299 assert(devinfo
->gen
>= 9);
5300 inst
->desc
= brw_sampler_desc(devinfo
,
5302 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5305 0 /* return_format unused on gen7+ */);
5307 /* For bindless samplers, the entire address is included in the message
5308 * header so we can leave the portion in the message descriptor 0.
5310 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5311 inst
->src
[0] = brw_imm_ud(0);
5313 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5314 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5315 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5316 inst
->src
[0] = desc
;
5319 /* We assume that the driver provided the handle in the top 20 bits so
5320 * we can use the surface handle directly as the extended descriptor.
5322 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5324 /* Immediate portion of the descriptor */
5325 inst
->desc
= brw_sampler_desc(devinfo
,
5330 0 /* return_format unused on gen7+ */);
5331 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5332 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5333 if (surface
.equals(sampler
)) {
5334 /* This case is common in GL */
5335 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5337 if (sampler_handle
.file
!= BAD_FILE
) {
5338 ubld
.MOV(desc
, surface
);
5339 } else if (sampler
.file
== IMM
) {
5340 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5342 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5343 ubld
.OR(desc
, desc
, surface
);
5346 if (base_binding_table_index
)
5347 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5348 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5350 inst
->src
[0] = component(desc
, 0);
5351 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5354 inst
->src
[2] = src_payload
;
5355 inst
->resize_sources(3);
5358 /* EOT sampler messages don't make sense to split because it would
5359 * involve ending half of the thread early.
5361 assert(inst
->group
== 0);
5362 /* We need to use SENDC for EOT sampler messages */
5363 inst
->check_tdr
= true;
5364 inst
->send_has_side_effects
= true;
5367 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5368 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5372 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5374 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5375 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5376 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5377 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5378 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5379 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5380 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5381 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5382 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5383 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5384 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5385 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5386 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5387 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5388 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5389 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5390 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5392 if (devinfo
->gen
>= 7) {
5393 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5394 shadow_c
, lod
, lod2
, min_lod
,
5396 mcs
, surface
, sampler
,
5397 surface_handle
, sampler_handle
,
5399 coord_components
, grad_components
);
5400 } else if (devinfo
->gen
>= 5) {
5401 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5402 shadow_c
, lod
, lod2
, sample_index
,
5404 coord_components
, grad_components
);
5406 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5407 shadow_c
, lod
, lod2
,
5409 coord_components
, grad_components
);
5414 * Predicate the specified instruction on the sample mask.
5417 emit_predicate_on_sample_mask(const fs_builder
&bld
, fs_inst
*inst
)
5419 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
&&
5420 bld
.group() == inst
->group
&&
5421 bld
.dispatch_width() == inst
->exec_size
);
5423 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
5424 const fs_reg sample_mask
= sample_mask_reg(bld
);
5425 const unsigned subreg
= sample_mask_flag_subreg(v
);
5427 if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
5428 assert(sample_mask
.file
== ARF
&&
5429 sample_mask
.nr
== brw_flag_subreg(subreg
).nr
&&
5430 sample_mask
.subnr
== brw_flag_subreg(
5431 subreg
+ inst
->group
/ 16).subnr
);
5433 bld
.group(1, 0).exec_all()
5434 .MOV(brw_flag_subreg(subreg
+ inst
->group
/ 16), sample_mask
);
5437 if (inst
->predicate
) {
5438 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5439 assert(!inst
->predicate_inverse
);
5440 assert(inst
->flag_subreg
== 0);
5441 /* Combine the sample mask with the existing predicate by using a
5442 * vertical predication mode.
5444 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5446 inst
->flag_subreg
= subreg
;
5447 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5448 inst
->predicate_inverse
= false;
5453 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5455 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5457 /* Get the logical send arguments. */
5458 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5459 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5460 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5461 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5462 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5463 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5464 assert(arg
.file
== IMM
);
5466 /* We must have exactly one of surface and surface_handle */
5467 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5469 /* Calculate the total number of components of the payload. */
5470 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5471 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5473 const bool is_typed_access
=
5474 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5475 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5476 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5478 const bool is_surface_access
= is_typed_access
||
5479 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
||
5480 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
||
5481 inst
->opcode
== SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
;
5483 const bool is_stateless
=
5484 surface
.file
== IMM
&& (surface
.ud
== BRW_BTI_STATELESS
||
5485 surface
.ud
== GEN8_BTI_STATELESS_NON_COHERENT
);
5487 const bool has_side_effects
= inst
->has_side_effects();
5488 fs_reg sample_mask
= has_side_effects
? sample_mask_reg(bld
) :
5489 fs_reg(brw_imm_d(0xffff));
5491 /* From the BDW PRM Volume 7, page 147:
5493 * "For the Data Cache Data Port*, the header must be present for the
5494 * following message types: [...] Typed read/write/atomics"
5496 * Earlier generations have a similar wording. Because of this restriction
5497 * we don't attempt to implement sample masks via predication for such
5498 * messages prior to Gen9, since we have to provide a header anyway. On
5499 * Gen11+ the header has been removed so we can only use predication.
5501 * For all stateless A32 messages, we also need a header
5504 if ((devinfo
->gen
< 9 && is_typed_access
) || is_stateless
) {
5505 fs_builder ubld
= bld
.exec_all().group(8, 0);
5506 header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5507 ubld
.MOV(header
, brw_imm_d(0));
5509 /* Both the typed and scattered byte/dword A32 messages take a buffer
5510 * base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
5511 * MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
5512 * for more details.) This is conveniently where the HW places the
5513 * scratch surface base address.
5515 * From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
5517 * "When a thread becomes 'active' it is allocated a portion of
5518 * scratch space, sized according to PerThreadScratchSpace. The
5519 * starting location of each thread’s scratch space allocation,
5520 * ScratchSpaceOffset, is passed in the thread payload in
5521 * R0.5[31:10] and is specified as a 1KB-granular offset from the
5522 * GeneralStateBaseAddress. The computation of ScratchSpaceOffset
5523 * includes the starting address of the stage’s scratch space
5524 * allocation, as programmed by ScratchSpaceBasePointer."
5526 * The base address is passed in bits R0.5[31:10] and the bottom 10
5527 * bits of R0.5 are used for other things. Therefore, we have to
5528 * mask off the bottom 10 bits so that we don't get a garbage base
5531 ubld
.group(1, 0).AND(component(header
, 5),
5532 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
5533 brw_imm_ud(0xfffffc00));
5535 if (is_surface_access
)
5536 ubld
.group(1, 0).MOV(component(header
, 7), sample_mask
);
5538 const unsigned header_sz
= header
.file
!= BAD_FILE
? 1 : 0;
5540 fs_reg payload
, payload2
;
5541 unsigned mlen
, ex_mlen
= 0;
5542 if (devinfo
->gen
>= 9 &&
5543 (src
.file
== BAD_FILE
|| header
.file
== BAD_FILE
)) {
5544 /* We have split sends on gen9 and above */
5545 if (header
.file
== BAD_FILE
) {
5546 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5547 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5548 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5549 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5551 assert(src
.file
== BAD_FILE
);
5553 payload2
= bld
.move_to_vgrf(addr
, addr_sz
);
5555 ex_mlen
= addr_sz
* (inst
->exec_size
/ 8);
5558 /* Allocate space for the payload. */
5559 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5560 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5561 fs_reg
*const components
= new fs_reg
[sz
];
5564 /* Construct the payload. */
5565 if (header
.file
!= BAD_FILE
)
5566 components
[n
++] = header
;
5568 for (unsigned i
= 0; i
< addr_sz
; i
++)
5569 components
[n
++] = offset(addr
, bld
, i
);
5571 for (unsigned i
= 0; i
< src_sz
; i
++)
5572 components
[n
++] = offset(src
, bld
, i
);
5574 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5575 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5577 delete[] components
;
5580 /* Predicate the instruction on the sample mask if no header is
5583 if ((header
.file
== BAD_FILE
|| !is_surface_access
) &&
5584 sample_mask
.file
!= BAD_FILE
&& sample_mask
.file
!= IMM
)
5585 emit_predicate_on_sample_mask(bld
, inst
);
5588 switch (inst
->opcode
) {
5589 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5590 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5591 /* Byte scattered opcodes go through the normal data cache */
5592 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5595 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5596 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5597 sfid
= devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
5598 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
5599 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
5602 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5603 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5604 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5605 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5606 /* Untyped Surface messages go through the data cache but the SFID value
5607 * changed on Haswell.
5609 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5610 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5611 GEN7_SFID_DATAPORT_DATA_CACHE
);
5614 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5615 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5616 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5617 /* Typed surface messages go through the render cache on IVB and the
5618 * data cache on HSW+.
5620 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5621 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5622 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5626 unreachable("Unsupported surface opcode");
5630 switch (inst
->opcode
) {
5631 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5632 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5633 arg
.ud
, /* num_channels */
5637 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5638 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5639 arg
.ud
, /* num_channels */
5643 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5644 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5645 arg
.ud
, /* bit_size */
5649 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5650 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5651 arg
.ud
, /* bit_size */
5655 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5656 assert(arg
.ud
== 32); /* bit_size */
5657 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5661 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5662 assert(arg
.ud
== 32); /* bit_size */
5663 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5667 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5668 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5669 arg
.ud
, /* atomic_op */
5670 !inst
->dst
.is_null());
5673 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5674 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5675 arg
.ud
, /* atomic_op */
5676 !inst
->dst
.is_null());
5679 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5680 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5681 arg
.ud
, /* num_channels */
5685 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5686 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5687 arg
.ud
, /* num_channels */
5691 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5692 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5693 arg
.ud
, /* atomic_op */
5694 !inst
->dst
.is_null());
5698 unreachable("Unknown surface logical instruction");
5701 /* Update the original instruction. */
5702 inst
->opcode
= SHADER_OPCODE_SEND
;
5704 inst
->ex_mlen
= ex_mlen
;
5705 inst
->header_size
= header_sz
;
5706 inst
->send_has_side_effects
= has_side_effects
;
5707 inst
->send_is_volatile
= !has_side_effects
;
5709 /* Set up SFID and descriptors */
5712 if (surface
.file
== IMM
) {
5713 inst
->desc
|= surface
.ud
& 0xff;
5714 inst
->src
[0] = brw_imm_ud(0);
5715 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5716 } else if (surface_handle
.file
!= BAD_FILE
) {
5717 /* Bindless surface */
5718 assert(devinfo
->gen
>= 9);
5719 inst
->desc
|= GEN9_BTI_BINDLESS
;
5720 inst
->src
[0] = brw_imm_ud(0);
5722 /* We assume that the driver provided the handle in the top 20 bits so
5723 * we can use the surface handle directly as the extended descriptor.
5725 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5727 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5728 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5729 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5730 inst
->src
[0] = component(tmp
, 0);
5731 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5734 /* Finally, the payload */
5735 inst
->src
[2] = payload
;
5736 inst
->src
[3] = payload2
;
5738 inst
->resize_sources(4);
5742 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5744 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5746 const fs_reg
&addr
= inst
->src
[0];
5747 const fs_reg
&src
= inst
->src
[1];
5748 const unsigned src_comps
= inst
->components_read(1);
5749 assert(inst
->src
[2].file
== IMM
);
5750 const unsigned arg
= inst
->src
[2].ud
;
5751 const bool has_side_effects
= inst
->has_side_effects();
5753 /* If the surface message has side effects and we're a fragment shader, we
5754 * have to predicate with the sample mask to avoid helper invocations.
5756 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
)
5757 emit_predicate_on_sample_mask(bld
, inst
);
5759 fs_reg payload
, payload2
;
5760 unsigned mlen
, ex_mlen
= 0;
5761 if (devinfo
->gen
>= 9) {
5762 /* On Skylake and above, we have SENDS */
5763 mlen
= 2 * (inst
->exec_size
/ 8);
5764 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5765 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5766 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5767 BRW_REGISTER_TYPE_UD
);
5769 /* Add two because the address is 64-bit */
5770 const unsigned dwords
= 2 + src_comps
;
5771 mlen
= dwords
* (inst
->exec_size
/ 8);
5777 for (unsigned i
= 0; i
< src_comps
; i
++)
5778 sources
[1 + i
] = offset(src
, bld
, i
);
5780 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5781 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5785 switch (inst
->opcode
) {
5786 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5787 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5788 arg
, /* num_channels */
5792 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5793 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5794 arg
, /* num_channels */
5798 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5799 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5804 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5805 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5810 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5811 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5812 arg
, /* atomic_op */
5813 !inst
->dst
.is_null());
5816 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5817 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5818 arg
, /* atomic_op */
5819 !inst
->dst
.is_null());
5823 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5824 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5825 arg
, /* atomic_op */
5826 !inst
->dst
.is_null());
5830 unreachable("Unknown A64 logical instruction");
5833 /* Update the original instruction. */
5834 inst
->opcode
= SHADER_OPCODE_SEND
;
5836 inst
->ex_mlen
= ex_mlen
;
5837 inst
->header_size
= 0;
5838 inst
->send_has_side_effects
= has_side_effects
;
5839 inst
->send_is_volatile
= !has_side_effects
;
5841 /* Set up SFID and descriptors */
5842 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5844 inst
->resize_sources(4);
5845 inst
->src
[0] = brw_imm_ud(0); /* desc */
5846 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5847 inst
->src
[2] = payload
;
5848 inst
->src
[3] = payload2
;
5852 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5854 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5856 if (devinfo
->gen
>= 7) {
5857 fs_reg index
= inst
->src
[0];
5858 /* We are switching the instruction from an ALU-like instruction to a
5859 * send-from-grf instruction. Since sends can't handle strides or
5860 * source modifiers, we have to make a copy of the offset source.
5862 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5863 bld
.MOV(offset
, inst
->src
[1]);
5865 const unsigned simd_mode
=
5866 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5867 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5869 inst
->opcode
= SHADER_OPCODE_SEND
;
5870 inst
->mlen
= inst
->exec_size
/ 8;
5871 inst
->resize_sources(3);
5873 inst
->sfid
= BRW_SFID_SAMPLER
;
5874 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5875 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5877 if (index
.file
== IMM
) {
5878 inst
->desc
|= index
.ud
& 0xff;
5879 inst
->src
[0] = brw_imm_ud(0);
5881 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5882 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5883 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5884 inst
->src
[0] = component(tmp
, 0);
5886 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5887 inst
->src
[2] = offset
; /* payload */
5889 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5890 BRW_REGISTER_TYPE_UD
);
5892 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5894 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5895 inst
->resize_sources(1);
5896 inst
->base_mrf
= payload
.nr
;
5897 inst
->header_size
= 1;
5898 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5903 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5905 assert(bld
.shader
->devinfo
->gen
< 6);
5908 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5910 if (inst
->sources
> 1) {
5911 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5912 * "Message Payload":
5914 * "Operand0[7]. For the INT DIV functions, this operand is the
5917 * "Operand1[7]. For the INT DIV functions, this operand is the
5920 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5921 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5922 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5924 inst
->resize_sources(1);
5925 inst
->src
[0] = src0
;
5927 assert(inst
->exec_size
== 8);
5928 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5933 fs_visitor::lower_logical_sends()
5935 bool progress
= false;
5937 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5938 const fs_builder
ibld(this, block
, inst
);
5940 switch (inst
->opcode
) {
5941 case FS_OPCODE_FB_WRITE_LOGICAL
:
5942 assert(stage
== MESA_SHADER_FRAGMENT
);
5943 lower_fb_write_logical_send(ibld
, inst
,
5944 brw_wm_prog_data(prog_data
),
5945 (const brw_wm_prog_key
*)key
,
5949 case FS_OPCODE_FB_READ_LOGICAL
:
5950 lower_fb_read_logical_send(ibld
, inst
);
5953 case SHADER_OPCODE_TEX_LOGICAL
:
5954 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5957 case SHADER_OPCODE_TXD_LOGICAL
:
5958 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5961 case SHADER_OPCODE_TXF_LOGICAL
:
5962 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5965 case SHADER_OPCODE_TXL_LOGICAL
:
5966 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5969 case SHADER_OPCODE_TXS_LOGICAL
:
5970 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5973 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5974 lower_sampler_logical_send(ibld
, inst
,
5975 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5978 case FS_OPCODE_TXB_LOGICAL
:
5979 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5982 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5983 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5986 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5987 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5990 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5991 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5994 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5995 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5998 case SHADER_OPCODE_LOD_LOGICAL
:
5999 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
6002 case SHADER_OPCODE_TG4_LOGICAL
:
6003 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
6006 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6007 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
6010 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6011 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
6014 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6015 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6016 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6017 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6018 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6019 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6020 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6021 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6022 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6023 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6024 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6025 lower_surface_logical_send(ibld
, inst
);
6028 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6029 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6030 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6031 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6032 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6033 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6034 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6035 lower_a64_logical_send(ibld
, inst
);
6038 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6039 lower_varying_pull_constant_logical_send(ibld
, inst
);
6042 case SHADER_OPCODE_RCP
:
6043 case SHADER_OPCODE_RSQ
:
6044 case SHADER_OPCODE_SQRT
:
6045 case SHADER_OPCODE_EXP2
:
6046 case SHADER_OPCODE_LOG2
:
6047 case SHADER_OPCODE_SIN
:
6048 case SHADER_OPCODE_COS
:
6049 case SHADER_OPCODE_POW
:
6050 case SHADER_OPCODE_INT_QUOTIENT
:
6051 case SHADER_OPCODE_INT_REMAINDER
:
6052 /* The math opcodes are overloaded for the send-like and
6053 * expression-like instructions which seems kind of icky. Gen6+ has
6054 * a native (but rather quirky) MATH instruction so we don't need to
6055 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
6056 * logical instructions (which we can easily recognize because they
6057 * have mlen = 0) into send-like virtual instructions.
6059 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
6060 lower_math_logical_send(ibld
, inst
);
6075 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6081 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
6083 /* This opcode sometimes uses :W type on the source even if the operand is
6084 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
6086 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
6089 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
6092 for (int i
= 0; i
< inst
->sources
; i
++) {
6093 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
6101 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
6103 /* This opcode sometimes uses :W type on the destination even if the
6104 * destination is a :HF, because in gen7 there is no support for :HF, and
6107 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
6108 inst
->dst
.stride
== 1)
6111 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
6112 inst
->dst
.stride
!= 1)
6115 for (int i
= 0; i
< inst
->sources
; i
++) {
6116 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
6124 * Get the closest allowed SIMD width for instruction \p inst accounting for
6125 * some common regioning and execution control restrictions that apply to FPU
6126 * instructions. These restrictions don't necessarily have any relevance to
6127 * instructions not executed by the FPU pipeline like extended math, control
6128 * flow or send message instructions.
6130 * For virtual opcodes it's really up to the instruction -- In some cases
6131 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
6132 * instructions) it may simplify virtual instruction lowering if we can
6133 * enforce FPU-like regioning restrictions already on the virtual instruction,
6134 * in other cases (e.g. virtual send-like instructions) this may be
6135 * excessively restrictive.
6138 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
6139 const fs_inst
*inst
)
6141 /* Maximum execution size representable in the instruction controls. */
6142 unsigned max_width
= MIN2(32, inst
->exec_size
);
6144 /* According to the PRMs:
6145 * "A. In Direct Addressing mode, a source cannot span more than 2
6146 * adjacent GRF registers.
6147 * B. A destination cannot span more than 2 adjacent GRF registers."
6149 * Look for the source or destination with the largest register region
6150 * which is the one that is going to limit the overall execution size of
6151 * the instruction due to this rule.
6153 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6155 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6156 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
6158 /* Calculate the maximum execution size of the instruction based on the
6159 * factor by which it goes over the hardware limit of 2 GRFs.
6162 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
6164 /* According to the IVB PRMs:
6165 * "When destination spans two registers, the source MUST span two
6166 * registers. The exception to the above rule:
6168 * - When source is scalar, the source registers are not incremented.
6169 * - When source is packed integer Word and destination is packed
6170 * integer DWord, the source register is not incremented but the
6171 * source sub register is incremented."
6173 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
6174 * restrictions. The code below intentionally doesn't check whether the
6175 * destination type is integer because empirically the hardware doesn't
6176 * seem to care what the actual type is as long as it's dword-aligned.
6178 if (devinfo
->gen
< 8) {
6179 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6180 /* IVB implements DF scalars as <0;2,1> regions. */
6181 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
6182 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
6183 const bool is_packed_word_exception
=
6184 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
6185 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
6187 /* We check size_read(i) against size_written instead of REG_SIZE
6188 * because we want to properly handle SIMD32. In SIMD32, you can end
6189 * up with writes to 4 registers and a source that reads 2 registers
6190 * and we may still need to lower all the way to SIMD8 in that case.
6192 if (inst
->size_written
> REG_SIZE
&&
6193 inst
->size_read(i
) != 0 &&
6194 inst
->size_read(i
) < inst
->size_written
&&
6195 !is_scalar_exception
&& !is_packed_word_exception
) {
6196 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6197 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6202 if (devinfo
->gen
< 6) {
6203 /* From the G45 PRM, Volume 4 Page 361:
6205 * "Operand Alignment Rule: With the exceptions listed below, a
6206 * source/destination operand in general should be aligned to even
6207 * 256-bit physical register with a region size equal to two 256-bit
6208 * physical registers."
6210 * Normally we enforce this by allocating virtual registers to the
6211 * even-aligned class. But we need to handle payload registers.
6213 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6214 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
6215 inst
->size_read(i
) > REG_SIZE
) {
6216 max_width
= MIN2(max_width
, 8);
6221 /* From the IVB PRMs:
6222 * "When an instruction is SIMD32, the low 16 bits of the execution mask
6223 * are applied for both halves of the SIMD32 instruction. If different
6224 * execution mask channels are required, split the instruction into two
6225 * SIMD16 instructions."
6227 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6228 * 32-wide control flow support in hardware and will behave similarly.
6230 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6231 max_width
= MIN2(max_width
, 16);
6233 /* From the IVB PRMs (applies to HSW too):
6234 * "Instructions with condition modifiers must not use SIMD32."
6236 * From the BDW PRMs (applies to later hardware too):
6237 * "Ternary instruction with condition modifiers must not use SIMD32."
6239 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6240 max_width
= MIN2(max_width
, 16);
6242 /* From the IVB PRMs (applies to other devices that don't have the
6243 * gen_device_info::supports_simd16_3src flag set):
6244 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6245 * SIMD8 is not allowed for DF operations."
6247 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6248 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6250 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6251 * the 8-bit quarter of the execution mask signals specified in the
6252 * instruction control fields) for the second compressed half of any
6253 * single-precision instruction (for double-precision instructions
6254 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6255 * the EU will apply the wrong execution controls for the second
6256 * sequential GRF write if the number of channels per GRF is not exactly
6257 * eight in single-precision mode (or four in double-float mode).
6259 * In this situation we calculate the maximum size of the split
6260 * instructions so they only ever write to a single register.
6262 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6263 !inst
->force_writemask_all
) {
6264 const unsigned channels_per_grf
= inst
->exec_size
/
6265 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6266 const unsigned exec_type_size
= get_exec_type_size(inst
);
6267 assert(exec_type_size
);
6269 /* The hardware shifts exactly 8 channels per compressed half of the
6270 * instruction in single-precision mode and exactly 4 in double-precision.
6272 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6273 max_width
= MIN2(max_width
, channels_per_grf
);
6275 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6276 * because HW applies the same channel enable signals to both halves of
6277 * the compressed instruction which will be just wrong under
6278 * non-uniform control flow.
6280 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6281 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6282 max_width
= MIN2(max_width
, 4);
6285 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6288 * "No SIMD16 in mixed mode when destination is f32. Instruction
6289 * execution size must be no more than 8."
6291 * FIXME: the simulator doesn't seem to complain if we don't do this and
6292 * empirical testing with existing CTS tests show that they pass just fine
6293 * without implementing this, however, since our interpretation of the PRM
6294 * is that conversion MOVs between HF and F are still mixed-float
6295 * instructions (and therefore subject to this restriction) we decided to
6296 * split them to be safe. Might be useful to do additional investigation to
6297 * lift the restriction if we can ensure that it is safe though, since these
6298 * conversions are common when half-float types are involved since many
6299 * instructions do not support HF types and conversions from/to F are
6302 if (is_mixed_float_with_fp32_dst(inst
))
6303 max_width
= MIN2(max_width
, 8);
6305 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6308 * "No SIMD16 in mixed mode when destination is packed f16 for both
6309 * Align1 and Align16."
6311 if (is_mixed_float_with_packed_fp16_dst(inst
))
6312 max_width
= MIN2(max_width
, 8);
6314 /* Only power-of-two execution sizes are representable in the instruction
6317 return 1 << util_logbase2(max_width
);
6321 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6322 * various payload size restrictions that apply to sampler message
6325 * This is only intended to provide a maximum theoretical bound for the
6326 * execution size of the message based on the number of argument components
6327 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6328 * variant of the message can be used, though some messages may have
6329 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6330 * the message length to determine the exact SIMD width and argument count,
6331 * which makes a number of sampler message combinations impossible to
6335 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6336 const fs_inst
*inst
)
6338 /* If we have a min_lod parameter on anything other than a simple sample
6339 * message, it will push it over 5 arguments and we have to fall back to
6342 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6343 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6346 /* Calculate the number of coordinate components that have to be present
6347 * assuming that additional arguments follow the texel coordinates in the
6348 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6349 * need to pad to four or three components depending on the message,
6350 * pre-ILK we need to pad to at most three components.
6352 const unsigned req_coord_components
=
6353 (devinfo
->gen
>= 7 ||
6354 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6355 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6356 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6359 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6360 * variant of the TXL or TXF message.
6362 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6363 (inst
->opcode
== SHADER_OPCODE_TXL
||
6364 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6365 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6367 /* Calculate the total number of argument components that need to be passed
6368 * to the sampler unit.
6370 const unsigned num_payload_components
=
6371 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6372 req_coord_components
) +
6373 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6374 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6375 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6376 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6377 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6378 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6379 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6381 /* SIMD16 messages with more than five arguments exceed the maximum message
6382 * size supported by the sampler, regardless of whether a header is
6385 return MIN2(inst
->exec_size
,
6386 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6390 * Get the closest native SIMD width supported by the hardware for instruction
6391 * \p inst. The instruction will be left untouched by
6392 * fs_visitor::lower_simd_width() if the returned value is equal to the
6393 * original execution size.
6396 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6397 const fs_inst
*inst
)
6399 switch (inst
->opcode
) {
6400 case BRW_OPCODE_MOV
:
6401 case BRW_OPCODE_SEL
:
6402 case BRW_OPCODE_NOT
:
6403 case BRW_OPCODE_AND
:
6405 case BRW_OPCODE_XOR
:
6406 case BRW_OPCODE_SHR
:
6407 case BRW_OPCODE_SHL
:
6408 case BRW_OPCODE_ASR
:
6409 case BRW_OPCODE_ROR
:
6410 case BRW_OPCODE_ROL
:
6411 case BRW_OPCODE_CMPN
:
6412 case BRW_OPCODE_CSEL
:
6413 case BRW_OPCODE_F32TO16
:
6414 case BRW_OPCODE_F16TO32
:
6415 case BRW_OPCODE_BFREV
:
6416 case BRW_OPCODE_BFE
:
6417 case BRW_OPCODE_ADD
:
6418 case BRW_OPCODE_MUL
:
6419 case BRW_OPCODE_AVG
:
6420 case BRW_OPCODE_FRC
:
6421 case BRW_OPCODE_RNDU
:
6422 case BRW_OPCODE_RNDD
:
6423 case BRW_OPCODE_RNDE
:
6424 case BRW_OPCODE_RNDZ
:
6425 case BRW_OPCODE_LZD
:
6426 case BRW_OPCODE_FBH
:
6427 case BRW_OPCODE_FBL
:
6428 case BRW_OPCODE_CBIT
:
6429 case BRW_OPCODE_SAD2
:
6430 case BRW_OPCODE_MAD
:
6431 case BRW_OPCODE_LRP
:
6432 case FS_OPCODE_PACK
:
6433 case SHADER_OPCODE_SEL_EXEC
:
6434 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6435 return get_fpu_lowered_simd_width(devinfo
, inst
);
6437 case BRW_OPCODE_CMP
: {
6438 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6439 * when the destination is a GRF the dependency-clear bit on the flag
6440 * register is cleared early.
6442 * Suggested workarounds are to disable coissuing CMP instructions
6443 * or to split CMP(16) instructions into two CMP(8) instructions.
6445 * We choose to split into CMP(8) instructions since disabling
6446 * coissuing would affect CMP instructions not otherwise affected by
6449 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6450 !inst
->dst
.is_null() ? 8 : ~0);
6451 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6453 case BRW_OPCODE_BFI1
:
6454 case BRW_OPCODE_BFI2
:
6455 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6457 * "Force BFI instructions to be executed always in SIMD8."
6459 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6460 get_fpu_lowered_simd_width(devinfo
, inst
));
6463 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6464 return inst
->exec_size
;
6466 case SHADER_OPCODE_RCP
:
6467 case SHADER_OPCODE_RSQ
:
6468 case SHADER_OPCODE_SQRT
:
6469 case SHADER_OPCODE_EXP2
:
6470 case SHADER_OPCODE_LOG2
:
6471 case SHADER_OPCODE_SIN
:
6472 case SHADER_OPCODE_COS
: {
6473 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6474 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6476 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6477 return MIN2(8, inst
->exec_size
);
6478 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6479 return MIN2(8, inst
->exec_size
);
6480 return MIN2(16, inst
->exec_size
);
6483 case SHADER_OPCODE_POW
: {
6484 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6485 * to SIMD8 with half-float
6487 if (devinfo
->gen
< 7)
6488 return MIN2(8, inst
->exec_size
);
6489 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6490 return MIN2(8, inst
->exec_size
);
6491 return MIN2(16, inst
->exec_size
);
6494 case SHADER_OPCODE_USUB_SAT
:
6495 case SHADER_OPCODE_ISUB_SAT
:
6496 return get_fpu_lowered_simd_width(devinfo
, inst
);
6498 case SHADER_OPCODE_INT_QUOTIENT
:
6499 case SHADER_OPCODE_INT_REMAINDER
:
6500 /* Integer division is limited to SIMD8 on all generations. */
6501 return MIN2(8, inst
->exec_size
);
6503 case FS_OPCODE_LINTERP
:
6504 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6505 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6506 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6507 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6508 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6509 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6510 return MIN2(16, inst
->exec_size
);
6512 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6513 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6514 * message used to implement varying pull constant loads, so expand it
6515 * to SIMD16. An alternative with longer message payload length but
6516 * shorter return payload would be to use the SIMD8 sampler message that
6517 * takes (header, u, v, r) as parameters instead of (header, u).
6519 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6521 case FS_OPCODE_DDX_COARSE
:
6522 case FS_OPCODE_DDX_FINE
:
6523 case FS_OPCODE_DDY_COARSE
:
6524 case FS_OPCODE_DDY_FINE
:
6525 /* The implementation of this virtual opcode may require emitting
6526 * compressed Align16 instructions, which are severely limited on some
6529 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6530 * Region Restrictions):
6532 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6533 * and SIMD8 is not allowed for DF operations."
6535 * In this context, "DW operations" means "operations acting on 32-bit
6536 * values", so it includes operations on floats.
6538 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6539 * (Instruction Compression -> Rules and Restrictions):
6541 * "A compressed instruction must be in Align1 access mode. Align16
6542 * mode instructions cannot be compressed."
6544 * Similar text exists in the g45 PRM.
6546 * Empirically, compressed align16 instructions using odd register
6547 * numbers don't appear to work on Sandybridge either.
6549 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6550 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6551 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6553 case SHADER_OPCODE_MULH
:
6554 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6555 * is 8-wide on Gen7+.
6557 return (devinfo
->gen
>= 7 ? 8 :
6558 get_fpu_lowered_simd_width(devinfo
, inst
));
6560 case FS_OPCODE_FB_WRITE_LOGICAL
:
6561 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6564 assert(devinfo
->gen
!= 6 ||
6565 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6566 inst
->exec_size
== 8);
6567 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6568 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6569 8 : MIN2(16, inst
->exec_size
));
6571 case FS_OPCODE_FB_READ_LOGICAL
:
6572 return MIN2(16, inst
->exec_size
);
6574 case SHADER_OPCODE_TEX_LOGICAL
:
6575 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6576 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6577 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6578 case SHADER_OPCODE_LOD_LOGICAL
:
6579 case SHADER_OPCODE_TG4_LOGICAL
:
6580 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6581 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6582 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6583 return get_sampler_lowered_simd_width(devinfo
, inst
);
6585 case SHADER_OPCODE_TXD_LOGICAL
:
6586 /* TXD is unsupported in SIMD16 mode. */
6589 case SHADER_OPCODE_TXL_LOGICAL
:
6590 case FS_OPCODE_TXB_LOGICAL
:
6591 /* Only one execution size is representable pre-ILK depending on whether
6592 * the shadow reference argument is present.
6594 if (devinfo
->gen
== 4)
6595 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6597 return get_sampler_lowered_simd_width(devinfo
, inst
);
6599 case SHADER_OPCODE_TXF_LOGICAL
:
6600 case SHADER_OPCODE_TXS_LOGICAL
:
6601 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6602 * messages. Use SIMD16 instead.
6604 if (devinfo
->gen
== 4)
6607 return get_sampler_lowered_simd_width(devinfo
, inst
);
6609 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6610 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6611 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6614 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6615 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6616 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6617 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6618 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6619 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6620 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6621 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6622 return MIN2(16, inst
->exec_size
);
6624 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6625 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6626 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6627 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6628 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6630 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6631 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6632 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6635 case SHADER_OPCODE_URB_READ_SIMD8
:
6636 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6637 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6638 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6639 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6640 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6641 return MIN2(8, inst
->exec_size
);
6643 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6644 const unsigned swiz
= inst
->src
[1].ud
;
6645 return (is_uniform(inst
->src
[0]) ?
6646 get_fpu_lowered_simd_width(devinfo
, inst
) :
6647 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6648 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6649 get_fpu_lowered_simd_width(devinfo
, inst
));
6651 case SHADER_OPCODE_MOV_INDIRECT
: {
6652 /* From IVB and HSW PRMs:
6654 * "2.When the destination requires two registers and the sources are
6655 * indirect, the sources must use 1x1 regioning mode.
6657 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6658 * the EU decompression logic not handling VxH indirect addressing
6661 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6662 /* Prior to Broadwell, we only have 8 address subregisters. */
6663 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6664 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6668 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6669 const unsigned reg_count
=
6670 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6672 if (reg_count
> 2) {
6673 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6674 * can be easily lowered (which excludes headers and heterogeneous
6677 assert(!inst
->header_size
);
6678 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6679 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6680 inst
->src
[i
].file
== BAD_FILE
);
6682 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6684 return inst
->exec_size
;
6688 return inst
->exec_size
;
6693 * Return true if splitting out the group of channels of instruction \p inst
6694 * given by lbld.group() requires allocating a temporary for the i-th source
6695 * of the lowered instruction.
6698 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6700 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6701 (inst
->components_read(i
) == 1 &&
6702 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6703 (inst
->flags_written() &
6704 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6708 * Extract the data that would be consumed by the channel group given by
6709 * lbld.group() from the i-th source region of instruction \p inst and return
6710 * it as result in packed form.
6713 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6715 assert(lbld
.group() >= inst
->group
);
6717 /* Specified channel group from the source region. */
6718 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6720 if (needs_src_copy(lbld
, inst
, i
)) {
6721 /* Builder of the right width to perform the copy avoiding uninitialized
6722 * data if the lowered execution size is greater than the original
6723 * execution size of the instruction.
6725 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6726 inst
->exec_size
), 0);
6727 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6729 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6730 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6734 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6735 /* The source is invariant for all dispatch_width-wide groups of the
6738 return inst
->src
[i
];
6741 /* We can just point the lowered instruction at the right channel group
6742 * from the original region.
6749 * Return true if splitting out the group of channels of instruction \p inst
6750 * given by lbld.group() requires allocating a temporary for the destination
6751 * of the lowered instruction and copying the data back to the original
6752 * destination region.
6755 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6757 /* If the instruction writes more than one component we'll have to shuffle
6758 * the results of multiple lowered instructions in order to make sure that
6759 * they end up arranged correctly in the original destination region.
6761 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6764 /* If the lowered execution size is larger than the original the result of
6765 * the instruction won't fit in the original destination, so we'll have to
6766 * allocate a temporary in any case.
6768 if (lbld
.dispatch_width() > inst
->exec_size
)
6771 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6772 /* If we already made a copy of the source for other reasons there won't
6773 * be any overlap with the destination.
6775 if (needs_src_copy(lbld
, inst
, i
))
6778 /* In order to keep the logic simple we emit a copy whenever the
6779 * destination region doesn't exactly match an overlapping source, which
6780 * may point at the source and destination not being aligned group by
6781 * group which could cause one of the lowered instructions to overwrite
6782 * the data read from the same source by other lowered instructions.
6784 if (regions_overlap(inst
->dst
, inst
->size_written
,
6785 inst
->src
[i
], inst
->size_read(i
)) &&
6786 !inst
->dst
.equals(inst
->src
[i
]))
6794 * Insert data from a packed temporary into the channel group given by
6795 * lbld.group() of the destination region of instruction \p inst and return
6796 * the temporary as result. Any copy instructions that are required for
6797 * unzipping the previous value (in the case of partial writes) will be
6798 * inserted using \p lbld_before and any copy instructions required for
6799 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6802 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6805 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6806 assert(lbld_before
.group() == lbld_after
.group());
6807 assert(lbld_after
.group() >= inst
->group
);
6809 /* Specified channel group from the destination region. */
6810 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6811 const unsigned dst_size
= inst
->size_written
/
6812 inst
->dst
.component_size(inst
->exec_size
);
6814 if (needs_dst_copy(lbld_after
, inst
)) {
6815 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6817 if (inst
->predicate
) {
6818 /* Handle predication by copying the original contents of
6819 * the destination into the temporary before emitting the
6820 * lowered instruction.
6822 const fs_builder gbld_before
=
6823 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6824 inst
->exec_size
), 0);
6825 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6826 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6827 offset(dst
, inst
->exec_size
, k
));
6831 const fs_builder gbld_after
=
6832 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6833 inst
->exec_size
), 0);
6834 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6835 /* Use a builder of the right width to perform the copy avoiding
6836 * uninitialized data if the lowered execution size is greater than
6837 * the original execution size of the instruction.
6839 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6840 offset(tmp
, lbld_after
, k
));
6846 /* No need to allocate a temporary for the lowered instruction, just
6847 * take the right group of channels from the original region.
6854 fs_visitor::lower_simd_width()
6856 bool progress
= false;
6858 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6859 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6861 if (lower_width
!= inst
->exec_size
) {
6862 /* Builder matching the original instruction. We may also need to
6863 * emit an instruction of width larger than the original, set the
6864 * execution size of the builder to the highest of both for now so
6865 * we're sure that both cases can be handled.
6867 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6868 const fs_builder ibld
= bld
.at(block
, inst
)
6869 .exec_all(inst
->force_writemask_all
)
6870 .group(max_width
, inst
->group
/ max_width
);
6872 /* Split the copies in chunks of the execution width of either the
6873 * original or the lowered instruction, whichever is lower.
6875 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6876 const unsigned dst_size
= inst
->size_written
/
6877 inst
->dst
.component_size(inst
->exec_size
);
6879 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6881 /* Inserting the zip, unzip, and duplicated instructions in all of
6882 * the right spots is somewhat tricky. All of the unzip and any
6883 * instructions from the zip which unzip the destination prior to
6884 * writing need to happen before all of the per-group instructions
6885 * and the zip instructions need to happen after. In order to sort
6886 * this all out, we insert the unzip instructions before \p inst,
6887 * insert the per-group instructions after \p inst (i.e. before
6888 * inst->next), and insert the zip instructions before the
6889 * instruction after \p inst. Since we are inserting instructions
6890 * after \p inst, inst->next is a moving target and we need to save
6891 * it off here so that we insert the zip instructions in the right
6894 * Since we're inserting split instructions after after_inst, the
6895 * instructions will end up in the reverse order that we insert them.
6896 * However, certain render target writes require that the low group
6897 * instructions come before the high group. From the Ivy Bridge PRM
6898 * Vol. 4, Pt. 1, Section 3.9.11:
6900 * "If multiple SIMD8 Dual Source messages are delivered by the
6901 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6902 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6903 * Group Select setting."
6905 * And, from Section 3.9.11.1 of the same PRM:
6907 * "When SIMD32 or SIMD16 PS threads send render target writes
6908 * with multiple SIMD8 and SIMD16 messages, the following must
6911 * All the slots (as described above) must have a corresponding
6912 * render target write irrespective of the slot's validity. A slot
6913 * is considered valid when at least one sample is enabled. For
6914 * example, a SIMD16 PS thread must send two SIMD8 render target
6915 * writes to cover all the slots.
6917 * PS thread must send SIMD render target write messages with
6918 * increasing slot numbers. For example, SIMD16 thread has
6919 * Slot[15:0] and if two SIMD8 render target writes are used, the
6920 * first SIMD8 render target write must send Slot[7:0] and the
6921 * next one must send Slot[15:8]."
6923 * In order to make low group instructions come before high group
6924 * instructions (this is required for some render target writes), we
6925 * split from the highest group to lowest.
6927 exec_node
*const after_inst
= inst
->next
;
6928 for (int i
= n
- 1; i
>= 0; i
--) {
6929 /* Emit a copy of the original instruction with the lowered width.
6930 * If the EOT flag was set throw it away except for the last
6931 * instruction to avoid killing the thread prematurely.
6933 fs_inst split_inst
= *inst
;
6934 split_inst
.exec_size
= lower_width
;
6935 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6937 /* Select the correct channel enables for the i-th group, then
6938 * transform the sources and destination and emit the lowered
6941 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6943 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6944 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6946 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6947 lbld
.at(block
, after_inst
), inst
);
6948 split_inst
.size_written
=
6949 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6951 lbld
.at(block
, inst
->next
).emit(split_inst
);
6954 inst
->remove(block
);
6960 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6966 * Transform barycentric vectors into the interleaved form expected by the PLN
6967 * instruction and returned by the Gen7+ PI shared function.
6969 * For channels 0-15 in SIMD16 mode they are expected to be laid out as
6970 * follows in the register file:
6977 * There is no need to handle SIMD32 here -- This is expected to be run after
6978 * SIMD lowering, since SIMD lowering relies on vectors having the standard
6982 fs_visitor::lower_barycentrics()
6984 const bool has_interleaved_layout
= devinfo
->has_pln
|| devinfo
->gen
>= 7;
6985 bool progress
= false;
6987 if (stage
!= MESA_SHADER_FRAGMENT
|| !has_interleaved_layout
)
6990 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6991 if (inst
->exec_size
< 16)
6994 const fs_builder
ibld(this, block
, inst
);
6995 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
6997 switch (inst
->opcode
) {
6998 case FS_OPCODE_LINTERP
: {
6999 assert(inst
->exec_size
== 16);
7000 const fs_reg tmp
= ibld
.vgrf(inst
->src
[0].type
, 2);
7003 for (unsigned i
= 0; i
< ARRAY_SIZE(srcs
); i
++)
7004 srcs
[i
] = horiz_offset(offset(inst
->src
[0], ibld
, i
% 2),
7007 ubld
.LOAD_PAYLOAD(tmp
, srcs
, ARRAY_SIZE(srcs
), ARRAY_SIZE(srcs
));
7013 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
7014 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
7015 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
: {
7016 assert(inst
->exec_size
== 16);
7017 const fs_reg tmp
= ibld
.vgrf(inst
->dst
.type
, 2);
7019 for (unsigned i
= 0; i
< 2; i
++) {
7020 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
7021 fs_inst
*mov
= ibld
.at(block
, inst
->next
).group(8, g
)
7022 .MOV(horiz_offset(offset(inst
->dst
, ibld
, i
),
7024 offset(tmp
, ubld
, 2 * g
+ i
));
7025 mov
->predicate
= inst
->predicate
;
7026 mov
->predicate_inverse
= inst
->predicate_inverse
;
7027 mov
->flag_subreg
= inst
->flag_subreg
;
7041 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7047 fs_visitor::dump_instructions() const
7049 dump_instructions(NULL
);
7053 fs_visitor::dump_instructions(const char *name
) const
7055 FILE *file
= stderr
;
7056 if (name
&& geteuid() != 0) {
7057 file
= fopen(name
, "w");
7063 const register_pressure
&rp
= regpressure_analysis
.require();
7064 unsigned ip
= 0, max_pressure
= 0;
7065 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
7066 max_pressure
= MAX2(max_pressure
, rp
.regs_live_at_ip
[ip
]);
7067 fprintf(file
, "{%3d} %4d: ", rp
.regs_live_at_ip
[ip
], ip
);
7068 dump_instruction(inst
, file
);
7071 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
7074 foreach_in_list(backend_instruction
, inst
, &instructions
) {
7075 fprintf(file
, "%4d: ", ip
++);
7076 dump_instruction(inst
, file
);
7080 if (file
!= stderr
) {
7086 fs_visitor::dump_instruction(const backend_instruction
*be_inst
) const
7088 dump_instruction(be_inst
, stderr
);
7092 fs_visitor::dump_instruction(const backend_instruction
*be_inst
, FILE *file
) const
7094 const fs_inst
*inst
= (const fs_inst
*)be_inst
;
7096 if (inst
->predicate
) {
7097 fprintf(file
, "(%cf%d.%d) ",
7098 inst
->predicate_inverse
? '-' : '+',
7099 inst
->flag_subreg
/ 2,
7100 inst
->flag_subreg
% 2);
7103 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
7105 fprintf(file
, ".sat");
7106 if (inst
->conditional_mod
) {
7107 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
7108 if (!inst
->predicate
&&
7109 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
7110 inst
->opcode
!= BRW_OPCODE_CSEL
&&
7111 inst
->opcode
!= BRW_OPCODE_IF
&&
7112 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
7113 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
7114 inst
->flag_subreg
% 2);
7117 fprintf(file
, "(%d) ", inst
->exec_size
);
7120 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
7123 if (inst
->ex_mlen
) {
7124 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
7128 fprintf(file
, "(EOT) ");
7131 switch (inst
->dst
.file
) {
7133 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
7136 fprintf(file
, "g%d", inst
->dst
.nr
);
7139 fprintf(file
, "m%d", inst
->dst
.nr
);
7142 fprintf(file
, "(null)");
7145 fprintf(file
, "***u%d***", inst
->dst
.nr
);
7148 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
7151 switch (inst
->dst
.nr
) {
7153 fprintf(file
, "null");
7155 case BRW_ARF_ADDRESS
:
7156 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
7158 case BRW_ARF_ACCUMULATOR
:
7159 fprintf(file
, "acc%d", inst
->dst
.subnr
);
7162 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7165 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7170 unreachable("not reached");
7173 if (inst
->dst
.offset
||
7174 (inst
->dst
.file
== VGRF
&&
7175 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
7176 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
7177 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
7178 inst
->dst
.offset
% reg_size
);
7181 if (inst
->dst
.stride
!= 1)
7182 fprintf(file
, "<%u>", inst
->dst
.stride
);
7183 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
7185 for (int i
= 0; i
< inst
->sources
; i
++) {
7186 if (inst
->src
[i
].negate
)
7188 if (inst
->src
[i
].abs
)
7190 switch (inst
->src
[i
].file
) {
7192 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
7195 fprintf(file
, "g%d", inst
->src
[i
].nr
);
7198 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
7201 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
7204 fprintf(file
, "u%d", inst
->src
[i
].nr
);
7207 fprintf(file
, "(null)");
7210 switch (inst
->src
[i
].type
) {
7211 case BRW_REGISTER_TYPE_F
:
7212 fprintf(file
, "%-gf", inst
->src
[i
].f
);
7214 case BRW_REGISTER_TYPE_DF
:
7215 fprintf(file
, "%fdf", inst
->src
[i
].df
);
7217 case BRW_REGISTER_TYPE_W
:
7218 case BRW_REGISTER_TYPE_D
:
7219 fprintf(file
, "%dd", inst
->src
[i
].d
);
7221 case BRW_REGISTER_TYPE_UW
:
7222 case BRW_REGISTER_TYPE_UD
:
7223 fprintf(file
, "%uu", inst
->src
[i
].ud
);
7225 case BRW_REGISTER_TYPE_Q
:
7226 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
7228 case BRW_REGISTER_TYPE_UQ
:
7229 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
7231 case BRW_REGISTER_TYPE_VF
:
7232 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
7233 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
7234 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
7235 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
7236 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
7238 case BRW_REGISTER_TYPE_V
:
7239 case BRW_REGISTER_TYPE_UV
:
7240 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
7241 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
7244 fprintf(file
, "???");
7249 switch (inst
->src
[i
].nr
) {
7251 fprintf(file
, "null");
7253 case BRW_ARF_ADDRESS
:
7254 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
7256 case BRW_ARF_ACCUMULATOR
:
7257 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7260 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7263 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7269 if (inst
->src
[i
].offset
||
7270 (inst
->src
[i
].file
== VGRF
&&
7271 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7272 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7273 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7274 inst
->src
[i
].offset
% reg_size
);
7277 if (inst
->src
[i
].abs
)
7280 if (inst
->src
[i
].file
!= IMM
) {
7282 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7283 unsigned hstride
= inst
->src
[i
].hstride
;
7284 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7286 stride
= inst
->src
[i
].stride
;
7289 fprintf(file
, "<%u>", stride
);
7291 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7294 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7295 fprintf(file
, ", ");
7300 if (inst
->force_writemask_all
)
7301 fprintf(file
, "NoMask ");
7303 if (inst
->exec_size
!= dispatch_width
)
7304 fprintf(file
, "group%d ", inst
->group
);
7306 fprintf(file
, "\n");
7310 fs_visitor::setup_fs_payload_gen6()
7312 assert(stage
== MESA_SHADER_FRAGMENT
);
7313 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7314 const unsigned payload_width
= MIN2(16, dispatch_width
);
7315 assert(dispatch_width
% payload_width
== 0);
7316 assert(devinfo
->gen
>= 6);
7318 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7319 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7321 prog_data
->uses_sample_mask
=
7322 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7324 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7326 * "MSDISPMODE_PERSAMPLE is required in order to select
7329 * So we can only really get sample positions if we are doing real
7330 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7331 * persample dispatch, we hard-code it to 0.5.
7333 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7334 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7336 /* R0: PS thread payload header. */
7339 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7340 /* R1: masks, pixel X/Y coordinates. */
7341 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7344 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7345 /* R3-26: barycentric interpolation coordinates. These appear in the
7346 * same order that they appear in the brw_barycentric_mode enum. Each
7347 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7348 * registers if dispatch width == 16. Coordinates only appear if they
7349 * were enabled using the "Barycentric Interpolation Mode" bits in
7352 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7353 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7354 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7355 payload
.num_regs
+= payload_width
/ 4;
7359 /* R27-28: interpolated depth if uses source depth */
7360 if (prog_data
->uses_src_depth
) {
7361 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7362 payload
.num_regs
+= payload_width
/ 8;
7365 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7366 if (prog_data
->uses_src_w
) {
7367 payload
.source_w_reg
[j
] = payload
.num_regs
;
7368 payload
.num_regs
+= payload_width
/ 8;
7371 /* R31: MSAA position offsets. */
7372 if (prog_data
->uses_pos_offset
) {
7373 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7377 /* R32-33: MSAA input coverage mask */
7378 if (prog_data
->uses_sample_mask
) {
7379 assert(devinfo
->gen
>= 7);
7380 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7381 payload
.num_regs
+= payload_width
/ 8;
7385 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7386 source_depth_to_render_target
= true;
7391 fs_visitor::setup_vs_payload()
7393 /* R0: thread header, R1: urb handles */
7394 payload
.num_regs
= 2;
7398 fs_visitor::setup_gs_payload()
7400 assert(stage
== MESA_SHADER_GEOMETRY
);
7402 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7403 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7405 /* R0: thread header, R1: output URB handles */
7406 payload
.num_regs
= 2;
7408 if (gs_prog_data
->include_primitive_id
) {
7409 /* R2: Primitive ID 0..7 */
7413 /* Always enable VUE handles so we can safely use pull model if needed.
7415 * The push model for a GS uses a ton of register space even for trivial
7416 * scenarios with just a few inputs, so just make things easier and a bit
7417 * safer by always having pull model available.
7419 gs_prog_data
->base
.include_vue_handles
= true;
7421 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7422 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7424 /* Use a maximum of 24 registers for push-model inputs. */
7425 const unsigned max_push_components
= 24;
7427 /* If pushing our inputs would take too many registers, reduce the URB read
7428 * length (which is in HWords, or 8 registers), and resort to pulling.
7430 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7431 * have to multiply by VerticesIn to obtain the total storage requirement.
7433 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7434 max_push_components
) {
7435 vue_prog_data
->urb_read_length
=
7436 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7441 fs_visitor::setup_cs_payload()
7443 assert(devinfo
->gen
>= 7);
7444 payload
.num_regs
= 1;
7447 brw::register_pressure::register_pressure(const fs_visitor
*v
)
7449 const fs_live_variables
&live
= v
->live_analysis
.require();
7450 const unsigned num_instructions
= v
->cfg
->num_blocks
?
7451 v
->cfg
->blocks
[v
->cfg
->num_blocks
- 1]->end_ip
+ 1 : 0;
7453 regs_live_at_ip
= new unsigned[num_instructions
]();
7455 for (unsigned reg
= 0; reg
< v
->alloc
.count
; reg
++) {
7456 for (int ip
= live
.vgrf_start
[reg
]; ip
<= live
.vgrf_end
[reg
]; ip
++)
7457 regs_live_at_ip
[ip
] += v
->alloc
.sizes
[reg
];
7461 brw::register_pressure::~register_pressure()
7463 delete[] regs_live_at_ip
;
7467 fs_visitor::invalidate_analysis(brw::analysis_dependency_class c
)
7469 backend_shader::invalidate_analysis(c
);
7470 live_analysis
.invalidate(c
);
7471 regpressure_analysis
.invalidate(c
);
7475 fs_visitor::optimize()
7477 /* Start by validating the shader we currently have. */
7480 /* bld is the common builder object pointing at the end of the program we
7481 * used to translate it into i965 IR. For the optimization and lowering
7482 * passes coming next, any code added after the end of the program without
7483 * having explicitly called fs_builder::at() clearly points at a mistake.
7484 * Ideally optimization passes wouldn't be part of the visitor so they
7485 * wouldn't have access to bld at all, but they do, so just in case some
7486 * pass forgets to ask for a location explicitly set it to NULL here to
7487 * make it trip. The dispatch width is initialized to a bogus value to
7488 * make sure that optimizations set the execution controls explicitly to
7489 * match the code they are manipulating instead of relying on the defaults.
7491 bld
= fs_builder(this, 64);
7493 assign_constant_locations();
7494 lower_constant_loads();
7498 split_virtual_grfs();
7501 #define OPT(pass, args...) ({ \
7503 bool this_progress = pass(args); \
7505 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7506 char filename[64]; \
7507 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7508 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7510 backend_shader::dump_instructions(filename); \
7515 progress = progress || this_progress; \
7519 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7521 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7522 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7524 backend_shader::dump_instructions(filename
);
7527 bool progress
= false;
7531 /* Before anything else, eliminate dead code. The results of some NIR
7532 * instructions may effectively be calculated twice. Once when the
7533 * instruction is encountered, and again when the user of that result is
7534 * encountered. Wipe those away before algebraic optimizations and
7535 * especially copy propagation can mix things up.
7537 OPT(dead_code_eliminate
);
7539 OPT(remove_extra_rounding_modes
);
7546 OPT(remove_duplicate_mrf_writes
);
7550 OPT(opt_copy_propagation
);
7551 OPT(opt_predicated_break
, this);
7552 OPT(opt_cmod_propagation
);
7553 OPT(dead_code_eliminate
);
7554 OPT(opt_peephole_sel
);
7555 OPT(dead_control_flow_eliminate
, this);
7556 OPT(opt_register_renaming
);
7557 OPT(opt_saturate_propagation
);
7558 OPT(register_coalesce
);
7559 OPT(compute_to_mrf
);
7560 OPT(eliminate_find_live_channel
);
7562 OPT(compact_virtual_grfs
);
7568 if (OPT(lower_pack
)) {
7569 OPT(register_coalesce
);
7570 OPT(dead_code_eliminate
);
7573 OPT(lower_simd_width
);
7574 OPT(lower_barycentrics
);
7576 /* After SIMD lowering just in case we had to unroll the EOT send. */
7577 OPT(opt_sampler_eot
);
7579 OPT(lower_logical_sends
);
7581 /* After logical SEND lowering. */
7582 OPT(fixup_nomask_control_flow
);
7585 OPT(opt_copy_propagation
);
7586 /* Only run after logical send lowering because it's easier to implement
7587 * in terms of physical sends.
7589 if (OPT(opt_zero_samples
))
7590 OPT(opt_copy_propagation
);
7591 /* Run after logical send lowering to give it a chance to CSE the
7592 * LOAD_PAYLOAD instructions created to construct the payloads of
7593 * e.g. texturing messages in cases where it wasn't possible to CSE the
7594 * whole logical instruction.
7597 OPT(register_coalesce
);
7598 OPT(compute_to_mrf
);
7599 OPT(dead_code_eliminate
);
7600 OPT(remove_duplicate_mrf_writes
);
7601 OPT(opt_peephole_sel
);
7604 OPT(opt_redundant_discard_jumps
);
7606 if (OPT(lower_load_payload
)) {
7607 split_virtual_grfs();
7609 /* Lower 64 bit MOVs generated by payload lowering. */
7610 if (!devinfo
->has_64bit_float
&& !devinfo
->has_64bit_int
)
7613 OPT(register_coalesce
);
7614 OPT(lower_simd_width
);
7615 OPT(compute_to_mrf
);
7616 OPT(dead_code_eliminate
);
7619 OPT(opt_combine_constants
);
7620 OPT(lower_integer_multiplication
);
7623 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7624 OPT(opt_cmod_propagation
);
7626 OPT(opt_copy_propagation
);
7627 OPT(dead_code_eliminate
);
7630 if (OPT(lower_regioning
)) {
7631 OPT(opt_copy_propagation
);
7632 OPT(dead_code_eliminate
);
7633 OPT(lower_simd_width
);
7636 OPT(fixup_sends_duplicate_payload
);
7638 lower_uniform_pull_constant_loads();
7644 * From the Skylake PRM Vol. 2a docs for sends:
7646 * "It is required that the second block of GRFs does not overlap with the
7649 * There are plenty of cases where we may accidentally violate this due to
7650 * having, for instance, both sources be the constant 0. This little pass
7651 * just adds a new vgrf for the second payload and copies it over.
7654 fs_visitor::fixup_sends_duplicate_payload()
7656 bool progress
= false;
7658 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7659 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7660 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7661 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7662 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7663 BRW_REGISTER_TYPE_UD
);
7664 /* Sadly, we've lost all notion of channels and bit sizes at this
7665 * point. Just WE_all it.
7667 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7668 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7669 fs_reg copy_dst
= tmp
;
7670 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7671 if (inst
->ex_mlen
== i
+ 1) {
7672 /* Only one register left; do SIMD8 */
7673 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7675 ibld
.MOV(copy_dst
, copy_src
);
7677 copy_src
= offset(copy_src
, ibld
, 1);
7678 copy_dst
= offset(copy_dst
, ibld
, 1);
7686 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7692 * Three source instruction must have a GRF/MRF destination register.
7693 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7696 fs_visitor::fixup_3src_null_dest()
7698 bool progress
= false;
7700 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7701 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7702 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7709 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
7710 DEPENDENCY_VARIABLES
);
7714 * Find the first instruction in the program that might start a region of
7715 * divergent control flow due to a HALT jump. There is no
7716 * find_halt_control_flow_region_end(), the region of divergence extends until
7717 * the only FS_OPCODE_PLACEHOLDER_HALT in the program.
7719 static const fs_inst
*
7720 find_halt_control_flow_region_start(const fs_visitor
*v
)
7722 if (brw_wm_prog_data(v
->prog_data
)->uses_kill
) {
7723 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
7724 if (inst
->opcode
== FS_OPCODE_DISCARD_JUMP
||
7725 inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
)
7734 * Work around the Gen12 hardware bug filed as GEN:BUG:1407528679. EU fusion
7735 * can cause a BB to be executed with all channels disabled, which will lead
7736 * to the execution of any NoMask instructions in it, even though any
7737 * execution-masked instructions will be correctly shot down. This may break
7738 * assumptions of some NoMask SEND messages whose descriptor depends on data
7739 * generated by live invocations of the shader.
7741 * This avoids the problem by predicating certain instructions on an ANY
7742 * horizontal predicate that makes sure that their execution is omitted when
7743 * all channels of the program are disabled.
7746 fs_visitor::fixup_nomask_control_flow()
7748 if (devinfo
->gen
!= 12)
7751 const brw_predicate pred
= dispatch_width
> 16 ? BRW_PREDICATE_ALIGN1_ANY32H
:
7752 dispatch_width
> 8 ? BRW_PREDICATE_ALIGN1_ANY16H
:
7753 BRW_PREDICATE_ALIGN1_ANY8H
;
7754 const fs_inst
*halt_start
= find_halt_control_flow_region_start(this);
7756 bool progress
= false;
7758 const fs_live_variables
&live_vars
= live_analysis
.require();
7760 /* Scan the program backwards in order to be able to easily determine
7761 * whether the flag register is live at any point.
7763 foreach_block_reverse_safe(block
, cfg
) {
7764 BITSET_WORD flag_liveout
= live_vars
.block_data
[block
->num
]
7766 STATIC_ASSERT(ARRAY_SIZE(live_vars
.block_data
[0].flag_liveout
) == 1);
7768 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
7769 if (!inst
->predicate
&& inst
->exec_size
>= 8)
7770 flag_liveout
&= ~inst
->flags_written();
7772 switch (inst
->opcode
) {
7775 /* Note that this doesn't handle FS_OPCODE_DISCARD_JUMP since only
7776 * the first one in the program closes the region of divergent
7777 * control flow due to any HALT instructions -- Instead this is
7778 * handled with the halt_start check below.
7783 case BRW_OPCODE_WHILE
:
7784 case BRW_OPCODE_ENDIF
:
7785 case FS_OPCODE_PLACEHOLDER_HALT
:
7790 /* Note that the vast majority of NoMask SEND instructions in the
7791 * program are harmless while executed in a block with all
7792 * channels disabled, since any instructions with side effects we
7793 * could hit here should be execution-masked.
7795 * The main concern is NoMask SEND instructions where the message
7796 * descriptor or header depends on data generated by live
7797 * invocations of the shader (RESINFO and
7798 * FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically
7799 * computed surface index seem to be the only examples right now
7800 * where this could easily lead to GPU hangs). Unfortunately we
7801 * have no straightforward way to detect that currently, so just
7802 * predicate any NoMask SEND instructions we find under control
7805 * If this proves to have a measurable performance impact it can
7806 * be easily extended with a whitelist of messages we know we can
7807 * safely omit the predication for.
7809 if (depth
&& inst
->force_writemask_all
&&
7810 is_send(inst
) && !inst
->predicate
) {
7811 /* We need to load the execution mask into the flag register by
7812 * using a builder with channel group matching the whole shader
7813 * (rather than the default which is derived from the original
7814 * instruction), in order to avoid getting a right-shifted
7817 const fs_builder ubld
= fs_builder(this, block
, inst
)
7818 .exec_all().group(dispatch_width
, 0);
7819 const fs_reg flag
= retype(brw_flag_reg(0, 0),
7820 BRW_REGISTER_TYPE_UD
);
7822 /* Due to the lack of flag register allocation we need to save
7823 * and restore the flag register if it's live.
7825 const bool save_flag
= flag_liveout
&
7826 flag_mask(flag
, dispatch_width
/ 8);
7827 const fs_reg tmp
= ubld
.group(1, 0).vgrf(flag
.type
);
7830 ubld
.group(1, 0).MOV(tmp
, flag
);
7832 ubld
.emit(FS_OPCODE_LOAD_LIVE_CHANNELS
);
7834 set_predicate(pred
, inst
);
7835 inst
->flag_subreg
= 0;
7838 ubld
.group(1, 0).at(block
, inst
->next
).MOV(flag
, tmp
);
7845 if (inst
== halt_start
)
7848 flag_liveout
|= inst
->flags_read(devinfo
);
7853 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7859 fs_visitor::allocate_registers(bool allow_spilling
)
7863 static const enum instruction_scheduler_mode pre_modes
[] = {
7865 SCHEDULE_PRE_NON_LIFO
,
7869 static const char *scheduler_mode_name
[] = {
7875 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7877 /* Try each scheduling heuristic to see if it can successfully register
7878 * allocate without spilling. They should be ordered by decreasing
7879 * performance but increasing likelihood of allocating.
7881 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7882 schedule_instructions(pre_modes
[i
]);
7883 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7886 assign_regs_trivial();
7891 /* Scheduling may create additional opportunities for CMOD propagation,
7892 * so let's do it again. If CMOD propagation made any progress,
7893 * elminate dead code one more time.
7895 bool progress
= false;
7896 const int iteration
= 99;
7899 if (OPT(opt_cmod_propagation
)) {
7900 /* dead_code_eliminate "undoes" the fixing done by
7901 * fixup_3src_null_dest, so we have to do it again if
7902 * dead_code_eliminiate makes any progress.
7904 if (OPT(dead_code_eliminate
))
7905 fixup_3src_null_dest();
7908 bool can_spill
= allow_spilling
&&
7909 (i
== ARRAY_SIZE(pre_modes
) - 1);
7911 /* We should only spill registers on the last scheduling. */
7912 assert(!spilled_any_registers
);
7914 allocated
= assign_regs(can_spill
, spill_all
);
7920 fail("Failure to register allocate. Reduce number of "
7921 "live scalar values to avoid this.");
7922 } else if (spilled_any_registers
) {
7923 compiler
->shader_perf_log(log_data
,
7924 "%s shader triggered register spilling. "
7925 "Try reducing the number of live scalar "
7926 "values to improve performance.\n",
7930 /* This must come after all optimization and register allocation, since
7931 * it inserts dead code that happens to have side effects, and it does
7932 * so based on the actual physical registers in use.
7934 insert_gen4_send_dependency_workarounds();
7939 opt_bank_conflicts();
7941 schedule_instructions(SCHEDULE_POST
);
7943 if (last_scratch
> 0) {
7944 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7946 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7948 if (stage
== MESA_SHADER_COMPUTE
) {
7949 if (devinfo
->is_haswell
) {
7950 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7951 * field documentation, Haswell supports a minimum of 2kB of
7952 * scratch space for compute shaders, unlike every other stage
7955 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7956 } else if (devinfo
->gen
<= 7) {
7957 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7958 * field documentation, platforms prior to Haswell measure scratch
7959 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7961 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7962 max_scratch_size
= 12 * 1024;
7966 /* We currently only support up to 2MB of scratch space. If we
7967 * need to support more eventually, the documentation suggests
7968 * that we could allocate a larger buffer, and partition it out
7969 * ourselves. We'd just have to undo the hardware's address
7970 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7971 * and then add FFTID * (Larger Per Thread Scratch Space).
7973 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7974 * Thread Group Tracking > Local Memory/Scratch Space.
7976 assert(prog_data
->total_scratch
< max_scratch_size
);
7983 fs_visitor::run_vs()
7985 assert(stage
== MESA_SHADER_VERTEX
);
7989 if (shader_time_index
>= 0)
7990 emit_shader_time_begin();
7999 if (shader_time_index
>= 0)
8000 emit_shader_time_end();
8006 assign_curb_setup();
8007 assign_vs_urb_setup();
8009 fixup_3src_null_dest();
8010 allocate_registers(true /* allow_spilling */);
8016 fs_visitor::set_tcs_invocation_id()
8018 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
8019 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
8021 const unsigned instance_id_mask
=
8022 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
8023 const unsigned instance_id_shift
=
8024 devinfo
->gen
>= 11 ? 16 : 17;
8026 /* Get instance number from g0.2 bits 22:16 or 23:17 */
8027 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
8028 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
8029 brw_imm_ud(instance_id_mask
));
8031 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
8033 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
8034 /* gl_InvocationID is just the thread number */
8035 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
8039 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
8041 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
8042 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
8043 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
8044 bld
.MOV(channels_ud
, channels_uw
);
8046 if (tcs_prog_data
->instances
== 1) {
8047 invocation_id
= channels_ud
;
8049 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
8050 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
8051 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
8056 fs_visitor::run_tcs()
8058 assert(stage
== MESA_SHADER_TESS_CTRL
);
8060 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
8061 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
8062 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
8064 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
8065 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
8067 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
8068 /* r1-r4 contain the ICP handles. */
8069 payload
.num_regs
= 5;
8071 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
8072 assert(tcs_key
->input_vertices
> 0);
8073 /* r1 contains output handles, r2 may contain primitive ID, then the
8074 * ICP handles occupy the next 1-32 registers.
8076 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
8077 tcs_key
->input_vertices
;
8080 if (shader_time_index
>= 0)
8081 emit_shader_time_begin();
8083 /* Initialize gl_InvocationID */
8084 set_tcs_invocation_id();
8086 const bool fix_dispatch_mask
=
8087 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
8088 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
8090 /* Fix the disptach mask */
8091 if (fix_dispatch_mask
) {
8092 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
8093 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
8094 bld
.IF(BRW_PREDICATE_NORMAL
);
8099 if (fix_dispatch_mask
) {
8100 bld
.emit(BRW_OPCODE_ENDIF
);
8103 /* Emit EOT write; set TR DS Cache bit */
8105 fs_reg(get_tcs_output_urb_handle()),
8106 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
8107 fs_reg(brw_imm_ud(0)),
8109 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
8110 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
8112 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
8113 bld
.null_reg_ud(), payload
);
8117 if (shader_time_index
>= 0)
8118 emit_shader_time_end();
8127 assign_curb_setup();
8128 assign_tcs_urb_setup();
8130 fixup_3src_null_dest();
8131 allocate_registers(true /* allow_spilling */);
8137 fs_visitor::run_tes()
8139 assert(stage
== MESA_SHADER_TESS_EVAL
);
8141 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
8142 payload
.num_regs
= 5;
8144 if (shader_time_index
>= 0)
8145 emit_shader_time_begin();
8154 if (shader_time_index
>= 0)
8155 emit_shader_time_end();
8161 assign_curb_setup();
8162 assign_tes_urb_setup();
8164 fixup_3src_null_dest();
8165 allocate_registers(true /* allow_spilling */);
8171 fs_visitor::run_gs()
8173 assert(stage
== MESA_SHADER_GEOMETRY
);
8177 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
8179 if (gs_compile
->control_data_header_size_bits
> 0) {
8180 /* Create a VGRF to store accumulated control data bits. */
8181 this->control_data_bits
= vgrf(glsl_type::uint_type
);
8183 /* If we're outputting more than 32 control data bits, then EmitVertex()
8184 * will set control_data_bits to 0 after emitting the first vertex.
8185 * Otherwise, we need to initialize it to 0 here.
8187 if (gs_compile
->control_data_header_size_bits
<= 32) {
8188 const fs_builder abld
= bld
.annotate("initialize control data bits");
8189 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
8193 if (shader_time_index
>= 0)
8194 emit_shader_time_begin();
8198 emit_gs_thread_end();
8200 if (shader_time_index
>= 0)
8201 emit_shader_time_end();
8210 assign_curb_setup();
8211 assign_gs_urb_setup();
8213 fixup_3src_null_dest();
8214 allocate_registers(true /* allow_spilling */);
8219 /* From the SKL PRM, Volume 16, Workarounds:
8221 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
8222 * only header phases (R0-R2)
8224 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
8225 * have been header only.
8227 * Instead of enabling push constants one can alternatively enable one of the
8228 * inputs. Here one simply chooses "layer" which shouldn't impose much
8232 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
8234 if (wm_prog_data
->num_varying_inputs
)
8237 if (wm_prog_data
->base
.curb_read_length
)
8240 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
8241 wm_prog_data
->num_varying_inputs
= 1;
8243 brw_compute_urb_setup_index(wm_prog_data
);
8247 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
8249 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
8250 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
8252 assert(stage
== MESA_SHADER_FRAGMENT
);
8254 if (devinfo
->gen
>= 6)
8255 setup_fs_payload_gen6();
8257 setup_fs_payload_gen4();
8261 } else if (do_rep_send
) {
8262 assert(dispatch_width
== 16);
8263 emit_repclear_shader();
8265 if (shader_time_index
>= 0)
8266 emit_shader_time_begin();
8268 if (nir
->info
.inputs_read
> 0 ||
8269 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
8270 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
8271 if (devinfo
->gen
< 6)
8272 emit_interpolation_setup_gen4();
8274 emit_interpolation_setup_gen6();
8277 /* We handle discards by keeping track of the still-live pixels in f0.1.
8278 * Initialize it with the dispatched pixels.
8280 if (wm_prog_data
->uses_kill
) {
8281 const unsigned lower_width
= MIN2(dispatch_width
, 16);
8282 for (unsigned i
= 0; i
< dispatch_width
/ lower_width
; i
++) {
8283 const fs_reg dispatch_mask
=
8284 devinfo
->gen
>= 6 ? brw_vec1_grf((i
? 2 : 1), 7) :
8286 bld
.exec_all().group(1, 0)
8287 .MOV(sample_mask_reg(bld
.group(lower_width
, i
)),
8288 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
8292 if (nir
->info
.writes_memory
)
8293 wm_prog_data
->has_side_effects
= true;
8300 if (wm_prog_data
->uses_kill
)
8301 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
8303 if (wm_key
->alpha_test_func
)
8308 if (shader_time_index
>= 0)
8309 emit_shader_time_end();
8315 assign_curb_setup();
8317 if (devinfo
->gen
>= 9)
8318 gen9_ps_header_only_workaround(wm_prog_data
);
8322 fixup_3src_null_dest();
8324 allocate_registers(allow_spilling
);
8334 fs_visitor::run_cs(bool allow_spilling
)
8336 assert(stage
== MESA_SHADER_COMPUTE
);
8340 if (shader_time_index
>= 0)
8341 emit_shader_time_begin();
8343 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
8344 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
8345 const fs_builder abld
= bld
.exec_all().group(1, 0);
8346 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
8347 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
8355 emit_cs_terminate();
8357 if (shader_time_index
>= 0)
8358 emit_shader_time_end();
8364 assign_curb_setup();
8366 fixup_3src_null_dest();
8367 allocate_registers(allow_spilling
);
8376 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
8378 nir_foreach_use(src
, def
) {
8379 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
8382 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
8383 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
8387 nir_foreach_if_use(src
, def
)
8394 * Return a bitfield where bit n is set if barycentric interpolation mode n
8395 * (see enum brw_barycentric_mode) is needed by the fragment shader.
8397 * We examine the load_barycentric intrinsics rather than looking at input
8398 * variables so that we catch interpolateAtCentroid() messages too, which
8399 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
8402 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
8403 const nir_shader
*shader
)
8405 unsigned barycentric_interp_modes
= 0;
8407 nir_foreach_function(f
, shader
) {
8411 nir_foreach_block(block
, f
->impl
) {
8412 nir_foreach_instr(instr
, block
) {
8413 if (instr
->type
!= nir_instr_type_intrinsic
)
8416 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8417 switch (intrin
->intrinsic
) {
8418 case nir_intrinsic_load_barycentric_pixel
:
8419 case nir_intrinsic_load_barycentric_centroid
:
8420 case nir_intrinsic_load_barycentric_sample
:
8426 /* Ignore WPOS; it doesn't require interpolation. */
8427 assert(intrin
->dest
.is_ssa
);
8428 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8431 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8432 nir_intrinsic_interp_mode(intrin
);
8433 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8434 enum brw_barycentric_mode bary
=
8435 brw_barycentric_mode(interp
, bary_op
);
8437 barycentric_interp_modes
|= 1 << bary
;
8439 if (devinfo
->needs_unlit_centroid_workaround
&&
8440 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8441 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8446 return barycentric_interp_modes
;
8450 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8451 const nir_shader
*shader
)
8453 prog_data
->flat_inputs
= 0;
8455 nir_foreach_variable(var
, &shader
->inputs
) {
8456 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8457 for (unsigned s
= 0; s
< slots
; s
++) {
8458 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8460 if (input_index
< 0)
8464 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8465 prog_data
->flat_inputs
|= 1 << input_index
;
8471 computed_depth_mode(const nir_shader
*shader
)
8473 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8474 switch (shader
->info
.fs
.depth_layout
) {
8475 case FRAG_DEPTH_LAYOUT_NONE
:
8476 case FRAG_DEPTH_LAYOUT_ANY
:
8477 return BRW_PSCDEPTH_ON
;
8478 case FRAG_DEPTH_LAYOUT_GREATER
:
8479 return BRW_PSCDEPTH_ON_GE
;
8480 case FRAG_DEPTH_LAYOUT_LESS
:
8481 return BRW_PSCDEPTH_ON_LE
;
8482 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8483 return BRW_PSCDEPTH_OFF
;
8486 return BRW_PSCDEPTH_OFF
;
8490 * Move load_interpolated_input with simple (payload-based) barycentric modes
8491 * to the top of the program so we don't emit multiple PLNs for the same input.
8493 * This works around CSE not being able to handle non-dominating cases
8499 * interpolate the same exact input
8502 * This should be replaced by global value numbering someday.
8505 move_interpolation_to_top(nir_shader
*nir
)
8507 bool progress
= false;
8509 nir_foreach_function(f
, nir
) {
8513 nir_block
*top
= nir_start_block(f
->impl
);
8514 exec_node
*cursor_node
= NULL
;
8516 nir_foreach_block(block
, f
->impl
) {
8520 nir_foreach_instr_safe(instr
, block
) {
8521 if (instr
->type
!= nir_instr_type_intrinsic
)
8524 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8525 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8527 nir_intrinsic_instr
*bary_intrinsic
=
8528 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8529 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8531 /* Leave interpolateAtSample/Offset() where they are. */
8532 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8533 op
== nir_intrinsic_load_barycentric_at_offset
)
8536 nir_instr
*move
[3] = {
8537 &bary_intrinsic
->instr
,
8538 intrin
->src
[1].ssa
->parent_instr
,
8542 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8543 if (move
[i
]->block
!= top
) {
8544 move
[i
]->block
= top
;
8545 exec_node_remove(&move
[i
]->node
);
8547 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8549 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8551 cursor_node
= &move
[i
]->node
;
8557 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8558 ((unsigned) nir_metadata_block_index
|
8559 (unsigned) nir_metadata_dominance
));
8566 * Demote per-sample barycentric intrinsics to centroid.
8568 * Useful when rendering to a non-multisampled buffer.
8571 demote_sample_qualifiers(nir_shader
*nir
)
8573 bool progress
= true;
8575 nir_foreach_function(f
, nir
) {
8580 nir_builder_init(&b
, f
->impl
);
8582 nir_foreach_block(block
, f
->impl
) {
8583 nir_foreach_instr_safe(instr
, block
) {
8584 if (instr
->type
!= nir_instr_type_intrinsic
)
8587 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8588 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8589 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8592 b
.cursor
= nir_before_instr(instr
);
8593 nir_ssa_def
*centroid
=
8594 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8595 nir_intrinsic_interp_mode(intrin
));
8596 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8597 nir_src_for_ssa(centroid
));
8598 nir_instr_remove(instr
);
8603 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8604 ((unsigned) nir_metadata_block_index
|
8605 (unsigned) nir_metadata_dominance
));
8612 * Pre-gen6, the register file of the EUs was shared between threads,
8613 * and each thread used some subset allocated on a 16-register block
8614 * granularity. The unit states wanted these block counts.
8617 brw_register_blocks(int reg_count
)
8619 return ALIGN(reg_count
, 16) / 16 - 1;
8623 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8625 const struct brw_wm_prog_key
*key
,
8626 struct brw_wm_prog_data
*prog_data
,
8628 int shader_time_index8
, int shader_time_index16
,
8629 int shader_time_index32
, bool allow_spilling
,
8630 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8631 struct brw_compile_stats
*stats
,
8634 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8635 const unsigned max_subgroup_size
= compiler
->devinfo
->gen
>= 6 ? 32 : 16;
8637 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8638 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8639 brw_nir_lower_fs_outputs(shader
);
8641 if (devinfo
->gen
< 6)
8642 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8644 /* From the SKL PRM, Volume 7, "Alpha Coverage":
8645 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
8646 * hardware, regardless of the state setting for this feature."
8648 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
) {
8649 /* Run constant fold optimization in order to get the correct source
8650 * offset to determine render target 0 store instruction in
8651 * emit_alpha_to_coverage pass.
8653 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8654 NIR_PASS_V(shader
, brw_nir_lower_alpha_to_coverage
);
8657 if (!key
->multisample_fbo
)
8658 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8659 NIR_PASS_V(shader
, move_interpolation_to_top
);
8660 brw_postprocess_nir(shader
, compiler
, true);
8662 /* key->alpha_test_func means simulating alpha testing via discards,
8663 * so the shader definitely kills pixels.
8665 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8666 key
->alpha_test_func
;
8667 prog_data
->uses_omask
= key
->multisample_fbo
&&
8668 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8669 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8670 prog_data
->computed_stencil
=
8671 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8673 prog_data
->persample_dispatch
=
8674 key
->multisample_fbo
&&
8675 (key
->persample_interp
||
8676 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8677 SYSTEM_BIT_SAMPLE_POS
)) ||
8678 shader
->info
.fs
.uses_sample_qualifier
||
8679 shader
->info
.outputs_read
);
8681 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8683 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8684 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8685 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8687 prog_data
->barycentric_interp_modes
=
8688 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8690 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8691 brw_compute_flat_inputs(prog_data
, shader
);
8693 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8694 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8695 float throughput
= 0;
8696 bool has_spilled
= false;
8698 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8699 &prog_data
->base
, shader
, 8, shader_time_index8
);
8700 if (!v8
->run_fs(allow_spilling
, false /* do_rep_send */)) {
8702 *error_str
= ralloc_strdup(mem_ctx
, v8
->fail_msg
);
8706 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8707 simd8_cfg
= v8
->cfg
;
8708 prog_data
->base
.dispatch_grf_start_reg
= v8
->payload
.num_regs
;
8709 prog_data
->reg_blocks_8
= brw_register_blocks(v8
->grf_used
);
8710 const performance
&perf
= v8
->performance_analysis
.require();
8711 throughput
= MAX2(throughput
, perf
.throughput
);
8712 has_spilled
= v8
->spilled_any_registers
;
8713 allow_spilling
= false;
8716 /* Limit dispatch width to simd8 with dual source blending on gen8.
8717 * See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1917
8719 if (devinfo
->gen
== 8 && prog_data
->dual_src_blend
&&
8720 !(INTEL_DEBUG
& DEBUG_NO8
)) {
8721 assert(!use_rep_send
);
8722 v8
->limit_dispatch_width(8, "gen8 workaround: "
8723 "using SIMD8 when dual src blending.\n");
8727 v8
->max_dispatch_width
>= 16 &&
8728 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8729 /* Try a SIMD16 compile */
8730 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8731 &prog_data
->base
, shader
, 16, shader_time_index16
);
8732 v16
->import_uniforms(v8
);
8733 if (!v16
->run_fs(allow_spilling
, use_rep_send
)) {
8734 compiler
->shader_perf_log(log_data
,
8735 "SIMD16 shader failed to compile: %s",
8738 simd16_cfg
= v16
->cfg
;
8739 prog_data
->dispatch_grf_start_reg_16
= v16
->payload
.num_regs
;
8740 prog_data
->reg_blocks_16
= brw_register_blocks(v16
->grf_used
);
8741 const performance
&perf
= v16
->performance_analysis
.require();
8742 throughput
= MAX2(throughput
, perf
.throughput
);
8743 has_spilled
= v16
->spilled_any_registers
;
8744 allow_spilling
= false;
8748 /* Currently, the compiler only supports SIMD32 on SNB+ */
8750 v8
->max_dispatch_width
>= 32 && !use_rep_send
&&
8751 devinfo
->gen
>= 6 && simd16_cfg
&&
8752 !(INTEL_DEBUG
& DEBUG_NO32
)) {
8753 /* Try a SIMD32 compile */
8754 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8755 &prog_data
->base
, shader
, 32, shader_time_index32
);
8756 v32
->import_uniforms(v8
);
8757 if (!v32
->run_fs(allow_spilling
, false)) {
8758 compiler
->shader_perf_log(log_data
,
8759 "SIMD32 shader failed to compile: %s",
8762 const performance
&perf
= v32
->performance_analysis
.require();
8764 if (!(INTEL_DEBUG
& DEBUG_DO32
) && throughput
>= perf
.throughput
) {
8765 compiler
->shader_perf_log(log_data
, "SIMD32 shader inefficient\n");
8767 simd32_cfg
= v32
->cfg
;
8768 prog_data
->dispatch_grf_start_reg_32
= v32
->payload
.num_regs
;
8769 prog_data
->reg_blocks_32
= brw_register_blocks(v32
->grf_used
);
8770 throughput
= MAX2(throughput
, perf
.throughput
);
8775 /* When the caller requests a repclear shader, they want SIMD16-only */
8779 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8780 * at the top to select the shader. We've never implemented that.
8781 * Instead, we just give them exactly one shader and we pick the widest one
8784 if (compiler
->devinfo
->gen
< 5) {
8785 if (simd32_cfg
|| simd16_cfg
)
8791 /* If computed depth is enabled SNB only allows SIMD8. */
8792 if (compiler
->devinfo
->gen
== 6 &&
8793 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8794 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8796 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8797 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8798 * the data available in the base prog data struct for convenience.
8801 prog_data
->base
.dispatch_grf_start_reg
=
8802 prog_data
->dispatch_grf_start_reg_16
;
8803 } else if (simd32_cfg
) {
8804 prog_data
->base
.dispatch_grf_start_reg
=
8805 prog_data
->dispatch_grf_start_reg_32
;
8809 if (prog_data
->persample_dispatch
) {
8810 /* Starting with SandyBridge (where we first get MSAA), the different
8811 * pixel dispatch combinations are grouped into classifications A
8812 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware
8813 * generations, the only configurations supporting persample dispatch
8814 * are those in which only one dispatch width is enabled.
8816 * The Gen12 hardware spec has a similar dispatch grouping table, but
8817 * the following conflicting restriction applies (from the page on
8818 * "Structure_3DSTATE_PS_BODY"), so we need to keep the SIMD16 shader:
8820 * "SIMD32 may only be enabled if SIMD16 or (dual)SIMD8 is also
8823 if (simd32_cfg
|| simd16_cfg
)
8825 if (simd32_cfg
&& devinfo
->gen
< 12)
8829 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8830 v8
->runtime_check_aads_emit
, MESA_SHADER_FRAGMENT
);
8832 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8833 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8834 shader
->info
.label
?
8835 shader
->info
.label
: "unnamed",
8836 shader
->info
.name
));
8840 prog_data
->dispatch_8
= true;
8841 g
.generate_code(simd8_cfg
, 8, v8
->shader_stats
,
8842 v8
->performance_analysis
.require(), stats
);
8843 stats
= stats
? stats
+ 1 : NULL
;
8847 prog_data
->dispatch_16
= true;
8848 prog_data
->prog_offset_16
= g
.generate_code(
8849 simd16_cfg
, 16, v16
->shader_stats
,
8850 v16
->performance_analysis
.require(), stats
);
8851 stats
= stats
? stats
+ 1 : NULL
;
8855 prog_data
->dispatch_32
= true;
8856 prog_data
->prog_offset_32
= g
.generate_code(
8857 simd32_cfg
, 32, v32
->shader_stats
,
8858 v32
->performance_analysis
.require(), stats
);
8859 stats
= stats
? stats
+ 1 : NULL
;
8866 return g
.get_assembly();
8870 fs_visitor::emit_cs_work_group_id_setup()
8872 assert(stage
== MESA_SHADER_COMPUTE
);
8874 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8876 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8877 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8878 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8880 bld
.MOV(*reg
, r0_1
);
8881 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8882 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8888 brw_cs_push_const_total_size(const struct brw_cs_prog_data
*cs_prog_data
,
8891 assert(cs_prog_data
->push
.per_thread
.size
% REG_SIZE
== 0);
8892 assert(cs_prog_data
->push
.cross_thread
.size
% REG_SIZE
== 0);
8893 return cs_prog_data
->push
.per_thread
.size
* threads
+
8894 cs_prog_data
->push
.cross_thread
.size
;
8898 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8900 block
->dwords
= dwords
;
8901 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8902 block
->size
= block
->regs
* 32;
8906 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8907 struct brw_cs_prog_data
*cs_prog_data
)
8909 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8910 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8911 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8913 /* The thread ID should be stored in the last param dword */
8914 assert(subgroup_id_index
== -1 ||
8915 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8917 unsigned cross_thread_dwords
, per_thread_dwords
;
8918 if (!cross_thread_supported
) {
8919 cross_thread_dwords
= 0u;
8920 per_thread_dwords
= prog_data
->nr_params
;
8921 } else if (subgroup_id_index
>= 0) {
8922 /* Fill all but the last register with cross-thread payload */
8923 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8924 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8925 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8927 /* Fill all data using cross-thread payload */
8928 cross_thread_dwords
= prog_data
->nr_params
;
8929 per_thread_dwords
= 0u;
8932 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8933 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8935 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8936 cs_prog_data
->push
.per_thread
.size
== 0);
8937 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8938 cs_prog_data
->push
.per_thread
.dwords
==
8939 prog_data
->nr_params
);
8943 filter_simd(const nir_instr
*instr
, const void *_options
)
8945 if (instr
->type
!= nir_instr_type_intrinsic
)
8948 switch (nir_instr_as_intrinsic(instr
)->intrinsic
) {
8949 case nir_intrinsic_load_simd_width_intel
:
8950 case nir_intrinsic_load_subgroup_id
:
8958 static nir_ssa_def
*
8959 lower_simd(nir_builder
*b
, nir_instr
*instr
, void *options
)
8961 uintptr_t simd_width
= (uintptr_t)options
;
8963 switch (nir_instr_as_intrinsic(instr
)->intrinsic
) {
8964 case nir_intrinsic_load_simd_width_intel
:
8965 return nir_imm_int(b
, simd_width
);
8967 case nir_intrinsic_load_subgroup_id
:
8968 /* If the whole workgroup fits in one thread, we can lower subgroup_id
8969 * to a constant zero.
8971 if (!b
->shader
->info
.cs
.local_size_variable
) {
8972 unsigned local_workgroup_size
= b
->shader
->info
.cs
.local_size
[0] *
8973 b
->shader
->info
.cs
.local_size
[1] *
8974 b
->shader
->info
.cs
.local_size
[2];
8975 if (local_workgroup_size
<= simd_width
)
8976 return nir_imm_int(b
, 0);
8986 brw_nir_lower_simd(nir_shader
*nir
, unsigned dispatch_width
)
8988 nir_shader_lower_instructions(nir
, filter_simd
, lower_simd
,
8989 (void *)(uintptr_t)dispatch_width
);
8993 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8995 const struct brw_cs_prog_key
*key
,
8996 const nir_shader
*src_shader
,
8997 unsigned dispatch_width
)
8999 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
9000 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
9002 NIR_PASS_V(shader
, brw_nir_lower_simd
, dispatch_width
);
9004 /* Clean up after the local index and ID calculations. */
9005 NIR_PASS_V(shader
, nir_opt_constant_folding
);
9006 NIR_PASS_V(shader
, nir_opt_dce
);
9008 brw_postprocess_nir(shader
, compiler
, true);
9014 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
9016 const struct brw_cs_prog_key
*key
,
9017 struct brw_cs_prog_data
*prog_data
,
9018 const nir_shader
*src_shader
,
9019 int shader_time_index
,
9020 struct brw_compile_stats
*stats
,
9023 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
9024 prog_data
->slm_size
= src_shader
->num_shared
;
9026 unsigned local_workgroup_size
;
9027 if (src_shader
->info
.cs
.local_size_variable
) {
9028 local_workgroup_size
= src_shader
->info
.cs
.max_variable_local_size
;
9030 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
9031 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
9032 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
9033 local_workgroup_size
= src_shader
->info
.cs
.local_size
[0] *
9034 src_shader
->info
.cs
.local_size
[1] * src_shader
->info
.cs
.local_size
[2];
9037 /* Limit max_threads to 64 for the GPGPU_WALKER command */
9038 const uint32_t max_threads
= MIN2(64, compiler
->devinfo
->max_cs_threads
);
9039 unsigned min_dispatch_width
=
9040 DIV_ROUND_UP(local_workgroup_size
, max_threads
);
9041 min_dispatch_width
= MAX2(8, min_dispatch_width
);
9042 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
9043 assert(min_dispatch_width
<= 32);
9044 unsigned max_dispatch_width
= 32;
9046 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
9047 /* These enum values are expressly chosen to be equal to the subgroup
9048 * size that they require.
9050 const unsigned required_dispatch_width
=
9051 (unsigned)key
->base
.subgroup_size_type
;
9052 assert(required_dispatch_width
== 8 ||
9053 required_dispatch_width
== 16 ||
9054 required_dispatch_width
== 32);
9055 if (required_dispatch_width
< min_dispatch_width
||
9056 required_dispatch_width
> max_dispatch_width
) {
9058 *error_str
= ralloc_strdup(mem_ctx
,
9059 "Cannot satisfy explicit subgroup size");
9063 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
9066 assert(min_dispatch_width
<= max_dispatch_width
);
9068 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
9069 fs_visitor
*v
= NULL
;
9070 const char *fail_msg
= NULL
;
9072 /* Now the main event: Visit the shader IR and generate our CS IR for it.
9074 if (likely(!(INTEL_DEBUG
& DEBUG_NO8
)) &&
9075 min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
9076 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
9078 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
9080 nir8
, 8, shader_time_index
);
9081 if (!v8
->run_cs(true /* allow_spilling */)) {
9082 fail_msg
= v8
->fail_msg
;
9084 /* We should always be able to do SIMD32 for compute shaders */
9085 assert(v8
->max_dispatch_width
>= 32);
9088 prog_data
->simd_size
= 8;
9089 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
9093 if ((!v
|| !v
->spilled_any_registers
) &&
9094 likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
9095 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
9096 /* Try a SIMD16 compile */
9097 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
9099 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
9101 nir16
, 16, shader_time_index
);
9103 v16
->import_uniforms(v8
);
9105 if (!v16
->run_cs(v
== NULL
/* allow_spilling */)) {
9106 compiler
->shader_perf_log(log_data
,
9107 "SIMD16 shader failed to compile: %s",
9111 "Couldn't generate SIMD16 program and not "
9112 "enough threads for SIMD8";
9115 /* We should always be able to do SIMD32 for compute shaders */
9116 assert(v16
->max_dispatch_width
>= 32);
9119 prog_data
->simd_size
= 16;
9120 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
9124 if (likely(!(INTEL_DEBUG
& DEBUG_NO32
)) &&
9125 (!v
|| !v
->spilled_any_registers
) &&
9126 !fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
9127 max_dispatch_width
>= 32) {
9128 /* Try a SIMD32 compile */
9129 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
9131 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
9133 nir32
, 32, shader_time_index
);
9135 v32
->import_uniforms(v8
);
9137 v32
->import_uniforms(v16
);
9139 if (!v32
->run_cs(v
== NULL
/* allow_spilling */)) {
9140 compiler
->shader_perf_log(log_data
,
9141 "SIMD32 shader failed to compile: %s",
9145 "Couldn't generate SIMD32 program and not "
9146 "enough threads for SIMD16";
9150 prog_data
->simd_size
= 32;
9151 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
9155 if (unlikely(!v
&& (INTEL_DEBUG
& (DEBUG_NO8
| DEBUG_NO16
| DEBUG_NO32
)))) {
9158 ralloc_strdup(mem_ctx
,
9159 "Cannot satisfy INTEL_DEBUG flags SIMD restrictions");
9166 const unsigned *ret
= NULL
;
9167 if (unlikely(v
== NULL
)) {
9170 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
9172 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
9173 v
->runtime_check_aads_emit
, MESA_SHADER_COMPUTE
);
9174 if (INTEL_DEBUG
& DEBUG_CS
) {
9175 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
9176 src_shader
->info
.label
?
9177 src_shader
->info
.label
: "unnamed",
9178 src_shader
->info
.name
);
9179 g
.enable_debug(name
);
9182 g
.generate_code(v
->cfg
, prog_data
->simd_size
, v
->shader_stats
,
9183 v
->performance_analysis
.require(), stats
);
9185 ret
= g
.get_assembly();
9196 brw_cs_simd_size_for_group_size(const struct gen_device_info
*devinfo
,
9197 const struct brw_cs_prog_data
*cs_prog_data
,
9198 unsigned group_size
)
9200 return cs_prog_data
->simd_size
;
9204 * Test the dispatch mask packing assumptions of
9205 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
9206 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
9207 * executed with an unexpected dispatch mask.
9210 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
9212 const gl_shader_stage stage
= bld
.shader
->stage
;
9214 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
9215 bld
.shader
->stage_prog_data
)) {
9216 const fs_builder ubld
= bld
.exec_all().group(1, 0);
9217 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
9218 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
9221 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
9222 ubld
.AND(tmp
, mask
, tmp
);
9224 /* This will loop forever if the dispatch mask doesn't have the expected
9225 * form '2^n-1', in which case tmp will be non-zero.
9227 bld
.emit(BRW_OPCODE_DO
);
9228 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
9229 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));
9234 fs_visitor::workgroup_size() const
9236 assert(stage
== MESA_SHADER_COMPUTE
);
9237 const struct brw_cs_prog_data
*cs
= brw_cs_prog_data(prog_data
);
9238 return cs
->local_size
[0] * cs
->local_size
[1] * cs
->local_size
[2];