intel/compiler: Fill a compiler statistics struct
[mesa.git] / src / intel / compiler / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #ifndef BRW_FS_H
29 #define BRW_FS_H
30
31 #include "brw_shader.h"
32 #include "brw_ir_fs.h"
33 #include "brw_fs_builder.h"
34 #include "compiler/nir/nir.h"
35
36 struct bblock_t;
37 namespace {
38 struct acp_entry;
39 }
40
41 namespace brw {
42 class fs_live_variables;
43 }
44
45 struct brw_gs_compile;
46
47 static inline fs_reg
48 offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
49 {
50 return offset(reg, bld.dispatch_width(), delta);
51 }
52
53 #define UBO_START ((1 << 16) - 4)
54
55 struct shader_stats {
56 const char *scheduler_mode;
57 unsigned promoted_constants;
58 };
59
60 /**
61 * The fragment shader front-end.
62 *
63 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
64 */
65 class fs_visitor : public backend_shader
66 {
67 public:
68 fs_visitor(const struct brw_compiler *compiler, void *log_data,
69 void *mem_ctx,
70 const brw_base_prog_key *key,
71 struct brw_stage_prog_data *prog_data,
72 struct gl_program *prog,
73 const nir_shader *shader,
74 unsigned dispatch_width,
75 int shader_time_index,
76 const struct brw_vue_map *input_vue_map = NULL);
77 fs_visitor(const struct brw_compiler *compiler, void *log_data,
78 void *mem_ctx,
79 struct brw_gs_compile *gs_compile,
80 struct brw_gs_prog_data *prog_data,
81 const nir_shader *shader,
82 int shader_time_index);
83 void init();
84 ~fs_visitor();
85
86 fs_reg vgrf(const glsl_type *const type);
87 void import_uniforms(fs_visitor *v);
88
89 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
90 const fs_reg &dst,
91 const fs_reg &surf_index,
92 const fs_reg &varying_offset,
93 uint32_t const_offset);
94 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
95
96 bool run_fs(bool allow_spilling, bool do_rep_send);
97 bool run_vs();
98 bool run_tcs();
99 bool run_tes();
100 bool run_gs();
101 bool run_cs(unsigned min_dispatch_width);
102 void optimize();
103 void allocate_registers(unsigned min_dispatch_width, bool allow_spilling);
104 void setup_fs_payload_gen4();
105 void setup_fs_payload_gen6();
106 void setup_vs_payload();
107 void setup_gs_payload();
108 void setup_cs_payload();
109 bool fixup_sends_duplicate_payload();
110 void fixup_3src_null_dest();
111 void assign_curb_setup();
112 void assign_urb_setup();
113 void convert_attr_sources_to_hw_regs(fs_inst *inst);
114 void assign_vs_urb_setup();
115 void assign_tcs_urb_setup();
116 void assign_tes_urb_setup();
117 void assign_gs_urb_setup();
118 bool assign_regs(bool allow_spilling, bool spill_all);
119 void assign_regs_trivial();
120 void calculate_payload_ranges(int payload_node_count,
121 int *payload_last_use_ip);
122 void split_virtual_grfs();
123 bool compact_virtual_grfs();
124 void assign_constant_locations();
125 bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
126 unsigned *out_pull_index);
127 void lower_constant_loads();
128 void invalidate_live_intervals();
129 void calculate_live_intervals();
130 void calculate_register_pressure();
131 void validate();
132 bool opt_algebraic();
133 bool opt_redundant_discard_jumps();
134 bool opt_cse();
135 bool opt_cse_local(bblock_t *block);
136 bool opt_copy_propagation();
137 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
138 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
139 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
140 exec_list *acp);
141 bool opt_drop_redundant_mov_to_flags();
142 bool opt_register_renaming();
143 bool opt_bank_conflicts();
144 unsigned bank_conflict_cycles(const fs_inst *inst) const;
145 bool register_coalesce();
146 bool compute_to_mrf();
147 bool eliminate_find_live_channel();
148 bool dead_code_eliminate();
149 bool remove_duplicate_mrf_writes();
150 bool remove_extra_rounding_modes();
151
152 bool opt_sampler_eot();
153 bool virtual_grf_interferes(int a, int b);
154 void schedule_instructions(instruction_scheduler_mode mode);
155 void insert_gen4_send_dependency_workarounds();
156 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
157 fs_inst *inst);
158 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
159 fs_inst *inst);
160 void vfail(const char *msg, va_list args);
161 void fail(const char *msg, ...);
162 void limit_dispatch_width(unsigned n, const char *msg);
163 void lower_uniform_pull_constant_loads();
164 bool lower_load_payload();
165 bool lower_pack();
166 bool lower_regioning();
167 bool lower_logical_sends();
168 bool lower_integer_multiplication();
169 bool lower_minmax();
170 bool lower_simd_width();
171 bool opt_combine_constants();
172
173 void emit_dummy_fs();
174 void emit_repclear_shader();
175 void emit_fragcoord_interpolation(fs_reg wpos);
176 fs_reg *emit_frontfacing_interpolation();
177 fs_reg *emit_samplepos_setup();
178 fs_reg *emit_sampleid_setup();
179 fs_reg *emit_samplemaskin_setup();
180 void emit_interpolation_setup_gen4();
181 void emit_interpolation_setup_gen6();
182 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
183 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
184 const fs_reg &texture,
185 const fs_reg &texture_handle);
186 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
187 fs_reg resolve_source_modifiers(const fs_reg &src);
188 void emit_discard_jump();
189 void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr,
190 fs_reg result, fs_reg *op, unsigned fsign_src);
191 bool opt_peephole_sel();
192 bool opt_peephole_csel();
193 bool opt_peephole_predicated_break();
194 bool opt_saturate_propagation();
195 bool opt_cmod_propagation();
196 bool opt_zero_samples();
197
198 void set_tcs_invocation_id();
199
200 void emit_nir_code();
201 void nir_setup_outputs();
202 void nir_setup_uniforms();
203 void nir_emit_system_values();
204 void nir_emit_impl(nir_function_impl *impl);
205 void nir_emit_cf_list(exec_list *list);
206 void nir_emit_if(nir_if *if_stmt);
207 void nir_emit_loop(nir_loop *loop);
208 void nir_emit_block(nir_block *block);
209 void nir_emit_instr(nir_instr *instr);
210 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr,
211 bool need_dest);
212 bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result,
213 nir_alu_instr *instr);
214 void nir_emit_load_const(const brw::fs_builder &bld,
215 nir_load_const_instr *instr);
216 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
217 nir_intrinsic_instr *instr);
218 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
219 nir_intrinsic_instr *instr);
220 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
221 nir_intrinsic_instr *instr);
222 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
223 nir_intrinsic_instr *instr);
224 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
225 nir_intrinsic_instr *instr);
226 fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
227 nir_intrinsic_instr *instr);
228 fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
229 nir_intrinsic_instr *instr);
230 void nir_emit_intrinsic(const brw::fs_builder &bld,
231 nir_intrinsic_instr *instr);
232 void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
233 nir_intrinsic_instr *instr);
234 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
235 int op, nir_intrinsic_instr *instr);
236 void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld,
237 int op, nir_intrinsic_instr *instr);
238 void nir_emit_shared_atomic(const brw::fs_builder &bld,
239 int op, nir_intrinsic_instr *instr);
240 void nir_emit_shared_atomic_float(const brw::fs_builder &bld,
241 int op, nir_intrinsic_instr *instr);
242 void nir_emit_global_atomic(const brw::fs_builder &bld,
243 int op, nir_intrinsic_instr *instr);
244 void nir_emit_global_atomic_float(const brw::fs_builder &bld,
245 int op, nir_intrinsic_instr *instr);
246 void nir_emit_texture(const brw::fs_builder &bld,
247 nir_tex_instr *instr);
248 void nir_emit_jump(const brw::fs_builder &bld,
249 nir_jump_instr *instr);
250 fs_reg get_nir_src(const nir_src &src);
251 fs_reg get_nir_src_imm(const nir_src &src);
252 fs_reg get_nir_dest(const nir_dest &dest);
253 fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
254 fs_reg get_tcs_single_patch_icp_handle(const brw::fs_builder &bld,
255 nir_intrinsic_instr *instr);
256 fs_reg get_tcs_eight_patch_icp_handle(const brw::fs_builder &bld,
257 nir_intrinsic_instr *instr);
258 struct brw_reg get_tcs_output_urb_handle();
259
260 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
261 unsigned wr_mask);
262
263 bool optimize_extract_to_float(nir_alu_instr *instr,
264 const fs_reg &result);
265 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
266 const fs_reg &result);
267
268 void emit_alpha_test();
269 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
270 fs_reg color1, fs_reg color2,
271 fs_reg src0_alpha, unsigned components);
272 void emit_alpha_to_coverage_workaround(const fs_reg &src0_alpha);
273 void emit_fb_writes();
274 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
275 const fs_reg &dst, unsigned target);
276 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
277 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
278 unsigned stream_id);
279 void emit_gs_control_data_bits(const fs_reg &vertex_count);
280 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
281 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
282 unsigned stream_id);
283 void emit_gs_thread_end();
284 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
285 unsigned base_offset, const nir_src &offset_src,
286 unsigned num_components, unsigned first_component);
287 void emit_cs_terminate();
288 fs_reg *emit_cs_work_group_id_setup();
289
290 void emit_barrier();
291
292 void emit_shader_time_begin();
293 void emit_shader_time_end();
294 void SHADER_TIME_ADD(const brw::fs_builder &bld,
295 int shader_time_subindex,
296 fs_reg value);
297
298 fs_reg get_timestamp(const brw::fs_builder &bld);
299
300 fs_reg interp_reg(int location, int channel);
301
302 int implied_mrf_writes(fs_inst *inst) const;
303
304 virtual void dump_instructions();
305 virtual void dump_instructions(const char *name);
306 void dump_instruction(backend_instruction *inst);
307 void dump_instruction(backend_instruction *inst, FILE *file);
308
309 const brw_base_prog_key *const key;
310 const struct brw_sampler_prog_key_data *key_tex;
311
312 struct brw_gs_compile *gs_compile;
313
314 struct brw_stage_prog_data *prog_data;
315 struct gl_program *prog;
316
317 const struct brw_vue_map *input_vue_map;
318
319 int *virtual_grf_start;
320 int *virtual_grf_end;
321 brw::fs_live_variables *live_intervals;
322
323 int *regs_live_at_ip;
324
325 /** Number of uniform variable components visited. */
326 unsigned uniforms;
327
328 /** Byte-offset for the next available spot in the scratch space buffer. */
329 unsigned last_scratch;
330
331 /**
332 * Array mapping UNIFORM register numbers to the pull parameter index,
333 * or -1 if this uniform register isn't being uploaded as a pull constant.
334 */
335 int *pull_constant_loc;
336
337 /**
338 * Array mapping UNIFORM register numbers to the push parameter index,
339 * or -1 if this uniform register isn't being uploaded as a push constant.
340 */
341 int *push_constant_loc;
342
343 fs_reg subgroup_id;
344 fs_reg frag_depth;
345 fs_reg frag_stencil;
346 fs_reg sample_mask;
347 fs_reg outputs[VARYING_SLOT_MAX];
348 fs_reg dual_src_output;
349 int first_non_payload_grf;
350 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
351 unsigned max_grf;
352
353 fs_reg *nir_locals;
354 fs_reg *nir_ssa_values;
355 fs_reg *nir_system_values;
356
357 bool failed;
358 char *fail_msg;
359
360 /** Register numbers for thread payload fields. */
361 struct thread_payload {
362 uint8_t subspan_coord_reg[2];
363 uint8_t source_depth_reg[2];
364 uint8_t source_w_reg[2];
365 uint8_t aa_dest_stencil_reg[2];
366 uint8_t dest_depth_reg[2];
367 uint8_t sample_pos_reg[2];
368 uint8_t sample_mask_in_reg[2];
369 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
370 uint8_t local_invocation_id_reg[2];
371
372 /** The number of thread payload registers the hardware will supply. */
373 uint8_t num_regs;
374 } payload;
375
376 bool source_depth_to_render_target;
377 bool runtime_check_aads_emit;
378
379 fs_reg pixel_x;
380 fs_reg pixel_y;
381 fs_reg wpos_w;
382 fs_reg pixel_w;
383 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
384 fs_reg shader_start_time;
385 fs_reg final_gs_vertex_count;
386 fs_reg control_data_bits;
387 fs_reg invocation_id;
388
389 unsigned grf_used;
390 bool spilled_any_registers;
391
392 const unsigned dispatch_width; /**< 8, 16 or 32 */
393 unsigned max_dispatch_width;
394
395 int shader_time_index;
396
397 struct shader_stats shader_stats;
398
399 brw::fs_builder bld;
400
401 private:
402 fs_reg prepare_alu_destination_and_sources(const brw::fs_builder &bld,
403 nir_alu_instr *instr,
404 fs_reg *op,
405 bool need_dest);
406
407 void resolve_inot_sources(const brw::fs_builder &bld, nir_alu_instr *instr,
408 fs_reg *op);
409 void lower_mul_dword_inst(fs_inst *inst, bblock_t *block);
410 void lower_mul_qword_inst(fs_inst *inst, bblock_t *block);
411 void lower_mulh_inst(fs_inst *inst, bblock_t *block);
412 };
413
414 /**
415 * The fragment shader code generator.
416 *
417 * Translates FS IR to actual i965 assembly code.
418 */
419 class fs_generator
420 {
421 public:
422 fs_generator(const struct brw_compiler *compiler, void *log_data,
423 void *mem_ctx,
424 struct brw_stage_prog_data *prog_data,
425 struct shader_stats shader_stats,
426 bool runtime_check_aads_emit,
427 gl_shader_stage stage);
428 ~fs_generator();
429
430 void enable_debug(const char *shader_name);
431 int generate_code(const cfg_t *cfg, int dispatch_width,
432 struct brw_compile_stats *stats);
433 const unsigned *get_assembly();
434
435 private:
436 void fire_fb_write(fs_inst *inst,
437 struct brw_reg payload,
438 struct brw_reg implied_header,
439 GLuint nr);
440 void generate_send(fs_inst *inst,
441 struct brw_reg dst,
442 struct brw_reg desc,
443 struct brw_reg ex_desc,
444 struct brw_reg payload,
445 struct brw_reg payload2);
446 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
447 void generate_fb_read(fs_inst *inst, struct brw_reg dst,
448 struct brw_reg payload);
449 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
450 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
451 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
452 void generate_barrier(fs_inst *inst, struct brw_reg src);
453 bool generate_linterp(fs_inst *inst, struct brw_reg dst,
454 struct brw_reg *src);
455 void generate_tex(fs_inst *inst, struct brw_reg dst,
456 struct brw_reg surface_index,
457 struct brw_reg sampler_index);
458 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
459 struct brw_reg src,
460 struct brw_reg surf_index);
461 void generate_ddx(const fs_inst *inst,
462 struct brw_reg dst, struct brw_reg src);
463 void generate_ddy(const fs_inst *inst,
464 struct brw_reg dst, struct brw_reg src);
465 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
466 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
467 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
468 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
469 struct brw_reg index,
470 struct brw_reg offset);
471 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
472 struct brw_reg dst,
473 struct brw_reg surf_index,
474 struct brw_reg payload);
475 void generate_varying_pull_constant_load_gen4(fs_inst *inst,
476 struct brw_reg dst,
477 struct brw_reg index);
478 void generate_mov_dispatch_to_flags(fs_inst *inst);
479
480 void generate_pixel_interpolator_query(fs_inst *inst,
481 struct brw_reg dst,
482 struct brw_reg src,
483 struct brw_reg msg_data,
484 unsigned msg_type);
485
486 void generate_set_sample_id(fs_inst *inst,
487 struct brw_reg dst,
488 struct brw_reg src0,
489 struct brw_reg src1);
490
491 void generate_discard_jump(fs_inst *inst);
492
493 void generate_pack_half_2x16_split(fs_inst *inst,
494 struct brw_reg dst,
495 struct brw_reg x,
496 struct brw_reg y);
497
498 void generate_shader_time_add(fs_inst *inst,
499 struct brw_reg payload,
500 struct brw_reg offset,
501 struct brw_reg value);
502
503 void generate_mov_indirect(fs_inst *inst,
504 struct brw_reg dst,
505 struct brw_reg reg,
506 struct brw_reg indirect_byte_offset);
507
508 void generate_shuffle(fs_inst *inst,
509 struct brw_reg dst,
510 struct brw_reg src,
511 struct brw_reg idx);
512
513 void generate_quad_swizzle(const fs_inst *inst,
514 struct brw_reg dst, struct brw_reg src,
515 unsigned swiz);
516
517 bool patch_discard_jumps_to_fb_writes();
518
519 const struct brw_compiler *compiler;
520 void *log_data; /* Passed to compiler->*_log functions */
521
522 const struct gen_device_info *devinfo;
523
524 struct brw_codegen *p;
525 struct brw_stage_prog_data * const prog_data;
526
527 unsigned dispatch_width; /**< 8, 16 or 32 */
528
529 exec_list discard_halt_patches;
530 struct shader_stats shader_stats;
531 bool runtime_check_aads_emit;
532 bool debug_flag;
533 const char *shader_name;
534 gl_shader_stage stage;
535 void *mem_ctx;
536 };
537
538 namespace brw {
539 inline fs_reg
540 fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
541 brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1)
542 {
543 if (!regs[0])
544 return fs_reg();
545
546 if (bld.dispatch_width() > 16) {
547 const fs_reg tmp = bld.vgrf(type, n);
548 const brw::fs_builder hbld = bld.exec_all().group(16, 0);
549 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
550 fs_reg *const components = new fs_reg[n * m];
551
552 for (unsigned c = 0; c < n; c++) {
553 for (unsigned g = 0; g < m; g++) {
554 components[c * m + g] =
555 offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c);
556 }
557 }
558
559 hbld.LOAD_PAYLOAD(tmp, components, n * m, 0);
560
561 delete[] components;
562 return tmp;
563
564 } else {
565 return fs_reg(retype(brw_vec8_grf(regs[0], 0), type));
566 }
567 }
568
569 bool
570 lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
571 }
572
573 void shuffle_from_32bit_read(const brw::fs_builder &bld,
574 const fs_reg &dst,
575 const fs_reg &src,
576 uint32_t first_component,
577 uint32_t components);
578
579 fs_reg setup_imm_df(const brw::fs_builder &bld,
580 double v);
581
582 fs_reg setup_imm_b(const brw::fs_builder &bld,
583 int8_t v);
584
585 fs_reg setup_imm_ub(const brw::fs_builder &bld,
586 uint8_t v);
587
588 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
589 nir_intrinsic_op op);
590
591 #endif /* BRW_FS_H */