intel/cs: Push subgroup ID instead of base thread ID
[mesa.git] / src / intel / compiler / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #ifndef BRW_FS_H
29 #define BRW_FS_H
30
31 #include "brw_shader.h"
32 #include "brw_ir_fs.h"
33 #include "brw_fs_builder.h"
34 #include "compiler/nir/nir.h"
35
36 struct bblock_t;
37 namespace {
38 struct acp_entry;
39 }
40
41 namespace brw {
42 class fs_live_variables;
43 }
44
45 struct brw_gs_compile;
46
47 static inline fs_reg
48 offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
49 {
50 return offset(reg, bld.dispatch_width(), delta);
51 }
52
53 #define UBO_START ((1 << 16) - 4)
54
55 /**
56 * The fragment shader front-end.
57 *
58 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
59 */
60 class fs_visitor : public backend_shader
61 {
62 public:
63 fs_visitor(const struct brw_compiler *compiler, void *log_data,
64 void *mem_ctx,
65 const void *key,
66 struct brw_stage_prog_data *prog_data,
67 struct gl_program *prog,
68 const nir_shader *shader,
69 unsigned dispatch_width,
70 int shader_time_index,
71 const struct brw_vue_map *input_vue_map = NULL);
72 fs_visitor(const struct brw_compiler *compiler, void *log_data,
73 void *mem_ctx,
74 struct brw_gs_compile *gs_compile,
75 struct brw_gs_prog_data *prog_data,
76 const nir_shader *shader,
77 int shader_time_index);
78 void init();
79 ~fs_visitor();
80
81 fs_reg vgrf(const glsl_type *const type);
82 void import_uniforms(fs_visitor *v);
83 void setup_uniform_clipplane_values();
84 void compute_clip_distance();
85
86 fs_inst *get_instruction_generating_reg(fs_inst *start,
87 fs_inst *end,
88 const fs_reg &reg);
89
90 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
91 const fs_reg &dst,
92 const fs_reg &surf_index,
93 const fs_reg &varying_offset,
94 uint32_t const_offset);
95 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
96
97 bool run_fs(bool allow_spilling, bool do_rep_send);
98 bool run_vs();
99 bool run_tcs_single_patch();
100 bool run_tes();
101 bool run_gs();
102 bool run_cs(unsigned min_dispatch_width);
103 void optimize();
104 void allocate_registers(unsigned min_dispatch_width, bool allow_spilling);
105 void setup_fs_payload_gen4();
106 void setup_fs_payload_gen6();
107 void setup_vs_payload();
108 void setup_gs_payload();
109 void setup_cs_payload();
110 void fixup_3src_null_dest();
111 void assign_curb_setup();
112 void calculate_urb_setup();
113 void assign_urb_setup();
114 void convert_attr_sources_to_hw_regs(fs_inst *inst);
115 void assign_vs_urb_setup();
116 void assign_tcs_single_patch_urb_setup();
117 void assign_tes_urb_setup();
118 void assign_gs_urb_setup();
119 bool assign_regs(bool allow_spilling, bool spill_all);
120 void assign_regs_trivial();
121 void calculate_payload_ranges(int payload_node_count,
122 int *payload_last_use_ip);
123 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
124 int first_payload_node);
125 int choose_spill_reg(struct ra_graph *g);
126 void spill_reg(int spill_reg);
127 void split_virtual_grfs();
128 bool compact_virtual_grfs();
129 void assign_constant_locations();
130 bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
131 unsigned *out_pull_index);
132 void lower_constant_loads();
133 void invalidate_live_intervals();
134 void calculate_live_intervals();
135 void calculate_register_pressure();
136 void validate();
137 bool opt_algebraic();
138 bool opt_redundant_discard_jumps();
139 bool opt_cse();
140 bool opt_cse_local(bblock_t *block);
141 bool opt_copy_propagation();
142 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
143 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
144 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
145 exec_list *acp);
146 bool opt_drop_redundant_mov_to_flags();
147 bool opt_register_renaming();
148 bool register_coalesce();
149 bool compute_to_mrf();
150 bool eliminate_find_live_channel();
151 bool dead_code_eliminate();
152 bool remove_duplicate_mrf_writes();
153
154 bool opt_sampler_eot();
155 bool virtual_grf_interferes(int a, int b);
156 void schedule_instructions(instruction_scheduler_mode mode);
157 void insert_gen4_send_dependency_workarounds();
158 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
159 fs_inst *inst);
160 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
161 fs_inst *inst);
162 void vfail(const char *msg, va_list args);
163 void fail(const char *msg, ...);
164 void limit_dispatch_width(unsigned n, const char *msg);
165 void lower_uniform_pull_constant_loads();
166 bool lower_load_payload();
167 bool lower_pack();
168 bool lower_conversions();
169 bool lower_logical_sends();
170 bool lower_integer_multiplication();
171 bool lower_minmax();
172 bool lower_simd_width();
173 bool opt_combine_constants();
174
175 void emit_dummy_fs();
176 void emit_repclear_shader();
177 void emit_fragcoord_interpolation(fs_reg wpos);
178 fs_reg *emit_frontfacing_interpolation();
179 fs_reg *emit_samplepos_setup();
180 fs_reg *emit_sampleid_setup();
181 fs_reg *emit_samplemaskin_setup();
182 void emit_interpolation_setup_gen4();
183 void emit_interpolation_setup_gen6();
184 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
185 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
186 const fs_reg &sampler);
187 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
188 fs_reg resolve_source_modifiers(const fs_reg &src);
189 void emit_discard_jump();
190 bool opt_peephole_sel();
191 bool opt_peephole_predicated_break();
192 bool opt_saturate_propagation();
193 bool opt_cmod_propagation();
194 bool opt_zero_samples();
195
196 void emit_nir_code();
197 void nir_setup_outputs();
198 void nir_setup_uniforms();
199 void nir_emit_system_values();
200 void nir_emit_impl(nir_function_impl *impl);
201 void nir_emit_cf_list(exec_list *list);
202 void nir_emit_if(nir_if *if_stmt);
203 void nir_emit_loop(nir_loop *loop);
204 void nir_emit_block(nir_block *block);
205 void nir_emit_instr(nir_instr *instr);
206 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
207 void nir_emit_load_const(const brw::fs_builder &bld,
208 nir_load_const_instr *instr);
209 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
210 nir_intrinsic_instr *instr);
211 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
212 nir_intrinsic_instr *instr);
213 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
214 nir_intrinsic_instr *instr);
215 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
216 nir_intrinsic_instr *instr);
217 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
218 nir_intrinsic_instr *instr);
219 void nir_emit_intrinsic(const brw::fs_builder &bld,
220 nir_intrinsic_instr *instr);
221 void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
222 nir_intrinsic_instr *instr);
223 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
224 int op, nir_intrinsic_instr *instr);
225 void nir_emit_shared_atomic(const brw::fs_builder &bld,
226 int op, nir_intrinsic_instr *instr);
227 void nir_emit_texture(const brw::fs_builder &bld,
228 nir_tex_instr *instr);
229 void nir_emit_jump(const brw::fs_builder &bld,
230 nir_jump_instr *instr);
231 fs_reg get_nir_src(const nir_src &src);
232 fs_reg get_nir_src_imm(const nir_src &src);
233 fs_reg get_nir_dest(const nir_dest &dest);
234 fs_reg get_nir_image_deref(const nir_deref_var *deref);
235 fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
236 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
237 unsigned wr_mask);
238
239 bool optimize_extract_to_float(nir_alu_instr *instr,
240 const fs_reg &result);
241 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
242 const fs_reg &result);
243
244 void emit_alpha_test();
245 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
246 fs_reg color1, fs_reg color2,
247 fs_reg src0_alpha, unsigned components);
248 void emit_fb_writes();
249 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
250 const fs_reg &dst, unsigned target);
251 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
252 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
253 unsigned stream_id);
254 void emit_gs_control_data_bits(const fs_reg &vertex_count);
255 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
256 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
257 unsigned stream_id);
258 void emit_gs_thread_end();
259 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
260 unsigned base_offset, const nir_src &offset_src,
261 unsigned num_components, unsigned first_component);
262 void emit_cs_terminate();
263 fs_reg *emit_cs_work_group_id_setup();
264
265 void emit_barrier();
266
267 void emit_shader_time_begin();
268 void emit_shader_time_end();
269 void SHADER_TIME_ADD(const brw::fs_builder &bld,
270 int shader_time_subindex,
271 fs_reg value);
272
273 fs_reg get_timestamp(const brw::fs_builder &bld);
274
275 struct brw_reg interp_reg(int location, int channel);
276
277 int implied_mrf_writes(fs_inst *inst);
278
279 virtual void dump_instructions();
280 virtual void dump_instructions(const char *name);
281 void dump_instruction(backend_instruction *inst);
282 void dump_instruction(backend_instruction *inst, FILE *file);
283
284 const void *const key;
285 const struct brw_sampler_prog_key_data *key_tex;
286
287 struct brw_gs_compile *gs_compile;
288
289 struct brw_stage_prog_data *prog_data;
290 struct gl_program *prog;
291
292 const struct brw_vue_map *input_vue_map;
293
294 int *virtual_grf_start;
295 int *virtual_grf_end;
296 brw::fs_live_variables *live_intervals;
297
298 int *regs_live_at_ip;
299
300 /** Number of uniform variable components visited. */
301 unsigned uniforms;
302
303 /** Byte-offset for the next available spot in the scratch space buffer. */
304 unsigned last_scratch;
305
306 /**
307 * Array mapping UNIFORM register numbers to the pull parameter index,
308 * or -1 if this uniform register isn't being uploaded as a pull constant.
309 */
310 int *pull_constant_loc;
311
312 /**
313 * Array mapping UNIFORM register numbers to the push parameter index,
314 * or -1 if this uniform register isn't being uploaded as a push constant.
315 */
316 int *push_constant_loc;
317
318 fs_reg subgroup_id;
319 fs_reg frag_depth;
320 fs_reg frag_stencil;
321 fs_reg sample_mask;
322 fs_reg outputs[VARYING_SLOT_MAX];
323 fs_reg dual_src_output;
324 int first_non_payload_grf;
325 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
326 unsigned max_grf;
327
328 fs_reg *nir_locals;
329 fs_reg *nir_ssa_values;
330 fs_reg *nir_system_values;
331
332 bool failed;
333 char *fail_msg;
334
335 /** Register numbers for thread payload fields. */
336 struct thread_payload {
337 uint8_t source_depth_reg;
338 uint8_t source_w_reg;
339 uint8_t aa_dest_stencil_reg;
340 uint8_t dest_depth_reg;
341 uint8_t sample_pos_reg;
342 uint8_t sample_mask_in_reg;
343 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT];
344 uint8_t local_invocation_id_reg;
345
346 /** The number of thread payload registers the hardware will supply. */
347 uint8_t num_regs;
348 } payload;
349
350 bool source_depth_to_render_target;
351 bool runtime_check_aads_emit;
352
353 fs_reg pixel_x;
354 fs_reg pixel_y;
355 fs_reg wpos_w;
356 fs_reg pixel_w;
357 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
358 fs_reg shader_start_time;
359 fs_reg userplane[MAX_CLIP_PLANES];
360 fs_reg final_gs_vertex_count;
361 fs_reg control_data_bits;
362 fs_reg invocation_id;
363
364 unsigned grf_used;
365 bool spilled_any_registers;
366
367 const unsigned dispatch_width; /**< 8, 16 or 32 */
368 unsigned max_dispatch_width;
369
370 int shader_time_index;
371
372 unsigned promoted_constants;
373 brw::fs_builder bld;
374 };
375
376 /**
377 * The fragment shader code generator.
378 *
379 * Translates FS IR to actual i965 assembly code.
380 */
381 class fs_generator
382 {
383 public:
384 fs_generator(const struct brw_compiler *compiler, void *log_data,
385 void *mem_ctx,
386 const void *key,
387 struct brw_stage_prog_data *prog_data,
388 unsigned promoted_constants,
389 bool runtime_check_aads_emit,
390 gl_shader_stage stage);
391 ~fs_generator();
392
393 void enable_debug(const char *shader_name);
394 int generate_code(const cfg_t *cfg, int dispatch_width);
395 const unsigned *get_assembly(unsigned int *assembly_size);
396
397 private:
398 void fire_fb_write(fs_inst *inst,
399 struct brw_reg payload,
400 struct brw_reg implied_header,
401 GLuint nr);
402 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
403 void generate_fb_read(fs_inst *inst, struct brw_reg dst,
404 struct brw_reg payload);
405 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
406 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
407 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
408 void generate_barrier(fs_inst *inst, struct brw_reg src);
409 void generate_linterp(fs_inst *inst, struct brw_reg dst,
410 struct brw_reg *src);
411 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
412 struct brw_reg surface_index,
413 struct brw_reg sampler_index);
414 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
415 struct brw_reg src,
416 struct brw_reg surf_index);
417 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
418 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src);
419 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
420 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
421 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
422 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
423 struct brw_reg index,
424 struct brw_reg offset);
425 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
426 struct brw_reg dst,
427 struct brw_reg surf_index,
428 struct brw_reg payload);
429 void generate_varying_pull_constant_load_gen4(fs_inst *inst,
430 struct brw_reg dst,
431 struct brw_reg index);
432 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
433 struct brw_reg dst,
434 struct brw_reg index,
435 struct brw_reg offset);
436 void generate_mov_dispatch_to_flags(fs_inst *inst);
437
438 void generate_pixel_interpolator_query(fs_inst *inst,
439 struct brw_reg dst,
440 struct brw_reg src,
441 struct brw_reg msg_data,
442 unsigned msg_type);
443
444 void generate_set_sample_id(fs_inst *inst,
445 struct brw_reg dst,
446 struct brw_reg src0,
447 struct brw_reg src1);
448
449 void generate_discard_jump(fs_inst *inst);
450
451 void generate_pack_half_2x16_split(fs_inst *inst,
452 struct brw_reg dst,
453 struct brw_reg x,
454 struct brw_reg y);
455 void generate_unpack_half_2x16_split(fs_inst *inst,
456 struct brw_reg dst,
457 struct brw_reg src);
458
459 void generate_shader_time_add(fs_inst *inst,
460 struct brw_reg payload,
461 struct brw_reg offset,
462 struct brw_reg value);
463
464 void generate_mov_indirect(fs_inst *inst,
465 struct brw_reg dst,
466 struct brw_reg reg,
467 struct brw_reg indirect_byte_offset);
468
469 bool patch_discard_jumps_to_fb_writes();
470
471 const struct brw_compiler *compiler;
472 void *log_data; /* Passed to compiler->*_log functions */
473
474 const struct gen_device_info *devinfo;
475
476 struct brw_codegen *p;
477 const void * const key;
478 struct brw_stage_prog_data * const prog_data;
479
480 unsigned dispatch_width; /**< 8, 16 or 32 */
481
482 exec_list discard_halt_patches;
483 unsigned promoted_constants;
484 bool runtime_check_aads_emit;
485 bool debug_flag;
486 const char *shader_name;
487 gl_shader_stage stage;
488 void *mem_ctx;
489 };
490
491 void shuffle_32bit_load_result_to_64bit_data(const brw::fs_builder &bld,
492 const fs_reg &dst,
493 const fs_reg &src,
494 uint32_t components);
495
496 fs_reg shuffle_64bit_data_for_32bit_write(const brw::fs_builder &bld,
497 const fs_reg &src,
498 uint32_t components);
499 fs_reg setup_imm_df(const brw::fs_builder &bld,
500 double v);
501
502 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
503 nir_intrinsic_op op);
504
505 #endif /* BRW_FS_H */