src/intel/compiler/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #ifndef BRW_FS_H
  29 #define BRW_FS_H
  30
  31 #include "brw_shader.h"
  32 #include "brw_ir_fs.h"
  33 #include "brw_fs_builder.h"
  34 #include "compiler/nir/nir.h"
  35
  36 struct bblock_t;
  37 namespace {
  38    struct acp_entry;
  39 }
  40
  41 namespace brw {
  42    class fs_live_variables;
  43 }
  44
  45 struct brw_gs_compile;
  46
  47 static inline fs_reg
  48 offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
  49 {
  50    return offset(reg, bld.dispatch_width(), delta);
  51 }
  52
  53 #define UBO_START ((1 << 16) - 4)
  54
  55 struct shader_stats {
  56    const char *scheduler_mode;
  57    unsigned promoted_constants;
  58 };
  59
  60 /**
  61  * The fragment shader front-end.
  62  *
  63  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
  64  */
  65 class fs_visitor : public backend_shader
  66 {
  67 public:
  68    fs_visitor(const struct brw_compiler *compiler, void *log_data,
  69               void *mem_ctx,
  70               const brw_base_prog_key *key,
  71               struct brw_stage_prog_data *prog_data,
  72               const nir_shader *shader,
  73               unsigned dispatch_width,
  74               int shader_time_index,
  75               const struct brw_vue_map *input_vue_map = NULL);
  76    fs_visitor(const struct brw_compiler *compiler, void *log_data,
  77               void *mem_ctx,
  78               struct brw_gs_compile *gs_compile,
  79               struct brw_gs_prog_data *prog_data,
  80               const nir_shader *shader,
  81               int shader_time_index);
  82    void init();
  83    ~fs_visitor();
  84
  85    fs_reg vgrf(const glsl_type *const type);
  86    void import_uniforms(fs_visitor *v);
  87
  88    void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
  89                                    const fs_reg &dst,
  90                                    const fs_reg &surf_index,
  91                                    const fs_reg &varying_offset,
  92                                    uint32_t const_offset);
  93    void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
  94
  95    bool run_fs(bool allow_spilling, bool do_rep_send);
  96    bool run_vs();
  97    bool run_tcs();
  98    bool run_tes();
  99    bool run_gs();
 100    bool run_cs(unsigned min_dispatch_width);
 101    void optimize();
 102    void allocate_registers(unsigned min_dispatch_width, bool allow_spilling);
 103    void setup_fs_payload_gen4();
 104    void setup_fs_payload_gen6();
 105    void setup_vs_payload();
 106    void setup_gs_payload();
 107    void setup_cs_payload();
 108    bool fixup_sends_duplicate_payload();
 109    void fixup_3src_null_dest();
 110    void assign_curb_setup();
 111    void assign_urb_setup();
 112    void convert_attr_sources_to_hw_regs(fs_inst *inst);
 113    void assign_vs_urb_setup();
 114    void assign_tcs_urb_setup();
 115    void assign_tes_urb_setup();
 116    void assign_gs_urb_setup();
 117    bool assign_regs(bool allow_spilling, bool spill_all);
 118    void assign_regs_trivial();
 119    void calculate_payload_ranges(int payload_node_count,
 120                                  int *payload_last_use_ip);
 121    void split_virtual_grfs();
 122    bool compact_virtual_grfs();
 123    void assign_constant_locations();
 124    bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
 125                       unsigned *out_pull_index);
 126    void lower_constant_loads();
 127    void invalidate_live_intervals();
 128    void calculate_live_intervals();
 129    void calculate_register_pressure();
 130    void validate();
 131    bool opt_algebraic();
 132    bool opt_redundant_discard_jumps();
 133    bool opt_cse();
 134    bool opt_cse_local(bblock_t *block);
 135    bool opt_copy_propagation();
 136    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 137    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 138    bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
 139                                    exec_list *acp);
 140    bool opt_drop_redundant_mov_to_flags();
 141    bool opt_register_renaming();
 142    bool opt_bank_conflicts();
 143    unsigned bank_conflict_cycles(const fs_inst *inst) const;
 144    bool register_coalesce();
 145    bool compute_to_mrf();
 146    bool eliminate_find_live_channel();
 147    bool dead_code_eliminate();
 148    bool remove_duplicate_mrf_writes();
 149    bool remove_extra_rounding_modes();
 150
 151    bool opt_sampler_eot();
 152    bool virtual_grf_interferes(int a, int b);
 153    void schedule_instructions(instruction_scheduler_mode mode);
 154    void insert_gen4_send_dependency_workarounds();
 155    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 156                                                     fs_inst *inst);
 157    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 158                                                      fs_inst *inst);
 159    void vfail(const char *msg, va_list args);
 160    void fail(const char *msg, ...);
 161    void limit_dispatch_width(unsigned n, const char *msg);
 162    void lower_uniform_pull_constant_loads();
 163    bool lower_load_payload();
 164    bool lower_pack();
 165    bool lower_regioning();
 166    bool lower_logical_sends();
 167    bool lower_integer_multiplication();
 168    bool lower_minmax();
 169    bool lower_simd_width();
 170    bool lower_scoreboard();
 171    bool opt_combine_constants();
 172
 173    void emit_dummy_fs();
 174    void emit_repclear_shader();
 175    void emit_fragcoord_interpolation(fs_reg wpos);
 176    fs_reg *emit_frontfacing_interpolation();
 177    fs_reg *emit_samplepos_setup();
 178    fs_reg *emit_sampleid_setup();
 179    fs_reg *emit_samplemaskin_setup();
 180    void emit_interpolation_setup_gen4();
 181    void emit_interpolation_setup_gen6();
 182    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 183    fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
 184                          const fs_reg &texture,
 185                          const fs_reg &texture_handle);
 186    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 187    fs_reg resolve_source_modifiers(const fs_reg &src);
 188    void emit_discard_jump();
 189    void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr,
 190                    fs_reg result, fs_reg *op, unsigned fsign_src);
 191    void emit_shader_float_controls_execution_mode();
 192    bool opt_peephole_sel();
 193    bool opt_peephole_predicated_break();
 194    bool opt_saturate_propagation();
 195    bool opt_cmod_propagation();
 196    bool opt_zero_samples();
 197
 198    void set_tcs_invocation_id();
 199
 200    void emit_nir_code();
 201    void nir_setup_outputs();
 202    void nir_setup_uniforms();
 203    void nir_emit_system_values();
 204    void nir_emit_impl(nir_function_impl *impl);
 205    void nir_emit_cf_list(exec_list *list);
 206    void nir_emit_if(nir_if *if_stmt);
 207    void nir_emit_loop(nir_loop *loop);
 208    void nir_emit_block(nir_block *block);
 209    void nir_emit_instr(nir_instr *instr);
 210    void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr,
 211                      bool need_dest);
 212    bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result,
 213                               nir_alu_instr *instr);
 214    void nir_emit_load_const(const brw::fs_builder &bld,
 215                             nir_load_const_instr *instr);
 216    void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
 217                               nir_intrinsic_instr *instr);
 218    void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
 219                                nir_intrinsic_instr *instr);
 220    void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
 221                               nir_intrinsic_instr *instr);
 222    void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
 223                               nir_intrinsic_instr *instr);
 224    void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
 225                               nir_intrinsic_instr *instr);
 226    fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
 227                                         nir_intrinsic_instr *instr);
 228    fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
 229                                        nir_intrinsic_instr *instr);
 230    fs_reg swizzle_nir_scratch_addr(const brw::fs_builder &bld,
 231                                    const fs_reg &addr,
 232                                    bool in_dwords);
 233    void nir_emit_intrinsic(const brw::fs_builder &bld,
 234                            nir_intrinsic_instr *instr);
 235    void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
 236                                nir_intrinsic_instr *instr);
 237    void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
 238                              int op, nir_intrinsic_instr *instr);
 239    void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld,
 240                                    int op, nir_intrinsic_instr *instr);
 241    void nir_emit_shared_atomic(const brw::fs_builder &bld,
 242                                int op, nir_intrinsic_instr *instr);
 243    void nir_emit_shared_atomic_float(const brw::fs_builder &bld,
 244                                      int op, nir_intrinsic_instr *instr);
 245    void nir_emit_global_atomic(const brw::fs_builder &bld,
 246                                int op, nir_intrinsic_instr *instr);
 247    void nir_emit_global_atomic_float(const brw::fs_builder &bld,
 248                                      int op, nir_intrinsic_instr *instr);
 249    void nir_emit_texture(const brw::fs_builder &bld,
 250                          nir_tex_instr *instr);
 251    void nir_emit_jump(const brw::fs_builder &bld,
 252                       nir_jump_instr *instr);
 253    fs_reg get_nir_src(const nir_src &src);
 254    fs_reg get_nir_src_imm(const nir_src &src);
 255    fs_reg get_nir_dest(const nir_dest &dest);
 256    fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
 257    fs_reg get_tcs_single_patch_icp_handle(const brw::fs_builder &bld,
 258                                           nir_intrinsic_instr *instr);
 259    fs_reg get_tcs_eight_patch_icp_handle(const brw::fs_builder &bld,
 260                                          nir_intrinsic_instr *instr);
 261    struct brw_reg get_tcs_output_urb_handle();
 262
 263    void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
 264                      unsigned wr_mask);
 265
 266    bool optimize_extract_to_float(nir_alu_instr *instr,
 267                                   const fs_reg &result);
 268    bool optimize_frontfacing_ternary(nir_alu_instr *instr,
 269                                      const fs_reg &result);
 270
 271    void emit_alpha_test();
 272    fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
 273                                  fs_reg color1, fs_reg color2,
 274                                  fs_reg src0_alpha, unsigned components);
 275    void emit_alpha_to_coverage_workaround(const fs_reg &src0_alpha);
 276    void emit_fb_writes();
 277    fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
 278                                       const fs_reg &dst, unsigned target);
 279    void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
 280    void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
 281                                         unsigned stream_id);
 282    void emit_gs_control_data_bits(const fs_reg &vertex_count);
 283    void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
 284    void emit_gs_vertex(const nir_src &vertex_count_nir_src,
 285                        unsigned stream_id);
 286    void emit_gs_thread_end();
 287    void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
 288                            unsigned base_offset, const nir_src &offset_src,
 289                            unsigned num_components, unsigned first_component);
 290    void emit_cs_terminate();
 291    fs_reg *emit_cs_work_group_id_setup();
 292
 293    void emit_barrier();
 294
 295    void emit_shader_time_begin();
 296    void emit_shader_time_end();
 297    void SHADER_TIME_ADD(const brw::fs_builder &bld,
 298                         int shader_time_subindex,
 299                         fs_reg value);
 300
 301    fs_reg get_timestamp(const brw::fs_builder &bld);
 302
 303    fs_reg interp_reg(int location, int channel);
 304
 305    int implied_mrf_writes(const fs_inst *inst) const;
 306
 307    virtual void dump_instructions();
 308    virtual void dump_instructions(const char *name);
 309    void dump_instruction(backend_instruction *inst);
 310    void dump_instruction(backend_instruction *inst, FILE *file);
 311
 312    const brw_base_prog_key *const key;
 313    const struct brw_sampler_prog_key_data *key_tex;
 314
 315    struct brw_gs_compile *gs_compile;
 316
 317    struct brw_stage_prog_data *prog_data;
 318
 319    const struct brw_vue_map *input_vue_map;
 320
 321    int *virtual_grf_start;
 322    int *virtual_grf_end;
 323    brw::fs_live_variables *live_intervals;
 324
 325    int *regs_live_at_ip;
 326
 327    /** Number of uniform variable components visited. */
 328    unsigned uniforms;
 329
 330    /** Byte-offset for the next available spot in the scratch space buffer. */
 331    unsigned last_scratch;
 332
 333    /**
 334     * Array mapping UNIFORM register numbers to the pull parameter index,
 335     * or -1 if this uniform register isn't being uploaded as a pull constant.
 336     */
 337    int *pull_constant_loc;
 338
 339    /**
 340     * Array mapping UNIFORM register numbers to the push parameter index,
 341     * or -1 if this uniform register isn't being uploaded as a push constant.
 342     */
 343    int *push_constant_loc;
 344
 345    fs_reg subgroup_id;
 346    fs_reg scratch_base;
 347    fs_reg frag_depth;
 348    fs_reg frag_stencil;
 349    fs_reg sample_mask;
 350    fs_reg outputs[VARYING_SLOT_MAX];
 351    fs_reg dual_src_output;
 352    int first_non_payload_grf;
 353    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 354    unsigned max_grf;
 355
 356    fs_reg *nir_locals;
 357    fs_reg *nir_ssa_values;
 358    fs_reg *nir_system_values;
 359
 360    bool failed;
 361    char *fail_msg;
 362
 363    /** Register numbers for thread payload fields. */
 364    struct thread_payload {
 365       uint8_t subspan_coord_reg[2];
 366       uint8_t source_depth_reg[2];
 367       uint8_t source_w_reg[2];
 368       uint8_t aa_dest_stencil_reg[2];
 369       uint8_t dest_depth_reg[2];
 370       uint8_t sample_pos_reg[2];
 371       uint8_t sample_mask_in_reg[2];
 372       uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
 373       uint8_t local_invocation_id_reg[2];
 374
 375       /** The number of thread payload registers the hardware will supply. */
 376       uint8_t num_regs;
 377    } payload;
 378
 379    bool source_depth_to_render_target;
 380    bool runtime_check_aads_emit;
 381
 382    fs_reg pixel_x;
 383    fs_reg pixel_y;
 384    fs_reg wpos_w;
 385    fs_reg pixel_w;
 386    fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
 387    fs_reg shader_start_time;
 388    fs_reg final_gs_vertex_count;
 389    fs_reg control_data_bits;
 390    fs_reg invocation_id;
 391
 392    unsigned grf_used;
 393    bool spilled_any_registers;
 394
 395    const unsigned dispatch_width; /**< 8, 16 or 32 */
 396    unsigned max_dispatch_width;
 397
 398    int shader_time_index;
 399
 400    struct shader_stats shader_stats;
 401
 402    brw::fs_builder bld;
 403
 404 private:
 405    fs_reg prepare_alu_destination_and_sources(const brw::fs_builder &bld,
 406                                               nir_alu_instr *instr,
 407                                               fs_reg *op,
 408                                               bool need_dest);
 409
 410    void resolve_inot_sources(const brw::fs_builder &bld, nir_alu_instr *instr,
 411                              fs_reg *op);
 412    void lower_mul_dword_inst(fs_inst *inst, bblock_t *block);
 413    void lower_mul_qword_inst(fs_inst *inst, bblock_t *block);
 414    void lower_mulh_inst(fs_inst *inst, bblock_t *block);
 415 };
 416
 417 /**
 418  * The fragment shader code generator.
 419  *
 420  * Translates FS IR to actual i965 assembly code.
 421  */
 422 class fs_generator
 423 {
 424 public:
 425    fs_generator(const struct brw_compiler *compiler, void *log_data,
 426                 void *mem_ctx,
 427                 struct brw_stage_prog_data *prog_data,
 428                 struct shader_stats shader_stats,
 429                 bool runtime_check_aads_emit,
 430                 gl_shader_stage stage);
 431    ~fs_generator();
 432
 433    void enable_debug(const char *shader_name);
 434    int generate_code(const cfg_t *cfg, int dispatch_width,
 435                      struct brw_compile_stats *stats);
 436    const unsigned *get_assembly();
 437
 438 private:
 439    void fire_fb_write(fs_inst *inst,
 440                       struct brw_reg payload,
 441                       struct brw_reg implied_header,
 442                       GLuint nr);
 443    void generate_send(fs_inst *inst,
 444                       struct brw_reg dst,
 445                       struct brw_reg desc,
 446                       struct brw_reg ex_desc,
 447                       struct brw_reg payload,
 448                       struct brw_reg payload2);
 449    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 450    void generate_fb_read(fs_inst *inst, struct brw_reg dst,
 451                          struct brw_reg payload);
 452    void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
 453    void generate_urb_write(fs_inst *inst, struct brw_reg payload);
 454    void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
 455    void generate_barrier(fs_inst *inst, struct brw_reg src);
 456    bool generate_linterp(fs_inst *inst, struct brw_reg dst,
 457                          struct brw_reg *src);
 458    void generate_tex(fs_inst *inst, struct brw_reg dst,
 459                      struct brw_reg surface_index,
 460                      struct brw_reg sampler_index);
 461    void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
 462                                  struct brw_reg src,
 463                                  struct brw_reg surf_index);
 464    void generate_ddx(const fs_inst *inst,
 465                      struct brw_reg dst, struct brw_reg src);
 466    void generate_ddy(const fs_inst *inst,
 467                      struct brw_reg dst, struct brw_reg src);
 468    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 469    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 470    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 471    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 472                                             struct brw_reg index,
 473                                             struct brw_reg offset);
 474    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 475                                                  struct brw_reg dst,
 476                                                  struct brw_reg surf_index,
 477                                                  struct brw_reg payload);
 478    void generate_varying_pull_constant_load_gen4(fs_inst *inst,
 479                                                  struct brw_reg dst,
 480                                                  struct brw_reg index);
 481    void generate_mov_dispatch_to_flags(fs_inst *inst);
 482
 483    void generate_pixel_interpolator_query(fs_inst *inst,
 484                                           struct brw_reg dst,
 485                                           struct brw_reg src,
 486                                           struct brw_reg msg_data,
 487                                           unsigned msg_type);
 488
 489    void generate_set_sample_id(fs_inst *inst,
 490                                struct brw_reg dst,
 491                                struct brw_reg src0,
 492                                struct brw_reg src1);
 493
 494    void generate_discard_jump(fs_inst *inst);
 495
 496    void generate_pack_half_2x16_split(fs_inst *inst,
 497                                       struct brw_reg dst,
 498                                       struct brw_reg x,
 499                                       struct brw_reg y);
 500
 501    void generate_shader_time_add(fs_inst *inst,
 502                                  struct brw_reg payload,
 503                                  struct brw_reg offset,
 504                                  struct brw_reg value);
 505
 506    void generate_mov_indirect(fs_inst *inst,
 507                               struct brw_reg dst,
 508                               struct brw_reg reg,
 509                               struct brw_reg indirect_byte_offset);
 510
 511    void generate_shuffle(fs_inst *inst,
 512                          struct brw_reg dst,
 513                          struct brw_reg src,
 514                          struct brw_reg idx);
 515
 516    void generate_quad_swizzle(const fs_inst *inst,
 517                               struct brw_reg dst, struct brw_reg src,
 518                               unsigned swiz);
 519
 520    bool patch_discard_jumps_to_fb_writes();
 521
 522    const struct brw_compiler *compiler;
 523    void *log_data; /* Passed to compiler->*_log functions */
 524
 525    const struct gen_device_info *devinfo;
 526
 527    struct brw_codegen *p;
 528    struct brw_stage_prog_data * const prog_data;
 529
 530    unsigned dispatch_width; /**< 8, 16 or 32 */
 531
 532    exec_list discard_halt_patches;
 533    struct shader_stats shader_stats;
 534    bool runtime_check_aads_emit;
 535    bool debug_flag;
 536    const char *shader_name;
 537    gl_shader_stage stage;
 538    void *mem_ctx;
 539 };
 540
 541 namespace brw {
 542    inline fs_reg
 543    fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
 544                      brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1)
 545    {
 546       if (!regs[0])
 547          return fs_reg();
 548
 549       if (bld.dispatch_width() > 16) {
 550          const fs_reg tmp = bld.vgrf(type, n);
 551          const brw::fs_builder hbld = bld.exec_all().group(16, 0);
 552          const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
 553          fs_reg *const components = new fs_reg[n * m];
 554
 555          for (unsigned c = 0; c < n; c++) {
 556             for (unsigned g = 0; g < m; g++) {
 557                components[c * m + g] =
 558                   offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c);
 559             }
 560          }
 561
 562          hbld.LOAD_PAYLOAD(tmp, components, n * m, 0);
 563
 564          delete[] components;
 565          return tmp;
 566
 567       } else {
 568          return fs_reg(retype(brw_vec8_grf(regs[0], 0), type));
 569       }
 570    }
 571
 572    bool
 573    lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
 574 }
 575
 576 void shuffle_from_32bit_read(const brw::fs_builder &bld,
 577                              const fs_reg &dst,
 578                              const fs_reg &src,
 579                              uint32_t first_component,
 580                              uint32_t components);
 581
 582 fs_reg setup_imm_df(const brw::fs_builder &bld,
 583                     double v);
 584
 585 fs_reg setup_imm_b(const brw::fs_builder &bld,
 586                    int8_t v);
 587
 588 fs_reg setup_imm_ub(const brw::fs_builder &bld,
 589                    uint8_t v);
 590
 591 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
 592                                                nir_intrinsic_op op);
 593
 594 uint32_t brw_fb_write_msg_control(const fs_inst *inst,
 595                                   const struct brw_wm_prog_data *prog_data);
 596
 597
 598 #endif /* BRW_FS_H */