intel/compiler: Implement TCS 8_PATCH mode and INTEL_DEBUG=tcs8
[mesa.git] / src / intel / compiler / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #ifndef BRW_FS_H
29 #define BRW_FS_H
30
31 #include "brw_shader.h"
32 #include "brw_ir_fs.h"
33 #include "brw_fs_builder.h"
34 #include "compiler/nir/nir.h"
35
36 struct bblock_t;
37 namespace {
38 struct acp_entry;
39 }
40
41 namespace brw {
42 class fs_live_variables;
43 }
44
45 struct brw_gs_compile;
46
47 static inline fs_reg
48 offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
49 {
50 return offset(reg, bld.dispatch_width(), delta);
51 }
52
53 #define UBO_START ((1 << 16) - 4)
54
55 /**
56 * The fragment shader front-end.
57 *
58 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
59 */
60 class fs_visitor : public backend_shader
61 {
62 public:
63 fs_visitor(const struct brw_compiler *compiler, void *log_data,
64 void *mem_ctx,
65 const void *key,
66 struct brw_stage_prog_data *prog_data,
67 struct gl_program *prog,
68 const nir_shader *shader,
69 unsigned dispatch_width,
70 int shader_time_index,
71 const struct brw_vue_map *input_vue_map = NULL);
72 fs_visitor(const struct brw_compiler *compiler, void *log_data,
73 void *mem_ctx,
74 struct brw_gs_compile *gs_compile,
75 struct brw_gs_prog_data *prog_data,
76 const nir_shader *shader,
77 int shader_time_index);
78 void init();
79 ~fs_visitor();
80
81 fs_reg vgrf(const glsl_type *const type);
82 void import_uniforms(fs_visitor *v);
83 void setup_uniform_clipplane_values();
84 void compute_clip_distance();
85
86 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
87 const fs_reg &dst,
88 const fs_reg &surf_index,
89 const fs_reg &varying_offset,
90 uint32_t const_offset);
91 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
92
93 bool run_fs(bool allow_spilling, bool do_rep_send);
94 bool run_vs();
95 bool run_tcs();
96 bool run_tes();
97 bool run_gs();
98 bool run_cs(unsigned min_dispatch_width);
99 void optimize();
100 void allocate_registers(unsigned min_dispatch_width, bool allow_spilling);
101 void setup_fs_payload_gen4();
102 void setup_fs_payload_gen6();
103 void setup_vs_payload();
104 void setup_gs_payload();
105 void setup_cs_payload();
106 bool fixup_sends_duplicate_payload();
107 void fixup_3src_null_dest();
108 void assign_curb_setup();
109 void calculate_urb_setup();
110 void assign_urb_setup();
111 void convert_attr_sources_to_hw_regs(fs_inst *inst);
112 void assign_vs_urb_setup();
113 void assign_tcs_urb_setup();
114 void assign_tes_urb_setup();
115 void assign_gs_urb_setup();
116 bool assign_regs(bool allow_spilling, bool spill_all);
117 void assign_regs_trivial();
118 void calculate_payload_ranges(int payload_node_count,
119 int *payload_last_use_ip);
120 void split_virtual_grfs();
121 bool compact_virtual_grfs();
122 void assign_constant_locations();
123 bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
124 unsigned *out_pull_index);
125 void lower_constant_loads();
126 void invalidate_live_intervals();
127 void calculate_live_intervals();
128 void calculate_register_pressure();
129 void validate();
130 bool opt_algebraic();
131 bool opt_redundant_discard_jumps();
132 bool opt_cse();
133 bool opt_cse_local(bblock_t *block);
134 bool opt_copy_propagation();
135 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
136 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
137 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
138 exec_list *acp);
139 bool opt_drop_redundant_mov_to_flags();
140 bool opt_register_renaming();
141 bool opt_bank_conflicts();
142 unsigned bank_conflict_cycles(const fs_inst *inst) const;
143 bool register_coalesce();
144 bool compute_to_mrf();
145 bool eliminate_find_live_channel();
146 bool dead_code_eliminate();
147 bool remove_duplicate_mrf_writes();
148 bool remove_extra_rounding_modes();
149
150 bool opt_sampler_eot();
151 bool virtual_grf_interferes(int a, int b);
152 void schedule_instructions(instruction_scheduler_mode mode);
153 void insert_gen4_send_dependency_workarounds();
154 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
155 fs_inst *inst);
156 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
157 fs_inst *inst);
158 void vfail(const char *msg, va_list args);
159 void fail(const char *msg, ...);
160 void limit_dispatch_width(unsigned n, const char *msg);
161 void lower_uniform_pull_constant_loads();
162 bool lower_load_payload();
163 bool lower_pack();
164 bool lower_regioning();
165 bool lower_logical_sends();
166 bool lower_linterp();
167 bool lower_integer_multiplication();
168 bool lower_minmax();
169 bool lower_simd_width();
170 bool opt_combine_constants();
171
172 void emit_dummy_fs();
173 void emit_repclear_shader();
174 void emit_fragcoord_interpolation(fs_reg wpos);
175 fs_reg *emit_frontfacing_interpolation();
176 fs_reg *emit_samplepos_setup();
177 fs_reg *emit_sampleid_setup();
178 fs_reg *emit_samplemaskin_setup();
179 void emit_interpolation_setup_gen4();
180 void emit_interpolation_setup_gen6();
181 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
182 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
183 const fs_reg &texture,
184 const fs_reg &texture_handle);
185 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
186 fs_reg resolve_source_modifiers(const fs_reg &src);
187 void emit_discard_jump();
188 void emit_fsign(const class brw::fs_builder &, const nir_alu_instr *instr,
189 fs_reg result, fs_reg *op, unsigned fsign_src);
190 bool opt_peephole_sel();
191 bool opt_peephole_csel();
192 bool opt_peephole_predicated_break();
193 bool opt_saturate_propagation();
194 bool opt_cmod_propagation();
195 bool opt_zero_samples();
196
197 void set_tcs_invocation_id();
198
199 void emit_nir_code();
200 void nir_setup_outputs();
201 void nir_setup_uniforms();
202 void nir_emit_system_values();
203 void nir_emit_impl(nir_function_impl *impl);
204 void nir_emit_cf_list(exec_list *list);
205 void nir_emit_if(nir_if *if_stmt);
206 void nir_emit_loop(nir_loop *loop);
207 void nir_emit_block(nir_block *block);
208 void nir_emit_instr(nir_instr *instr);
209 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
210 bool try_emit_b2fi_of_inot(const brw::fs_builder &bld, fs_reg result,
211 nir_alu_instr *instr);
212 void nir_emit_load_const(const brw::fs_builder &bld,
213 nir_load_const_instr *instr);
214 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
215 nir_intrinsic_instr *instr);
216 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
217 nir_intrinsic_instr *instr);
218 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
219 nir_intrinsic_instr *instr);
220 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
221 nir_intrinsic_instr *instr);
222 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
223 nir_intrinsic_instr *instr);
224 fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
225 nir_intrinsic_instr *instr);
226 fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
227 nir_intrinsic_instr *instr);
228 void nir_emit_intrinsic(const brw::fs_builder &bld,
229 nir_intrinsic_instr *instr);
230 void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
231 nir_intrinsic_instr *instr);
232 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
233 int op, nir_intrinsic_instr *instr);
234 void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld,
235 int op, nir_intrinsic_instr *instr);
236 void nir_emit_shared_atomic(const brw::fs_builder &bld,
237 int op, nir_intrinsic_instr *instr);
238 void nir_emit_shared_atomic_float(const brw::fs_builder &bld,
239 int op, nir_intrinsic_instr *instr);
240 void nir_emit_global_atomic(const brw::fs_builder &bld,
241 int op, nir_intrinsic_instr *instr);
242 void nir_emit_global_atomic_float(const brw::fs_builder &bld,
243 int op, nir_intrinsic_instr *instr);
244 void nir_emit_texture(const brw::fs_builder &bld,
245 nir_tex_instr *instr);
246 void nir_emit_jump(const brw::fs_builder &bld,
247 nir_jump_instr *instr);
248 fs_reg get_nir_src(const nir_src &src);
249 fs_reg get_nir_src_imm(const nir_src &src);
250 fs_reg get_nir_dest(const nir_dest &dest);
251 fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
252 fs_reg get_tcs_single_patch_icp_handle(const brw::fs_builder &bld,
253 nir_intrinsic_instr *instr);
254 fs_reg get_tcs_eight_patch_icp_handle(const brw::fs_builder &bld,
255 nir_intrinsic_instr *instr);
256 struct brw_reg get_tcs_output_urb_handle();
257
258 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
259 unsigned wr_mask);
260
261 bool optimize_extract_to_float(nir_alu_instr *instr,
262 const fs_reg &result);
263 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
264 const fs_reg &result);
265
266 void emit_alpha_test();
267 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
268 fs_reg color1, fs_reg color2,
269 fs_reg src0_alpha, unsigned components);
270 void emit_alpha_to_coverage_workaround(const fs_reg &src0_alpha);
271 void emit_fb_writes();
272 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
273 const fs_reg &dst, unsigned target);
274 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
275 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
276 unsigned stream_id);
277 void emit_gs_control_data_bits(const fs_reg &vertex_count);
278 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
279 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
280 unsigned stream_id);
281 void emit_gs_thread_end();
282 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
283 unsigned base_offset, const nir_src &offset_src,
284 unsigned num_components, unsigned first_component);
285 void emit_cs_terminate();
286 fs_reg *emit_cs_work_group_id_setup();
287
288 void emit_barrier();
289
290 void emit_shader_time_begin();
291 void emit_shader_time_end();
292 void SHADER_TIME_ADD(const brw::fs_builder &bld,
293 int shader_time_subindex,
294 fs_reg value);
295
296 fs_reg get_timestamp(const brw::fs_builder &bld);
297
298 fs_reg interp_reg(int location, int channel);
299
300 int implied_mrf_writes(fs_inst *inst) const;
301
302 virtual void dump_instructions();
303 virtual void dump_instructions(const char *name);
304 void dump_instruction(backend_instruction *inst);
305 void dump_instruction(backend_instruction *inst, FILE *file);
306
307 const void *const key;
308 const struct brw_sampler_prog_key_data *key_tex;
309
310 struct brw_gs_compile *gs_compile;
311
312 struct brw_stage_prog_data *prog_data;
313 struct gl_program *prog;
314
315 const struct brw_vue_map *input_vue_map;
316
317 int *virtual_grf_start;
318 int *virtual_grf_end;
319 brw::fs_live_variables *live_intervals;
320
321 int *regs_live_at_ip;
322
323 /** Number of uniform variable components visited. */
324 unsigned uniforms;
325
326 /** Byte-offset for the next available spot in the scratch space buffer. */
327 unsigned last_scratch;
328
329 /**
330 * Array mapping UNIFORM register numbers to the pull parameter index,
331 * or -1 if this uniform register isn't being uploaded as a pull constant.
332 */
333 int *pull_constant_loc;
334
335 /**
336 * Array mapping UNIFORM register numbers to the push parameter index,
337 * or -1 if this uniform register isn't being uploaded as a push constant.
338 */
339 int *push_constant_loc;
340
341 fs_reg subgroup_id;
342 fs_reg frag_depth;
343 fs_reg frag_stencil;
344 fs_reg sample_mask;
345 fs_reg outputs[VARYING_SLOT_MAX];
346 fs_reg dual_src_output;
347 int first_non_payload_grf;
348 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
349 unsigned max_grf;
350
351 fs_reg *nir_locals;
352 fs_reg *nir_ssa_values;
353 fs_reg *nir_system_values;
354
355 bool failed;
356 char *fail_msg;
357
358 /** Register numbers for thread payload fields. */
359 struct thread_payload {
360 uint8_t subspan_coord_reg[2];
361 uint8_t source_depth_reg[2];
362 uint8_t source_w_reg[2];
363 uint8_t aa_dest_stencil_reg[2];
364 uint8_t dest_depth_reg[2];
365 uint8_t sample_pos_reg[2];
366 uint8_t sample_mask_in_reg[2];
367 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
368 uint8_t local_invocation_id_reg[2];
369
370 /** The number of thread payload registers the hardware will supply. */
371 uint8_t num_regs;
372 } payload;
373
374 bool source_depth_to_render_target;
375 bool runtime_check_aads_emit;
376
377 fs_reg pixel_x;
378 fs_reg pixel_y;
379 fs_reg wpos_w;
380 fs_reg pixel_w;
381 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
382 fs_reg shader_start_time;
383 fs_reg userplane[MAX_CLIP_PLANES];
384 fs_reg final_gs_vertex_count;
385 fs_reg control_data_bits;
386 fs_reg invocation_id;
387
388 unsigned grf_used;
389 bool spilled_any_registers;
390
391 const unsigned dispatch_width; /**< 8, 16 or 32 */
392 unsigned max_dispatch_width;
393
394 int shader_time_index;
395
396 unsigned promoted_constants;
397 brw::fs_builder bld;
398
399 private:
400 fs_reg prepare_alu_destination_and_sources(const brw::fs_builder &bld,
401 nir_alu_instr *instr,
402 fs_reg *op,
403 bool need_dest);
404
405 void resolve_inot_sources(const brw::fs_builder &bld, nir_alu_instr *instr,
406 fs_reg *op);
407 };
408
409 /**
410 * The fragment shader code generator.
411 *
412 * Translates FS IR to actual i965 assembly code.
413 */
414 class fs_generator
415 {
416 public:
417 fs_generator(const struct brw_compiler *compiler, void *log_data,
418 void *mem_ctx,
419 struct brw_stage_prog_data *prog_data,
420 unsigned promoted_constants,
421 bool runtime_check_aads_emit,
422 gl_shader_stage stage);
423 ~fs_generator();
424
425 void enable_debug(const char *shader_name);
426 int generate_code(const cfg_t *cfg, int dispatch_width);
427 const unsigned *get_assembly();
428
429 private:
430 void fire_fb_write(fs_inst *inst,
431 struct brw_reg payload,
432 struct brw_reg implied_header,
433 GLuint nr);
434 void generate_send(fs_inst *inst,
435 struct brw_reg dst,
436 struct brw_reg desc,
437 struct brw_reg ex_desc,
438 struct brw_reg payload,
439 struct brw_reg payload2);
440 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
441 void generate_fb_read(fs_inst *inst, struct brw_reg dst,
442 struct brw_reg payload);
443 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
444 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
445 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
446 void generate_barrier(fs_inst *inst, struct brw_reg src);
447 bool generate_linterp(fs_inst *inst, struct brw_reg dst,
448 struct brw_reg *src);
449 void generate_tex(fs_inst *inst, struct brw_reg dst,
450 struct brw_reg surface_index,
451 struct brw_reg sampler_index);
452 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
453 struct brw_reg src,
454 struct brw_reg surf_index);
455 void generate_ddx(const fs_inst *inst,
456 struct brw_reg dst, struct brw_reg src);
457 void generate_ddy(const fs_inst *inst,
458 struct brw_reg dst, struct brw_reg src);
459 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
460 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
461 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
462 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
463 struct brw_reg index,
464 struct brw_reg offset);
465 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
466 struct brw_reg dst,
467 struct brw_reg surf_index,
468 struct brw_reg payload);
469 void generate_varying_pull_constant_load_gen4(fs_inst *inst,
470 struct brw_reg dst,
471 struct brw_reg index);
472 void generate_mov_dispatch_to_flags(fs_inst *inst);
473
474 void generate_pixel_interpolator_query(fs_inst *inst,
475 struct brw_reg dst,
476 struct brw_reg src,
477 struct brw_reg msg_data,
478 unsigned msg_type);
479
480 void generate_set_sample_id(fs_inst *inst,
481 struct brw_reg dst,
482 struct brw_reg src0,
483 struct brw_reg src1);
484
485 void generate_discard_jump(fs_inst *inst);
486
487 void generate_pack_half_2x16_split(fs_inst *inst,
488 struct brw_reg dst,
489 struct brw_reg x,
490 struct brw_reg y);
491
492 void generate_shader_time_add(fs_inst *inst,
493 struct brw_reg payload,
494 struct brw_reg offset,
495 struct brw_reg value);
496
497 void generate_mov_indirect(fs_inst *inst,
498 struct brw_reg dst,
499 struct brw_reg reg,
500 struct brw_reg indirect_byte_offset);
501
502 void generate_shuffle(fs_inst *inst,
503 struct brw_reg dst,
504 struct brw_reg src,
505 struct brw_reg idx);
506
507 void generate_quad_swizzle(const fs_inst *inst,
508 struct brw_reg dst, struct brw_reg src,
509 unsigned swiz);
510
511 bool patch_discard_jumps_to_fb_writes();
512
513 const struct brw_compiler *compiler;
514 void *log_data; /* Passed to compiler->*_log functions */
515
516 const struct gen_device_info *devinfo;
517
518 struct brw_codegen *p;
519 struct brw_stage_prog_data * const prog_data;
520
521 unsigned dispatch_width; /**< 8, 16 or 32 */
522
523 exec_list discard_halt_patches;
524 unsigned promoted_constants;
525 bool runtime_check_aads_emit;
526 bool debug_flag;
527 const char *shader_name;
528 gl_shader_stage stage;
529 void *mem_ctx;
530 };
531
532 namespace brw {
533 inline fs_reg
534 fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
535 brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1)
536 {
537 if (!regs[0])
538 return fs_reg();
539
540 if (bld.dispatch_width() > 16) {
541 const fs_reg tmp = bld.vgrf(type, n);
542 const brw::fs_builder hbld = bld.exec_all().group(16, 0);
543 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
544 fs_reg *const components = new fs_reg[n * m];
545
546 for (unsigned c = 0; c < n; c++) {
547 for (unsigned g = 0; g < m; g++) {
548 components[c * m + g] =
549 offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c);
550 }
551 }
552
553 hbld.LOAD_PAYLOAD(tmp, components, n * m, 0);
554
555 delete[] components;
556 return tmp;
557
558 } else {
559 return fs_reg(retype(brw_vec8_grf(regs[0], 0), type));
560 }
561 }
562
563 bool
564 lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
565 }
566
567 void shuffle_from_32bit_read(const brw::fs_builder &bld,
568 const fs_reg &dst,
569 const fs_reg &src,
570 uint32_t first_component,
571 uint32_t components);
572
573 fs_reg shuffle_for_32bit_write(const brw::fs_builder &bld,
574 const fs_reg &src,
575 uint32_t first_component,
576 uint32_t components);
577
578 fs_reg setup_imm_df(const brw::fs_builder &bld,
579 double v);
580
581 fs_reg setup_imm_b(const brw::fs_builder &bld,
582 int8_t v);
583
584 fs_reg setup_imm_ub(const brw::fs_builder &bld,
585 uint8_t v);
586
587 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
588 nir_intrinsic_op op);
589
590 #endif /* BRW_FS_H */