94eb84870f1200c4d4a26200f41425c6f1ee6956
[mesa.git] / src / intel / compiler / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "util/mesa-sha1.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
58 fs_reg *reg, bool compressed)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else {
70 /* From the Haswell PRM:
71 *
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
74 * boundaries."
75 *
76 * The maximum width value that could satisfy this restriction is:
77 */
78 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type));
79
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
84 */
85 const unsigned phys_width = compressed ? inst->exec_size / 2 :
86 inst->exec_size;
87
88 const unsigned max_hw_width = 16;
89
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
95 */
96 if (reg->stride > 4) {
97 assert(reg != &inst->dst);
98 assert(reg->stride * type_sz(reg->type) <= REG_SIZE);
99 brw_reg = brw_vecn_reg(1, brw_file_from_reg(reg), reg->nr, 0);
100 brw_reg = stride(brw_reg, reg->stride, 1, 0);
101 } else {
102 const unsigned width = MIN3(reg_width, phys_width, max_hw_width);
103 brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
104 brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
105 }
106
107 if (devinfo->gen == 7 && !devinfo->is_haswell) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
114 * appropriately."
115 *
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
122 * of floats."
123 *
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
126 *
127 * It applies to BayTrail too.
128 */
129 if (type_sz(reg->type) == 8) {
130 brw_reg.width++;
131 if (brw_reg.vstride > 0)
132 brw_reg.vstride++;
133 assert(brw_reg.hstride == BRW_HORIZONTAL_STRIDE_1);
134 }
135
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
141 */
142 if (reg == &inst->dst && get_exec_type_size(inst) == 8 &&
143 type_sz(inst->dst.type) < 8) {
144 assert(brw_reg.hstride > BRW_HORIZONTAL_STRIDE_1);
145 brw_reg.hstride--;
146 }
147 }
148 }
149
150 brw_reg = retype(brw_reg, reg->type);
151 brw_reg = byte_offset(brw_reg, reg->offset);
152 brw_reg.abs = reg->abs;
153 brw_reg.negate = reg->negate;
154 break;
155 case ARF:
156 case FIXED_GRF:
157 case IMM:
158 assert(reg->offset == 0);
159 brw_reg = reg->as_brw_reg();
160 break;
161 case BAD_FILE:
162 /* Probably unused. */
163 brw_reg = brw_null_reg();
164 break;
165 case ATTR:
166 case UNIFORM:
167 unreachable("not reached");
168 }
169
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
173 */
174 if (devinfo->gen == 7 && !devinfo->is_haswell &&
175 type_sz(reg->type) == 8 &&
176 brw_reg.vstride == BRW_VERTICAL_STRIDE_0 &&
177 brw_reg.width == BRW_WIDTH_1 &&
178 brw_reg.hstride == BRW_HORIZONTAL_STRIDE_0) {
179 brw_reg.width = BRW_WIDTH_2;
180 brw_reg.hstride = BRW_HORIZONTAL_STRIDE_1;
181 }
182
183 return brw_reg;
184 }
185
186 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
187 void *mem_ctx,
188 struct brw_stage_prog_data *prog_data,
189 bool runtime_check_aads_emit,
190 gl_shader_stage stage)
191
192 : compiler(compiler), log_data(log_data),
193 devinfo(compiler->devinfo),
194 prog_data(prog_data),
195 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
196 stage(stage), mem_ctx(mem_ctx)
197 {
198 p = rzalloc(mem_ctx, struct brw_codegen);
199 brw_init_codegen(devinfo, p, mem_ctx);
200
201 /* In the FS code generator, we are very careful to ensure that we always
202 * set the right execution size so we don't need the EU code to "help" us
203 * by trying to infer it. Sometimes, it infers the wrong thing.
204 */
205 p->automatic_exec_sizes = false;
206 }
207
208 fs_generator::~fs_generator()
209 {
210 }
211
212 class ip_record : public exec_node {
213 public:
214 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
215
216 ip_record(int ip)
217 {
218 this->ip = ip;
219 }
220
221 int ip;
222 };
223
224 bool
225 fs_generator::patch_discard_jumps_to_fb_writes()
226 {
227 if (this->discard_halt_patches.is_empty())
228 return false;
229
230 int scale = brw_jump_scale(p->devinfo);
231
232 if (devinfo->gen >= 6) {
233 /* There is a somewhat strange undocumented requirement of using
234 * HALT, according to the simulator. If some channel has HALTed to
235 * a particular UIP, then by the end of the program, every channel
236 * must have HALTed to that UIP. Furthermore, the tracking is a
237 * stack, so you can't do the final halt of a UIP after starting
238 * halting to a new UIP.
239 *
240 * Symptoms of not emitting this instruction on actual hardware
241 * included GPU hangs and sparkly rendering on the piglit discard
242 * tests.
243 */
244 brw_inst *last_halt = brw_HALT(p);
245 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
246 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
247 }
248
249 int ip = p->nr_insn;
250
251 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
252 brw_inst *patch = &p->store[patch_ip->ip];
253
254 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
255 if (devinfo->gen >= 6) {
256 /* HALT takes a half-instruction distance from the pre-incremented IP. */
257 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
258 } else {
259 brw_set_src1(p, patch, brw_imm_d((ip - patch_ip->ip) * scale));
260 }
261 }
262
263 this->discard_halt_patches.make_empty();
264
265 if (devinfo->gen < 6) {
266 /* From the g965 PRM:
267 *
268 * "As DMask is not automatically reloaded into AMask upon completion
269 * of this instruction, software has to manually restore AMask upon
270 * completion."
271 *
272 * DMask lives in the bottom 16 bits of sr0.1.
273 */
274 brw_inst *reset = brw_MOV(p, brw_mask_reg(BRW_AMASK),
275 retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW));
276 brw_inst_set_exec_size(devinfo, reset, BRW_EXECUTE_1);
277 brw_inst_set_mask_control(devinfo, reset, BRW_MASK_DISABLE);
278 brw_inst_set_qtr_control(devinfo, reset, BRW_COMPRESSION_NONE);
279 brw_inst_set_thread_control(devinfo, reset, BRW_THREAD_SWITCH);
280 }
281
282 if (devinfo->gen == 4 && !devinfo->is_g4x) {
283 /* From the g965 PRM:
284 *
285 * "[DevBW, DevCL] Erratum: The subfields in mask stack register are
286 * reset to zero during graphics reset, however, they are not
287 * initialized at thread dispatch. These subfields will retain the
288 * values from the previous thread. Software should make sure the
289 * mask stack is empty (reset to zero) before terminating the thread.
290 * In case that this is not practical, software may have to reset the
291 * mask stack at the beginning of each kernel, which will impact the
292 * performance."
293 *
294 * Luckily we can rely on:
295 *
296 * "[DevBW, DevCL] This register access restriction is not
297 * applicable, hardware does ensure execution pipeline coherency,
298 * when a mask stack register is used as an explicit source and/or
299 * destination."
300 */
301 brw_push_insn_state(p);
302 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
303 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
304
305 brw_set_default_exec_size(p, BRW_EXECUTE_2);
306 brw_MOV(p, vec2(brw_mask_stack_depth_reg(0)), brw_imm_uw(0));
307
308 brw_set_default_exec_size(p, BRW_EXECUTE_16);
309 /* Reset the if stack. */
310 brw_MOV(p, retype(brw_mask_stack_reg(0), BRW_REGISTER_TYPE_UW),
311 brw_imm_uw(0));
312
313 brw_pop_insn_state(p);
314 }
315
316 return true;
317 }
318
319 void
320 fs_generator::generate_send(fs_inst *inst,
321 struct brw_reg dst,
322 struct brw_reg desc,
323 struct brw_reg ex_desc,
324 struct brw_reg payload,
325 struct brw_reg payload2)
326 {
327 const bool dst_is_null = dst.file == BRW_ARCHITECTURE_REGISTER_FILE &&
328 dst.nr == BRW_ARF_NULL;
329 const unsigned rlen = dst_is_null ? 0 : inst->size_written / REG_SIZE;
330
331 uint32_t desc_imm = inst->desc |
332 brw_message_desc(devinfo, inst->mlen, rlen, inst->header_size);
333
334 uint32_t ex_desc_imm = brw_message_ex_desc(devinfo, inst->ex_mlen);
335
336 if (ex_desc.file != BRW_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm) {
337 /* If we have any sort of extended descriptor, then we need SENDS. This
338 * also covers the dual-payload case because ex_mlen goes in ex_desc.
339 */
340 brw_send_indirect_split_message(p, inst->sfid, dst, payload, payload2,
341 desc, desc_imm, ex_desc, ex_desc_imm,
342 inst->eot);
343 if (inst->check_tdr)
344 brw_inst_set_opcode(p->devinfo, brw_last_inst,
345 devinfo->gen >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
346 } else {
347 brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
348 inst->eot);
349 if (inst->check_tdr)
350 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
351 }
352 }
353
354 void
355 fs_generator::fire_fb_write(fs_inst *inst,
356 struct brw_reg payload,
357 struct brw_reg implied_header,
358 GLuint nr)
359 {
360 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
361
362 if (devinfo->gen < 6) {
363 brw_push_insn_state(p);
364 brw_set_default_exec_size(p, BRW_EXECUTE_8);
365 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
366 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
367 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
368 brw_MOV(p, offset(retype(payload, BRW_REGISTER_TYPE_UD), 1),
369 offset(retype(implied_header, BRW_REGISTER_TYPE_UD), 1));
370 brw_pop_insn_state(p);
371 }
372
373 uint32_t msg_control = brw_fb_write_msg_control(inst, prog_data);
374
375 /* We assume render targets start at 0, because headerless FB write
376 * messages set "Render Target Index" to 0. Using a different binding
377 * table index would make it impossible to use headerless messages.
378 */
379 const uint32_t surf_index = inst->target;
380
381 brw_inst *insn = brw_fb_WRITE(p,
382 payload,
383 retype(implied_header, BRW_REGISTER_TYPE_UW),
384 msg_control,
385 surf_index,
386 nr,
387 0,
388 inst->eot,
389 inst->last_rt,
390 inst->header_size != 0);
391
392 if (devinfo->gen >= 6)
393 brw_inst_set_rt_slot_group(devinfo, insn, inst->group / 16);
394 }
395
396 void
397 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
398 {
399 if (devinfo->gen < 8 && !devinfo->is_haswell) {
400 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
401 brw_set_default_flag_reg(p, 0, 0);
402 }
403
404 const struct brw_reg implied_header =
405 devinfo->gen < 6 ? payload : brw_null_reg();
406
407 if (inst->base_mrf >= 0)
408 payload = brw_message_reg(inst->base_mrf);
409
410 if (!runtime_check_aads_emit) {
411 fire_fb_write(inst, payload, implied_header, inst->mlen);
412 } else {
413 /* This can only happen in gen < 6 */
414 assert(devinfo->gen < 6);
415
416 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
417
418 /* Check runtime bit to detect if we have to send AA data or not */
419 brw_push_insn_state(p);
420 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
421 brw_set_default_exec_size(p, BRW_EXECUTE_1);
422 brw_AND(p,
423 v1_null_ud,
424 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
425 brw_imm_ud(1<<26));
426 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
427
428 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
429 brw_pop_insn_state(p);
430 {
431 /* Don't send AA data */
432 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
433 }
434 brw_land_fwd_jump(p, jmp);
435 fire_fb_write(inst, payload, implied_header, inst->mlen);
436 }
437 }
438
439 void
440 fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst,
441 struct brw_reg payload)
442 {
443 assert(inst->size_written % REG_SIZE == 0);
444 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
445 /* We assume that render targets start at binding table index 0. */
446 const unsigned surf_index = inst->target;
447
448 gen9_fb_READ(p, dst, payload, surf_index,
449 inst->header_size, inst->size_written / REG_SIZE,
450 prog_data->persample_dispatch);
451 }
452
453 void
454 fs_generator::generate_mov_indirect(fs_inst *inst,
455 struct brw_reg dst,
456 struct brw_reg reg,
457 struct brw_reg indirect_byte_offset)
458 {
459 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
460 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
461 assert(!reg.abs && !reg.negate);
462 assert(reg.type == dst.type);
463
464 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
465
466 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
467 imm_byte_offset += indirect_byte_offset.ud;
468
469 reg.nr = imm_byte_offset / REG_SIZE;
470 reg.subnr = imm_byte_offset % REG_SIZE;
471 if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
472 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
473 subscript(reg, BRW_REGISTER_TYPE_D, 0));
474 brw_set_default_swsb(p, tgl_swsb_null());
475 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
476 subscript(reg, BRW_REGISTER_TYPE_D, 1));
477 } else {
478 brw_MOV(p, dst, reg);
479 }
480 } else {
481 /* Prior to Broadwell, there are only 8 address registers. */
482 assert(inst->exec_size <= 8 || devinfo->gen >= 8);
483
484 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
485 struct brw_reg addr = vec8(brw_address_reg(0));
486
487 /* Whether we can use destination dependency control without running the
488 * risk of a hang if an instruction gets shot down.
489 */
490 const bool use_dep_ctrl = !inst->predicate &&
491 inst->exec_size == dispatch_width;
492 brw_inst *insn;
493
494 /* The destination stride of an instruction (in bytes) must be greater
495 * than or equal to the size of the rest of the instruction. Since the
496 * address register is of type UW, we can't use a D-type instruction.
497 * In order to get around this, re retype to UW and use a stride.
498 */
499 indirect_byte_offset =
500 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
501
502 /* There are a number of reasons why we don't use the base offset here.
503 * One reason is that the field is only 9 bits which means we can only
504 * use it to access the first 16 GRFs. Also, from the Haswell PRM
505 * section "Register Region Restrictions":
506 *
507 * "The lower bits of the AddressImmediate must not overflow to
508 * change the register address. The lower 5 bits of Address
509 * Immediate when added to lower 5 bits of address register gives
510 * the sub-register offset. The upper bits of Address Immediate
511 * when added to upper bits of address register gives the register
512 * address. Any overflow from sub-register offset is dropped."
513 *
514 * Since the indirect may cause us to cross a register boundary, this
515 * makes the base offset almost useless. We could try and do something
516 * clever where we use a actual base offset if base_offset % 32 == 0 but
517 * that would mean we were generating different code depending on the
518 * base offset. Instead, for the sake of consistency, we'll just do the
519 * add ourselves. This restriction is only listed in the Haswell PRM
520 * but empirical testing indicates that it applies on all older
521 * generations and is lifted on Broadwell.
522 *
523 * In the end, while base_offset is nice to look at in the generated
524 * code, using it saves us 0 instructions and would require quite a bit
525 * of case-by-case work. It's just not worth it.
526 *
527 * Due to a hardware bug some platforms (particularly Gen11+) seem to
528 * require the address components of all channels to be valid whether or
529 * not they're active, which causes issues if we use VxH addressing
530 * under non-uniform control-flow. We can easily work around that by
531 * initializing the whole address register with a pipelined NoMask MOV
532 * instruction.
533 */
534 if (devinfo->gen >= 7) {
535 insn = brw_MOV(p, addr, brw_imm_uw(imm_byte_offset));
536 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
537 brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
538 if (devinfo->gen >= 12)
539 brw_set_default_swsb(p, tgl_swsb_null());
540 else
541 brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
542 }
543
544 insn = brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
545 if (devinfo->gen >= 12)
546 brw_set_default_swsb(p, tgl_swsb_regdist(1));
547 else if (devinfo->gen >= 7)
548 brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
549
550 if (type_sz(reg.type) > 4 &&
551 ((devinfo->gen == 7 && !devinfo->is_haswell) ||
552 devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
553 !devinfo->has_64bit_float)) {
554 /* IVB has an issue (which we found empirically) where it reads two
555 * address register components per channel for indirectly addressed
556 * 64-bit sources.
557 *
558 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
559 *
560 * "When source or destination datatype is 64b or operation is
561 * integer DWord multiply, indirect addressing must not be used."
562 *
563 * To work around both of these, we do two integer MOVs insead of one
564 * 64-bit MOV. Because no double value should ever cross a register
565 * boundary, it's safe to use the immediate offset in the indirect
566 * here to handle adding 4 bytes to the offset and avoid the extra
567 * ADD to the register file.
568 */
569 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
570 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
571 brw_set_default_swsb(p, tgl_swsb_null());
572 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
573 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
574 } else {
575 struct brw_reg ind_src = brw_VxH_indirect(0, 0);
576
577 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, reg.type));
578
579 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
580 !inst->get_next()->is_tail_sentinel() &&
581 ((fs_inst *)inst->get_next())->mlen > 0) {
582 /* From the Sandybridge PRM:
583 *
584 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
585 * instruction that “indexed/indirect” source AND is followed
586 * by a send, the instruction requires a “Switch”. This is to
587 * avoid race condition where send may dispatch before MRF is
588 * updated."
589 */
590 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
591 }
592 }
593 }
594 }
595
596 void
597 fs_generator::generate_shuffle(fs_inst *inst,
598 struct brw_reg dst,
599 struct brw_reg src,
600 struct brw_reg idx)
601 {
602 /* Ivy bridge has some strange behavior that makes this a real pain to
603 * implement for 64-bit values so we just don't bother.
604 */
605 assert(devinfo->gen >= 8 || devinfo->is_haswell || type_sz(src.type) <= 4);
606
607 /* Because we're using the address register, we're limited to 8-wide
608 * execution on gen7. On gen8, we're limited to 16-wide by the address
609 * register file and 8-wide for 64-bit types. We could try and make this
610 * instruction splittable higher up in the compiler but that gets weird
611 * because it reads all of the channels regardless of execution size. It's
612 * easier just to split it here.
613 */
614 const unsigned lower_width =
615 (devinfo->gen <= 7 || type_sz(src.type) > 4) ?
616 8 : MIN2(16, inst->exec_size);
617
618 brw_set_default_exec_size(p, cvt(lower_width) - 1);
619 for (unsigned group = 0; group < inst->exec_size; group += lower_width) {
620 brw_set_default_group(p, group);
621
622 if ((src.vstride == 0 && src.hstride == 0) ||
623 idx.file == BRW_IMMEDIATE_VALUE) {
624 /* Trivial, the source is already uniform or the index is a constant.
625 * We will typically not get here if the optimizer is doing its job,
626 * but asserting would be mean.
627 */
628 const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
629 brw_MOV(p, suboffset(dst, group), stride(suboffset(src, i), 0, 1, 0));
630 } else {
631 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
632 struct brw_reg addr = vec8(brw_address_reg(0));
633
634 struct brw_reg group_idx = suboffset(idx, group);
635
636 if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) {
637 /* Things get grumpy if the register is too wide. */
638 group_idx.width--;
639 group_idx.vstride--;
640 }
641
642 assert(type_sz(group_idx.type) <= 4);
643 if (type_sz(group_idx.type) == 4) {
644 /* The destination stride of an instruction (in bytes) must be
645 * greater than or equal to the size of the rest of the
646 * instruction. Since the address register is of type UW, we
647 * can't use a D-type instruction. In order to get around this,
648 * re retype to UW and use a stride.
649 */
650 group_idx = retype(spread(group_idx, 2), BRW_REGISTER_TYPE_W);
651 }
652
653 /* Take into account the component size and horizontal stride. */
654 assert(src.vstride == src.hstride + src.width);
655 brw_SHL(p, addr, group_idx,
656 brw_imm_uw(util_logbase2(type_sz(src.type)) +
657 src.hstride - 1));
658
659 /* Add on the register start offset */
660 brw_set_default_swsb(p, tgl_swsb_regdist(1));
661 brw_ADD(p, addr, addr, brw_imm_uw(src.nr * REG_SIZE + src.subnr));
662
663 if (type_sz(src.type) > 4 &&
664 ((devinfo->gen == 7 && !devinfo->is_haswell) ||
665 devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
666 /* IVB has an issue (which we found empirically) where it reads
667 * two address register components per channel for indirectly
668 * addressed 64-bit sources.
669 *
670 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
671 *
672 * "When source or destination datatype is 64b or operation is
673 * integer DWord multiply, indirect addressing must not be
674 * used."
675 *
676 * To work around both of these, we do two integer MOVs insead of
677 * one 64-bit MOV. Because no double value should ever cross a
678 * register boundary, it's safe to use the immediate offset in the
679 * indirect here to handle adding 4 bytes to the offset and avoid
680 * the extra ADD to the register file.
681 */
682 struct brw_reg gdst = suboffset(dst, group);
683 struct brw_reg dst_d = retype(spread(gdst, 2),
684 BRW_REGISTER_TYPE_D);
685 assert(dst.hstride == 1);
686 brw_MOV(p, dst_d,
687 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
688 brw_set_default_swsb(p, tgl_swsb_null());
689 brw_MOV(p, byte_offset(dst_d, 4),
690 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
691 } else {
692 brw_MOV(p, suboffset(dst, group * dst.hstride),
693 retype(brw_VxH_indirect(0, 0), src.type));
694 }
695 }
696
697 brw_set_default_swsb(p, tgl_swsb_null());
698 }
699 }
700
701 void
702 fs_generator::generate_quad_swizzle(const fs_inst *inst,
703 struct brw_reg dst, struct brw_reg src,
704 unsigned swiz)
705 {
706 /* Requires a quad. */
707 assert(inst->exec_size >= 4);
708
709 if (src.file == BRW_IMMEDIATE_VALUE ||
710 has_scalar_region(src)) {
711 /* The value is uniform across all channels */
712 brw_MOV(p, dst, src);
713
714 } else if (devinfo->gen < 11 && type_sz(src.type) == 4) {
715 /* This only works on 8-wide 32-bit values */
716 assert(inst->exec_size == 8);
717 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
718 assert(src.vstride == src.width + 1);
719 brw_set_default_access_mode(p, BRW_ALIGN_16);
720 struct brw_reg swiz_src = stride(src, 4, 4, 1);
721 swiz_src.swizzle = swiz;
722 brw_MOV(p, dst, swiz_src);
723
724 } else {
725 assert(src.hstride == BRW_HORIZONTAL_STRIDE_1);
726 assert(src.vstride == src.width + 1);
727 const struct brw_reg src_0 = suboffset(src, BRW_GET_SWZ(swiz, 0));
728
729 switch (swiz) {
730 case BRW_SWIZZLE_XXXX:
731 case BRW_SWIZZLE_YYYY:
732 case BRW_SWIZZLE_ZZZZ:
733 case BRW_SWIZZLE_WWWW:
734 brw_MOV(p, dst, stride(src_0, 4, 4, 0));
735 break;
736
737 case BRW_SWIZZLE_XXZZ:
738 case BRW_SWIZZLE_YYWW:
739 brw_MOV(p, dst, stride(src_0, 2, 2, 0));
740 break;
741
742 case BRW_SWIZZLE_XYXY:
743 case BRW_SWIZZLE_ZWZW:
744 assert(inst->exec_size == 4);
745 brw_MOV(p, dst, stride(src_0, 0, 2, 1));
746 break;
747
748 default:
749 assert(inst->force_writemask_all);
750 brw_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1);
751
752 for (unsigned c = 0; c < 4; c++) {
753 brw_inst *insn = brw_MOV(
754 p, stride(suboffset(dst, c),
755 4 * inst->dst.stride, 1, 4 * inst->dst.stride),
756 stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0));
757
758 if (devinfo->gen < 12) {
759 brw_inst_set_no_dd_clear(devinfo, insn, c < 3);
760 brw_inst_set_no_dd_check(devinfo, insn, c > 0);
761 }
762
763 brw_set_default_swsb(p, tgl_swsb_null());
764 }
765
766 break;
767 }
768 }
769 }
770
771 void
772 fs_generator::generate_urb_read(fs_inst *inst,
773 struct brw_reg dst,
774 struct brw_reg header)
775 {
776 assert(inst->size_written % REG_SIZE == 0);
777 assert(header.file == BRW_GENERAL_REGISTER_FILE);
778 assert(header.type == BRW_REGISTER_TYPE_UD);
779
780 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
781 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
782 brw_set_src0(p, send, header);
783 if (devinfo->gen < 12)
784 brw_set_src1(p, send, brw_imm_ud(0u));
785
786 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
787 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
788
789 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
790 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
791
792 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
793 brw_inst_set_rlen(p->devinfo, send, inst->size_written / REG_SIZE);
794 brw_inst_set_header_present(p->devinfo, send, true);
795 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
796 }
797
798 void
799 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
800 {
801 brw_inst *insn;
802
803 /* WaClearTDRRegBeforeEOTForNonPS.
804 *
805 * WA: Clear tdr register before send EOT in all non-PS shader kernels
806 *
807 * mov(8) tdr0:ud 0x0:ud {NoMask}"
808 */
809 if (inst->eot && p->devinfo->gen == 10) {
810 brw_push_insn_state(p);
811 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
812 brw_MOV(p, brw_tdr_reg(), brw_imm_uw(0));
813 brw_pop_insn_state(p);
814 }
815
816 insn = brw_next_insn(p, BRW_OPCODE_SEND);
817
818 brw_set_dest(p, insn, brw_null_reg());
819 brw_set_src0(p, insn, payload);
820 if (devinfo->gen < 12)
821 brw_set_src1(p, insn, brw_imm_ud(0u));
822
823 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
824 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
825
826 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
827 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
828 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
829
830 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
831 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
832 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
833
834 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
835 brw_inst_set_rlen(p->devinfo, insn, 0);
836 brw_inst_set_eot(p->devinfo, insn, inst->eot);
837 brw_inst_set_header_present(p->devinfo, insn, true);
838 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
839 }
840
841 void
842 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
843 {
844 struct brw_inst *insn;
845
846 insn = brw_next_insn(p, BRW_OPCODE_SEND);
847
848 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
849 brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW));
850 if (devinfo->gen < 12)
851 brw_set_src1(p, insn, brw_imm_ud(0u));
852
853 /* Terminate a compute shader by sending a message to the thread spawner.
854 */
855 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
856 brw_inst_set_mlen(devinfo, insn, 1);
857 brw_inst_set_rlen(devinfo, insn, 0);
858 brw_inst_set_eot(devinfo, insn, inst->eot);
859 brw_inst_set_header_present(devinfo, insn, false);
860
861 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
862
863 if (devinfo->gen < 11) {
864 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
865
866 /* Note that even though the thread has a URB resource associated with it,
867 * we set the "do not dereference URB" bit, because the URB resource is
868 * managed by the fixed-function unit, so it will free it automatically.
869 */
870 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
871 }
872
873 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
874 }
875
876 void
877 fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
878 {
879 brw_barrier(p, src);
880 if (devinfo->gen >= 12) {
881 brw_set_default_swsb(p, tgl_swsb_null());
882 brw_SYNC(p, TGL_SYNC_BAR);
883 } else {
884 brw_WAIT(p);
885 }
886 }
887
888 bool
889 fs_generator::generate_linterp(fs_inst *inst,
890 struct brw_reg dst, struct brw_reg *src)
891 {
892 /* PLN reads:
893 * / in SIMD16 \
894 * -----------------------------------
895 * | src1+0 | src1+1 | src1+2 | src1+3 |
896 * |-----------------------------------|
897 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
898 * -----------------------------------
899 *
900 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
901 *
902 * -----------------------------------
903 * | src1+0 | src1+1 | src1+2 | src1+3 |
904 * |-----------------------------------|
905 * |(x0, x1)|(y0, y1)| | | in SIMD8
906 * |-----------------------------------|
907 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
908 * -----------------------------------
909 *
910 * See also: emit_interpolation_setup_gen4().
911 */
912 struct brw_reg delta_x = src[0];
913 struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
914 struct brw_reg interp = src[1];
915 brw_inst *i[2];
916
917 /* nir_lower_interpolation() will do the lowering to MAD instructions for
918 * us on gen11+
919 */
920 assert(devinfo->gen < 11);
921
922 if (devinfo->has_pln) {
923 if (devinfo->gen <= 6 && (delta_x.nr & 1) != 0) {
924 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
925 *
926 * "[DevSNB]:<src1> must be even register aligned.
927 *
928 * This restriction is lifted on Ivy Bridge.
929 *
930 * This means that we need to split PLN into LINE+MAC on-the-fly.
931 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
932 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
933 * coordinate registers are laid out differently so we leave it as a
934 * SIMD16 instruction.
935 */
936 assert(inst->exec_size == 8 || inst->exec_size == 16);
937 assert(inst->group % 16 == 0);
938
939 brw_push_insn_state(p);
940 brw_set_default_exec_size(p, BRW_EXECUTE_8);
941
942 /* Thanks to two accumulators, we can emit all the LINEs and then all
943 * the MACs. This improves parallelism a bit.
944 */
945 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
946 brw_inst *line = brw_LINE(p, brw_null_reg(), interp,
947 offset(delta_x, g * 2));
948 brw_inst_set_group(devinfo, line, inst->group + g * 8);
949
950 /* LINE writes the accumulator automatically on gen4-5. On Sandy
951 * Bridge and later, we have to explicitly enable it.
952 */
953 if (devinfo->gen >= 6)
954 brw_inst_set_acc_wr_control(p->devinfo, line, true);
955
956 /* brw_set_default_saturate() is called before emitting
957 * instructions, so the saturate bit is set in each instruction,
958 * so we need to unset it on the LINE instructions.
959 */
960 brw_inst_set_saturate(p->devinfo, line, false);
961 }
962
963 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
964 brw_inst *mac = brw_MAC(p, offset(dst, g), suboffset(interp, 1),
965 offset(delta_x, g * 2 + 1));
966 brw_inst_set_group(devinfo, mac, inst->group + g * 8);
967 brw_inst_set_cond_modifier(p->devinfo, mac, inst->conditional_mod);
968 }
969
970 brw_pop_insn_state(p);
971
972 return true;
973 } else {
974 brw_PLN(p, dst, interp, delta_x);
975
976 return false;
977 }
978 } else {
979 i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x);
980 i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y);
981
982 brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
983
984 /* brw_set_default_saturate() is called before emitting instructions, so
985 * the saturate bit is set in each instruction, so we need to unset it on
986 * the first instruction.
987 */
988 brw_inst_set_saturate(p->devinfo, i[0], false);
989
990 return true;
991 }
992 }
993
994 void
995 fs_generator::generate_get_buffer_size(fs_inst *inst,
996 struct brw_reg dst,
997 struct brw_reg src,
998 struct brw_reg surf_index)
999 {
1000 assert(devinfo->gen >= 7);
1001 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
1002
1003 uint32_t simd_mode;
1004 int rlen = 4;
1005
1006 switch (inst->exec_size) {
1007 case 8:
1008 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1009 break;
1010 case 16:
1011 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1012 break;
1013 default:
1014 unreachable("Invalid width for texture instruction");
1015 }
1016
1017 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
1018 rlen = 8;
1019 dst = vec16(dst);
1020 }
1021
1022 brw_SAMPLE(p,
1023 retype(dst, BRW_REGISTER_TYPE_UW),
1024 inst->base_mrf,
1025 src,
1026 surf_index.ud,
1027 0,
1028 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1029 rlen, /* response length */
1030 inst->mlen,
1031 inst->header_size > 0,
1032 simd_mode,
1033 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1034 }
1035
1036 void
1037 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
1038 struct brw_reg surface_index,
1039 struct brw_reg sampler_index)
1040 {
1041 assert(devinfo->gen < 7);
1042 assert(inst->size_written % REG_SIZE == 0);
1043 int msg_type = -1;
1044 uint32_t simd_mode;
1045 uint32_t return_format;
1046
1047 /* Sampler EOT message of less than the dispatch width would kill the
1048 * thread prematurely.
1049 */
1050 assert(!inst->eot || inst->exec_size == dispatch_width);
1051
1052 switch (dst.type) {
1053 case BRW_REGISTER_TYPE_D:
1054 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
1055 break;
1056 case BRW_REGISTER_TYPE_UD:
1057 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
1058 break;
1059 default:
1060 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1061 break;
1062 }
1063
1064 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
1065 * is set as part of the message descriptor. On gen4, the PRM seems to
1066 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
1067 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
1068 * gone from the message descriptor entirely and you just get UINT32 all
1069 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
1070 * just stomp it to UINT32 all the time.
1071 */
1072 if (inst->opcode == SHADER_OPCODE_TXS)
1073 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
1074
1075 switch (inst->exec_size) {
1076 case 8:
1077 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1078 break;
1079 case 16:
1080 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1081 break;
1082 default:
1083 unreachable("Invalid width for texture instruction");
1084 }
1085
1086 if (devinfo->gen >= 5) {
1087 switch (inst->opcode) {
1088 case SHADER_OPCODE_TEX:
1089 if (inst->shadow_compare) {
1090 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
1091 } else {
1092 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
1093 }
1094 break;
1095 case FS_OPCODE_TXB:
1096 if (inst->shadow_compare) {
1097 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
1098 } else {
1099 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
1100 }
1101 break;
1102 case SHADER_OPCODE_TXL:
1103 if (inst->shadow_compare) {
1104 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
1105 } else {
1106 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
1107 }
1108 break;
1109 case SHADER_OPCODE_TXS:
1110 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
1111 break;
1112 case SHADER_OPCODE_TXD:
1113 assert(!inst->shadow_compare);
1114 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
1115 break;
1116 case SHADER_OPCODE_TXF:
1117 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1118 break;
1119 case SHADER_OPCODE_TXF_CMS:
1120 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1121 break;
1122 case SHADER_OPCODE_LOD:
1123 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
1124 break;
1125 case SHADER_OPCODE_TG4:
1126 assert(devinfo->gen == 6);
1127 assert(!inst->shadow_compare);
1128 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
1129 break;
1130 case SHADER_OPCODE_SAMPLEINFO:
1131 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
1132 break;
1133 default:
1134 unreachable("not reached");
1135 }
1136 } else {
1137 switch (inst->opcode) {
1138 case SHADER_OPCODE_TEX:
1139 /* Note that G45 and older determines shadow compare and dispatch width
1140 * from message length for most messages.
1141 */
1142 if (inst->exec_size == 8) {
1143 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
1144 if (inst->shadow_compare) {
1145 assert(inst->mlen == 6);
1146 } else {
1147 assert(inst->mlen <= 4);
1148 }
1149 } else {
1150 if (inst->shadow_compare) {
1151 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1152 assert(inst->mlen == 9);
1153 } else {
1154 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1155 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
1156 }
1157 }
1158 break;
1159 case FS_OPCODE_TXB:
1160 if (inst->shadow_compare) {
1161 assert(inst->exec_size == 8);
1162 assert(inst->mlen == 6);
1163 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
1164 } else {
1165 assert(inst->mlen == 9);
1166 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1167 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1168 }
1169 break;
1170 case SHADER_OPCODE_TXL:
1171 if (inst->shadow_compare) {
1172 assert(inst->exec_size == 8);
1173 assert(inst->mlen == 6);
1174 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
1175 } else {
1176 assert(inst->mlen == 9);
1177 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
1178 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1179 }
1180 break;
1181 case SHADER_OPCODE_TXD:
1182 /* There is no sample_d_c message; comparisons are done manually */
1183 assert(inst->exec_size == 8);
1184 assert(inst->mlen == 7 || inst->mlen == 10);
1185 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
1186 break;
1187 case SHADER_OPCODE_TXF:
1188 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
1189 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1190 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1191 break;
1192 case SHADER_OPCODE_TXS:
1193 assert(inst->mlen == 3);
1194 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
1195 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1196 break;
1197 default:
1198 unreachable("not reached");
1199 }
1200 }
1201 assert(msg_type != -1);
1202
1203 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
1204 dst = vec16(dst);
1205 }
1206
1207 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
1208
1209 /* Load the message header if present. If there's a texture offset,
1210 * we need to set it up explicitly and load the offset bitfield.
1211 * Otherwise, we can use an implied move from g0 to the first message reg.
1212 */
1213 struct brw_reg src = brw_null_reg();
1214 if (inst->header_size != 0) {
1215 if (devinfo->gen < 6 && !inst->offset) {
1216 /* Set up an implied move from g0 to the MRF. */
1217 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
1218 } else {
1219 const tgl_swsb swsb = brw_get_default_swsb(p);
1220 assert(inst->base_mrf != -1);
1221 struct brw_reg header_reg = brw_message_reg(inst->base_mrf);
1222
1223 brw_push_insn_state(p);
1224 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1225 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1226 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1227 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1228 /* Explicitly set up the message header by copying g0 to the MRF. */
1229 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
1230 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1231
1232 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1233 if (inst->offset) {
1234 /* Set the offset bits in DWord 2. */
1235 brw_MOV(p, get_element_ud(header_reg, 2),
1236 brw_imm_ud(inst->offset));
1237 }
1238
1239 brw_pop_insn_state(p);
1240 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1241 }
1242 }
1243
1244 uint32_t base_binding_table_index;
1245 switch (inst->opcode) {
1246 case SHADER_OPCODE_TG4:
1247 base_binding_table_index = prog_data->binding_table.gather_texture_start;
1248 break;
1249 default:
1250 base_binding_table_index = prog_data->binding_table.texture_start;
1251 break;
1252 }
1253
1254 assert(surface_index.file == BRW_IMMEDIATE_VALUE);
1255 assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
1256
1257 brw_SAMPLE(p,
1258 retype(dst, BRW_REGISTER_TYPE_UW),
1259 inst->base_mrf,
1260 src,
1261 surface_index.ud + base_binding_table_index,
1262 sampler_index.ud % 16,
1263 msg_type,
1264 inst->size_written / REG_SIZE,
1265 inst->mlen,
1266 inst->header_size != 0,
1267 simd_mode,
1268 return_format);
1269 }
1270
1271
1272 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1273 * looking like:
1274 *
1275 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1276 *
1277 * Ideally, we want to produce:
1278 *
1279 * DDX DDY
1280 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1281 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1282 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1283 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1284 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1285 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1286 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1287 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1288 *
1289 * and add another set of two more subspans if in 16-pixel dispatch mode.
1290 *
1291 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1292 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1293 * pair. But the ideal approximation may impose a huge performance cost on
1294 * sample_d. On at least Haswell, sample_d instruction does some
1295 * optimizations if the same LOD is used for all pixels in the subspan.
1296 *
1297 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1298 * appropriate swizzling.
1299 */
1300 void
1301 fs_generator::generate_ddx(const fs_inst *inst,
1302 struct brw_reg dst, struct brw_reg src)
1303 {
1304 unsigned vstride, width;
1305
1306 if (devinfo->gen >= 8) {
1307 if (inst->opcode == FS_OPCODE_DDX_FINE) {
1308 /* produce accurate derivatives */
1309 vstride = BRW_VERTICAL_STRIDE_2;
1310 width = BRW_WIDTH_2;
1311 } else {
1312 /* replicate the derivative at the top-left pixel to other pixels */
1313 vstride = BRW_VERTICAL_STRIDE_4;
1314 width = BRW_WIDTH_4;
1315 }
1316
1317 struct brw_reg src0 = byte_offset(src, type_sz(src.type));;
1318 struct brw_reg src1 = src;
1319
1320 src0.vstride = vstride;
1321 src0.width = width;
1322 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
1323 src1.vstride = vstride;
1324 src1.width = width;
1325 src1.hstride = BRW_HORIZONTAL_STRIDE_0;
1326
1327 brw_ADD(p, dst, src0, negate(src1));
1328 } else {
1329 /* On Haswell and earlier, the region used above appears to not work
1330 * correctly for compressed instructions. At least on Haswell and
1331 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1332 * would have to split to SIMD8 no matter which method we choose, we
1333 * may as well use ALIGN16 on all platforms gen7 and earlier.
1334 */
1335 struct brw_reg src0 = stride(src, 4, 4, 1);
1336 struct brw_reg src1 = stride(src, 4, 4, 1);
1337 if (inst->opcode == FS_OPCODE_DDX_FINE) {
1338 src0.swizzle = BRW_SWIZZLE_XXZZ;
1339 src1.swizzle = BRW_SWIZZLE_YYWW;
1340 } else {
1341 src0.swizzle = BRW_SWIZZLE_XXXX;
1342 src1.swizzle = BRW_SWIZZLE_YYYY;
1343 }
1344
1345 brw_push_insn_state(p);
1346 brw_set_default_access_mode(p, BRW_ALIGN_16);
1347 brw_ADD(p, dst, negate(src0), src1);
1348 brw_pop_insn_state(p);
1349 }
1350 }
1351
1352 /* The negate_value boolean is used to negate the derivative computation for
1353 * FBOs, since they place the origin at the upper left instead of the lower
1354 * left.
1355 */
1356 void
1357 fs_generator::generate_ddy(const fs_inst *inst,
1358 struct brw_reg dst, struct brw_reg src)
1359 {
1360 const uint32_t type_size = type_sz(src.type);
1361
1362 if (inst->opcode == FS_OPCODE_DDY_FINE) {
1363 /* produce accurate derivatives.
1364 *
1365 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1366 * "Register Region Restrictions", Section "1. Special Restrictions":
1367 *
1368 * "In Align16 mode, the channel selects and channel enables apply to
1369 * a pair of half-floats, because these parameters are defined for
1370 * DWord elements ONLY. This is applicable when both source and
1371 * destination are half-floats."
1372 *
1373 * So for half-float operations we use the Gen11+ Align1 path. CHV
1374 * inherits its FP16 hardware from SKL, so it is not affected.
1375 */
1376 if (devinfo->gen >= 11 ||
1377 (devinfo->is_broadwell && src.type == BRW_REGISTER_TYPE_HF)) {
1378 src = stride(src, 0, 2, 1);
1379
1380 brw_push_insn_state(p);
1381 brw_set_default_exec_size(p, BRW_EXECUTE_4);
1382 for (uint32_t g = 0; g < inst->exec_size; g += 4) {
1383 brw_set_default_group(p, inst->group + g);
1384 brw_ADD(p, byte_offset(dst, g * type_size),
1385 negate(byte_offset(src, g * type_size)),
1386 byte_offset(src, (g + 2) * type_size));
1387 brw_set_default_swsb(p, tgl_swsb_null());
1388 }
1389 brw_pop_insn_state(p);
1390 } else {
1391 struct brw_reg src0 = stride(src, 4, 4, 1);
1392 struct brw_reg src1 = stride(src, 4, 4, 1);
1393 src0.swizzle = BRW_SWIZZLE_XYXY;
1394 src1.swizzle = BRW_SWIZZLE_ZWZW;
1395
1396 brw_push_insn_state(p);
1397 brw_set_default_access_mode(p, BRW_ALIGN_16);
1398 brw_ADD(p, dst, negate(src0), src1);
1399 brw_pop_insn_state(p);
1400 }
1401 } else {
1402 /* replicate the derivative at the top-left pixel to other pixels */
1403 if (devinfo->gen >= 8) {
1404 struct brw_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
1405 struct brw_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
1406
1407 brw_ADD(p, dst, negate(src0), src1);
1408 } else {
1409 /* On Haswell and earlier, the region used above appears to not work
1410 * correctly for compressed instructions. At least on Haswell and
1411 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1412 * would have to split to SIMD8 no matter which method we choose, we
1413 * may as well use ALIGN16 on all platforms gen7 and earlier.
1414 */
1415 struct brw_reg src0 = stride(src, 4, 4, 1);
1416 struct brw_reg src1 = stride(src, 4, 4, 1);
1417 src0.swizzle = BRW_SWIZZLE_XXXX;
1418 src1.swizzle = BRW_SWIZZLE_ZZZZ;
1419
1420 brw_push_insn_state(p);
1421 brw_set_default_access_mode(p, BRW_ALIGN_16);
1422 brw_ADD(p, dst, negate(src0), src1);
1423 brw_pop_insn_state(p);
1424 }
1425 }
1426 }
1427
1428 void
1429 fs_generator::generate_discard_jump(fs_inst *)
1430 {
1431 /* This HALT will be patched up at FB write time to point UIP at the end of
1432 * the program, and at brw_uip_jip() JIP will be set to the end of the
1433 * current block (or the program).
1434 */
1435 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1436 brw_HALT(p);
1437 }
1438
1439 void
1440 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1441 {
1442 /* The 32-wide messages only respect the first 16-wide half of the channel
1443 * enable signals which are replicated identically for the second group of
1444 * 16 channels, so we cannot use them unless the write is marked
1445 * force_writemask_all.
1446 */
1447 const unsigned lower_size = inst->force_writemask_all ? inst->exec_size :
1448 MIN2(16, inst->exec_size);
1449 const unsigned block_size = 4 * lower_size / REG_SIZE;
1450 const tgl_swsb swsb = brw_get_default_swsb(p);
1451 assert(inst->mlen != 0);
1452
1453 brw_push_insn_state(p);
1454 brw_set_default_exec_size(p, cvt(lower_size) - 1);
1455 brw_set_default_compression(p, lower_size > 8);
1456
1457 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1458 brw_set_default_group(p, inst->group + lower_size * i);
1459
1460 if (i > 0) {
1461 assert(swsb.mode & TGL_SBID_SET);
1462 brw_set_default_swsb(p, tgl_swsb_sbid(TGL_SBID_SRC, swsb.sbid));
1463 } else {
1464 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1465 }
1466
1467 brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
1468 retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD));
1469
1470 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1471 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1472 block_size,
1473 inst->offset + block_size * REG_SIZE * i);
1474 }
1475
1476 brw_pop_insn_state(p);
1477 }
1478
1479 void
1480 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1481 {
1482 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1483 assert(inst->mlen != 0);
1484
1485 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1486 inst->exec_size / 8, inst->offset);
1487 }
1488
1489 void
1490 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1491 {
1492 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1493
1494 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1495 }
1496
1497 void
1498 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1499 struct brw_reg dst,
1500 struct brw_reg index,
1501 struct brw_reg offset)
1502 {
1503 assert(type_sz(dst.type) == 4);
1504 assert(inst->mlen != 0);
1505
1506 assert(index.file == BRW_IMMEDIATE_VALUE &&
1507 index.type == BRW_REGISTER_TYPE_UD);
1508 uint32_t surf_index = index.ud;
1509
1510 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1511 offset.type == BRW_REGISTER_TYPE_UD);
1512 uint32_t read_offset = offset.ud;
1513
1514 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1515 read_offset, surf_index);
1516 }
1517
1518 void
1519 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1520 struct brw_reg dst,
1521 struct brw_reg index,
1522 struct brw_reg payload)
1523 {
1524 assert(index.type == BRW_REGISTER_TYPE_UD);
1525 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1526 assert(type_sz(dst.type) == 4);
1527
1528 if (index.file == BRW_IMMEDIATE_VALUE) {
1529 const uint32_t surf_index = index.ud;
1530
1531 brw_push_insn_state(p);
1532 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1533 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1534 brw_pop_insn_state(p);
1535
1536 brw_inst_set_sfid(devinfo, send, GEN6_SFID_DATAPORT_CONSTANT_CACHE);
1537 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
1538 brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
1539 brw_set_desc(p, send,
1540 brw_message_desc(devinfo, 1, DIV_ROUND_UP(inst->size_written,
1541 REG_SIZE), true) |
1542 brw_dp_read_desc(devinfo, surf_index,
1543 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
1544 GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
1545 BRW_DATAPORT_READ_TARGET_DATA_CACHE));
1546
1547 } else {
1548 const tgl_swsb swsb = brw_get_default_swsb(p);
1549 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1550
1551 brw_push_insn_state(p);
1552 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1553
1554 /* a0.0 = surf_index & 0xff */
1555 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1556 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1557 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1558 brw_set_dest(p, insn_and, addr);
1559 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1560 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1561
1562 /* dst = send(payload, a0.0 | <descriptor>) */
1563 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1564 brw_send_indirect_message(
1565 p, GEN6_SFID_DATAPORT_CONSTANT_CACHE,
1566 retype(dst, BRW_REGISTER_TYPE_UD),
1567 retype(payload, BRW_REGISTER_TYPE_UD), addr,
1568 brw_message_desc(devinfo, 1,
1569 DIV_ROUND_UP(inst->size_written, REG_SIZE), true) |
1570 brw_dp_read_desc(devinfo, 0 /* surface */,
1571 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
1572 GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
1573 BRW_DATAPORT_READ_TARGET_DATA_CACHE),
1574 false /* EOT */);
1575
1576 brw_pop_insn_state(p);
1577 }
1578 }
1579
1580 void
1581 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
1582 struct brw_reg dst,
1583 struct brw_reg index)
1584 {
1585 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1586 assert(inst->header_size != 0);
1587 assert(inst->mlen);
1588
1589 assert(index.file == BRW_IMMEDIATE_VALUE &&
1590 index.type == BRW_REGISTER_TYPE_UD);
1591 uint32_t surf_index = index.ud;
1592
1593 uint32_t simd_mode, rlen, msg_type;
1594 if (inst->exec_size == 16) {
1595 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1596 rlen = 8;
1597 } else {
1598 assert(inst->exec_size == 8);
1599 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1600 rlen = 4;
1601 }
1602
1603 if (devinfo->gen >= 5)
1604 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1605 else {
1606 /* We always use the SIMD16 message so that we only have to load U, and
1607 * not V or R.
1608 */
1609 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1610 assert(inst->mlen == 3);
1611 assert(inst->size_written == 8 * REG_SIZE);
1612 rlen = 8;
1613 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1614 }
1615
1616 struct brw_reg header = brw_vec8_grf(0, 0);
1617 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1618
1619 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1620 brw_inst_set_compression(devinfo, send, false);
1621 brw_inst_set_sfid(devinfo, send, BRW_SFID_SAMPLER);
1622 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1623 brw_set_src0(p, send, header);
1624 if (devinfo->gen < 6)
1625 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1626
1627 /* Our surface is set up as floats, regardless of what actual data is
1628 * stored in it.
1629 */
1630 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1631 brw_set_desc(p, send,
1632 brw_message_desc(devinfo, inst->mlen, rlen, inst->header_size) |
1633 brw_sampler_desc(devinfo, surf_index,
1634 0, /* sampler (unused) */
1635 msg_type, simd_mode, return_format));
1636 }
1637
1638 void
1639 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1640 struct brw_reg dst,
1641 struct brw_reg src,
1642 struct brw_reg msg_data,
1643 unsigned msg_type)
1644 {
1645 const bool has_payload = inst->src[0].file != BAD_FILE;
1646 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1647 assert(inst->size_written % REG_SIZE == 0);
1648
1649 brw_pixel_interpolator_query(p,
1650 retype(dst, BRW_REGISTER_TYPE_UW),
1651 /* If we don't have a payload, what we send doesn't matter */
1652 has_payload ? src : brw_vec8_grf(0, 0),
1653 inst->pi_noperspective,
1654 msg_type,
1655 msg_data,
1656 has_payload ? 2 * inst->exec_size / 8 : 1,
1657 inst->size_written / REG_SIZE);
1658 }
1659
1660 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1661 * the ADD instruction.
1662 */
1663 void
1664 fs_generator::generate_set_sample_id(fs_inst *inst,
1665 struct brw_reg dst,
1666 struct brw_reg src0,
1667 struct brw_reg src1)
1668 {
1669 assert(dst.type == BRW_REGISTER_TYPE_D ||
1670 dst.type == BRW_REGISTER_TYPE_UD);
1671 assert(src0.type == BRW_REGISTER_TYPE_D ||
1672 src0.type == BRW_REGISTER_TYPE_UD);
1673
1674 const struct brw_reg reg = stride(src1, 1, 4, 0);
1675 const unsigned lower_size = MIN2(inst->exec_size,
1676 devinfo->gen >= 8 ? 16 : 8);
1677
1678 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1679 brw_inst *insn = brw_ADD(p, offset(dst, i * lower_size / 8),
1680 offset(src0, (src0.vstride == 0 ? 0 : (1 << (src0.vstride - 1)) *
1681 (i * lower_size / (1 << src0.width))) *
1682 type_sz(src0.type) / REG_SIZE),
1683 suboffset(reg, i * lower_size / 4));
1684 brw_inst_set_exec_size(devinfo, insn, cvt(lower_size) - 1);
1685 brw_inst_set_group(devinfo, insn, inst->group + lower_size * i);
1686 brw_inst_set_compression(devinfo, insn, lower_size > 8);
1687 brw_set_default_swsb(p, tgl_swsb_null());
1688 }
1689 }
1690
1691 void
1692 fs_generator::generate_pack_half_2x16_split(fs_inst *,
1693 struct brw_reg dst,
1694 struct brw_reg x,
1695 struct brw_reg y)
1696 {
1697 assert(devinfo->gen >= 7);
1698 assert(dst.type == BRW_REGISTER_TYPE_UD);
1699 assert(x.type == BRW_REGISTER_TYPE_F);
1700 assert(y.type == BRW_REGISTER_TYPE_F);
1701
1702 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1703 *
1704 * Because this instruction does not have a 16-bit floating-point type,
1705 * the destination data type must be Word (W).
1706 *
1707 * The destination must be DWord-aligned and specify a horizontal stride
1708 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1709 * each destination channel and the upper word is not modified.
1710 */
1711 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1712
1713 /* Give each 32-bit channel of dst the form below, where "." means
1714 * unchanged.
1715 * 0x....hhhh
1716 */
1717 brw_F32TO16(p, dst_w, y);
1718
1719 /* Now the form:
1720 * 0xhhhh0000
1721 */
1722 brw_set_default_swsb(p, tgl_swsb_regdist(1));
1723 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1724
1725 /* And, finally the form of packHalf2x16's output:
1726 * 0xhhhhllll
1727 */
1728 brw_F32TO16(p, dst_w, x);
1729 }
1730
1731 void
1732 fs_generator::generate_shader_time_add(fs_inst *,
1733 struct brw_reg payload,
1734 struct brw_reg offset,
1735 struct brw_reg value)
1736 {
1737 const tgl_swsb swsb = brw_get_default_swsb(p);
1738
1739 assert(devinfo->gen >= 7);
1740 brw_push_insn_state(p);
1741 brw_set_default_mask_control(p, true);
1742 brw_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1743
1744 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1745 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1746 offset.type);
1747 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1748 value.type);
1749
1750 assert(offset.file == BRW_IMMEDIATE_VALUE);
1751 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1752 value.width = BRW_WIDTH_1;
1753 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1754 value.vstride = BRW_VERTICAL_STRIDE_0;
1755 } else {
1756 assert(value.file == BRW_IMMEDIATE_VALUE);
1757 }
1758
1759 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1760 * case, and we don't really care about squeezing every bit of performance
1761 * out of this path, so we just emit the MOVs from here.
1762 */
1763 brw_MOV(p, payload_offset, offset);
1764 brw_set_default_swsb(p, tgl_swsb_null());
1765 brw_MOV(p, payload_value, value);
1766 brw_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1767 brw_shader_time_add(p, payload,
1768 prog_data->binding_table.shader_time_start);
1769 brw_pop_insn_state(p);
1770 }
1771
1772 void
1773 fs_generator::enable_debug(const char *shader_name)
1774 {
1775 debug_flag = true;
1776 this->shader_name = shader_name;
1777 }
1778
1779 int
1780 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
1781 struct shader_stats shader_stats,
1782 const brw::performance &perf,
1783 struct brw_compile_stats *stats)
1784 {
1785 /* align to 64 byte boundary. */
1786 while (p->next_insn_offset % 64)
1787 brw_NOP(p);
1788
1789 this->dispatch_width = dispatch_width;
1790
1791 int start_offset = p->next_insn_offset;
1792
1793 /* `send_count` explicitly does not include spills or fills, as we'd
1794 * like to use it as a metric for intentional memory access or other
1795 * shared function use. Otherwise, subtle changes to scheduling or
1796 * register allocation could cause it to fluctuate wildly - and that
1797 * effect is already counted in spill/fill counts.
1798 */
1799 int spill_count = 0, fill_count = 0;
1800 int loop_count = 0, send_count = 0, nop_count = 0;
1801 bool is_accum_used = false;
1802
1803 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1804
1805 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1806 if (inst->opcode == SHADER_OPCODE_UNDEF)
1807 continue;
1808
1809 struct brw_reg src[4], dst;
1810 unsigned int last_insn_offset = p->next_insn_offset;
1811 bool multiple_instructions_emitted = false;
1812
1813 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1814 * "Register Region Restrictions" section: for BDW, SKL:
1815 *
1816 * "A POW/FDIV operation must not be followed by an instruction
1817 * that requires two destination registers."
1818 *
1819 * The documentation is often lacking annotations for Atom parts,
1820 * and empirically this affects CHV as well.
1821 */
1822 if (devinfo->gen >= 8 &&
1823 devinfo->gen <= 9 &&
1824 p->nr_insn > 1 &&
1825 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1826 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1827 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1828 brw_NOP(p);
1829 last_insn_offset = p->next_insn_offset;
1830
1831 /* In order to avoid spurious instruction count differences when the
1832 * instruction schedule changes, keep track of the number of inserted
1833 * NOPs.
1834 */
1835 nop_count++;
1836 }
1837
1838 /* GEN:BUG:14010017096:
1839 *
1840 * Clear accumulator register before end of thread.
1841 */
1842 if (inst->eot && is_accum_used && devinfo->gen >= 12) {
1843 brw_set_default_exec_size(p, BRW_EXECUTE_16);
1844 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1845 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1846 brw_MOV(p, brw_acc_reg(8), brw_imm_f(0.0f));
1847 last_insn_offset = p->next_insn_offset;
1848 }
1849
1850 if (!is_accum_used && !inst->eot) {
1851 is_accum_used = inst->writes_accumulator_implicitly(devinfo) ||
1852 inst->dst.is_accumulator();
1853 }
1854
1855 if (unlikely(debug_flag))
1856 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1857
1858 /* If the instruction writes to more than one register, it needs to be
1859 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1860 * hardware figures out by itself what the right compression mode is,
1861 * but we still need to know whether the instruction is compressed to
1862 * set up the source register regions appropriately.
1863 *
1864 * XXX - This is wrong for instructions that write a single register but
1865 * read more than one which should strictly speaking be treated as
1866 * compressed. For instructions that don't write any registers it
1867 * relies on the destination being a null register of the correct
1868 * type and regioning so the instruction is considered compressed
1869 * or not accordingly.
1870 */
1871 const bool compressed =
1872 inst->dst.component_size(inst->exec_size) > REG_SIZE;
1873 brw_set_default_compression(p, compressed);
1874 brw_set_default_group(p, inst->group);
1875
1876 for (unsigned int i = 0; i < inst->sources; i++) {
1877 src[i] = brw_reg_from_fs_reg(devinfo, inst,
1878 &inst->src[i], compressed);
1879 /* The accumulator result appears to get used for the
1880 * conditional modifier generation. When negating a UD
1881 * value, there is a 33rd bit generated for the sign in the
1882 * accumulator value, so now you can't check, for example,
1883 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1884 */
1885 assert(!inst->conditional_mod ||
1886 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1887 !inst->src[i].negate);
1888 }
1889 dst = brw_reg_from_fs_reg(devinfo, inst,
1890 &inst->dst, compressed);
1891
1892 brw_set_default_access_mode(p, BRW_ALIGN_1);
1893 brw_set_default_predicate_control(p, inst->predicate);
1894 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1895 /* On gen7 and above, hardware automatically adds the group onto the
1896 * flag subregister number. On Sandy Bridge and older, we have to do it
1897 * ourselves.
1898 */
1899 const unsigned flag_subreg = inst->flag_subreg +
1900 (devinfo->gen >= 7 ? 0 : inst->group / 16);
1901 brw_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2);
1902 brw_set_default_saturate(p, inst->saturate);
1903 brw_set_default_mask_control(p, inst->force_writemask_all);
1904 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1905 brw_set_default_swsb(p, inst->sched);
1906
1907 unsigned exec_size = inst->exec_size;
1908 if (devinfo->gen == 7 && !devinfo->is_haswell &&
1909 (get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) {
1910 exec_size *= 2;
1911 }
1912
1913 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1914
1915 assert(inst->force_writemask_all || inst->exec_size >= 4);
1916 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
1917 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1918 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1919
1920 switch (inst->opcode) {
1921 case BRW_OPCODE_SYNC:
1922 assert(src[0].file == BRW_IMMEDIATE_VALUE);
1923 brw_SYNC(p, tgl_sync_function(src[0].ud));
1924 break;
1925 case BRW_OPCODE_MOV:
1926 brw_MOV(p, dst, src[0]);
1927 break;
1928 case BRW_OPCODE_ADD:
1929 brw_ADD(p, dst, src[0], src[1]);
1930 break;
1931 case BRW_OPCODE_MUL:
1932 brw_MUL(p, dst, src[0], src[1]);
1933 break;
1934 case BRW_OPCODE_AVG:
1935 brw_AVG(p, dst, src[0], src[1]);
1936 break;
1937 case BRW_OPCODE_MACH:
1938 brw_MACH(p, dst, src[0], src[1]);
1939 break;
1940
1941 case BRW_OPCODE_LINE:
1942 brw_LINE(p, dst, src[0], src[1]);
1943 break;
1944
1945 case BRW_OPCODE_MAD:
1946 assert(devinfo->gen >= 6);
1947 if (devinfo->gen < 10)
1948 brw_set_default_access_mode(p, BRW_ALIGN_16);
1949 brw_MAD(p, dst, src[0], src[1], src[2]);
1950 break;
1951
1952 case BRW_OPCODE_LRP:
1953 assert(devinfo->gen >= 6 && devinfo->gen <= 10);
1954 if (devinfo->gen < 10)
1955 brw_set_default_access_mode(p, BRW_ALIGN_16);
1956 brw_LRP(p, dst, src[0], src[1], src[2]);
1957 break;
1958
1959 case BRW_OPCODE_FRC:
1960 brw_FRC(p, dst, src[0]);
1961 break;
1962 case BRW_OPCODE_RNDD:
1963 brw_RNDD(p, dst, src[0]);
1964 break;
1965 case BRW_OPCODE_RNDE:
1966 brw_RNDE(p, dst, src[0]);
1967 break;
1968 case BRW_OPCODE_RNDZ:
1969 brw_RNDZ(p, dst, src[0]);
1970 break;
1971
1972 case BRW_OPCODE_AND:
1973 brw_AND(p, dst, src[0], src[1]);
1974 break;
1975 case BRW_OPCODE_OR:
1976 brw_OR(p, dst, src[0], src[1]);
1977 break;
1978 case BRW_OPCODE_XOR:
1979 brw_XOR(p, dst, src[0], src[1]);
1980 break;
1981 case BRW_OPCODE_NOT:
1982 brw_NOT(p, dst, src[0]);
1983 break;
1984 case BRW_OPCODE_ASR:
1985 brw_ASR(p, dst, src[0], src[1]);
1986 break;
1987 case BRW_OPCODE_SHR:
1988 brw_SHR(p, dst, src[0], src[1]);
1989 break;
1990 case BRW_OPCODE_SHL:
1991 brw_SHL(p, dst, src[0], src[1]);
1992 break;
1993 case BRW_OPCODE_ROL:
1994 assert(devinfo->gen >= 11);
1995 assert(src[0].type == dst.type);
1996 brw_ROL(p, dst, src[0], src[1]);
1997 break;
1998 case BRW_OPCODE_ROR:
1999 assert(devinfo->gen >= 11);
2000 assert(src[0].type == dst.type);
2001 brw_ROR(p, dst, src[0], src[1]);
2002 break;
2003 case BRW_OPCODE_F32TO16:
2004 assert(devinfo->gen >= 7);
2005 brw_F32TO16(p, dst, src[0]);
2006 break;
2007 case BRW_OPCODE_F16TO32:
2008 assert(devinfo->gen >= 7);
2009 brw_F16TO32(p, dst, src[0]);
2010 break;
2011 case BRW_OPCODE_CMP:
2012 if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
2013 dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
2014 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
2015 * implemented in the compiler is not sufficient. Overriding the
2016 * type when the destination is the null register is necessary but
2017 * not sufficient by itself.
2018 */
2019 assert(dst.nr == BRW_ARF_NULL);
2020 dst.type = BRW_REGISTER_TYPE_D;
2021 }
2022 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
2023 break;
2024 case BRW_OPCODE_SEL:
2025 brw_SEL(p, dst, src[0], src[1]);
2026 break;
2027 case BRW_OPCODE_CSEL:
2028 assert(devinfo->gen >= 8);
2029 if (devinfo->gen < 10)
2030 brw_set_default_access_mode(p, BRW_ALIGN_16);
2031 brw_CSEL(p, dst, src[0], src[1], src[2]);
2032 break;
2033 case BRW_OPCODE_BFREV:
2034 assert(devinfo->gen >= 7);
2035 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
2036 retype(src[0], BRW_REGISTER_TYPE_UD));
2037 break;
2038 case BRW_OPCODE_FBH:
2039 assert(devinfo->gen >= 7);
2040 brw_FBH(p, retype(dst, src[0].type), src[0]);
2041 break;
2042 case BRW_OPCODE_FBL:
2043 assert(devinfo->gen >= 7);
2044 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
2045 retype(src[0], BRW_REGISTER_TYPE_UD));
2046 break;
2047 case BRW_OPCODE_LZD:
2048 brw_LZD(p, dst, src[0]);
2049 break;
2050 case BRW_OPCODE_CBIT:
2051 assert(devinfo->gen >= 7);
2052 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
2053 retype(src[0], BRW_REGISTER_TYPE_UD));
2054 break;
2055 case BRW_OPCODE_ADDC:
2056 assert(devinfo->gen >= 7);
2057 brw_ADDC(p, dst, src[0], src[1]);
2058 break;
2059 case BRW_OPCODE_SUBB:
2060 assert(devinfo->gen >= 7);
2061 brw_SUBB(p, dst, src[0], src[1]);
2062 break;
2063 case BRW_OPCODE_MAC:
2064 brw_MAC(p, dst, src[0], src[1]);
2065 break;
2066
2067 case BRW_OPCODE_BFE:
2068 assert(devinfo->gen >= 7);
2069 if (devinfo->gen < 10)
2070 brw_set_default_access_mode(p, BRW_ALIGN_16);
2071 brw_BFE(p, dst, src[0], src[1], src[2]);
2072 break;
2073
2074 case BRW_OPCODE_BFI1:
2075 assert(devinfo->gen >= 7);
2076 brw_BFI1(p, dst, src[0], src[1]);
2077 break;
2078 case BRW_OPCODE_BFI2:
2079 assert(devinfo->gen >= 7);
2080 if (devinfo->gen < 10)
2081 brw_set_default_access_mode(p, BRW_ALIGN_16);
2082 brw_BFI2(p, dst, src[0], src[1], src[2]);
2083 break;
2084
2085 case BRW_OPCODE_IF:
2086 if (inst->src[0].file != BAD_FILE) {
2087 /* The instruction has an embedded compare (only allowed on gen6) */
2088 assert(devinfo->gen == 6);
2089 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
2090 } else {
2091 brw_IF(p, brw_get_default_exec_size(p));
2092 }
2093 break;
2094
2095 case BRW_OPCODE_ELSE:
2096 brw_ELSE(p);
2097 break;
2098 case BRW_OPCODE_ENDIF:
2099 brw_ENDIF(p);
2100 break;
2101
2102 case BRW_OPCODE_DO:
2103 brw_DO(p, brw_get_default_exec_size(p));
2104 break;
2105
2106 case BRW_OPCODE_BREAK:
2107 brw_BREAK(p);
2108 break;
2109 case BRW_OPCODE_CONTINUE:
2110 brw_CONT(p);
2111 break;
2112
2113 case BRW_OPCODE_WHILE:
2114 brw_WHILE(p);
2115 loop_count++;
2116 break;
2117
2118 case SHADER_OPCODE_RCP:
2119 case SHADER_OPCODE_RSQ:
2120 case SHADER_OPCODE_SQRT:
2121 case SHADER_OPCODE_EXP2:
2122 case SHADER_OPCODE_LOG2:
2123 case SHADER_OPCODE_SIN:
2124 case SHADER_OPCODE_COS:
2125 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2126 if (devinfo->gen >= 6) {
2127 assert(inst->mlen == 0);
2128 assert(devinfo->gen >= 7 || inst->exec_size == 8);
2129 gen6_math(p, dst, brw_math_function(inst->opcode),
2130 src[0], brw_null_reg());
2131 } else {
2132 assert(inst->mlen >= 1);
2133 assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
2134 gen4_math(p, dst,
2135 brw_math_function(inst->opcode),
2136 inst->base_mrf, src[0],
2137 BRW_MATH_PRECISION_FULL);
2138 send_count++;
2139 }
2140 break;
2141 case SHADER_OPCODE_INT_QUOTIENT:
2142 case SHADER_OPCODE_INT_REMAINDER:
2143 case SHADER_OPCODE_POW:
2144 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2145 if (devinfo->gen >= 6) {
2146 assert(inst->mlen == 0);
2147 assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
2148 inst->exec_size == 8);
2149 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2150 } else {
2151 assert(inst->mlen >= 1);
2152 assert(inst->exec_size == 8);
2153 gen4_math(p, dst, brw_math_function(inst->opcode),
2154 inst->base_mrf, src[0],
2155 BRW_MATH_PRECISION_FULL);
2156 send_count++;
2157 }
2158 break;
2159 case FS_OPCODE_LINTERP:
2160 multiple_instructions_emitted = generate_linterp(inst, dst, src);
2161 break;
2162 case FS_OPCODE_PIXEL_X:
2163 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2164 src[0].subnr = 0 * type_sz(src[0].type);
2165 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2166 break;
2167 case FS_OPCODE_PIXEL_Y:
2168 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2169 src[0].subnr = 4 * type_sz(src[0].type);
2170 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2171 break;
2172
2173 case SHADER_OPCODE_SEND:
2174 generate_send(inst, dst, src[0], src[1], src[2],
2175 inst->ex_mlen > 0 ? src[3] : brw_null_reg());
2176 if ((inst->desc & 0xff) == BRW_BTI_STATELESS ||
2177 (inst->desc & 0xff) == GEN8_BTI_STATELESS_NON_COHERENT) {
2178 if (inst->size_written)
2179 fill_count++;
2180 else
2181 spill_count++;
2182 } else {
2183 send_count++;
2184 }
2185 break;
2186
2187 case SHADER_OPCODE_GET_BUFFER_SIZE:
2188 generate_get_buffer_size(inst, dst, src[0], src[1]);
2189 send_count++;
2190 break;
2191 case SHADER_OPCODE_TEX:
2192 case FS_OPCODE_TXB:
2193 case SHADER_OPCODE_TXD:
2194 case SHADER_OPCODE_TXF:
2195 case SHADER_OPCODE_TXF_CMS:
2196 case SHADER_OPCODE_TXL:
2197 case SHADER_OPCODE_TXS:
2198 case SHADER_OPCODE_LOD:
2199 case SHADER_OPCODE_TG4:
2200 case SHADER_OPCODE_SAMPLEINFO:
2201 assert(inst->src[0].file == BAD_FILE);
2202 generate_tex(inst, dst, src[1], src[2]);
2203 send_count++;
2204 break;
2205
2206 case FS_OPCODE_DDX_COARSE:
2207 case FS_OPCODE_DDX_FINE:
2208 generate_ddx(inst, dst, src[0]);
2209 break;
2210 case FS_OPCODE_DDY_COARSE:
2211 case FS_OPCODE_DDY_FINE:
2212 generate_ddy(inst, dst, src[0]);
2213 break;
2214
2215 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2216 generate_scratch_write(inst, src[0]);
2217 spill_count++;
2218 break;
2219
2220 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2221 generate_scratch_read(inst, dst);
2222 fill_count++;
2223 break;
2224
2225 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2226 generate_scratch_read_gen7(inst, dst);
2227 fill_count++;
2228 break;
2229
2230 case SHADER_OPCODE_MOV_INDIRECT:
2231 generate_mov_indirect(inst, dst, src[0], src[1]);
2232 break;
2233
2234 case SHADER_OPCODE_URB_READ_SIMD8:
2235 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2236 generate_urb_read(inst, dst, src[0]);
2237 send_count++;
2238 break;
2239
2240 case SHADER_OPCODE_URB_WRITE_SIMD8:
2241 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2242 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2243 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2244 generate_urb_write(inst, src[0]);
2245 send_count++;
2246 break;
2247
2248 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2249 assert(inst->force_writemask_all);
2250 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2251 send_count++;
2252 break;
2253
2254 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2255 assert(inst->force_writemask_all);
2256 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2257 send_count++;
2258 break;
2259
2260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
2261 generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
2262 send_count++;
2263 break;
2264
2265 case FS_OPCODE_REP_FB_WRITE:
2266 case FS_OPCODE_FB_WRITE:
2267 generate_fb_write(inst, src[0]);
2268 send_count++;
2269 break;
2270
2271 case FS_OPCODE_FB_READ:
2272 generate_fb_read(inst, dst, src[0]);
2273 send_count++;
2274 break;
2275
2276 case FS_OPCODE_DISCARD_JUMP:
2277 generate_discard_jump(inst);
2278 break;
2279
2280 case SHADER_OPCODE_SHADER_TIME_ADD:
2281 generate_shader_time_add(inst, src[0], src[1], src[2]);
2282 break;
2283
2284 case SHADER_OPCODE_INTERLOCK:
2285 case SHADER_OPCODE_MEMORY_FENCE: {
2286 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2287 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2288
2289 const enum opcode send_op = inst->opcode == SHADER_OPCODE_INTERLOCK ?
2290 BRW_OPCODE_SENDC : BRW_OPCODE_SEND;
2291
2292 brw_memory_fence(p, dst, src[0], send_op,
2293 brw_message_target(inst->sfid),
2294 /* commit_enable */ src[1].ud,
2295 /* bti */ src[2].ud);
2296 send_count++;
2297 break;
2298 }
2299
2300 case FS_OPCODE_SCHEDULING_FENCE:
2301 if (inst->sources == 0 && inst->sched.regdist == 0 &&
2302 inst->sched.mode == TGL_SBID_NULL) {
2303 if (unlikely(debug_flag))
2304 disasm_info->use_tail = true;
2305 break;
2306 }
2307
2308 if (devinfo->gen >= 12) {
2309 /* Use the available SWSB information to stall. A single SYNC is
2310 * sufficient since if there were multiple dependencies, the
2311 * scoreboard algorithm already injected other SYNCs before this
2312 * instruction.
2313 */
2314 brw_SYNC(p, TGL_SYNC_NOP);
2315 } else {
2316 for (unsigned i = 0; i < inst->sources; i++) {
2317 /* Emit a MOV to force a stall until the instruction producing the
2318 * registers finishes.
2319 */
2320 brw_MOV(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW),
2321 retype(src[i], BRW_REGISTER_TYPE_UW));
2322 }
2323
2324 if (inst->sources > 1)
2325 multiple_instructions_emitted = true;
2326 }
2327
2328 break;
2329
2330 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
2331 const struct brw_reg mask =
2332 brw_stage_has_packed_dispatch(devinfo, stage,
2333 prog_data) ? brw_imm_ud(~0u) :
2334 stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() :
2335 brw_dmask_reg();
2336 brw_find_live_channel(p, dst, mask);
2337 break;
2338 }
2339 case FS_OPCODE_LOAD_LIVE_CHANNELS: {
2340 assert(devinfo->gen >= 8);
2341 assert(inst->force_writemask_all && inst->group == 0);
2342 assert(inst->dst.file == BAD_FILE);
2343 brw_set_default_exec_size(p, BRW_EXECUTE_1);
2344 brw_MOV(p, retype(brw_flag_subreg(inst->flag_subreg),
2345 BRW_REGISTER_TYPE_UD),
2346 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD));
2347 break;
2348 }
2349 case SHADER_OPCODE_BROADCAST:
2350 assert(inst->force_writemask_all);
2351 brw_broadcast(p, dst, src[0], src[1]);
2352 break;
2353
2354 case SHADER_OPCODE_SHUFFLE:
2355 generate_shuffle(inst, dst, src[0], src[1]);
2356 break;
2357
2358 case SHADER_OPCODE_SEL_EXEC:
2359 assert(inst->force_writemask_all);
2360 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
2361 brw_MOV(p, dst, src[1]);
2362 brw_set_default_mask_control(p, BRW_MASK_ENABLE);
2363 brw_set_default_swsb(p, tgl_swsb_null());
2364 brw_MOV(p, dst, src[0]);
2365 break;
2366
2367 case SHADER_OPCODE_QUAD_SWIZZLE:
2368 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2369 assert(src[1].type == BRW_REGISTER_TYPE_UD);
2370 generate_quad_swizzle(inst, dst, src[0], src[1].ud);
2371 break;
2372
2373 case SHADER_OPCODE_CLUSTER_BROADCAST: {
2374 assert(!src[0].negate && !src[0].abs);
2375 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2376 assert(src[1].type == BRW_REGISTER_TYPE_UD);
2377 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2378 assert(src[2].type == BRW_REGISTER_TYPE_UD);
2379 const unsigned component = src[1].ud;
2380 const unsigned cluster_size = src[2].ud;
2381 unsigned vstride = cluster_size;
2382 unsigned width = cluster_size;
2383
2384 /* The maximum exec_size is 32, but the maximum width is only 16. */
2385 if (inst->exec_size == width) {
2386 vstride = 0;
2387 width = 1;
2388 }
2389
2390 struct brw_reg strided = stride(suboffset(src[0], component),
2391 vstride, width, 0);
2392 if (type_sz(src[0].type) > 4 &&
2393 (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
2394 /* IVB has an issue (which we found empirically) where it reads
2395 * two address register components per channel for indirectly
2396 * addressed 64-bit sources.
2397 *
2398 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2399 *
2400 * "When source or destination datatype is 64b or operation is
2401 * integer DWord multiply, indirect addressing must not be
2402 * used."
2403 *
2404 * To work around both of these, we do two integer MOVs insead of
2405 * one 64-bit MOV. Because no double value should ever cross a
2406 * register boundary, it's safe to use the immediate offset in the
2407 * indirect here to handle adding 4 bytes to the offset and avoid
2408 * the extra ADD to the register file.
2409 */
2410 assert(src[0].type == dst.type);
2411 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
2412 subscript(strided, BRW_REGISTER_TYPE_D, 0));
2413 brw_set_default_swsb(p, tgl_swsb_null());
2414 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
2415 subscript(strided, BRW_REGISTER_TYPE_D, 1));
2416 } else {
2417 brw_MOV(p, dst, strided);
2418 }
2419 break;
2420 }
2421
2422 case FS_OPCODE_SET_SAMPLE_ID:
2423 generate_set_sample_id(inst, dst, src[0], src[1]);
2424 break;
2425
2426 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2427 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2428 break;
2429
2430 case FS_OPCODE_PLACEHOLDER_HALT:
2431 /* This is the place where the final HALT needs to be inserted if
2432 * we've emitted any discards. If not, this will emit no code.
2433 */
2434 if (!patch_discard_jumps_to_fb_writes()) {
2435 if (unlikely(debug_flag)) {
2436 disasm_info->use_tail = true;
2437 }
2438 }
2439 break;
2440
2441 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2442 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2443 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2444 send_count++;
2445 break;
2446
2447 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2448 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2449 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2450 send_count++;
2451 break;
2452
2453 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2454 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2455 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2456 send_count++;
2457 break;
2458
2459 case CS_OPCODE_CS_TERMINATE:
2460 generate_cs_terminate(inst, src[0]);
2461 send_count++;
2462 break;
2463
2464 case SHADER_OPCODE_BARRIER:
2465 generate_barrier(inst, src[0]);
2466 send_count++;
2467 break;
2468
2469 case BRW_OPCODE_DIM:
2470 assert(devinfo->is_haswell);
2471 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2472 assert(dst.type == BRW_REGISTER_TYPE_DF);
2473 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2474 break;
2475
2476 case SHADER_OPCODE_RND_MODE: {
2477 assert(src[0].file == BRW_IMMEDIATE_VALUE);
2478 /*
2479 * Changes the floating point rounding mode updating the control
2480 * register field defined at cr0.0[5-6] bits.
2481 */
2482 enum brw_rnd_mode mode =
2483 (enum brw_rnd_mode) (src[0].d << BRW_CR0_RND_MODE_SHIFT);
2484 brw_float_controls_mode(p, mode, BRW_CR0_RND_MODE_MASK);
2485 }
2486 break;
2487
2488 case SHADER_OPCODE_FLOAT_CONTROL_MODE:
2489 assert(src[0].file == BRW_IMMEDIATE_VALUE);
2490 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2491 brw_float_controls_mode(p, src[0].d, src[1].d);
2492 break;
2493
2494 default:
2495 unreachable("Unsupported opcode");
2496
2497 case SHADER_OPCODE_LOAD_PAYLOAD:
2498 unreachable("Should be lowered by lower_load_payload()");
2499 }
2500
2501 if (multiple_instructions_emitted)
2502 continue;
2503
2504 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2505 assert(p->next_insn_offset == last_insn_offset + 16 ||
2506 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2507 "emitting more than 1 instruction");
2508
2509 brw_inst *last = &p->store[last_insn_offset / 16];
2510
2511 if (inst->conditional_mod)
2512 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2513 if (devinfo->gen < 12) {
2514 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2515 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2516 }
2517 }
2518 }
2519
2520 brw_set_uip_jip(p, start_offset);
2521
2522 /* end of program sentinel */
2523 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2524
2525 #ifndef NDEBUG
2526 bool validated =
2527 #else
2528 if (unlikely(debug_flag))
2529 #endif
2530 brw_validate_instructions(devinfo, p->store,
2531 start_offset,
2532 p->next_insn_offset,
2533 disasm_info);
2534
2535 int before_size = p->next_insn_offset - start_offset;
2536 brw_compact_instructions(p, start_offset, disasm_info);
2537 int after_size = p->next_insn_offset - start_offset;
2538
2539 if (unlikely(debug_flag)) {
2540 unsigned char sha1[21];
2541 char sha1buf[41];
2542
2543 _mesa_sha1_compute(p->store + start_offset / sizeof(brw_inst),
2544 after_size, sha1);
2545 _mesa_sha1_format(sha1buf, sha1);
2546
2547 fprintf(stderr, "Native code for %s (sha1 %s)\n"
2548 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2549 "%d:%d spills:fills, %u sends, "
2550 "scheduled with mode %s. "
2551 "Promoted %u constants. "
2552 "Compacted %d to %d bytes (%.0f%%)\n",
2553 shader_name, sha1buf,
2554 dispatch_width, before_size / 16,
2555 loop_count, perf.latency,
2556 spill_count, fill_count, send_count,
2557 shader_stats.scheduler_mode,
2558 shader_stats.promoted_constants,
2559 before_size, after_size,
2560 100.0f * (before_size - after_size) / before_size);
2561
2562 /* overriding the shader makes disasm_info invalid */
2563 if (!brw_try_override_assembly(p, start_offset, sha1buf)) {
2564 dump_assembly(p->store, start_offset, p->next_insn_offset,
2565 disasm_info, perf.block_latency);
2566 } else {
2567 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
2568 }
2569 }
2570 ralloc_free(disasm_info);
2571 assert(validated);
2572
2573 compiler->shader_debug_log(log_data,
2574 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2575 "%d:%d spills:fills, %u sends, "
2576 "scheduled with mode %s, "
2577 "Promoted %u constants, "
2578 "compacted %d to %d bytes.",
2579 _mesa_shader_stage_to_abbrev(stage),
2580 dispatch_width, before_size / 16 - nop_count,
2581 loop_count, perf.latency,
2582 spill_count, fill_count, send_count,
2583 shader_stats.scheduler_mode,
2584 shader_stats.promoted_constants,
2585 before_size, after_size);
2586 if (stats) {
2587 stats->dispatch_width = dispatch_width;
2588 stats->instructions = before_size / 16 - nop_count;
2589 stats->sends = send_count;
2590 stats->loops = loop_count;
2591 stats->cycles = perf.latency;
2592 stats->spills = spill_count;
2593 stats->fills = fill_count;
2594 }
2595
2596 return start_offset;
2597 }
2598
2599 const unsigned *
2600 fs_generator::get_assembly()
2601 {
2602 return brw_get_program(p, &prog_data->program_size);
2603 }