2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 const unsigned max_hw_width
= 16;
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
96 if (reg
->stride
> 4) {
97 assert(reg
!= &inst
->dst
);
98 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
99 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
100 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
102 const unsigned width
= MIN3(reg_width
, phys_width
, max_hw_width
);
103 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
104 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
107 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
127 * It applies to BayTrail too.
129 if (type_sz(reg
->type
) == 8) {
131 if (brw_reg
.vstride
> 0)
133 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
142 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
143 type_sz(inst
->dst
.type
) < 8) {
144 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
150 brw_reg
= retype(brw_reg
, reg
->type
);
151 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
152 brw_reg
.abs
= reg
->abs
;
153 brw_reg
.negate
= reg
->negate
;
158 assert(reg
->offset
== 0);
159 brw_reg
= reg
->as_brw_reg();
162 /* Probably unused. */
163 brw_reg
= brw_null_reg();
167 unreachable("not reached");
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
174 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
175 type_sz(reg
->type
) == 8 &&
176 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
177 brw_reg
.width
== BRW_WIDTH_1
&&
178 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
179 brw_reg
.width
= BRW_WIDTH_2
;
180 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
186 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
188 struct brw_stage_prog_data
*prog_data
,
189 bool runtime_check_aads_emit
,
190 gl_shader_stage stage
)
192 : compiler(compiler
), log_data(log_data
),
193 devinfo(compiler
->devinfo
),
194 prog_data(prog_data
),
195 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
196 stage(stage
), mem_ctx(mem_ctx
)
198 p
= rzalloc(mem_ctx
, struct brw_codegen
);
199 brw_init_codegen(devinfo
, p
, mem_ctx
);
201 /* In the FS code generator, we are very careful to ensure that we always
202 * set the right execution size so we don't need the EU code to "help" us
203 * by trying to infer it. Sometimes, it infers the wrong thing.
205 p
->automatic_exec_sizes
= false;
208 fs_generator::~fs_generator()
212 class ip_record
: public exec_node
{
214 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
225 fs_generator::patch_discard_jumps_to_fb_writes()
227 if (this->discard_halt_patches
.is_empty())
230 int scale
= brw_jump_scale(p
->devinfo
);
232 if (devinfo
->gen
>= 6) {
233 /* There is a somewhat strange undocumented requirement of using
234 * HALT, according to the simulator. If some channel has HALTed to
235 * a particular UIP, then by the end of the program, every channel
236 * must have HALTed to that UIP. Furthermore, the tracking is a
237 * stack, so you can't do the final halt of a UIP after starting
238 * halting to a new UIP.
240 * Symptoms of not emitting this instruction on actual hardware
241 * included GPU hangs and sparkly rendering on the piglit discard
244 brw_inst
*last_halt
= brw_HALT(p
);
245 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
246 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
251 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
252 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
254 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
255 if (devinfo
->gen
>= 6) {
256 /* HALT takes a half-instruction distance from the pre-incremented IP. */
257 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
259 brw_set_src1(p
, patch
, brw_imm_d((ip
- patch_ip
->ip
) * scale
));
263 this->discard_halt_patches
.make_empty();
265 if (devinfo
->gen
< 6) {
266 /* From the g965 PRM:
268 * "As DMask is not automatically reloaded into AMask upon completion
269 * of this instruction, software has to manually restore AMask upon
272 * DMask lives in the bottom 16 bits of sr0.1.
274 brw_inst
*reset
= brw_MOV(p
, brw_mask_reg(BRW_AMASK
),
275 retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
));
276 brw_inst_set_exec_size(devinfo
, reset
, BRW_EXECUTE_1
);
277 brw_inst_set_mask_control(devinfo
, reset
, BRW_MASK_DISABLE
);
278 brw_inst_set_qtr_control(devinfo
, reset
, BRW_COMPRESSION_NONE
);
279 brw_inst_set_thread_control(devinfo
, reset
, BRW_THREAD_SWITCH
);
282 if (devinfo
->gen
== 4 && !devinfo
->is_g4x
) {
283 /* From the g965 PRM:
285 * "[DevBW, DevCL] Erratum: The subfields in mask stack register are
286 * reset to zero during graphics reset, however, they are not
287 * initialized at thread dispatch. These subfields will retain the
288 * values from the previous thread. Software should make sure the
289 * mask stack is empty (reset to zero) before terminating the thread.
290 * In case that this is not practical, software may have to reset the
291 * mask stack at the beginning of each kernel, which will impact the
294 * Luckily we can rely on:
296 * "[DevBW, DevCL] This register access restriction is not
297 * applicable, hardware does ensure execution pipeline coherency,
298 * when a mask stack register is used as an explicit source and/or
301 brw_push_insn_state(p
);
302 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
303 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
305 brw_set_default_exec_size(p
, BRW_EXECUTE_2
);
306 brw_MOV(p
, vec2(brw_mask_stack_depth_reg(0)), brw_imm_uw(0));
308 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
309 /* Reset the if stack. */
310 brw_MOV(p
, retype(brw_mask_stack_reg(0), BRW_REGISTER_TYPE_UW
),
313 brw_pop_insn_state(p
);
320 fs_generator::generate_send(fs_inst
*inst
,
323 struct brw_reg ex_desc
,
324 struct brw_reg payload
,
325 struct brw_reg payload2
)
327 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
328 dst
.nr
== BRW_ARF_NULL
;
329 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
331 uint32_t desc_imm
= inst
->desc
|
332 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
334 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
336 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
337 /* If we have any sort of extended descriptor, then we need SENDS. This
338 * also covers the dual-payload case because ex_mlen goes in ex_desc.
340 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
341 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
344 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
,
345 devinfo
->gen
>= 12 ? BRW_OPCODE_SENDC
: BRW_OPCODE_SENDSC
);
347 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
350 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
355 fs_generator::fire_fb_write(fs_inst
*inst
,
356 struct brw_reg payload
,
357 struct brw_reg implied_header
,
360 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
362 if (devinfo
->gen
< 6) {
363 brw_push_insn_state(p
);
364 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
365 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
366 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
367 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
368 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
369 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
370 brw_pop_insn_state(p
);
373 uint32_t msg_control
= brw_fb_write_msg_control(inst
, prog_data
);
375 /* We assume render targets start at 0, because headerless FB write
376 * messages set "Render Target Index" to 0. Using a different binding
377 * table index would make it impossible to use headerless messages.
379 const uint32_t surf_index
= inst
->target
;
381 brw_inst
*insn
= brw_fb_WRITE(p
,
383 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
390 inst
->header_size
!= 0);
392 if (devinfo
->gen
>= 6)
393 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
397 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
399 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
400 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
401 brw_set_default_flag_reg(p
, 0, 0);
404 const struct brw_reg implied_header
=
405 devinfo
->gen
< 6 ? payload
: brw_null_reg();
407 if (inst
->base_mrf
>= 0)
408 payload
= brw_message_reg(inst
->base_mrf
);
410 if (!runtime_check_aads_emit
) {
411 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
413 /* This can only happen in gen < 6 */
414 assert(devinfo
->gen
< 6);
416 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
418 /* Check runtime bit to detect if we have to send AA data or not */
419 brw_push_insn_state(p
);
420 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
421 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
424 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
426 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
428 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
429 brw_pop_insn_state(p
);
431 /* Don't send AA data */
432 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
434 brw_land_fwd_jump(p
, jmp
);
435 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
440 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
441 struct brw_reg payload
)
443 assert(inst
->size_written
% REG_SIZE
== 0);
444 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
445 /* We assume that render targets start at binding table index 0. */
446 const unsigned surf_index
= inst
->target
;
448 gen9_fb_READ(p
, dst
, payload
, surf_index
,
449 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
450 prog_data
->persample_dispatch
);
454 fs_generator::generate_mov_indirect(fs_inst
*inst
,
457 struct brw_reg indirect_byte_offset
)
459 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
460 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
461 assert(!reg
.abs
&& !reg
.negate
);
462 assert(reg
.type
== dst
.type
);
464 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
466 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
467 imm_byte_offset
+= indirect_byte_offset
.ud
;
469 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
470 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
471 brw_MOV(p
, dst
, reg
);
473 /* Prior to Broadwell, there are only 8 address registers. */
474 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
476 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
477 struct brw_reg addr
= vec8(brw_address_reg(0));
479 /* Whether we can use destination dependency control without running the
480 * risk of a hang if an instruction gets shot down.
482 const bool use_dep_ctrl
= !inst
->predicate
&&
483 inst
->exec_size
== dispatch_width
;
486 /* The destination stride of an instruction (in bytes) must be greater
487 * than or equal to the size of the rest of the instruction. Since the
488 * address register is of type UW, we can't use a D-type instruction.
489 * In order to get around this, re retype to UW and use a stride.
491 indirect_byte_offset
=
492 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
494 /* There are a number of reasons why we don't use the base offset here.
495 * One reason is that the field is only 9 bits which means we can only
496 * use it to access the first 16 GRFs. Also, from the Haswell PRM
497 * section "Register Region Restrictions":
499 * "The lower bits of the AddressImmediate must not overflow to
500 * change the register address. The lower 5 bits of Address
501 * Immediate when added to lower 5 bits of address register gives
502 * the sub-register offset. The upper bits of Address Immediate
503 * when added to upper bits of address register gives the register
504 * address. Any overflow from sub-register offset is dropped."
506 * Since the indirect may cause us to cross a register boundary, this
507 * makes the base offset almost useless. We could try and do something
508 * clever where we use a actual base offset if base_offset % 32 == 0 but
509 * that would mean we were generating different code depending on the
510 * base offset. Instead, for the sake of consistency, we'll just do the
511 * add ourselves. This restriction is only listed in the Haswell PRM
512 * but empirical testing indicates that it applies on all older
513 * generations and is lifted on Broadwell.
515 * In the end, while base_offset is nice to look at in the generated
516 * code, using it saves us 0 instructions and would require quite a bit
517 * of case-by-case work. It's just not worth it.
519 * Due to a hardware bug some platforms (particularly Gen11+) seem to
520 * require the address components of all channels to be valid whether or
521 * not they're active, which causes issues if we use VxH addressing
522 * under non-uniform control-flow. We can easily work around that by
523 * initializing the whole address register with a pipelined NoMask MOV
526 if (devinfo
->gen
>= 7) {
527 insn
= brw_MOV(p
, addr
, brw_imm_uw(imm_byte_offset
));
528 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
529 brw_inst_set_pred_control(devinfo
, insn
, BRW_PREDICATE_NONE
);
530 if (devinfo
->gen
>= 12)
531 brw_set_default_swsb(p
, tgl_swsb_null());
533 brw_inst_set_no_dd_clear(devinfo
, insn
, use_dep_ctrl
);
536 insn
= brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
537 if (devinfo
->gen
>= 12)
538 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
539 else if (devinfo
->gen
>= 7)
540 brw_inst_set_no_dd_check(devinfo
, insn
, use_dep_ctrl
);
542 if (type_sz(reg
.type
) > 4 &&
543 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
544 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
545 !devinfo
->has_64bit_float
)) {
546 /* IVB has an issue (which we found empirically) where it reads two
547 * address register components per channel for indirectly addressed
550 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
552 * "When source or destination datatype is 64b or operation is
553 * integer DWord multiply, indirect addressing must not be used."
555 * To work around both of these, we do two integer MOVs insead of one
556 * 64-bit MOV. Because no double value should ever cross a register
557 * boundary, it's safe to use the immediate offset in the indirect
558 * here to handle adding 4 bytes to the offset and avoid the extra
559 * ADD to the register file.
561 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
562 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
563 brw_set_default_swsb(p
, tgl_swsb_null());
564 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
565 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
567 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
569 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
571 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
572 !inst
->get_next()->is_tail_sentinel() &&
573 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
574 /* From the Sandybridge PRM:
576 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
577 * instruction that “indexed/indirect” source AND is followed
578 * by a send, the instruction requires a “Switch”. This is to
579 * avoid race condition where send may dispatch before MRF is
582 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
589 fs_generator::generate_shuffle(fs_inst
*inst
,
594 /* Ivy bridge has some strange behavior that makes this a real pain to
595 * implement for 64-bit values so we just don't bother.
597 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
599 /* Because we're using the address register, we're limited to 8-wide
600 * execution on gen7. On gen8, we're limited to 16-wide by the address
601 * register file and 8-wide for 64-bit types. We could try and make this
602 * instruction splittable higher up in the compiler but that gets weird
603 * because it reads all of the channels regardless of execution size. It's
604 * easier just to split it here.
606 const unsigned lower_width
=
607 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
608 8 : MIN2(16, inst
->exec_size
);
610 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
611 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
612 brw_set_default_group(p
, group
);
614 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
615 idx
.file
== BRW_IMMEDIATE_VALUE
) {
616 /* Trivial, the source is already uniform or the index is a constant.
617 * We will typically not get here if the optimizer is doing its job,
618 * but asserting would be mean.
620 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
621 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
623 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
624 struct brw_reg addr
= vec8(brw_address_reg(0));
626 struct brw_reg group_idx
= suboffset(idx
, group
);
628 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
629 /* Things get grumpy if the register is too wide. */
634 assert(type_sz(group_idx
.type
) <= 4);
635 if (type_sz(group_idx
.type
) == 4) {
636 /* The destination stride of an instruction (in bytes) must be
637 * greater than or equal to the size of the rest of the
638 * instruction. Since the address register is of type UW, we
639 * can't use a D-type instruction. In order to get around this,
640 * re retype to UW and use a stride.
642 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
645 /* Take into account the component size and horizontal stride. */
646 assert(src
.vstride
== src
.hstride
+ src
.width
);
647 brw_SHL(p
, addr
, group_idx
,
648 brw_imm_uw(util_logbase2(type_sz(src
.type
)) +
651 /* Add on the register start offset */
652 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
653 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
655 if (type_sz(src
.type
) > 4 &&
656 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
657 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
658 /* IVB has an issue (which we found empirically) where it reads
659 * two address register components per channel for indirectly
660 * addressed 64-bit sources.
662 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
664 * "When source or destination datatype is 64b or operation is
665 * integer DWord multiply, indirect addressing must not be
668 * To work around both of these, we do two integer MOVs insead of
669 * one 64-bit MOV. Because no double value should ever cross a
670 * register boundary, it's safe to use the immediate offset in the
671 * indirect here to handle adding 4 bytes to the offset and avoid
672 * the extra ADD to the register file.
674 struct brw_reg gdst
= suboffset(dst
, group
);
675 struct brw_reg dst_d
= retype(spread(gdst
, 2),
676 BRW_REGISTER_TYPE_D
);
677 assert(dst
.hstride
== 1);
679 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
680 brw_set_default_swsb(p
, tgl_swsb_null());
681 brw_MOV(p
, byte_offset(dst_d
, 4),
682 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
684 brw_MOV(p
, suboffset(dst
, group
* dst
.hstride
),
685 retype(brw_VxH_indirect(0, 0), src
.type
));
689 brw_set_default_swsb(p
, tgl_swsb_null());
694 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
695 struct brw_reg dst
, struct brw_reg src
,
698 /* Requires a quad. */
699 assert(inst
->exec_size
>= 4);
701 if (src
.file
== BRW_IMMEDIATE_VALUE
||
702 has_scalar_region(src
)) {
703 /* The value is uniform across all channels */
704 brw_MOV(p
, dst
, src
);
706 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
707 /* This only works on 8-wide 32-bit values */
708 assert(inst
->exec_size
== 8);
709 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
710 assert(src
.vstride
== src
.width
+ 1);
711 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
712 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
713 swiz_src
.swizzle
= swiz
;
714 brw_MOV(p
, dst
, swiz_src
);
717 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
718 assert(src
.vstride
== src
.width
+ 1);
719 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
722 case BRW_SWIZZLE_XXXX
:
723 case BRW_SWIZZLE_YYYY
:
724 case BRW_SWIZZLE_ZZZZ
:
725 case BRW_SWIZZLE_WWWW
:
726 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
729 case BRW_SWIZZLE_XXZZ
:
730 case BRW_SWIZZLE_YYWW
:
731 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
734 case BRW_SWIZZLE_XYXY
:
735 case BRW_SWIZZLE_ZWZW
:
736 assert(inst
->exec_size
== 4);
737 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
741 assert(inst
->force_writemask_all
);
742 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
744 for (unsigned c
= 0; c
< 4; c
++) {
745 brw_inst
*insn
= brw_MOV(
746 p
, stride(suboffset(dst
, c
),
747 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
748 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
750 if (devinfo
->gen
< 12) {
751 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
752 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
755 brw_set_default_swsb(p
, tgl_swsb_null());
764 fs_generator::generate_urb_read(fs_inst
*inst
,
766 struct brw_reg header
)
768 assert(inst
->size_written
% REG_SIZE
== 0);
769 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
770 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
772 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
773 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
774 brw_set_src0(p
, send
, header
);
775 if (devinfo
->gen
< 12)
776 brw_set_src1(p
, send
, brw_imm_ud(0u));
778 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
779 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
781 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
782 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
784 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
785 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
786 brw_inst_set_header_present(p
->devinfo
, send
, true);
787 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
791 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
795 /* WaClearTDRRegBeforeEOTForNonPS.
797 * WA: Clear tdr register before send EOT in all non-PS shader kernels
799 * mov(8) tdr0:ud 0x0:ud {NoMask}"
801 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
802 brw_push_insn_state(p
);
803 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
804 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
805 brw_pop_insn_state(p
);
808 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
810 brw_set_dest(p
, insn
, brw_null_reg());
811 brw_set_src0(p
, insn
, payload
);
812 if (devinfo
->gen
< 12)
813 brw_set_src1(p
, insn
, brw_imm_ud(0u));
815 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
816 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
818 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
819 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
820 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
822 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
823 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
824 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
826 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
827 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
828 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
829 brw_inst_set_header_present(p
->devinfo
, insn
, true);
830 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
834 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
836 struct brw_inst
*insn
;
838 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
840 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
841 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
842 if (devinfo
->gen
< 12)
843 brw_set_src1(p
, insn
, brw_imm_ud(0u));
845 /* Terminate a compute shader by sending a message to the thread spawner.
847 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
848 brw_inst_set_mlen(devinfo
, insn
, 1);
849 brw_inst_set_rlen(devinfo
, insn
, 0);
850 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
851 brw_inst_set_header_present(devinfo
, insn
, false);
853 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
855 if (devinfo
->gen
< 11) {
856 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
858 /* Note that even though the thread has a URB resource associated with it,
859 * we set the "do not dereference URB" bit, because the URB resource is
860 * managed by the fixed-function unit, so it will free it automatically.
862 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
865 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
869 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
872 if (devinfo
->gen
>= 12) {
873 brw_set_default_swsb(p
, tgl_swsb_null());
874 brw_SYNC(p
, TGL_SYNC_BAR
);
881 fs_generator::generate_linterp(fs_inst
*inst
,
882 struct brw_reg dst
, struct brw_reg
*src
)
886 * -----------------------------------
887 * | src1+0 | src1+1 | src1+2 | src1+3 |
888 * |-----------------------------------|
889 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
890 * -----------------------------------
892 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
894 * -----------------------------------
895 * | src1+0 | src1+1 | src1+2 | src1+3 |
896 * |-----------------------------------|
897 * |(x0, x1)|(y0, y1)| | | in SIMD8
898 * |-----------------------------------|
899 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
900 * -----------------------------------
902 * See also: emit_interpolation_setup_gen4().
904 struct brw_reg delta_x
= src
[0];
905 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
906 struct brw_reg interp
= src
[1];
909 /* nir_lower_interpolation() will do the lowering to MAD instructions for
912 assert(devinfo
->gen
< 11);
914 if (devinfo
->has_pln
) {
915 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
916 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
918 * "[DevSNB]:<src1> must be even register aligned.
920 * This restriction is lifted on Ivy Bridge.
922 * This means that we need to split PLN into LINE+MAC on-the-fly.
923 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
924 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
925 * coordinate registers are laid out differently so we leave it as a
926 * SIMD16 instruction.
928 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
929 assert(inst
->group
% 16 == 0);
931 brw_push_insn_state(p
);
932 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
934 /* Thanks to two accumulators, we can emit all the LINEs and then all
935 * the MACs. This improves parallelism a bit.
937 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
938 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
939 offset(delta_x
, g
* 2));
940 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
942 /* LINE writes the accumulator automatically on gen4-5. On Sandy
943 * Bridge and later, we have to explicitly enable it.
945 if (devinfo
->gen
>= 6)
946 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
948 /* brw_set_default_saturate() is called before emitting
949 * instructions, so the saturate bit is set in each instruction,
950 * so we need to unset it on the LINE instructions.
952 brw_inst_set_saturate(p
->devinfo
, line
, false);
955 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
956 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
957 offset(delta_x
, g
* 2 + 1));
958 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
959 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
962 brw_pop_insn_state(p
);
966 brw_PLN(p
, dst
, interp
, delta_x
);
971 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
972 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
974 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
976 /* brw_set_default_saturate() is called before emitting instructions, so
977 * the saturate bit is set in each instruction, so we need to unset it on
978 * the first instruction.
980 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
987 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
990 struct brw_reg surf_index
)
992 assert(devinfo
->gen
>= 7);
993 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
998 switch (inst
->exec_size
) {
1000 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1003 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1006 unreachable("Invalid width for texture instruction");
1009 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1015 retype(dst
, BRW_REGISTER_TYPE_UW
),
1020 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
1021 rlen
, /* response length */
1023 inst
->header_size
> 0,
1025 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
1029 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
1030 struct brw_reg surface_index
,
1031 struct brw_reg sampler_index
)
1033 assert(devinfo
->gen
< 7);
1034 assert(inst
->size_written
% REG_SIZE
== 0);
1037 uint32_t return_format
;
1039 /* Sampler EOT message of less than the dispatch width would kill the
1040 * thread prematurely.
1042 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
1045 case BRW_REGISTER_TYPE_D
:
1046 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
1048 case BRW_REGISTER_TYPE_UD
:
1049 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
1052 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1056 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
1057 * is set as part of the message descriptor. On gen4, the PRM seems to
1058 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
1059 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
1060 * gone from the message descriptor entirely and you just get UINT32 all
1061 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
1062 * just stomp it to UINT32 all the time.
1064 if (inst
->opcode
== SHADER_OPCODE_TXS
)
1065 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
1067 switch (inst
->exec_size
) {
1069 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1072 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1075 unreachable("Invalid width for texture instruction");
1078 if (devinfo
->gen
>= 5) {
1079 switch (inst
->opcode
) {
1080 case SHADER_OPCODE_TEX
:
1081 if (inst
->shadow_compare
) {
1082 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1084 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1088 if (inst
->shadow_compare
) {
1089 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1091 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1094 case SHADER_OPCODE_TXL
:
1095 if (inst
->shadow_compare
) {
1096 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1098 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1101 case SHADER_OPCODE_TXS
:
1102 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1104 case SHADER_OPCODE_TXD
:
1105 assert(!inst
->shadow_compare
);
1106 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1108 case SHADER_OPCODE_TXF
:
1109 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1111 case SHADER_OPCODE_TXF_CMS
:
1112 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1114 case SHADER_OPCODE_LOD
:
1115 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1117 case SHADER_OPCODE_TG4
:
1118 assert(devinfo
->gen
== 6);
1119 assert(!inst
->shadow_compare
);
1120 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1122 case SHADER_OPCODE_SAMPLEINFO
:
1123 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1126 unreachable("not reached");
1129 switch (inst
->opcode
) {
1130 case SHADER_OPCODE_TEX
:
1131 /* Note that G45 and older determines shadow compare and dispatch width
1132 * from message length for most messages.
1134 if (inst
->exec_size
== 8) {
1135 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1136 if (inst
->shadow_compare
) {
1137 assert(inst
->mlen
== 6);
1139 assert(inst
->mlen
<= 4);
1142 if (inst
->shadow_compare
) {
1143 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1144 assert(inst
->mlen
== 9);
1146 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1147 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1152 if (inst
->shadow_compare
) {
1153 assert(inst
->exec_size
== 8);
1154 assert(inst
->mlen
== 6);
1155 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1157 assert(inst
->mlen
== 9);
1158 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1159 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1162 case SHADER_OPCODE_TXL
:
1163 if (inst
->shadow_compare
) {
1164 assert(inst
->exec_size
== 8);
1165 assert(inst
->mlen
== 6);
1166 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1168 assert(inst
->mlen
== 9);
1169 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1170 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1173 case SHADER_OPCODE_TXD
:
1174 /* There is no sample_d_c message; comparisons are done manually */
1175 assert(inst
->exec_size
== 8);
1176 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1177 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1179 case SHADER_OPCODE_TXF
:
1180 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1181 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1182 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1184 case SHADER_OPCODE_TXS
:
1185 assert(inst
->mlen
== 3);
1186 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1187 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1190 unreachable("not reached");
1193 assert(msg_type
!= -1);
1195 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1199 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1201 /* Load the message header if present. If there's a texture offset,
1202 * we need to set it up explicitly and load the offset bitfield.
1203 * Otherwise, we can use an implied move from g0 to the first message reg.
1205 struct brw_reg src
= brw_null_reg();
1206 if (inst
->header_size
!= 0) {
1207 if (devinfo
->gen
< 6 && !inst
->offset
) {
1208 /* Set up an implied move from g0 to the MRF. */
1209 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1211 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1212 assert(inst
->base_mrf
!= -1);
1213 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1215 brw_push_insn_state(p
);
1216 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1217 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1218 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1219 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1220 /* Explicitly set up the message header by copying g0 to the MRF. */
1221 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1222 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1224 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1226 /* Set the offset bits in DWord 2. */
1227 brw_MOV(p
, get_element_ud(header_reg
, 2),
1228 brw_imm_ud(inst
->offset
));
1231 brw_pop_insn_state(p
);
1232 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1236 uint32_t base_binding_table_index
;
1237 switch (inst
->opcode
) {
1238 case SHADER_OPCODE_TG4
:
1239 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1242 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1246 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1247 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1250 retype(dst
, BRW_REGISTER_TYPE_UW
),
1253 surface_index
.ud
+ base_binding_table_index
,
1254 sampler_index
.ud
% 16,
1256 inst
->size_written
/ REG_SIZE
,
1258 inst
->header_size
!= 0,
1264 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1267 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1269 * Ideally, we want to produce:
1272 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1273 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1274 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1275 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1276 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1277 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1278 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1279 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1281 * and add another set of two more subspans if in 16-pixel dispatch mode.
1283 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1284 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1285 * pair. But the ideal approximation may impose a huge performance cost on
1286 * sample_d. On at least Haswell, sample_d instruction does some
1287 * optimizations if the same LOD is used for all pixels in the subspan.
1289 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1290 * appropriate swizzling.
1293 fs_generator::generate_ddx(const fs_inst
*inst
,
1294 struct brw_reg dst
, struct brw_reg src
)
1296 unsigned vstride
, width
;
1298 if (devinfo
->gen
>= 8) {
1299 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1300 /* produce accurate derivatives */
1301 vstride
= BRW_VERTICAL_STRIDE_2
;
1302 width
= BRW_WIDTH_2
;
1304 /* replicate the derivative at the top-left pixel to other pixels */
1305 vstride
= BRW_VERTICAL_STRIDE_4
;
1306 width
= BRW_WIDTH_4
;
1309 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1310 struct brw_reg src1
= src
;
1312 src0
.vstride
= vstride
;
1314 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1315 src1
.vstride
= vstride
;
1317 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1319 brw_ADD(p
, dst
, src0
, negate(src1
));
1321 /* On Haswell and earlier, the region used above appears to not work
1322 * correctly for compressed instructions. At least on Haswell and
1323 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1324 * would have to split to SIMD8 no matter which method we choose, we
1325 * may as well use ALIGN16 on all platforms gen7 and earlier.
1327 struct brw_reg src0
= stride(src
, 4, 4, 1);
1328 struct brw_reg src1
= stride(src
, 4, 4, 1);
1329 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1330 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1331 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1333 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1334 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1337 brw_push_insn_state(p
);
1338 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1339 brw_ADD(p
, dst
, negate(src0
), src1
);
1340 brw_pop_insn_state(p
);
1344 /* The negate_value boolean is used to negate the derivative computation for
1345 * FBOs, since they place the origin at the upper left instead of the lower
1349 fs_generator::generate_ddy(const fs_inst
*inst
,
1350 struct brw_reg dst
, struct brw_reg src
)
1352 const uint32_t type_size
= type_sz(src
.type
);
1354 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1355 /* produce accurate derivatives.
1357 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1358 * "Register Region Restrictions", Section "1. Special Restrictions":
1360 * "In Align16 mode, the channel selects and channel enables apply to
1361 * a pair of half-floats, because these parameters are defined for
1362 * DWord elements ONLY. This is applicable when both source and
1363 * destination are half-floats."
1365 * So for half-float operations we use the Gen11+ Align1 path. CHV
1366 * inherits its FP16 hardware from SKL, so it is not affected.
1368 if (devinfo
->gen
>= 11 ||
1369 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1370 src
= stride(src
, 0, 2, 1);
1372 brw_push_insn_state(p
);
1373 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1374 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1375 brw_set_default_group(p
, inst
->group
+ g
);
1376 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1377 negate(byte_offset(src
, g
* type_size
)),
1378 byte_offset(src
, (g
+ 2) * type_size
));
1379 brw_set_default_swsb(p
, tgl_swsb_null());
1381 brw_pop_insn_state(p
);
1383 struct brw_reg src0
= stride(src
, 4, 4, 1);
1384 struct brw_reg src1
= stride(src
, 4, 4, 1);
1385 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1386 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1388 brw_push_insn_state(p
);
1389 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1390 brw_ADD(p
, dst
, negate(src0
), src1
);
1391 brw_pop_insn_state(p
);
1394 /* replicate the derivative at the top-left pixel to other pixels */
1395 if (devinfo
->gen
>= 8) {
1396 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1397 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1399 brw_ADD(p
, dst
, negate(src0
), src1
);
1401 /* On Haswell and earlier, the region used above appears to not work
1402 * correctly for compressed instructions. At least on Haswell and
1403 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1404 * would have to split to SIMD8 no matter which method we choose, we
1405 * may as well use ALIGN16 on all platforms gen7 and earlier.
1407 struct brw_reg src0
= stride(src
, 4, 4, 1);
1408 struct brw_reg src1
= stride(src
, 4, 4, 1);
1409 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1410 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1412 brw_push_insn_state(p
);
1413 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1414 brw_ADD(p
, dst
, negate(src0
), src1
);
1415 brw_pop_insn_state(p
);
1421 fs_generator::generate_discard_jump(fs_inst
*)
1423 /* This HALT will be patched up at FB write time to point UIP at the end of
1424 * the program, and at brw_uip_jip() JIP will be set to the end of the
1425 * current block (or the program).
1427 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1432 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1434 /* The 32-wide messages only respect the first 16-wide half of the channel
1435 * enable signals which are replicated identically for the second group of
1436 * 16 channels, so we cannot use them unless the write is marked
1437 * force_writemask_all.
1439 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1440 MIN2(16, inst
->exec_size
);
1441 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1442 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1443 assert(inst
->mlen
!= 0);
1445 brw_push_insn_state(p
);
1446 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1447 brw_set_default_compression(p
, lower_size
> 8);
1449 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1450 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1453 assert(swsb
.mode
& TGL_SBID_SET
);
1454 brw_set_default_swsb(p
, tgl_swsb_sbid(TGL_SBID_SRC
, swsb
.sbid
));
1456 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1459 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1460 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1462 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1463 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1465 inst
->offset
+ block_size
* REG_SIZE
* i
);
1468 brw_pop_insn_state(p
);
1472 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1474 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1475 assert(inst
->mlen
!= 0);
1477 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1478 inst
->exec_size
/ 8, inst
->offset
);
1482 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1484 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1486 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1490 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1492 struct brw_reg index
,
1493 struct brw_reg offset
)
1495 assert(type_sz(dst
.type
) == 4);
1496 assert(inst
->mlen
!= 0);
1498 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1499 index
.type
== BRW_REGISTER_TYPE_UD
);
1500 uint32_t surf_index
= index
.ud
;
1502 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1503 offset
.type
== BRW_REGISTER_TYPE_UD
);
1504 uint32_t read_offset
= offset
.ud
;
1506 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1507 read_offset
, surf_index
);
1511 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1513 struct brw_reg index
,
1514 struct brw_reg payload
)
1516 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1517 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1518 assert(type_sz(dst
.type
) == 4);
1520 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1521 const uint32_t surf_index
= index
.ud
;
1523 brw_push_insn_state(p
);
1524 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1525 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1526 brw_pop_insn_state(p
);
1528 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1529 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1530 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1531 brw_set_desc(p
, send
,
1532 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1534 brw_dp_read_desc(devinfo
, surf_index
,
1535 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1536 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1537 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1540 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1541 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1543 brw_push_insn_state(p
);
1544 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1546 /* a0.0 = surf_index & 0xff */
1547 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1548 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1549 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1550 brw_set_dest(p
, insn_and
, addr
);
1551 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1552 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1554 /* dst = send(payload, a0.0 | <descriptor>) */
1555 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1556 brw_send_indirect_message(
1557 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1558 retype(dst
, BRW_REGISTER_TYPE_UD
),
1559 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1560 brw_message_desc(devinfo
, 1,
1561 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1562 brw_dp_read_desc(devinfo
, 0 /* surface */,
1563 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1564 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1565 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1568 brw_pop_insn_state(p
);
1573 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1575 struct brw_reg index
)
1577 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1578 assert(inst
->header_size
!= 0);
1581 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1582 index
.type
== BRW_REGISTER_TYPE_UD
);
1583 uint32_t surf_index
= index
.ud
;
1585 uint32_t simd_mode
, rlen
, msg_type
;
1586 if (inst
->exec_size
== 16) {
1587 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1590 assert(inst
->exec_size
== 8);
1591 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1595 if (devinfo
->gen
>= 5)
1596 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1598 /* We always use the SIMD16 message so that we only have to load U, and
1601 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1602 assert(inst
->mlen
== 3);
1603 assert(inst
->size_written
== 8 * REG_SIZE
);
1605 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1608 struct brw_reg header
= brw_vec8_grf(0, 0);
1609 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1611 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1612 brw_inst_set_compression(devinfo
, send
, false);
1613 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1614 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1615 brw_set_src0(p
, send
, header
);
1616 if (devinfo
->gen
< 6)
1617 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1619 /* Our surface is set up as floats, regardless of what actual data is
1622 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1623 brw_set_desc(p
, send
,
1624 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1625 brw_sampler_desc(devinfo
, surf_index
,
1626 0, /* sampler (unused) */
1627 msg_type
, simd_mode
, return_format
));
1631 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1634 struct brw_reg msg_data
,
1637 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1638 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1639 assert(inst
->size_written
% REG_SIZE
== 0);
1641 brw_pixel_interpolator_query(p
,
1642 retype(dst
, BRW_REGISTER_TYPE_UW
),
1643 /* If we don't have a payload, what we send doesn't matter */
1644 has_payload
? src
: brw_vec8_grf(0, 0),
1645 inst
->pi_noperspective
,
1648 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1649 inst
->size_written
/ REG_SIZE
);
1652 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1653 * the ADD instruction.
1656 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1658 struct brw_reg src0
,
1659 struct brw_reg src1
)
1661 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1662 dst
.type
== BRW_REGISTER_TYPE_UD
);
1663 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1664 src0
.type
== BRW_REGISTER_TYPE_UD
);
1666 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1667 const unsigned lower_size
= MIN2(inst
->exec_size
,
1668 devinfo
->gen
>= 8 ? 16 : 8);
1670 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1671 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1672 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1673 (i
* lower_size
/ (1 << src0
.width
))) *
1674 type_sz(src0
.type
) / REG_SIZE
),
1675 suboffset(reg
, i
* lower_size
/ 4));
1676 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1677 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1678 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1679 brw_set_default_swsb(p
, tgl_swsb_null());
1684 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1689 assert(devinfo
->gen
>= 7);
1690 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1691 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1692 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1694 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1696 * Because this instruction does not have a 16-bit floating-point type,
1697 * the destination data type must be Word (W).
1699 * The destination must be DWord-aligned and specify a horizontal stride
1700 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1701 * each destination channel and the upper word is not modified.
1703 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1705 /* Give each 32-bit channel of dst the form below, where "." means
1709 brw_F32TO16(p
, dst_w
, y
);
1714 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1715 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1717 /* And, finally the form of packHalf2x16's output:
1720 brw_F32TO16(p
, dst_w
, x
);
1724 fs_generator::generate_shader_time_add(fs_inst
*,
1725 struct brw_reg payload
,
1726 struct brw_reg offset
,
1727 struct brw_reg value
)
1729 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1731 assert(devinfo
->gen
>= 7);
1732 brw_push_insn_state(p
);
1733 brw_set_default_mask_control(p
, true);
1734 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1736 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1737 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1739 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1742 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1743 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1744 value
.width
= BRW_WIDTH_1
;
1745 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1746 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1748 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1751 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1752 * case, and we don't really care about squeezing every bit of performance
1753 * out of this path, so we just emit the MOVs from here.
1755 brw_MOV(p
, payload_offset
, offset
);
1756 brw_set_default_swsb(p
, tgl_swsb_null());
1757 brw_MOV(p
, payload_value
, value
);
1758 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1759 brw_shader_time_add(p
, payload
,
1760 prog_data
->binding_table
.shader_time_start
);
1761 brw_pop_insn_state(p
);
1765 fs_generator::enable_debug(const char *shader_name
)
1768 this->shader_name
= shader_name
;
1772 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1773 struct shader_stats shader_stats
,
1774 const brw::performance
&perf
,
1775 struct brw_compile_stats
*stats
)
1777 /* align to 64 byte boundary. */
1778 while (p
->next_insn_offset
% 64)
1781 this->dispatch_width
= dispatch_width
;
1783 int start_offset
= p
->next_insn_offset
;
1785 /* `send_count` explicitly does not include spills or fills, as we'd
1786 * like to use it as a metric for intentional memory access or other
1787 * shared function use. Otherwise, subtle changes to scheduling or
1788 * register allocation could cause it to fluctuate wildly - and that
1789 * effect is already counted in spill/fill counts.
1791 int spill_count
= 0, fill_count
= 0;
1792 int loop_count
= 0, send_count
= 0, nop_count
= 0;
1793 bool is_accum_used
= false;
1795 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1797 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1798 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1801 struct brw_reg src
[4], dst
;
1802 unsigned int last_insn_offset
= p
->next_insn_offset
;
1803 bool multiple_instructions_emitted
= false;
1805 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1806 * "Register Region Restrictions" section: for BDW, SKL:
1808 * "A POW/FDIV operation must not be followed by an instruction
1809 * that requires two destination registers."
1811 * The documentation is often lacking annotations for Atom parts,
1812 * and empirically this affects CHV as well.
1814 if (devinfo
->gen
>= 8 &&
1815 devinfo
->gen
<= 9 &&
1817 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1818 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1819 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1821 last_insn_offset
= p
->next_insn_offset
;
1823 /* In order to avoid spurious instruction count differences when the
1824 * instruction schedule changes, keep track of the number of inserted
1830 /* GEN:BUG:14010017096:
1832 * Clear accumulator register before end of thread.
1834 if (inst
->eot
&& is_accum_used
&& devinfo
->gen
>= 12) {
1835 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
1836 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1837 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1838 brw_MOV(p
, brw_acc_reg(8), brw_imm_f(0.0f
));
1839 last_insn_offset
= p
->next_insn_offset
;
1842 if (!is_accum_used
&& !inst
->eot
) {
1843 is_accum_used
= inst
->writes_accumulator_implicitly(devinfo
) ||
1844 inst
->dst
.is_accumulator();
1847 if (unlikely(debug_flag
))
1848 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1850 /* If the instruction writes to more than one register, it needs to be
1851 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1852 * hardware figures out by itself what the right compression mode is,
1853 * but we still need to know whether the instruction is compressed to
1854 * set up the source register regions appropriately.
1856 * XXX - This is wrong for instructions that write a single register but
1857 * read more than one which should strictly speaking be treated as
1858 * compressed. For instructions that don't write any registers it
1859 * relies on the destination being a null register of the correct
1860 * type and regioning so the instruction is considered compressed
1861 * or not accordingly.
1863 const bool compressed
=
1864 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1865 brw_set_default_compression(p
, compressed
);
1866 brw_set_default_group(p
, inst
->group
);
1868 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1869 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1870 &inst
->src
[i
], compressed
);
1871 /* The accumulator result appears to get used for the
1872 * conditional modifier generation. When negating a UD
1873 * value, there is a 33rd bit generated for the sign in the
1874 * accumulator value, so now you can't check, for example,
1875 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1877 assert(!inst
->conditional_mod
||
1878 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1879 !inst
->src
[i
].negate
);
1881 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1882 &inst
->dst
, compressed
);
1884 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1885 brw_set_default_predicate_control(p
, inst
->predicate
);
1886 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1887 /* On gen7 and above, hardware automatically adds the group onto the
1888 * flag subregister number. On Sandy Bridge and older, we have to do it
1891 const unsigned flag_subreg
= inst
->flag_subreg
+
1892 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1893 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1894 brw_set_default_saturate(p
, inst
->saturate
);
1895 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1896 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1897 brw_set_default_swsb(p
, inst
->sched
);
1899 unsigned exec_size
= inst
->exec_size
;
1900 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1901 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1905 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1907 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1908 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1909 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1910 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1912 switch (inst
->opcode
) {
1913 case BRW_OPCODE_SYNC
:
1914 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
1915 brw_SYNC(p
, tgl_sync_function(src
[0].ud
));
1917 case BRW_OPCODE_MOV
:
1918 brw_MOV(p
, dst
, src
[0]);
1920 case BRW_OPCODE_ADD
:
1921 brw_ADD(p
, dst
, src
[0], src
[1]);
1923 case BRW_OPCODE_MUL
:
1924 brw_MUL(p
, dst
, src
[0], src
[1]);
1926 case BRW_OPCODE_AVG
:
1927 brw_AVG(p
, dst
, src
[0], src
[1]);
1929 case BRW_OPCODE_MACH
:
1930 brw_MACH(p
, dst
, src
[0], src
[1]);
1933 case BRW_OPCODE_LINE
:
1934 brw_LINE(p
, dst
, src
[0], src
[1]);
1937 case BRW_OPCODE_MAD
:
1938 assert(devinfo
->gen
>= 6);
1939 if (devinfo
->gen
< 10)
1940 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1941 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1944 case BRW_OPCODE_LRP
:
1945 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1946 if (devinfo
->gen
< 10)
1947 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1948 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1951 case BRW_OPCODE_FRC
:
1952 brw_FRC(p
, dst
, src
[0]);
1954 case BRW_OPCODE_RNDD
:
1955 brw_RNDD(p
, dst
, src
[0]);
1957 case BRW_OPCODE_RNDE
:
1958 brw_RNDE(p
, dst
, src
[0]);
1960 case BRW_OPCODE_RNDZ
:
1961 brw_RNDZ(p
, dst
, src
[0]);
1964 case BRW_OPCODE_AND
:
1965 brw_AND(p
, dst
, src
[0], src
[1]);
1968 brw_OR(p
, dst
, src
[0], src
[1]);
1970 case BRW_OPCODE_XOR
:
1971 brw_XOR(p
, dst
, src
[0], src
[1]);
1973 case BRW_OPCODE_NOT
:
1974 brw_NOT(p
, dst
, src
[0]);
1976 case BRW_OPCODE_ASR
:
1977 brw_ASR(p
, dst
, src
[0], src
[1]);
1979 case BRW_OPCODE_SHR
:
1980 brw_SHR(p
, dst
, src
[0], src
[1]);
1982 case BRW_OPCODE_SHL
:
1983 brw_SHL(p
, dst
, src
[0], src
[1]);
1985 case BRW_OPCODE_ROL
:
1986 assert(devinfo
->gen
>= 11);
1987 assert(src
[0].type
== dst
.type
);
1988 brw_ROL(p
, dst
, src
[0], src
[1]);
1990 case BRW_OPCODE_ROR
:
1991 assert(devinfo
->gen
>= 11);
1992 assert(src
[0].type
== dst
.type
);
1993 brw_ROR(p
, dst
, src
[0], src
[1]);
1995 case BRW_OPCODE_F32TO16
:
1996 assert(devinfo
->gen
>= 7);
1997 brw_F32TO16(p
, dst
, src
[0]);
1999 case BRW_OPCODE_F16TO32
:
2000 assert(devinfo
->gen
>= 7);
2001 brw_F16TO32(p
, dst
, src
[0]);
2003 case BRW_OPCODE_CMP
:
2004 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
2005 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
2006 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
2007 * implemented in the compiler is not sufficient. Overriding the
2008 * type when the destination is the null register is necessary but
2009 * not sufficient by itself.
2011 assert(dst
.nr
== BRW_ARF_NULL
);
2012 dst
.type
= BRW_REGISTER_TYPE_D
;
2014 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2016 case BRW_OPCODE_SEL
:
2017 brw_SEL(p
, dst
, src
[0], src
[1]);
2019 case BRW_OPCODE_CSEL
:
2020 assert(devinfo
->gen
>= 8);
2021 if (devinfo
->gen
< 10)
2022 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2023 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
2025 case BRW_OPCODE_BFREV
:
2026 assert(devinfo
->gen
>= 7);
2027 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
2028 retype(src
[0], BRW_REGISTER_TYPE_UD
));
2030 case BRW_OPCODE_FBH
:
2031 assert(devinfo
->gen
>= 7);
2032 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
2034 case BRW_OPCODE_FBL
:
2035 assert(devinfo
->gen
>= 7);
2036 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
2037 retype(src
[0], BRW_REGISTER_TYPE_UD
));
2039 case BRW_OPCODE_LZD
:
2040 brw_LZD(p
, dst
, src
[0]);
2042 case BRW_OPCODE_CBIT
:
2043 assert(devinfo
->gen
>= 7);
2044 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
2045 retype(src
[0], BRW_REGISTER_TYPE_UD
));
2047 case BRW_OPCODE_ADDC
:
2048 assert(devinfo
->gen
>= 7);
2049 brw_ADDC(p
, dst
, src
[0], src
[1]);
2051 case BRW_OPCODE_SUBB
:
2052 assert(devinfo
->gen
>= 7);
2053 brw_SUBB(p
, dst
, src
[0], src
[1]);
2055 case BRW_OPCODE_MAC
:
2056 brw_MAC(p
, dst
, src
[0], src
[1]);
2059 case BRW_OPCODE_BFE
:
2060 assert(devinfo
->gen
>= 7);
2061 if (devinfo
->gen
< 10)
2062 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2063 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
2066 case BRW_OPCODE_BFI1
:
2067 assert(devinfo
->gen
>= 7);
2068 brw_BFI1(p
, dst
, src
[0], src
[1]);
2070 case BRW_OPCODE_BFI2
:
2071 assert(devinfo
->gen
>= 7);
2072 if (devinfo
->gen
< 10)
2073 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2074 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2078 if (inst
->src
[0].file
!= BAD_FILE
) {
2079 /* The instruction has an embedded compare (only allowed on gen6) */
2080 assert(devinfo
->gen
== 6);
2081 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2083 brw_IF(p
, brw_get_default_exec_size(p
));
2087 case BRW_OPCODE_ELSE
:
2090 case BRW_OPCODE_ENDIF
:
2095 brw_DO(p
, brw_get_default_exec_size(p
));
2098 case BRW_OPCODE_BREAK
:
2101 case BRW_OPCODE_CONTINUE
:
2105 case BRW_OPCODE_WHILE
:
2110 case SHADER_OPCODE_RCP
:
2111 case SHADER_OPCODE_RSQ
:
2112 case SHADER_OPCODE_SQRT
:
2113 case SHADER_OPCODE_EXP2
:
2114 case SHADER_OPCODE_LOG2
:
2115 case SHADER_OPCODE_SIN
:
2116 case SHADER_OPCODE_COS
:
2117 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2118 if (devinfo
->gen
>= 6) {
2119 assert(inst
->mlen
== 0);
2120 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2121 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2122 src
[0], brw_null_reg());
2124 assert(inst
->mlen
>= 1);
2125 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2127 brw_math_function(inst
->opcode
),
2128 inst
->base_mrf
, src
[0],
2129 BRW_MATH_PRECISION_FULL
);
2133 case SHADER_OPCODE_INT_QUOTIENT
:
2134 case SHADER_OPCODE_INT_REMAINDER
:
2135 case SHADER_OPCODE_POW
:
2136 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2137 if (devinfo
->gen
>= 6) {
2138 assert(inst
->mlen
== 0);
2139 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2140 inst
->exec_size
== 8);
2141 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2143 assert(inst
->mlen
>= 1);
2144 assert(inst
->exec_size
== 8);
2145 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2146 inst
->base_mrf
, src
[0],
2147 BRW_MATH_PRECISION_FULL
);
2151 case FS_OPCODE_LINTERP
:
2152 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2154 case FS_OPCODE_PIXEL_X
:
2155 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2156 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2157 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2159 case FS_OPCODE_PIXEL_Y
:
2160 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2161 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2162 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2165 case SHADER_OPCODE_SEND
:
2166 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2167 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2168 if ((inst
->desc
& 0xff) == BRW_BTI_STATELESS
||
2169 (inst
->desc
& 0xff) == GEN8_BTI_STATELESS_NON_COHERENT
) {
2170 if (inst
->size_written
)
2179 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2180 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2183 case SHADER_OPCODE_TEX
:
2185 case SHADER_OPCODE_TXD
:
2186 case SHADER_OPCODE_TXF
:
2187 case SHADER_OPCODE_TXF_CMS
:
2188 case SHADER_OPCODE_TXL
:
2189 case SHADER_OPCODE_TXS
:
2190 case SHADER_OPCODE_LOD
:
2191 case SHADER_OPCODE_TG4
:
2192 case SHADER_OPCODE_SAMPLEINFO
:
2193 assert(inst
->src
[0].file
== BAD_FILE
);
2194 generate_tex(inst
, dst
, src
[1], src
[2]);
2198 case FS_OPCODE_DDX_COARSE
:
2199 case FS_OPCODE_DDX_FINE
:
2200 generate_ddx(inst
, dst
, src
[0]);
2202 case FS_OPCODE_DDY_COARSE
:
2203 case FS_OPCODE_DDY_FINE
:
2204 generate_ddy(inst
, dst
, src
[0]);
2207 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2208 generate_scratch_write(inst
, src
[0]);
2212 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2213 generate_scratch_read(inst
, dst
);
2217 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2218 generate_scratch_read_gen7(inst
, dst
);
2222 case SHADER_OPCODE_MOV_INDIRECT
:
2223 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2226 case SHADER_OPCODE_URB_READ_SIMD8
:
2227 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2228 generate_urb_read(inst
, dst
, src
[0]);
2232 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2233 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2234 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2235 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2236 generate_urb_write(inst
, src
[0]);
2240 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2241 assert(inst
->force_writemask_all
);
2242 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2246 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2247 assert(inst
->force_writemask_all
);
2248 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2252 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2253 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2257 case FS_OPCODE_REP_FB_WRITE
:
2258 case FS_OPCODE_FB_WRITE
:
2259 generate_fb_write(inst
, src
[0]);
2263 case FS_OPCODE_FB_READ
:
2264 generate_fb_read(inst
, dst
, src
[0]);
2268 case FS_OPCODE_DISCARD_JUMP
:
2269 generate_discard_jump(inst
);
2272 case SHADER_OPCODE_SHADER_TIME_ADD
:
2273 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2276 case SHADER_OPCODE_INTERLOCK
:
2277 case SHADER_OPCODE_MEMORY_FENCE
: {
2278 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2279 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2281 const enum opcode send_op
= inst
->opcode
== SHADER_OPCODE_INTERLOCK
?
2282 BRW_OPCODE_SENDC
: BRW_OPCODE_SEND
;
2284 brw_memory_fence(p
, dst
, src
[0], send_op
,
2285 brw_message_target(inst
->sfid
),
2286 /* commit_enable */ src
[1].ud
,
2287 /* bti */ src
[2].ud
);
2292 case FS_OPCODE_SCHEDULING_FENCE
:
2293 if (inst
->sources
== 0 && inst
->sched
.regdist
== 0 &&
2294 inst
->sched
.mode
== TGL_SBID_NULL
) {
2295 if (unlikely(debug_flag
))
2296 disasm_info
->use_tail
= true;
2300 if (devinfo
->gen
>= 12) {
2301 /* Use the available SWSB information to stall. A single SYNC is
2302 * sufficient since if there were multiple dependencies, the
2303 * scoreboard algorithm already injected other SYNCs before this
2306 brw_SYNC(p
, TGL_SYNC_NOP
);
2308 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
2309 /* Emit a MOV to force a stall until the instruction producing the
2310 * registers finishes.
2312 brw_MOV(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
),
2313 retype(src
[i
], BRW_REGISTER_TYPE_UW
));
2316 if (inst
->sources
> 1)
2317 multiple_instructions_emitted
= true;
2322 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2323 const struct brw_reg mask
=
2324 brw_stage_has_packed_dispatch(devinfo
, stage
,
2325 prog_data
) ? brw_imm_ud(~0u) :
2326 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2328 brw_find_live_channel(p
, dst
, mask
);
2331 case FS_OPCODE_LOAD_LIVE_CHANNELS
: {
2332 assert(devinfo
->gen
>= 8);
2333 assert(inst
->force_writemask_all
&& inst
->group
== 0);
2334 assert(inst
->dst
.file
== BAD_FILE
);
2335 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
2336 brw_MOV(p
, retype(brw_flag_subreg(inst
->flag_subreg
),
2337 BRW_REGISTER_TYPE_UD
),
2338 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD
));
2341 case SHADER_OPCODE_BROADCAST
:
2342 assert(inst
->force_writemask_all
);
2343 brw_broadcast(p
, dst
, src
[0], src
[1]);
2346 case SHADER_OPCODE_SHUFFLE
:
2347 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2350 case SHADER_OPCODE_SEL_EXEC
:
2351 assert(inst
->force_writemask_all
);
2352 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2353 brw_MOV(p
, dst
, src
[1]);
2354 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2355 brw_set_default_swsb(p
, tgl_swsb_null());
2356 brw_MOV(p
, dst
, src
[0]);
2359 case SHADER_OPCODE_QUAD_SWIZZLE
:
2360 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2361 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2362 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2365 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2366 assert(!src
[0].negate
&& !src
[0].abs
);
2367 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2368 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2369 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2370 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2371 const unsigned component
= src
[1].ud
;
2372 const unsigned cluster_size
= src
[2].ud
;
2373 unsigned vstride
= cluster_size
;
2374 unsigned width
= cluster_size
;
2376 /* The maximum exec_size is 32, but the maximum width is only 16. */
2377 if (inst
->exec_size
== width
) {
2382 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2384 if (type_sz(src
[0].type
) > 4 &&
2385 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2386 /* IVB has an issue (which we found empirically) where it reads
2387 * two address register components per channel for indirectly
2388 * addressed 64-bit sources.
2390 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2392 * "When source or destination datatype is 64b or operation is
2393 * integer DWord multiply, indirect addressing must not be
2396 * To work around both of these, we do two integer MOVs insead of
2397 * one 64-bit MOV. Because no double value should ever cross a
2398 * register boundary, it's safe to use the immediate offset in the
2399 * indirect here to handle adding 4 bytes to the offset and avoid
2400 * the extra ADD to the register file.
2402 assert(src
[0].type
== dst
.type
);
2403 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2404 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2405 brw_set_default_swsb(p
, tgl_swsb_null());
2406 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2407 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2409 brw_MOV(p
, dst
, strided
);
2414 case FS_OPCODE_SET_SAMPLE_ID
:
2415 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2418 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2419 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2422 case FS_OPCODE_PLACEHOLDER_HALT
:
2423 /* This is the place where the final HALT needs to be inserted if
2424 * we've emitted any discards. If not, this will emit no code.
2426 if (!patch_discard_jumps_to_fb_writes()) {
2427 if (unlikely(debug_flag
)) {
2428 disasm_info
->use_tail
= true;
2433 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2434 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2435 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2439 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2440 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2441 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2445 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2446 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2447 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2451 case CS_OPCODE_CS_TERMINATE
:
2452 generate_cs_terminate(inst
, src
[0]);
2456 case SHADER_OPCODE_BARRIER
:
2457 generate_barrier(inst
, src
[0]);
2461 case BRW_OPCODE_DIM
:
2462 assert(devinfo
->is_haswell
);
2463 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2464 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2465 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2468 case SHADER_OPCODE_RND_MODE
: {
2469 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2471 * Changes the floating point rounding mode updating the control
2472 * register field defined at cr0.0[5-6] bits.
2474 enum brw_rnd_mode mode
=
2475 (enum brw_rnd_mode
) (src
[0].d
<< BRW_CR0_RND_MODE_SHIFT
);
2476 brw_float_controls_mode(p
, mode
, BRW_CR0_RND_MODE_MASK
);
2480 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
2481 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2482 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2483 brw_float_controls_mode(p
, src
[0].d
, src
[1].d
);
2487 unreachable("Unsupported opcode");
2489 case SHADER_OPCODE_LOAD_PAYLOAD
:
2490 unreachable("Should be lowered by lower_load_payload()");
2493 if (multiple_instructions_emitted
)
2496 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2497 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2498 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2499 "emitting more than 1 instruction");
2501 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2503 if (inst
->conditional_mod
)
2504 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2505 if (devinfo
->gen
< 12) {
2506 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2507 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2512 brw_set_uip_jip(p
, start_offset
);
2514 /* end of program sentinel */
2515 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2520 if (unlikely(debug_flag
))
2522 brw_validate_instructions(devinfo
, p
->store
,
2524 p
->next_insn_offset
,
2527 int before_size
= p
->next_insn_offset
- start_offset
;
2528 brw_compact_instructions(p
, start_offset
, disasm_info
);
2529 int after_size
= p
->next_insn_offset
- start_offset
;
2531 if (unlikely(debug_flag
)) {
2532 unsigned char sha1
[21];
2535 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2537 _mesa_sha1_format(sha1buf
, sha1
);
2539 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2540 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2541 "%d:%d spills:fills, %u sends, "
2542 "scheduled with mode %s. "
2543 "Promoted %u constants. "
2544 "Compacted %d to %d bytes (%.0f%%)\n",
2545 shader_name
, sha1buf
,
2546 dispatch_width
, before_size
/ 16,
2547 loop_count
, perf
.latency
,
2548 spill_count
, fill_count
, send_count
,
2549 shader_stats
.scheduler_mode
,
2550 shader_stats
.promoted_constants
,
2551 before_size
, after_size
,
2552 100.0f
* (before_size
- after_size
) / before_size
);
2554 /* overriding the shader makes disasm_info invalid */
2555 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2556 dump_assembly(p
->store
, disasm_info
, perf
.block_latency
);
2558 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2561 ralloc_free(disasm_info
);
2564 compiler
->shader_debug_log(log_data
,
2565 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2566 "%d:%d spills:fills, %u sends, "
2567 "scheduled with mode %s, "
2568 "Promoted %u constants, "
2569 "compacted %d to %d bytes.",
2570 _mesa_shader_stage_to_abbrev(stage
),
2571 dispatch_width
, before_size
/ 16 - nop_count
,
2572 loop_count
, perf
.latency
,
2573 spill_count
, fill_count
, send_count
,
2574 shader_stats
.scheduler_mode
,
2575 shader_stats
.promoted_constants
,
2576 before_size
, after_size
);
2578 stats
->dispatch_width
= dispatch_width
;
2579 stats
->instructions
= before_size
/ 16 - nop_count
;
2580 stats
->sends
= send_count
;
2581 stats
->loops
= loop_count
;
2582 stats
->cycles
= perf
.latency
;
2583 stats
->spills
= spill_count
;
2584 stats
->fills
= fill_count
;
2587 return start_offset
;
2591 fs_generator::get_assembly()
2593 return brw_get_program(p
, &prog_data
->program_size
);