2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 const unsigned max_hw_width
= 16;
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
96 if (reg
->stride
> 4) {
97 assert(reg
!= &inst
->dst
);
98 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
99 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
100 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
102 const unsigned width
= MIN3(reg_width
, phys_width
, max_hw_width
);
103 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
104 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
107 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
127 * It applies to BayTrail too.
129 if (type_sz(reg
->type
) == 8) {
131 if (brw_reg
.vstride
> 0)
133 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
142 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
143 type_sz(inst
->dst
.type
) < 8) {
144 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
150 brw_reg
= retype(brw_reg
, reg
->type
);
151 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
152 brw_reg
.abs
= reg
->abs
;
153 brw_reg
.negate
= reg
->negate
;
158 assert(reg
->offset
== 0);
159 brw_reg
= reg
->as_brw_reg();
162 /* Probably unused. */
163 brw_reg
= brw_null_reg();
167 unreachable("not reached");
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
174 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
175 type_sz(reg
->type
) == 8 &&
176 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
177 brw_reg
.width
== BRW_WIDTH_1
&&
178 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
179 brw_reg
.width
= BRW_WIDTH_2
;
180 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
186 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
188 struct brw_stage_prog_data
*prog_data
,
189 struct shader_stats shader_stats
,
190 bool runtime_check_aads_emit
,
191 gl_shader_stage stage
)
193 : compiler(compiler
), log_data(log_data
),
194 devinfo(compiler
->devinfo
),
195 prog_data(prog_data
),
196 shader_stats(shader_stats
),
197 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
198 stage(stage
), mem_ctx(mem_ctx
)
200 p
= rzalloc(mem_ctx
, struct brw_codegen
);
201 brw_init_codegen(devinfo
, p
, mem_ctx
);
203 /* In the FS code generator, we are very careful to ensure that we always
204 * set the right execution size so we don't need the EU code to "help" us
205 * by trying to infer it. Sometimes, it infers the wrong thing.
207 p
->automatic_exec_sizes
= false;
210 fs_generator::~fs_generator()
214 class ip_record
: public exec_node
{
216 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
227 fs_generator::patch_discard_jumps_to_fb_writes()
229 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
232 int scale
= brw_jump_scale(p
->devinfo
);
234 /* There is a somewhat strange undocumented requirement of using
235 * HALT, according to the simulator. If some channel has HALTed to
236 * a particular UIP, then by the end of the program, every channel
237 * must have HALTed to that UIP. Furthermore, the tracking is a
238 * stack, so you can't do the final halt of a UIP after starting
239 * halting to a new UIP.
241 * Symptoms of not emitting this instruction on actual hardware
242 * included GPU hangs and sparkly rendering on the piglit discard
245 brw_inst
*last_halt
= gen6_HALT(p
);
246 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
247 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
251 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
252 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
254 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
255 /* HALT takes a half-instruction distance from the pre-incremented IP. */
256 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
259 this->discard_halt_patches
.make_empty();
264 fs_generator::generate_send(fs_inst
*inst
,
267 struct brw_reg ex_desc
,
268 struct brw_reg payload
,
269 struct brw_reg payload2
)
271 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
272 dst
.nr
== BRW_ARF_NULL
;
273 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
275 uint32_t desc_imm
= inst
->desc
|
276 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
278 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
280 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
281 /* If we have any sort of extended descriptor, then we need SENDS. This
282 * also covers the dual-payload case because ex_mlen goes in ex_desc.
284 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
285 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
288 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
,
289 devinfo
->gen
>= 12 ? BRW_OPCODE_SENDC
: BRW_OPCODE_SENDSC
);
291 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
294 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
299 fs_generator::fire_fb_write(fs_inst
*inst
,
300 struct brw_reg payload
,
301 struct brw_reg implied_header
,
304 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
306 if (devinfo
->gen
< 6) {
307 brw_push_insn_state(p
);
308 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
309 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
310 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
311 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
312 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
313 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
314 brw_pop_insn_state(p
);
317 uint32_t msg_control
= brw_fb_write_msg_control(inst
, prog_data
);
319 /* We assume render targets start at 0, because headerless FB write
320 * messages set "Render Target Index" to 0. Using a different binding
321 * table index would make it impossible to use headerless messages.
323 const uint32_t surf_index
= inst
->target
;
325 brw_inst
*insn
= brw_fb_WRITE(p
,
327 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
334 inst
->header_size
!= 0);
336 if (devinfo
->gen
>= 6)
337 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
341 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
343 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
344 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
345 brw_set_default_flag_reg(p
, 0, 0);
348 const struct brw_reg implied_header
=
349 devinfo
->gen
< 6 ? payload
: brw_null_reg();
351 if (inst
->base_mrf
>= 0)
352 payload
= brw_message_reg(inst
->base_mrf
);
354 if (!runtime_check_aads_emit
) {
355 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
357 /* This can only happen in gen < 6 */
358 assert(devinfo
->gen
< 6);
360 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
362 /* Check runtime bit to detect if we have to send AA data or not */
363 brw_push_insn_state(p
);
364 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
365 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
368 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
370 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
372 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
373 brw_pop_insn_state(p
);
375 /* Don't send AA data */
376 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
378 brw_land_fwd_jump(p
, jmp
);
379 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
384 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
385 struct brw_reg payload
)
387 assert(inst
->size_written
% REG_SIZE
== 0);
388 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
389 /* We assume that render targets start at binding table index 0. */
390 const unsigned surf_index
= inst
->target
;
392 gen9_fb_READ(p
, dst
, payload
, surf_index
,
393 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
394 prog_data
->persample_dispatch
);
398 fs_generator::generate_mov_indirect(fs_inst
*inst
,
401 struct brw_reg indirect_byte_offset
)
403 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
404 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
405 assert(!reg
.abs
&& !reg
.negate
);
406 assert(reg
.type
== dst
.type
);
408 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
410 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
411 imm_byte_offset
+= indirect_byte_offset
.ud
;
413 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
414 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
415 brw_MOV(p
, dst
, reg
);
417 /* Prior to Broadwell, there are only 8 address registers. */
418 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
420 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
421 struct brw_reg addr
= vec8(brw_address_reg(0));
423 /* The destination stride of an instruction (in bytes) must be greater
424 * than or equal to the size of the rest of the instruction. Since the
425 * address register is of type UW, we can't use a D-type instruction.
426 * In order to get around this, re retype to UW and use a stride.
428 indirect_byte_offset
=
429 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
431 /* There are a number of reasons why we don't use the base offset here.
432 * One reason is that the field is only 9 bits which means we can only
433 * use it to access the first 16 GRFs. Also, from the Haswell PRM
434 * section "Register Region Restrictions":
436 * "The lower bits of the AddressImmediate must not overflow to
437 * change the register address. The lower 5 bits of Address
438 * Immediate when added to lower 5 bits of address register gives
439 * the sub-register offset. The upper bits of Address Immediate
440 * when added to upper bits of address register gives the register
441 * address. Any overflow from sub-register offset is dropped."
443 * Since the indirect may cause us to cross a register boundary, this
444 * makes the base offset almost useless. We could try and do something
445 * clever where we use a actual base offset if base_offset % 32 == 0 but
446 * that would mean we were generating different code depending on the
447 * base offset. Instead, for the sake of consistency, we'll just do the
448 * add ourselves. This restriction is only listed in the Haswell PRM
449 * but empirical testing indicates that it applies on all older
450 * generations and is lifted on Broadwell.
452 * In the end, while base_offset is nice to look at in the generated
453 * code, using it saves us 0 instructions and would require quite a bit
454 * of case-by-case work. It's just not worth it.
456 * There's some sort of HW bug on Gen12 which causes issues if we write
457 * to the address register in control-flow. Since we only ever touch
458 * the address register from the generator, we can easily enough work
459 * around it by setting NoMask on the add.
461 brw_push_insn_state(p
);
462 if (devinfo
->gen
== 12)
463 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
464 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
465 brw_pop_insn_state(p
);
466 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
468 if (type_sz(reg
.type
) > 4 &&
469 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
470 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
471 !devinfo
->has_64bit_float
)) {
472 /* IVB has an issue (which we found empirically) where it reads two
473 * address register components per channel for indirectly addressed
476 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
478 * "When source or destination datatype is 64b or operation is
479 * integer DWord multiply, indirect addressing must not be used."
481 * To work around both of these, we do two integer MOVs insead of one
482 * 64-bit MOV. Because no double value should ever cross a register
483 * boundary, it's safe to use the immediate offset in the indirect
484 * here to handle adding 4 bytes to the offset and avoid the extra
485 * ADD to the register file.
487 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
488 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
489 brw_set_default_swsb(p
, tgl_swsb_null());
490 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
491 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
493 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
495 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
497 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
498 !inst
->get_next()->is_tail_sentinel() &&
499 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
500 /* From the Sandybridge PRM:
502 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
503 * instruction that “indexed/indirect” source AND is followed
504 * by a send, the instruction requires a “Switch”. This is to
505 * avoid race condition where send may dispatch before MRF is
508 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
515 fs_generator::generate_shuffle(fs_inst
*inst
,
520 /* Ivy bridge has some strange behavior that makes this a real pain to
521 * implement for 64-bit values so we just don't bother.
523 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
525 /* Because we're using the address register, we're limited to 8-wide
526 * execution on gen7. On gen8, we're limited to 16-wide by the address
527 * register file and 8-wide for 64-bit types. We could try and make this
528 * instruction splittable higher up in the compiler but that gets weird
529 * because it reads all of the channels regardless of execution size. It's
530 * easier just to split it here.
532 const unsigned lower_width
=
533 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
534 8 : MIN2(16, inst
->exec_size
);
536 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
537 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
538 brw_set_default_group(p
, group
);
540 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
541 idx
.file
== BRW_IMMEDIATE_VALUE
) {
542 /* Trivial, the source is already uniform or the index is a constant.
543 * We will typically not get here if the optimizer is doing its job,
544 * but asserting would be mean.
546 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
547 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
549 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
550 struct brw_reg addr
= vec8(brw_address_reg(0));
552 struct brw_reg group_idx
= suboffset(idx
, group
);
554 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
555 /* Things get grumpy if the register is too wide. */
560 assert(type_sz(group_idx
.type
) <= 4);
561 if (type_sz(group_idx
.type
) == 4) {
562 /* The destination stride of an instruction (in bytes) must be
563 * greater than or equal to the size of the rest of the
564 * instruction. Since the address register is of type UW, we
565 * can't use a D-type instruction. In order to get around this,
566 * re retype to UW and use a stride.
568 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
571 /* Take into account the component size and horizontal stride. */
572 assert(src
.vstride
== src
.hstride
+ src
.width
);
573 brw_SHL(p
, addr
, group_idx
,
574 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
577 /* Add on the register start offset */
578 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
579 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
581 if (type_sz(src
.type
) > 4 &&
582 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
583 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
584 /* IVB has an issue (which we found empirically) where it reads
585 * two address register components per channel for indirectly
586 * addressed 64-bit sources.
588 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
590 * "When source or destination datatype is 64b or operation is
591 * integer DWord multiply, indirect addressing must not be
594 * To work around both of these, we do two integer MOVs insead of
595 * one 64-bit MOV. Because no double value should ever cross a
596 * register boundary, it's safe to use the immediate offset in the
597 * indirect here to handle adding 4 bytes to the offset and avoid
598 * the extra ADD to the register file.
600 struct brw_reg gdst
= suboffset(dst
, group
);
601 struct brw_reg dst_d
= retype(spread(gdst
, 2),
602 BRW_REGISTER_TYPE_D
);
603 assert(dst
.hstride
== 1);
605 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
606 brw_set_default_swsb(p
, tgl_swsb_null());
607 brw_MOV(p
, byte_offset(dst_d
, 4),
608 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
610 brw_MOV(p
, suboffset(dst
, group
* dst
.hstride
),
611 retype(brw_VxH_indirect(0, 0), src
.type
));
615 brw_set_default_swsb(p
, tgl_swsb_null());
620 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
621 struct brw_reg dst
, struct brw_reg src
,
624 /* Requires a quad. */
625 assert(inst
->exec_size
>= 4);
627 if (src
.file
== BRW_IMMEDIATE_VALUE
||
628 has_scalar_region(src
)) {
629 /* The value is uniform across all channels */
630 brw_MOV(p
, dst
, src
);
632 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
633 /* This only works on 8-wide 32-bit values */
634 assert(inst
->exec_size
== 8);
635 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
636 assert(src
.vstride
== src
.width
+ 1);
637 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
638 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
639 swiz_src
.swizzle
= swiz
;
640 brw_MOV(p
, dst
, swiz_src
);
643 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
644 assert(src
.vstride
== src
.width
+ 1);
645 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
648 case BRW_SWIZZLE_XXXX
:
649 case BRW_SWIZZLE_YYYY
:
650 case BRW_SWIZZLE_ZZZZ
:
651 case BRW_SWIZZLE_WWWW
:
652 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
655 case BRW_SWIZZLE_XXZZ
:
656 case BRW_SWIZZLE_YYWW
:
657 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
660 case BRW_SWIZZLE_XYXY
:
661 case BRW_SWIZZLE_ZWZW
:
662 assert(inst
->exec_size
== 4);
663 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
667 assert(inst
->force_writemask_all
);
668 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
670 for (unsigned c
= 0; c
< 4; c
++) {
671 brw_inst
*insn
= brw_MOV(
672 p
, stride(suboffset(dst
, c
),
673 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
674 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
676 if (devinfo
->gen
< 12) {
677 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
678 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
681 brw_set_default_swsb(p
, tgl_swsb_null());
690 fs_generator::generate_urb_read(fs_inst
*inst
,
692 struct brw_reg header
)
694 assert(inst
->size_written
% REG_SIZE
== 0);
695 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
696 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
698 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
699 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
700 brw_set_src0(p
, send
, header
);
701 if (devinfo
->gen
< 12)
702 brw_set_src1(p
, send
, brw_imm_ud(0u));
704 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
705 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
707 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
708 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
710 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
711 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
712 brw_inst_set_header_present(p
->devinfo
, send
, true);
713 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
717 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
721 /* WaClearTDRRegBeforeEOTForNonPS.
723 * WA: Clear tdr register before send EOT in all non-PS shader kernels
725 * mov(8) tdr0:ud 0x0:ud {NoMask}"
727 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
728 brw_push_insn_state(p
);
729 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
730 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
731 brw_pop_insn_state(p
);
734 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
736 brw_set_dest(p
, insn
, brw_null_reg());
737 brw_set_src0(p
, insn
, payload
);
738 if (devinfo
->gen
< 12)
739 brw_set_src1(p
, insn
, brw_imm_ud(0u));
741 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
742 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
744 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
745 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
746 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
748 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
749 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
750 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
752 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
753 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
754 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
755 brw_inst_set_header_present(p
->devinfo
, insn
, true);
756 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
760 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
762 struct brw_inst
*insn
;
764 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
766 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
767 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
768 if (devinfo
->gen
< 12)
769 brw_set_src1(p
, insn
, brw_imm_ud(0u));
771 /* Terminate a compute shader by sending a message to the thread spawner.
773 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
774 brw_inst_set_mlen(devinfo
, insn
, 1);
775 brw_inst_set_rlen(devinfo
, insn
, 0);
776 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
777 brw_inst_set_header_present(devinfo
, insn
, false);
779 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
781 if (devinfo
->gen
< 11) {
782 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
784 /* Note that even though the thread has a URB resource associated with it,
785 * we set the "do not dereference URB" bit, because the URB resource is
786 * managed by the fixed-function unit, so it will free it automatically.
788 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
791 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
795 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
798 if (devinfo
->gen
>= 12) {
799 brw_set_default_swsb(p
, tgl_swsb_null());
800 brw_SYNC(p
, TGL_SYNC_BAR
);
807 fs_generator::generate_linterp(fs_inst
*inst
,
808 struct brw_reg dst
, struct brw_reg
*src
)
812 * -----------------------------------
813 * | src1+0 | src1+1 | src1+2 | src1+3 |
814 * |-----------------------------------|
815 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
816 * -----------------------------------
818 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
820 * -----------------------------------
821 * | src1+0 | src1+1 | src1+2 | src1+3 |
822 * |-----------------------------------|
823 * |(x0, x1)|(y0, y1)| | | in SIMD8
824 * |-----------------------------------|
825 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
826 * -----------------------------------
828 * See also: emit_interpolation_setup_gen4().
830 struct brw_reg delta_x
= src
[0];
831 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
832 struct brw_reg interp
= src
[1];
835 /* nir_lower_interpolation() will do the lowering to MAD instructions for
838 assert(devinfo
->gen
< 11);
840 if (devinfo
->has_pln
) {
841 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
842 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
844 * "[DevSNB]:<src1> must be even register aligned.
846 * This restriction is lifted on Ivy Bridge.
848 * This means that we need to split PLN into LINE+MAC on-the-fly.
849 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
850 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
851 * coordinate registers are laid out differently so we leave it as a
852 * SIMD16 instruction.
854 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
855 assert(inst
->group
% 16 == 0);
857 brw_push_insn_state(p
);
858 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
860 /* Thanks to two accumulators, we can emit all the LINEs and then all
861 * the MACs. This improves parallelism a bit.
863 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
864 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
865 offset(delta_x
, g
* 2));
866 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
868 /* LINE writes the accumulator automatically on gen4-5. On Sandy
869 * Bridge and later, we have to explicitly enable it.
871 if (devinfo
->gen
>= 6)
872 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
874 /* brw_set_default_saturate() is called before emitting
875 * instructions, so the saturate bit is set in each instruction,
876 * so we need to unset it on the LINE instructions.
878 brw_inst_set_saturate(p
->devinfo
, line
, false);
881 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
882 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
883 offset(delta_x
, g
* 2 + 1));
884 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
885 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
888 brw_pop_insn_state(p
);
892 brw_PLN(p
, dst
, interp
, delta_x
);
897 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
898 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
900 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
902 /* brw_set_default_saturate() is called before emitting instructions, so
903 * the saturate bit is set in each instruction, so we need to unset it on
904 * the first instruction.
906 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
913 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
916 struct brw_reg surf_index
)
918 assert(devinfo
->gen
>= 7);
919 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
924 switch (inst
->exec_size
) {
926 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
929 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
932 unreachable("Invalid width for texture instruction");
935 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
941 retype(dst
, BRW_REGISTER_TYPE_UW
),
946 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
947 rlen
, /* response length */
949 inst
->header_size
> 0,
951 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
955 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
956 struct brw_reg surface_index
,
957 struct brw_reg sampler_index
)
959 assert(devinfo
->gen
< 7);
960 assert(inst
->size_written
% REG_SIZE
== 0);
963 uint32_t return_format
;
965 /* Sampler EOT message of less than the dispatch width would kill the
966 * thread prematurely.
968 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
971 case BRW_REGISTER_TYPE_D
:
972 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
974 case BRW_REGISTER_TYPE_UD
:
975 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
978 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
982 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
983 * is set as part of the message descriptor. On gen4, the PRM seems to
984 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
985 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
986 * gone from the message descriptor entirely and you just get UINT32 all
987 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
988 * just stomp it to UINT32 all the time.
990 if (inst
->opcode
== SHADER_OPCODE_TXS
)
991 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
993 switch (inst
->exec_size
) {
995 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
998 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1001 unreachable("Invalid width for texture instruction");
1004 if (devinfo
->gen
>= 5) {
1005 switch (inst
->opcode
) {
1006 case SHADER_OPCODE_TEX
:
1007 if (inst
->shadow_compare
) {
1008 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1010 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1014 if (inst
->shadow_compare
) {
1015 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1017 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1020 case SHADER_OPCODE_TXL
:
1021 if (inst
->shadow_compare
) {
1022 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1024 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1027 case SHADER_OPCODE_TXS
:
1028 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1030 case SHADER_OPCODE_TXD
:
1031 assert(!inst
->shadow_compare
);
1032 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1034 case SHADER_OPCODE_TXF
:
1035 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1037 case SHADER_OPCODE_TXF_CMS
:
1038 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1040 case SHADER_OPCODE_LOD
:
1041 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1043 case SHADER_OPCODE_TG4
:
1044 assert(devinfo
->gen
== 6);
1045 assert(!inst
->shadow_compare
);
1046 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1048 case SHADER_OPCODE_SAMPLEINFO
:
1049 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1052 unreachable("not reached");
1055 switch (inst
->opcode
) {
1056 case SHADER_OPCODE_TEX
:
1057 /* Note that G45 and older determines shadow compare and dispatch width
1058 * from message length for most messages.
1060 if (inst
->exec_size
== 8) {
1061 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1062 if (inst
->shadow_compare
) {
1063 assert(inst
->mlen
== 6);
1065 assert(inst
->mlen
<= 4);
1068 if (inst
->shadow_compare
) {
1069 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1070 assert(inst
->mlen
== 9);
1072 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1073 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1078 if (inst
->shadow_compare
) {
1079 assert(inst
->exec_size
== 8);
1080 assert(inst
->mlen
== 6);
1081 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1083 assert(inst
->mlen
== 9);
1084 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1085 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1088 case SHADER_OPCODE_TXL
:
1089 if (inst
->shadow_compare
) {
1090 assert(inst
->exec_size
== 8);
1091 assert(inst
->mlen
== 6);
1092 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1094 assert(inst
->mlen
== 9);
1095 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1096 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1099 case SHADER_OPCODE_TXD
:
1100 /* There is no sample_d_c message; comparisons are done manually */
1101 assert(inst
->exec_size
== 8);
1102 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1103 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1105 case SHADER_OPCODE_TXF
:
1106 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1107 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1108 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1110 case SHADER_OPCODE_TXS
:
1111 assert(inst
->mlen
== 3);
1112 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1113 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1116 unreachable("not reached");
1119 assert(msg_type
!= -1);
1121 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1125 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1127 /* Load the message header if present. If there's a texture offset,
1128 * we need to set it up explicitly and load the offset bitfield.
1129 * Otherwise, we can use an implied move from g0 to the first message reg.
1131 struct brw_reg src
= brw_null_reg();
1132 if (inst
->header_size
!= 0) {
1133 if (devinfo
->gen
< 6 && !inst
->offset
) {
1134 /* Set up an implied move from g0 to the MRF. */
1135 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1137 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1138 assert(inst
->base_mrf
!= -1);
1139 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1141 brw_push_insn_state(p
);
1142 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1143 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1144 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1145 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1146 /* Explicitly set up the message header by copying g0 to the MRF. */
1147 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1148 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1150 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1152 /* Set the offset bits in DWord 2. */
1153 brw_MOV(p
, get_element_ud(header_reg
, 2),
1154 brw_imm_ud(inst
->offset
));
1157 brw_pop_insn_state(p
);
1158 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1162 uint32_t base_binding_table_index
;
1163 switch (inst
->opcode
) {
1164 case SHADER_OPCODE_TG4
:
1165 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1168 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1172 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1173 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1176 retype(dst
, BRW_REGISTER_TYPE_UW
),
1179 surface_index
.ud
+ base_binding_table_index
,
1180 sampler_index
.ud
% 16,
1182 inst
->size_written
/ REG_SIZE
,
1184 inst
->header_size
!= 0,
1190 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1193 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1195 * Ideally, we want to produce:
1198 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1199 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1200 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1201 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1202 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1203 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1204 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1205 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1207 * and add another set of two more subspans if in 16-pixel dispatch mode.
1209 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1210 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1211 * pair. But the ideal approximation may impose a huge performance cost on
1212 * sample_d. On at least Haswell, sample_d instruction does some
1213 * optimizations if the same LOD is used for all pixels in the subspan.
1215 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1216 * appropriate swizzling.
1219 fs_generator::generate_ddx(const fs_inst
*inst
,
1220 struct brw_reg dst
, struct brw_reg src
)
1222 unsigned vstride
, width
;
1224 if (devinfo
->gen
>= 8) {
1225 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1226 /* produce accurate derivatives */
1227 vstride
= BRW_VERTICAL_STRIDE_2
;
1228 width
= BRW_WIDTH_2
;
1230 /* replicate the derivative at the top-left pixel to other pixels */
1231 vstride
= BRW_VERTICAL_STRIDE_4
;
1232 width
= BRW_WIDTH_4
;
1235 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1236 struct brw_reg src1
= src
;
1238 src0
.vstride
= vstride
;
1240 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1241 src1
.vstride
= vstride
;
1243 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1245 brw_ADD(p
, dst
, src0
, negate(src1
));
1247 /* On Haswell and earlier, the region used above appears to not work
1248 * correctly for compressed instructions. At least on Haswell and
1249 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1250 * would have to split to SIMD8 no matter which method we choose, we
1251 * may as well use ALIGN16 on all platforms gen7 and earlier.
1253 struct brw_reg src0
= stride(src
, 4, 4, 1);
1254 struct brw_reg src1
= stride(src
, 4, 4, 1);
1255 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1256 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1257 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1259 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1260 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1263 brw_push_insn_state(p
);
1264 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1265 brw_ADD(p
, dst
, negate(src0
), src1
);
1266 brw_pop_insn_state(p
);
1270 /* The negate_value boolean is used to negate the derivative computation for
1271 * FBOs, since they place the origin at the upper left instead of the lower
1275 fs_generator::generate_ddy(const fs_inst
*inst
,
1276 struct brw_reg dst
, struct brw_reg src
)
1278 const uint32_t type_size
= type_sz(src
.type
);
1280 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1281 /* produce accurate derivatives.
1283 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1284 * "Register Region Restrictions", Section "1. Special Restrictions":
1286 * "In Align16 mode, the channel selects and channel enables apply to
1287 * a pair of half-floats, because these parameters are defined for
1288 * DWord elements ONLY. This is applicable when both source and
1289 * destination are half-floats."
1291 * So for half-float operations we use the Gen11+ Align1 path. CHV
1292 * inherits its FP16 hardware from SKL, so it is not affected.
1294 if (devinfo
->gen
>= 11 ||
1295 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1296 src
= stride(src
, 0, 2, 1);
1298 brw_push_insn_state(p
);
1299 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1300 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1301 brw_set_default_group(p
, inst
->group
+ g
);
1302 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1303 negate(byte_offset(src
, g
* type_size
)),
1304 byte_offset(src
, (g
+ 2) * type_size
));
1305 brw_set_default_swsb(p
, tgl_swsb_null());
1307 brw_pop_insn_state(p
);
1309 struct brw_reg src0
= stride(src
, 4, 4, 1);
1310 struct brw_reg src1
= stride(src
, 4, 4, 1);
1311 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1312 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1314 brw_push_insn_state(p
);
1315 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1316 brw_ADD(p
, dst
, negate(src0
), src1
);
1317 brw_pop_insn_state(p
);
1320 /* replicate the derivative at the top-left pixel to other pixels */
1321 if (devinfo
->gen
>= 8) {
1322 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1323 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1325 brw_ADD(p
, dst
, negate(src0
), src1
);
1327 /* On Haswell and earlier, the region used above appears to not work
1328 * correctly for compressed instructions. At least on Haswell and
1329 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1330 * would have to split to SIMD8 no matter which method we choose, we
1331 * may as well use ALIGN16 on all platforms gen7 and earlier.
1333 struct brw_reg src0
= stride(src
, 4, 4, 1);
1334 struct brw_reg src1
= stride(src
, 4, 4, 1);
1335 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1336 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1338 brw_push_insn_state(p
);
1339 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1340 brw_ADD(p
, dst
, negate(src0
), src1
);
1341 brw_pop_insn_state(p
);
1347 fs_generator::generate_discard_jump(fs_inst
*)
1349 assert(devinfo
->gen
>= 6);
1351 /* This HALT will be patched up at FB write time to point UIP at the end of
1352 * the program, and at brw_uip_jip() JIP will be set to the end of the
1353 * current block (or the program).
1355 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1360 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1362 /* The 32-wide messages only respect the first 16-wide half of the channel
1363 * enable signals which are replicated identically for the second group of
1364 * 16 channels, so we cannot use them unless the write is marked
1365 * force_writemask_all.
1367 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1368 MIN2(16, inst
->exec_size
);
1369 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1370 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1371 assert(inst
->mlen
!= 0);
1373 brw_push_insn_state(p
);
1374 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1375 brw_set_default_compression(p
, lower_size
> 8);
1377 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1378 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1381 brw_set_default_swsb(p
, tgl_swsb_null());
1382 brw_SYNC(p
, TGL_SYNC_ALLRD
);
1384 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1387 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1388 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1390 if (i
+ 1 < inst
->exec_size
/ lower_size
)
1391 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1393 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1395 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1397 inst
->offset
+ block_size
* REG_SIZE
* i
);
1400 brw_pop_insn_state(p
);
1404 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1406 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1407 assert(inst
->mlen
!= 0);
1409 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1410 inst
->exec_size
/ 8, inst
->offset
);
1414 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1416 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1418 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1422 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1424 struct brw_reg index
,
1425 struct brw_reg offset
)
1427 assert(type_sz(dst
.type
) == 4);
1428 assert(inst
->mlen
!= 0);
1430 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1431 index
.type
== BRW_REGISTER_TYPE_UD
);
1432 uint32_t surf_index
= index
.ud
;
1434 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1435 offset
.type
== BRW_REGISTER_TYPE_UD
);
1436 uint32_t read_offset
= offset
.ud
;
1438 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1439 read_offset
, surf_index
);
1443 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1445 struct brw_reg index
,
1446 struct brw_reg payload
)
1448 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1449 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1450 assert(type_sz(dst
.type
) == 4);
1452 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1453 const uint32_t surf_index
= index
.ud
;
1455 brw_push_insn_state(p
);
1456 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1457 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1458 brw_pop_insn_state(p
);
1460 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1461 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1462 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1463 brw_set_desc(p
, send
,
1464 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1466 brw_dp_read_desc(devinfo
, surf_index
,
1467 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1468 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1469 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1472 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1473 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1475 brw_push_insn_state(p
);
1476 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1478 /* a0.0 = surf_index & 0xff */
1479 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1480 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1481 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1482 brw_set_dest(p
, insn_and
, addr
);
1483 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1484 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1486 /* dst = send(payload, a0.0 | <descriptor>) */
1487 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1488 brw_send_indirect_message(
1489 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1490 retype(dst
, BRW_REGISTER_TYPE_UD
),
1491 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1492 brw_message_desc(devinfo
, 1,
1493 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1494 brw_dp_read_desc(devinfo
, 0 /* surface */,
1495 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1496 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1497 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1500 brw_pop_insn_state(p
);
1505 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1507 struct brw_reg index
)
1509 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1510 assert(inst
->header_size
!= 0);
1513 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1514 index
.type
== BRW_REGISTER_TYPE_UD
);
1515 uint32_t surf_index
= index
.ud
;
1517 uint32_t simd_mode
, rlen
, msg_type
;
1518 if (inst
->exec_size
== 16) {
1519 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1522 assert(inst
->exec_size
== 8);
1523 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1527 if (devinfo
->gen
>= 5)
1528 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1530 /* We always use the SIMD16 message so that we only have to load U, and
1533 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1534 assert(inst
->mlen
== 3);
1535 assert(inst
->size_written
== 8 * REG_SIZE
);
1537 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1540 struct brw_reg header
= brw_vec8_grf(0, 0);
1541 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1543 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1544 brw_inst_set_compression(devinfo
, send
, false);
1545 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1546 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1547 brw_set_src0(p
, send
, header
);
1548 if (devinfo
->gen
< 6)
1549 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1551 /* Our surface is set up as floats, regardless of what actual data is
1554 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1555 brw_set_desc(p
, send
,
1556 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1557 brw_sampler_desc(devinfo
, surf_index
,
1558 0, /* sampler (unused) */
1559 msg_type
, simd_mode
, return_format
));
1563 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1566 struct brw_reg msg_data
,
1569 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1570 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1571 assert(inst
->size_written
% REG_SIZE
== 0);
1573 brw_pixel_interpolator_query(p
,
1574 retype(dst
, BRW_REGISTER_TYPE_UW
),
1575 /* If we don't have a payload, what we send doesn't matter */
1576 has_payload
? src
: brw_vec8_grf(0, 0),
1577 inst
->pi_noperspective
,
1580 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1581 inst
->size_written
/ REG_SIZE
);
1584 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1585 * the ADD instruction.
1588 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1590 struct brw_reg src0
,
1591 struct brw_reg src1
)
1593 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1594 dst
.type
== BRW_REGISTER_TYPE_UD
);
1595 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1596 src0
.type
== BRW_REGISTER_TYPE_UD
);
1598 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1599 const unsigned lower_size
= MIN2(inst
->exec_size
,
1600 devinfo
->gen
>= 8 ? 16 : 8);
1602 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1603 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1604 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1605 (i
* lower_size
/ (1 << src0
.width
))) *
1606 type_sz(src0
.type
) / REG_SIZE
),
1607 suboffset(reg
, i
* lower_size
/ 4));
1608 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1609 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1610 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1611 brw_set_default_swsb(p
, tgl_swsb_null());
1616 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1621 assert(devinfo
->gen
>= 7);
1622 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1623 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1624 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1626 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1628 * Because this instruction does not have a 16-bit floating-point type,
1629 * the destination data type must be Word (W).
1631 * The destination must be DWord-aligned and specify a horizontal stride
1632 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1633 * each destination channel and the upper word is not modified.
1635 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1637 /* Give each 32-bit channel of dst the form below, where "." means
1641 brw_F32TO16(p
, dst_w
, y
);
1646 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1647 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1649 /* And, finally the form of packHalf2x16's output:
1652 brw_F32TO16(p
, dst_w
, x
);
1656 fs_generator::generate_shader_time_add(fs_inst
*,
1657 struct brw_reg payload
,
1658 struct brw_reg offset
,
1659 struct brw_reg value
)
1661 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1663 assert(devinfo
->gen
>= 7);
1664 brw_push_insn_state(p
);
1665 brw_set_default_mask_control(p
, true);
1666 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1668 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1669 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1671 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1674 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1675 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1676 value
.width
= BRW_WIDTH_1
;
1677 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1678 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1680 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1683 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1684 * case, and we don't really care about squeezing every bit of performance
1685 * out of this path, so we just emit the MOVs from here.
1687 brw_MOV(p
, payload_offset
, offset
);
1688 brw_set_default_swsb(p
, tgl_swsb_null());
1689 brw_MOV(p
, payload_value
, value
);
1690 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1691 brw_shader_time_add(p
, payload
,
1692 prog_data
->binding_table
.shader_time_start
);
1693 brw_pop_insn_state(p
);
1697 fs_generator::enable_debug(const char *shader_name
)
1700 this->shader_name
= shader_name
;
1704 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1705 struct brw_compile_stats
*stats
)
1707 /* align to 64 byte boundary. */
1708 while (p
->next_insn_offset
% 64)
1711 this->dispatch_width
= dispatch_width
;
1713 int start_offset
= p
->next_insn_offset
;
1715 /* `send_count` explicitly does not include spills or fills, as we'd
1716 * like to use it as a metric for intentional memory access or other
1717 * shared function use. Otherwise, subtle changes to scheduling or
1718 * register allocation could cause it to fluctuate wildly - and that
1719 * effect is already counted in spill/fill counts.
1721 int spill_count
= 0, fill_count
= 0;
1722 int loop_count
= 0, send_count
= 0;
1723 bool is_accum_used
= false;
1725 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1727 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1728 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1731 struct brw_reg src
[4], dst
;
1732 unsigned int last_insn_offset
= p
->next_insn_offset
;
1733 bool multiple_instructions_emitted
= false;
1735 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1736 * "Register Region Restrictions" section: for BDW, SKL:
1738 * "A POW/FDIV operation must not be followed by an instruction
1739 * that requires two destination registers."
1741 * The documentation is often lacking annotations for Atom parts,
1742 * and empirically this affects CHV as well.
1744 if (devinfo
->gen
>= 8 &&
1745 devinfo
->gen
<= 9 &&
1747 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1748 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1749 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1751 last_insn_offset
= p
->next_insn_offset
;
1754 /* GEN:BUG:14010017096:
1756 * Clear accumulator register before end of thread.
1758 if (inst
->eot
&& is_accum_used
&& devinfo
->gen
>= 12) {
1759 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
1760 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1761 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1762 brw_MOV(p
, brw_acc_reg(8), brw_imm_f(0.0f
));
1763 last_insn_offset
= p
->next_insn_offset
;
1766 if (!is_accum_used
&& !inst
->eot
) {
1767 is_accum_used
= inst
->writes_accumulator_implicitly(devinfo
) ||
1768 inst
->dst
.is_accumulator();
1771 if (unlikely(debug_flag
))
1772 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1774 /* If the instruction writes to more than one register, it needs to be
1775 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1776 * hardware figures out by itself what the right compression mode is,
1777 * but we still need to know whether the instruction is compressed to
1778 * set up the source register regions appropriately.
1780 * XXX - This is wrong for instructions that write a single register but
1781 * read more than one which should strictly speaking be treated as
1782 * compressed. For instructions that don't write any registers it
1783 * relies on the destination being a null register of the correct
1784 * type and regioning so the instruction is considered compressed
1785 * or not accordingly.
1787 const bool compressed
=
1788 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1789 brw_set_default_compression(p
, compressed
);
1790 brw_set_default_group(p
, inst
->group
);
1792 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1793 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1794 &inst
->src
[i
], compressed
);
1795 /* The accumulator result appears to get used for the
1796 * conditional modifier generation. When negating a UD
1797 * value, there is a 33rd bit generated for the sign in the
1798 * accumulator value, so now you can't check, for example,
1799 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1801 assert(!inst
->conditional_mod
||
1802 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1803 !inst
->src
[i
].negate
);
1805 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1806 &inst
->dst
, compressed
);
1808 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1809 brw_set_default_predicate_control(p
, inst
->predicate
);
1810 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1811 /* On gen7 and above, hardware automatically adds the group onto the
1812 * flag subregister number. On Sandy Bridge and older, we have to do it
1815 const unsigned flag_subreg
= inst
->flag_subreg
+
1816 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1817 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1818 brw_set_default_saturate(p
, inst
->saturate
);
1819 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1820 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1821 brw_set_default_swsb(p
, inst
->sched
);
1823 unsigned exec_size
= inst
->exec_size
;
1824 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1825 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1829 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1831 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1832 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1833 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1834 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1836 switch (inst
->opcode
) {
1837 case BRW_OPCODE_SYNC
:
1838 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
1839 brw_SYNC(p
, tgl_sync_function(src
[0].ud
));
1841 case BRW_OPCODE_MOV
:
1842 brw_MOV(p
, dst
, src
[0]);
1844 case BRW_OPCODE_ADD
:
1845 brw_ADD(p
, dst
, src
[0], src
[1]);
1847 case BRW_OPCODE_MUL
:
1848 brw_MUL(p
, dst
, src
[0], src
[1]);
1850 case BRW_OPCODE_AVG
:
1851 brw_AVG(p
, dst
, src
[0], src
[1]);
1853 case BRW_OPCODE_MACH
:
1854 brw_MACH(p
, dst
, src
[0], src
[1]);
1857 case BRW_OPCODE_LINE
:
1858 brw_LINE(p
, dst
, src
[0], src
[1]);
1861 case BRW_OPCODE_MAD
:
1862 assert(devinfo
->gen
>= 6);
1863 if (devinfo
->gen
< 10)
1864 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1865 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1868 case BRW_OPCODE_LRP
:
1869 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1870 if (devinfo
->gen
< 10)
1871 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1872 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1875 case BRW_OPCODE_FRC
:
1876 brw_FRC(p
, dst
, src
[0]);
1878 case BRW_OPCODE_RNDD
:
1879 brw_RNDD(p
, dst
, src
[0]);
1881 case BRW_OPCODE_RNDE
:
1882 brw_RNDE(p
, dst
, src
[0]);
1884 case BRW_OPCODE_RNDZ
:
1885 brw_RNDZ(p
, dst
, src
[0]);
1888 case BRW_OPCODE_AND
:
1889 brw_AND(p
, dst
, src
[0], src
[1]);
1892 brw_OR(p
, dst
, src
[0], src
[1]);
1894 case BRW_OPCODE_XOR
:
1895 brw_XOR(p
, dst
, src
[0], src
[1]);
1897 case BRW_OPCODE_NOT
:
1898 brw_NOT(p
, dst
, src
[0]);
1900 case BRW_OPCODE_ASR
:
1901 brw_ASR(p
, dst
, src
[0], src
[1]);
1903 case BRW_OPCODE_SHR
:
1904 brw_SHR(p
, dst
, src
[0], src
[1]);
1906 case BRW_OPCODE_SHL
:
1907 brw_SHL(p
, dst
, src
[0], src
[1]);
1909 case BRW_OPCODE_ROL
:
1910 assert(devinfo
->gen
>= 11);
1911 assert(src
[0].type
== dst
.type
);
1912 brw_ROL(p
, dst
, src
[0], src
[1]);
1914 case BRW_OPCODE_ROR
:
1915 assert(devinfo
->gen
>= 11);
1916 assert(src
[0].type
== dst
.type
);
1917 brw_ROR(p
, dst
, src
[0], src
[1]);
1919 case BRW_OPCODE_F32TO16
:
1920 assert(devinfo
->gen
>= 7);
1921 brw_F32TO16(p
, dst
, src
[0]);
1923 case BRW_OPCODE_F16TO32
:
1924 assert(devinfo
->gen
>= 7);
1925 brw_F16TO32(p
, dst
, src
[0]);
1927 case BRW_OPCODE_CMP
:
1928 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1929 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1930 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1931 * implemented in the compiler is not sufficient. Overriding the
1932 * type when the destination is the null register is necessary but
1933 * not sufficient by itself.
1935 assert(dst
.nr
== BRW_ARF_NULL
);
1936 dst
.type
= BRW_REGISTER_TYPE_D
;
1938 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1940 case BRW_OPCODE_SEL
:
1941 brw_SEL(p
, dst
, src
[0], src
[1]);
1943 case BRW_OPCODE_CSEL
:
1944 assert(devinfo
->gen
>= 8);
1945 if (devinfo
->gen
< 10)
1946 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1947 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1949 case BRW_OPCODE_BFREV
:
1950 assert(devinfo
->gen
>= 7);
1951 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1952 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1954 case BRW_OPCODE_FBH
:
1955 assert(devinfo
->gen
>= 7);
1956 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1958 case BRW_OPCODE_FBL
:
1959 assert(devinfo
->gen
>= 7);
1960 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1961 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1963 case BRW_OPCODE_LZD
:
1964 brw_LZD(p
, dst
, src
[0]);
1966 case BRW_OPCODE_CBIT
:
1967 assert(devinfo
->gen
>= 7);
1968 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1969 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1971 case BRW_OPCODE_ADDC
:
1972 assert(devinfo
->gen
>= 7);
1973 brw_ADDC(p
, dst
, src
[0], src
[1]);
1975 case BRW_OPCODE_SUBB
:
1976 assert(devinfo
->gen
>= 7);
1977 brw_SUBB(p
, dst
, src
[0], src
[1]);
1979 case BRW_OPCODE_MAC
:
1980 brw_MAC(p
, dst
, src
[0], src
[1]);
1983 case BRW_OPCODE_BFE
:
1984 assert(devinfo
->gen
>= 7);
1985 if (devinfo
->gen
< 10)
1986 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1987 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1990 case BRW_OPCODE_BFI1
:
1991 assert(devinfo
->gen
>= 7);
1992 brw_BFI1(p
, dst
, src
[0], src
[1]);
1994 case BRW_OPCODE_BFI2
:
1995 assert(devinfo
->gen
>= 7);
1996 if (devinfo
->gen
< 10)
1997 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1998 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2002 if (inst
->src
[0].file
!= BAD_FILE
) {
2003 /* The instruction has an embedded compare (only allowed on gen6) */
2004 assert(devinfo
->gen
== 6);
2005 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2007 brw_IF(p
, brw_get_default_exec_size(p
));
2011 case BRW_OPCODE_ELSE
:
2014 case BRW_OPCODE_ENDIF
:
2019 brw_DO(p
, brw_get_default_exec_size(p
));
2022 case BRW_OPCODE_BREAK
:
2025 case BRW_OPCODE_CONTINUE
:
2029 case BRW_OPCODE_WHILE
:
2034 case SHADER_OPCODE_RCP
:
2035 case SHADER_OPCODE_RSQ
:
2036 case SHADER_OPCODE_SQRT
:
2037 case SHADER_OPCODE_EXP2
:
2038 case SHADER_OPCODE_LOG2
:
2039 case SHADER_OPCODE_SIN
:
2040 case SHADER_OPCODE_COS
:
2041 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2042 if (devinfo
->gen
>= 6) {
2043 assert(inst
->mlen
== 0);
2044 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2045 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2046 src
[0], brw_null_reg());
2048 assert(inst
->mlen
>= 1);
2049 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2051 brw_math_function(inst
->opcode
),
2052 inst
->base_mrf
, src
[0],
2053 BRW_MATH_PRECISION_FULL
);
2057 case SHADER_OPCODE_INT_QUOTIENT
:
2058 case SHADER_OPCODE_INT_REMAINDER
:
2059 case SHADER_OPCODE_POW
:
2060 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2061 if (devinfo
->gen
>= 6) {
2062 assert(inst
->mlen
== 0);
2063 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2064 inst
->exec_size
== 8);
2065 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2067 assert(inst
->mlen
>= 1);
2068 assert(inst
->exec_size
== 8);
2069 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2070 inst
->base_mrf
, src
[0],
2071 BRW_MATH_PRECISION_FULL
);
2075 case FS_OPCODE_LINTERP
:
2076 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2078 case FS_OPCODE_PIXEL_X
:
2079 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2080 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2081 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2083 case FS_OPCODE_PIXEL_Y
:
2084 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2085 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2086 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2089 case SHADER_OPCODE_SEND
:
2090 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2091 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2092 if ((inst
->desc
& 0xff) == BRW_BTI_STATELESS
||
2093 (inst
->desc
& 0xff) == GEN8_BTI_STATELESS_NON_COHERENT
) {
2094 if (inst
->size_written
)
2103 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2104 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2107 case SHADER_OPCODE_TEX
:
2109 case SHADER_OPCODE_TXD
:
2110 case SHADER_OPCODE_TXF
:
2111 case SHADER_OPCODE_TXF_CMS
:
2112 case SHADER_OPCODE_TXL
:
2113 case SHADER_OPCODE_TXS
:
2114 case SHADER_OPCODE_LOD
:
2115 case SHADER_OPCODE_TG4
:
2116 case SHADER_OPCODE_SAMPLEINFO
:
2117 assert(inst
->src
[0].file
== BAD_FILE
);
2118 generate_tex(inst
, dst
, src
[1], src
[2]);
2122 case FS_OPCODE_DDX_COARSE
:
2123 case FS_OPCODE_DDX_FINE
:
2124 generate_ddx(inst
, dst
, src
[0]);
2126 case FS_OPCODE_DDY_COARSE
:
2127 case FS_OPCODE_DDY_FINE
:
2128 generate_ddy(inst
, dst
, src
[0]);
2131 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2132 generate_scratch_write(inst
, src
[0]);
2136 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2137 generate_scratch_read(inst
, dst
);
2141 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2142 generate_scratch_read_gen7(inst
, dst
);
2146 case SHADER_OPCODE_MOV_INDIRECT
:
2147 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2150 case SHADER_OPCODE_URB_READ_SIMD8
:
2151 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2152 generate_urb_read(inst
, dst
, src
[0]);
2156 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2157 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2158 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2159 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2160 generate_urb_write(inst
, src
[0]);
2164 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2165 assert(inst
->force_writemask_all
);
2166 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2170 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2171 assert(inst
->force_writemask_all
);
2172 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2176 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2177 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2181 case FS_OPCODE_REP_FB_WRITE
:
2182 case FS_OPCODE_FB_WRITE
:
2183 generate_fb_write(inst
, src
[0]);
2187 case FS_OPCODE_FB_READ
:
2188 generate_fb_read(inst
, dst
, src
[0]);
2192 case FS_OPCODE_DISCARD_JUMP
:
2193 generate_discard_jump(inst
);
2196 case SHADER_OPCODE_SHADER_TIME_ADD
:
2197 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2200 case SHADER_OPCODE_MEMORY_FENCE
:
2201 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2202 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2203 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2207 case FS_OPCODE_SCHEDULING_FENCE
:
2208 if (unlikely(debug_flag
))
2209 disasm_info
->use_tail
= true;
2212 case SHADER_OPCODE_INTERLOCK
:
2213 assert(devinfo
->gen
>= 9);
2214 /* The interlock is basically a memory fence issued via sendc */
2215 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2218 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2219 const struct brw_reg mask
=
2220 brw_stage_has_packed_dispatch(devinfo
, stage
,
2221 prog_data
) ? brw_imm_ud(~0u) :
2222 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2224 brw_find_live_channel(p
, dst
, mask
);
2227 case FS_OPCODE_LOAD_LIVE_CHANNELS
: {
2228 assert(devinfo
->gen
>= 8);
2229 assert(inst
->force_writemask_all
&& inst
->group
== 0);
2230 assert(inst
->dst
.file
== BAD_FILE
);
2231 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
2232 brw_MOV(p
, retype(brw_flag_subreg(inst
->flag_subreg
),
2233 BRW_REGISTER_TYPE_UD
),
2234 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD
));
2237 case SHADER_OPCODE_BROADCAST
:
2238 assert(inst
->force_writemask_all
);
2239 brw_broadcast(p
, dst
, src
[0], src
[1]);
2242 case SHADER_OPCODE_SHUFFLE
:
2243 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2246 case SHADER_OPCODE_SEL_EXEC
:
2247 assert(inst
->force_writemask_all
);
2248 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2249 brw_MOV(p
, dst
, src
[1]);
2250 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2251 brw_set_default_swsb(p
, tgl_swsb_null());
2252 brw_MOV(p
, dst
, src
[0]);
2255 case SHADER_OPCODE_QUAD_SWIZZLE
:
2256 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2257 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2258 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2261 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2262 assert(!src
[0].negate
&& !src
[0].abs
);
2263 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2264 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2265 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2266 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2267 const unsigned component
= src
[1].ud
;
2268 const unsigned cluster_size
= src
[2].ud
;
2269 unsigned vstride
= cluster_size
;
2270 unsigned width
= cluster_size
;
2272 /* The maximum exec_size is 32, but the maximum width is only 16. */
2273 if (inst
->exec_size
== width
) {
2278 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2280 if (type_sz(src
[0].type
) > 4 &&
2281 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2282 /* IVB has an issue (which we found empirically) where it reads
2283 * two address register components per channel for indirectly
2284 * addressed 64-bit sources.
2286 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2288 * "When source or destination datatype is 64b or operation is
2289 * integer DWord multiply, indirect addressing must not be
2292 * To work around both of these, we do two integer MOVs insead of
2293 * one 64-bit MOV. Because no double value should ever cross a
2294 * register boundary, it's safe to use the immediate offset in the
2295 * indirect here to handle adding 4 bytes to the offset and avoid
2296 * the extra ADD to the register file.
2298 assert(src
[0].type
== dst
.type
);
2299 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2300 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2301 brw_set_default_swsb(p
, tgl_swsb_null());
2302 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2303 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2305 brw_MOV(p
, dst
, strided
);
2310 case FS_OPCODE_SET_SAMPLE_ID
:
2311 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2314 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2315 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2318 case FS_OPCODE_PLACEHOLDER_HALT
:
2319 /* This is the place where the final HALT needs to be inserted if
2320 * we've emitted any discards. If not, this will emit no code.
2322 if (!patch_discard_jumps_to_fb_writes()) {
2323 if (unlikely(debug_flag
)) {
2324 disasm_info
->use_tail
= true;
2329 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2330 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2331 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2335 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2336 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2337 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2341 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2342 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2343 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2347 case CS_OPCODE_CS_TERMINATE
:
2348 generate_cs_terminate(inst
, src
[0]);
2352 case SHADER_OPCODE_BARRIER
:
2353 generate_barrier(inst
, src
[0]);
2357 case BRW_OPCODE_DIM
:
2358 assert(devinfo
->is_haswell
);
2359 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2360 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2361 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2364 case SHADER_OPCODE_RND_MODE
: {
2365 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2367 * Changes the floating point rounding mode updating the control
2368 * register field defined at cr0.0[5-6] bits.
2370 enum brw_rnd_mode mode
=
2371 (enum brw_rnd_mode
) (src
[0].d
<< BRW_CR0_RND_MODE_SHIFT
);
2372 brw_float_controls_mode(p
, mode
, BRW_CR0_RND_MODE_MASK
);
2376 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
2377 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2378 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2379 brw_float_controls_mode(p
, src
[0].d
, src
[1].d
);
2383 unreachable("Unsupported opcode");
2385 case SHADER_OPCODE_LOAD_PAYLOAD
:
2386 unreachable("Should be lowered by lower_load_payload()");
2389 if (multiple_instructions_emitted
)
2392 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2393 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2394 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2395 "emitting more than 1 instruction");
2397 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2399 if (inst
->conditional_mod
)
2400 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2401 if (devinfo
->gen
< 12) {
2402 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2403 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2408 brw_set_uip_jip(p
, start_offset
);
2410 /* end of program sentinel */
2411 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2416 if (unlikely(debug_flag
))
2418 brw_validate_instructions(devinfo
, p
->store
,
2420 p
->next_insn_offset
,
2423 int before_size
= p
->next_insn_offset
- start_offset
;
2424 brw_compact_instructions(p
, start_offset
, disasm_info
);
2425 int after_size
= p
->next_insn_offset
- start_offset
;
2427 if (unlikely(debug_flag
)) {
2428 unsigned char sha1
[21];
2431 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2433 _mesa_sha1_format(sha1buf
, sha1
);
2435 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2436 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2437 "%d:%d spills:fills, %u sends, "
2438 "scheduled with mode %s. "
2439 "Promoted %u constants. "
2440 "Compacted %d to %d bytes (%.0f%%)\n",
2441 shader_name
, sha1buf
,
2442 dispatch_width
, before_size
/ 16,
2443 loop_count
, cfg
->cycle_count
,
2444 spill_count
, fill_count
, send_count
,
2445 shader_stats
.scheduler_mode
,
2446 shader_stats
.promoted_constants
,
2447 before_size
, after_size
,
2448 100.0f
* (before_size
- after_size
) / before_size
);
2450 /* overriding the shader makes disasm_info invalid */
2451 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2452 dump_assembly(p
->store
, disasm_info
);
2454 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2457 ralloc_free(disasm_info
);
2460 compiler
->shader_debug_log(log_data
,
2461 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2462 "%d:%d spills:fills, %u sends, "
2463 "scheduled with mode %s, "
2464 "Promoted %u constants, "
2465 "compacted %d to %d bytes.",
2466 _mesa_shader_stage_to_abbrev(stage
),
2467 dispatch_width
, before_size
/ 16,
2468 loop_count
, cfg
->cycle_count
,
2469 spill_count
, fill_count
, send_count
,
2470 shader_stats
.scheduler_mode
,
2471 shader_stats
.promoted_constants
,
2472 before_size
, after_size
);
2474 stats
->dispatch_width
= dispatch_width
;
2475 stats
->instructions
= before_size
/ 16;
2476 stats
->loops
= loop_count
;
2477 stats
->cycles
= cfg
->cycle_count
;
2478 stats
->spills
= spill_count
;
2479 stats
->fills
= fill_count
;
2482 return start_offset
;
2486 fs_generator::get_assembly()
2488 return brw_get_program(p
, &prog_data
->program_size
);