2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 /* XXX - The equation above is strictly speaking not correct on
89 * hardware that supports unbalanced GRF writes -- On Gen9+
90 * each decompressed chunk of the instruction may have a
91 * different execution size when the number of components
92 * written to each destination GRF is not the same.
94 if (reg
->stride
> 4) {
95 assert(reg
!= &inst
->dst
);
96 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
97 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
98 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
100 const unsigned width
= MIN2(reg_width
, phys_width
);
101 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
102 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
105 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
106 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
107 * "Each DF (Double Float) operand uses an element size of 4 rather
108 * than 8 and all regioning parameters are twice what the values
109 * would be based on the true element size: ExecSize, Width,
110 * HorzStride, and VertStride. Each DF operand uses a pair of
111 * channels and all masking and swizzing should be adjusted
114 * From the IvyBridge PRM (Special Requirements for Handling Double
115 * Precision Data Types, page 71):
116 * "In Align1 mode, all regioning parameters like stride, execution
117 * size, and width must use the syntax of a pair of packed
118 * floats. The offsets for these data types must be 64-bit
119 * aligned. The execution size and regioning parameters are in terms
122 * Summarized: when handling DF-typed arguments, ExecSize,
123 * VertStride, and Width must be doubled.
125 * It applies to BayTrail too.
127 if (type_sz(reg
->type
) == 8) {
129 if (brw_reg
.vstride
> 0)
131 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
134 /* When converting from DF->F, we set the destination stride to 2
135 * because each d2f conversion implicitly writes 2 floats, being
136 * the first one the converted value. IVB/BYT actually writes two
137 * F components per SIMD channel, and every other component is
138 * filled with garbage.
140 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
141 type_sz(inst
->dst
.type
) < 8) {
142 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
148 brw_reg
= retype(brw_reg
, reg
->type
);
149 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
150 brw_reg
.abs
= reg
->abs
;
151 brw_reg
.negate
= reg
->negate
;
156 assert(reg
->offset
== 0);
157 brw_reg
= reg
->as_brw_reg();
160 /* Probably unused. */
161 brw_reg
= brw_null_reg();
165 unreachable("not reached");
168 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
169 * region, but on IVB and BYT DF regions must be programmed in terms of
170 * floats. A <0,2,1> region accomplishes this.
172 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
173 type_sz(reg
->type
) == 8 &&
174 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
175 brw_reg
.width
== BRW_WIDTH_1
&&
176 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
177 brw_reg
.width
= BRW_WIDTH_2
;
178 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
184 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
186 struct brw_stage_prog_data
*prog_data
,
187 struct shader_stats shader_stats
,
188 bool runtime_check_aads_emit
,
189 gl_shader_stage stage
)
191 : compiler(compiler
), log_data(log_data
),
192 devinfo(compiler
->devinfo
),
193 prog_data(prog_data
),
194 shader_stats(shader_stats
),
195 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
196 stage(stage
), mem_ctx(mem_ctx
)
198 p
= rzalloc(mem_ctx
, struct brw_codegen
);
199 brw_init_codegen(devinfo
, p
, mem_ctx
);
201 /* In the FS code generator, we are very careful to ensure that we always
202 * set the right execution size so we don't need the EU code to "help" us
203 * by trying to infer it. Sometimes, it infers the wrong thing.
205 p
->automatic_exec_sizes
= false;
208 fs_generator::~fs_generator()
212 class ip_record
: public exec_node
{
214 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
225 fs_generator::patch_discard_jumps_to_fb_writes()
227 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
230 int scale
= brw_jump_scale(p
->devinfo
);
232 /* There is a somewhat strange undocumented requirement of using
233 * HALT, according to the simulator. If some channel has HALTed to
234 * a particular UIP, then by the end of the program, every channel
235 * must have HALTed to that UIP. Furthermore, the tracking is a
236 * stack, so you can't do the final halt of a UIP after starting
237 * halting to a new UIP.
239 * Symptoms of not emitting this instruction on actual hardware
240 * included GPU hangs and sparkly rendering on the piglit discard
243 brw_inst
*last_halt
= gen6_HALT(p
);
244 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
245 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
249 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
250 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
252 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
253 /* HALT takes a half-instruction distance from the pre-incremented IP. */
254 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
257 this->discard_halt_patches
.make_empty();
262 fs_generator::generate_send(fs_inst
*inst
,
265 struct brw_reg ex_desc
,
266 struct brw_reg payload
,
267 struct brw_reg payload2
)
269 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
270 dst
.nr
== BRW_ARF_NULL
;
271 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
273 uint32_t desc_imm
= inst
->desc
|
274 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
276 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
278 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
279 /* If we have any sort of extended descriptor, then we need SENDS. This
280 * also covers the dual-payload case because ex_mlen goes in ex_desc.
282 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
283 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
286 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDSC
);
288 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
291 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
296 fs_generator::fire_fb_write(fs_inst
*inst
,
297 struct brw_reg payload
,
298 struct brw_reg implied_header
,
301 uint32_t msg_control
;
303 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
305 if (devinfo
->gen
< 6) {
306 brw_push_insn_state(p
);
307 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
308 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
309 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
310 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
311 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
312 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
313 brw_pop_insn_state(p
);
316 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
317 assert(inst
->group
== 0 && inst
->exec_size
== 16);
318 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
320 } else if (prog_data
->dual_src_blend
) {
321 assert(inst
->exec_size
== 8);
323 if (inst
->group
% 16 == 0)
324 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
325 else if (inst
->group
% 16 == 8)
326 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
328 unreachable("Invalid dual-source FB write instruction group");
331 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
333 if (inst
->exec_size
== 16)
334 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
335 else if (inst
->exec_size
== 8)
336 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
338 unreachable("Invalid FB write execution size");
341 /* We assume render targets start at 0, because headerless FB write
342 * messages set "Render Target Index" to 0. Using a different binding
343 * table index would make it impossible to use headerless messages.
345 const uint32_t surf_index
= inst
->target
;
347 brw_inst
*insn
= brw_fb_WRITE(p
,
349 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
356 inst
->header_size
!= 0);
358 if (devinfo
->gen
>= 6)
359 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
363 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
365 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
366 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
367 brw_set_default_flag_reg(p
, 0, 0);
370 const struct brw_reg implied_header
=
371 devinfo
->gen
< 6 ? payload
: brw_null_reg();
373 if (inst
->base_mrf
>= 0)
374 payload
= brw_message_reg(inst
->base_mrf
);
376 if (!runtime_check_aads_emit
) {
377 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
379 /* This can only happen in gen < 6 */
380 assert(devinfo
->gen
< 6);
382 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
384 /* Check runtime bit to detect if we have to send AA data or not */
385 brw_push_insn_state(p
);
386 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
387 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
390 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
392 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
394 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
395 brw_pop_insn_state(p
);
397 /* Don't send AA data */
398 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
400 brw_land_fwd_jump(p
, jmp
);
401 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
406 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
407 struct brw_reg payload
)
409 assert(inst
->size_written
% REG_SIZE
== 0);
410 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
411 /* We assume that render targets start at binding table index 0. */
412 const unsigned surf_index
= inst
->target
;
414 gen9_fb_READ(p
, dst
, payload
, surf_index
,
415 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
416 prog_data
->persample_dispatch
);
420 fs_generator::generate_mov_indirect(fs_inst
*inst
,
423 struct brw_reg indirect_byte_offset
)
425 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
426 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
427 assert(!reg
.abs
&& !reg
.negate
);
428 assert(reg
.type
== dst
.type
);
430 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
432 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
433 imm_byte_offset
+= indirect_byte_offset
.ud
;
435 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
436 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
437 brw_MOV(p
, dst
, reg
);
439 /* Prior to Broadwell, there are only 8 address registers. */
440 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
442 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
443 struct brw_reg addr
= vec8(brw_address_reg(0));
445 /* The destination stride of an instruction (in bytes) must be greater
446 * than or equal to the size of the rest of the instruction. Since the
447 * address register is of type UW, we can't use a D-type instruction.
448 * In order to get around this, re retype to UW and use a stride.
450 indirect_byte_offset
=
451 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
453 /* There are a number of reasons why we don't use the base offset here.
454 * One reason is that the field is only 9 bits which means we can only
455 * use it to access the first 16 GRFs. Also, from the Haswell PRM
456 * section "Register Region Restrictions":
458 * "The lower bits of the AddressImmediate must not overflow to
459 * change the register address. The lower 5 bits of Address
460 * Immediate when added to lower 5 bits of address register gives
461 * the sub-register offset. The upper bits of Address Immediate
462 * when added to upper bits of address register gives the register
463 * address. Any overflow from sub-register offset is dropped."
465 * Since the indirect may cause us to cross a register boundary, this
466 * makes the base offset almost useless. We could try and do something
467 * clever where we use a actual base offset if base_offset % 32 == 0 but
468 * that would mean we were generating different code depending on the
469 * base offset. Instead, for the sake of consistency, we'll just do the
470 * add ourselves. This restriction is only listed in the Haswell PRM
471 * but empirical testing indicates that it applies on all older
472 * generations and is lifted on Broadwell.
474 * In the end, while base_offset is nice to look at in the generated
475 * code, using it saves us 0 instructions and would require quite a bit
476 * of case-by-case work. It's just not worth it.
478 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
480 if (type_sz(reg
.type
) > 4 &&
481 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
482 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
483 !devinfo
->has_64bit_types
)) {
484 /* IVB has an issue (which we found empirically) where it reads two
485 * address register components per channel for indirectly addressed
488 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
490 * "When source or destination datatype is 64b or operation is
491 * integer DWord multiply, indirect addressing must not be used."
493 * To work around both of these, we do two integer MOVs insead of one
494 * 64-bit MOV. Because no double value should ever cross a register
495 * boundary, it's safe to use the immediate offset in the indirect
496 * here to handle adding 4 bytes to the offset and avoid the extra
497 * ADD to the register file.
499 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
500 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
501 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
502 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
504 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
506 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
508 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
509 !inst
->get_next()->is_tail_sentinel() &&
510 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
511 /* From the Sandybridge PRM:
513 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
514 * instruction that “indexed/indirect” source AND is followed
515 * by a send, the instruction requires a “Switch”. This is to
516 * avoid race condition where send may dispatch before MRF is
519 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
526 fs_generator::generate_shuffle(fs_inst
*inst
,
531 /* Ivy bridge has some strange behavior that makes this a real pain to
532 * implement for 64-bit values so we just don't bother.
534 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
536 /* Because we're using the address register, we're limited to 8-wide
537 * execution on gen7. On gen8, we're limited to 16-wide by the address
538 * register file and 8-wide for 64-bit types. We could try and make this
539 * instruction splittable higher up in the compiler but that gets weird
540 * because it reads all of the channels regardless of execution size. It's
541 * easier just to split it here.
543 const unsigned lower_width
=
544 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
545 8 : MIN2(16, inst
->exec_size
);
547 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
548 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
549 brw_set_default_group(p
, group
);
551 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
552 idx
.file
== BRW_IMMEDIATE_VALUE
) {
553 /* Trivial, the source is already uniform or the index is a constant.
554 * We will typically not get here if the optimizer is doing its job,
555 * but asserting would be mean.
557 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
558 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
560 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
561 struct brw_reg addr
= vec8(brw_address_reg(0));
563 struct brw_reg group_idx
= suboffset(idx
, group
);
565 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
566 /* Things get grumpy if the register is too wide. */
571 assert(type_sz(group_idx
.type
) <= 4);
572 if (type_sz(group_idx
.type
) == 4) {
573 /* The destination stride of an instruction (in bytes) must be
574 * greater than or equal to the size of the rest of the
575 * instruction. Since the address register is of type UW, we
576 * can't use a D-type instruction. In order to get around this,
577 * re retype to UW and use a stride.
579 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
582 /* Take into account the component size and horizontal stride. */
583 assert(src
.vstride
== src
.hstride
+ src
.width
);
584 brw_SHL(p
, addr
, group_idx
,
585 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
588 /* Add on the register start offset */
589 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
591 if (type_sz(src
.type
) > 4 &&
592 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
593 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
594 /* IVB has an issue (which we found empirically) where it reads
595 * two address register components per channel for indirectly
596 * addressed 64-bit sources.
598 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
600 * "When source or destination datatype is 64b or operation is
601 * integer DWord multiply, indirect addressing must not be
604 * To work around both of these, we do two integer MOVs insead of
605 * one 64-bit MOV. Because no double value should ever cross a
606 * register boundary, it's safe to use the immediate offset in the
607 * indirect here to handle adding 4 bytes to the offset and avoid
608 * the extra ADD to the register file.
610 struct brw_reg gdst
= suboffset(dst
, group
);
611 struct brw_reg dst_d
= retype(spread(gdst
, 2),
612 BRW_REGISTER_TYPE_D
);
614 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
615 brw_MOV(p
, byte_offset(dst_d
, 4),
616 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
618 brw_MOV(p
, suboffset(dst
, group
),
619 retype(brw_VxH_indirect(0, 0), src
.type
));
626 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
627 struct brw_reg dst
, struct brw_reg src
,
630 /* Requires a quad. */
631 assert(inst
->exec_size
>= 4);
633 if (src
.file
== BRW_IMMEDIATE_VALUE
||
634 has_scalar_region(src
)) {
635 /* The value is uniform across all channels */
636 brw_MOV(p
, dst
, src
);
638 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
639 /* This only works on 8-wide 32-bit values */
640 assert(inst
->exec_size
== 8);
641 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
642 assert(src
.vstride
== src
.width
+ 1);
643 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
644 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
645 swiz_src
.swizzle
= swiz
;
646 brw_MOV(p
, dst
, swiz_src
);
649 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
650 assert(src
.vstride
== src
.width
+ 1);
651 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
654 case BRW_SWIZZLE_XXXX
:
655 case BRW_SWIZZLE_YYYY
:
656 case BRW_SWIZZLE_ZZZZ
:
657 case BRW_SWIZZLE_WWWW
:
658 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
661 case BRW_SWIZZLE_XXZZ
:
662 case BRW_SWIZZLE_YYWW
:
663 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
666 case BRW_SWIZZLE_XYXY
:
667 case BRW_SWIZZLE_ZWZW
:
668 assert(inst
->exec_size
== 4);
669 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
673 assert(inst
->force_writemask_all
);
674 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
676 for (unsigned c
= 0; c
< 4; c
++) {
677 brw_inst
*insn
= brw_MOV(
678 p
, stride(suboffset(dst
, c
),
679 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
680 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
682 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
683 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
692 fs_generator::generate_urb_read(fs_inst
*inst
,
694 struct brw_reg header
)
696 assert(inst
->size_written
% REG_SIZE
== 0);
697 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
698 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
700 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
701 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
702 brw_set_src0(p
, send
, header
);
703 brw_set_src1(p
, send
, brw_imm_ud(0u));
705 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
706 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
708 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
709 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
711 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
712 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
713 brw_inst_set_header_present(p
->devinfo
, send
, true);
714 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
718 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
722 /* WaClearTDRRegBeforeEOTForNonPS.
724 * WA: Clear tdr register before send EOT in all non-PS shader kernels
726 * mov(8) tdr0:ud 0x0:ud {NoMask}"
728 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
729 brw_push_insn_state(p
);
730 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
731 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
732 brw_pop_insn_state(p
);
735 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
737 brw_set_dest(p
, insn
, brw_null_reg());
738 brw_set_src0(p
, insn
, payload
);
739 brw_set_src1(p
, insn
, brw_imm_ud(0u));
741 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
742 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
744 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
745 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
746 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
748 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
749 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
750 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
752 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
753 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
754 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
755 brw_inst_set_header_present(p
->devinfo
, insn
, true);
756 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
760 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
762 struct brw_inst
*insn
;
764 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
766 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
767 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
768 brw_set_src1(p
, insn
, brw_imm_ud(0u));
770 /* Terminate a compute shader by sending a message to the thread spawner.
772 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
773 brw_inst_set_mlen(devinfo
, insn
, 1);
774 brw_inst_set_rlen(devinfo
, insn
, 0);
775 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
776 brw_inst_set_header_present(devinfo
, insn
, false);
778 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
779 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
781 /* Note that even though the thread has a URB resource associated with it,
782 * we set the "do not dereference URB" bit, because the URB resource is
783 * managed by the fixed-function unit, so it will free it automatically.
785 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
787 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
791 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
798 fs_generator::generate_linterp(fs_inst
*inst
,
799 struct brw_reg dst
, struct brw_reg
*src
)
803 * -----------------------------------
804 * | src1+0 | src1+1 | src1+2 | src1+3 |
805 * |-----------------------------------|
806 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
807 * -----------------------------------
809 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
811 * -----------------------------------
812 * | src1+0 | src1+1 | src1+2 | src1+3 |
813 * |-----------------------------------|
814 * |(x0, x1)|(y0, y1)| | | in SIMD8
815 * |-----------------------------------|
816 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
817 * -----------------------------------
819 * See also: emit_interpolation_setup_gen4().
821 struct brw_reg delta_x
= src
[0];
822 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
823 struct brw_reg interp
= stride(src
[1], 0, 1, 0);
826 /* nir_lower_interpolation() will do the lowering to MAD instructions for
829 assert(devinfo
->gen
< 11);
831 if (devinfo
->has_pln
) {
832 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
833 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
835 * "[DevSNB]:<src1> must be even register aligned.
837 * This restriction is lifted on Ivy Bridge.
839 * This means that we need to split PLN into LINE+MAC on-the-fly.
840 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
841 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
842 * coordinate registers are laid out differently so we leave it as a
843 * SIMD16 instruction.
845 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
846 assert(inst
->group
% 16 == 0);
848 brw_push_insn_state(p
);
849 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
851 /* Thanks to two accumulators, we can emit all the LINEs and then all
852 * the MACs. This improves parallelism a bit.
854 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
855 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
856 offset(delta_x
, g
* 2));
857 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
859 /* LINE writes the accumulator automatically on gen4-5. On Sandy
860 * Bridge and later, we have to explicitly enable it.
862 if (devinfo
->gen
>= 6)
863 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
865 /* brw_set_default_saturate() is called before emitting
866 * instructions, so the saturate bit is set in each instruction,
867 * so we need to unset it on the LINE instructions.
869 brw_inst_set_saturate(p
->devinfo
, line
, false);
872 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
873 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
874 offset(delta_x
, g
* 2 + 1));
875 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
876 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
879 brw_pop_insn_state(p
);
883 brw_PLN(p
, dst
, interp
, delta_x
);
888 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
889 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
891 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
893 /* brw_set_default_saturate() is called before emitting instructions, so
894 * the saturate bit is set in each instruction, so we need to unset it on
895 * the first instruction.
897 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
904 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
907 struct brw_reg surf_index
)
909 assert(devinfo
->gen
>= 7);
910 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
915 switch (inst
->exec_size
) {
917 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
920 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
923 unreachable("Invalid width for texture instruction");
926 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
932 retype(dst
, BRW_REGISTER_TYPE_UW
),
937 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
938 rlen
, /* response length */
940 inst
->header_size
> 0,
942 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
946 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
947 struct brw_reg surface_index
,
948 struct brw_reg sampler_index
)
950 assert(devinfo
->gen
< 7);
951 assert(inst
->size_written
% REG_SIZE
== 0);
954 uint32_t return_format
;
956 /* Sampler EOT message of less than the dispatch width would kill the
957 * thread prematurely.
959 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
962 case BRW_REGISTER_TYPE_D
:
963 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
965 case BRW_REGISTER_TYPE_UD
:
966 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
969 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
973 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
974 * is set as part of the message descriptor. On gen4, the PRM seems to
975 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
976 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
977 * gone from the message descriptor entirely and you just get UINT32 all
978 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
979 * just stomp it to UINT32 all the time.
981 if (inst
->opcode
== SHADER_OPCODE_TXS
)
982 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
984 switch (inst
->exec_size
) {
986 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
989 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
992 unreachable("Invalid width for texture instruction");
995 if (devinfo
->gen
>= 5) {
996 switch (inst
->opcode
) {
997 case SHADER_OPCODE_TEX
:
998 if (inst
->shadow_compare
) {
999 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1001 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1005 if (inst
->shadow_compare
) {
1006 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1008 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1011 case SHADER_OPCODE_TXL
:
1012 if (inst
->shadow_compare
) {
1013 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1015 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1018 case SHADER_OPCODE_TXS
:
1019 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1021 case SHADER_OPCODE_TXD
:
1022 assert(!inst
->shadow_compare
);
1023 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1025 case SHADER_OPCODE_TXF
:
1026 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1028 case SHADER_OPCODE_TXF_CMS
:
1029 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1031 case SHADER_OPCODE_LOD
:
1032 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1034 case SHADER_OPCODE_TG4
:
1035 assert(devinfo
->gen
== 6);
1036 assert(!inst
->shadow_compare
);
1037 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1039 case SHADER_OPCODE_SAMPLEINFO
:
1040 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1043 unreachable("not reached");
1046 switch (inst
->opcode
) {
1047 case SHADER_OPCODE_TEX
:
1048 /* Note that G45 and older determines shadow compare and dispatch width
1049 * from message length for most messages.
1051 if (inst
->exec_size
== 8) {
1052 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1053 if (inst
->shadow_compare
) {
1054 assert(inst
->mlen
== 6);
1056 assert(inst
->mlen
<= 4);
1059 if (inst
->shadow_compare
) {
1060 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1061 assert(inst
->mlen
== 9);
1063 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1064 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1069 if (inst
->shadow_compare
) {
1070 assert(inst
->exec_size
== 8);
1071 assert(inst
->mlen
== 6);
1072 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1074 assert(inst
->mlen
== 9);
1075 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1076 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1079 case SHADER_OPCODE_TXL
:
1080 if (inst
->shadow_compare
) {
1081 assert(inst
->exec_size
== 8);
1082 assert(inst
->mlen
== 6);
1083 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1085 assert(inst
->mlen
== 9);
1086 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1087 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1090 case SHADER_OPCODE_TXD
:
1091 /* There is no sample_d_c message; comparisons are done manually */
1092 assert(inst
->exec_size
== 8);
1093 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1094 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1096 case SHADER_OPCODE_TXF
:
1097 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1098 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1099 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1101 case SHADER_OPCODE_TXS
:
1102 assert(inst
->mlen
== 3);
1103 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1104 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1107 unreachable("not reached");
1110 assert(msg_type
!= -1);
1112 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1116 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1118 /* Load the message header if present. If there's a texture offset,
1119 * we need to set it up explicitly and load the offset bitfield.
1120 * Otherwise, we can use an implied move from g0 to the first message reg.
1122 struct brw_reg src
= brw_null_reg();
1123 if (inst
->header_size
!= 0) {
1124 if (devinfo
->gen
< 6 && !inst
->offset
) {
1125 /* Set up an implied move from g0 to the MRF. */
1126 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1128 assert(inst
->base_mrf
!= -1);
1129 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1131 brw_push_insn_state(p
);
1132 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1133 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1134 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1135 /* Explicitly set up the message header by copying g0 to the MRF. */
1136 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1138 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1140 /* Set the offset bits in DWord 2. */
1141 brw_MOV(p
, get_element_ud(header_reg
, 2),
1142 brw_imm_ud(inst
->offset
));
1145 brw_pop_insn_state(p
);
1149 uint32_t base_binding_table_index
;
1150 switch (inst
->opcode
) {
1151 case SHADER_OPCODE_TG4
:
1152 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1155 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1159 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1160 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1163 retype(dst
, BRW_REGISTER_TYPE_UW
),
1166 surface_index
.ud
+ base_binding_table_index
,
1167 sampler_index
.ud
% 16,
1169 inst
->size_written
/ REG_SIZE
,
1171 inst
->header_size
!= 0,
1177 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1180 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1182 * Ideally, we want to produce:
1185 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1186 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1187 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1188 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1189 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1190 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1191 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1192 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1194 * and add another set of two more subspans if in 16-pixel dispatch mode.
1196 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1197 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1198 * pair. But the ideal approximation may impose a huge performance cost on
1199 * sample_d. On at least Haswell, sample_d instruction does some
1200 * optimizations if the same LOD is used for all pixels in the subspan.
1202 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1203 * appropriate swizzling.
1206 fs_generator::generate_ddx(const fs_inst
*inst
,
1207 struct brw_reg dst
, struct brw_reg src
)
1209 unsigned vstride
, width
;
1211 if (devinfo
->gen
>= 8) {
1212 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1213 /* produce accurate derivatives */
1214 vstride
= BRW_VERTICAL_STRIDE_2
;
1215 width
= BRW_WIDTH_2
;
1217 /* replicate the derivative at the top-left pixel to other pixels */
1218 vstride
= BRW_VERTICAL_STRIDE_4
;
1219 width
= BRW_WIDTH_4
;
1222 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1223 struct brw_reg src1
= src
;
1225 src0
.vstride
= vstride
;
1227 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1228 src1
.vstride
= vstride
;
1230 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1232 brw_ADD(p
, dst
, src0
, negate(src1
));
1234 /* On Haswell and earlier, the region used above appears to not work
1235 * correctly for compressed instructions. At least on Haswell and
1236 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1237 * would have to split to SIMD8 no matter which method we choose, we
1238 * may as well use ALIGN16 on all platforms gen7 and earlier.
1240 struct brw_reg src0
= stride(src
, 4, 4, 1);
1241 struct brw_reg src1
= stride(src
, 4, 4, 1);
1242 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1243 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1244 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1246 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1247 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1250 brw_push_insn_state(p
);
1251 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1252 brw_ADD(p
, dst
, negate(src0
), src1
);
1253 brw_pop_insn_state(p
);
1257 /* The negate_value boolean is used to negate the derivative computation for
1258 * FBOs, since they place the origin at the upper left instead of the lower
1262 fs_generator::generate_ddy(const fs_inst
*inst
,
1263 struct brw_reg dst
, struct brw_reg src
)
1265 const uint32_t type_size
= type_sz(src
.type
);
1267 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1268 /* produce accurate derivatives.
1270 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1271 * "Register Region Restrictions", Section "1. Special Restrictions":
1273 * "In Align16 mode, the channel selects and channel enables apply to
1274 * a pair of half-floats, because these parameters are defined for
1275 * DWord elements ONLY. This is applicable when both source and
1276 * destination are half-floats."
1278 * So for half-float operations we use the Gen11+ Align1 path. CHV
1279 * inherits its FP16 hardware from SKL, so it is not affected.
1281 if (devinfo
->gen
>= 11 ||
1282 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1283 src
= stride(src
, 0, 2, 1);
1285 brw_push_insn_state(p
);
1286 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1287 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1288 brw_set_default_group(p
, inst
->group
+ g
);
1289 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1290 negate(byte_offset(src
, g
* type_size
)),
1291 byte_offset(src
, (g
+ 2) * type_size
));
1293 brw_pop_insn_state(p
);
1295 struct brw_reg src0
= stride(src
, 4, 4, 1);
1296 struct brw_reg src1
= stride(src
, 4, 4, 1);
1297 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1298 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1300 brw_push_insn_state(p
);
1301 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1302 brw_ADD(p
, dst
, negate(src0
), src1
);
1303 brw_pop_insn_state(p
);
1306 /* replicate the derivative at the top-left pixel to other pixels */
1307 if (devinfo
->gen
>= 8) {
1308 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1309 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1311 brw_ADD(p
, dst
, negate(src0
), src1
);
1313 /* On Haswell and earlier, the region used above appears to not work
1314 * correctly for compressed instructions. At least on Haswell and
1315 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1316 * would have to split to SIMD8 no matter which method we choose, we
1317 * may as well use ALIGN16 on all platforms gen7 and earlier.
1319 struct brw_reg src0
= stride(src
, 4, 4, 1);
1320 struct brw_reg src1
= stride(src
, 4, 4, 1);
1321 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1322 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1324 brw_push_insn_state(p
);
1325 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1326 brw_ADD(p
, dst
, negate(src0
), src1
);
1327 brw_pop_insn_state(p
);
1333 fs_generator::generate_discard_jump(fs_inst
*)
1335 assert(devinfo
->gen
>= 6);
1337 /* This HALT will be patched up at FB write time to point UIP at the end of
1338 * the program, and at brw_uip_jip() JIP will be set to the end of the
1339 * current block (or the program).
1341 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1346 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1348 /* The 32-wide messages only respect the first 16-wide half of the channel
1349 * enable signals which are replicated identically for the second group of
1350 * 16 channels, so we cannot use them unless the write is marked
1351 * force_writemask_all.
1353 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1354 MIN2(16, inst
->exec_size
);
1355 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1356 assert(inst
->mlen
!= 0);
1358 brw_push_insn_state(p
);
1359 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1360 brw_set_default_compression(p
, lower_size
> 8);
1362 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1363 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1365 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1366 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1368 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1370 inst
->offset
+ block_size
* REG_SIZE
* i
);
1373 brw_pop_insn_state(p
);
1377 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1379 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1380 assert(inst
->mlen
!= 0);
1382 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1383 inst
->exec_size
/ 8, inst
->offset
);
1387 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1389 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1391 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1395 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1397 struct brw_reg index
,
1398 struct brw_reg offset
)
1400 assert(type_sz(dst
.type
) == 4);
1401 assert(inst
->mlen
!= 0);
1403 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1404 index
.type
== BRW_REGISTER_TYPE_UD
);
1405 uint32_t surf_index
= index
.ud
;
1407 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1408 offset
.type
== BRW_REGISTER_TYPE_UD
);
1409 uint32_t read_offset
= offset
.ud
;
1411 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1412 read_offset
, surf_index
);
1416 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1418 struct brw_reg index
,
1419 struct brw_reg payload
)
1421 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1422 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1423 assert(type_sz(dst
.type
) == 4);
1425 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1426 const uint32_t surf_index
= index
.ud
;
1428 brw_push_insn_state(p
);
1429 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1430 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1431 brw_pop_insn_state(p
);
1433 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1434 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1435 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1436 brw_set_desc(p
, send
,
1437 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1439 brw_dp_read_desc(devinfo
, surf_index
,
1440 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1441 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1442 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1445 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1447 brw_push_insn_state(p
);
1448 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1450 /* a0.0 = surf_index & 0xff */
1451 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1452 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1453 brw_set_dest(p
, insn_and
, addr
);
1454 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1455 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1457 /* dst = send(payload, a0.0 | <descriptor>) */
1458 brw_send_indirect_message(
1459 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1460 retype(dst
, BRW_REGISTER_TYPE_UD
),
1461 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1462 brw_message_desc(devinfo
, 1,
1463 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1464 brw_dp_read_desc(devinfo
, 0 /* surface */,
1465 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1466 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1467 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1470 brw_pop_insn_state(p
);
1475 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1477 struct brw_reg index
)
1479 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1480 assert(inst
->header_size
!= 0);
1483 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1484 index
.type
== BRW_REGISTER_TYPE_UD
);
1485 uint32_t surf_index
= index
.ud
;
1487 uint32_t simd_mode
, rlen
, msg_type
;
1488 if (inst
->exec_size
== 16) {
1489 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1492 assert(inst
->exec_size
== 8);
1493 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1497 if (devinfo
->gen
>= 5)
1498 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1500 /* We always use the SIMD16 message so that we only have to load U, and
1503 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1504 assert(inst
->mlen
== 3);
1505 assert(inst
->size_written
== 8 * REG_SIZE
);
1507 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1510 struct brw_reg header
= brw_vec8_grf(0, 0);
1511 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1513 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1514 brw_inst_set_compression(devinfo
, send
, false);
1515 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1516 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1517 brw_set_src0(p
, send
, header
);
1518 if (devinfo
->gen
< 6)
1519 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1521 /* Our surface is set up as floats, regardless of what actual data is
1524 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1525 brw_set_desc(p
, send
,
1526 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1527 brw_sampler_desc(devinfo
, surf_index
,
1528 0, /* sampler (unused) */
1529 msg_type
, simd_mode
, return_format
));
1533 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1536 struct brw_reg msg_data
,
1539 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1540 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1541 assert(inst
->size_written
% REG_SIZE
== 0);
1543 brw_pixel_interpolator_query(p
,
1544 retype(dst
, BRW_REGISTER_TYPE_UW
),
1545 /* If we don't have a payload, what we send doesn't matter */
1546 has_payload
? src
: brw_vec8_grf(0, 0),
1547 inst
->pi_noperspective
,
1550 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1551 inst
->size_written
/ REG_SIZE
);
1554 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1555 * the ADD instruction.
1558 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1560 struct brw_reg src0
,
1561 struct brw_reg src1
)
1563 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1564 dst
.type
== BRW_REGISTER_TYPE_UD
);
1565 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1566 src0
.type
== BRW_REGISTER_TYPE_UD
);
1568 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1569 const unsigned lower_size
= MIN2(inst
->exec_size
,
1570 devinfo
->gen
>= 8 ? 16 : 8);
1572 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1573 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1574 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1575 (i
* lower_size
/ (1 << src0
.width
))) *
1576 type_sz(src0
.type
) / REG_SIZE
),
1577 suboffset(reg
, i
* lower_size
/ 4));
1578 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1579 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1580 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1585 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1590 assert(devinfo
->gen
>= 7);
1591 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1592 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1593 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1595 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1597 * Because this instruction does not have a 16-bit floating-point type,
1598 * the destination data type must be Word (W).
1600 * The destination must be DWord-aligned and specify a horizontal stride
1601 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1602 * each destination channel and the upper word is not modified.
1604 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1606 /* Give each 32-bit channel of dst the form below, where "." means
1610 brw_F32TO16(p
, dst_w
, y
);
1615 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1617 /* And, finally the form of packHalf2x16's output:
1620 brw_F32TO16(p
, dst_w
, x
);
1624 fs_generator::generate_shader_time_add(fs_inst
*,
1625 struct brw_reg payload
,
1626 struct brw_reg offset
,
1627 struct brw_reg value
)
1629 assert(devinfo
->gen
>= 7);
1630 brw_push_insn_state(p
);
1631 brw_set_default_mask_control(p
, true);
1633 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1634 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1636 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1639 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1640 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1641 value
.width
= BRW_WIDTH_1
;
1642 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1643 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1645 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1648 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1649 * case, and we don't really care about squeezing every bit of performance
1650 * out of this path, so we just emit the MOVs from here.
1652 brw_MOV(p
, payload_offset
, offset
);
1653 brw_MOV(p
, payload_value
, value
);
1654 brw_shader_time_add(p
, payload
,
1655 prog_data
->binding_table
.shader_time_start
);
1656 brw_pop_insn_state(p
);
1660 fs_generator::enable_debug(const char *shader_name
)
1663 this->shader_name
= shader_name
;
1667 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1668 struct brw_compile_stats
*stats
)
1670 /* align to 64 byte boundary. */
1671 while (p
->next_insn_offset
% 64)
1674 this->dispatch_width
= dispatch_width
;
1676 int start_offset
= p
->next_insn_offset
;
1677 int spill_count
= 0, fill_count
= 0;
1680 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1682 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1683 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1686 struct brw_reg src
[4], dst
;
1687 unsigned int last_insn_offset
= p
->next_insn_offset
;
1688 bool multiple_instructions_emitted
= false;
1690 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1691 * "Register Region Restrictions" section: for BDW, SKL:
1693 * "A POW/FDIV operation must not be followed by an instruction
1694 * that requires two destination registers."
1696 * The documentation is often lacking annotations for Atom parts,
1697 * and empirically this affects CHV as well.
1699 if (devinfo
->gen
>= 8 &&
1700 devinfo
->gen
<= 9 &&
1702 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1703 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1704 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1706 last_insn_offset
= p
->next_insn_offset
;
1709 if (unlikely(debug_flag
))
1710 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1712 /* If the instruction writes to more than one register, it needs to be
1713 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1714 * hardware figures out by itself what the right compression mode is,
1715 * but we still need to know whether the instruction is compressed to
1716 * set up the source register regions appropriately.
1718 * XXX - This is wrong for instructions that write a single register but
1719 * read more than one which should strictly speaking be treated as
1720 * compressed. For instructions that don't write any registers it
1721 * relies on the destination being a null register of the correct
1722 * type and regioning so the instruction is considered compressed
1723 * or not accordingly.
1725 const bool compressed
=
1726 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1727 brw_set_default_compression(p
, compressed
);
1728 brw_set_default_group(p
, inst
->group
);
1730 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1731 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1732 &inst
->src
[i
], compressed
);
1733 /* The accumulator result appears to get used for the
1734 * conditional modifier generation. When negating a UD
1735 * value, there is a 33rd bit generated for the sign in the
1736 * accumulator value, so now you can't check, for example,
1737 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1739 assert(!inst
->conditional_mod
||
1740 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1741 !inst
->src
[i
].negate
);
1743 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1744 &inst
->dst
, compressed
);
1746 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1747 brw_set_default_predicate_control(p
, inst
->predicate
);
1748 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1749 /* On gen7 and above, hardware automatically adds the group onto the
1750 * flag subregister number. On Sandy Bridge and older, we have to do it
1753 const unsigned flag_subreg
= inst
->flag_subreg
+
1754 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1755 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1756 brw_set_default_saturate(p
, inst
->saturate
);
1757 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1758 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1760 unsigned exec_size
= inst
->exec_size
;
1761 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1762 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1766 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1768 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1769 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1770 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1771 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1773 switch (inst
->opcode
) {
1774 case BRW_OPCODE_MOV
:
1775 brw_MOV(p
, dst
, src
[0]);
1777 case BRW_OPCODE_ADD
:
1778 brw_ADD(p
, dst
, src
[0], src
[1]);
1780 case BRW_OPCODE_MUL
:
1781 brw_MUL(p
, dst
, src
[0], src
[1]);
1783 case BRW_OPCODE_AVG
:
1784 brw_AVG(p
, dst
, src
[0], src
[1]);
1786 case BRW_OPCODE_MACH
:
1787 brw_MACH(p
, dst
, src
[0], src
[1]);
1790 case BRW_OPCODE_LINE
:
1791 brw_LINE(p
, dst
, src
[0], src
[1]);
1794 case BRW_OPCODE_MAD
:
1795 assert(devinfo
->gen
>= 6);
1796 if (devinfo
->gen
< 10)
1797 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1798 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1801 case BRW_OPCODE_LRP
:
1802 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1803 if (devinfo
->gen
< 10)
1804 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1805 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1808 case BRW_OPCODE_FRC
:
1809 brw_FRC(p
, dst
, src
[0]);
1811 case BRW_OPCODE_RNDD
:
1812 brw_RNDD(p
, dst
, src
[0]);
1814 case BRW_OPCODE_RNDE
:
1815 brw_RNDE(p
, dst
, src
[0]);
1817 case BRW_OPCODE_RNDZ
:
1818 brw_RNDZ(p
, dst
, src
[0]);
1821 case BRW_OPCODE_AND
:
1822 brw_AND(p
, dst
, src
[0], src
[1]);
1825 brw_OR(p
, dst
, src
[0], src
[1]);
1827 case BRW_OPCODE_XOR
:
1828 brw_XOR(p
, dst
, src
[0], src
[1]);
1830 case BRW_OPCODE_NOT
:
1831 brw_NOT(p
, dst
, src
[0]);
1833 case BRW_OPCODE_ASR
:
1834 brw_ASR(p
, dst
, src
[0], src
[1]);
1836 case BRW_OPCODE_SHR
:
1837 brw_SHR(p
, dst
, src
[0], src
[1]);
1839 case BRW_OPCODE_SHL
:
1840 brw_SHL(p
, dst
, src
[0], src
[1]);
1842 case BRW_OPCODE_ROL
:
1843 assert(devinfo
->gen
>= 11);
1844 assert(src
[0].type
== dst
.type
);
1845 brw_ROL(p
, dst
, src
[0], src
[1]);
1847 case BRW_OPCODE_ROR
:
1848 assert(devinfo
->gen
>= 11);
1849 assert(src
[0].type
== dst
.type
);
1850 brw_ROR(p
, dst
, src
[0], src
[1]);
1852 case BRW_OPCODE_F32TO16
:
1853 assert(devinfo
->gen
>= 7);
1854 brw_F32TO16(p
, dst
, src
[0]);
1856 case BRW_OPCODE_F16TO32
:
1857 assert(devinfo
->gen
>= 7);
1858 brw_F16TO32(p
, dst
, src
[0]);
1860 case BRW_OPCODE_CMP
:
1861 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1862 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1863 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1864 * implemented in the compiler is not sufficient. Overriding the
1865 * type when the destination is the null register is necessary but
1866 * not sufficient by itself.
1868 assert(dst
.nr
== BRW_ARF_NULL
);
1869 dst
.type
= BRW_REGISTER_TYPE_D
;
1871 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1873 case BRW_OPCODE_SEL
:
1874 brw_SEL(p
, dst
, src
[0], src
[1]);
1876 case BRW_OPCODE_CSEL
:
1877 assert(devinfo
->gen
>= 8);
1878 if (devinfo
->gen
< 10)
1879 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1880 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1882 case BRW_OPCODE_BFREV
:
1883 assert(devinfo
->gen
>= 7);
1884 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1885 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1887 case BRW_OPCODE_FBH
:
1888 assert(devinfo
->gen
>= 7);
1889 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1891 case BRW_OPCODE_FBL
:
1892 assert(devinfo
->gen
>= 7);
1893 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1894 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1896 case BRW_OPCODE_LZD
:
1897 brw_LZD(p
, dst
, src
[0]);
1899 case BRW_OPCODE_CBIT
:
1900 assert(devinfo
->gen
>= 7);
1901 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1902 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1904 case BRW_OPCODE_ADDC
:
1905 assert(devinfo
->gen
>= 7);
1906 brw_ADDC(p
, dst
, src
[0], src
[1]);
1908 case BRW_OPCODE_SUBB
:
1909 assert(devinfo
->gen
>= 7);
1910 brw_SUBB(p
, dst
, src
[0], src
[1]);
1912 case BRW_OPCODE_MAC
:
1913 brw_MAC(p
, dst
, src
[0], src
[1]);
1916 case BRW_OPCODE_BFE
:
1917 assert(devinfo
->gen
>= 7);
1918 if (devinfo
->gen
< 10)
1919 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1920 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1923 case BRW_OPCODE_BFI1
:
1924 assert(devinfo
->gen
>= 7);
1925 brw_BFI1(p
, dst
, src
[0], src
[1]);
1927 case BRW_OPCODE_BFI2
:
1928 assert(devinfo
->gen
>= 7);
1929 if (devinfo
->gen
< 10)
1930 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1931 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1935 if (inst
->src
[0].file
!= BAD_FILE
) {
1936 /* The instruction has an embedded compare (only allowed on gen6) */
1937 assert(devinfo
->gen
== 6);
1938 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1940 brw_IF(p
, brw_get_default_exec_size(p
));
1944 case BRW_OPCODE_ELSE
:
1947 case BRW_OPCODE_ENDIF
:
1952 brw_DO(p
, brw_get_default_exec_size(p
));
1955 case BRW_OPCODE_BREAK
:
1958 case BRW_OPCODE_CONTINUE
:
1962 case BRW_OPCODE_WHILE
:
1967 case SHADER_OPCODE_RCP
:
1968 case SHADER_OPCODE_RSQ
:
1969 case SHADER_OPCODE_SQRT
:
1970 case SHADER_OPCODE_EXP2
:
1971 case SHADER_OPCODE_LOG2
:
1972 case SHADER_OPCODE_SIN
:
1973 case SHADER_OPCODE_COS
:
1974 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1975 if (devinfo
->gen
>= 6) {
1976 assert(inst
->mlen
== 0);
1977 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1978 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1979 src
[0], brw_null_reg());
1981 assert(inst
->mlen
>= 1);
1982 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1984 brw_math_function(inst
->opcode
),
1985 inst
->base_mrf
, src
[0],
1986 BRW_MATH_PRECISION_FULL
);
1989 case SHADER_OPCODE_INT_QUOTIENT
:
1990 case SHADER_OPCODE_INT_REMAINDER
:
1991 case SHADER_OPCODE_POW
:
1992 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1993 if (devinfo
->gen
>= 6) {
1994 assert(inst
->mlen
== 0);
1995 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1996 inst
->exec_size
== 8);
1997 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1999 assert(inst
->mlen
>= 1);
2000 assert(inst
->exec_size
== 8);
2001 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2002 inst
->base_mrf
, src
[0],
2003 BRW_MATH_PRECISION_FULL
);
2006 case FS_OPCODE_LINTERP
:
2007 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2009 case FS_OPCODE_PIXEL_X
:
2010 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2011 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2012 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2014 case FS_OPCODE_PIXEL_Y
:
2015 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2016 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2017 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2020 case SHADER_OPCODE_SEND
:
2021 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2022 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2025 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2026 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2028 case SHADER_OPCODE_TEX
:
2030 case SHADER_OPCODE_TXD
:
2031 case SHADER_OPCODE_TXF
:
2032 case SHADER_OPCODE_TXF_CMS
:
2033 case SHADER_OPCODE_TXL
:
2034 case SHADER_OPCODE_TXS
:
2035 case SHADER_OPCODE_LOD
:
2036 case SHADER_OPCODE_TG4
:
2037 case SHADER_OPCODE_SAMPLEINFO
:
2038 assert(inst
->src
[0].file
== BAD_FILE
);
2039 generate_tex(inst
, dst
, src
[1], src
[2]);
2042 case FS_OPCODE_DDX_COARSE
:
2043 case FS_OPCODE_DDX_FINE
:
2044 generate_ddx(inst
, dst
, src
[0]);
2046 case FS_OPCODE_DDY_COARSE
:
2047 case FS_OPCODE_DDY_FINE
:
2048 generate_ddy(inst
, dst
, src
[0]);
2051 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2052 generate_scratch_write(inst
, src
[0]);
2056 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2057 generate_scratch_read(inst
, dst
);
2061 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2062 generate_scratch_read_gen7(inst
, dst
);
2066 case SHADER_OPCODE_MOV_INDIRECT
:
2067 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2070 case SHADER_OPCODE_URB_READ_SIMD8
:
2071 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2072 generate_urb_read(inst
, dst
, src
[0]);
2075 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2076 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2077 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2078 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2079 generate_urb_write(inst
, src
[0]);
2082 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2083 assert(inst
->force_writemask_all
);
2084 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2087 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2088 assert(inst
->force_writemask_all
);
2089 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2092 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2093 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2096 case FS_OPCODE_REP_FB_WRITE
:
2097 case FS_OPCODE_FB_WRITE
:
2098 generate_fb_write(inst
, src
[0]);
2101 case FS_OPCODE_FB_READ
:
2102 generate_fb_read(inst
, dst
, src
[0]);
2105 case FS_OPCODE_DISCARD_JUMP
:
2106 generate_discard_jump(inst
);
2109 case SHADER_OPCODE_SHADER_TIME_ADD
:
2110 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2113 case SHADER_OPCODE_MEMORY_FENCE
:
2114 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2115 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2116 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2119 case SHADER_OPCODE_INTERLOCK
:
2120 assert(devinfo
->gen
>= 9);
2121 /* The interlock is basically a memory fence issued via sendc */
2122 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2125 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2126 const struct brw_reg mask
=
2127 brw_stage_has_packed_dispatch(devinfo
, stage
,
2128 prog_data
) ? brw_imm_ud(~0u) :
2129 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2131 brw_find_live_channel(p
, dst
, mask
);
2135 case SHADER_OPCODE_BROADCAST
:
2136 assert(inst
->force_writemask_all
);
2137 brw_broadcast(p
, dst
, src
[0], src
[1]);
2140 case SHADER_OPCODE_SHUFFLE
:
2141 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2144 case SHADER_OPCODE_SEL_EXEC
:
2145 assert(inst
->force_writemask_all
);
2146 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2147 brw_MOV(p
, dst
, src
[1]);
2148 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2149 brw_MOV(p
, dst
, src
[0]);
2152 case SHADER_OPCODE_QUAD_SWIZZLE
:
2153 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2154 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2155 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2158 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2159 assert(src
[0].type
== dst
.type
);
2160 assert(!src
[0].negate
&& !src
[0].abs
);
2161 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2162 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2163 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2164 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2165 const unsigned component
= src
[1].ud
;
2166 const unsigned cluster_size
= src
[2].ud
;
2167 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2168 cluster_size
, cluster_size
, 0);
2169 if (type_sz(src
[0].type
) > 4 &&
2170 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2171 /* IVB has an issue (which we found empirically) where it reads
2172 * two address register components per channel for indirectly
2173 * addressed 64-bit sources.
2175 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2177 * "When source or destination datatype is 64b or operation is
2178 * integer DWord multiply, indirect addressing must not be
2181 * To work around both of these, we do two integer MOVs insead of
2182 * one 64-bit MOV. Because no double value should ever cross a
2183 * register boundary, it's safe to use the immediate offset in the
2184 * indirect here to handle adding 4 bytes to the offset and avoid
2185 * the extra ADD to the register file.
2187 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2188 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2189 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2190 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2192 brw_MOV(p
, dst
, strided
);
2197 case FS_OPCODE_SET_SAMPLE_ID
:
2198 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2201 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2202 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2205 case FS_OPCODE_PLACEHOLDER_HALT
:
2206 /* This is the place where the final HALT needs to be inserted if
2207 * we've emitted any discards. If not, this will emit no code.
2209 if (!patch_discard_jumps_to_fb_writes()) {
2210 if (unlikely(debug_flag
)) {
2211 disasm_info
->use_tail
= true;
2216 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2217 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2218 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2221 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2222 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2223 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2226 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2227 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2228 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2231 case CS_OPCODE_CS_TERMINATE
:
2232 generate_cs_terminate(inst
, src
[0]);
2235 case SHADER_OPCODE_BARRIER
:
2236 generate_barrier(inst
, src
[0]);
2239 case BRW_OPCODE_DIM
:
2240 assert(devinfo
->is_haswell
);
2241 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2242 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2243 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2246 case SHADER_OPCODE_RND_MODE
:
2247 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2248 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2252 unreachable("Unsupported opcode");
2254 case SHADER_OPCODE_LOAD_PAYLOAD
:
2255 unreachable("Should be lowered by lower_load_payload()");
2258 if (multiple_instructions_emitted
)
2261 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2262 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2263 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2264 "emitting more than 1 instruction");
2266 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2268 if (inst
->conditional_mod
)
2269 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2270 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2271 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2275 brw_set_uip_jip(p
, start_offset
);
2277 /* end of program sentinel */
2278 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2283 if (unlikely(debug_flag
))
2285 brw_validate_instructions(devinfo
, p
->store
,
2287 p
->next_insn_offset
,
2290 int before_size
= p
->next_insn_offset
- start_offset
;
2291 brw_compact_instructions(p
, start_offset
, disasm_info
);
2292 int after_size
= p
->next_insn_offset
- start_offset
;
2294 if (unlikely(debug_flag
)) {
2295 unsigned char sha1
[21];
2298 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2300 _mesa_sha1_format(sha1buf
, sha1
);
2302 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2303 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2304 "%d:%d spills:fills. "
2305 "scheduled with mode %s. "
2306 "Promoted %u constants. "
2307 "Compacted %d to %d bytes (%.0f%%)\n",
2308 shader_name
, sha1buf
,
2309 dispatch_width
, before_size
/ 16,
2310 loop_count
, cfg
->cycle_count
,
2311 spill_count
, fill_count
,
2312 shader_stats
.scheduler_mode
,
2313 shader_stats
.promoted_constants
,
2314 before_size
, after_size
,
2315 100.0f
* (before_size
- after_size
) / before_size
);
2317 /* overriding the shader makes disasm_info invalid */
2318 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2319 dump_assembly(p
->store
, disasm_info
);
2321 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2324 ralloc_free(disasm_info
);
2327 compiler
->shader_debug_log(log_data
,
2328 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2329 "%d:%d spills:fills, "
2330 "scheduled with mode %s, "
2331 "Promoted %u constants, "
2332 "compacted %d to %d bytes.",
2333 _mesa_shader_stage_to_abbrev(stage
),
2334 dispatch_width
, before_size
/ 16,
2335 loop_count
, cfg
->cycle_count
,
2336 spill_count
, fill_count
,
2337 shader_stats
.scheduler_mode
,
2338 shader_stats
.promoted_constants
,
2339 before_size
, after_size
);
2341 stats
->dispatch_width
= dispatch_width
;
2342 stats
->instructions
= before_size
/ 16;
2343 stats
->loops
= loop_count
;
2344 stats
->cycles
= cfg
->cycle_count
;
2345 stats
->spills
= spill_count
;
2346 stats
->fills
= fill_count
;
2349 return start_offset
;
2353 fs_generator::get_assembly()
2355 return brw_get_program(p
, &prog_data
->program_size
);