2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 if (reg
->stride
> 4) {
94 assert(reg
!= &inst
->dst
);
95 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
96 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
97 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
99 const unsigned width
= MIN2(reg_width
, phys_width
);
100 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
101 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
104 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
105 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
106 * "Each DF (Double Float) operand uses an element size of 4 rather
107 * than 8 and all regioning parameters are twice what the values
108 * would be based on the true element size: ExecSize, Width,
109 * HorzStride, and VertStride. Each DF operand uses a pair of
110 * channels and all masking and swizzing should be adjusted
113 * From the IvyBridge PRM (Special Requirements for Handling Double
114 * Precision Data Types, page 71):
115 * "In Align1 mode, all regioning parameters like stride, execution
116 * size, and width must use the syntax of a pair of packed
117 * floats. The offsets for these data types must be 64-bit
118 * aligned. The execution size and regioning parameters are in terms
121 * Summarized: when handling DF-typed arguments, ExecSize,
122 * VertStride, and Width must be doubled.
124 * It applies to BayTrail too.
126 if (type_sz(reg
->type
) == 8) {
128 if (brw_reg
.vstride
> 0)
130 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
133 /* When converting from DF->F, we set the destination stride to 2
134 * because each d2f conversion implicitly writes 2 floats, being
135 * the first one the converted value. IVB/BYT actually writes two
136 * F components per SIMD channel, and every other component is
137 * filled with garbage.
139 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
140 type_sz(inst
->dst
.type
) < 8) {
141 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
147 brw_reg
= retype(brw_reg
, reg
->type
);
148 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
149 brw_reg
.abs
= reg
->abs
;
150 brw_reg
.negate
= reg
->negate
;
155 assert(reg
->offset
== 0);
156 brw_reg
= reg
->as_brw_reg();
159 /* Probably unused. */
160 brw_reg
= brw_null_reg();
164 unreachable("not reached");
167 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
168 * region, but on IVB and BYT DF regions must be programmed in terms of
169 * floats. A <0,2,1> region accomplishes this.
171 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
172 type_sz(reg
->type
) == 8 &&
173 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
174 brw_reg
.width
== BRW_WIDTH_1
&&
175 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
176 brw_reg
.width
= BRW_WIDTH_2
;
177 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
183 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
185 struct brw_stage_prog_data
*prog_data
,
186 struct shader_stats shader_stats
,
187 bool runtime_check_aads_emit
,
188 gl_shader_stage stage
)
190 : compiler(compiler
), log_data(log_data
),
191 devinfo(compiler
->devinfo
),
192 prog_data(prog_data
),
193 shader_stats(shader_stats
),
194 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
195 stage(stage
), mem_ctx(mem_ctx
)
197 p
= rzalloc(mem_ctx
, struct brw_codegen
);
198 brw_init_codegen(devinfo
, p
, mem_ctx
);
200 /* In the FS code generator, we are very careful to ensure that we always
201 * set the right execution size so we don't need the EU code to "help" us
202 * by trying to infer it. Sometimes, it infers the wrong thing.
204 p
->automatic_exec_sizes
= false;
207 fs_generator::~fs_generator()
211 class ip_record
: public exec_node
{
213 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
224 fs_generator::patch_discard_jumps_to_fb_writes()
226 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
229 int scale
= brw_jump_scale(p
->devinfo
);
231 /* There is a somewhat strange undocumented requirement of using
232 * HALT, according to the simulator. If some channel has HALTed to
233 * a particular UIP, then by the end of the program, every channel
234 * must have HALTed to that UIP. Furthermore, the tracking is a
235 * stack, so you can't do the final halt of a UIP after starting
236 * halting to a new UIP.
238 * Symptoms of not emitting this instruction on actual hardware
239 * included GPU hangs and sparkly rendering on the piglit discard
242 brw_inst
*last_halt
= gen6_HALT(p
);
243 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
244 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
248 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
249 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
251 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
252 /* HALT takes a half-instruction distance from the pre-incremented IP. */
253 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
256 this->discard_halt_patches
.make_empty();
261 fs_generator::generate_send(fs_inst
*inst
,
264 struct brw_reg ex_desc
,
265 struct brw_reg payload
,
266 struct brw_reg payload2
)
268 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
269 dst
.nr
== BRW_ARF_NULL
;
270 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
272 uint32_t desc_imm
= inst
->desc
|
273 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
275 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
277 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
278 /* If we have any sort of extended descriptor, then we need SENDS. This
279 * also covers the dual-payload case because ex_mlen goes in ex_desc.
281 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
282 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
285 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDSC
);
287 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
290 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
295 fs_generator::fire_fb_write(fs_inst
*inst
,
296 struct brw_reg payload
,
297 struct brw_reg implied_header
,
300 uint32_t msg_control
;
302 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
304 if (devinfo
->gen
< 6) {
305 brw_push_insn_state(p
);
306 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
307 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
308 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
309 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
310 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
311 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
312 brw_pop_insn_state(p
);
315 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
316 assert(inst
->group
== 0 && inst
->exec_size
== 16);
317 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
319 } else if (prog_data
->dual_src_blend
) {
320 assert(inst
->exec_size
== 8);
322 if (inst
->group
% 16 == 0)
323 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
324 else if (inst
->group
% 16 == 8)
325 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
327 unreachable("Invalid dual-source FB write instruction group");
330 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
332 if (inst
->exec_size
== 16)
333 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
334 else if (inst
->exec_size
== 8)
335 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
337 unreachable("Invalid FB write execution size");
340 /* We assume render targets start at 0, because headerless FB write
341 * messages set "Render Target Index" to 0. Using a different binding
342 * table index would make it impossible to use headerless messages.
344 const uint32_t surf_index
= inst
->target
;
346 brw_inst
*insn
= brw_fb_WRITE(p
,
348 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
355 inst
->header_size
!= 0);
357 if (devinfo
->gen
>= 6)
358 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
362 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
364 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
365 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
366 brw_set_default_flag_reg(p
, 0, 0);
369 const struct brw_reg implied_header
=
370 devinfo
->gen
< 6 ? payload
: brw_null_reg();
372 if (inst
->base_mrf
>= 0)
373 payload
= brw_message_reg(inst
->base_mrf
);
375 if (!runtime_check_aads_emit
) {
376 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
378 /* This can only happen in gen < 6 */
379 assert(devinfo
->gen
< 6);
381 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
383 /* Check runtime bit to detect if we have to send AA data or not */
384 brw_push_insn_state(p
);
385 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
386 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
389 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
391 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
393 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
394 brw_pop_insn_state(p
);
396 /* Don't send AA data */
397 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
399 brw_land_fwd_jump(p
, jmp
);
400 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
405 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
406 struct brw_reg payload
)
408 assert(inst
->size_written
% REG_SIZE
== 0);
409 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
410 /* We assume that render targets start at binding table index 0. */
411 const unsigned surf_index
= inst
->target
;
413 gen9_fb_READ(p
, dst
, payload
, surf_index
,
414 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
415 prog_data
->persample_dispatch
);
419 fs_generator::generate_mov_indirect(fs_inst
*inst
,
422 struct brw_reg indirect_byte_offset
)
424 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
425 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
426 assert(!reg
.abs
&& !reg
.negate
);
427 assert(reg
.type
== dst
.type
);
429 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
431 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
432 imm_byte_offset
+= indirect_byte_offset
.ud
;
434 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
435 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
436 brw_MOV(p
, dst
, reg
);
438 /* Prior to Broadwell, there are only 8 address registers. */
439 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
441 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
442 struct brw_reg addr
= vec8(brw_address_reg(0));
444 /* The destination stride of an instruction (in bytes) must be greater
445 * than or equal to the size of the rest of the instruction. Since the
446 * address register is of type UW, we can't use a D-type instruction.
447 * In order to get around this, re retype to UW and use a stride.
449 indirect_byte_offset
=
450 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
452 /* There are a number of reasons why we don't use the base offset here.
453 * One reason is that the field is only 9 bits which means we can only
454 * use it to access the first 16 GRFs. Also, from the Haswell PRM
455 * section "Register Region Restrictions":
457 * "The lower bits of the AddressImmediate must not overflow to
458 * change the register address. The lower 5 bits of Address
459 * Immediate when added to lower 5 bits of address register gives
460 * the sub-register offset. The upper bits of Address Immediate
461 * when added to upper bits of address register gives the register
462 * address. Any overflow from sub-register offset is dropped."
464 * Since the indirect may cause us to cross a register boundary, this
465 * makes the base offset almost useless. We could try and do something
466 * clever where we use a actual base offset if base_offset % 32 == 0 but
467 * that would mean we were generating different code depending on the
468 * base offset. Instead, for the sake of consistency, we'll just do the
469 * add ourselves. This restriction is only listed in the Haswell PRM
470 * but empirical testing indicates that it applies on all older
471 * generations and is lifted on Broadwell.
473 * In the end, while base_offset is nice to look at in the generated
474 * code, using it saves us 0 instructions and would require quite a bit
475 * of case-by-case work. It's just not worth it.
477 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
479 if (type_sz(reg
.type
) > 4 &&
480 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
481 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
482 !devinfo
->has_64bit_types
)) {
483 /* IVB has an issue (which we found empirically) where it reads two
484 * address register components per channel for indirectly addressed
487 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
489 * "When source or destination datatype is 64b or operation is
490 * integer DWord multiply, indirect addressing must not be used."
492 * To work around both of these, we do two integer MOVs insead of one
493 * 64-bit MOV. Because no double value should ever cross a register
494 * boundary, it's safe to use the immediate offset in the indirect
495 * here to handle adding 4 bytes to the offset and avoid the extra
496 * ADD to the register file.
498 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
499 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
500 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
501 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
503 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
505 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
507 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
508 !inst
->get_next()->is_tail_sentinel() &&
509 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
510 /* From the Sandybridge PRM:
512 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
513 * instruction that “indexed/indirect” source AND is followed
514 * by a send, the instruction requires a “Switch”. This is to
515 * avoid race condition where send may dispatch before MRF is
518 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
525 fs_generator::generate_shuffle(fs_inst
*inst
,
530 /* Ivy bridge has some strange behavior that makes this a real pain to
531 * implement for 64-bit values so we just don't bother.
533 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
535 /* Because we're using the address register, we're limited to 8-wide
536 * execution on gen7. On gen8, we're limited to 16-wide by the address
537 * register file and 8-wide for 64-bit types. We could try and make this
538 * instruction splittable higher up in the compiler but that gets weird
539 * because it reads all of the channels regardless of execution size. It's
540 * easier just to split it here.
542 const unsigned lower_width
=
543 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
544 8 : MIN2(16, inst
->exec_size
);
546 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
547 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
548 brw_set_default_group(p
, group
);
550 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
551 idx
.file
== BRW_IMMEDIATE_VALUE
) {
552 /* Trivial, the source is already uniform or the index is a constant.
553 * We will typically not get here if the optimizer is doing its job,
554 * but asserting would be mean.
556 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
557 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
559 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
560 struct brw_reg addr
= vec8(brw_address_reg(0));
562 struct brw_reg group_idx
= suboffset(idx
, group
);
564 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
565 /* Things get grumpy if the register is too wide. */
570 assert(type_sz(group_idx
.type
) <= 4);
571 if (type_sz(group_idx
.type
) == 4) {
572 /* The destination stride of an instruction (in bytes) must be
573 * greater than or equal to the size of the rest of the
574 * instruction. Since the address register is of type UW, we
575 * can't use a D-type instruction. In order to get around this,
576 * re retype to UW and use a stride.
578 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
581 /* Take into account the component size and horizontal stride. */
582 assert(src
.vstride
== src
.hstride
+ src
.width
);
583 brw_SHL(p
, addr
, group_idx
,
584 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
587 /* Add on the register start offset */
588 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
590 if (type_sz(src
.type
) > 4 &&
591 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
592 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
593 /* IVB has an issue (which we found empirically) where it reads
594 * two address register components per channel for indirectly
595 * addressed 64-bit sources.
597 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
599 * "When source or destination datatype is 64b or operation is
600 * integer DWord multiply, indirect addressing must not be
603 * To work around both of these, we do two integer MOVs insead of
604 * one 64-bit MOV. Because no double value should ever cross a
605 * register boundary, it's safe to use the immediate offset in the
606 * indirect here to handle adding 4 bytes to the offset and avoid
607 * the extra ADD to the register file.
609 struct brw_reg gdst
= suboffset(dst
, group
);
610 struct brw_reg dst_d
= retype(spread(gdst
, 2),
611 BRW_REGISTER_TYPE_D
);
613 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
614 brw_MOV(p
, byte_offset(dst_d
, 4),
615 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
617 brw_MOV(p
, suboffset(dst
, group
),
618 retype(brw_VxH_indirect(0, 0), src
.type
));
625 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
626 struct brw_reg dst
, struct brw_reg src
,
629 /* Requires a quad. */
630 assert(inst
->exec_size
>= 4);
632 if (src
.file
== BRW_IMMEDIATE_VALUE
||
633 has_scalar_region(src
)) {
634 /* The value is uniform across all channels */
635 brw_MOV(p
, dst
, src
);
637 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
638 /* This only works on 8-wide 32-bit values */
639 assert(inst
->exec_size
== 8);
640 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
641 assert(src
.vstride
== src
.width
+ 1);
642 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
643 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
644 swiz_src
.swizzle
= swiz
;
645 brw_MOV(p
, dst
, swiz_src
);
648 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
649 assert(src
.vstride
== src
.width
+ 1);
650 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
653 case BRW_SWIZZLE_XXXX
:
654 case BRW_SWIZZLE_YYYY
:
655 case BRW_SWIZZLE_ZZZZ
:
656 case BRW_SWIZZLE_WWWW
:
657 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
660 case BRW_SWIZZLE_XXZZ
:
661 case BRW_SWIZZLE_YYWW
:
662 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
665 case BRW_SWIZZLE_XYXY
:
666 case BRW_SWIZZLE_ZWZW
:
667 assert(inst
->exec_size
== 4);
668 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
672 assert(inst
->force_writemask_all
);
673 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
675 for (unsigned c
= 0; c
< 4; c
++) {
676 brw_inst
*insn
= brw_MOV(
677 p
, stride(suboffset(dst
, c
),
678 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
679 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
681 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
682 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
691 fs_generator::generate_urb_read(fs_inst
*inst
,
693 struct brw_reg header
)
695 assert(inst
->size_written
% REG_SIZE
== 0);
696 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
697 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
699 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
700 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
701 brw_set_src0(p
, send
, header
);
702 brw_set_src1(p
, send
, brw_imm_ud(0u));
704 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
705 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
707 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
708 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
710 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
711 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
712 brw_inst_set_header_present(p
->devinfo
, send
, true);
713 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
717 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
721 /* WaClearTDRRegBeforeEOTForNonPS.
723 * WA: Clear tdr register before send EOT in all non-PS shader kernels
725 * mov(8) tdr0:ud 0x0:ud {NoMask}"
727 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
728 brw_push_insn_state(p
);
729 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
730 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
731 brw_pop_insn_state(p
);
734 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
736 brw_set_dest(p
, insn
, brw_null_reg());
737 brw_set_src0(p
, insn
, payload
);
738 brw_set_src1(p
, insn
, brw_imm_ud(0u));
740 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
741 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
743 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
744 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
745 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
747 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
748 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
749 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
751 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
752 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
753 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
754 brw_inst_set_header_present(p
->devinfo
, insn
, true);
755 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
759 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
761 struct brw_inst
*insn
;
763 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
765 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
766 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
767 brw_set_src1(p
, insn
, brw_imm_ud(0u));
769 /* Terminate a compute shader by sending a message to the thread spawner.
771 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
772 brw_inst_set_mlen(devinfo
, insn
, 1);
773 brw_inst_set_rlen(devinfo
, insn
, 0);
774 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
775 brw_inst_set_header_present(devinfo
, insn
, false);
777 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
778 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
780 /* Note that even though the thread has a URB resource associated with it,
781 * we set the "do not dereference URB" bit, because the URB resource is
782 * managed by the fixed-function unit, so it will free it automatically.
784 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
786 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
790 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
797 fs_generator::generate_linterp(fs_inst
*inst
,
798 struct brw_reg dst
, struct brw_reg
*src
)
802 * -----------------------------------
803 * | src1+0 | src1+1 | src1+2 | src1+3 |
804 * |-----------------------------------|
805 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
806 * -----------------------------------
808 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
810 * -----------------------------------
811 * | src1+0 | src1+1 | src1+2 | src1+3 |
812 * |-----------------------------------|
813 * |(x0, x1)|(y0, y1)| | | in SIMD8
814 * |-----------------------------------|
815 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
816 * -----------------------------------
818 * See also: emit_interpolation_setup_gen4().
820 struct brw_reg delta_x
= src
[0];
821 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
822 struct brw_reg interp
= stride(src
[1], 0, 1, 0);
825 /* nir_lower_interpolation() will do the lowering to MAD instructions for
828 assert(devinfo
->gen
< 11);
830 if (devinfo
->has_pln
) {
831 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
832 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
834 * "[DevSNB]:<src1> must be even register aligned.
836 * This restriction is lifted on Ivy Bridge.
838 * This means that we need to split PLN into LINE+MAC on-the-fly.
839 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
840 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
841 * coordinate registers are laid out differently so we leave it as a
842 * SIMD16 instruction.
844 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
845 assert(inst
->group
% 16 == 0);
847 brw_push_insn_state(p
);
848 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
850 /* Thanks to two accumulators, we can emit all the LINEs and then all
851 * the MACs. This improves parallelism a bit.
853 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
854 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
855 offset(delta_x
, g
* 2));
856 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
858 /* LINE writes the accumulator automatically on gen4-5. On Sandy
859 * Bridge and later, we have to explicitly enable it.
861 if (devinfo
->gen
>= 6)
862 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
864 /* brw_set_default_saturate() is called before emitting
865 * instructions, so the saturate bit is set in each instruction,
866 * so we need to unset it on the LINE instructions.
868 brw_inst_set_saturate(p
->devinfo
, line
, false);
871 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
872 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
873 offset(delta_x
, g
* 2 + 1));
874 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
875 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
878 brw_pop_insn_state(p
);
882 brw_PLN(p
, dst
, interp
, delta_x
);
887 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
888 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
890 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
892 /* brw_set_default_saturate() is called before emitting instructions, so
893 * the saturate bit is set in each instruction, so we need to unset it on
894 * the first instruction.
896 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
903 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
906 struct brw_reg surf_index
)
908 assert(devinfo
->gen
>= 7);
909 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
914 switch (inst
->exec_size
) {
916 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
919 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
922 unreachable("Invalid width for texture instruction");
925 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
931 retype(dst
, BRW_REGISTER_TYPE_UW
),
936 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
937 rlen
, /* response length */
939 inst
->header_size
> 0,
941 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
945 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
946 struct brw_reg surface_index
,
947 struct brw_reg sampler_index
)
949 assert(devinfo
->gen
< 7);
950 assert(inst
->size_written
% REG_SIZE
== 0);
953 uint32_t return_format
;
955 /* Sampler EOT message of less than the dispatch width would kill the
956 * thread prematurely.
958 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
961 case BRW_REGISTER_TYPE_D
:
962 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
964 case BRW_REGISTER_TYPE_UD
:
965 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
968 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
972 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
973 * is set as part of the message descriptor. On gen4, the PRM seems to
974 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
975 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
976 * gone from the message descriptor entirely and you just get UINT32 all
977 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
978 * just stomp it to UINT32 all the time.
980 if (inst
->opcode
== SHADER_OPCODE_TXS
)
981 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
983 switch (inst
->exec_size
) {
985 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
988 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
991 unreachable("Invalid width for texture instruction");
994 if (devinfo
->gen
>= 5) {
995 switch (inst
->opcode
) {
996 case SHADER_OPCODE_TEX
:
997 if (inst
->shadow_compare
) {
998 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1000 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1004 if (inst
->shadow_compare
) {
1005 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1007 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1010 case SHADER_OPCODE_TXL
:
1011 if (inst
->shadow_compare
) {
1012 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1014 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1017 case SHADER_OPCODE_TXS
:
1018 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1020 case SHADER_OPCODE_TXD
:
1021 assert(!inst
->shadow_compare
);
1022 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1024 case SHADER_OPCODE_TXF
:
1025 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1027 case SHADER_OPCODE_TXF_CMS
:
1028 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1030 case SHADER_OPCODE_LOD
:
1031 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1033 case SHADER_OPCODE_TG4
:
1034 assert(devinfo
->gen
== 6);
1035 assert(!inst
->shadow_compare
);
1036 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1038 case SHADER_OPCODE_SAMPLEINFO
:
1039 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1042 unreachable("not reached");
1045 switch (inst
->opcode
) {
1046 case SHADER_OPCODE_TEX
:
1047 /* Note that G45 and older determines shadow compare and dispatch width
1048 * from message length for most messages.
1050 if (inst
->exec_size
== 8) {
1051 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1052 if (inst
->shadow_compare
) {
1053 assert(inst
->mlen
== 6);
1055 assert(inst
->mlen
<= 4);
1058 if (inst
->shadow_compare
) {
1059 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1060 assert(inst
->mlen
== 9);
1062 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1063 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1068 if (inst
->shadow_compare
) {
1069 assert(inst
->exec_size
== 8);
1070 assert(inst
->mlen
== 6);
1071 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1073 assert(inst
->mlen
== 9);
1074 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1075 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1078 case SHADER_OPCODE_TXL
:
1079 if (inst
->shadow_compare
) {
1080 assert(inst
->exec_size
== 8);
1081 assert(inst
->mlen
== 6);
1082 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1084 assert(inst
->mlen
== 9);
1085 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1086 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1089 case SHADER_OPCODE_TXD
:
1090 /* There is no sample_d_c message; comparisons are done manually */
1091 assert(inst
->exec_size
== 8);
1092 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1093 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1095 case SHADER_OPCODE_TXF
:
1096 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1097 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1098 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1100 case SHADER_OPCODE_TXS
:
1101 assert(inst
->mlen
== 3);
1102 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1103 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1106 unreachable("not reached");
1109 assert(msg_type
!= -1);
1111 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1115 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1117 /* Load the message header if present. If there's a texture offset,
1118 * we need to set it up explicitly and load the offset bitfield.
1119 * Otherwise, we can use an implied move from g0 to the first message reg.
1121 struct brw_reg src
= brw_null_reg();
1122 if (inst
->header_size
!= 0) {
1123 if (devinfo
->gen
< 6 && !inst
->offset
) {
1124 /* Set up an implied move from g0 to the MRF. */
1125 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1127 assert(inst
->base_mrf
!= -1);
1128 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1130 brw_push_insn_state(p
);
1131 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1132 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1133 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1134 /* Explicitly set up the message header by copying g0 to the MRF. */
1135 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1137 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1139 /* Set the offset bits in DWord 2. */
1140 brw_MOV(p
, get_element_ud(header_reg
, 2),
1141 brw_imm_ud(inst
->offset
));
1144 brw_pop_insn_state(p
);
1148 uint32_t base_binding_table_index
;
1149 switch (inst
->opcode
) {
1150 case SHADER_OPCODE_TG4
:
1151 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1154 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1158 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1159 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1162 retype(dst
, BRW_REGISTER_TYPE_UW
),
1165 surface_index
.ud
+ base_binding_table_index
,
1166 sampler_index
.ud
% 16,
1168 inst
->size_written
/ REG_SIZE
,
1170 inst
->header_size
!= 0,
1176 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1179 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1181 * Ideally, we want to produce:
1184 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1185 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1186 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1187 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1188 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1189 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1190 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1191 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1193 * and add another set of two more subspans if in 16-pixel dispatch mode.
1195 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1196 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1197 * pair. But the ideal approximation may impose a huge performance cost on
1198 * sample_d. On at least Haswell, sample_d instruction does some
1199 * optimizations if the same LOD is used for all pixels in the subspan.
1201 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1202 * appropriate swizzling.
1205 fs_generator::generate_ddx(const fs_inst
*inst
,
1206 struct brw_reg dst
, struct brw_reg src
)
1208 unsigned vstride
, width
;
1210 if (devinfo
->gen
>= 8) {
1211 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1212 /* produce accurate derivatives */
1213 vstride
= BRW_VERTICAL_STRIDE_2
;
1214 width
= BRW_WIDTH_2
;
1216 /* replicate the derivative at the top-left pixel to other pixels */
1217 vstride
= BRW_VERTICAL_STRIDE_4
;
1218 width
= BRW_WIDTH_4
;
1221 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1222 struct brw_reg src1
= src
;
1224 src0
.vstride
= vstride
;
1226 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1227 src1
.vstride
= vstride
;
1229 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1231 brw_ADD(p
, dst
, src0
, negate(src1
));
1233 /* On Haswell and earlier, the region used above appears to not work
1234 * correctly for compressed instructions. At least on Haswell and
1235 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1236 * would have to split to SIMD8 no matter which method we choose, we
1237 * may as well use ALIGN16 on all platforms gen7 and earlier.
1239 struct brw_reg src0
= stride(src
, 4, 4, 1);
1240 struct brw_reg src1
= stride(src
, 4, 4, 1);
1241 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1242 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1243 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1245 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1246 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1249 brw_push_insn_state(p
);
1250 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1251 brw_ADD(p
, dst
, negate(src0
), src1
);
1252 brw_pop_insn_state(p
);
1256 /* The negate_value boolean is used to negate the derivative computation for
1257 * FBOs, since they place the origin at the upper left instead of the lower
1261 fs_generator::generate_ddy(const fs_inst
*inst
,
1262 struct brw_reg dst
, struct brw_reg src
)
1264 const uint32_t type_size
= type_sz(src
.type
);
1266 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1267 /* produce accurate derivatives.
1269 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1270 * "Register Region Restrictions", Section "1. Special Restrictions":
1272 * "In Align16 mode, the channel selects and channel enables apply to
1273 * a pair of half-floats, because these parameters are defined for
1274 * DWord elements ONLY. This is applicable when both source and
1275 * destination are half-floats."
1277 * So for half-float operations we use the Gen11+ Align1 path. CHV
1278 * inherits its FP16 hardware from SKL, so it is not affected.
1280 if (devinfo
->gen
>= 11 ||
1281 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1282 src
= stride(src
, 0, 2, 1);
1284 brw_push_insn_state(p
);
1285 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1286 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1287 brw_set_default_group(p
, inst
->group
+ g
);
1288 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1289 negate(byte_offset(src
, g
* type_size
)),
1290 byte_offset(src
, (g
+ 2) * type_size
));
1292 brw_pop_insn_state(p
);
1294 struct brw_reg src0
= stride(src
, 4, 4, 1);
1295 struct brw_reg src1
= stride(src
, 4, 4, 1);
1296 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1297 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1299 brw_push_insn_state(p
);
1300 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1301 brw_ADD(p
, dst
, negate(src0
), src1
);
1302 brw_pop_insn_state(p
);
1305 /* replicate the derivative at the top-left pixel to other pixels */
1306 if (devinfo
->gen
>= 8) {
1307 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1308 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1310 brw_ADD(p
, dst
, negate(src0
), src1
);
1312 /* On Haswell and earlier, the region used above appears to not work
1313 * correctly for compressed instructions. At least on Haswell and
1314 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1315 * would have to split to SIMD8 no matter which method we choose, we
1316 * may as well use ALIGN16 on all platforms gen7 and earlier.
1318 struct brw_reg src0
= stride(src
, 4, 4, 1);
1319 struct brw_reg src1
= stride(src
, 4, 4, 1);
1320 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1321 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1323 brw_push_insn_state(p
);
1324 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1325 brw_ADD(p
, dst
, negate(src0
), src1
);
1326 brw_pop_insn_state(p
);
1332 fs_generator::generate_discard_jump(fs_inst
*)
1334 assert(devinfo
->gen
>= 6);
1336 /* This HALT will be patched up at FB write time to point UIP at the end of
1337 * the program, and at brw_uip_jip() JIP will be set to the end of the
1338 * current block (or the program).
1340 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1345 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1347 /* The 32-wide messages only respect the first 16-wide half of the channel
1348 * enable signals which are replicated identically for the second group of
1349 * 16 channels, so we cannot use them unless the write is marked
1350 * force_writemask_all.
1352 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1353 MIN2(16, inst
->exec_size
);
1354 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1355 assert(inst
->mlen
!= 0);
1357 brw_push_insn_state(p
);
1358 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1359 brw_set_default_compression(p
, lower_size
> 8);
1361 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1362 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1364 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1365 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1367 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1369 inst
->offset
+ block_size
* REG_SIZE
* i
);
1372 brw_pop_insn_state(p
);
1376 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1378 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1379 assert(inst
->mlen
!= 0);
1381 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1382 inst
->exec_size
/ 8, inst
->offset
);
1386 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1388 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1390 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1394 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1396 struct brw_reg index
,
1397 struct brw_reg offset
)
1399 assert(type_sz(dst
.type
) == 4);
1400 assert(inst
->mlen
!= 0);
1402 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1403 index
.type
== BRW_REGISTER_TYPE_UD
);
1404 uint32_t surf_index
= index
.ud
;
1406 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1407 offset
.type
== BRW_REGISTER_TYPE_UD
);
1408 uint32_t read_offset
= offset
.ud
;
1410 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1411 read_offset
, surf_index
);
1415 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1417 struct brw_reg index
,
1418 struct brw_reg payload
)
1420 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1421 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1422 assert(type_sz(dst
.type
) == 4);
1424 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1425 const uint32_t surf_index
= index
.ud
;
1427 brw_push_insn_state(p
);
1428 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1429 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1430 brw_pop_insn_state(p
);
1432 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1433 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1434 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1435 brw_set_desc(p
, send
,
1436 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1438 brw_dp_read_desc(devinfo
, surf_index
,
1439 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1440 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1441 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1444 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1446 brw_push_insn_state(p
);
1447 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1449 /* a0.0 = surf_index & 0xff */
1450 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1451 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1452 brw_set_dest(p
, insn_and
, addr
);
1453 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1454 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1456 /* dst = send(payload, a0.0 | <descriptor>) */
1457 brw_send_indirect_message(
1458 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1459 retype(dst
, BRW_REGISTER_TYPE_UD
),
1460 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1461 brw_message_desc(devinfo
, 1,
1462 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1463 brw_dp_read_desc(devinfo
, 0 /* surface */,
1464 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1465 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1466 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1469 brw_pop_insn_state(p
);
1474 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1476 struct brw_reg index
)
1478 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1479 assert(inst
->header_size
!= 0);
1482 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1483 index
.type
== BRW_REGISTER_TYPE_UD
);
1484 uint32_t surf_index
= index
.ud
;
1486 uint32_t simd_mode
, rlen
, msg_type
;
1487 if (inst
->exec_size
== 16) {
1488 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1491 assert(inst
->exec_size
== 8);
1492 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1496 if (devinfo
->gen
>= 5)
1497 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1499 /* We always use the SIMD16 message so that we only have to load U, and
1502 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1503 assert(inst
->mlen
== 3);
1504 assert(inst
->size_written
== 8 * REG_SIZE
);
1506 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1509 struct brw_reg header
= brw_vec8_grf(0, 0);
1510 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1512 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1513 brw_inst_set_compression(devinfo
, send
, false);
1514 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1515 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1516 brw_set_src0(p
, send
, header
);
1517 if (devinfo
->gen
< 6)
1518 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1520 /* Our surface is set up as floats, regardless of what actual data is
1523 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1524 brw_set_desc(p
, send
,
1525 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1526 brw_sampler_desc(devinfo
, surf_index
,
1527 0, /* sampler (unused) */
1528 msg_type
, simd_mode
, return_format
));
1532 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1535 struct brw_reg msg_data
,
1538 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1539 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1540 assert(inst
->size_written
% REG_SIZE
== 0);
1542 brw_pixel_interpolator_query(p
,
1543 retype(dst
, BRW_REGISTER_TYPE_UW
),
1544 /* If we don't have a payload, what we send doesn't matter */
1545 has_payload
? src
: brw_vec8_grf(0, 0),
1546 inst
->pi_noperspective
,
1549 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1550 inst
->size_written
/ REG_SIZE
);
1553 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1554 * the ADD instruction.
1557 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1559 struct brw_reg src0
,
1560 struct brw_reg src1
)
1562 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1563 dst
.type
== BRW_REGISTER_TYPE_UD
);
1564 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1565 src0
.type
== BRW_REGISTER_TYPE_UD
);
1567 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1568 const unsigned lower_size
= MIN2(inst
->exec_size
,
1569 devinfo
->gen
>= 8 ? 16 : 8);
1571 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1572 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1573 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1574 (i
* lower_size
/ (1 << src0
.width
))) *
1575 type_sz(src0
.type
) / REG_SIZE
),
1576 suboffset(reg
, i
* lower_size
/ 4));
1577 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1578 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1579 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1584 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1589 assert(devinfo
->gen
>= 7);
1590 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1591 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1592 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1594 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1596 * Because this instruction does not have a 16-bit floating-point type,
1597 * the destination data type must be Word (W).
1599 * The destination must be DWord-aligned and specify a horizontal stride
1600 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1601 * each destination channel and the upper word is not modified.
1603 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1605 /* Give each 32-bit channel of dst the form below, where "." means
1609 brw_F32TO16(p
, dst_w
, y
);
1614 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1616 /* And, finally the form of packHalf2x16's output:
1619 brw_F32TO16(p
, dst_w
, x
);
1623 fs_generator::generate_shader_time_add(fs_inst
*,
1624 struct brw_reg payload
,
1625 struct brw_reg offset
,
1626 struct brw_reg value
)
1628 assert(devinfo
->gen
>= 7);
1629 brw_push_insn_state(p
);
1630 brw_set_default_mask_control(p
, true);
1632 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1633 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1635 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1638 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1639 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1640 value
.width
= BRW_WIDTH_1
;
1641 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1642 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1644 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1647 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1648 * case, and we don't really care about squeezing every bit of performance
1649 * out of this path, so we just emit the MOVs from here.
1651 brw_MOV(p
, payload_offset
, offset
);
1652 brw_MOV(p
, payload_value
, value
);
1653 brw_shader_time_add(p
, payload
,
1654 prog_data
->binding_table
.shader_time_start
);
1655 brw_pop_insn_state(p
);
1659 fs_generator::enable_debug(const char *shader_name
)
1662 this->shader_name
= shader_name
;
1666 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1668 /* align to 64 byte boundary. */
1669 while (p
->next_insn_offset
% 64)
1672 this->dispatch_width
= dispatch_width
;
1674 int start_offset
= p
->next_insn_offset
;
1675 int spill_count
= 0, fill_count
= 0;
1678 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1680 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1681 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1684 struct brw_reg src
[4], dst
;
1685 unsigned int last_insn_offset
= p
->next_insn_offset
;
1686 bool multiple_instructions_emitted
= false;
1688 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1689 * "Register Region Restrictions" section: for BDW, SKL:
1691 * "A POW/FDIV operation must not be followed by an instruction
1692 * that requires two destination registers."
1694 * The documentation is often lacking annotations for Atom parts,
1695 * and empirically this affects CHV as well.
1697 if (devinfo
->gen
>= 8 &&
1698 devinfo
->gen
<= 9 &&
1700 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1701 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1702 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1704 last_insn_offset
= p
->next_insn_offset
;
1707 if (unlikely(debug_flag
))
1708 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1710 /* If the instruction writes to more than one register, it needs to be
1711 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1712 * hardware figures out by itself what the right compression mode is,
1713 * but we still need to know whether the instruction is compressed to
1714 * set up the source register regions appropriately.
1716 * XXX - This is wrong for instructions that write a single register but
1717 * read more than one which should strictly speaking be treated as
1718 * compressed. For instructions that don't write any registers it
1719 * relies on the destination being a null register of the correct
1720 * type and regioning so the instruction is considered compressed
1721 * or not accordingly.
1723 const bool compressed
=
1724 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1725 brw_set_default_compression(p
, compressed
);
1726 brw_set_default_group(p
, inst
->group
);
1728 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1729 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1730 &inst
->src
[i
], compressed
);
1731 /* The accumulator result appears to get used for the
1732 * conditional modifier generation. When negating a UD
1733 * value, there is a 33rd bit generated for the sign in the
1734 * accumulator value, so now you can't check, for example,
1735 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1737 assert(!inst
->conditional_mod
||
1738 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1739 !inst
->src
[i
].negate
);
1741 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1742 &inst
->dst
, compressed
);
1744 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1745 brw_set_default_predicate_control(p
, inst
->predicate
);
1746 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1747 /* On gen7 and above, hardware automatically adds the group onto the
1748 * flag subregister number. On Sandy Bridge and older, we have to do it
1751 const unsigned flag_subreg
= inst
->flag_subreg
+
1752 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1753 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1754 brw_set_default_saturate(p
, inst
->saturate
);
1755 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1756 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1758 unsigned exec_size
= inst
->exec_size
;
1759 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1760 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1764 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1766 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1767 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1768 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1769 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1771 switch (inst
->opcode
) {
1772 case BRW_OPCODE_MOV
:
1773 brw_MOV(p
, dst
, src
[0]);
1775 case BRW_OPCODE_ADD
:
1776 brw_ADD(p
, dst
, src
[0], src
[1]);
1778 case BRW_OPCODE_MUL
:
1779 brw_MUL(p
, dst
, src
[0], src
[1]);
1781 case BRW_OPCODE_AVG
:
1782 brw_AVG(p
, dst
, src
[0], src
[1]);
1784 case BRW_OPCODE_MACH
:
1785 brw_MACH(p
, dst
, src
[0], src
[1]);
1788 case BRW_OPCODE_LINE
:
1789 brw_LINE(p
, dst
, src
[0], src
[1]);
1792 case BRW_OPCODE_MAD
:
1793 assert(devinfo
->gen
>= 6);
1794 if (devinfo
->gen
< 10)
1795 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1796 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1799 case BRW_OPCODE_LRP
:
1800 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1801 if (devinfo
->gen
< 10)
1802 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1803 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1806 case BRW_OPCODE_FRC
:
1807 brw_FRC(p
, dst
, src
[0]);
1809 case BRW_OPCODE_RNDD
:
1810 brw_RNDD(p
, dst
, src
[0]);
1812 case BRW_OPCODE_RNDE
:
1813 brw_RNDE(p
, dst
, src
[0]);
1815 case BRW_OPCODE_RNDZ
:
1816 brw_RNDZ(p
, dst
, src
[0]);
1819 case BRW_OPCODE_AND
:
1820 brw_AND(p
, dst
, src
[0], src
[1]);
1823 brw_OR(p
, dst
, src
[0], src
[1]);
1825 case BRW_OPCODE_XOR
:
1826 brw_XOR(p
, dst
, src
[0], src
[1]);
1828 case BRW_OPCODE_NOT
:
1829 brw_NOT(p
, dst
, src
[0]);
1831 case BRW_OPCODE_ASR
:
1832 brw_ASR(p
, dst
, src
[0], src
[1]);
1834 case BRW_OPCODE_SHR
:
1835 brw_SHR(p
, dst
, src
[0], src
[1]);
1837 case BRW_OPCODE_SHL
:
1838 brw_SHL(p
, dst
, src
[0], src
[1]);
1840 case BRW_OPCODE_ROL
:
1841 assert(devinfo
->gen
>= 11);
1842 assert(src
[0].type
== dst
.type
);
1843 brw_ROL(p
, dst
, src
[0], src
[1]);
1845 case BRW_OPCODE_ROR
:
1846 assert(devinfo
->gen
>= 11);
1847 assert(src
[0].type
== dst
.type
);
1848 brw_ROR(p
, dst
, src
[0], src
[1]);
1850 case BRW_OPCODE_F32TO16
:
1851 assert(devinfo
->gen
>= 7);
1852 brw_F32TO16(p
, dst
, src
[0]);
1854 case BRW_OPCODE_F16TO32
:
1855 assert(devinfo
->gen
>= 7);
1856 brw_F16TO32(p
, dst
, src
[0]);
1858 case BRW_OPCODE_CMP
:
1859 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1860 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1861 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1862 * implemented in the compiler is not sufficient. Overriding the
1863 * type when the destination is the null register is necessary but
1864 * not sufficient by itself.
1866 assert(dst
.nr
== BRW_ARF_NULL
);
1867 dst
.type
= BRW_REGISTER_TYPE_D
;
1869 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1871 case BRW_OPCODE_SEL
:
1872 brw_SEL(p
, dst
, src
[0], src
[1]);
1874 case BRW_OPCODE_CSEL
:
1875 assert(devinfo
->gen
>= 8);
1876 if (devinfo
->gen
< 10)
1877 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1878 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1880 case BRW_OPCODE_BFREV
:
1881 assert(devinfo
->gen
>= 7);
1882 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1883 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1885 case BRW_OPCODE_FBH
:
1886 assert(devinfo
->gen
>= 7);
1887 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1889 case BRW_OPCODE_FBL
:
1890 assert(devinfo
->gen
>= 7);
1891 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1892 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1894 case BRW_OPCODE_LZD
:
1895 brw_LZD(p
, dst
, src
[0]);
1897 case BRW_OPCODE_CBIT
:
1898 assert(devinfo
->gen
>= 7);
1899 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1900 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1902 case BRW_OPCODE_ADDC
:
1903 assert(devinfo
->gen
>= 7);
1904 brw_ADDC(p
, dst
, src
[0], src
[1]);
1906 case BRW_OPCODE_SUBB
:
1907 assert(devinfo
->gen
>= 7);
1908 brw_SUBB(p
, dst
, src
[0], src
[1]);
1910 case BRW_OPCODE_MAC
:
1911 brw_MAC(p
, dst
, src
[0], src
[1]);
1914 case BRW_OPCODE_BFE
:
1915 assert(devinfo
->gen
>= 7);
1916 if (devinfo
->gen
< 10)
1917 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1918 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1921 case BRW_OPCODE_BFI1
:
1922 assert(devinfo
->gen
>= 7);
1923 brw_BFI1(p
, dst
, src
[0], src
[1]);
1925 case BRW_OPCODE_BFI2
:
1926 assert(devinfo
->gen
>= 7);
1927 if (devinfo
->gen
< 10)
1928 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1929 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1933 if (inst
->src
[0].file
!= BAD_FILE
) {
1934 /* The instruction has an embedded compare (only allowed on gen6) */
1935 assert(devinfo
->gen
== 6);
1936 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1938 brw_IF(p
, brw_get_default_exec_size(p
));
1942 case BRW_OPCODE_ELSE
:
1945 case BRW_OPCODE_ENDIF
:
1950 brw_DO(p
, brw_get_default_exec_size(p
));
1953 case BRW_OPCODE_BREAK
:
1956 case BRW_OPCODE_CONTINUE
:
1960 case BRW_OPCODE_WHILE
:
1965 case SHADER_OPCODE_RCP
:
1966 case SHADER_OPCODE_RSQ
:
1967 case SHADER_OPCODE_SQRT
:
1968 case SHADER_OPCODE_EXP2
:
1969 case SHADER_OPCODE_LOG2
:
1970 case SHADER_OPCODE_SIN
:
1971 case SHADER_OPCODE_COS
:
1972 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1973 if (devinfo
->gen
>= 6) {
1974 assert(inst
->mlen
== 0);
1975 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1976 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1977 src
[0], brw_null_reg());
1979 assert(inst
->mlen
>= 1);
1980 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1982 brw_math_function(inst
->opcode
),
1983 inst
->base_mrf
, src
[0],
1984 BRW_MATH_PRECISION_FULL
);
1987 case SHADER_OPCODE_INT_QUOTIENT
:
1988 case SHADER_OPCODE_INT_REMAINDER
:
1989 case SHADER_OPCODE_POW
:
1990 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1991 if (devinfo
->gen
>= 6) {
1992 assert(inst
->mlen
== 0);
1993 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1994 inst
->exec_size
== 8);
1995 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1997 assert(inst
->mlen
>= 1);
1998 assert(inst
->exec_size
== 8);
1999 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2000 inst
->base_mrf
, src
[0],
2001 BRW_MATH_PRECISION_FULL
);
2004 case FS_OPCODE_LINTERP
:
2005 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2007 case FS_OPCODE_PIXEL_X
:
2008 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2009 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2010 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2012 case FS_OPCODE_PIXEL_Y
:
2013 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2014 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2015 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2018 case SHADER_OPCODE_SEND
:
2019 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2020 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2023 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2024 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2026 case SHADER_OPCODE_TEX
:
2028 case SHADER_OPCODE_TXD
:
2029 case SHADER_OPCODE_TXF
:
2030 case SHADER_OPCODE_TXF_CMS
:
2031 case SHADER_OPCODE_TXL
:
2032 case SHADER_OPCODE_TXS
:
2033 case SHADER_OPCODE_LOD
:
2034 case SHADER_OPCODE_TG4
:
2035 case SHADER_OPCODE_SAMPLEINFO
:
2036 assert(inst
->src
[0].file
== BAD_FILE
);
2037 generate_tex(inst
, dst
, src
[1], src
[2]);
2040 case FS_OPCODE_DDX_COARSE
:
2041 case FS_OPCODE_DDX_FINE
:
2042 generate_ddx(inst
, dst
, src
[0]);
2044 case FS_OPCODE_DDY_COARSE
:
2045 case FS_OPCODE_DDY_FINE
:
2046 generate_ddy(inst
, dst
, src
[0]);
2049 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2050 generate_scratch_write(inst
, src
[0]);
2054 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2055 generate_scratch_read(inst
, dst
);
2059 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2060 generate_scratch_read_gen7(inst
, dst
);
2064 case SHADER_OPCODE_MOV_INDIRECT
:
2065 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2068 case SHADER_OPCODE_URB_READ_SIMD8
:
2069 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2070 generate_urb_read(inst
, dst
, src
[0]);
2073 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2074 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2075 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2076 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2077 generate_urb_write(inst
, src
[0]);
2080 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2081 assert(inst
->force_writemask_all
);
2082 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2085 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2086 assert(inst
->force_writemask_all
);
2087 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2090 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2091 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2094 case FS_OPCODE_REP_FB_WRITE
:
2095 case FS_OPCODE_FB_WRITE
:
2096 generate_fb_write(inst
, src
[0]);
2099 case FS_OPCODE_FB_READ
:
2100 generate_fb_read(inst
, dst
, src
[0]);
2103 case FS_OPCODE_DISCARD_JUMP
:
2104 generate_discard_jump(inst
);
2107 case SHADER_OPCODE_SHADER_TIME_ADD
:
2108 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2111 case SHADER_OPCODE_MEMORY_FENCE
:
2112 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2113 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2114 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2117 case SHADER_OPCODE_INTERLOCK
:
2118 assert(devinfo
->gen
>= 9);
2119 /* The interlock is basically a memory fence issued via sendc */
2120 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2123 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2124 const struct brw_reg mask
=
2125 brw_stage_has_packed_dispatch(devinfo
, stage
,
2126 prog_data
) ? brw_imm_ud(~0u) :
2127 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2129 brw_find_live_channel(p
, dst
, mask
);
2133 case SHADER_OPCODE_BROADCAST
:
2134 assert(inst
->force_writemask_all
);
2135 brw_broadcast(p
, dst
, src
[0], src
[1]);
2138 case SHADER_OPCODE_SHUFFLE
:
2139 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2142 case SHADER_OPCODE_SEL_EXEC
:
2143 assert(inst
->force_writemask_all
);
2144 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2145 brw_MOV(p
, dst
, src
[1]);
2146 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2147 brw_MOV(p
, dst
, src
[0]);
2150 case SHADER_OPCODE_QUAD_SWIZZLE
:
2151 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2152 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2153 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2156 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2157 assert(src
[0].type
== dst
.type
);
2158 assert(!src
[0].negate
&& !src
[0].abs
);
2159 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2160 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2161 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2162 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2163 const unsigned component
= src
[1].ud
;
2164 const unsigned cluster_size
= src
[2].ud
;
2165 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2166 cluster_size
, cluster_size
, 0);
2167 if (type_sz(src
[0].type
) > 4 &&
2168 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2169 /* IVB has an issue (which we found empirically) where it reads
2170 * two address register components per channel for indirectly
2171 * addressed 64-bit sources.
2173 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2175 * "When source or destination datatype is 64b or operation is
2176 * integer DWord multiply, indirect addressing must not be
2179 * To work around both of these, we do two integer MOVs insead of
2180 * one 64-bit MOV. Because no double value should ever cross a
2181 * register boundary, it's safe to use the immediate offset in the
2182 * indirect here to handle adding 4 bytes to the offset and avoid
2183 * the extra ADD to the register file.
2185 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2186 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2187 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2188 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2190 brw_MOV(p
, dst
, strided
);
2195 case FS_OPCODE_SET_SAMPLE_ID
:
2196 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2199 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2200 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2203 case FS_OPCODE_PLACEHOLDER_HALT
:
2204 /* This is the place where the final HALT needs to be inserted if
2205 * we've emitted any discards. If not, this will emit no code.
2207 if (!patch_discard_jumps_to_fb_writes()) {
2208 if (unlikely(debug_flag
)) {
2209 disasm_info
->use_tail
= true;
2214 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2215 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2216 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2219 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2220 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2221 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2224 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2225 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2226 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2229 case CS_OPCODE_CS_TERMINATE
:
2230 generate_cs_terminate(inst
, src
[0]);
2233 case SHADER_OPCODE_BARRIER
:
2234 generate_barrier(inst
, src
[0]);
2237 case BRW_OPCODE_DIM
:
2238 assert(devinfo
->is_haswell
);
2239 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2240 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2241 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2244 case SHADER_OPCODE_RND_MODE
:
2245 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2246 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2250 unreachable("Unsupported opcode");
2252 case SHADER_OPCODE_LOAD_PAYLOAD
:
2253 unreachable("Should be lowered by lower_load_payload()");
2256 if (multiple_instructions_emitted
)
2259 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2260 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2261 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2262 "emitting more than 1 instruction");
2264 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2266 if (inst
->conditional_mod
)
2267 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2268 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2269 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2273 brw_set_uip_jip(p
, start_offset
);
2275 /* end of program sentinel */
2276 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2281 if (unlikely(debug_flag
))
2283 brw_validate_instructions(devinfo
, p
->store
,
2285 p
->next_insn_offset
,
2288 int before_size
= p
->next_insn_offset
- start_offset
;
2289 brw_compact_instructions(p
, start_offset
, disasm_info
);
2290 int after_size
= p
->next_insn_offset
- start_offset
;
2292 if (unlikely(debug_flag
)) {
2293 fprintf(stderr
, "Native code for %s\n"
2294 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2295 "%d:%d spills:fills. "
2296 "scheduled with mode %s. "
2297 "Promoted %u constants. "
2298 "Compacted %d to %d bytes (%.0f%%)\n",
2299 shader_name
, dispatch_width
, before_size
/ 16,
2300 loop_count
, cfg
->cycle_count
,
2301 spill_count
, fill_count
,
2302 shader_stats
.scheduler_mode
,
2303 shader_stats
.promoted_constants
,
2304 before_size
, after_size
,
2305 100.0f
* (before_size
- after_size
) / before_size
);
2307 dump_assembly(p
->store
, disasm_info
);
2309 ralloc_free(disasm_info
);
2312 compiler
->shader_debug_log(log_data
,
2313 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2314 "%d:%d spills:fills, "
2315 "scheduled with mode %s, "
2316 "Promoted %u constants, "
2317 "compacted %d to %d bytes.",
2318 _mesa_shader_stage_to_abbrev(stage
),
2319 dispatch_width
, before_size
/ 16,
2320 loop_count
, cfg
->cycle_count
,
2321 spill_count
, fill_count
,
2322 shader_stats
.scheduler_mode
,
2323 shader_stats
.promoted_constants
,
2324 before_size
, after_size
);
2326 return start_offset
;
2330 fs_generator::get_assembly()
2332 return brw_get_program(p
, &prog_data
->program_size
);