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intel/fs: Add explicit last_rt flag to fb writes orthogonal to eot.
[mesa.git] / src / intel / compiler / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg *reg)
36 {
37 switch (reg->file) {
38 case ARF:
39 return BRW_ARCHITECTURE_REGISTER_FILE;
40 case FIXED_GRF:
41 case VGRF:
42 return BRW_GENERAL_REGISTER_FILE;
43 case MRF:
44 return BRW_MESSAGE_REGISTER_FILE;
45 case IMM:
46 return BRW_IMMEDIATE_VALUE;
47 case BAD_FILE:
48 case ATTR:
49 case UNIFORM:
50 unreachable("not reached");
51 }
52 return BRW_ARCHITECTURE_REGISTER_FILE;
53 }
54
55 static struct brw_reg
56 brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
57 fs_reg *reg, bool compressed)
58 {
59 struct brw_reg brw_reg;
60
61 switch (reg->file) {
62 case MRF:
63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
64 /* Fallthrough */
65 case VGRF:
66 if (reg->stride == 0) {
67 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
68 } else {
69 /* From the Haswell PRM:
70 *
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
73 * boundaries."
74 *
75 * The maximum width value that could satisfy this restriction is:
76 */
77 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type));
78
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
83 */
84 const unsigned phys_width = compressed ? inst->exec_size / 2 :
85 inst->exec_size;
86
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
92 */
93 const unsigned width = MIN2(reg_width, phys_width);
94 brw_reg = brw_vecn_reg(width, brw_file_from_reg(reg), reg->nr, 0);
95 brw_reg = stride(brw_reg, width * reg->stride, width, reg->stride);
96
97 if (devinfo->gen == 7 && !devinfo->is_haswell) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
104 * appropriately."
105 *
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
112 * of floats."
113 *
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
116 *
117 * It applies to BayTrail too.
118 */
119 if (type_sz(reg->type) == 8) {
120 brw_reg.width++;
121 if (brw_reg.vstride > 0)
122 brw_reg.vstride++;
123 assert(brw_reg.hstride == BRW_HORIZONTAL_STRIDE_1);
124 }
125
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
131 */
132 if (reg == &inst->dst && get_exec_type_size(inst) == 8 &&
133 type_sz(inst->dst.type) < 8) {
134 assert(brw_reg.hstride > BRW_HORIZONTAL_STRIDE_1);
135 brw_reg.hstride--;
136 }
137 }
138 }
139
140 brw_reg = retype(brw_reg, reg->type);
141 brw_reg = byte_offset(brw_reg, reg->offset);
142 brw_reg.abs = reg->abs;
143 brw_reg.negate = reg->negate;
144 break;
145 case ARF:
146 case FIXED_GRF:
147 case IMM:
148 assert(reg->offset == 0);
149 brw_reg = reg->as_brw_reg();
150 break;
151 case BAD_FILE:
152 /* Probably unused. */
153 brw_reg = brw_null_reg();
154 break;
155 case ATTR:
156 case UNIFORM:
157 unreachable("not reached");
158 }
159
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
163 */
164 if (devinfo->gen == 7 && !devinfo->is_haswell &&
165 type_sz(reg->type) == 8 &&
166 brw_reg.vstride == BRW_VERTICAL_STRIDE_0 &&
167 brw_reg.width == BRW_WIDTH_1 &&
168 brw_reg.hstride == BRW_HORIZONTAL_STRIDE_0) {
169 brw_reg.width = BRW_WIDTH_2;
170 brw_reg.hstride = BRW_HORIZONTAL_STRIDE_1;
171 }
172
173 return brw_reg;
174 }
175
176 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
177 void *mem_ctx,
178 const void *key,
179 struct brw_stage_prog_data *prog_data,
180 unsigned promoted_constants,
181 bool runtime_check_aads_emit,
182 gl_shader_stage stage)
183
184 : compiler(compiler), log_data(log_data),
185 devinfo(compiler->devinfo), key(key),
186 prog_data(prog_data),
187 promoted_constants(promoted_constants),
188 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
189 stage(stage), mem_ctx(mem_ctx)
190 {
191 p = rzalloc(mem_ctx, struct brw_codegen);
192 brw_init_codegen(devinfo, p, mem_ctx);
193
194 /* In the FS code generator, we are very careful to ensure that we always
195 * set the right execution size so we don't need the EU code to "help" us
196 * by trying to infer it. Sometimes, it infers the wrong thing.
197 */
198 p->automatic_exec_sizes = false;
199 }
200
201 fs_generator::~fs_generator()
202 {
203 }
204
205 class ip_record : public exec_node {
206 public:
207 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
208
209 ip_record(int ip)
210 {
211 this->ip = ip;
212 }
213
214 int ip;
215 };
216
217 bool
218 fs_generator::patch_discard_jumps_to_fb_writes()
219 {
220 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
221 return false;
222
223 int scale = brw_jump_scale(p->devinfo);
224
225 /* There is a somewhat strange undocumented requirement of using
226 * HALT, according to the simulator. If some channel has HALTed to
227 * a particular UIP, then by the end of the program, every channel
228 * must have HALTed to that UIP. Furthermore, the tracking is a
229 * stack, so you can't do the final halt of a UIP after starting
230 * halting to a new UIP.
231 *
232 * Symptoms of not emitting this instruction on actual hardware
233 * included GPU hangs and sparkly rendering on the piglit discard
234 * tests.
235 */
236 brw_inst *last_halt = gen6_HALT(p);
237 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
238 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
239
240 int ip = p->nr_insn;
241
242 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
243 brw_inst *patch = &p->store[patch_ip->ip];
244
245 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
246 /* HALT takes a half-instruction distance from the pre-incremented IP. */
247 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
248 }
249
250 this->discard_halt_patches.make_empty();
251 return true;
252 }
253
254 void
255 fs_generator::fire_fb_write(fs_inst *inst,
256 struct brw_reg payload,
257 struct brw_reg implied_header,
258 GLuint nr)
259 {
260 uint32_t msg_control;
261
262 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
263
264 if (devinfo->gen < 6) {
265 brw_push_insn_state(p);
266 brw_set_default_exec_size(p, BRW_EXECUTE_8);
267 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
268 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
269 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
270 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
271 brw_pop_insn_state(p);
272 }
273
274 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
275 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
276 else if (prog_data->dual_src_blend) {
277 if (!inst->group)
278 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
279 else
280 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
281 } else if (inst->exec_size == 16)
282 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
283 else
284 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
285
286 /* We assume render targets start at 0, because headerless FB write
287 * messages set "Render Target Index" to 0. Using a different binding
288 * table index would make it impossible to use headerless messages.
289 */
290 const uint32_t surf_index = inst->target;
291
292 brw_fb_WRITE(p,
293 payload,
294 implied_header,
295 msg_control,
296 surf_index,
297 nr,
298 0,
299 inst->eot,
300 inst->last_rt,
301 inst->header_size != 0);
302
303 brw_mark_surface_used(&prog_data->base, surf_index);
304 }
305
306 void
307 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
308 {
309 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
310 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
311 struct brw_reg implied_header;
312
313 if (devinfo->gen < 8 && !devinfo->is_haswell) {
314 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
315 }
316
317 if (inst->base_mrf >= 0)
318 payload = brw_message_reg(inst->base_mrf);
319
320 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
321 * move, here's g1.
322 */
323 if (inst->header_size != 0) {
324 brw_push_insn_state(p);
325 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
326 brw_set_default_exec_size(p, BRW_EXECUTE_1);
327 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
328 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
329 brw_set_default_flag_reg(p, 0, 0);
330
331 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
332 * present.
333 */
334 if (prog_data->uses_kill) {
335 struct brw_reg pixel_mask;
336
337 if (devinfo->gen >= 6)
338 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
339 else
340 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
341
342 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
343 }
344
345 if (devinfo->gen >= 6) {
346 brw_push_insn_state(p);
347 brw_set_default_exec_size(p, BRW_EXECUTE_16);
348 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
349 brw_MOV(p,
350 retype(payload, BRW_REGISTER_TYPE_UD),
351 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
352 brw_pop_insn_state(p);
353
354 if (inst->target > 0 && key->replicate_alpha) {
355 /* Set "Source0 Alpha Present to RenderTarget" bit in message
356 * header.
357 */
358 brw_OR(p,
359 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
360 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
361 brw_imm_ud(0x1 << 11));
362 }
363
364 if (inst->target > 0) {
365 /* Set the render target index for choosing BLEND_STATE. */
366 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
367 BRW_REGISTER_TYPE_UD),
368 brw_imm_ud(inst->target));
369 }
370
371 /* Set computes stencil to render target */
372 if (prog_data->computed_stencil) {
373 brw_OR(p,
374 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
375 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
376 brw_imm_ud(0x1 << 14));
377 }
378
379 implied_header = brw_null_reg();
380 } else {
381 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
382 }
383
384 brw_pop_insn_state(p);
385 } else {
386 implied_header = brw_null_reg();
387 }
388
389 if (!runtime_check_aads_emit) {
390 fire_fb_write(inst, payload, implied_header, inst->mlen);
391 } else {
392 /* This can only happen in gen < 6 */
393 assert(devinfo->gen < 6);
394
395 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
396
397 /* Check runtime bit to detect if we have to send AA data or not */
398 brw_push_insn_state(p);
399 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
400 brw_set_default_exec_size(p, BRW_EXECUTE_1);
401 brw_AND(p,
402 v1_null_ud,
403 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
404 brw_imm_ud(1<<26));
405 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
406
407 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
408 brw_pop_insn_state(p);
409 {
410 /* Don't send AA data */
411 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
412 }
413 brw_land_fwd_jump(p, jmp);
414 fire_fb_write(inst, payload, implied_header, inst->mlen);
415 }
416 }
417
418 void
419 fs_generator::generate_fb_read(fs_inst *inst, struct brw_reg dst,
420 struct brw_reg payload)
421 {
422 assert(inst->size_written % REG_SIZE == 0);
423 struct brw_wm_prog_data *prog_data = brw_wm_prog_data(this->prog_data);
424 /* We assume that render targets start at binding table index 0. */
425 const unsigned surf_index = inst->target;
426
427 gen9_fb_READ(p, dst, payload, surf_index,
428 inst->header_size, inst->size_written / REG_SIZE,
429 prog_data->persample_dispatch);
430
431 brw_mark_surface_used(&prog_data->base, surf_index);
432 }
433
434 void
435 fs_generator::generate_mov_indirect(fs_inst *inst,
436 struct brw_reg dst,
437 struct brw_reg reg,
438 struct brw_reg indirect_byte_offset)
439 {
440 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
441 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
442 assert(!reg.abs && !reg.negate);
443 assert(reg.type == dst.type);
444
445 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
446
447 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
448 imm_byte_offset += indirect_byte_offset.ud;
449
450 reg.nr = imm_byte_offset / REG_SIZE;
451 reg.subnr = imm_byte_offset % REG_SIZE;
452 brw_MOV(p, dst, reg);
453 } else {
454 /* Prior to Broadwell, there are only 8 address registers. */
455 assert(inst->exec_size <= 8 || devinfo->gen >= 8);
456
457 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
458 struct brw_reg addr = vec8(brw_address_reg(0));
459
460 /* The destination stride of an instruction (in bytes) must be greater
461 * than or equal to the size of the rest of the instruction. Since the
462 * address register is of type UW, we can't use a D-type instruction.
463 * In order to get around this, re retype to UW and use a stride.
464 */
465 indirect_byte_offset =
466 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
467
468 /* There are a number of reasons why we don't use the base offset here.
469 * One reason is that the field is only 9 bits which means we can only
470 * use it to access the first 16 GRFs. Also, from the Haswell PRM
471 * section "Register Region Restrictions":
472 *
473 * "The lower bits of the AddressImmediate must not overflow to
474 * change the register address. The lower 5 bits of Address
475 * Immediate when added to lower 5 bits of address register gives
476 * the sub-register offset. The upper bits of Address Immediate
477 * when added to upper bits of address register gives the register
478 * address. Any overflow from sub-register offset is dropped."
479 *
480 * Since the indirect may cause us to cross a register boundary, this
481 * makes the base offset almost useless. We could try and do something
482 * clever where we use a actual base offset if base_offset % 32 == 0 but
483 * that would mean we were generating different code depending on the
484 * base offset. Instead, for the sake of consistency, we'll just do the
485 * add ourselves. This restriction is only listed in the Haswell PRM
486 * but empirical testing indicates that it applies on all older
487 * generations and is lifted on Broadwell.
488 *
489 * In the end, while base_offset is nice to look at in the generated
490 * code, using it saves us 0 instructions and would require quite a bit
491 * of case-by-case work. It's just not worth it.
492 */
493 brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
494
495 if (type_sz(reg.type) > 4 &&
496 ((devinfo->gen == 7 && !devinfo->is_haswell) ||
497 devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
498 /* IVB has an issue (which we found empirically) where it reads two
499 * address register components per channel for indirectly addressed
500 * 64-bit sources.
501 *
502 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
503 *
504 * "When source or destination datatype is 64b or operation is
505 * integer DWord multiply, indirect addressing must not be used."
506 *
507 * To work around both of these, we do two integer MOVs insead of one
508 * 64-bit MOV. Because no double value should ever cross a register
509 * boundary, it's safe to use the immediate offset in the indirect
510 * here to handle adding 4 bytes to the offset and avoid the extra
511 * ADD to the register file.
512 */
513 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
514 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
515 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
516 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
517 } else {
518 struct brw_reg ind_src = brw_VxH_indirect(0, 0);
519
520 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, reg.type));
521
522 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
523 !inst->get_next()->is_tail_sentinel() &&
524 ((fs_inst *)inst->get_next())->mlen > 0) {
525 /* From the Sandybridge PRM:
526 *
527 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
528 * instruction that “indexed/indirect” source AND is followed
529 * by a send, the instruction requires a “Switch”. This is to
530 * avoid race condition where send may dispatch before MRF is
531 * updated."
532 */
533 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
534 }
535 }
536 }
537 }
538
539 void
540 fs_generator::generate_shuffle(fs_inst *inst,
541 struct brw_reg dst,
542 struct brw_reg src,
543 struct brw_reg idx)
544 {
545 /* Ivy bridge has some strange behavior that makes this a real pain to
546 * implement for 64-bit values so we just don't bother.
547 */
548 assert(devinfo->gen >= 8 || devinfo->is_haswell || type_sz(src.type) <= 4);
549
550 /* Because we're using the address register, we're limited to 8-wide
551 * execution on gen7. On gen8, we're limited to 16-wide by the address
552 * register file and 8-wide for 64-bit types. We could try and make this
553 * instruction splittable higher up in the compiler but that gets weird
554 * because it reads all of the channels regardless of execution size. It's
555 * easier just to split it here.
556 */
557 const unsigned lower_width =
558 (devinfo->gen <= 7 || type_sz(src.type) > 4) ?
559 8 : MIN2(16, inst->exec_size);
560
561 brw_set_default_exec_size(p, cvt(lower_width) - 1);
562 for (unsigned group = 0; group < inst->exec_size; group += lower_width) {
563 brw_set_default_group(p, group);
564
565 if ((src.vstride == 0 && src.hstride == 0) ||
566 idx.file == BRW_IMMEDIATE_VALUE) {
567 /* Trivial, the source is already uniform or the index is a constant.
568 * We will typically not get here if the optimizer is doing its job,
569 * but asserting would be mean.
570 */
571 const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
572 brw_MOV(p, suboffset(dst, group), stride(suboffset(src, i), 0, 1, 0));
573 } else {
574 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
575 struct brw_reg addr = vec8(brw_address_reg(0));
576
577 struct brw_reg group_idx = suboffset(idx, group);
578
579 if (lower_width == 8 && group_idx.width == BRW_WIDTH_16) {
580 /* Things get grumpy if the register is too wide. */
581 group_idx.width--;
582 group_idx.vstride--;
583 }
584
585 assert(type_sz(group_idx.type) <= 4);
586 if (type_sz(group_idx.type) == 4) {
587 /* The destination stride of an instruction (in bytes) must be
588 * greater than or equal to the size of the rest of the
589 * instruction. Since the address register is of type UW, we
590 * can't use a D-type instruction. In order to get around this,
591 * re retype to UW and use a stride.
592 */
593 group_idx = retype(spread(group_idx, 2), BRW_REGISTER_TYPE_W);
594 }
595
596 /* Take into account the component size and horizontal stride. */
597 assert(src.vstride == src.hstride + src.width);
598 brw_SHL(p, addr, group_idx,
599 brw_imm_uw(_mesa_logbase2(type_sz(src.type)) +
600 src.hstride - 1));
601
602 /* Add on the register start offset */
603 brw_ADD(p, addr, addr, brw_imm_uw(src.nr * REG_SIZE + src.subnr));
604
605 if (type_sz(src.type) > 4 &&
606 ((devinfo->gen == 7 && !devinfo->is_haswell) ||
607 devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
608 /* IVB has an issue (which we found empirically) where it reads
609 * two address register components per channel for indirectly
610 * addressed 64-bit sources.
611 *
612 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
613 *
614 * "When source or destination datatype is 64b or operation is
615 * integer DWord multiply, indirect addressing must not be
616 * used."
617 *
618 * To work around both of these, we do two integer MOVs insead of
619 * one 64-bit MOV. Because no double value should ever cross a
620 * register boundary, it's safe to use the immediate offset in the
621 * indirect here to handle adding 4 bytes to the offset and avoid
622 * the extra ADD to the register file.
623 */
624 struct brw_reg gdst = suboffset(dst, group);
625 struct brw_reg dst_d = retype(spread(gdst, 2),
626 BRW_REGISTER_TYPE_D);
627 brw_MOV(p, dst_d,
628 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D));
629 brw_MOV(p, byte_offset(dst_d, 4),
630 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D));
631 } else {
632 brw_MOV(p, suboffset(dst, group),
633 retype(brw_VxH_indirect(0, 0), src.type));
634 }
635 }
636 }
637 }
638
639 void
640 fs_generator::generate_urb_read(fs_inst *inst,
641 struct brw_reg dst,
642 struct brw_reg header)
643 {
644 assert(inst->size_written % REG_SIZE == 0);
645 assert(header.file == BRW_GENERAL_REGISTER_FILE);
646 assert(header.type == BRW_REGISTER_TYPE_UD);
647
648 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
649 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
650 brw_set_src0(p, send, header);
651 brw_set_src1(p, send, brw_imm_ud(0u));
652
653 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
654 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
655
656 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
657 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
658
659 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
660 brw_inst_set_rlen(p->devinfo, send, inst->size_written / REG_SIZE);
661 brw_inst_set_header_present(p->devinfo, send, true);
662 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
663 }
664
665 void
666 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
667 {
668 brw_inst *insn;
669
670 /* WaClearTDRRegBeforeEOTForNonPS.
671 *
672 * WA: Clear tdr register before send EOT in all non-PS shader kernels
673 *
674 * mov(8) tdr0:ud 0x0:ud {NoMask}"
675 */
676 if (inst->eot && p->devinfo->gen == 10) {
677 brw_push_insn_state(p);
678 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
679 brw_MOV(p, brw_tdr_reg(), brw_imm_uw(0));
680 brw_pop_insn_state(p);
681 }
682
683 insn = brw_next_insn(p, BRW_OPCODE_SEND);
684
685 brw_set_dest(p, insn, brw_null_reg());
686 brw_set_src0(p, insn, payload);
687 brw_set_src1(p, insn, brw_imm_d(0));
688
689 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
690 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
691
692 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
693 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
694 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
695
696 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
697 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
698 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
699
700 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
701 brw_inst_set_rlen(p->devinfo, insn, 0);
702 brw_inst_set_eot(p->devinfo, insn, inst->eot);
703 brw_inst_set_header_present(p->devinfo, insn, true);
704 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
705 }
706
707 void
708 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
709 {
710 struct brw_inst *insn;
711
712 insn = brw_next_insn(p, BRW_OPCODE_SEND);
713
714 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
715 brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UW));
716 brw_set_src1(p, insn, brw_imm_d(0));
717
718 /* Terminate a compute shader by sending a message to the thread spawner.
719 */
720 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
721 brw_inst_set_mlen(devinfo, insn, 1);
722 brw_inst_set_rlen(devinfo, insn, 0);
723 brw_inst_set_eot(devinfo, insn, inst->eot);
724 brw_inst_set_header_present(devinfo, insn, false);
725
726 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
727 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
728
729 /* Note that even though the thread has a URB resource associated with it,
730 * we set the "do not dereference URB" bit, because the URB resource is
731 * managed by the fixed-function unit, so it will free it automatically.
732 */
733 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
734
735 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
736 }
737
738 void
739 fs_generator::generate_barrier(fs_inst *, struct brw_reg src)
740 {
741 brw_barrier(p, src);
742 brw_WAIT(p);
743 }
744
745 bool
746 fs_generator::generate_linterp(fs_inst *inst,
747 struct brw_reg dst, struct brw_reg *src)
748 {
749 /* PLN reads:
750 * / in SIMD16 \
751 * -----------------------------------
752 * | src1+0 | src1+1 | src1+2 | src1+3 |
753 * |-----------------------------------|
754 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
755 * -----------------------------------
756 *
757 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
758 *
759 * -----------------------------------
760 * | src1+0 | src1+1 | src1+2 | src1+3 |
761 * |-----------------------------------|
762 * |(x0, x1)|(y0, y1)| | | in SIMD8
763 * |-----------------------------------|
764 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
765 * -----------------------------------
766 *
767 * See also: emit_interpolation_setup_gen4().
768 */
769 struct brw_reg delta_x = src[0];
770 struct brw_reg delta_y = offset(src[0], inst->exec_size / 8);
771 struct brw_reg interp = src[1];
772 brw_inst *i[4];
773
774 if (devinfo->gen >= 11) {
775 struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF);
776 struct brw_reg dwP = suboffset(interp, 0);
777 struct brw_reg dwQ = suboffset(interp, 1);
778 struct brw_reg dwR = suboffset(interp, 3);
779
780 brw_push_insn_state(p);
781 brw_set_default_exec_size(p, BRW_EXECUTE_8);
782
783 if (inst->exec_size == 8) {
784 i[0] = brw_MAD(p, acc, dwR, offset(delta_x, 0), dwP);
785 i[1] = brw_MAD(p, offset(dst, 0), acc, offset(delta_y, 0), dwQ);
786
787 brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
788
789 /* brw_set_default_saturate() is called before emitting instructions,
790 * so the saturate bit is set in each instruction, so we need to unset
791 * it on the first instruction of each pair.
792 */
793 brw_inst_set_saturate(p->devinfo, i[0], false);
794 } else {
795 brw_set_default_group(p, inst->group);
796 i[0] = brw_MAD(p, acc, dwR, offset(delta_x, 0), dwP);
797 i[1] = brw_MAD(p, offset(dst, 0), acc, offset(delta_x, 1), dwQ);
798
799 brw_set_default_group(p, inst->group + 8);
800 i[2] = brw_MAD(p, acc, dwR, offset(delta_y, 0), dwP);
801 i[3] = brw_MAD(p, offset(dst, 1), acc, offset(delta_y, 1), dwQ);
802
803 brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
804 brw_inst_set_cond_modifier(p->devinfo, i[3], inst->conditional_mod);
805
806 /* brw_set_default_saturate() is called before emitting instructions,
807 * so the saturate bit is set in each instruction, so we need to unset
808 * it on the first instruction of each pair.
809 */
810 brw_inst_set_saturate(p->devinfo, i[0], false);
811 brw_inst_set_saturate(p->devinfo, i[2], false);
812 }
813
814 brw_pop_insn_state(p);
815
816 return true;
817 } else if (devinfo->has_pln) {
818 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
819 *
820 * "[DevSNB]:<src1> must be even register aligned.
821 *
822 * This restriction is lifted on Ivy Bridge.
823 */
824 assert(devinfo->gen >= 7 || (delta_x.nr & 1) == 0);
825 brw_PLN(p, dst, interp, delta_x);
826
827 return false;
828 } else {
829 i[0] = brw_LINE(p, brw_null_reg(), interp, delta_x);
830 i[1] = brw_MAC(p, dst, suboffset(interp, 1), delta_y);
831
832 brw_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
833
834 /* brw_set_default_saturate() is called before emitting instructions, so
835 * the saturate bit is set in each instruction, so we need to unset it on
836 * the first instruction.
837 */
838 brw_inst_set_saturate(p->devinfo, i[0], false);
839
840 return true;
841 }
842 }
843
844 void
845 fs_generator::generate_get_buffer_size(fs_inst *inst,
846 struct brw_reg dst,
847 struct brw_reg src,
848 struct brw_reg surf_index)
849 {
850 assert(devinfo->gen >= 7);
851 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
852
853 uint32_t simd_mode;
854 int rlen = 4;
855
856 switch (inst->exec_size) {
857 case 8:
858 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
859 break;
860 case 16:
861 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
862 break;
863 default:
864 unreachable("Invalid width for texture instruction");
865 }
866
867 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
868 rlen = 8;
869 dst = vec16(dst);
870 }
871
872 brw_SAMPLE(p,
873 retype(dst, BRW_REGISTER_TYPE_UW),
874 inst->base_mrf,
875 src,
876 surf_index.ud,
877 0,
878 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
879 rlen, /* response length */
880 inst->mlen,
881 inst->header_size > 0,
882 simd_mode,
883 BRW_SAMPLER_RETURN_FORMAT_SINT32);
884
885 brw_mark_surface_used(prog_data, surf_index.ud);
886 }
887
888 void
889 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
890 struct brw_reg surface_index,
891 struct brw_reg sampler_index)
892 {
893 assert(inst->size_written % REG_SIZE == 0);
894 int msg_type = -1;
895 uint32_t simd_mode;
896 uint32_t return_format;
897 bool is_combined_send = inst->eot;
898
899 switch (dst.type) {
900 case BRW_REGISTER_TYPE_D:
901 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
902 break;
903 case BRW_REGISTER_TYPE_UD:
904 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
905 break;
906 default:
907 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
908 break;
909 }
910
911 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
912 * is set as part of the message descriptor. On gen4, the PRM seems to
913 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
914 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
915 * gone from the message descriptor entirely and you just get UINT32 all
916 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
917 * just stomp it to UINT32 all the time.
918 */
919 if (inst->opcode == SHADER_OPCODE_TXS)
920 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
921
922 switch (inst->exec_size) {
923 case 8:
924 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
925 break;
926 case 16:
927 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
928 break;
929 default:
930 unreachable("Invalid width for texture instruction");
931 }
932
933 if (devinfo->gen >= 5) {
934 switch (inst->opcode) {
935 case SHADER_OPCODE_TEX:
936 if (inst->shadow_compare) {
937 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
938 } else {
939 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
940 }
941 break;
942 case FS_OPCODE_TXB:
943 if (inst->shadow_compare) {
944 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
945 } else {
946 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
947 }
948 break;
949 case SHADER_OPCODE_TXL:
950 if (inst->shadow_compare) {
951 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
952 } else {
953 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
954 }
955 break;
956 case SHADER_OPCODE_TXL_LZ:
957 assert(devinfo->gen >= 9);
958 if (inst->shadow_compare) {
959 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ;
960 } else {
961 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LZ;
962 }
963 break;
964 case SHADER_OPCODE_TXS:
965 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
966 break;
967 case SHADER_OPCODE_TXD:
968 if (inst->shadow_compare) {
969 /* Gen7.5+. Otherwise, lowered in NIR */
970 assert(devinfo->gen >= 8 || devinfo->is_haswell);
971 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
972 } else {
973 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
974 }
975 break;
976 case SHADER_OPCODE_TXF:
977 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
978 break;
979 case SHADER_OPCODE_TXF_LZ:
980 assert(devinfo->gen >= 9);
981 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
982 break;
983 case SHADER_OPCODE_TXF_CMS_W:
984 assert(devinfo->gen >= 9);
985 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
986 break;
987 case SHADER_OPCODE_TXF_CMS:
988 if (devinfo->gen >= 7)
989 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
990 else
991 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
992 break;
993 case SHADER_OPCODE_TXF_UMS:
994 assert(devinfo->gen >= 7);
995 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
996 break;
997 case SHADER_OPCODE_TXF_MCS:
998 assert(devinfo->gen >= 7);
999 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
1000 break;
1001 case SHADER_OPCODE_LOD:
1002 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
1003 break;
1004 case SHADER_OPCODE_TG4:
1005 if (inst->shadow_compare) {
1006 assert(devinfo->gen >= 7);
1007 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
1008 } else {
1009 assert(devinfo->gen >= 6);
1010 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
1011 }
1012 break;
1013 case SHADER_OPCODE_TG4_OFFSET:
1014 assert(devinfo->gen >= 7);
1015 if (inst->shadow_compare) {
1016 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
1017 } else {
1018 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
1019 }
1020 break;
1021 case SHADER_OPCODE_SAMPLEINFO:
1022 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
1023 break;
1024 default:
1025 unreachable("not reached");
1026 }
1027 } else {
1028 switch (inst->opcode) {
1029 case SHADER_OPCODE_TEX:
1030 /* Note that G45 and older determines shadow compare and dispatch width
1031 * from message length for most messages.
1032 */
1033 if (inst->exec_size == 8) {
1034 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
1035 if (inst->shadow_compare) {
1036 assert(inst->mlen == 6);
1037 } else {
1038 assert(inst->mlen <= 4);
1039 }
1040 } else {
1041 if (inst->shadow_compare) {
1042 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1043 assert(inst->mlen == 9);
1044 } else {
1045 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1046 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
1047 }
1048 }
1049 break;
1050 case FS_OPCODE_TXB:
1051 if (inst->shadow_compare) {
1052 assert(inst->exec_size == 8);
1053 assert(inst->mlen == 6);
1054 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
1055 } else {
1056 assert(inst->mlen == 9);
1057 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1058 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1059 }
1060 break;
1061 case SHADER_OPCODE_TXL:
1062 if (inst->shadow_compare) {
1063 assert(inst->exec_size == 8);
1064 assert(inst->mlen == 6);
1065 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
1066 } else {
1067 assert(inst->mlen == 9);
1068 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
1069 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1070 }
1071 break;
1072 case SHADER_OPCODE_TXD:
1073 /* There is no sample_d_c message; comparisons are done manually */
1074 assert(inst->exec_size == 8);
1075 assert(inst->mlen == 7 || inst->mlen == 10);
1076 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
1077 break;
1078 case SHADER_OPCODE_TXF:
1079 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
1080 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1081 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1082 break;
1083 case SHADER_OPCODE_TXS:
1084 assert(inst->mlen == 3);
1085 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
1086 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1087 break;
1088 default:
1089 unreachable("not reached");
1090 }
1091 }
1092 assert(msg_type != -1);
1093
1094 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
1095 dst = vec16(dst);
1096 }
1097
1098 assert(devinfo->gen < 7 || inst->header_size == 0 ||
1099 src.file == BRW_GENERAL_REGISTER_FILE);
1100
1101 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
1102
1103 /* Load the message header if present. If there's a texture offset,
1104 * we need to set it up explicitly and load the offset bitfield.
1105 * Otherwise, we can use an implied move from g0 to the first message reg.
1106 */
1107 if (inst->header_size != 0 && devinfo->gen < 7) {
1108 if (devinfo->gen < 6 && !inst->offset) {
1109 /* Set up an implied move from g0 to the MRF. */
1110 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
1111 } else {
1112 assert(inst->base_mrf != -1);
1113 struct brw_reg header_reg = brw_message_reg(inst->base_mrf);
1114
1115 brw_push_insn_state(p);
1116 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1117 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1118 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1119 /* Explicitly set up the message header by copying g0 to the MRF. */
1120 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
1121
1122 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1123 if (inst->offset) {
1124 /* Set the offset bits in DWord 2. */
1125 brw_MOV(p, get_element_ud(header_reg, 2),
1126 brw_imm_ud(inst->offset));
1127 }
1128
1129 brw_pop_insn_state(p);
1130 }
1131 }
1132
1133 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
1134 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
1135 ? prog_data->binding_table.gather_texture_start
1136 : prog_data->binding_table.texture_start;
1137
1138 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
1139 sampler_index.file == BRW_IMMEDIATE_VALUE) {
1140 uint32_t surface = surface_index.ud;
1141 uint32_t sampler = sampler_index.ud;
1142
1143 brw_SAMPLE(p,
1144 retype(dst, BRW_REGISTER_TYPE_UW),
1145 inst->base_mrf,
1146 src,
1147 surface + base_binding_table_index,
1148 sampler % 16,
1149 msg_type,
1150 inst->size_written / REG_SIZE,
1151 inst->mlen,
1152 inst->header_size != 0,
1153 simd_mode,
1154 return_format);
1155
1156 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
1157 } else {
1158 /* Non-const sampler index */
1159
1160 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1161 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
1162 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
1163
1164 brw_push_insn_state(p);
1165 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1166 brw_set_default_access_mode(p, BRW_ALIGN_1);
1167 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1168
1169 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
1170 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
1171 } else {
1172 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
1173 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
1174 } else {
1175 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
1176 brw_OR(p, addr, addr, surface_reg);
1177 }
1178 }
1179 if (base_binding_table_index)
1180 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
1181 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
1182
1183 brw_pop_insn_state(p);
1184
1185 /* dst = send(offset, a0.0 | <descriptor>) */
1186 brw_inst *insn = brw_send_indirect_message(
1187 p, BRW_SFID_SAMPLER, dst, src, addr);
1188 brw_set_sampler_message(p, insn,
1189 0 /* surface */,
1190 0 /* sampler */,
1191 msg_type,
1192 inst->size_written / REG_SIZE,
1193 inst->mlen /* mlen */,
1194 inst->header_size != 0 /* header */,
1195 simd_mode,
1196 return_format);
1197
1198 /* visitor knows more than we do about the surface limit required,
1199 * so has already done marking.
1200 */
1201 }
1202
1203 if (is_combined_send) {
1204 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
1205 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
1206 }
1207 }
1208
1209
1210 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1211 * looking like:
1212 *
1213 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1214 *
1215 * Ideally, we want to produce:
1216 *
1217 * DDX DDY
1218 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1219 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1220 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1221 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1222 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1223 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1224 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1225 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1226 *
1227 * and add another set of two more subspans if in 16-pixel dispatch mode.
1228 *
1229 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1230 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1231 * pair. But the ideal approximation may impose a huge performance cost on
1232 * sample_d. On at least Haswell, sample_d instruction does some
1233 * optimizations if the same LOD is used for all pixels in the subspan.
1234 *
1235 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1236 * appropriate swizzling.
1237 */
1238 void
1239 fs_generator::generate_ddx(const fs_inst *inst,
1240 struct brw_reg dst, struct brw_reg src)
1241 {
1242 unsigned vstride, width;
1243
1244 if (inst->opcode == FS_OPCODE_DDX_FINE) {
1245 /* produce accurate derivatives */
1246 vstride = BRW_VERTICAL_STRIDE_2;
1247 width = BRW_WIDTH_2;
1248 } else {
1249 /* replicate the derivative at the top-left pixel to other pixels */
1250 vstride = BRW_VERTICAL_STRIDE_4;
1251 width = BRW_WIDTH_4;
1252 }
1253
1254 struct brw_reg src0 = src;
1255 struct brw_reg src1 = src;
1256
1257 src0.subnr = sizeof(float);
1258 src0.vstride = vstride;
1259 src0.width = width;
1260 src0.hstride = BRW_HORIZONTAL_STRIDE_0;
1261 src1.vstride = vstride;
1262 src1.width = width;
1263 src1.hstride = BRW_HORIZONTAL_STRIDE_0;
1264
1265 brw_ADD(p, dst, src0, negate(src1));
1266 }
1267
1268 /* The negate_value boolean is used to negate the derivative computation for
1269 * FBOs, since they place the origin at the upper left instead of the lower
1270 * left.
1271 */
1272 void
1273 fs_generator::generate_ddy(const fs_inst *inst,
1274 struct brw_reg dst, struct brw_reg src)
1275 {
1276 if (inst->opcode == FS_OPCODE_DDY_FINE) {
1277 /* produce accurate derivatives */
1278 if (devinfo->gen >= 11) {
1279 src = stride(src, 0, 2, 1);
1280 struct brw_reg src_0 = byte_offset(src, 0 * sizeof(float));
1281 struct brw_reg src_2 = byte_offset(src, 2 * sizeof(float));
1282 struct brw_reg src_4 = byte_offset(src, 4 * sizeof(float));
1283 struct brw_reg src_6 = byte_offset(src, 6 * sizeof(float));
1284 struct brw_reg src_8 = byte_offset(src, 8 * sizeof(float));
1285 struct brw_reg src_10 = byte_offset(src, 10 * sizeof(float));
1286 struct brw_reg src_12 = byte_offset(src, 12 * sizeof(float));
1287 struct brw_reg src_14 = byte_offset(src, 14 * sizeof(float));
1288
1289 struct brw_reg dst_0 = byte_offset(dst, 0 * sizeof(float));
1290 struct brw_reg dst_4 = byte_offset(dst, 4 * sizeof(float));
1291 struct brw_reg dst_8 = byte_offset(dst, 8 * sizeof(float));
1292 struct brw_reg dst_12 = byte_offset(dst, 12 * sizeof(float));
1293
1294 brw_push_insn_state(p);
1295 brw_set_default_exec_size(p, BRW_EXECUTE_4);
1296
1297 brw_ADD(p, dst_0, negate(src_0), src_2);
1298 brw_ADD(p, dst_4, negate(src_4), src_6);
1299
1300 if (inst->exec_size == 16) {
1301 brw_ADD(p, dst_8, negate(src_8), src_10);
1302 brw_ADD(p, dst_12, negate(src_12), src_14);
1303 }
1304
1305 brw_pop_insn_state(p);
1306 } else {
1307 struct brw_reg src0 = stride(src, 4, 4, 1);
1308 struct brw_reg src1 = stride(src, 4, 4, 1);
1309 src0.swizzle = BRW_SWIZZLE_XYXY;
1310 src1.swizzle = BRW_SWIZZLE_ZWZW;
1311
1312 brw_push_insn_state(p);
1313 brw_set_default_access_mode(p, BRW_ALIGN_16);
1314 brw_ADD(p, dst, negate(src0), src1);
1315 brw_pop_insn_state(p);
1316 }
1317 } else {
1318 /* replicate the derivative at the top-left pixel to other pixels */
1319 struct brw_reg src0 = stride(src, 4, 4, 0);
1320 struct brw_reg src1 = stride(src, 4, 4, 0);
1321 src0.subnr = 0 * sizeof(float);
1322 src1.subnr = 2 * sizeof(float);
1323
1324 brw_ADD(p, dst, negate(src0), src1);
1325 }
1326 }
1327
1328 void
1329 fs_generator::generate_discard_jump(fs_inst *)
1330 {
1331 assert(devinfo->gen >= 6);
1332
1333 /* This HALT will be patched up at FB write time to point UIP at the end of
1334 * the program, and at brw_uip_jip() JIP will be set to the end of the
1335 * current block (or the program).
1336 */
1337 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1338 gen6_HALT(p);
1339 }
1340
1341 void
1342 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1343 {
1344 /* The 32-wide messages only respect the first 16-wide half of the channel
1345 * enable signals which are replicated identically for the second group of
1346 * 16 channels, so we cannot use them unless the write is marked
1347 * force_writemask_all.
1348 */
1349 const unsigned lower_size = inst->force_writemask_all ? inst->exec_size :
1350 MIN2(16, inst->exec_size);
1351 const unsigned block_size = 4 * lower_size / REG_SIZE;
1352 assert(inst->mlen != 0);
1353
1354 brw_push_insn_state(p);
1355 brw_set_default_exec_size(p, cvt(lower_size) - 1);
1356 brw_set_default_compression(p, lower_size > 8);
1357
1358 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1359 brw_set_default_group(p, inst->group + lower_size * i);
1360
1361 brw_MOV(p, brw_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
1362 retype(offset(src, block_size * i), BRW_REGISTER_TYPE_UD));
1363
1364 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1365 block_size,
1366 inst->offset + block_size * REG_SIZE * i);
1367 }
1368
1369 brw_pop_insn_state(p);
1370 }
1371
1372 void
1373 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1374 {
1375 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1376 assert(inst->mlen != 0);
1377
1378 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1379 inst->exec_size / 8, inst->offset);
1380 }
1381
1382 void
1383 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1384 {
1385 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1386
1387 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1388 }
1389
1390 void
1391 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1392 struct brw_reg dst,
1393 struct brw_reg index,
1394 struct brw_reg offset)
1395 {
1396 assert(type_sz(dst.type) == 4);
1397 assert(inst->mlen != 0);
1398
1399 assert(index.file == BRW_IMMEDIATE_VALUE &&
1400 index.type == BRW_REGISTER_TYPE_UD);
1401 uint32_t surf_index = index.ud;
1402
1403 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1404 offset.type == BRW_REGISTER_TYPE_UD);
1405 uint32_t read_offset = offset.ud;
1406
1407 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1408 read_offset, surf_index);
1409 }
1410
1411 void
1412 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1413 struct brw_reg dst,
1414 struct brw_reg index,
1415 struct brw_reg payload)
1416 {
1417 assert(index.type == BRW_REGISTER_TYPE_UD);
1418 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1419 assert(type_sz(dst.type) == 4);
1420
1421 if (index.file == BRW_IMMEDIATE_VALUE) {
1422 const uint32_t surf_index = index.ud;
1423
1424 brw_push_insn_state(p);
1425 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1426 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1427 brw_pop_insn_state(p);
1428
1429 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
1430 brw_set_src0(p, send, retype(payload, BRW_REGISTER_TYPE_UD));
1431 brw_set_dp_read_message(p, send, surf_index,
1432 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
1433 GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
1434 GEN6_SFID_DATAPORT_CONSTANT_CACHE,
1435 1, /* mlen */
1436 true, /* header */
1437 DIV_ROUND_UP(inst->size_written, REG_SIZE));
1438
1439 } else {
1440 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1441
1442 brw_push_insn_state(p);
1443 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1444
1445 /* a0.0 = surf_index & 0xff */
1446 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1447 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1448 brw_set_dest(p, insn_and, addr);
1449 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1450 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1451
1452 /* dst = send(payload, a0.0 | <descriptor>) */
1453 brw_inst *insn = brw_send_indirect_message(
1454 p, GEN6_SFID_DATAPORT_CONSTANT_CACHE,
1455 retype(dst, BRW_REGISTER_TYPE_UD),
1456 retype(payload, BRW_REGISTER_TYPE_UD), addr);
1457 brw_set_dp_read_message(p, insn, 0 /* surface */,
1458 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst->exec_size),
1459 GEN7_DATAPORT_DC_OWORD_BLOCK_READ,
1460 GEN6_SFID_DATAPORT_CONSTANT_CACHE,
1461 1, /* mlen */
1462 true, /* header */
1463 DIV_ROUND_UP(inst->size_written, REG_SIZE));
1464
1465 brw_pop_insn_state(p);
1466 }
1467 }
1468
1469 void
1470 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
1471 struct brw_reg dst,
1472 struct brw_reg index)
1473 {
1474 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1475 assert(inst->header_size != 0);
1476 assert(inst->mlen);
1477
1478 assert(index.file == BRW_IMMEDIATE_VALUE &&
1479 index.type == BRW_REGISTER_TYPE_UD);
1480 uint32_t surf_index = index.ud;
1481
1482 uint32_t simd_mode, rlen, msg_type;
1483 if (inst->exec_size == 16) {
1484 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1485 rlen = 8;
1486 } else {
1487 assert(inst->exec_size == 8);
1488 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1489 rlen = 4;
1490 }
1491
1492 if (devinfo->gen >= 5)
1493 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1494 else {
1495 /* We always use the SIMD16 message so that we only have to load U, and
1496 * not V or R.
1497 */
1498 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1499 assert(inst->mlen == 3);
1500 assert(inst->size_written == 8 * REG_SIZE);
1501 rlen = 8;
1502 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1503 }
1504
1505 struct brw_reg header = brw_vec8_grf(0, 0);
1506 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1507
1508 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1509 brw_inst_set_compression(devinfo, send, false);
1510 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1511 brw_set_src0(p, send, header);
1512 if (devinfo->gen < 6)
1513 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1514
1515 /* Our surface is set up as floats, regardless of what actual data is
1516 * stored in it.
1517 */
1518 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1519 brw_set_sampler_message(p, send,
1520 surf_index,
1521 0, /* sampler (unused) */
1522 msg_type,
1523 rlen,
1524 inst->mlen,
1525 inst->header_size != 0,
1526 simd_mode,
1527 return_format);
1528 }
1529
1530 void
1531 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1532 struct brw_reg dst,
1533 struct brw_reg index,
1534 struct brw_reg offset)
1535 {
1536 assert(devinfo->gen >= 7);
1537 /* Varying-offset pull constant loads are treated as a normal expression on
1538 * gen7, so the fact that it's a send message is hidden at the IR level.
1539 */
1540 assert(inst->header_size == 0);
1541 assert(!inst->mlen);
1542 assert(index.type == BRW_REGISTER_TYPE_UD);
1543
1544 uint32_t simd_mode, rlen, mlen;
1545 if (inst->exec_size == 16) {
1546 mlen = 2;
1547 rlen = 8;
1548 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1549 } else {
1550 assert(inst->exec_size == 8);
1551 mlen = 1;
1552 rlen = 4;
1553 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1554 }
1555
1556 if (index.file == BRW_IMMEDIATE_VALUE) {
1557
1558 uint32_t surf_index = index.ud;
1559
1560 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1561 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1562 brw_set_src0(p, send, offset);
1563 brw_set_sampler_message(p, send,
1564 surf_index,
1565 0, /* LD message ignores sampler unit */
1566 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1567 rlen,
1568 mlen,
1569 false, /* no header */
1570 simd_mode,
1571 0);
1572
1573 } else {
1574
1575 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1576
1577 brw_push_insn_state(p);
1578 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1579
1580 /* a0.0 = surf_index & 0xff */
1581 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1582 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1583 brw_set_dest(p, insn_and, addr);
1584 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1585 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1586
1587 brw_pop_insn_state(p);
1588
1589 /* dst = send(offset, a0.0 | <descriptor>) */
1590 brw_inst *insn = brw_send_indirect_message(
1591 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1592 offset, addr);
1593 brw_set_sampler_message(p, insn,
1594 0 /* surface */,
1595 0 /* sampler */,
1596 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1597 rlen /* rlen */,
1598 mlen /* mlen */,
1599 false /* header */,
1600 simd_mode,
1601 0);
1602 }
1603 }
1604
1605 /**
1606 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1607 * into the flags register (f0.0).
1608 *
1609 * Used only on Gen6 and above.
1610 */
1611 void
1612 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1613 {
1614 struct brw_reg flags = brw_flag_subreg(inst->flag_subreg);
1615 struct brw_reg dispatch_mask;
1616
1617 if (devinfo->gen >= 6)
1618 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1619 else
1620 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1621
1622 brw_push_insn_state(p);
1623 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1624 brw_set_default_exec_size(p, BRW_EXECUTE_1);
1625 brw_MOV(p, flags, dispatch_mask);
1626 brw_pop_insn_state(p);
1627 }
1628
1629 void
1630 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1631 struct brw_reg dst,
1632 struct brw_reg src,
1633 struct brw_reg msg_data,
1634 unsigned msg_type)
1635 {
1636 assert(inst->size_written % REG_SIZE == 0);
1637 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1638
1639 brw_pixel_interpolator_query(p,
1640 retype(dst, BRW_REGISTER_TYPE_UW),
1641 src,
1642 inst->pi_noperspective,
1643 msg_type,
1644 msg_data,
1645 inst->mlen,
1646 inst->size_written / REG_SIZE);
1647 }
1648
1649 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1650 * the ADD instruction.
1651 */
1652 void
1653 fs_generator::generate_set_sample_id(fs_inst *inst,
1654 struct brw_reg dst,
1655 struct brw_reg src0,
1656 struct brw_reg src1)
1657 {
1658 assert(dst.type == BRW_REGISTER_TYPE_D ||
1659 dst.type == BRW_REGISTER_TYPE_UD);
1660 assert(src0.type == BRW_REGISTER_TYPE_D ||
1661 src0.type == BRW_REGISTER_TYPE_UD);
1662
1663 struct brw_reg reg = stride(src1, 1, 4, 0);
1664 if (devinfo->gen >= 8 || inst->exec_size == 8) {
1665 brw_ADD(p, dst, src0, reg);
1666 } else if (inst->exec_size == 16) {
1667 brw_push_insn_state(p);
1668 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1669 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1670 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1671 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1672 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1673 brw_pop_insn_state(p);
1674 }
1675 }
1676
1677 void
1678 fs_generator::generate_pack_half_2x16_split(fs_inst *,
1679 struct brw_reg dst,
1680 struct brw_reg x,
1681 struct brw_reg y)
1682 {
1683 assert(devinfo->gen >= 7);
1684 assert(dst.type == BRW_REGISTER_TYPE_UD);
1685 assert(x.type == BRW_REGISTER_TYPE_F);
1686 assert(y.type == BRW_REGISTER_TYPE_F);
1687
1688 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1689 *
1690 * Because this instruction does not have a 16-bit floating-point type,
1691 * the destination data type must be Word (W).
1692 *
1693 * The destination must be DWord-aligned and specify a horizontal stride
1694 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1695 * each destination channel and the upper word is not modified.
1696 */
1697 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1698
1699 /* Give each 32-bit channel of dst the form below, where "." means
1700 * unchanged.
1701 * 0x....hhhh
1702 */
1703 brw_F32TO16(p, dst_w, y);
1704
1705 /* Now the form:
1706 * 0xhhhh0000
1707 */
1708 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1709
1710 /* And, finally the form of packHalf2x16's output:
1711 * 0xhhhhllll
1712 */
1713 brw_F32TO16(p, dst_w, x);
1714 }
1715
1716 void
1717 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1718 struct brw_reg dst,
1719 struct brw_reg src)
1720 {
1721 assert(devinfo->gen >= 7);
1722 assert(dst.type == BRW_REGISTER_TYPE_F);
1723 assert(src.type == BRW_REGISTER_TYPE_UD);
1724
1725 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1726 *
1727 * Because this instruction does not have a 16-bit floating-point type,
1728 * the source data type must be Word (W). The destination type must be
1729 * F (Float).
1730 */
1731 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1732
1733 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1734 * For the Y case, we wish to access only the upper word; therefore
1735 * a 16-bit subregister offset is needed.
1736 */
1737 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1738 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1739 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1740 src_w.subnr += 2;
1741
1742 brw_F16TO32(p, dst, src_w);
1743 }
1744
1745 void
1746 fs_generator::generate_shader_time_add(fs_inst *,
1747 struct brw_reg payload,
1748 struct brw_reg offset,
1749 struct brw_reg value)
1750 {
1751 assert(devinfo->gen >= 7);
1752 brw_push_insn_state(p);
1753 brw_set_default_mask_control(p, true);
1754
1755 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1756 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1757 offset.type);
1758 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1759 value.type);
1760
1761 assert(offset.file == BRW_IMMEDIATE_VALUE);
1762 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1763 value.width = BRW_WIDTH_1;
1764 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1765 value.vstride = BRW_VERTICAL_STRIDE_0;
1766 } else {
1767 assert(value.file == BRW_IMMEDIATE_VALUE);
1768 }
1769
1770 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1771 * case, and we don't really care about squeezing every bit of performance
1772 * out of this path, so we just emit the MOVs from here.
1773 */
1774 brw_MOV(p, payload_offset, offset);
1775 brw_MOV(p, payload_value, value);
1776 brw_shader_time_add(p, payload,
1777 prog_data->binding_table.shader_time_start);
1778 brw_pop_insn_state(p);
1779
1780 brw_mark_surface_used(prog_data,
1781 prog_data->binding_table.shader_time_start);
1782 }
1783
1784 void
1785 fs_generator::enable_debug(const char *shader_name)
1786 {
1787 debug_flag = true;
1788 this->shader_name = shader_name;
1789 }
1790
1791 int
1792 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1793 {
1794 /* align to 64 byte boundary. */
1795 while (p->next_insn_offset % 64)
1796 brw_NOP(p);
1797
1798 this->dispatch_width = dispatch_width;
1799
1800 int start_offset = p->next_insn_offset;
1801 int spill_count = 0, fill_count = 0;
1802 int loop_count = 0;
1803
1804 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1805
1806 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1807 struct brw_reg src[3], dst;
1808 unsigned int last_insn_offset = p->next_insn_offset;
1809 bool multiple_instructions_emitted = false;
1810
1811 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1812 * "Register Region Restrictions" section: for BDW, SKL:
1813 *
1814 * "A POW/FDIV operation must not be followed by an instruction
1815 * that requires two destination registers."
1816 *
1817 * The documentation is often lacking annotations for Atom parts,
1818 * and empirically this affects CHV as well.
1819 */
1820 if (devinfo->gen >= 8 &&
1821 devinfo->gen <= 9 &&
1822 p->nr_insn > 1 &&
1823 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1824 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1825 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1826 brw_NOP(p);
1827 last_insn_offset = p->next_insn_offset;
1828 }
1829
1830 if (unlikely(debug_flag))
1831 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1832
1833 /* If the instruction writes to more than one register, it needs to be
1834 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1835 * hardware figures out by itself what the right compression mode is,
1836 * but we still need to know whether the instruction is compressed to
1837 * set up the source register regions appropriately.
1838 *
1839 * XXX - This is wrong for instructions that write a single register but
1840 * read more than one which should strictly speaking be treated as
1841 * compressed. For instructions that don't write any registers it
1842 * relies on the destination being a null register of the correct
1843 * type and regioning so the instruction is considered compressed
1844 * or not accordingly.
1845 */
1846 const bool compressed =
1847 inst->dst.component_size(inst->exec_size) > REG_SIZE;
1848 brw_set_default_compression(p, compressed);
1849 brw_set_default_group(p, inst->group);
1850
1851 for (unsigned int i = 0; i < inst->sources; i++) {
1852 src[i] = brw_reg_from_fs_reg(devinfo, inst,
1853 &inst->src[i], compressed);
1854 /* The accumulator result appears to get used for the
1855 * conditional modifier generation. When negating a UD
1856 * value, there is a 33rd bit generated for the sign in the
1857 * accumulator value, so now you can't check, for example,
1858 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1859 */
1860 assert(!inst->conditional_mod ||
1861 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1862 !inst->src[i].negate);
1863 }
1864 dst = brw_reg_from_fs_reg(devinfo, inst,
1865 &inst->dst, compressed);
1866
1867 brw_set_default_access_mode(p, BRW_ALIGN_1);
1868 brw_set_default_predicate_control(p, inst->predicate);
1869 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1870 brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
1871 brw_set_default_saturate(p, inst->saturate);
1872 brw_set_default_mask_control(p, inst->force_writemask_all);
1873 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1874
1875 unsigned exec_size = inst->exec_size;
1876 if (devinfo->gen == 7 && !devinfo->is_haswell &&
1877 (get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) {
1878 exec_size *= 2;
1879 }
1880
1881 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1882
1883 assert(inst->force_writemask_all || inst->exec_size >= 4);
1884 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
1885 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1886 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1887
1888 switch (inst->opcode) {
1889 case BRW_OPCODE_MOV:
1890 brw_MOV(p, dst, src[0]);
1891 break;
1892 case BRW_OPCODE_ADD:
1893 brw_ADD(p, dst, src[0], src[1]);
1894 break;
1895 case BRW_OPCODE_MUL:
1896 brw_MUL(p, dst, src[0], src[1]);
1897 break;
1898 case BRW_OPCODE_AVG:
1899 brw_AVG(p, dst, src[0], src[1]);
1900 break;
1901 case BRW_OPCODE_MACH:
1902 brw_MACH(p, dst, src[0], src[1]);
1903 break;
1904
1905 case BRW_OPCODE_LINE:
1906 brw_LINE(p, dst, src[0], src[1]);
1907 break;
1908
1909 case BRW_OPCODE_MAD:
1910 assert(devinfo->gen >= 6);
1911 if (devinfo->gen < 10)
1912 brw_set_default_access_mode(p, BRW_ALIGN_16);
1913 brw_MAD(p, dst, src[0], src[1], src[2]);
1914 break;
1915
1916 case BRW_OPCODE_LRP:
1917 assert(devinfo->gen >= 6 && devinfo->gen <= 10);
1918 if (devinfo->gen < 10)
1919 brw_set_default_access_mode(p, BRW_ALIGN_16);
1920 brw_LRP(p, dst, src[0], src[1], src[2]);
1921 break;
1922
1923 case BRW_OPCODE_FRC:
1924 brw_FRC(p, dst, src[0]);
1925 break;
1926 case BRW_OPCODE_RNDD:
1927 brw_RNDD(p, dst, src[0]);
1928 break;
1929 case BRW_OPCODE_RNDE:
1930 brw_RNDE(p, dst, src[0]);
1931 break;
1932 case BRW_OPCODE_RNDZ:
1933 brw_RNDZ(p, dst, src[0]);
1934 break;
1935
1936 case BRW_OPCODE_AND:
1937 brw_AND(p, dst, src[0], src[1]);
1938 break;
1939 case BRW_OPCODE_OR:
1940 brw_OR(p, dst, src[0], src[1]);
1941 break;
1942 case BRW_OPCODE_XOR:
1943 brw_XOR(p, dst, src[0], src[1]);
1944 break;
1945 case BRW_OPCODE_NOT:
1946 brw_NOT(p, dst, src[0]);
1947 break;
1948 case BRW_OPCODE_ASR:
1949 brw_ASR(p, dst, src[0], src[1]);
1950 break;
1951 case BRW_OPCODE_SHR:
1952 brw_SHR(p, dst, src[0], src[1]);
1953 break;
1954 case BRW_OPCODE_SHL:
1955 brw_SHL(p, dst, src[0], src[1]);
1956 break;
1957 case BRW_OPCODE_F32TO16:
1958 assert(devinfo->gen >= 7);
1959 brw_F32TO16(p, dst, src[0]);
1960 break;
1961 case BRW_OPCODE_F16TO32:
1962 assert(devinfo->gen >= 7);
1963 brw_F16TO32(p, dst, src[0]);
1964 break;
1965 case BRW_OPCODE_CMP:
1966 if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell &&
1967 dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1968 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1969 * implemented in the compiler is not sufficient. Overriding the
1970 * type when the destination is the null register is necessary but
1971 * not sufficient by itself.
1972 */
1973 assert(dst.nr == BRW_ARF_NULL);
1974 dst.type = BRW_REGISTER_TYPE_D;
1975 }
1976 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1977 break;
1978 case BRW_OPCODE_SEL:
1979 brw_SEL(p, dst, src[0], src[1]);
1980 break;
1981 case BRW_OPCODE_CSEL:
1982 assert(devinfo->gen >= 8);
1983 if (devinfo->gen < 10)
1984 brw_set_default_access_mode(p, BRW_ALIGN_16);
1985 brw_CSEL(p, dst, src[0], src[1], src[2]);
1986 break;
1987 case BRW_OPCODE_BFREV:
1988 assert(devinfo->gen >= 7);
1989 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1990 retype(src[0], BRW_REGISTER_TYPE_UD));
1991 break;
1992 case BRW_OPCODE_FBH:
1993 assert(devinfo->gen >= 7);
1994 brw_FBH(p, retype(dst, src[0].type), src[0]);
1995 break;
1996 case BRW_OPCODE_FBL:
1997 assert(devinfo->gen >= 7);
1998 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
1999 retype(src[0], BRW_REGISTER_TYPE_UD));
2000 break;
2001 case BRW_OPCODE_LZD:
2002 brw_LZD(p, dst, src[0]);
2003 break;
2004 case BRW_OPCODE_CBIT:
2005 assert(devinfo->gen >= 7);
2006 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
2007 retype(src[0], BRW_REGISTER_TYPE_UD));
2008 break;
2009 case BRW_OPCODE_ADDC:
2010 assert(devinfo->gen >= 7);
2011 brw_ADDC(p, dst, src[0], src[1]);
2012 break;
2013 case BRW_OPCODE_SUBB:
2014 assert(devinfo->gen >= 7);
2015 brw_SUBB(p, dst, src[0], src[1]);
2016 break;
2017 case BRW_OPCODE_MAC:
2018 brw_MAC(p, dst, src[0], src[1]);
2019 break;
2020
2021 case BRW_OPCODE_BFE:
2022 assert(devinfo->gen >= 7);
2023 if (devinfo->gen < 10)
2024 brw_set_default_access_mode(p, BRW_ALIGN_16);
2025 brw_BFE(p, dst, src[0], src[1], src[2]);
2026 break;
2027
2028 case BRW_OPCODE_BFI1:
2029 assert(devinfo->gen >= 7);
2030 brw_BFI1(p, dst, src[0], src[1]);
2031 break;
2032 case BRW_OPCODE_BFI2:
2033 assert(devinfo->gen >= 7);
2034 if (devinfo->gen < 10)
2035 brw_set_default_access_mode(p, BRW_ALIGN_16);
2036 brw_BFI2(p, dst, src[0], src[1], src[2]);
2037 break;
2038
2039 case BRW_OPCODE_IF:
2040 if (inst->src[0].file != BAD_FILE) {
2041 /* The instruction has an embedded compare (only allowed on gen6) */
2042 assert(devinfo->gen == 6);
2043 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
2044 } else {
2045 brw_IF(p, brw_inst_exec_size(devinfo, p->current));
2046 }
2047 break;
2048
2049 case BRW_OPCODE_ELSE:
2050 brw_ELSE(p);
2051 break;
2052 case BRW_OPCODE_ENDIF:
2053 brw_ENDIF(p);
2054 break;
2055
2056 case BRW_OPCODE_DO:
2057 brw_DO(p, brw_inst_exec_size(devinfo, p->current));
2058 break;
2059
2060 case BRW_OPCODE_BREAK:
2061 brw_BREAK(p);
2062 break;
2063 case BRW_OPCODE_CONTINUE:
2064 brw_CONT(p);
2065 break;
2066
2067 case BRW_OPCODE_WHILE:
2068 brw_WHILE(p);
2069 loop_count++;
2070 break;
2071
2072 case SHADER_OPCODE_RCP:
2073 case SHADER_OPCODE_RSQ:
2074 case SHADER_OPCODE_SQRT:
2075 case SHADER_OPCODE_EXP2:
2076 case SHADER_OPCODE_LOG2:
2077 case SHADER_OPCODE_SIN:
2078 case SHADER_OPCODE_COS:
2079 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2080 if (devinfo->gen >= 6) {
2081 assert(inst->mlen == 0);
2082 assert(devinfo->gen >= 7 || inst->exec_size == 8);
2083 gen6_math(p, dst, brw_math_function(inst->opcode),
2084 src[0], brw_null_reg());
2085 } else {
2086 assert(inst->mlen >= 1);
2087 assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
2088 gen4_math(p, dst,
2089 brw_math_function(inst->opcode),
2090 inst->base_mrf, src[0],
2091 BRW_MATH_PRECISION_FULL);
2092 }
2093 break;
2094 case SHADER_OPCODE_INT_QUOTIENT:
2095 case SHADER_OPCODE_INT_REMAINDER:
2096 case SHADER_OPCODE_POW:
2097 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2098 if (devinfo->gen >= 6) {
2099 assert(inst->mlen == 0);
2100 assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
2101 inst->exec_size == 8);
2102 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2103 } else {
2104 assert(inst->mlen >= 1);
2105 assert(inst->exec_size == 8);
2106 gen4_math(p, dst, brw_math_function(inst->opcode),
2107 inst->base_mrf, src[0],
2108 BRW_MATH_PRECISION_FULL);
2109 }
2110 break;
2111 case FS_OPCODE_LINTERP:
2112 multiple_instructions_emitted = generate_linterp(inst, dst, src);
2113 break;
2114 case FS_OPCODE_PIXEL_X:
2115 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2116 src[0].subnr = 0 * type_sz(src[0].type);
2117 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2118 break;
2119 case FS_OPCODE_PIXEL_Y:
2120 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2121 src[0].subnr = 4 * type_sz(src[0].type);
2122 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2123 break;
2124 case SHADER_OPCODE_GET_BUFFER_SIZE:
2125 generate_get_buffer_size(inst, dst, src[0], src[1]);
2126 break;
2127 case SHADER_OPCODE_TEX:
2128 case FS_OPCODE_TXB:
2129 case SHADER_OPCODE_TXD:
2130 case SHADER_OPCODE_TXF:
2131 case SHADER_OPCODE_TXF_LZ:
2132 case SHADER_OPCODE_TXF_CMS:
2133 case SHADER_OPCODE_TXF_CMS_W:
2134 case SHADER_OPCODE_TXF_UMS:
2135 case SHADER_OPCODE_TXF_MCS:
2136 case SHADER_OPCODE_TXL:
2137 case SHADER_OPCODE_TXL_LZ:
2138 case SHADER_OPCODE_TXS:
2139 case SHADER_OPCODE_LOD:
2140 case SHADER_OPCODE_TG4:
2141 case SHADER_OPCODE_TG4_OFFSET:
2142 case SHADER_OPCODE_SAMPLEINFO:
2143 generate_tex(inst, dst, src[0], src[1], src[2]);
2144 break;
2145 case FS_OPCODE_DDX_COARSE:
2146 case FS_OPCODE_DDX_FINE:
2147 generate_ddx(inst, dst, src[0]);
2148 break;
2149 case FS_OPCODE_DDY_COARSE:
2150 case FS_OPCODE_DDY_FINE:
2151 generate_ddy(inst, dst, src[0]);
2152 break;
2153
2154 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2155 generate_scratch_write(inst, src[0]);
2156 spill_count++;
2157 break;
2158
2159 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2160 generate_scratch_read(inst, dst);
2161 fill_count++;
2162 break;
2163
2164 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2165 generate_scratch_read_gen7(inst, dst);
2166 fill_count++;
2167 break;
2168
2169 case SHADER_OPCODE_MOV_INDIRECT:
2170 generate_mov_indirect(inst, dst, src[0], src[1]);
2171 break;
2172
2173 case SHADER_OPCODE_URB_READ_SIMD8:
2174 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2175 generate_urb_read(inst, dst, src[0]);
2176 break;
2177
2178 case SHADER_OPCODE_URB_WRITE_SIMD8:
2179 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2180 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2181 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2182 generate_urb_write(inst, src[0]);
2183 break;
2184
2185 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2186 assert(inst->force_writemask_all);
2187 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2188 break;
2189
2190 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2191 assert(inst->force_writemask_all);
2192 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2193 break;
2194
2195 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
2196 generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
2197 break;
2198
2199 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2200 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2201 break;
2202
2203 case FS_OPCODE_REP_FB_WRITE:
2204 case FS_OPCODE_FB_WRITE:
2205 generate_fb_write(inst, src[0]);
2206 break;
2207
2208 case FS_OPCODE_FB_READ:
2209 generate_fb_read(inst, dst, src[0]);
2210 break;
2211
2212 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2213 generate_mov_dispatch_to_flags(inst);
2214 break;
2215
2216 case FS_OPCODE_DISCARD_JUMP:
2217 generate_discard_jump(inst);
2218 break;
2219
2220 case SHADER_OPCODE_SHADER_TIME_ADD:
2221 generate_shader_time_add(inst, src[0], src[1], src[2]);
2222 break;
2223
2224 case SHADER_OPCODE_UNTYPED_ATOMIC:
2225 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2226 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2227 inst->mlen, !inst->dst.is_null(),
2228 inst->header_size);
2229 break;
2230
2231 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2232 assert(!inst->header_size);
2233 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2234 brw_untyped_surface_read(p, dst, src[0], src[1],
2235 inst->mlen, src[2].ud);
2236 break;
2237
2238 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2239 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2240 brw_untyped_surface_write(p, src[0], src[1],
2241 inst->mlen, src[2].ud,
2242 inst->header_size);
2243 break;
2244
2245 case SHADER_OPCODE_BYTE_SCATTERED_READ:
2246 assert(!inst->header_size);
2247 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2248 brw_byte_scattered_read(p, dst, src[0], src[1],
2249 inst->mlen, src[2].ud);
2250 break;
2251
2252 case SHADER_OPCODE_BYTE_SCATTERED_WRITE:
2253 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2254 brw_byte_scattered_write(p, src[0], src[1],
2255 inst->mlen, src[2].ud,
2256 inst->header_size);
2257 break;
2258
2259 case SHADER_OPCODE_TYPED_ATOMIC:
2260 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2261 brw_typed_atomic(p, dst, src[0], src[1],
2262 src[2].ud, inst->mlen, !inst->dst.is_null(),
2263 inst->header_size);
2264 break;
2265
2266 case SHADER_OPCODE_TYPED_SURFACE_READ:
2267 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2268 brw_typed_surface_read(p, dst, src[0], src[1],
2269 inst->mlen, src[2].ud,
2270 inst->header_size);
2271 break;
2272
2273 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2274 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2275 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud,
2276 inst->header_size);
2277 break;
2278
2279 case SHADER_OPCODE_MEMORY_FENCE:
2280 brw_memory_fence(p, dst);
2281 break;
2282
2283 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
2284 const struct brw_reg mask =
2285 brw_stage_has_packed_dispatch(devinfo, stage,
2286 prog_data) ? brw_imm_ud(~0u) :
2287 stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() :
2288 brw_dmask_reg();
2289 brw_find_live_channel(p, dst, mask);
2290 break;
2291 }
2292
2293 case SHADER_OPCODE_BROADCAST:
2294 assert(inst->force_writemask_all);
2295 brw_broadcast(p, dst, src[0], src[1]);
2296 break;
2297
2298 case SHADER_OPCODE_SHUFFLE:
2299 generate_shuffle(inst, dst, src[0], src[1]);
2300 break;
2301
2302 case SHADER_OPCODE_SEL_EXEC:
2303 assert(inst->force_writemask_all);
2304 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
2305 brw_MOV(p, dst, src[1]);
2306 brw_set_default_mask_control(p, BRW_MASK_ENABLE);
2307 brw_MOV(p, dst, src[0]);
2308 break;
2309
2310 case SHADER_OPCODE_QUAD_SWIZZLE:
2311 /* This only works on 8-wide 32-bit values */
2312 assert(inst->exec_size == 8);
2313 assert(type_sz(src[0].type) == 4);
2314 assert(inst->force_writemask_all);
2315 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2316 assert(src[1].type == BRW_REGISTER_TYPE_UD);
2317
2318 if (src[0].file == BRW_IMMEDIATE_VALUE ||
2319 (src[0].vstride == 0 && src[0].hstride == 0)) {
2320 /* The value is uniform across all channels */
2321 brw_MOV(p, dst, src[0]);
2322 } else {
2323 brw_set_default_access_mode(p, BRW_ALIGN_16);
2324 struct brw_reg swiz_src = stride(src[0], 4, 4, 1);
2325 swiz_src.swizzle = inst->src[1].ud;
2326 brw_MOV(p, dst, swiz_src);
2327 }
2328 break;
2329
2330 case SHADER_OPCODE_CLUSTER_BROADCAST: {
2331 assert(src[0].type == dst.type);
2332 assert(!src[0].negate && !src[0].abs);
2333 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2334 assert(src[1].type == BRW_REGISTER_TYPE_UD);
2335 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2336 assert(src[2].type == BRW_REGISTER_TYPE_UD);
2337 const unsigned component = src[1].ud;
2338 const unsigned cluster_size = src[2].ud;
2339 struct brw_reg strided = stride(suboffset(src[0], component),
2340 cluster_size, cluster_size, 0);
2341 if (type_sz(src[0].type) > 4 &&
2342 (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
2343 /* IVB has an issue (which we found empirically) where it reads
2344 * two address register components per channel for indirectly
2345 * addressed 64-bit sources.
2346 *
2347 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2348 *
2349 * "When source or destination datatype is 64b or operation is
2350 * integer DWord multiply, indirect addressing must not be
2351 * used."
2352 *
2353 * To work around both of these, we do two integer MOVs insead of
2354 * one 64-bit MOV. Because no double value should ever cross a
2355 * register boundary, it's safe to use the immediate offset in the
2356 * indirect here to handle adding 4 bytes to the offset and avoid
2357 * the extra ADD to the register file.
2358 */
2359 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
2360 subscript(strided, BRW_REGISTER_TYPE_D, 0));
2361 brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
2362 subscript(strided, BRW_REGISTER_TYPE_D, 1));
2363 } else {
2364 brw_MOV(p, dst, strided);
2365 }
2366 break;
2367 }
2368
2369 case FS_OPCODE_SET_SAMPLE_ID:
2370 generate_set_sample_id(inst, dst, src[0], src[1]);
2371 break;
2372
2373 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2374 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2375 break;
2376
2377 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2378 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2379 generate_unpack_half_2x16_split(inst, dst, src[0]);
2380 break;
2381
2382 case FS_OPCODE_PLACEHOLDER_HALT:
2383 /* This is the place where the final HALT needs to be inserted if
2384 * we've emitted any discards. If not, this will emit no code.
2385 */
2386 if (!patch_discard_jumps_to_fb_writes()) {
2387 if (unlikely(debug_flag)) {
2388 disasm_info->use_tail = true;
2389 }
2390 }
2391 break;
2392
2393 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2394 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2395 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2396 break;
2397
2398 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2399 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2400 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2401 break;
2402
2403 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2404 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2405 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2406 break;
2407
2408 case CS_OPCODE_CS_TERMINATE:
2409 generate_cs_terminate(inst, src[0]);
2410 break;
2411
2412 case SHADER_OPCODE_BARRIER:
2413 generate_barrier(inst, src[0]);
2414 break;
2415
2416 case BRW_OPCODE_DIM:
2417 assert(devinfo->is_haswell);
2418 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2419 assert(dst.type == BRW_REGISTER_TYPE_DF);
2420 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2421 break;
2422
2423 case SHADER_OPCODE_RND_MODE:
2424 assert(src[0].file == BRW_IMMEDIATE_VALUE);
2425 brw_rounding_mode(p, (brw_rnd_mode) src[0].d);
2426 break;
2427
2428 default:
2429 unreachable("Unsupported opcode");
2430
2431 case SHADER_OPCODE_LOAD_PAYLOAD:
2432 unreachable("Should be lowered by lower_load_payload()");
2433 }
2434
2435 if (multiple_instructions_emitted)
2436 continue;
2437
2438 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2439 assert(p->next_insn_offset == last_insn_offset + 16 ||
2440 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2441 "emitting more than 1 instruction");
2442
2443 brw_inst *last = &p->store[last_insn_offset / 16];
2444
2445 if (inst->conditional_mod)
2446 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2447 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2448 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2449 }
2450 }
2451
2452 brw_set_uip_jip(p, start_offset);
2453
2454 /* end of program sentinel */
2455 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2456
2457 #ifndef NDEBUG
2458 bool validated =
2459 #else
2460 if (unlikely(debug_flag))
2461 #endif
2462 brw_validate_instructions(devinfo, p->store,
2463 start_offset,
2464 p->next_insn_offset,
2465 disasm_info);
2466
2467 int before_size = p->next_insn_offset - start_offset;
2468 brw_compact_instructions(p, start_offset, disasm_info);
2469 int after_size = p->next_insn_offset - start_offset;
2470
2471 if (unlikely(debug_flag)) {
2472 fprintf(stderr, "Native code for %s\n"
2473 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2474 " bytes (%.0f%%)\n",
2475 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2476 spill_count, fill_count, promoted_constants, before_size, after_size,
2477 100.0f * (before_size - after_size) / before_size);
2478
2479 dump_assembly(p->store, disasm_info);
2480 }
2481 ralloc_free(disasm_info);
2482 assert(validated);
2483
2484 compiler->shader_debug_log(log_data,
2485 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2486 "%d:%d spills:fills, Promoted %u constants, "
2487 "compacted %d to %d bytes.",
2488 _mesa_shader_stage_to_abbrev(stage),
2489 dispatch_width, before_size / 16,
2490 loop_count, cfg->cycle_count, spill_count,
2491 fill_count, promoted_constants, before_size,
2492 after_size);
2493
2494 return start_offset;
2495 }
2496
2497 const unsigned *
2498 fs_generator::get_assembly()
2499 {
2500 return brw_get_program(p, &prog_data->program_size);
2501 }