2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
178 struct brw_stage_prog_data
*prog_data
,
179 unsigned promoted_constants
,
180 bool runtime_check_aads_emit
,
181 gl_shader_stage stage
)
183 : compiler(compiler
), log_data(log_data
),
184 devinfo(compiler
->devinfo
),
185 prog_data(prog_data
),
186 promoted_constants(promoted_constants
),
187 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
188 stage(stage
), mem_ctx(mem_ctx
)
190 p
= rzalloc(mem_ctx
, struct brw_codegen
);
191 brw_init_codegen(devinfo
, p
, mem_ctx
);
193 /* In the FS code generator, we are very careful to ensure that we always
194 * set the right execution size so we don't need the EU code to "help" us
195 * by trying to infer it. Sometimes, it infers the wrong thing.
197 p
->automatic_exec_sizes
= false;
200 fs_generator::~fs_generator()
204 class ip_record
: public exec_node
{
206 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
217 fs_generator::patch_discard_jumps_to_fb_writes()
219 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
222 int scale
= brw_jump_scale(p
->devinfo
);
224 /* There is a somewhat strange undocumented requirement of using
225 * HALT, according to the simulator. If some channel has HALTed to
226 * a particular UIP, then by the end of the program, every channel
227 * must have HALTed to that UIP. Furthermore, the tracking is a
228 * stack, so you can't do the final halt of a UIP after starting
229 * halting to a new UIP.
231 * Symptoms of not emitting this instruction on actual hardware
232 * included GPU hangs and sparkly rendering on the piglit discard
235 brw_inst
*last_halt
= gen6_HALT(p
);
236 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
237 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
241 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
242 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
244 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
245 /* HALT takes a half-instruction distance from the pre-incremented IP. */
246 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
249 this->discard_halt_patches
.make_empty();
254 fs_generator::generate_send(fs_inst
*inst
,
257 struct brw_reg ex_desc
,
258 struct brw_reg payload
,
259 struct brw_reg payload2
)
261 /* SENDS not yet supported */
262 assert(ex_desc
.file
== BRW_IMMEDIATE_VALUE
&& ex_desc
.d
== 0);
263 assert(payload2
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
264 payload2
.nr
== BRW_ARF_NULL
);
266 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
267 dst
.nr
== BRW_ARF_NULL
;
268 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
270 uint32_t desc_imm
= inst
->desc
|
271 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
273 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
);
275 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, inst
->eot
);
277 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
281 fs_generator::fire_fb_write(fs_inst
*inst
,
282 struct brw_reg payload
,
283 struct brw_reg implied_header
,
286 uint32_t msg_control
;
288 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
290 if (devinfo
->gen
< 6) {
291 brw_push_insn_state(p
);
292 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
293 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
294 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
295 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
296 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
297 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
298 brw_pop_insn_state(p
);
301 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
302 assert(inst
->group
== 0 && inst
->exec_size
== 16);
303 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
305 } else if (prog_data
->dual_src_blend
) {
306 assert(inst
->exec_size
== 8);
308 if (inst
->group
% 16 == 0)
309 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
310 else if (inst
->group
% 16 == 8)
311 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
313 unreachable("Invalid dual-source FB write instruction group");
316 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
318 if (inst
->exec_size
== 16)
319 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
320 else if (inst
->exec_size
== 8)
321 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
323 unreachable("Invalid FB write execution size");
326 /* We assume render targets start at 0, because headerless FB write
327 * messages set "Render Target Index" to 0. Using a different binding
328 * table index would make it impossible to use headerless messages.
330 const uint32_t surf_index
= inst
->target
;
332 brw_inst
*insn
= brw_fb_WRITE(p
,
334 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
341 inst
->header_size
!= 0);
343 if (devinfo
->gen
>= 6)
344 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
348 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
350 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
351 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
354 const struct brw_reg implied_header
=
355 devinfo
->gen
< 6 ? payload
: brw_null_reg();
357 if (inst
->base_mrf
>= 0)
358 payload
= brw_message_reg(inst
->base_mrf
);
360 if (!runtime_check_aads_emit
) {
361 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
363 /* This can only happen in gen < 6 */
364 assert(devinfo
->gen
< 6);
366 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
368 /* Check runtime bit to detect if we have to send AA data or not */
369 brw_push_insn_state(p
);
370 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
371 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
374 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
376 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
378 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
379 brw_pop_insn_state(p
);
381 /* Don't send AA data */
382 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
384 brw_land_fwd_jump(p
, jmp
);
385 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
390 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
391 struct brw_reg payload
)
393 assert(inst
->size_written
% REG_SIZE
== 0);
394 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
395 /* We assume that render targets start at binding table index 0. */
396 const unsigned surf_index
= inst
->target
;
398 gen9_fb_READ(p
, dst
, payload
, surf_index
,
399 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
400 prog_data
->persample_dispatch
);
404 fs_generator::generate_mov_indirect(fs_inst
*inst
,
407 struct brw_reg indirect_byte_offset
)
409 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
410 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
411 assert(!reg
.abs
&& !reg
.negate
);
412 assert(reg
.type
== dst
.type
);
414 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
416 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
417 imm_byte_offset
+= indirect_byte_offset
.ud
;
419 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
420 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
421 brw_MOV(p
, dst
, reg
);
423 /* Prior to Broadwell, there are only 8 address registers. */
424 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
426 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
427 struct brw_reg addr
= vec8(brw_address_reg(0));
429 /* The destination stride of an instruction (in bytes) must be greater
430 * than or equal to the size of the rest of the instruction. Since the
431 * address register is of type UW, we can't use a D-type instruction.
432 * In order to get around this, re retype to UW and use a stride.
434 indirect_byte_offset
=
435 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
437 /* There are a number of reasons why we don't use the base offset here.
438 * One reason is that the field is only 9 bits which means we can only
439 * use it to access the first 16 GRFs. Also, from the Haswell PRM
440 * section "Register Region Restrictions":
442 * "The lower bits of the AddressImmediate must not overflow to
443 * change the register address. The lower 5 bits of Address
444 * Immediate when added to lower 5 bits of address register gives
445 * the sub-register offset. The upper bits of Address Immediate
446 * when added to upper bits of address register gives the register
447 * address. Any overflow from sub-register offset is dropped."
449 * Since the indirect may cause us to cross a register boundary, this
450 * makes the base offset almost useless. We could try and do something
451 * clever where we use a actual base offset if base_offset % 32 == 0 but
452 * that would mean we were generating different code depending on the
453 * base offset. Instead, for the sake of consistency, we'll just do the
454 * add ourselves. This restriction is only listed in the Haswell PRM
455 * but empirical testing indicates that it applies on all older
456 * generations and is lifted on Broadwell.
458 * In the end, while base_offset is nice to look at in the generated
459 * code, using it saves us 0 instructions and would require quite a bit
460 * of case-by-case work. It's just not worth it.
462 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
464 if (type_sz(reg
.type
) > 4 &&
465 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
466 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
467 !devinfo
->has_64bit_types
)) {
468 /* IVB has an issue (which we found empirically) where it reads two
469 * address register components per channel for indirectly addressed
472 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
474 * "When source or destination datatype is 64b or operation is
475 * integer DWord multiply, indirect addressing must not be used."
477 * To work around both of these, we do two integer MOVs insead of one
478 * 64-bit MOV. Because no double value should ever cross a register
479 * boundary, it's safe to use the immediate offset in the indirect
480 * here to handle adding 4 bytes to the offset and avoid the extra
481 * ADD to the register file.
483 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
484 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
485 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
486 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
488 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
490 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
492 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
493 !inst
->get_next()->is_tail_sentinel() &&
494 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
495 /* From the Sandybridge PRM:
497 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
498 * instruction that “indexed/indirect” source AND is followed
499 * by a send, the instruction requires a “Switch”. This is to
500 * avoid race condition where send may dispatch before MRF is
503 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
510 fs_generator::generate_shuffle(fs_inst
*inst
,
515 /* Ivy bridge has some strange behavior that makes this a real pain to
516 * implement for 64-bit values so we just don't bother.
518 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
520 /* Because we're using the address register, we're limited to 8-wide
521 * execution on gen7. On gen8, we're limited to 16-wide by the address
522 * register file and 8-wide for 64-bit types. We could try and make this
523 * instruction splittable higher up in the compiler but that gets weird
524 * because it reads all of the channels regardless of execution size. It's
525 * easier just to split it here.
527 const unsigned lower_width
=
528 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
529 8 : MIN2(16, inst
->exec_size
);
531 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
532 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
533 brw_set_default_group(p
, group
);
535 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
536 idx
.file
== BRW_IMMEDIATE_VALUE
) {
537 /* Trivial, the source is already uniform or the index is a constant.
538 * We will typically not get here if the optimizer is doing its job,
539 * but asserting would be mean.
541 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
542 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
544 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
545 struct brw_reg addr
= vec8(brw_address_reg(0));
547 struct brw_reg group_idx
= suboffset(idx
, group
);
549 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
550 /* Things get grumpy if the register is too wide. */
555 assert(type_sz(group_idx
.type
) <= 4);
556 if (type_sz(group_idx
.type
) == 4) {
557 /* The destination stride of an instruction (in bytes) must be
558 * greater than or equal to the size of the rest of the
559 * instruction. Since the address register is of type UW, we
560 * can't use a D-type instruction. In order to get around this,
561 * re retype to UW and use a stride.
563 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
566 /* Take into account the component size and horizontal stride. */
567 assert(src
.vstride
== src
.hstride
+ src
.width
);
568 brw_SHL(p
, addr
, group_idx
,
569 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
572 /* Add on the register start offset */
573 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
575 if (type_sz(src
.type
) > 4 &&
576 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
577 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
578 /* IVB has an issue (which we found empirically) where it reads
579 * two address register components per channel for indirectly
580 * addressed 64-bit sources.
582 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
584 * "When source or destination datatype is 64b or operation is
585 * integer DWord multiply, indirect addressing must not be
588 * To work around both of these, we do two integer MOVs insead of
589 * one 64-bit MOV. Because no double value should ever cross a
590 * register boundary, it's safe to use the immediate offset in the
591 * indirect here to handle adding 4 bytes to the offset and avoid
592 * the extra ADD to the register file.
594 struct brw_reg gdst
= suboffset(dst
, group
);
595 struct brw_reg dst_d
= retype(spread(gdst
, 2),
596 BRW_REGISTER_TYPE_D
);
598 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
599 brw_MOV(p
, byte_offset(dst_d
, 4),
600 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
602 brw_MOV(p
, suboffset(dst
, group
),
603 retype(brw_VxH_indirect(0, 0), src
.type
));
610 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
611 struct brw_reg dst
, struct brw_reg src
,
614 /* Requires a quad. */
615 assert(inst
->exec_size
>= 4);
617 if (src
.file
== BRW_IMMEDIATE_VALUE
||
618 has_scalar_region(src
)) {
619 /* The value is uniform across all channels */
620 brw_MOV(p
, dst
, src
);
622 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
623 /* This only works on 8-wide 32-bit values */
624 assert(inst
->exec_size
== 8);
625 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
626 assert(src
.vstride
== src
.width
+ 1);
627 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
628 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
629 swiz_src
.swizzle
= swiz
;
630 brw_MOV(p
, dst
, swiz_src
);
633 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
634 assert(src
.vstride
== src
.width
+ 1);
635 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
638 case BRW_SWIZZLE_XXXX
:
639 case BRW_SWIZZLE_YYYY
:
640 case BRW_SWIZZLE_ZZZZ
:
641 case BRW_SWIZZLE_WWWW
:
642 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
645 case BRW_SWIZZLE_XXZZ
:
646 case BRW_SWIZZLE_YYWW
:
647 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
650 case BRW_SWIZZLE_XYXY
:
651 case BRW_SWIZZLE_ZWZW
:
652 assert(inst
->exec_size
== 4);
653 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
657 assert(inst
->force_writemask_all
);
658 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
660 for (unsigned c
= 0; c
< 4; c
++) {
661 brw_inst
*insn
= brw_MOV(
662 p
, stride(suboffset(dst
, c
),
663 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
664 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
666 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
667 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
676 fs_generator::generate_urb_read(fs_inst
*inst
,
678 struct brw_reg header
)
680 assert(inst
->size_written
% REG_SIZE
== 0);
681 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
682 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
684 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
685 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
686 brw_set_src0(p
, send
, header
);
687 brw_set_src1(p
, send
, brw_imm_ud(0u));
689 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
690 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
692 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
693 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
695 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
696 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
697 brw_inst_set_header_present(p
->devinfo
, send
, true);
698 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
702 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
706 /* WaClearTDRRegBeforeEOTForNonPS.
708 * WA: Clear tdr register before send EOT in all non-PS shader kernels
710 * mov(8) tdr0:ud 0x0:ud {NoMask}"
712 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
713 brw_push_insn_state(p
);
714 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
715 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
716 brw_pop_insn_state(p
);
719 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
721 brw_set_dest(p
, insn
, brw_null_reg());
722 brw_set_src0(p
, insn
, payload
);
723 brw_set_src1(p
, insn
, brw_imm_ud(0u));
725 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
726 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
728 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
729 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
730 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
732 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
733 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
734 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
736 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
737 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
738 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
739 brw_inst_set_header_present(p
->devinfo
, insn
, true);
740 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
744 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
746 struct brw_inst
*insn
;
748 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
750 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
751 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
752 brw_set_src1(p
, insn
, brw_imm_ud(0u));
754 /* Terminate a compute shader by sending a message to the thread spawner.
756 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
757 brw_inst_set_mlen(devinfo
, insn
, 1);
758 brw_inst_set_rlen(devinfo
, insn
, 0);
759 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
760 brw_inst_set_header_present(devinfo
, insn
, false);
762 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
763 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
765 /* Note that even though the thread has a URB resource associated with it,
766 * we set the "do not dereference URB" bit, because the URB resource is
767 * managed by the fixed-function unit, so it will free it automatically.
769 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
771 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
775 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
782 fs_generator::generate_linterp(fs_inst
*inst
,
783 struct brw_reg dst
, struct brw_reg
*src
)
787 * -----------------------------------
788 * | src1+0 | src1+1 | src1+2 | src1+3 |
789 * |-----------------------------------|
790 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
791 * -----------------------------------
793 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
795 * -----------------------------------
796 * | src1+0 | src1+1 | src1+2 | src1+3 |
797 * |-----------------------------------|
798 * |(x0, x1)|(y0, y1)| | | in SIMD8
799 * |-----------------------------------|
800 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
801 * -----------------------------------
803 * See also: emit_interpolation_setup_gen4().
805 struct brw_reg delta_x
= src
[0];
806 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
807 struct brw_reg interp
= src
[1];
810 if (devinfo
->gen
>= 11) {
811 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF
);
812 struct brw_reg dwP
= suboffset(interp
, 0);
813 struct brw_reg dwQ
= suboffset(interp
, 1);
814 struct brw_reg dwR
= suboffset(interp
, 3);
816 brw_push_insn_state(p
);
817 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
819 if (inst
->exec_size
== 8) {
820 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
821 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_y
, 0), dwQ
);
823 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
825 /* brw_set_default_saturate() is called before emitting instructions,
826 * so the saturate bit is set in each instruction, so we need to unset
827 * it on the first instruction of each pair.
829 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
831 brw_set_default_group(p
, inst
->group
);
832 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
833 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_x
, 1), dwQ
);
835 brw_set_default_group(p
, inst
->group
+ 8);
836 i
[2] = brw_MAD(p
, acc
, dwR
, offset(delta_y
, 0), dwP
);
837 i
[3] = brw_MAD(p
, offset(dst
, 1), acc
, offset(delta_y
, 1), dwQ
);
839 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
840 brw_inst_set_cond_modifier(p
->devinfo
, i
[3], inst
->conditional_mod
);
842 /* brw_set_default_saturate() is called before emitting instructions,
843 * so the saturate bit is set in each instruction, so we need to unset
844 * it on the first instruction of each pair.
846 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
847 brw_inst_set_saturate(p
->devinfo
, i
[2], false);
850 brw_pop_insn_state(p
);
853 } else if (devinfo
->has_pln
) {
854 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
855 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
857 * "[DevSNB]:<src1> must be even register aligned.
859 * This restriction is lifted on Ivy Bridge.
861 * This means that we need to split PLN into LINE+MAC on-the-fly.
862 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
863 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
864 * coordinate registers are laid out differently so we leave it as a
865 * SIMD16 instruction.
867 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
868 assert(inst
->group
% 16 == 0);
870 brw_push_insn_state(p
);
871 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
873 /* Thanks to two accumulators, we can emit all the LINEs and then all
874 * the MACs. This improves parallelism a bit.
876 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
877 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
878 offset(delta_x
, g
* 2));
879 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
881 /* LINE writes the accumulator automatically on gen4-5. On Sandy
882 * Bridge and later, we have to explicitly enable it.
884 if (devinfo
->gen
>= 6)
885 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
887 /* brw_set_default_saturate() is called before emitting
888 * instructions, so the saturate bit is set in each instruction,
889 * so we need to unset it on the LINE instructions.
891 brw_inst_set_saturate(p
->devinfo
, line
, false);
894 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
895 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
896 offset(delta_x
, g
* 2 + 1));
897 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
898 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
901 brw_pop_insn_state(p
);
905 brw_PLN(p
, dst
, interp
, delta_x
);
910 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
911 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
913 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
915 /* brw_set_default_saturate() is called before emitting instructions, so
916 * the saturate bit is set in each instruction, so we need to unset it on
917 * the first instruction.
919 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
926 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
929 struct brw_reg surf_index
)
931 assert(devinfo
->gen
>= 7);
932 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
937 switch (inst
->exec_size
) {
939 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
942 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
945 unreachable("Invalid width for texture instruction");
948 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
954 retype(dst
, BRW_REGISTER_TYPE_UW
),
959 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
960 rlen
, /* response length */
962 inst
->header_size
> 0,
964 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
968 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
969 struct brw_reg surface_index
,
970 struct brw_reg sampler_index
)
972 assert(devinfo
->gen
< 7);
973 assert(inst
->size_written
% REG_SIZE
== 0);
976 uint32_t return_format
;
977 bool is_combined_send
= inst
->eot
;
979 /* Sampler EOT message of less than the dispatch width would kill the
980 * thread prematurely.
982 assert(!is_combined_send
|| inst
->exec_size
== dispatch_width
);
985 case BRW_REGISTER_TYPE_D
:
986 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
988 case BRW_REGISTER_TYPE_UD
:
989 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
992 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
996 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
997 * is set as part of the message descriptor. On gen4, the PRM seems to
998 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
999 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
1000 * gone from the message descriptor entirely and you just get UINT32 all
1001 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
1002 * just stomp it to UINT32 all the time.
1004 if (inst
->opcode
== SHADER_OPCODE_TXS
)
1005 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
1007 switch (inst
->exec_size
) {
1009 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1012 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1015 unreachable("Invalid width for texture instruction");
1018 if (devinfo
->gen
>= 5) {
1019 switch (inst
->opcode
) {
1020 case SHADER_OPCODE_TEX
:
1021 if (inst
->shadow_compare
) {
1022 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1024 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1028 if (inst
->shadow_compare
) {
1029 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1031 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1034 case SHADER_OPCODE_TXL
:
1035 if (inst
->shadow_compare
) {
1036 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1038 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1041 case SHADER_OPCODE_TXS
:
1042 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1044 case SHADER_OPCODE_TXD
:
1045 assert(!inst
->shadow_compare
);
1046 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1048 case SHADER_OPCODE_TXF
:
1049 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1051 case SHADER_OPCODE_TXF_CMS
:
1052 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1054 case SHADER_OPCODE_LOD
:
1055 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1057 case SHADER_OPCODE_TG4
:
1058 assert(devinfo
->gen
== 6);
1059 assert(!inst
->shadow_compare
);
1060 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1062 case SHADER_OPCODE_SAMPLEINFO
:
1063 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1066 unreachable("not reached");
1069 switch (inst
->opcode
) {
1070 case SHADER_OPCODE_TEX
:
1071 /* Note that G45 and older determines shadow compare and dispatch width
1072 * from message length for most messages.
1074 if (inst
->exec_size
== 8) {
1075 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1076 if (inst
->shadow_compare
) {
1077 assert(inst
->mlen
== 6);
1079 assert(inst
->mlen
<= 4);
1082 if (inst
->shadow_compare
) {
1083 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1084 assert(inst
->mlen
== 9);
1086 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1087 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1092 if (inst
->shadow_compare
) {
1093 assert(inst
->exec_size
== 8);
1094 assert(inst
->mlen
== 6);
1095 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1097 assert(inst
->mlen
== 9);
1098 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1099 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1102 case SHADER_OPCODE_TXL
:
1103 if (inst
->shadow_compare
) {
1104 assert(inst
->exec_size
== 8);
1105 assert(inst
->mlen
== 6);
1106 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1108 assert(inst
->mlen
== 9);
1109 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1110 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1113 case SHADER_OPCODE_TXD
:
1114 /* There is no sample_d_c message; comparisons are done manually */
1115 assert(inst
->exec_size
== 8);
1116 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1117 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1119 case SHADER_OPCODE_TXF
:
1120 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1121 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1122 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1124 case SHADER_OPCODE_TXS
:
1125 assert(inst
->mlen
== 3);
1126 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1127 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1130 unreachable("not reached");
1133 assert(msg_type
!= -1);
1135 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1139 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1141 /* Load the message header if present. If there's a texture offset,
1142 * we need to set it up explicitly and load the offset bitfield.
1143 * Otherwise, we can use an implied move from g0 to the first message reg.
1145 struct brw_reg src
= brw_null_reg();
1146 if (inst
->header_size
!= 0) {
1147 if (devinfo
->gen
< 6 && !inst
->offset
) {
1148 /* Set up an implied move from g0 to the MRF. */
1149 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1151 assert(inst
->base_mrf
!= -1);
1152 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1154 brw_push_insn_state(p
);
1155 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1156 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1157 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1158 /* Explicitly set up the message header by copying g0 to the MRF. */
1159 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1161 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1163 /* Set the offset bits in DWord 2. */
1164 brw_MOV(p
, get_element_ud(header_reg
, 2),
1165 brw_imm_ud(inst
->offset
));
1168 brw_pop_insn_state(p
);
1172 uint32_t base_binding_table_index
;
1173 switch (inst
->opcode
) {
1174 case SHADER_OPCODE_TG4
:
1175 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1178 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1182 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1183 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1186 retype(dst
, BRW_REGISTER_TYPE_UW
),
1189 surface_index
.ud
+ base_binding_table_index
,
1190 sampler_index
.ud
% 16,
1192 inst
->size_written
/ REG_SIZE
,
1194 inst
->header_size
!= 0,
1200 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1203 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1205 * Ideally, we want to produce:
1208 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1209 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1210 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1211 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1212 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1213 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1214 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1215 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1217 * and add another set of two more subspans if in 16-pixel dispatch mode.
1219 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1220 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1221 * pair. But the ideal approximation may impose a huge performance cost on
1222 * sample_d. On at least Haswell, sample_d instruction does some
1223 * optimizations if the same LOD is used for all pixels in the subspan.
1225 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1226 * appropriate swizzling.
1229 fs_generator::generate_ddx(const fs_inst
*inst
,
1230 struct brw_reg dst
, struct brw_reg src
)
1232 unsigned vstride
, width
;
1234 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1235 /* produce accurate derivatives */
1236 vstride
= BRW_VERTICAL_STRIDE_2
;
1237 width
= BRW_WIDTH_2
;
1239 /* replicate the derivative at the top-left pixel to other pixels */
1240 vstride
= BRW_VERTICAL_STRIDE_4
;
1241 width
= BRW_WIDTH_4
;
1244 struct brw_reg src0
= src
;
1245 struct brw_reg src1
= src
;
1247 src0
.subnr
= sizeof(float);
1248 src0
.vstride
= vstride
;
1250 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1251 src1
.vstride
= vstride
;
1253 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1255 brw_ADD(p
, dst
, src0
, negate(src1
));
1258 /* The negate_value boolean is used to negate the derivative computation for
1259 * FBOs, since they place the origin at the upper left instead of the lower
1263 fs_generator::generate_ddy(const fs_inst
*inst
,
1264 struct brw_reg dst
, struct brw_reg src
)
1266 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1267 /* produce accurate derivatives */
1268 if (devinfo
->gen
>= 11) {
1269 src
= stride(src
, 0, 2, 1);
1270 struct brw_reg src_0
= byte_offset(src
, 0 * sizeof(float));
1271 struct brw_reg src_2
= byte_offset(src
, 2 * sizeof(float));
1272 struct brw_reg src_4
= byte_offset(src
, 4 * sizeof(float));
1273 struct brw_reg src_6
= byte_offset(src
, 6 * sizeof(float));
1274 struct brw_reg src_8
= byte_offset(src
, 8 * sizeof(float));
1275 struct brw_reg src_10
= byte_offset(src
, 10 * sizeof(float));
1276 struct brw_reg src_12
= byte_offset(src
, 12 * sizeof(float));
1277 struct brw_reg src_14
= byte_offset(src
, 14 * sizeof(float));
1279 struct brw_reg dst_0
= byte_offset(dst
, 0 * sizeof(float));
1280 struct brw_reg dst_4
= byte_offset(dst
, 4 * sizeof(float));
1281 struct brw_reg dst_8
= byte_offset(dst
, 8 * sizeof(float));
1282 struct brw_reg dst_12
= byte_offset(dst
, 12 * sizeof(float));
1284 brw_push_insn_state(p
);
1285 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1287 brw_ADD(p
, dst_0
, negate(src_0
), src_2
);
1288 brw_ADD(p
, dst_4
, negate(src_4
), src_6
);
1290 if (inst
->exec_size
== 16) {
1291 brw_ADD(p
, dst_8
, negate(src_8
), src_10
);
1292 brw_ADD(p
, dst_12
, negate(src_12
), src_14
);
1295 brw_pop_insn_state(p
);
1297 struct brw_reg src0
= stride(src
, 4, 4, 1);
1298 struct brw_reg src1
= stride(src
, 4, 4, 1);
1299 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1300 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1302 brw_push_insn_state(p
);
1303 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1304 brw_ADD(p
, dst
, negate(src0
), src1
);
1305 brw_pop_insn_state(p
);
1308 /* replicate the derivative at the top-left pixel to other pixels */
1309 struct brw_reg src0
= stride(src
, 4, 4, 0);
1310 struct brw_reg src1
= stride(src
, 4, 4, 0);
1311 src0
.subnr
= 0 * sizeof(float);
1312 src1
.subnr
= 2 * sizeof(float);
1314 brw_ADD(p
, dst
, negate(src0
), src1
);
1319 fs_generator::generate_discard_jump(fs_inst
*)
1321 assert(devinfo
->gen
>= 6);
1323 /* This HALT will be patched up at FB write time to point UIP at the end of
1324 * the program, and at brw_uip_jip() JIP will be set to the end of the
1325 * current block (or the program).
1327 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1332 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1334 /* The 32-wide messages only respect the first 16-wide half of the channel
1335 * enable signals which are replicated identically for the second group of
1336 * 16 channels, so we cannot use them unless the write is marked
1337 * force_writemask_all.
1339 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1340 MIN2(16, inst
->exec_size
);
1341 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1342 assert(inst
->mlen
!= 0);
1344 brw_push_insn_state(p
);
1345 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1346 brw_set_default_compression(p
, lower_size
> 8);
1348 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1349 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1351 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1352 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1354 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1356 inst
->offset
+ block_size
* REG_SIZE
* i
);
1359 brw_pop_insn_state(p
);
1363 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1365 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1366 assert(inst
->mlen
!= 0);
1368 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1369 inst
->exec_size
/ 8, inst
->offset
);
1373 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1375 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1377 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1381 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1383 struct brw_reg index
,
1384 struct brw_reg offset
)
1386 assert(type_sz(dst
.type
) == 4);
1387 assert(inst
->mlen
!= 0);
1389 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1390 index
.type
== BRW_REGISTER_TYPE_UD
);
1391 uint32_t surf_index
= index
.ud
;
1393 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1394 offset
.type
== BRW_REGISTER_TYPE_UD
);
1395 uint32_t read_offset
= offset
.ud
;
1397 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1398 read_offset
, surf_index
);
1402 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1404 struct brw_reg index
,
1405 struct brw_reg payload
)
1407 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1408 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1409 assert(type_sz(dst
.type
) == 4);
1411 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1412 const uint32_t surf_index
= index
.ud
;
1414 brw_push_insn_state(p
);
1415 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1416 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1417 brw_pop_insn_state(p
);
1419 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1420 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1421 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1422 brw_set_desc(p
, send
,
1423 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1425 brw_dp_read_desc(devinfo
, surf_index
,
1426 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1427 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1428 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1431 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1433 brw_push_insn_state(p
);
1434 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1436 /* a0.0 = surf_index & 0xff */
1437 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1438 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1439 brw_set_dest(p
, insn_and
, addr
);
1440 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1441 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1443 /* dst = send(payload, a0.0 | <descriptor>) */
1444 brw_send_indirect_message(
1445 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1446 retype(dst
, BRW_REGISTER_TYPE_UD
),
1447 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1448 brw_message_desc(devinfo
, 1,
1449 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1450 brw_dp_read_desc(devinfo
, 0 /* surface */,
1451 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1452 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1453 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1455 brw_pop_insn_state(p
);
1460 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1462 struct brw_reg index
)
1464 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1465 assert(inst
->header_size
!= 0);
1468 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1469 index
.type
== BRW_REGISTER_TYPE_UD
);
1470 uint32_t surf_index
= index
.ud
;
1472 uint32_t simd_mode
, rlen
, msg_type
;
1473 if (inst
->exec_size
== 16) {
1474 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1477 assert(inst
->exec_size
== 8);
1478 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1482 if (devinfo
->gen
>= 5)
1483 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1485 /* We always use the SIMD16 message so that we only have to load U, and
1488 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1489 assert(inst
->mlen
== 3);
1490 assert(inst
->size_written
== 8 * REG_SIZE
);
1492 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1495 struct brw_reg header
= brw_vec8_grf(0, 0);
1496 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1498 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1499 brw_inst_set_compression(devinfo
, send
, false);
1500 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1501 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1502 brw_set_src0(p
, send
, header
);
1503 if (devinfo
->gen
< 6)
1504 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1506 /* Our surface is set up as floats, regardless of what actual data is
1509 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1510 brw_set_desc(p
, send
,
1511 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1512 brw_sampler_desc(devinfo
, surf_index
,
1513 0, /* sampler (unused) */
1514 msg_type
, simd_mode
, return_format
));
1518 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1520 struct brw_reg index
,
1521 struct brw_reg offset
)
1523 assert(devinfo
->gen
>= 7);
1524 /* Varying-offset pull constant loads are treated as a normal expression on
1525 * gen7, so the fact that it's a send message is hidden at the IR level.
1527 assert(inst
->header_size
== 0);
1529 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1531 uint32_t simd_mode
, rlen
;
1532 if (inst
->exec_size
== 16) {
1534 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1536 assert(inst
->exec_size
== 8);
1538 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1541 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1543 uint32_t surf_index
= index
.ud
;
1545 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1546 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1547 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1548 brw_set_src0(p
, send
, offset
);
1549 brw_set_desc(p
, send
,
1550 brw_message_desc(devinfo
, inst
->mlen
, rlen
, false) |
1551 brw_sampler_desc(devinfo
, surf_index
,
1552 0, /* LD message ignores sampler unit */
1553 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1558 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1560 brw_push_insn_state(p
);
1561 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1563 /* a0.0 = surf_index & 0xff */
1564 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1565 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1566 brw_set_dest(p
, insn_and
, addr
);
1567 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1568 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1570 brw_pop_insn_state(p
);
1572 /* dst = send(offset, a0.0 | <descriptor>) */
1573 brw_send_indirect_message(
1574 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1576 brw_message_desc(devinfo
, inst
->mlen
, rlen
, false) |
1577 brw_sampler_desc(devinfo
,
1580 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1587 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1590 struct brw_reg msg_data
,
1593 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1594 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1595 assert(inst
->size_written
% REG_SIZE
== 0);
1597 brw_pixel_interpolator_query(p
,
1598 retype(dst
, BRW_REGISTER_TYPE_UW
),
1599 /* If we don't have a payload, what we send doesn't matter */
1600 has_payload
? src
: brw_vec8_grf(0, 0),
1601 inst
->pi_noperspective
,
1604 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1605 inst
->size_written
/ REG_SIZE
);
1608 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1609 * the ADD instruction.
1612 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1614 struct brw_reg src0
,
1615 struct brw_reg src1
)
1617 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1618 dst
.type
== BRW_REGISTER_TYPE_UD
);
1619 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1620 src0
.type
== BRW_REGISTER_TYPE_UD
);
1622 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1623 const unsigned lower_size
= MIN2(inst
->exec_size
,
1624 devinfo
->gen
>= 8 ? 16 : 8);
1626 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1627 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1628 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1629 (i
* lower_size
/ (1 << src0
.width
))) *
1630 type_sz(src0
.type
) / REG_SIZE
),
1631 suboffset(reg
, i
* lower_size
/ 4));
1632 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1633 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1634 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1639 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1644 assert(devinfo
->gen
>= 7);
1645 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1646 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1647 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1649 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1651 * Because this instruction does not have a 16-bit floating-point type,
1652 * the destination data type must be Word (W).
1654 * The destination must be DWord-aligned and specify a horizontal stride
1655 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1656 * each destination channel and the upper word is not modified.
1658 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1660 /* Give each 32-bit channel of dst the form below, where "." means
1664 brw_F32TO16(p
, dst_w
, y
);
1669 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1671 /* And, finally the form of packHalf2x16's output:
1674 brw_F32TO16(p
, dst_w
, x
);
1678 fs_generator::generate_shader_time_add(fs_inst
*,
1679 struct brw_reg payload
,
1680 struct brw_reg offset
,
1681 struct brw_reg value
)
1683 assert(devinfo
->gen
>= 7);
1684 brw_push_insn_state(p
);
1685 brw_set_default_mask_control(p
, true);
1687 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1688 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1690 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1693 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1694 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1695 value
.width
= BRW_WIDTH_1
;
1696 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1697 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1699 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1702 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1703 * case, and we don't really care about squeezing every bit of performance
1704 * out of this path, so we just emit the MOVs from here.
1706 brw_MOV(p
, payload_offset
, offset
);
1707 brw_MOV(p
, payload_value
, value
);
1708 brw_shader_time_add(p
, payload
,
1709 prog_data
->binding_table
.shader_time_start
);
1710 brw_pop_insn_state(p
);
1714 fs_generator::enable_debug(const char *shader_name
)
1717 this->shader_name
= shader_name
;
1721 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1723 /* align to 64 byte boundary. */
1724 while (p
->next_insn_offset
% 64)
1727 this->dispatch_width
= dispatch_width
;
1729 int start_offset
= p
->next_insn_offset
;
1730 int spill_count
= 0, fill_count
= 0;
1733 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1735 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1736 struct brw_reg src
[4], dst
;
1737 unsigned int last_insn_offset
= p
->next_insn_offset
;
1738 bool multiple_instructions_emitted
= false;
1740 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1741 * "Register Region Restrictions" section: for BDW, SKL:
1743 * "A POW/FDIV operation must not be followed by an instruction
1744 * that requires two destination registers."
1746 * The documentation is often lacking annotations for Atom parts,
1747 * and empirically this affects CHV as well.
1749 if (devinfo
->gen
>= 8 &&
1750 devinfo
->gen
<= 9 &&
1752 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1753 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1754 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1756 last_insn_offset
= p
->next_insn_offset
;
1759 if (unlikely(debug_flag
))
1760 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1762 /* If the instruction writes to more than one register, it needs to be
1763 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1764 * hardware figures out by itself what the right compression mode is,
1765 * but we still need to know whether the instruction is compressed to
1766 * set up the source register regions appropriately.
1768 * XXX - This is wrong for instructions that write a single register but
1769 * read more than one which should strictly speaking be treated as
1770 * compressed. For instructions that don't write any registers it
1771 * relies on the destination being a null register of the correct
1772 * type and regioning so the instruction is considered compressed
1773 * or not accordingly.
1775 const bool compressed
=
1776 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1777 brw_set_default_compression(p
, compressed
);
1778 brw_set_default_group(p
, inst
->group
);
1780 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1781 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1782 &inst
->src
[i
], compressed
);
1783 /* The accumulator result appears to get used for the
1784 * conditional modifier generation. When negating a UD
1785 * value, there is a 33rd bit generated for the sign in the
1786 * accumulator value, so now you can't check, for example,
1787 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1789 assert(!inst
->conditional_mod
||
1790 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1791 !inst
->src
[i
].negate
);
1793 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1794 &inst
->dst
, compressed
);
1796 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1797 brw_set_default_predicate_control(p
, inst
->predicate
);
1798 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1799 /* On gen7 and above, hardware automatically adds the group onto the
1800 * flag subregister number. On Sandy Bridge and older, we have to do it
1803 const unsigned flag_subreg
= inst
->flag_subreg
+
1804 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1805 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1806 brw_set_default_saturate(p
, inst
->saturate
);
1807 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1808 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1810 unsigned exec_size
= inst
->exec_size
;
1811 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1812 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1816 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1818 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1819 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1820 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1821 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1823 switch (inst
->opcode
) {
1824 case BRW_OPCODE_MOV
:
1825 brw_MOV(p
, dst
, src
[0]);
1827 case BRW_OPCODE_ADD
:
1828 brw_ADD(p
, dst
, src
[0], src
[1]);
1830 case BRW_OPCODE_MUL
:
1831 brw_MUL(p
, dst
, src
[0], src
[1]);
1833 case BRW_OPCODE_AVG
:
1834 brw_AVG(p
, dst
, src
[0], src
[1]);
1836 case BRW_OPCODE_MACH
:
1837 brw_MACH(p
, dst
, src
[0], src
[1]);
1840 case BRW_OPCODE_LINE
:
1841 brw_LINE(p
, dst
, src
[0], src
[1]);
1844 case BRW_OPCODE_MAD
:
1845 assert(devinfo
->gen
>= 6);
1846 if (devinfo
->gen
< 10)
1847 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1848 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1851 case BRW_OPCODE_LRP
:
1852 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1853 if (devinfo
->gen
< 10)
1854 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1855 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1858 case BRW_OPCODE_FRC
:
1859 brw_FRC(p
, dst
, src
[0]);
1861 case BRW_OPCODE_RNDD
:
1862 brw_RNDD(p
, dst
, src
[0]);
1864 case BRW_OPCODE_RNDE
:
1865 brw_RNDE(p
, dst
, src
[0]);
1867 case BRW_OPCODE_RNDZ
:
1868 brw_RNDZ(p
, dst
, src
[0]);
1871 case BRW_OPCODE_AND
:
1872 brw_AND(p
, dst
, src
[0], src
[1]);
1875 brw_OR(p
, dst
, src
[0], src
[1]);
1877 case BRW_OPCODE_XOR
:
1878 brw_XOR(p
, dst
, src
[0], src
[1]);
1880 case BRW_OPCODE_NOT
:
1881 brw_NOT(p
, dst
, src
[0]);
1883 case BRW_OPCODE_ASR
:
1884 brw_ASR(p
, dst
, src
[0], src
[1]);
1886 case BRW_OPCODE_SHR
:
1887 brw_SHR(p
, dst
, src
[0], src
[1]);
1889 case BRW_OPCODE_SHL
:
1890 brw_SHL(p
, dst
, src
[0], src
[1]);
1892 case BRW_OPCODE_F32TO16
:
1893 assert(devinfo
->gen
>= 7);
1894 brw_F32TO16(p
, dst
, src
[0]);
1896 case BRW_OPCODE_F16TO32
:
1897 assert(devinfo
->gen
>= 7);
1898 brw_F16TO32(p
, dst
, src
[0]);
1900 case BRW_OPCODE_CMP
:
1901 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1902 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1903 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1904 * implemented in the compiler is not sufficient. Overriding the
1905 * type when the destination is the null register is necessary but
1906 * not sufficient by itself.
1908 assert(dst
.nr
== BRW_ARF_NULL
);
1909 dst
.type
= BRW_REGISTER_TYPE_D
;
1911 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1913 case BRW_OPCODE_SEL
:
1914 brw_SEL(p
, dst
, src
[0], src
[1]);
1916 case BRW_OPCODE_CSEL
:
1917 assert(devinfo
->gen
>= 8);
1918 if (devinfo
->gen
< 10)
1919 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1920 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1922 case BRW_OPCODE_BFREV
:
1923 assert(devinfo
->gen
>= 7);
1924 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1925 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1927 case BRW_OPCODE_FBH
:
1928 assert(devinfo
->gen
>= 7);
1929 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1931 case BRW_OPCODE_FBL
:
1932 assert(devinfo
->gen
>= 7);
1933 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1934 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1936 case BRW_OPCODE_LZD
:
1937 brw_LZD(p
, dst
, src
[0]);
1939 case BRW_OPCODE_CBIT
:
1940 assert(devinfo
->gen
>= 7);
1941 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1942 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1944 case BRW_OPCODE_ADDC
:
1945 assert(devinfo
->gen
>= 7);
1946 brw_ADDC(p
, dst
, src
[0], src
[1]);
1948 case BRW_OPCODE_SUBB
:
1949 assert(devinfo
->gen
>= 7);
1950 brw_SUBB(p
, dst
, src
[0], src
[1]);
1952 case BRW_OPCODE_MAC
:
1953 brw_MAC(p
, dst
, src
[0], src
[1]);
1956 case BRW_OPCODE_BFE
:
1957 assert(devinfo
->gen
>= 7);
1958 if (devinfo
->gen
< 10)
1959 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1960 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1963 case BRW_OPCODE_BFI1
:
1964 assert(devinfo
->gen
>= 7);
1965 brw_BFI1(p
, dst
, src
[0], src
[1]);
1967 case BRW_OPCODE_BFI2
:
1968 assert(devinfo
->gen
>= 7);
1969 if (devinfo
->gen
< 10)
1970 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1971 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1975 if (inst
->src
[0].file
!= BAD_FILE
) {
1976 /* The instruction has an embedded compare (only allowed on gen6) */
1977 assert(devinfo
->gen
== 6);
1978 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1980 brw_IF(p
, brw_get_default_exec_size(p
));
1984 case BRW_OPCODE_ELSE
:
1987 case BRW_OPCODE_ENDIF
:
1992 brw_DO(p
, brw_get_default_exec_size(p
));
1995 case BRW_OPCODE_BREAK
:
1998 case BRW_OPCODE_CONTINUE
:
2002 case BRW_OPCODE_WHILE
:
2007 case SHADER_OPCODE_RCP
:
2008 case SHADER_OPCODE_RSQ
:
2009 case SHADER_OPCODE_SQRT
:
2010 case SHADER_OPCODE_EXP2
:
2011 case SHADER_OPCODE_LOG2
:
2012 case SHADER_OPCODE_SIN
:
2013 case SHADER_OPCODE_COS
:
2014 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2015 if (devinfo
->gen
>= 6) {
2016 assert(inst
->mlen
== 0);
2017 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2018 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2019 src
[0], brw_null_reg());
2021 assert(inst
->mlen
>= 1);
2022 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2024 brw_math_function(inst
->opcode
),
2025 inst
->base_mrf
, src
[0],
2026 BRW_MATH_PRECISION_FULL
);
2029 case SHADER_OPCODE_INT_QUOTIENT
:
2030 case SHADER_OPCODE_INT_REMAINDER
:
2031 case SHADER_OPCODE_POW
:
2032 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2033 if (devinfo
->gen
>= 6) {
2034 assert(inst
->mlen
== 0);
2035 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2036 inst
->exec_size
== 8);
2037 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2039 assert(inst
->mlen
>= 1);
2040 assert(inst
->exec_size
== 8);
2041 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2042 inst
->base_mrf
, src
[0],
2043 BRW_MATH_PRECISION_FULL
);
2046 case FS_OPCODE_LINTERP
:
2047 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2049 case FS_OPCODE_PIXEL_X
:
2050 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2051 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2052 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2054 case FS_OPCODE_PIXEL_Y
:
2055 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2056 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2057 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2060 case SHADER_OPCODE_SEND
:
2061 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2062 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2065 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2066 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2068 case SHADER_OPCODE_TEX
:
2070 case SHADER_OPCODE_TXD
:
2071 case SHADER_OPCODE_TXF
:
2072 case SHADER_OPCODE_TXF_CMS
:
2073 case SHADER_OPCODE_TXL
:
2074 case SHADER_OPCODE_TXS
:
2075 case SHADER_OPCODE_LOD
:
2076 case SHADER_OPCODE_TG4
:
2077 case SHADER_OPCODE_SAMPLEINFO
:
2078 assert(inst
->src
[0].file
== BAD_FILE
);
2079 generate_tex(inst
, dst
, src
[1], src
[2]);
2082 case FS_OPCODE_DDX_COARSE
:
2083 case FS_OPCODE_DDX_FINE
:
2084 generate_ddx(inst
, dst
, src
[0]);
2086 case FS_OPCODE_DDY_COARSE
:
2087 case FS_OPCODE_DDY_FINE
:
2088 generate_ddy(inst
, dst
, src
[0]);
2091 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2092 generate_scratch_write(inst
, src
[0]);
2096 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2097 generate_scratch_read(inst
, dst
);
2101 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2102 generate_scratch_read_gen7(inst
, dst
);
2106 case SHADER_OPCODE_MOV_INDIRECT
:
2107 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2110 case SHADER_OPCODE_URB_READ_SIMD8
:
2111 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2112 generate_urb_read(inst
, dst
, src
[0]);
2115 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2116 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2117 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2118 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2119 generate_urb_write(inst
, src
[0]);
2122 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2123 assert(inst
->force_writemask_all
);
2124 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2127 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2128 assert(inst
->force_writemask_all
);
2129 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2132 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2133 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2136 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2137 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2140 case FS_OPCODE_REP_FB_WRITE
:
2141 case FS_OPCODE_FB_WRITE
:
2142 generate_fb_write(inst
, src
[0]);
2145 case FS_OPCODE_FB_READ
:
2146 generate_fb_read(inst
, dst
, src
[0]);
2149 case FS_OPCODE_DISCARD_JUMP
:
2150 generate_discard_jump(inst
);
2153 case SHADER_OPCODE_SHADER_TIME_ADD
:
2154 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2157 case SHADER_OPCODE_MEMORY_FENCE
:
2158 brw_memory_fence(p
, dst
, BRW_OPCODE_SEND
);
2161 case SHADER_OPCODE_INTERLOCK
:
2162 /* The interlock is basically a memory fence issued via sendc */
2163 brw_memory_fence(p
, dst
, BRW_OPCODE_SENDC
);
2166 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2167 const struct brw_reg mask
=
2168 brw_stage_has_packed_dispatch(devinfo
, stage
,
2169 prog_data
) ? brw_imm_ud(~0u) :
2170 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2172 brw_find_live_channel(p
, dst
, mask
);
2176 case SHADER_OPCODE_BROADCAST
:
2177 assert(inst
->force_writemask_all
);
2178 brw_broadcast(p
, dst
, src
[0], src
[1]);
2181 case SHADER_OPCODE_SHUFFLE
:
2182 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2185 case SHADER_OPCODE_SEL_EXEC
:
2186 assert(inst
->force_writemask_all
);
2187 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2188 brw_MOV(p
, dst
, src
[1]);
2189 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2190 brw_MOV(p
, dst
, src
[0]);
2193 case SHADER_OPCODE_QUAD_SWIZZLE
:
2194 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2195 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2196 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2199 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2200 assert(src
[0].type
== dst
.type
);
2201 assert(!src
[0].negate
&& !src
[0].abs
);
2202 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2203 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2204 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2205 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2206 const unsigned component
= src
[1].ud
;
2207 const unsigned cluster_size
= src
[2].ud
;
2208 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2209 cluster_size
, cluster_size
, 0);
2210 if (type_sz(src
[0].type
) > 4 &&
2211 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2212 /* IVB has an issue (which we found empirically) where it reads
2213 * two address register components per channel for indirectly
2214 * addressed 64-bit sources.
2216 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2218 * "When source or destination datatype is 64b or operation is
2219 * integer DWord multiply, indirect addressing must not be
2222 * To work around both of these, we do two integer MOVs insead of
2223 * one 64-bit MOV. Because no double value should ever cross a
2224 * register boundary, it's safe to use the immediate offset in the
2225 * indirect here to handle adding 4 bytes to the offset and avoid
2226 * the extra ADD to the register file.
2228 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2229 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2230 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2231 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2233 brw_MOV(p
, dst
, strided
);
2238 case FS_OPCODE_SET_SAMPLE_ID
:
2239 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2242 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2243 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2246 case FS_OPCODE_PLACEHOLDER_HALT
:
2247 /* This is the place where the final HALT needs to be inserted if
2248 * we've emitted any discards. If not, this will emit no code.
2250 if (!patch_discard_jumps_to_fb_writes()) {
2251 if (unlikely(debug_flag
)) {
2252 disasm_info
->use_tail
= true;
2257 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2258 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2259 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2262 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2263 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2264 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2267 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2268 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2269 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2272 case CS_OPCODE_CS_TERMINATE
:
2273 generate_cs_terminate(inst
, src
[0]);
2276 case SHADER_OPCODE_BARRIER
:
2277 generate_barrier(inst
, src
[0]);
2280 case BRW_OPCODE_DIM
:
2281 assert(devinfo
->is_haswell
);
2282 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2283 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2284 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2287 case SHADER_OPCODE_RND_MODE
:
2288 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2289 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2293 unreachable("Unsupported opcode");
2295 case SHADER_OPCODE_LOAD_PAYLOAD
:
2296 unreachable("Should be lowered by lower_load_payload()");
2299 if (multiple_instructions_emitted
)
2302 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2303 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2304 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2305 "emitting more than 1 instruction");
2307 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2309 if (inst
->conditional_mod
)
2310 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2311 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2312 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2316 brw_set_uip_jip(p
, start_offset
);
2318 /* end of program sentinel */
2319 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2324 if (unlikely(debug_flag
))
2326 brw_validate_instructions(devinfo
, p
->store
,
2328 p
->next_insn_offset
,
2331 int before_size
= p
->next_insn_offset
- start_offset
;
2332 brw_compact_instructions(p
, start_offset
, disasm_info
);
2333 int after_size
= p
->next_insn_offset
- start_offset
;
2335 if (unlikely(debug_flag
)) {
2336 fprintf(stderr
, "Native code for %s\n"
2337 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2338 " bytes (%.0f%%)\n",
2339 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2340 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2341 100.0f
* (before_size
- after_size
) / before_size
);
2343 dump_assembly(p
->store
, disasm_info
);
2345 ralloc_free(disasm_info
);
2348 compiler
->shader_debug_log(log_data
,
2349 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2350 "%d:%d spills:fills, Promoted %u constants, "
2351 "compacted %d to %d bytes.",
2352 _mesa_shader_stage_to_abbrev(stage
),
2353 dispatch_width
, before_size
/ 16,
2354 loop_count
, cfg
->cycle_count
, spill_count
,
2355 fill_count
, promoted_constants
, before_size
,
2358 return start_offset
;
2362 fs_generator::get_assembly()
2364 return brw_get_program(p
, &prog_data
->program_size
);