2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
179 struct brw_stage_prog_data
*prog_data
,
180 unsigned promoted_constants
,
181 bool runtime_check_aads_emit
,
182 gl_shader_stage stage
)
184 : compiler(compiler
), log_data(log_data
),
185 devinfo(compiler
->devinfo
), key(key
),
186 prog_data(prog_data
),
187 promoted_constants(promoted_constants
),
188 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
189 stage(stage
), mem_ctx(mem_ctx
)
191 p
= rzalloc(mem_ctx
, struct brw_codegen
);
192 brw_init_codegen(devinfo
, p
, mem_ctx
);
194 /* In the FS code generator, we are very careful to ensure that we always
195 * set the right execution size so we don't need the EU code to "help" us
196 * by trying to infer it. Sometimes, it infers the wrong thing.
198 p
->automatic_exec_sizes
= false;
201 fs_generator::~fs_generator()
205 class ip_record
: public exec_node
{
207 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
218 fs_generator::patch_discard_jumps_to_fb_writes()
220 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
223 int scale
= brw_jump_scale(p
->devinfo
);
225 /* There is a somewhat strange undocumented requirement of using
226 * HALT, according to the simulator. If some channel has HALTed to
227 * a particular UIP, then by the end of the program, every channel
228 * must have HALTed to that UIP. Furthermore, the tracking is a
229 * stack, so you can't do the final halt of a UIP after starting
230 * halting to a new UIP.
232 * Symptoms of not emitting this instruction on actual hardware
233 * included GPU hangs and sparkly rendering on the piglit discard
236 brw_inst
*last_halt
= gen6_HALT(p
);
237 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
238 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
242 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
243 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
245 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
246 /* HALT takes a half-instruction distance from the pre-incremented IP. */
247 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
250 this->discard_halt_patches
.make_empty();
255 fs_generator::fire_fb_write(fs_inst
*inst
,
256 struct brw_reg payload
,
257 struct brw_reg implied_header
,
260 uint32_t msg_control
;
262 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
264 if (devinfo
->gen
< 6) {
265 brw_push_insn_state(p
);
266 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
267 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
268 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
269 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
270 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
271 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
272 brw_pop_insn_state(p
);
275 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
276 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
277 else if (prog_data
->dual_src_blend
) {
279 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
281 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
282 } else if (inst
->exec_size
== 16)
283 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
285 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
287 /* We assume render targets start at 0, because headerless FB write
288 * messages set "Render Target Index" to 0. Using a different binding
289 * table index would make it impossible to use headerless messages.
291 const uint32_t surf_index
= inst
->target
;
295 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
302 inst
->header_size
!= 0);
304 brw_mark_surface_used(&prog_data
->base
, surf_index
);
308 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
310 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
311 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
313 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
314 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
317 const struct brw_reg implied_header
=
318 devinfo
->gen
< 6 ? payload
: brw_null_reg();
320 if (inst
->base_mrf
>= 0)
321 payload
= brw_message_reg(inst
->base_mrf
);
323 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
326 if (inst
->header_size
!= 0) {
327 brw_push_insn_state(p
);
328 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
329 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
330 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
331 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
332 brw_set_default_flag_reg(p
, 0, 0);
334 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
337 if (prog_data
->uses_kill
) {
338 struct brw_reg pixel_mask
;
340 if (devinfo
->gen
>= 6)
341 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
343 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
345 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
348 if (devinfo
->gen
>= 6) {
349 brw_push_insn_state(p
);
350 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
351 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
353 retype(payload
, BRW_REGISTER_TYPE_UD
),
354 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
355 brw_pop_insn_state(p
);
357 if (inst
->target
> 0 && key
->replicate_alpha
) {
358 /* Set "Source0 Alpha Present to RenderTarget" bit in message
362 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
363 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
364 brw_imm_ud(0x1 << 11));
367 if (inst
->target
> 0) {
368 /* Set the render target index for choosing BLEND_STATE. */
369 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
370 BRW_REGISTER_TYPE_UD
),
371 brw_imm_ud(inst
->target
));
374 /* Set computes stencil to render target */
375 if (prog_data
->computed_stencil
) {
377 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
378 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
379 brw_imm_ud(0x1 << 14));
383 brw_pop_insn_state(p
);
386 if (!runtime_check_aads_emit
) {
387 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
389 /* This can only happen in gen < 6 */
390 assert(devinfo
->gen
< 6);
392 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
394 /* Check runtime bit to detect if we have to send AA data or not */
395 brw_push_insn_state(p
);
396 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
397 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
400 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
402 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
404 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
405 brw_pop_insn_state(p
);
407 /* Don't send AA data */
408 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
410 brw_land_fwd_jump(p
, jmp
);
411 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
416 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
417 struct brw_reg payload
)
419 assert(inst
->size_written
% REG_SIZE
== 0);
420 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
421 /* We assume that render targets start at binding table index 0. */
422 const unsigned surf_index
= inst
->target
;
424 gen9_fb_READ(p
, dst
, payload
, surf_index
,
425 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
426 prog_data
->persample_dispatch
);
428 brw_mark_surface_used(&prog_data
->base
, surf_index
);
432 fs_generator::generate_mov_indirect(fs_inst
*inst
,
435 struct brw_reg indirect_byte_offset
)
437 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
438 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
439 assert(!reg
.abs
&& !reg
.negate
);
440 assert(reg
.type
== dst
.type
);
442 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
444 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
445 imm_byte_offset
+= indirect_byte_offset
.ud
;
447 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
448 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
449 brw_MOV(p
, dst
, reg
);
451 /* Prior to Broadwell, there are only 8 address registers. */
452 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
454 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
455 struct brw_reg addr
= vec8(brw_address_reg(0));
457 /* The destination stride of an instruction (in bytes) must be greater
458 * than or equal to the size of the rest of the instruction. Since the
459 * address register is of type UW, we can't use a D-type instruction.
460 * In order to get around this, re retype to UW and use a stride.
462 indirect_byte_offset
=
463 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
465 /* There are a number of reasons why we don't use the base offset here.
466 * One reason is that the field is only 9 bits which means we can only
467 * use it to access the first 16 GRFs. Also, from the Haswell PRM
468 * section "Register Region Restrictions":
470 * "The lower bits of the AddressImmediate must not overflow to
471 * change the register address. The lower 5 bits of Address
472 * Immediate when added to lower 5 bits of address register gives
473 * the sub-register offset. The upper bits of Address Immediate
474 * when added to upper bits of address register gives the register
475 * address. Any overflow from sub-register offset is dropped."
477 * Since the indirect may cause us to cross a register boundary, this
478 * makes the base offset almost useless. We could try and do something
479 * clever where we use a actual base offset if base_offset % 32 == 0 but
480 * that would mean we were generating different code depending on the
481 * base offset. Instead, for the sake of consistency, we'll just do the
482 * add ourselves. This restriction is only listed in the Haswell PRM
483 * but empirical testing indicates that it applies on all older
484 * generations and is lifted on Broadwell.
486 * In the end, while base_offset is nice to look at in the generated
487 * code, using it saves us 0 instructions and would require quite a bit
488 * of case-by-case work. It's just not worth it.
490 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
492 if (type_sz(reg
.type
) > 4 &&
493 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
494 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
495 /* IVB has an issue (which we found empirically) where it reads two
496 * address register components per channel for indirectly addressed
499 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
501 * "When source or destination datatype is 64b or operation is
502 * integer DWord multiply, indirect addressing must not be used."
504 * To work around both of these, we do two integer MOVs insead of one
505 * 64-bit MOV. Because no double value should ever cross a register
506 * boundary, it's safe to use the immediate offset in the indirect
507 * here to handle adding 4 bytes to the offset and avoid the extra
508 * ADD to the register file.
510 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
511 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
512 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
513 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
515 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
517 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
519 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
520 !inst
->get_next()->is_tail_sentinel() &&
521 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
522 /* From the Sandybridge PRM:
524 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
525 * instruction that “indexed/indirect” source AND is followed
526 * by a send, the instruction requires a “Switch”. This is to
527 * avoid race condition where send may dispatch before MRF is
530 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
537 fs_generator::generate_shuffle(fs_inst
*inst
,
542 /* Ivy bridge has some strange behavior that makes this a real pain to
543 * implement for 64-bit values so we just don't bother.
545 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
547 /* Because we're using the address register, we're limited to 8-wide
548 * execution on gen7. On gen8, we're limited to 16-wide by the address
549 * register file and 8-wide for 64-bit types. We could try and make this
550 * instruction splittable higher up in the compiler but that gets weird
551 * because it reads all of the channels regardless of execution size. It's
552 * easier just to split it here.
554 const unsigned lower_width
=
555 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
556 8 : MIN2(16, inst
->exec_size
);
558 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
559 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
560 brw_set_default_group(p
, group
);
562 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
563 idx
.file
== BRW_IMMEDIATE_VALUE
) {
564 /* Trivial, the source is already uniform or the index is a constant.
565 * We will typically not get here if the optimizer is doing its job,
566 * but asserting would be mean.
568 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
569 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
571 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
572 struct brw_reg addr
= vec8(brw_address_reg(0));
574 struct brw_reg group_idx
= suboffset(idx
, group
);
576 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
577 /* Things get grumpy if the register is too wide. */
582 assert(type_sz(group_idx
.type
) <= 4);
583 if (type_sz(group_idx
.type
) == 4) {
584 /* The destination stride of an instruction (in bytes) must be
585 * greater than or equal to the size of the rest of the
586 * instruction. Since the address register is of type UW, we
587 * can't use a D-type instruction. In order to get around this,
588 * re retype to UW and use a stride.
590 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
593 /* Take into account the component size and horizontal stride. */
594 assert(src
.vstride
== src
.hstride
+ src
.width
);
595 brw_SHL(p
, addr
, group_idx
,
596 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
599 /* Add on the register start offset */
600 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
602 if (type_sz(src
.type
) > 4 &&
603 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
604 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
605 /* IVB has an issue (which we found empirically) where it reads
606 * two address register components per channel for indirectly
607 * addressed 64-bit sources.
609 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
611 * "When source or destination datatype is 64b or operation is
612 * integer DWord multiply, indirect addressing must not be
615 * To work around both of these, we do two integer MOVs insead of
616 * one 64-bit MOV. Because no double value should ever cross a
617 * register boundary, it's safe to use the immediate offset in the
618 * indirect here to handle adding 4 bytes to the offset and avoid
619 * the extra ADD to the register file.
621 struct brw_reg gdst
= suboffset(dst
, group
);
622 struct brw_reg dst_d
= retype(spread(gdst
, 2),
623 BRW_REGISTER_TYPE_D
);
625 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
626 brw_MOV(p
, byte_offset(dst_d
, 4),
627 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
629 brw_MOV(p
, suboffset(dst
, group
),
630 retype(brw_VxH_indirect(0, 0), src
.type
));
637 fs_generator::generate_urb_read(fs_inst
*inst
,
639 struct brw_reg header
)
641 assert(inst
->size_written
% REG_SIZE
== 0);
642 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
643 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
645 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
646 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
647 brw_set_src0(p
, send
, header
);
648 brw_set_src1(p
, send
, brw_imm_ud(0u));
650 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
651 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
653 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
654 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
656 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
657 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
658 brw_inst_set_header_present(p
->devinfo
, send
, true);
659 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
663 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
667 /* WaClearTDRRegBeforeEOTForNonPS.
669 * WA: Clear tdr register before send EOT in all non-PS shader kernels
671 * mov(8) tdr0:ud 0x0:ud {NoMask}"
673 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
674 brw_push_insn_state(p
);
675 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
676 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
677 brw_pop_insn_state(p
);
680 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
682 brw_set_dest(p
, insn
, brw_null_reg());
683 brw_set_src0(p
, insn
, payload
);
684 brw_set_src1(p
, insn
, brw_imm_d(0));
686 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
687 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
689 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
690 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
691 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
693 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
694 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
695 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
697 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
698 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
699 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
700 brw_inst_set_header_present(p
->devinfo
, insn
, true);
701 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
705 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
707 struct brw_inst
*insn
;
709 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
711 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
712 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
713 brw_set_src1(p
, insn
, brw_imm_d(0));
715 /* Terminate a compute shader by sending a message to the thread spawner.
717 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
718 brw_inst_set_mlen(devinfo
, insn
, 1);
719 brw_inst_set_rlen(devinfo
, insn
, 0);
720 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
721 brw_inst_set_header_present(devinfo
, insn
, false);
723 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
724 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
726 /* Note that even though the thread has a URB resource associated with it,
727 * we set the "do not dereference URB" bit, because the URB resource is
728 * managed by the fixed-function unit, so it will free it automatically.
730 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
732 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
736 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
743 fs_generator::generate_linterp(fs_inst
*inst
,
744 struct brw_reg dst
, struct brw_reg
*src
)
748 * -----------------------------------
749 * | src1+0 | src1+1 | src1+2 | src1+3 |
750 * |-----------------------------------|
751 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
752 * -----------------------------------
754 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
756 * -----------------------------------
757 * | src1+0 | src1+1 | src1+2 | src1+3 |
758 * |-----------------------------------|
759 * |(x0, x1)|(y0, y1)| | | in SIMD8
760 * |-----------------------------------|
761 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
762 * -----------------------------------
764 * See also: emit_interpolation_setup_gen4().
766 struct brw_reg delta_x
= src
[0];
767 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
768 struct brw_reg interp
= src
[1];
771 if (devinfo
->gen
>= 11) {
772 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF
);
773 struct brw_reg dwP
= suboffset(interp
, 0);
774 struct brw_reg dwQ
= suboffset(interp
, 1);
775 struct brw_reg dwR
= suboffset(interp
, 3);
777 brw_push_insn_state(p
);
778 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
780 if (inst
->exec_size
== 8) {
781 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
782 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_y
, 0), dwQ
);
784 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
786 /* brw_set_default_saturate() is called before emitting instructions,
787 * so the saturate bit is set in each instruction, so we need to unset
788 * it on the first instruction of each pair.
790 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
792 brw_set_default_group(p
, inst
->group
);
793 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
794 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_x
, 1), dwQ
);
796 brw_set_default_group(p
, inst
->group
+ 8);
797 i
[2] = brw_MAD(p
, acc
, dwR
, offset(delta_y
, 0), dwP
);
798 i
[3] = brw_MAD(p
, offset(dst
, 1), acc
, offset(delta_y
, 1), dwQ
);
800 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
801 brw_inst_set_cond_modifier(p
->devinfo
, i
[3], inst
->conditional_mod
);
803 /* brw_set_default_saturate() is called before emitting instructions,
804 * so the saturate bit is set in each instruction, so we need to unset
805 * it on the first instruction of each pair.
807 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
808 brw_inst_set_saturate(p
->devinfo
, i
[2], false);
811 brw_pop_insn_state(p
);
814 } else if (devinfo
->has_pln
) {
815 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
817 * "[DevSNB]:<src1> must be even register aligned.
819 * This restriction is lifted on Ivy Bridge.
821 assert(devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0);
822 brw_PLN(p
, dst
, interp
, delta_x
);
826 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
827 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
829 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
831 /* brw_set_default_saturate() is called before emitting instructions, so
832 * the saturate bit is set in each instruction, so we need to unset it on
833 * the first instruction.
835 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
842 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
845 struct brw_reg surf_index
)
847 assert(devinfo
->gen
>= 7);
848 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
853 switch (inst
->exec_size
) {
855 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
858 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
861 unreachable("Invalid width for texture instruction");
864 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
870 retype(dst
, BRW_REGISTER_TYPE_UW
),
875 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
876 rlen
, /* response length */
878 inst
->header_size
> 0,
880 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
882 brw_mark_surface_used(prog_data
, surf_index
.ud
);
886 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
887 struct brw_reg surface_index
,
888 struct brw_reg sampler_index
)
890 assert(inst
->size_written
% REG_SIZE
== 0);
893 uint32_t return_format
;
894 bool is_combined_send
= inst
->eot
;
897 case BRW_REGISTER_TYPE_D
:
898 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
900 case BRW_REGISTER_TYPE_UD
:
901 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
904 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
908 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
909 * is set as part of the message descriptor. On gen4, the PRM seems to
910 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
911 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
912 * gone from the message descriptor entirely and you just get UINT32 all
913 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
914 * just stomp it to UINT32 all the time.
916 if (inst
->opcode
== SHADER_OPCODE_TXS
)
917 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
919 switch (inst
->exec_size
) {
921 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
924 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
927 unreachable("Invalid width for texture instruction");
930 if (devinfo
->gen
>= 5) {
931 switch (inst
->opcode
) {
932 case SHADER_OPCODE_TEX
:
933 if (inst
->shadow_compare
) {
934 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
936 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
940 if (inst
->shadow_compare
) {
941 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
943 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
946 case SHADER_OPCODE_TXL
:
947 if (inst
->shadow_compare
) {
948 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
950 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
953 case SHADER_OPCODE_TXL_LZ
:
954 assert(devinfo
->gen
>= 9);
955 if (inst
->shadow_compare
) {
956 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
958 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
961 case SHADER_OPCODE_TXS
:
962 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
964 case SHADER_OPCODE_TXD
:
965 if (inst
->shadow_compare
) {
966 /* Gen7.5+. Otherwise, lowered in NIR */
967 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
968 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
970 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
973 case SHADER_OPCODE_TXF
:
974 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
976 case SHADER_OPCODE_TXF_LZ
:
977 assert(devinfo
->gen
>= 9);
978 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
980 case SHADER_OPCODE_TXF_CMS_W
:
981 assert(devinfo
->gen
>= 9);
982 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
984 case SHADER_OPCODE_TXF_CMS
:
985 if (devinfo
->gen
>= 7)
986 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
988 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
990 case SHADER_OPCODE_TXF_UMS
:
991 assert(devinfo
->gen
>= 7);
992 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
994 case SHADER_OPCODE_TXF_MCS
:
995 assert(devinfo
->gen
>= 7);
996 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
998 case SHADER_OPCODE_LOD
:
999 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1001 case SHADER_OPCODE_TG4
:
1002 if (inst
->shadow_compare
) {
1003 assert(devinfo
->gen
>= 7);
1004 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
1006 assert(devinfo
->gen
>= 6);
1007 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1010 case SHADER_OPCODE_TG4_OFFSET
:
1011 assert(devinfo
->gen
>= 7);
1012 if (inst
->shadow_compare
) {
1013 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
1015 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
1018 case SHADER_OPCODE_SAMPLEINFO
:
1019 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1022 unreachable("not reached");
1025 switch (inst
->opcode
) {
1026 case SHADER_OPCODE_TEX
:
1027 /* Note that G45 and older determines shadow compare and dispatch width
1028 * from message length for most messages.
1030 if (inst
->exec_size
== 8) {
1031 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1032 if (inst
->shadow_compare
) {
1033 assert(inst
->mlen
== 6);
1035 assert(inst
->mlen
<= 4);
1038 if (inst
->shadow_compare
) {
1039 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1040 assert(inst
->mlen
== 9);
1042 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1043 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1048 if (inst
->shadow_compare
) {
1049 assert(inst
->exec_size
== 8);
1050 assert(inst
->mlen
== 6);
1051 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1053 assert(inst
->mlen
== 9);
1054 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1055 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1058 case SHADER_OPCODE_TXL
:
1059 if (inst
->shadow_compare
) {
1060 assert(inst
->exec_size
== 8);
1061 assert(inst
->mlen
== 6);
1062 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1064 assert(inst
->mlen
== 9);
1065 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1066 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1069 case SHADER_OPCODE_TXD
:
1070 /* There is no sample_d_c message; comparisons are done manually */
1071 assert(inst
->exec_size
== 8);
1072 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1073 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1075 case SHADER_OPCODE_TXF
:
1076 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1077 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1078 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1080 case SHADER_OPCODE_TXS
:
1081 assert(inst
->mlen
== 3);
1082 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1083 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1086 unreachable("not reached");
1089 assert(msg_type
!= -1);
1091 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1095 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
1096 src
.file
== BRW_GENERAL_REGISTER_FILE
);
1098 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1100 /* Load the message header if present. If there's a texture offset,
1101 * we need to set it up explicitly and load the offset bitfield.
1102 * Otherwise, we can use an implied move from g0 to the first message reg.
1104 if (inst
->header_size
!= 0 && devinfo
->gen
< 7) {
1105 if (devinfo
->gen
< 6 && !inst
->offset
) {
1106 /* Set up an implied move from g0 to the MRF. */
1107 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1109 assert(inst
->base_mrf
!= -1);
1110 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1112 brw_push_insn_state(p
);
1113 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1114 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1115 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1116 /* Explicitly set up the message header by copying g0 to the MRF. */
1117 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1119 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1121 /* Set the offset bits in DWord 2. */
1122 brw_MOV(p
, get_element_ud(header_reg
, 2),
1123 brw_imm_ud(inst
->offset
));
1126 brw_pop_insn_state(p
);
1130 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
1131 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
1132 ? prog_data
->binding_table
.gather_texture_start
1133 : prog_data
->binding_table
.texture_start
;
1135 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
1136 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
1137 uint32_t surface
= surface_index
.ud
;
1138 uint32_t sampler
= sampler_index
.ud
;
1141 retype(dst
, BRW_REGISTER_TYPE_UW
),
1144 surface
+ base_binding_table_index
,
1147 inst
->size_written
/ REG_SIZE
,
1149 inst
->header_size
!= 0,
1153 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1155 /* Non-const sampler index */
1157 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1158 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1159 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1161 brw_push_insn_state(p
);
1162 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1163 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1164 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1166 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
1167 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1169 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
1170 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
1172 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1173 brw_OR(p
, addr
, addr
, surface_reg
);
1176 if (base_binding_table_index
)
1177 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1178 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1180 brw_pop_insn_state(p
);
1182 /* dst = send(offset, a0.0 | <descriptor>) */
1183 brw_inst
*insn
= brw_send_indirect_message(
1184 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1185 brw_set_sampler_message(p
, insn
,
1189 inst
->size_written
/ REG_SIZE
,
1190 inst
->mlen
/* mlen */,
1191 inst
->header_size
!= 0 /* header */,
1195 /* visitor knows more than we do about the surface limit required,
1196 * so has already done marking.
1200 if (is_combined_send
) {
1201 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1202 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1207 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1210 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1212 * Ideally, we want to produce:
1215 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1216 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1217 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1218 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1219 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1220 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1221 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1222 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1224 * and add another set of two more subspans if in 16-pixel dispatch mode.
1226 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1227 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1228 * pair. But the ideal approximation may impose a huge performance cost on
1229 * sample_d. On at least Haswell, sample_d instruction does some
1230 * optimizations if the same LOD is used for all pixels in the subspan.
1232 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1233 * appropriate swizzling.
1236 fs_generator::generate_ddx(const fs_inst
*inst
,
1237 struct brw_reg dst
, struct brw_reg src
)
1239 unsigned vstride
, width
;
1241 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1242 /* produce accurate derivatives */
1243 vstride
= BRW_VERTICAL_STRIDE_2
;
1244 width
= BRW_WIDTH_2
;
1246 /* replicate the derivative at the top-left pixel to other pixels */
1247 vstride
= BRW_VERTICAL_STRIDE_4
;
1248 width
= BRW_WIDTH_4
;
1251 struct brw_reg src0
= src
;
1252 struct brw_reg src1
= src
;
1254 src0
.subnr
= sizeof(float);
1255 src0
.vstride
= vstride
;
1257 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1258 src1
.vstride
= vstride
;
1260 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1262 brw_ADD(p
, dst
, src0
, negate(src1
));
1265 /* The negate_value boolean is used to negate the derivative computation for
1266 * FBOs, since they place the origin at the upper left instead of the lower
1270 fs_generator::generate_ddy(const fs_inst
*inst
,
1271 struct brw_reg dst
, struct brw_reg src
)
1273 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1274 /* produce accurate derivatives */
1275 if (devinfo
->gen
>= 11) {
1276 src
= stride(src
, 0, 2, 1);
1277 struct brw_reg src_0
= byte_offset(src
, 0 * sizeof(float));
1278 struct brw_reg src_2
= byte_offset(src
, 2 * sizeof(float));
1279 struct brw_reg src_4
= byte_offset(src
, 4 * sizeof(float));
1280 struct brw_reg src_6
= byte_offset(src
, 6 * sizeof(float));
1281 struct brw_reg src_8
= byte_offset(src
, 8 * sizeof(float));
1282 struct brw_reg src_10
= byte_offset(src
, 10 * sizeof(float));
1283 struct brw_reg src_12
= byte_offset(src
, 12 * sizeof(float));
1284 struct brw_reg src_14
= byte_offset(src
, 14 * sizeof(float));
1286 struct brw_reg dst_0
= byte_offset(dst
, 0 * sizeof(float));
1287 struct brw_reg dst_4
= byte_offset(dst
, 4 * sizeof(float));
1288 struct brw_reg dst_8
= byte_offset(dst
, 8 * sizeof(float));
1289 struct brw_reg dst_12
= byte_offset(dst
, 12 * sizeof(float));
1291 brw_push_insn_state(p
);
1292 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1294 brw_ADD(p
, dst_0
, negate(src_0
), src_2
);
1295 brw_ADD(p
, dst_4
, negate(src_4
), src_6
);
1297 if (inst
->exec_size
== 16) {
1298 brw_ADD(p
, dst_8
, negate(src_8
), src_10
);
1299 brw_ADD(p
, dst_12
, negate(src_12
), src_14
);
1302 brw_pop_insn_state(p
);
1304 struct brw_reg src0
= stride(src
, 4, 4, 1);
1305 struct brw_reg src1
= stride(src
, 4, 4, 1);
1306 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1307 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1309 brw_push_insn_state(p
);
1310 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1311 brw_ADD(p
, dst
, negate(src0
), src1
);
1312 brw_pop_insn_state(p
);
1315 /* replicate the derivative at the top-left pixel to other pixels */
1316 struct brw_reg src0
= stride(src
, 4, 4, 0);
1317 struct brw_reg src1
= stride(src
, 4, 4, 0);
1318 src0
.subnr
= 0 * sizeof(float);
1319 src1
.subnr
= 2 * sizeof(float);
1321 brw_ADD(p
, dst
, negate(src0
), src1
);
1326 fs_generator::generate_discard_jump(fs_inst
*)
1328 assert(devinfo
->gen
>= 6);
1330 /* This HALT will be patched up at FB write time to point UIP at the end of
1331 * the program, and at brw_uip_jip() JIP will be set to the end of the
1332 * current block (or the program).
1334 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1339 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1341 /* The 32-wide messages only respect the first 16-wide half of the channel
1342 * enable signals which are replicated identically for the second group of
1343 * 16 channels, so we cannot use them unless the write is marked
1344 * force_writemask_all.
1346 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1347 MIN2(16, inst
->exec_size
);
1348 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1349 assert(inst
->mlen
!= 0);
1351 brw_push_insn_state(p
);
1352 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1353 brw_set_default_compression(p
, lower_size
> 8);
1355 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1356 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1358 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1359 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1361 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1363 inst
->offset
+ block_size
* REG_SIZE
* i
);
1366 brw_pop_insn_state(p
);
1370 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1372 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1373 assert(inst
->mlen
!= 0);
1375 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1376 inst
->exec_size
/ 8, inst
->offset
);
1380 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1382 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1384 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1388 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1390 struct brw_reg index
,
1391 struct brw_reg offset
)
1393 assert(type_sz(dst
.type
) == 4);
1394 assert(inst
->mlen
!= 0);
1396 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1397 index
.type
== BRW_REGISTER_TYPE_UD
);
1398 uint32_t surf_index
= index
.ud
;
1400 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1401 offset
.type
== BRW_REGISTER_TYPE_UD
);
1402 uint32_t read_offset
= offset
.ud
;
1404 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1405 read_offset
, surf_index
);
1409 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1411 struct brw_reg index
,
1412 struct brw_reg payload
)
1414 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1415 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1416 assert(type_sz(dst
.type
) == 4);
1418 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1419 const uint32_t surf_index
= index
.ud
;
1421 brw_push_insn_state(p
);
1422 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1423 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1424 brw_pop_insn_state(p
);
1426 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1427 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1428 brw_set_dp_read_message(p
, send
, surf_index
,
1429 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1430 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1431 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1434 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1437 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1439 brw_push_insn_state(p
);
1440 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1442 /* a0.0 = surf_index & 0xff */
1443 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1444 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1445 brw_set_dest(p
, insn_and
, addr
);
1446 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1447 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1449 /* dst = send(payload, a0.0 | <descriptor>) */
1450 brw_inst
*insn
= brw_send_indirect_message(
1451 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1452 retype(dst
, BRW_REGISTER_TYPE_UD
),
1453 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
);
1454 brw_set_dp_read_message(p
, insn
, 0 /* surface */,
1455 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1456 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1457 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1460 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1462 brw_pop_insn_state(p
);
1467 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1469 struct brw_reg index
)
1471 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1472 assert(inst
->header_size
!= 0);
1475 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1476 index
.type
== BRW_REGISTER_TYPE_UD
);
1477 uint32_t surf_index
= index
.ud
;
1479 uint32_t simd_mode
, rlen
, msg_type
;
1480 if (inst
->exec_size
== 16) {
1481 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1484 assert(inst
->exec_size
== 8);
1485 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1489 if (devinfo
->gen
>= 5)
1490 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1492 /* We always use the SIMD16 message so that we only have to load U, and
1495 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1496 assert(inst
->mlen
== 3);
1497 assert(inst
->size_written
== 8 * REG_SIZE
);
1499 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1502 struct brw_reg header
= brw_vec8_grf(0, 0);
1503 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1505 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1506 brw_inst_set_compression(devinfo
, send
, false);
1507 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1508 brw_set_src0(p
, send
, header
);
1509 if (devinfo
->gen
< 6)
1510 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1512 /* Our surface is set up as floats, regardless of what actual data is
1515 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1516 brw_set_sampler_message(p
, send
,
1518 0, /* sampler (unused) */
1522 inst
->header_size
!= 0,
1528 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1530 struct brw_reg index
,
1531 struct brw_reg offset
)
1533 assert(devinfo
->gen
>= 7);
1534 /* Varying-offset pull constant loads are treated as a normal expression on
1535 * gen7, so the fact that it's a send message is hidden at the IR level.
1537 assert(inst
->header_size
== 0);
1538 assert(!inst
->mlen
);
1539 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1541 uint32_t simd_mode
, rlen
, mlen
;
1542 if (inst
->exec_size
== 16) {
1545 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1547 assert(inst
->exec_size
== 8);
1550 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1553 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1555 uint32_t surf_index
= index
.ud
;
1557 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1558 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1559 brw_set_src0(p
, send
, offset
);
1560 brw_set_sampler_message(p
, send
,
1562 0, /* LD message ignores sampler unit */
1563 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1566 false, /* no header */
1572 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1574 brw_push_insn_state(p
);
1575 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1577 /* a0.0 = surf_index & 0xff */
1578 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1579 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1580 brw_set_dest(p
, insn_and
, addr
);
1581 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1582 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1584 brw_pop_insn_state(p
);
1586 /* dst = send(offset, a0.0 | <descriptor>) */
1587 brw_inst
*insn
= brw_send_indirect_message(
1588 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1590 brw_set_sampler_message(p
, insn
,
1593 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1603 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1604 * into the flags register (f0.0).
1606 * Used only on Gen6 and above.
1609 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1611 struct brw_reg flags
= brw_flag_subreg(inst
->flag_subreg
);
1612 struct brw_reg dispatch_mask
;
1614 if (devinfo
->gen
>= 6)
1615 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1617 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1619 brw_push_insn_state(p
);
1620 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1621 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1622 brw_MOV(p
, flags
, dispatch_mask
);
1623 brw_pop_insn_state(p
);
1627 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1630 struct brw_reg msg_data
,
1633 assert(inst
->size_written
% REG_SIZE
== 0);
1634 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1636 brw_pixel_interpolator_query(p
,
1637 retype(dst
, BRW_REGISTER_TYPE_UW
),
1639 inst
->pi_noperspective
,
1643 inst
->size_written
/ REG_SIZE
);
1646 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1647 * the ADD instruction.
1650 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1652 struct brw_reg src0
,
1653 struct brw_reg src1
)
1655 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1656 dst
.type
== BRW_REGISTER_TYPE_UD
);
1657 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1658 src0
.type
== BRW_REGISTER_TYPE_UD
);
1660 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1661 if (devinfo
->gen
>= 8 || inst
->exec_size
== 8) {
1662 brw_ADD(p
, dst
, src0
, reg
);
1663 } else if (inst
->exec_size
== 16) {
1664 brw_push_insn_state(p
);
1665 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1666 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1667 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1668 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1669 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1670 brw_pop_insn_state(p
);
1675 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1680 assert(devinfo
->gen
>= 7);
1681 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1682 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1683 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1685 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1687 * Because this instruction does not have a 16-bit floating-point type,
1688 * the destination data type must be Word (W).
1690 * The destination must be DWord-aligned and specify a horizontal stride
1691 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1692 * each destination channel and the upper word is not modified.
1694 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1696 /* Give each 32-bit channel of dst the form below, where "." means
1700 brw_F32TO16(p
, dst_w
, y
);
1705 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1707 /* And, finally the form of packHalf2x16's output:
1710 brw_F32TO16(p
, dst_w
, x
);
1714 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1718 assert(devinfo
->gen
>= 7);
1719 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1720 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1722 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1724 * Because this instruction does not have a 16-bit floating-point type,
1725 * the source data type must be Word (W). The destination type must be
1728 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1730 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1731 * For the Y case, we wish to access only the upper word; therefore
1732 * a 16-bit subregister offset is needed.
1734 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1735 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1736 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1739 brw_F16TO32(p
, dst
, src_w
);
1743 fs_generator::generate_shader_time_add(fs_inst
*,
1744 struct brw_reg payload
,
1745 struct brw_reg offset
,
1746 struct brw_reg value
)
1748 assert(devinfo
->gen
>= 7);
1749 brw_push_insn_state(p
);
1750 brw_set_default_mask_control(p
, true);
1752 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1753 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1755 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1758 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1759 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1760 value
.width
= BRW_WIDTH_1
;
1761 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1762 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1764 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1767 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1768 * case, and we don't really care about squeezing every bit of performance
1769 * out of this path, so we just emit the MOVs from here.
1771 brw_MOV(p
, payload_offset
, offset
);
1772 brw_MOV(p
, payload_value
, value
);
1773 brw_shader_time_add(p
, payload
,
1774 prog_data
->binding_table
.shader_time_start
);
1775 brw_pop_insn_state(p
);
1777 brw_mark_surface_used(prog_data
,
1778 prog_data
->binding_table
.shader_time_start
);
1782 fs_generator::enable_debug(const char *shader_name
)
1785 this->shader_name
= shader_name
;
1789 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1791 /* align to 64 byte boundary. */
1792 while (p
->next_insn_offset
% 64)
1795 this->dispatch_width
= dispatch_width
;
1797 int start_offset
= p
->next_insn_offset
;
1798 int spill_count
= 0, fill_count
= 0;
1801 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1803 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1804 struct brw_reg src
[3], dst
;
1805 unsigned int last_insn_offset
= p
->next_insn_offset
;
1806 bool multiple_instructions_emitted
= false;
1808 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1809 * "Register Region Restrictions" section: for BDW, SKL:
1811 * "A POW/FDIV operation must not be followed by an instruction
1812 * that requires two destination registers."
1814 * The documentation is often lacking annotations for Atom parts,
1815 * and empirically this affects CHV as well.
1817 if (devinfo
->gen
>= 8 &&
1818 devinfo
->gen
<= 9 &&
1820 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1821 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1822 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1824 last_insn_offset
= p
->next_insn_offset
;
1827 if (unlikely(debug_flag
))
1828 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1830 /* If the instruction writes to more than one register, it needs to be
1831 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1832 * hardware figures out by itself what the right compression mode is,
1833 * but we still need to know whether the instruction is compressed to
1834 * set up the source register regions appropriately.
1836 * XXX - This is wrong for instructions that write a single register but
1837 * read more than one which should strictly speaking be treated as
1838 * compressed. For instructions that don't write any registers it
1839 * relies on the destination being a null register of the correct
1840 * type and regioning so the instruction is considered compressed
1841 * or not accordingly.
1843 const bool compressed
=
1844 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1845 brw_set_default_compression(p
, compressed
);
1846 brw_set_default_group(p
, inst
->group
);
1848 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1849 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1850 &inst
->src
[i
], compressed
);
1851 /* The accumulator result appears to get used for the
1852 * conditional modifier generation. When negating a UD
1853 * value, there is a 33rd bit generated for the sign in the
1854 * accumulator value, so now you can't check, for example,
1855 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1857 assert(!inst
->conditional_mod
||
1858 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1859 !inst
->src
[i
].negate
);
1861 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1862 &inst
->dst
, compressed
);
1864 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1865 brw_set_default_predicate_control(p
, inst
->predicate
);
1866 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1867 brw_set_default_flag_reg(p
, inst
->flag_subreg
/ 2, inst
->flag_subreg
% 2);
1868 brw_set_default_saturate(p
, inst
->saturate
);
1869 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1870 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1872 unsigned exec_size
= inst
->exec_size
;
1873 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1874 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1878 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1880 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1881 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1882 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1883 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1885 switch (inst
->opcode
) {
1886 case BRW_OPCODE_MOV
:
1887 brw_MOV(p
, dst
, src
[0]);
1889 case BRW_OPCODE_ADD
:
1890 brw_ADD(p
, dst
, src
[0], src
[1]);
1892 case BRW_OPCODE_MUL
:
1893 brw_MUL(p
, dst
, src
[0], src
[1]);
1895 case BRW_OPCODE_AVG
:
1896 brw_AVG(p
, dst
, src
[0], src
[1]);
1898 case BRW_OPCODE_MACH
:
1899 brw_MACH(p
, dst
, src
[0], src
[1]);
1902 case BRW_OPCODE_LINE
:
1903 brw_LINE(p
, dst
, src
[0], src
[1]);
1906 case BRW_OPCODE_MAD
:
1907 assert(devinfo
->gen
>= 6);
1908 if (devinfo
->gen
< 10)
1909 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1910 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1913 case BRW_OPCODE_LRP
:
1914 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1915 if (devinfo
->gen
< 10)
1916 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1917 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1920 case BRW_OPCODE_FRC
:
1921 brw_FRC(p
, dst
, src
[0]);
1923 case BRW_OPCODE_RNDD
:
1924 brw_RNDD(p
, dst
, src
[0]);
1926 case BRW_OPCODE_RNDE
:
1927 brw_RNDE(p
, dst
, src
[0]);
1929 case BRW_OPCODE_RNDZ
:
1930 brw_RNDZ(p
, dst
, src
[0]);
1933 case BRW_OPCODE_AND
:
1934 brw_AND(p
, dst
, src
[0], src
[1]);
1937 brw_OR(p
, dst
, src
[0], src
[1]);
1939 case BRW_OPCODE_XOR
:
1940 brw_XOR(p
, dst
, src
[0], src
[1]);
1942 case BRW_OPCODE_NOT
:
1943 brw_NOT(p
, dst
, src
[0]);
1945 case BRW_OPCODE_ASR
:
1946 brw_ASR(p
, dst
, src
[0], src
[1]);
1948 case BRW_OPCODE_SHR
:
1949 brw_SHR(p
, dst
, src
[0], src
[1]);
1951 case BRW_OPCODE_SHL
:
1952 brw_SHL(p
, dst
, src
[0], src
[1]);
1954 case BRW_OPCODE_F32TO16
:
1955 assert(devinfo
->gen
>= 7);
1956 brw_F32TO16(p
, dst
, src
[0]);
1958 case BRW_OPCODE_F16TO32
:
1959 assert(devinfo
->gen
>= 7);
1960 brw_F16TO32(p
, dst
, src
[0]);
1962 case BRW_OPCODE_CMP
:
1963 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1964 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1965 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1966 * implemented in the compiler is not sufficient. Overriding the
1967 * type when the destination is the null register is necessary but
1968 * not sufficient by itself.
1970 assert(dst
.nr
== BRW_ARF_NULL
);
1971 dst
.type
= BRW_REGISTER_TYPE_D
;
1973 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1975 case BRW_OPCODE_SEL
:
1976 brw_SEL(p
, dst
, src
[0], src
[1]);
1978 case BRW_OPCODE_CSEL
:
1979 assert(devinfo
->gen
>= 8);
1980 if (devinfo
->gen
< 10)
1981 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1982 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1984 case BRW_OPCODE_BFREV
:
1985 assert(devinfo
->gen
>= 7);
1986 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1987 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1989 case BRW_OPCODE_FBH
:
1990 assert(devinfo
->gen
>= 7);
1991 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1993 case BRW_OPCODE_FBL
:
1994 assert(devinfo
->gen
>= 7);
1995 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1996 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1998 case BRW_OPCODE_LZD
:
1999 brw_LZD(p
, dst
, src
[0]);
2001 case BRW_OPCODE_CBIT
:
2002 assert(devinfo
->gen
>= 7);
2003 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
2004 retype(src
[0], BRW_REGISTER_TYPE_UD
));
2006 case BRW_OPCODE_ADDC
:
2007 assert(devinfo
->gen
>= 7);
2008 brw_ADDC(p
, dst
, src
[0], src
[1]);
2010 case BRW_OPCODE_SUBB
:
2011 assert(devinfo
->gen
>= 7);
2012 brw_SUBB(p
, dst
, src
[0], src
[1]);
2014 case BRW_OPCODE_MAC
:
2015 brw_MAC(p
, dst
, src
[0], src
[1]);
2018 case BRW_OPCODE_BFE
:
2019 assert(devinfo
->gen
>= 7);
2020 if (devinfo
->gen
< 10)
2021 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2022 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
2025 case BRW_OPCODE_BFI1
:
2026 assert(devinfo
->gen
>= 7);
2027 brw_BFI1(p
, dst
, src
[0], src
[1]);
2029 case BRW_OPCODE_BFI2
:
2030 assert(devinfo
->gen
>= 7);
2031 if (devinfo
->gen
< 10)
2032 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2033 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2037 if (inst
->src
[0].file
!= BAD_FILE
) {
2038 /* The instruction has an embedded compare (only allowed on gen6) */
2039 assert(devinfo
->gen
== 6);
2040 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2042 brw_IF(p
, brw_get_default_exec_size(p
));
2046 case BRW_OPCODE_ELSE
:
2049 case BRW_OPCODE_ENDIF
:
2054 brw_DO(p
, brw_get_default_exec_size(p
));
2057 case BRW_OPCODE_BREAK
:
2060 case BRW_OPCODE_CONTINUE
:
2064 case BRW_OPCODE_WHILE
:
2069 case SHADER_OPCODE_RCP
:
2070 case SHADER_OPCODE_RSQ
:
2071 case SHADER_OPCODE_SQRT
:
2072 case SHADER_OPCODE_EXP2
:
2073 case SHADER_OPCODE_LOG2
:
2074 case SHADER_OPCODE_SIN
:
2075 case SHADER_OPCODE_COS
:
2076 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2077 if (devinfo
->gen
>= 6) {
2078 assert(inst
->mlen
== 0);
2079 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2080 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2081 src
[0], brw_null_reg());
2083 assert(inst
->mlen
>= 1);
2084 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2086 brw_math_function(inst
->opcode
),
2087 inst
->base_mrf
, src
[0],
2088 BRW_MATH_PRECISION_FULL
);
2091 case SHADER_OPCODE_INT_QUOTIENT
:
2092 case SHADER_OPCODE_INT_REMAINDER
:
2093 case SHADER_OPCODE_POW
:
2094 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2095 if (devinfo
->gen
>= 6) {
2096 assert(inst
->mlen
== 0);
2097 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2098 inst
->exec_size
== 8);
2099 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2101 assert(inst
->mlen
>= 1);
2102 assert(inst
->exec_size
== 8);
2103 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2104 inst
->base_mrf
, src
[0],
2105 BRW_MATH_PRECISION_FULL
);
2108 case FS_OPCODE_LINTERP
:
2109 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2111 case FS_OPCODE_PIXEL_X
:
2112 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2113 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2114 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2116 case FS_OPCODE_PIXEL_Y
:
2117 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2118 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2119 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2121 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2122 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2124 case SHADER_OPCODE_TEX
:
2126 case SHADER_OPCODE_TXD
:
2127 case SHADER_OPCODE_TXF
:
2128 case SHADER_OPCODE_TXF_LZ
:
2129 case SHADER_OPCODE_TXF_CMS
:
2130 case SHADER_OPCODE_TXF_CMS_W
:
2131 case SHADER_OPCODE_TXF_UMS
:
2132 case SHADER_OPCODE_TXF_MCS
:
2133 case SHADER_OPCODE_TXL
:
2134 case SHADER_OPCODE_TXL_LZ
:
2135 case SHADER_OPCODE_TXS
:
2136 case SHADER_OPCODE_LOD
:
2137 case SHADER_OPCODE_TG4
:
2138 case SHADER_OPCODE_TG4_OFFSET
:
2139 case SHADER_OPCODE_SAMPLEINFO
:
2140 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2142 case FS_OPCODE_DDX_COARSE
:
2143 case FS_OPCODE_DDX_FINE
:
2144 generate_ddx(inst
, dst
, src
[0]);
2146 case FS_OPCODE_DDY_COARSE
:
2147 case FS_OPCODE_DDY_FINE
:
2148 generate_ddy(inst
, dst
, src
[0]);
2151 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2152 generate_scratch_write(inst
, src
[0]);
2156 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2157 generate_scratch_read(inst
, dst
);
2161 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2162 generate_scratch_read_gen7(inst
, dst
);
2166 case SHADER_OPCODE_MOV_INDIRECT
:
2167 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2170 case SHADER_OPCODE_URB_READ_SIMD8
:
2171 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2172 generate_urb_read(inst
, dst
, src
[0]);
2175 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2176 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2177 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2178 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2179 generate_urb_write(inst
, src
[0]);
2182 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2183 assert(inst
->force_writemask_all
);
2184 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2187 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2188 assert(inst
->force_writemask_all
);
2189 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2192 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2193 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2196 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2197 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2200 case FS_OPCODE_REP_FB_WRITE
:
2201 case FS_OPCODE_FB_WRITE
:
2202 generate_fb_write(inst
, src
[0]);
2205 case FS_OPCODE_FB_READ
:
2206 generate_fb_read(inst
, dst
, src
[0]);
2209 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2210 generate_mov_dispatch_to_flags(inst
);
2213 case FS_OPCODE_DISCARD_JUMP
:
2214 generate_discard_jump(inst
);
2217 case SHADER_OPCODE_SHADER_TIME_ADD
:
2218 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2221 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2222 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2223 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2224 inst
->mlen
, !inst
->dst
.is_null(),
2228 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2229 assert(!inst
->header_size
);
2230 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2231 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2232 inst
->mlen
, src
[2].ud
);
2235 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2236 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2237 brw_untyped_surface_write(p
, src
[0], src
[1],
2238 inst
->mlen
, src
[2].ud
,
2242 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
2243 assert(!inst
->header_size
);
2244 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2245 brw_byte_scattered_read(p
, dst
, src
[0], src
[1],
2246 inst
->mlen
, src
[2].ud
);
2249 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
2250 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2251 brw_byte_scattered_write(p
, src
[0], src
[1],
2252 inst
->mlen
, src
[2].ud
,
2256 case SHADER_OPCODE_TYPED_ATOMIC
:
2257 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2258 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2259 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null(),
2263 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2264 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2265 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2266 inst
->mlen
, src
[2].ud
,
2270 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2271 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2272 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
,
2276 case SHADER_OPCODE_MEMORY_FENCE
:
2277 brw_memory_fence(p
, dst
, BRW_OPCODE_SEND
);
2280 case SHADER_OPCODE_INTERLOCK
:
2281 /* The interlock is basically a memory fence issued via sendc */
2282 brw_memory_fence(p
, dst
, BRW_OPCODE_SENDC
);
2285 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2286 const struct brw_reg mask
=
2287 brw_stage_has_packed_dispatch(devinfo
, stage
,
2288 prog_data
) ? brw_imm_ud(~0u) :
2289 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2291 brw_find_live_channel(p
, dst
, mask
);
2295 case SHADER_OPCODE_BROADCAST
:
2296 assert(inst
->force_writemask_all
);
2297 brw_broadcast(p
, dst
, src
[0], src
[1]);
2300 case SHADER_OPCODE_SHUFFLE
:
2301 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2304 case SHADER_OPCODE_SEL_EXEC
:
2305 assert(inst
->force_writemask_all
);
2306 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2307 brw_MOV(p
, dst
, src
[1]);
2308 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2309 brw_MOV(p
, dst
, src
[0]);
2312 case SHADER_OPCODE_QUAD_SWIZZLE
:
2313 /* This only works on 8-wide 32-bit values */
2314 assert(inst
->exec_size
== 8);
2315 assert(type_sz(src
[0].type
) == 4);
2316 assert(inst
->force_writemask_all
);
2317 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2318 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2320 if (src
[0].file
== BRW_IMMEDIATE_VALUE
||
2321 (src
[0].vstride
== 0 && src
[0].hstride
== 0)) {
2322 /* The value is uniform across all channels */
2323 brw_MOV(p
, dst
, src
[0]);
2325 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2326 struct brw_reg swiz_src
= stride(src
[0], 4, 4, 1);
2327 swiz_src
.swizzle
= inst
->src
[1].ud
;
2328 brw_MOV(p
, dst
, swiz_src
);
2332 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2333 assert(src
[0].type
== dst
.type
);
2334 assert(!src
[0].negate
&& !src
[0].abs
);
2335 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2336 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2337 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2338 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2339 const unsigned component
= src
[1].ud
;
2340 const unsigned cluster_size
= src
[2].ud
;
2341 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2342 cluster_size
, cluster_size
, 0);
2343 if (type_sz(src
[0].type
) > 4 &&
2344 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2345 /* IVB has an issue (which we found empirically) where it reads
2346 * two address register components per channel for indirectly
2347 * addressed 64-bit sources.
2349 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2351 * "When source or destination datatype is 64b or operation is
2352 * integer DWord multiply, indirect addressing must not be
2355 * To work around both of these, we do two integer MOVs insead of
2356 * one 64-bit MOV. Because no double value should ever cross a
2357 * register boundary, it's safe to use the immediate offset in the
2358 * indirect here to handle adding 4 bytes to the offset and avoid
2359 * the extra ADD to the register file.
2361 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2362 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2363 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2364 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2366 brw_MOV(p
, dst
, strided
);
2371 case FS_OPCODE_SET_SAMPLE_ID
:
2372 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2375 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2376 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2379 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2380 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2381 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2384 case FS_OPCODE_PLACEHOLDER_HALT
:
2385 /* This is the place where the final HALT needs to be inserted if
2386 * we've emitted any discards. If not, this will emit no code.
2388 if (!patch_discard_jumps_to_fb_writes()) {
2389 if (unlikely(debug_flag
)) {
2390 disasm_info
->use_tail
= true;
2395 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2396 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2397 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2400 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2401 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2402 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2405 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2406 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2407 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2410 case CS_OPCODE_CS_TERMINATE
:
2411 generate_cs_terminate(inst
, src
[0]);
2414 case SHADER_OPCODE_BARRIER
:
2415 generate_barrier(inst
, src
[0]);
2418 case BRW_OPCODE_DIM
:
2419 assert(devinfo
->is_haswell
);
2420 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2421 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2422 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2425 case SHADER_OPCODE_RND_MODE
:
2426 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2427 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2431 unreachable("Unsupported opcode");
2433 case SHADER_OPCODE_LOAD_PAYLOAD
:
2434 unreachable("Should be lowered by lower_load_payload()");
2437 if (multiple_instructions_emitted
)
2440 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2441 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2442 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2443 "emitting more than 1 instruction");
2445 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2447 if (inst
->conditional_mod
)
2448 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2449 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2450 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2454 brw_set_uip_jip(p
, start_offset
);
2456 /* end of program sentinel */
2457 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2462 if (unlikely(debug_flag
))
2464 brw_validate_instructions(devinfo
, p
->store
,
2466 p
->next_insn_offset
,
2469 int before_size
= p
->next_insn_offset
- start_offset
;
2470 brw_compact_instructions(p
, start_offset
, disasm_info
);
2471 int after_size
= p
->next_insn_offset
- start_offset
;
2473 if (unlikely(debug_flag
)) {
2474 fprintf(stderr
, "Native code for %s\n"
2475 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2476 " bytes (%.0f%%)\n",
2477 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2478 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2479 100.0f
* (before_size
- after_size
) / before_size
);
2481 dump_assembly(p
->store
, disasm_info
);
2483 ralloc_free(disasm_info
);
2486 compiler
->shader_debug_log(log_data
,
2487 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2488 "%d:%d spills:fills, Promoted %u constants, "
2489 "compacted %d to %d bytes.",
2490 _mesa_shader_stage_to_abbrev(stage
),
2491 dispatch_width
, before_size
/ 16,
2492 loop_count
, cfg
->cycle_count
, spill_count
,
2493 fill_count
, promoted_constants
, before_size
,
2496 return start_offset
;
2500 fs_generator::get_assembly()
2502 return brw_get_program(p
, &prog_data
->program_size
);