2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
178 struct brw_stage_prog_data
*prog_data
,
179 unsigned promoted_constants
,
180 bool runtime_check_aads_emit
,
181 gl_shader_stage stage
)
183 : compiler(compiler
), log_data(log_data
),
184 devinfo(compiler
->devinfo
),
185 prog_data(prog_data
),
186 promoted_constants(promoted_constants
),
187 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
188 stage(stage
), mem_ctx(mem_ctx
)
190 p
= rzalloc(mem_ctx
, struct brw_codegen
);
191 brw_init_codegen(devinfo
, p
, mem_ctx
);
193 /* In the FS code generator, we are very careful to ensure that we always
194 * set the right execution size so we don't need the EU code to "help" us
195 * by trying to infer it. Sometimes, it infers the wrong thing.
197 p
->automatic_exec_sizes
= false;
200 fs_generator::~fs_generator()
204 class ip_record
: public exec_node
{
206 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
217 fs_generator::patch_discard_jumps_to_fb_writes()
219 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
222 int scale
= brw_jump_scale(p
->devinfo
);
224 /* There is a somewhat strange undocumented requirement of using
225 * HALT, according to the simulator. If some channel has HALTed to
226 * a particular UIP, then by the end of the program, every channel
227 * must have HALTed to that UIP. Furthermore, the tracking is a
228 * stack, so you can't do the final halt of a UIP after starting
229 * halting to a new UIP.
231 * Symptoms of not emitting this instruction on actual hardware
232 * included GPU hangs and sparkly rendering on the piglit discard
235 brw_inst
*last_halt
= gen6_HALT(p
);
236 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
237 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
241 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
242 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
244 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
245 /* HALT takes a half-instruction distance from the pre-incremented IP. */
246 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
249 this->discard_halt_patches
.make_empty();
254 fs_generator::fire_fb_write(fs_inst
*inst
,
255 struct brw_reg payload
,
256 struct brw_reg implied_header
,
259 uint32_t msg_control
;
261 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
263 if (devinfo
->gen
< 6) {
264 brw_push_insn_state(p
);
265 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
266 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
267 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
268 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
269 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
270 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
271 brw_pop_insn_state(p
);
274 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
275 assert(inst
->group
== 0 && inst
->exec_size
== 16);
276 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
278 } else if (prog_data
->dual_src_blend
) {
279 assert(inst
->exec_size
== 8);
281 if (inst
->group
% 16 == 0)
282 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
283 else if (inst
->group
% 16 == 8)
284 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
286 unreachable("Invalid dual-source FB write instruction group");
289 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
291 if (inst
->exec_size
== 16)
292 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
293 else if (inst
->exec_size
== 8)
294 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
296 unreachable("Invalid FB write execution size");
299 /* We assume render targets start at 0, because headerless FB write
300 * messages set "Render Target Index" to 0. Using a different binding
301 * table index would make it impossible to use headerless messages.
303 const uint32_t surf_index
= inst
->target
;
305 brw_inst
*insn
= brw_fb_WRITE(p
,
307 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
314 inst
->header_size
!= 0);
316 if (devinfo
->gen
>= 6)
317 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
319 brw_mark_surface_used(&prog_data
->base
, surf_index
);
323 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
325 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
326 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
329 const struct brw_reg implied_header
=
330 devinfo
->gen
< 6 ? payload
: brw_null_reg();
332 if (inst
->base_mrf
>= 0)
333 payload
= brw_message_reg(inst
->base_mrf
);
335 if (!runtime_check_aads_emit
) {
336 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
338 /* This can only happen in gen < 6 */
339 assert(devinfo
->gen
< 6);
341 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
343 /* Check runtime bit to detect if we have to send AA data or not */
344 brw_push_insn_state(p
);
345 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
346 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
349 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
351 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
353 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
354 brw_pop_insn_state(p
);
356 /* Don't send AA data */
357 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
359 brw_land_fwd_jump(p
, jmp
);
360 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
365 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
366 struct brw_reg payload
)
368 assert(inst
->size_written
% REG_SIZE
== 0);
369 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
370 /* We assume that render targets start at binding table index 0. */
371 const unsigned surf_index
= inst
->target
;
373 gen9_fb_READ(p
, dst
, payload
, surf_index
,
374 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
375 prog_data
->persample_dispatch
);
377 brw_mark_surface_used(&prog_data
->base
, surf_index
);
381 fs_generator::generate_mov_indirect(fs_inst
*inst
,
384 struct brw_reg indirect_byte_offset
)
386 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
387 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
388 assert(!reg
.abs
&& !reg
.negate
);
389 assert(reg
.type
== dst
.type
);
391 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
393 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
394 imm_byte_offset
+= indirect_byte_offset
.ud
;
396 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
397 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
398 brw_MOV(p
, dst
, reg
);
400 /* Prior to Broadwell, there are only 8 address registers. */
401 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
403 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
404 struct brw_reg addr
= vec8(brw_address_reg(0));
406 /* The destination stride of an instruction (in bytes) must be greater
407 * than or equal to the size of the rest of the instruction. Since the
408 * address register is of type UW, we can't use a D-type instruction.
409 * In order to get around this, re retype to UW and use a stride.
411 indirect_byte_offset
=
412 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
414 /* There are a number of reasons why we don't use the base offset here.
415 * One reason is that the field is only 9 bits which means we can only
416 * use it to access the first 16 GRFs. Also, from the Haswell PRM
417 * section "Register Region Restrictions":
419 * "The lower bits of the AddressImmediate must not overflow to
420 * change the register address. The lower 5 bits of Address
421 * Immediate when added to lower 5 bits of address register gives
422 * the sub-register offset. The upper bits of Address Immediate
423 * when added to upper bits of address register gives the register
424 * address. Any overflow from sub-register offset is dropped."
426 * Since the indirect may cause us to cross a register boundary, this
427 * makes the base offset almost useless. We could try and do something
428 * clever where we use a actual base offset if base_offset % 32 == 0 but
429 * that would mean we were generating different code depending on the
430 * base offset. Instead, for the sake of consistency, we'll just do the
431 * add ourselves. This restriction is only listed in the Haswell PRM
432 * but empirical testing indicates that it applies on all older
433 * generations and is lifted on Broadwell.
435 * In the end, while base_offset is nice to look at in the generated
436 * code, using it saves us 0 instructions and would require quite a bit
437 * of case-by-case work. It's just not worth it.
439 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
441 if (type_sz(reg
.type
) > 4 &&
442 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
443 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
444 /* IVB has an issue (which we found empirically) where it reads two
445 * address register components per channel for indirectly addressed
448 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
450 * "When source or destination datatype is 64b or operation is
451 * integer DWord multiply, indirect addressing must not be used."
453 * To work around both of these, we do two integer MOVs insead of one
454 * 64-bit MOV. Because no double value should ever cross a register
455 * boundary, it's safe to use the immediate offset in the indirect
456 * here to handle adding 4 bytes to the offset and avoid the extra
457 * ADD to the register file.
459 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
460 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
461 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
462 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
464 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
466 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
468 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
469 !inst
->get_next()->is_tail_sentinel() &&
470 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
471 /* From the Sandybridge PRM:
473 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
474 * instruction that “indexed/indirect” source AND is followed
475 * by a send, the instruction requires a “Switch”. This is to
476 * avoid race condition where send may dispatch before MRF is
479 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
486 fs_generator::generate_shuffle(fs_inst
*inst
,
491 /* Ivy bridge has some strange behavior that makes this a real pain to
492 * implement for 64-bit values so we just don't bother.
494 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
496 /* Because we're using the address register, we're limited to 8-wide
497 * execution on gen7. On gen8, we're limited to 16-wide by the address
498 * register file and 8-wide for 64-bit types. We could try and make this
499 * instruction splittable higher up in the compiler but that gets weird
500 * because it reads all of the channels regardless of execution size. It's
501 * easier just to split it here.
503 const unsigned lower_width
=
504 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
505 8 : MIN2(16, inst
->exec_size
);
507 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
508 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
509 brw_set_default_group(p
, group
);
511 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
512 idx
.file
== BRW_IMMEDIATE_VALUE
) {
513 /* Trivial, the source is already uniform or the index is a constant.
514 * We will typically not get here if the optimizer is doing its job,
515 * but asserting would be mean.
517 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
518 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
520 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
521 struct brw_reg addr
= vec8(brw_address_reg(0));
523 struct brw_reg group_idx
= suboffset(idx
, group
);
525 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
526 /* Things get grumpy if the register is too wide. */
531 assert(type_sz(group_idx
.type
) <= 4);
532 if (type_sz(group_idx
.type
) == 4) {
533 /* The destination stride of an instruction (in bytes) must be
534 * greater than or equal to the size of the rest of the
535 * instruction. Since the address register is of type UW, we
536 * can't use a D-type instruction. In order to get around this,
537 * re retype to UW and use a stride.
539 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
542 /* Take into account the component size and horizontal stride. */
543 assert(src
.vstride
== src
.hstride
+ src
.width
);
544 brw_SHL(p
, addr
, group_idx
,
545 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
548 /* Add on the register start offset */
549 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
551 if (type_sz(src
.type
) > 4 &&
552 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
553 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
554 /* IVB has an issue (which we found empirically) where it reads
555 * two address register components per channel for indirectly
556 * addressed 64-bit sources.
558 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
560 * "When source or destination datatype is 64b or operation is
561 * integer DWord multiply, indirect addressing must not be
564 * To work around both of these, we do two integer MOVs insead of
565 * one 64-bit MOV. Because no double value should ever cross a
566 * register boundary, it's safe to use the immediate offset in the
567 * indirect here to handle adding 4 bytes to the offset and avoid
568 * the extra ADD to the register file.
570 struct brw_reg gdst
= suboffset(dst
, group
);
571 struct brw_reg dst_d
= retype(spread(gdst
, 2),
572 BRW_REGISTER_TYPE_D
);
574 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
575 brw_MOV(p
, byte_offset(dst_d
, 4),
576 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
578 brw_MOV(p
, suboffset(dst
, group
),
579 retype(brw_VxH_indirect(0, 0), src
.type
));
586 fs_generator::generate_urb_read(fs_inst
*inst
,
588 struct brw_reg header
)
590 assert(inst
->size_written
% REG_SIZE
== 0);
591 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
592 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
594 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
595 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
596 brw_set_src0(p
, send
, header
);
597 brw_set_src1(p
, send
, brw_imm_ud(0u));
599 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
600 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
602 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
603 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
605 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
606 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
607 brw_inst_set_header_present(p
->devinfo
, send
, true);
608 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
612 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
616 /* WaClearTDRRegBeforeEOTForNonPS.
618 * WA: Clear tdr register before send EOT in all non-PS shader kernels
620 * mov(8) tdr0:ud 0x0:ud {NoMask}"
622 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
623 brw_push_insn_state(p
);
624 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
625 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
626 brw_pop_insn_state(p
);
629 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
631 brw_set_dest(p
, insn
, brw_null_reg());
632 brw_set_src0(p
, insn
, payload
);
633 brw_set_src1(p
, insn
, brw_imm_d(0));
635 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
636 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
638 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
639 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
640 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
642 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
643 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
644 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
646 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
647 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
648 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
649 brw_inst_set_header_present(p
->devinfo
, insn
, true);
650 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
654 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
656 struct brw_inst
*insn
;
658 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
660 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
661 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
662 brw_set_src1(p
, insn
, brw_imm_d(0));
664 /* Terminate a compute shader by sending a message to the thread spawner.
666 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
667 brw_inst_set_mlen(devinfo
, insn
, 1);
668 brw_inst_set_rlen(devinfo
, insn
, 0);
669 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
670 brw_inst_set_header_present(devinfo
, insn
, false);
672 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
673 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
675 /* Note that even though the thread has a URB resource associated with it,
676 * we set the "do not dereference URB" bit, because the URB resource is
677 * managed by the fixed-function unit, so it will free it automatically.
679 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
681 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
685 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
692 fs_generator::generate_linterp(fs_inst
*inst
,
693 struct brw_reg dst
, struct brw_reg
*src
)
697 * -----------------------------------
698 * | src1+0 | src1+1 | src1+2 | src1+3 |
699 * |-----------------------------------|
700 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
701 * -----------------------------------
703 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
705 * -----------------------------------
706 * | src1+0 | src1+1 | src1+2 | src1+3 |
707 * |-----------------------------------|
708 * |(x0, x1)|(y0, y1)| | | in SIMD8
709 * |-----------------------------------|
710 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
711 * -----------------------------------
713 * See also: emit_interpolation_setup_gen4().
715 struct brw_reg delta_x
= src
[0];
716 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
717 struct brw_reg interp
= src
[1];
720 if (devinfo
->gen
>= 11) {
721 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF
);
722 struct brw_reg dwP
= suboffset(interp
, 0);
723 struct brw_reg dwQ
= suboffset(interp
, 1);
724 struct brw_reg dwR
= suboffset(interp
, 3);
726 brw_push_insn_state(p
);
727 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
729 if (inst
->exec_size
== 8) {
730 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
731 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_y
, 0), dwQ
);
733 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
735 /* brw_set_default_saturate() is called before emitting instructions,
736 * so the saturate bit is set in each instruction, so we need to unset
737 * it on the first instruction of each pair.
739 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
741 brw_set_default_group(p
, inst
->group
);
742 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
743 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_x
, 1), dwQ
);
745 brw_set_default_group(p
, inst
->group
+ 8);
746 i
[2] = brw_MAD(p
, acc
, dwR
, offset(delta_y
, 0), dwP
);
747 i
[3] = brw_MAD(p
, offset(dst
, 1), acc
, offset(delta_y
, 1), dwQ
);
749 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
750 brw_inst_set_cond_modifier(p
->devinfo
, i
[3], inst
->conditional_mod
);
752 /* brw_set_default_saturate() is called before emitting instructions,
753 * so the saturate bit is set in each instruction, so we need to unset
754 * it on the first instruction of each pair.
756 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
757 brw_inst_set_saturate(p
->devinfo
, i
[2], false);
760 brw_pop_insn_state(p
);
763 } else if (devinfo
->has_pln
) {
764 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
766 * "[DevSNB]:<src1> must be even register aligned.
768 * This restriction is lifted on Ivy Bridge.
770 assert(devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0);
771 brw_PLN(p
, dst
, interp
, delta_x
);
775 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
776 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
778 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
780 /* brw_set_default_saturate() is called before emitting instructions, so
781 * the saturate bit is set in each instruction, so we need to unset it on
782 * the first instruction.
784 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
791 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
794 struct brw_reg surf_index
)
796 assert(devinfo
->gen
>= 7);
797 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
802 switch (inst
->exec_size
) {
804 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
807 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
810 unreachable("Invalid width for texture instruction");
813 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
819 retype(dst
, BRW_REGISTER_TYPE_UW
),
824 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
825 rlen
, /* response length */
827 inst
->header_size
> 0,
829 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
831 brw_mark_surface_used(prog_data
, surf_index
.ud
);
835 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
836 struct brw_reg surface_index
,
837 struct brw_reg sampler_index
)
839 assert(inst
->size_written
% REG_SIZE
== 0);
842 uint32_t return_format
;
843 bool is_combined_send
= inst
->eot
;
846 case BRW_REGISTER_TYPE_D
:
847 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
849 case BRW_REGISTER_TYPE_UD
:
850 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
853 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
857 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
858 * is set as part of the message descriptor. On gen4, the PRM seems to
859 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
860 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
861 * gone from the message descriptor entirely and you just get UINT32 all
862 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
863 * just stomp it to UINT32 all the time.
865 if (inst
->opcode
== SHADER_OPCODE_TXS
)
866 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
868 switch (inst
->exec_size
) {
870 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
873 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
876 unreachable("Invalid width for texture instruction");
879 if (devinfo
->gen
>= 5) {
880 switch (inst
->opcode
) {
881 case SHADER_OPCODE_TEX
:
882 if (inst
->shadow_compare
) {
883 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
885 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
889 if (inst
->shadow_compare
) {
890 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
892 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
895 case SHADER_OPCODE_TXL
:
896 if (inst
->shadow_compare
) {
897 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
899 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
902 case SHADER_OPCODE_TXL_LZ
:
903 assert(devinfo
->gen
>= 9);
904 if (inst
->shadow_compare
) {
905 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
907 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
910 case SHADER_OPCODE_TXS
:
911 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
913 case SHADER_OPCODE_TXD
:
914 if (inst
->shadow_compare
) {
915 /* Gen7.5+. Otherwise, lowered in NIR */
916 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
917 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
919 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
922 case SHADER_OPCODE_TXF
:
923 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
925 case SHADER_OPCODE_TXF_LZ
:
926 assert(devinfo
->gen
>= 9);
927 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
929 case SHADER_OPCODE_TXF_CMS_W
:
930 assert(devinfo
->gen
>= 9);
931 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
933 case SHADER_OPCODE_TXF_CMS
:
934 if (devinfo
->gen
>= 7)
935 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
937 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
939 case SHADER_OPCODE_TXF_UMS
:
940 assert(devinfo
->gen
>= 7);
941 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
943 case SHADER_OPCODE_TXF_MCS
:
944 assert(devinfo
->gen
>= 7);
945 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
947 case SHADER_OPCODE_LOD
:
948 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
950 case SHADER_OPCODE_TG4
:
951 if (inst
->shadow_compare
) {
952 assert(devinfo
->gen
>= 7);
953 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
955 assert(devinfo
->gen
>= 6);
956 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
959 case SHADER_OPCODE_TG4_OFFSET
:
960 assert(devinfo
->gen
>= 7);
961 if (inst
->shadow_compare
) {
962 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
964 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
967 case SHADER_OPCODE_SAMPLEINFO
:
968 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
971 unreachable("not reached");
974 switch (inst
->opcode
) {
975 case SHADER_OPCODE_TEX
:
976 /* Note that G45 and older determines shadow compare and dispatch width
977 * from message length for most messages.
979 if (inst
->exec_size
== 8) {
980 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
981 if (inst
->shadow_compare
) {
982 assert(inst
->mlen
== 6);
984 assert(inst
->mlen
<= 4);
987 if (inst
->shadow_compare
) {
988 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
989 assert(inst
->mlen
== 9);
991 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
992 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
997 if (inst
->shadow_compare
) {
998 assert(inst
->exec_size
== 8);
999 assert(inst
->mlen
== 6);
1000 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1002 assert(inst
->mlen
== 9);
1003 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1004 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1007 case SHADER_OPCODE_TXL
:
1008 if (inst
->shadow_compare
) {
1009 assert(inst
->exec_size
== 8);
1010 assert(inst
->mlen
== 6);
1011 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1013 assert(inst
->mlen
== 9);
1014 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1015 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1018 case SHADER_OPCODE_TXD
:
1019 /* There is no sample_d_c message; comparisons are done manually */
1020 assert(inst
->exec_size
== 8);
1021 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1022 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1024 case SHADER_OPCODE_TXF
:
1025 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1026 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1027 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1029 case SHADER_OPCODE_TXS
:
1030 assert(inst
->mlen
== 3);
1031 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1032 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1035 unreachable("not reached");
1038 assert(msg_type
!= -1);
1040 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1044 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
1045 src
.file
== BRW_GENERAL_REGISTER_FILE
);
1047 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1049 /* Load the message header if present. If there's a texture offset,
1050 * we need to set it up explicitly and load the offset bitfield.
1051 * Otherwise, we can use an implied move from g0 to the first message reg.
1053 if (inst
->header_size
!= 0 && devinfo
->gen
< 7) {
1054 if (devinfo
->gen
< 6 && !inst
->offset
) {
1055 /* Set up an implied move from g0 to the MRF. */
1056 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1058 assert(inst
->base_mrf
!= -1);
1059 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1061 brw_push_insn_state(p
);
1062 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1063 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1064 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1065 /* Explicitly set up the message header by copying g0 to the MRF. */
1066 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1068 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1070 /* Set the offset bits in DWord 2. */
1071 brw_MOV(p
, get_element_ud(header_reg
, 2),
1072 brw_imm_ud(inst
->offset
));
1075 brw_pop_insn_state(p
);
1079 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
1080 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
1081 ? prog_data
->binding_table
.gather_texture_start
1082 : prog_data
->binding_table
.texture_start
;
1084 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
1085 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
1086 uint32_t surface
= surface_index
.ud
;
1087 uint32_t sampler
= sampler_index
.ud
;
1090 retype(dst
, BRW_REGISTER_TYPE_UW
),
1093 surface
+ base_binding_table_index
,
1096 inst
->size_written
/ REG_SIZE
,
1098 inst
->header_size
!= 0,
1102 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1104 /* Non-const sampler index */
1106 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1107 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1108 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1110 brw_push_insn_state(p
);
1111 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1112 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1113 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1115 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
1116 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1118 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
1119 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
1121 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1122 brw_OR(p
, addr
, addr
, surface_reg
);
1125 if (base_binding_table_index
)
1126 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1127 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1129 brw_pop_insn_state(p
);
1131 /* dst = send(offset, a0.0 | <descriptor>) */
1132 brw_inst
*insn
= brw_send_indirect_message(
1133 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1134 brw_set_sampler_message(p
, insn
,
1138 inst
->size_written
/ REG_SIZE
,
1139 inst
->mlen
/* mlen */,
1140 inst
->header_size
!= 0 /* header */,
1144 /* visitor knows more than we do about the surface limit required,
1145 * so has already done marking.
1149 if (is_combined_send
) {
1150 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1151 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1156 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1159 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1161 * Ideally, we want to produce:
1164 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1165 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1166 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1167 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1168 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1169 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1170 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1171 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1173 * and add another set of two more subspans if in 16-pixel dispatch mode.
1175 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1176 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1177 * pair. But the ideal approximation may impose a huge performance cost on
1178 * sample_d. On at least Haswell, sample_d instruction does some
1179 * optimizations if the same LOD is used for all pixels in the subspan.
1181 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1182 * appropriate swizzling.
1185 fs_generator::generate_ddx(const fs_inst
*inst
,
1186 struct brw_reg dst
, struct brw_reg src
)
1188 unsigned vstride
, width
;
1190 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1191 /* produce accurate derivatives */
1192 vstride
= BRW_VERTICAL_STRIDE_2
;
1193 width
= BRW_WIDTH_2
;
1195 /* replicate the derivative at the top-left pixel to other pixels */
1196 vstride
= BRW_VERTICAL_STRIDE_4
;
1197 width
= BRW_WIDTH_4
;
1200 struct brw_reg src0
= src
;
1201 struct brw_reg src1
= src
;
1203 src0
.subnr
= sizeof(float);
1204 src0
.vstride
= vstride
;
1206 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1207 src1
.vstride
= vstride
;
1209 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1211 brw_ADD(p
, dst
, src0
, negate(src1
));
1214 /* The negate_value boolean is used to negate the derivative computation for
1215 * FBOs, since they place the origin at the upper left instead of the lower
1219 fs_generator::generate_ddy(const fs_inst
*inst
,
1220 struct brw_reg dst
, struct brw_reg src
)
1222 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1223 /* produce accurate derivatives */
1224 if (devinfo
->gen
>= 11) {
1225 src
= stride(src
, 0, 2, 1);
1226 struct brw_reg src_0
= byte_offset(src
, 0 * sizeof(float));
1227 struct brw_reg src_2
= byte_offset(src
, 2 * sizeof(float));
1228 struct brw_reg src_4
= byte_offset(src
, 4 * sizeof(float));
1229 struct brw_reg src_6
= byte_offset(src
, 6 * sizeof(float));
1230 struct brw_reg src_8
= byte_offset(src
, 8 * sizeof(float));
1231 struct brw_reg src_10
= byte_offset(src
, 10 * sizeof(float));
1232 struct brw_reg src_12
= byte_offset(src
, 12 * sizeof(float));
1233 struct brw_reg src_14
= byte_offset(src
, 14 * sizeof(float));
1235 struct brw_reg dst_0
= byte_offset(dst
, 0 * sizeof(float));
1236 struct brw_reg dst_4
= byte_offset(dst
, 4 * sizeof(float));
1237 struct brw_reg dst_8
= byte_offset(dst
, 8 * sizeof(float));
1238 struct brw_reg dst_12
= byte_offset(dst
, 12 * sizeof(float));
1240 brw_push_insn_state(p
);
1241 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1243 brw_ADD(p
, dst_0
, negate(src_0
), src_2
);
1244 brw_ADD(p
, dst_4
, negate(src_4
), src_6
);
1246 if (inst
->exec_size
== 16) {
1247 brw_ADD(p
, dst_8
, negate(src_8
), src_10
);
1248 brw_ADD(p
, dst_12
, negate(src_12
), src_14
);
1251 brw_pop_insn_state(p
);
1253 struct brw_reg src0
= stride(src
, 4, 4, 1);
1254 struct brw_reg src1
= stride(src
, 4, 4, 1);
1255 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1256 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1258 brw_push_insn_state(p
);
1259 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1260 brw_ADD(p
, dst
, negate(src0
), src1
);
1261 brw_pop_insn_state(p
);
1264 /* replicate the derivative at the top-left pixel to other pixels */
1265 struct brw_reg src0
= stride(src
, 4, 4, 0);
1266 struct brw_reg src1
= stride(src
, 4, 4, 0);
1267 src0
.subnr
= 0 * sizeof(float);
1268 src1
.subnr
= 2 * sizeof(float);
1270 brw_ADD(p
, dst
, negate(src0
), src1
);
1275 fs_generator::generate_discard_jump(fs_inst
*)
1277 assert(devinfo
->gen
>= 6);
1279 /* This HALT will be patched up at FB write time to point UIP at the end of
1280 * the program, and at brw_uip_jip() JIP will be set to the end of the
1281 * current block (or the program).
1283 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1288 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1290 /* The 32-wide messages only respect the first 16-wide half of the channel
1291 * enable signals which are replicated identically for the second group of
1292 * 16 channels, so we cannot use them unless the write is marked
1293 * force_writemask_all.
1295 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1296 MIN2(16, inst
->exec_size
);
1297 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1298 assert(inst
->mlen
!= 0);
1300 brw_push_insn_state(p
);
1301 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1302 brw_set_default_compression(p
, lower_size
> 8);
1304 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1305 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1307 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1308 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1310 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1312 inst
->offset
+ block_size
* REG_SIZE
* i
);
1315 brw_pop_insn_state(p
);
1319 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1321 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1322 assert(inst
->mlen
!= 0);
1324 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1325 inst
->exec_size
/ 8, inst
->offset
);
1329 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1331 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1333 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1337 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1339 struct brw_reg index
,
1340 struct brw_reg offset
)
1342 assert(type_sz(dst
.type
) == 4);
1343 assert(inst
->mlen
!= 0);
1345 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1346 index
.type
== BRW_REGISTER_TYPE_UD
);
1347 uint32_t surf_index
= index
.ud
;
1349 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1350 offset
.type
== BRW_REGISTER_TYPE_UD
);
1351 uint32_t read_offset
= offset
.ud
;
1353 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1354 read_offset
, surf_index
);
1358 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1360 struct brw_reg index
,
1361 struct brw_reg payload
)
1363 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1364 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1365 assert(type_sz(dst
.type
) == 4);
1367 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1368 const uint32_t surf_index
= index
.ud
;
1370 brw_push_insn_state(p
);
1371 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1372 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1373 brw_pop_insn_state(p
);
1375 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1376 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1377 brw_set_dp_read_message(p
, send
, surf_index
,
1378 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1379 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1380 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1383 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1386 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1388 brw_push_insn_state(p
);
1389 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1391 /* a0.0 = surf_index & 0xff */
1392 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1393 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1394 brw_set_dest(p
, insn_and
, addr
);
1395 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1396 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1398 /* dst = send(payload, a0.0 | <descriptor>) */
1399 brw_inst
*insn
= brw_send_indirect_message(
1400 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1401 retype(dst
, BRW_REGISTER_TYPE_UD
),
1402 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
);
1403 brw_set_dp_read_message(p
, insn
, 0 /* surface */,
1404 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1405 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1406 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1409 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1411 brw_pop_insn_state(p
);
1416 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1418 struct brw_reg index
)
1420 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1421 assert(inst
->header_size
!= 0);
1424 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1425 index
.type
== BRW_REGISTER_TYPE_UD
);
1426 uint32_t surf_index
= index
.ud
;
1428 uint32_t simd_mode
, rlen
, msg_type
;
1429 if (inst
->exec_size
== 16) {
1430 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1433 assert(inst
->exec_size
== 8);
1434 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1438 if (devinfo
->gen
>= 5)
1439 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1441 /* We always use the SIMD16 message so that we only have to load U, and
1444 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1445 assert(inst
->mlen
== 3);
1446 assert(inst
->size_written
== 8 * REG_SIZE
);
1448 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1451 struct brw_reg header
= brw_vec8_grf(0, 0);
1452 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1454 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1455 brw_inst_set_compression(devinfo
, send
, false);
1456 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1457 brw_set_src0(p
, send
, header
);
1458 if (devinfo
->gen
< 6)
1459 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1461 /* Our surface is set up as floats, regardless of what actual data is
1464 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1465 brw_set_sampler_message(p
, send
,
1467 0, /* sampler (unused) */
1471 inst
->header_size
!= 0,
1477 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1479 struct brw_reg index
,
1480 struct brw_reg offset
)
1482 assert(devinfo
->gen
>= 7);
1483 /* Varying-offset pull constant loads are treated as a normal expression on
1484 * gen7, so the fact that it's a send message is hidden at the IR level.
1486 assert(inst
->header_size
== 0);
1487 assert(!inst
->mlen
);
1488 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1490 uint32_t simd_mode
, rlen
, mlen
;
1491 if (inst
->exec_size
== 16) {
1494 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1496 assert(inst
->exec_size
== 8);
1499 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1502 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1504 uint32_t surf_index
= index
.ud
;
1506 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1507 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1508 brw_set_src0(p
, send
, offset
);
1509 brw_set_sampler_message(p
, send
,
1511 0, /* LD message ignores sampler unit */
1512 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1515 false, /* no header */
1521 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1523 brw_push_insn_state(p
);
1524 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1526 /* a0.0 = surf_index & 0xff */
1527 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1528 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1529 brw_set_dest(p
, insn_and
, addr
);
1530 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1531 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1533 brw_pop_insn_state(p
);
1535 /* dst = send(offset, a0.0 | <descriptor>) */
1536 brw_inst
*insn
= brw_send_indirect_message(
1537 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1539 brw_set_sampler_message(p
, insn
,
1542 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1552 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1553 * into the flags register (f0.0).
1555 * Used only on Gen6 and above.
1558 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1560 struct brw_reg flags
= brw_flag_subreg(inst
->flag_subreg
);
1561 struct brw_reg dispatch_mask
;
1563 if (devinfo
->gen
>= 6)
1564 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1566 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1568 brw_push_insn_state(p
);
1569 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1570 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1571 brw_MOV(p
, flags
, dispatch_mask
);
1572 brw_pop_insn_state(p
);
1576 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1579 struct brw_reg msg_data
,
1582 assert(inst
->size_written
% REG_SIZE
== 0);
1583 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1585 brw_pixel_interpolator_query(p
,
1586 retype(dst
, BRW_REGISTER_TYPE_UW
),
1588 inst
->pi_noperspective
,
1592 inst
->size_written
/ REG_SIZE
);
1595 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1596 * the ADD instruction.
1599 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1601 struct brw_reg src0
,
1602 struct brw_reg src1
)
1604 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1605 dst
.type
== BRW_REGISTER_TYPE_UD
);
1606 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1607 src0
.type
== BRW_REGISTER_TYPE_UD
);
1609 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1610 const unsigned lower_size
= MIN2(inst
->exec_size
,
1611 devinfo
->gen
>= 8 ? 16 : 8);
1613 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1614 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1615 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1616 (i
* lower_size
/ (1 << src0
.width
))) *
1617 type_sz(src0
.type
) / REG_SIZE
),
1618 suboffset(reg
, i
* lower_size
/ 4));
1619 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1620 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1621 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1626 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1631 assert(devinfo
->gen
>= 7);
1632 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1633 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1634 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1636 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1638 * Because this instruction does not have a 16-bit floating-point type,
1639 * the destination data type must be Word (W).
1641 * The destination must be DWord-aligned and specify a horizontal stride
1642 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1643 * each destination channel and the upper word is not modified.
1645 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1647 /* Give each 32-bit channel of dst the form below, where "." means
1651 brw_F32TO16(p
, dst_w
, y
);
1656 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1658 /* And, finally the form of packHalf2x16's output:
1661 brw_F32TO16(p
, dst_w
, x
);
1665 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1669 assert(devinfo
->gen
>= 7);
1670 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1671 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1673 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1675 * Because this instruction does not have a 16-bit floating-point type,
1676 * the source data type must be Word (W). The destination type must be
1679 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1681 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1682 * For the Y case, we wish to access only the upper word; therefore
1683 * a 16-bit subregister offset is needed.
1685 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1686 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1687 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1690 brw_F16TO32(p
, dst
, src_w
);
1694 fs_generator::generate_shader_time_add(fs_inst
*,
1695 struct brw_reg payload
,
1696 struct brw_reg offset
,
1697 struct brw_reg value
)
1699 assert(devinfo
->gen
>= 7);
1700 brw_push_insn_state(p
);
1701 brw_set_default_mask_control(p
, true);
1703 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1704 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1706 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1709 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1710 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1711 value
.width
= BRW_WIDTH_1
;
1712 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1713 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1715 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1718 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1719 * case, and we don't really care about squeezing every bit of performance
1720 * out of this path, so we just emit the MOVs from here.
1722 brw_MOV(p
, payload_offset
, offset
);
1723 brw_MOV(p
, payload_value
, value
);
1724 brw_shader_time_add(p
, payload
,
1725 prog_data
->binding_table
.shader_time_start
);
1726 brw_pop_insn_state(p
);
1728 brw_mark_surface_used(prog_data
,
1729 prog_data
->binding_table
.shader_time_start
);
1733 fs_generator::enable_debug(const char *shader_name
)
1736 this->shader_name
= shader_name
;
1740 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1742 /* align to 64 byte boundary. */
1743 while (p
->next_insn_offset
% 64)
1746 this->dispatch_width
= dispatch_width
;
1748 int start_offset
= p
->next_insn_offset
;
1749 int spill_count
= 0, fill_count
= 0;
1752 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1754 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1755 struct brw_reg src
[3], dst
;
1756 unsigned int last_insn_offset
= p
->next_insn_offset
;
1757 bool multiple_instructions_emitted
= false;
1759 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1760 * "Register Region Restrictions" section: for BDW, SKL:
1762 * "A POW/FDIV operation must not be followed by an instruction
1763 * that requires two destination registers."
1765 * The documentation is often lacking annotations for Atom parts,
1766 * and empirically this affects CHV as well.
1768 if (devinfo
->gen
>= 8 &&
1769 devinfo
->gen
<= 9 &&
1771 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1772 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1773 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1775 last_insn_offset
= p
->next_insn_offset
;
1778 if (unlikely(debug_flag
))
1779 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1781 /* If the instruction writes to more than one register, it needs to be
1782 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1783 * hardware figures out by itself what the right compression mode is,
1784 * but we still need to know whether the instruction is compressed to
1785 * set up the source register regions appropriately.
1787 * XXX - This is wrong for instructions that write a single register but
1788 * read more than one which should strictly speaking be treated as
1789 * compressed. For instructions that don't write any registers it
1790 * relies on the destination being a null register of the correct
1791 * type and regioning so the instruction is considered compressed
1792 * or not accordingly.
1794 const bool compressed
=
1795 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1796 brw_set_default_compression(p
, compressed
);
1797 brw_set_default_group(p
, inst
->group
);
1799 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1800 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1801 &inst
->src
[i
], compressed
);
1802 /* The accumulator result appears to get used for the
1803 * conditional modifier generation. When negating a UD
1804 * value, there is a 33rd bit generated for the sign in the
1805 * accumulator value, so now you can't check, for example,
1806 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1808 assert(!inst
->conditional_mod
||
1809 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1810 !inst
->src
[i
].negate
);
1812 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1813 &inst
->dst
, compressed
);
1815 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1816 brw_set_default_predicate_control(p
, inst
->predicate
);
1817 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1818 brw_set_default_flag_reg(p
, inst
->flag_subreg
/ 2, inst
->flag_subreg
% 2);
1819 brw_set_default_saturate(p
, inst
->saturate
);
1820 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1821 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1823 unsigned exec_size
= inst
->exec_size
;
1824 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1825 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1829 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1831 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1832 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1833 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1834 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1836 switch (inst
->opcode
) {
1837 case BRW_OPCODE_MOV
:
1838 brw_MOV(p
, dst
, src
[0]);
1840 case BRW_OPCODE_ADD
:
1841 brw_ADD(p
, dst
, src
[0], src
[1]);
1843 case BRW_OPCODE_MUL
:
1844 brw_MUL(p
, dst
, src
[0], src
[1]);
1846 case BRW_OPCODE_AVG
:
1847 brw_AVG(p
, dst
, src
[0], src
[1]);
1849 case BRW_OPCODE_MACH
:
1850 brw_MACH(p
, dst
, src
[0], src
[1]);
1853 case BRW_OPCODE_LINE
:
1854 brw_LINE(p
, dst
, src
[0], src
[1]);
1857 case BRW_OPCODE_MAD
:
1858 assert(devinfo
->gen
>= 6);
1859 if (devinfo
->gen
< 10)
1860 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1861 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1864 case BRW_OPCODE_LRP
:
1865 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1866 if (devinfo
->gen
< 10)
1867 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1868 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1871 case BRW_OPCODE_FRC
:
1872 brw_FRC(p
, dst
, src
[0]);
1874 case BRW_OPCODE_RNDD
:
1875 brw_RNDD(p
, dst
, src
[0]);
1877 case BRW_OPCODE_RNDE
:
1878 brw_RNDE(p
, dst
, src
[0]);
1880 case BRW_OPCODE_RNDZ
:
1881 brw_RNDZ(p
, dst
, src
[0]);
1884 case BRW_OPCODE_AND
:
1885 brw_AND(p
, dst
, src
[0], src
[1]);
1888 brw_OR(p
, dst
, src
[0], src
[1]);
1890 case BRW_OPCODE_XOR
:
1891 brw_XOR(p
, dst
, src
[0], src
[1]);
1893 case BRW_OPCODE_NOT
:
1894 brw_NOT(p
, dst
, src
[0]);
1896 case BRW_OPCODE_ASR
:
1897 brw_ASR(p
, dst
, src
[0], src
[1]);
1899 case BRW_OPCODE_SHR
:
1900 brw_SHR(p
, dst
, src
[0], src
[1]);
1902 case BRW_OPCODE_SHL
:
1903 brw_SHL(p
, dst
, src
[0], src
[1]);
1905 case BRW_OPCODE_F32TO16
:
1906 assert(devinfo
->gen
>= 7);
1907 brw_F32TO16(p
, dst
, src
[0]);
1909 case BRW_OPCODE_F16TO32
:
1910 assert(devinfo
->gen
>= 7);
1911 brw_F16TO32(p
, dst
, src
[0]);
1913 case BRW_OPCODE_CMP
:
1914 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1915 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1916 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1917 * implemented in the compiler is not sufficient. Overriding the
1918 * type when the destination is the null register is necessary but
1919 * not sufficient by itself.
1921 assert(dst
.nr
== BRW_ARF_NULL
);
1922 dst
.type
= BRW_REGISTER_TYPE_D
;
1924 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1926 case BRW_OPCODE_SEL
:
1927 brw_SEL(p
, dst
, src
[0], src
[1]);
1929 case BRW_OPCODE_CSEL
:
1930 assert(devinfo
->gen
>= 8);
1931 if (devinfo
->gen
< 10)
1932 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1933 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1935 case BRW_OPCODE_BFREV
:
1936 assert(devinfo
->gen
>= 7);
1937 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1938 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1940 case BRW_OPCODE_FBH
:
1941 assert(devinfo
->gen
>= 7);
1942 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1944 case BRW_OPCODE_FBL
:
1945 assert(devinfo
->gen
>= 7);
1946 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1947 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1949 case BRW_OPCODE_LZD
:
1950 brw_LZD(p
, dst
, src
[0]);
1952 case BRW_OPCODE_CBIT
:
1953 assert(devinfo
->gen
>= 7);
1954 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1955 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1957 case BRW_OPCODE_ADDC
:
1958 assert(devinfo
->gen
>= 7);
1959 brw_ADDC(p
, dst
, src
[0], src
[1]);
1961 case BRW_OPCODE_SUBB
:
1962 assert(devinfo
->gen
>= 7);
1963 brw_SUBB(p
, dst
, src
[0], src
[1]);
1965 case BRW_OPCODE_MAC
:
1966 brw_MAC(p
, dst
, src
[0], src
[1]);
1969 case BRW_OPCODE_BFE
:
1970 assert(devinfo
->gen
>= 7);
1971 if (devinfo
->gen
< 10)
1972 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1973 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1976 case BRW_OPCODE_BFI1
:
1977 assert(devinfo
->gen
>= 7);
1978 brw_BFI1(p
, dst
, src
[0], src
[1]);
1980 case BRW_OPCODE_BFI2
:
1981 assert(devinfo
->gen
>= 7);
1982 if (devinfo
->gen
< 10)
1983 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1984 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1988 if (inst
->src
[0].file
!= BAD_FILE
) {
1989 /* The instruction has an embedded compare (only allowed on gen6) */
1990 assert(devinfo
->gen
== 6);
1991 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1993 brw_IF(p
, brw_get_default_exec_size(p
));
1997 case BRW_OPCODE_ELSE
:
2000 case BRW_OPCODE_ENDIF
:
2005 brw_DO(p
, brw_get_default_exec_size(p
));
2008 case BRW_OPCODE_BREAK
:
2011 case BRW_OPCODE_CONTINUE
:
2015 case BRW_OPCODE_WHILE
:
2020 case SHADER_OPCODE_RCP
:
2021 case SHADER_OPCODE_RSQ
:
2022 case SHADER_OPCODE_SQRT
:
2023 case SHADER_OPCODE_EXP2
:
2024 case SHADER_OPCODE_LOG2
:
2025 case SHADER_OPCODE_SIN
:
2026 case SHADER_OPCODE_COS
:
2027 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2028 if (devinfo
->gen
>= 6) {
2029 assert(inst
->mlen
== 0);
2030 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2031 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2032 src
[0], brw_null_reg());
2034 assert(inst
->mlen
>= 1);
2035 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2037 brw_math_function(inst
->opcode
),
2038 inst
->base_mrf
, src
[0],
2039 BRW_MATH_PRECISION_FULL
);
2042 case SHADER_OPCODE_INT_QUOTIENT
:
2043 case SHADER_OPCODE_INT_REMAINDER
:
2044 case SHADER_OPCODE_POW
:
2045 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2046 if (devinfo
->gen
>= 6) {
2047 assert(inst
->mlen
== 0);
2048 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2049 inst
->exec_size
== 8);
2050 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2052 assert(inst
->mlen
>= 1);
2053 assert(inst
->exec_size
== 8);
2054 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2055 inst
->base_mrf
, src
[0],
2056 BRW_MATH_PRECISION_FULL
);
2059 case FS_OPCODE_LINTERP
:
2060 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2062 case FS_OPCODE_PIXEL_X
:
2063 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2064 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2065 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2067 case FS_OPCODE_PIXEL_Y
:
2068 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2069 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2070 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2072 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2073 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2075 case SHADER_OPCODE_TEX
:
2077 case SHADER_OPCODE_TXD
:
2078 case SHADER_OPCODE_TXF
:
2079 case SHADER_OPCODE_TXF_LZ
:
2080 case SHADER_OPCODE_TXF_CMS
:
2081 case SHADER_OPCODE_TXF_CMS_W
:
2082 case SHADER_OPCODE_TXF_UMS
:
2083 case SHADER_OPCODE_TXF_MCS
:
2084 case SHADER_OPCODE_TXL
:
2085 case SHADER_OPCODE_TXL_LZ
:
2086 case SHADER_OPCODE_TXS
:
2087 case SHADER_OPCODE_LOD
:
2088 case SHADER_OPCODE_TG4
:
2089 case SHADER_OPCODE_TG4_OFFSET
:
2090 case SHADER_OPCODE_SAMPLEINFO
:
2091 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2093 case FS_OPCODE_DDX_COARSE
:
2094 case FS_OPCODE_DDX_FINE
:
2095 generate_ddx(inst
, dst
, src
[0]);
2097 case FS_OPCODE_DDY_COARSE
:
2098 case FS_OPCODE_DDY_FINE
:
2099 generate_ddy(inst
, dst
, src
[0]);
2102 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2103 generate_scratch_write(inst
, src
[0]);
2107 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2108 generate_scratch_read(inst
, dst
);
2112 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2113 generate_scratch_read_gen7(inst
, dst
);
2117 case SHADER_OPCODE_MOV_INDIRECT
:
2118 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2121 case SHADER_OPCODE_URB_READ_SIMD8
:
2122 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2123 generate_urb_read(inst
, dst
, src
[0]);
2126 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2127 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2128 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2129 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2130 generate_urb_write(inst
, src
[0]);
2133 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2134 assert(inst
->force_writemask_all
);
2135 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2138 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2139 assert(inst
->force_writemask_all
);
2140 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2143 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2144 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2147 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2148 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2151 case FS_OPCODE_REP_FB_WRITE
:
2152 case FS_OPCODE_FB_WRITE
:
2153 generate_fb_write(inst
, src
[0]);
2156 case FS_OPCODE_FB_READ
:
2157 generate_fb_read(inst
, dst
, src
[0]);
2160 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2161 generate_mov_dispatch_to_flags(inst
);
2164 case FS_OPCODE_DISCARD_JUMP
:
2165 generate_discard_jump(inst
);
2168 case SHADER_OPCODE_SHADER_TIME_ADD
:
2169 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2172 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2173 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2174 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2175 inst
->mlen
, !inst
->dst
.is_null(),
2179 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2180 assert(!inst
->header_size
);
2181 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2182 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2183 inst
->mlen
, src
[2].ud
);
2186 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2187 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2188 brw_untyped_surface_write(p
, src
[0], src
[1],
2189 inst
->mlen
, src
[2].ud
,
2193 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
2194 assert(!inst
->header_size
);
2195 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2196 brw_byte_scattered_read(p
, dst
, src
[0], src
[1],
2197 inst
->mlen
, src
[2].ud
);
2200 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
2201 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2202 brw_byte_scattered_write(p
, src
[0], src
[1],
2203 inst
->mlen
, src
[2].ud
,
2207 case SHADER_OPCODE_TYPED_ATOMIC
:
2208 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2209 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2210 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null(),
2214 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2215 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2216 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2217 inst
->mlen
, src
[2].ud
,
2221 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2222 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2223 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
,
2227 case SHADER_OPCODE_MEMORY_FENCE
:
2228 brw_memory_fence(p
, dst
, BRW_OPCODE_SEND
);
2231 case SHADER_OPCODE_INTERLOCK
:
2232 /* The interlock is basically a memory fence issued via sendc */
2233 brw_memory_fence(p
, dst
, BRW_OPCODE_SENDC
);
2236 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2237 const struct brw_reg mask
=
2238 brw_stage_has_packed_dispatch(devinfo
, stage
,
2239 prog_data
) ? brw_imm_ud(~0u) :
2240 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2242 brw_find_live_channel(p
, dst
, mask
);
2246 case SHADER_OPCODE_BROADCAST
:
2247 assert(inst
->force_writemask_all
);
2248 brw_broadcast(p
, dst
, src
[0], src
[1]);
2251 case SHADER_OPCODE_SHUFFLE
:
2252 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2255 case SHADER_OPCODE_SEL_EXEC
:
2256 assert(inst
->force_writemask_all
);
2257 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2258 brw_MOV(p
, dst
, src
[1]);
2259 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2260 brw_MOV(p
, dst
, src
[0]);
2263 case SHADER_OPCODE_QUAD_SWIZZLE
:
2264 /* This only works on 8-wide 32-bit values */
2265 assert(inst
->exec_size
== 8);
2266 assert(type_sz(src
[0].type
) == 4);
2267 assert(inst
->force_writemask_all
);
2268 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2269 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2271 if (src
[0].file
== BRW_IMMEDIATE_VALUE
||
2272 (src
[0].vstride
== 0 && src
[0].hstride
== 0)) {
2273 /* The value is uniform across all channels */
2274 brw_MOV(p
, dst
, src
[0]);
2276 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2277 struct brw_reg swiz_src
= stride(src
[0], 4, 4, 1);
2278 swiz_src
.swizzle
= inst
->src
[1].ud
;
2279 brw_MOV(p
, dst
, swiz_src
);
2283 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2284 assert(src
[0].type
== dst
.type
);
2285 assert(!src
[0].negate
&& !src
[0].abs
);
2286 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2287 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2288 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2289 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2290 const unsigned component
= src
[1].ud
;
2291 const unsigned cluster_size
= src
[2].ud
;
2292 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2293 cluster_size
, cluster_size
, 0);
2294 if (type_sz(src
[0].type
) > 4 &&
2295 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2296 /* IVB has an issue (which we found empirically) where it reads
2297 * two address register components per channel for indirectly
2298 * addressed 64-bit sources.
2300 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2302 * "When source or destination datatype is 64b or operation is
2303 * integer DWord multiply, indirect addressing must not be
2306 * To work around both of these, we do two integer MOVs insead of
2307 * one 64-bit MOV. Because no double value should ever cross a
2308 * register boundary, it's safe to use the immediate offset in the
2309 * indirect here to handle adding 4 bytes to the offset and avoid
2310 * the extra ADD to the register file.
2312 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2313 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2314 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2315 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2317 brw_MOV(p
, dst
, strided
);
2322 case FS_OPCODE_SET_SAMPLE_ID
:
2323 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2326 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2327 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2330 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2331 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2332 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2335 case FS_OPCODE_PLACEHOLDER_HALT
:
2336 /* This is the place where the final HALT needs to be inserted if
2337 * we've emitted any discards. If not, this will emit no code.
2339 if (!patch_discard_jumps_to_fb_writes()) {
2340 if (unlikely(debug_flag
)) {
2341 disasm_info
->use_tail
= true;
2346 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2347 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2348 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2351 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2352 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2353 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2356 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2357 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2358 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2361 case CS_OPCODE_CS_TERMINATE
:
2362 generate_cs_terminate(inst
, src
[0]);
2365 case SHADER_OPCODE_BARRIER
:
2366 generate_barrier(inst
, src
[0]);
2369 case BRW_OPCODE_DIM
:
2370 assert(devinfo
->is_haswell
);
2371 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2372 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2373 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2376 case SHADER_OPCODE_RND_MODE
:
2377 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2378 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2382 unreachable("Unsupported opcode");
2384 case SHADER_OPCODE_LOAD_PAYLOAD
:
2385 unreachable("Should be lowered by lower_load_payload()");
2388 if (multiple_instructions_emitted
)
2391 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2392 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2393 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2394 "emitting more than 1 instruction");
2396 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2398 if (inst
->conditional_mod
)
2399 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2400 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2401 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2405 brw_set_uip_jip(p
, start_offset
);
2407 /* end of program sentinel */
2408 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2413 if (unlikely(debug_flag
))
2415 brw_validate_instructions(devinfo
, p
->store
,
2417 p
->next_insn_offset
,
2420 int before_size
= p
->next_insn_offset
- start_offset
;
2421 brw_compact_instructions(p
, start_offset
, disasm_info
);
2422 int after_size
= p
->next_insn_offset
- start_offset
;
2424 if (unlikely(debug_flag
)) {
2425 fprintf(stderr
, "Native code for %s\n"
2426 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2427 " bytes (%.0f%%)\n",
2428 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2429 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2430 100.0f
* (before_size
- after_size
) / before_size
);
2432 dump_assembly(p
->store
, disasm_info
);
2434 ralloc_free(disasm_info
);
2437 compiler
->shader_debug_log(log_data
,
2438 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2439 "%d:%d spills:fills, Promoted %u constants, "
2440 "compacted %d to %d bytes.",
2441 _mesa_shader_stage_to_abbrev(stage
),
2442 dispatch_width
, before_size
/ 16,
2443 loop_count
, cfg
->cycle_count
, spill_count
,
2444 fill_count
, promoted_constants
, before_size
,
2447 return start_offset
;
2451 fs_generator::get_assembly()
2453 return brw_get_program(p
, &prog_data
->program_size
);