2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
45 last_scratch
= ALIGN(nir
->scratch_size
, 4) * dispatch_width
;
47 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_shader_out_variable(var
, nir
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
, true);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
) {
104 /* Add uniforms for builtins after regular NIR uniforms. */
105 assert(uniforms
== prog_data
->nr_params
);
108 if (nir
->info
.cs
.local_size_variable
&&
109 compiler
->lower_variable_group_size
) {
110 param
= brw_stage_prog_data_add_params(prog_data
, 3);
111 for (unsigned i
= 0; i
< 3; i
++) {
112 param
[i
] = (BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
+ i
);
113 group_size
[i
] = fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
117 /* Subgroup ID must be the last uniform on the list. This will make
118 * easier later to split between cross thread and per thread
121 param
= brw_stage_prog_data_add_params(prog_data
, 1);
122 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
123 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
128 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
132 nir_foreach_instr(instr
, block
) {
133 if (instr
->type
!= nir_instr_type_intrinsic
)
136 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
137 switch (intrin
->intrinsic
) {
138 case nir_intrinsic_load_vertex_id
:
139 case nir_intrinsic_load_base_vertex
:
140 unreachable("should be lowered by nir_lower_system_values().");
142 case nir_intrinsic_load_vertex_id_zero_base
:
143 case nir_intrinsic_load_is_indexed_draw
:
144 case nir_intrinsic_load_first_vertex
:
145 case nir_intrinsic_load_instance_id
:
146 case nir_intrinsic_load_base_instance
:
147 case nir_intrinsic_load_draw_id
:
148 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
150 case nir_intrinsic_load_invocation_id
:
151 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
153 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
154 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
155 if (reg
->file
== BAD_FILE
) {
156 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
157 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
158 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
159 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
164 case nir_intrinsic_load_sample_pos
:
165 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
166 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
167 if (reg
->file
== BAD_FILE
)
168 *reg
= *v
->emit_samplepos_setup();
171 case nir_intrinsic_load_sample_id
:
172 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
173 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
174 if (reg
->file
== BAD_FILE
)
175 *reg
= *v
->emit_sampleid_setup();
178 case nir_intrinsic_load_sample_mask_in
:
179 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
180 assert(v
->devinfo
->gen
>= 7);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
182 if (reg
->file
== BAD_FILE
)
183 *reg
= *v
->emit_samplemaskin_setup();
186 case nir_intrinsic_load_work_group_id
:
187 assert(v
->stage
== MESA_SHADER_COMPUTE
||
188 v
->stage
== MESA_SHADER_KERNEL
);
189 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
190 if (reg
->file
== BAD_FILE
)
191 *reg
= *v
->emit_cs_work_group_id_setup();
194 case nir_intrinsic_load_helper_invocation
:
195 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
196 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
197 if (reg
->file
== BAD_FILE
) {
198 const fs_builder abld
=
199 v
->bld
.annotate("gl_HelperInvocation", NULL
);
201 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
202 * pixel mask is in g1.7 of the thread payload.
204 * We move the per-channel pixel enable bit to the low bit of each
205 * channel by shifting the byte containing the pixel mask by the
206 * vector immediate 0x76543210UV.
208 * The region of <1,8,0> reads only 1 byte (the pixel masks for
209 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
210 * masks for 2 and 3) in SIMD16.
212 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
214 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
215 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
216 hbld
.SHR(offset(shifted
, hbld
, i
),
217 stride(retype(brw_vec1_grf(1 + i
, 7),
218 BRW_REGISTER_TYPE_UB
),
220 brw_imm_v(0x76543210));
223 /* A set bit in the pixel mask means the channel is enabled, but
224 * that is the opposite of gl_HelperInvocation so we need to invert
227 * The negate source-modifier bit of logical instructions on Gen8+
228 * performs 1's complement negation, so we can use that instead of
231 fs_reg inverted
= negate(shifted
);
232 if (v
->devinfo
->gen
< 8) {
233 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
234 abld
.NOT(inverted
, shifted
);
237 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
238 * with 1 and negating.
240 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
241 abld
.AND(anded
, inverted
, brw_imm_uw(1));
243 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
244 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
258 fs_visitor::nir_emit_system_values()
260 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
261 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
262 nir_system_values
[i
] = fs_reg();
265 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
266 * never end up using it.
269 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
270 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
271 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
273 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
274 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
275 if (dispatch_width
> 8)
276 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
277 if (dispatch_width
> 16) {
278 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
279 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
283 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
284 nir_foreach_block(block
, impl
)
285 emit_system_values_block(block
, this);
289 * Returns a type based on a reference_type (word, float, half-float) and a
292 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
294 * @FIXME: 64-bit return types are always DF on integer types to maintain
295 * compability with uses of DF previously to the introduction of int64
299 brw_reg_type_from_bit_size(const unsigned bit_size
,
300 const brw_reg_type reference_type
)
302 switch(reference_type
) {
303 case BRW_REGISTER_TYPE_HF
:
304 case BRW_REGISTER_TYPE_F
:
305 case BRW_REGISTER_TYPE_DF
:
308 return BRW_REGISTER_TYPE_HF
;
310 return BRW_REGISTER_TYPE_F
;
312 return BRW_REGISTER_TYPE_DF
;
314 unreachable("Invalid bit size");
316 case BRW_REGISTER_TYPE_B
:
317 case BRW_REGISTER_TYPE_W
:
318 case BRW_REGISTER_TYPE_D
:
319 case BRW_REGISTER_TYPE_Q
:
322 return BRW_REGISTER_TYPE_B
;
324 return BRW_REGISTER_TYPE_W
;
326 return BRW_REGISTER_TYPE_D
;
328 return BRW_REGISTER_TYPE_Q
;
330 unreachable("Invalid bit size");
332 case BRW_REGISTER_TYPE_UB
:
333 case BRW_REGISTER_TYPE_UW
:
334 case BRW_REGISTER_TYPE_UD
:
335 case BRW_REGISTER_TYPE_UQ
:
338 return BRW_REGISTER_TYPE_UB
;
340 return BRW_REGISTER_TYPE_UW
;
342 return BRW_REGISTER_TYPE_UD
;
344 return BRW_REGISTER_TYPE_UQ
;
346 unreachable("Invalid bit size");
349 unreachable("Unknown type");
354 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
356 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
357 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
358 nir_locals
[i
] = fs_reg();
361 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
362 unsigned array_elems
=
363 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
364 unsigned size
= array_elems
* reg
->num_components
;
365 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
366 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
367 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
370 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
373 nir_emit_cf_list(&impl
->body
);
377 fs_visitor::nir_emit_cf_list(exec_list
*list
)
379 exec_list_validate(list
);
380 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
381 switch (node
->type
) {
383 nir_emit_if(nir_cf_node_as_if(node
));
386 case nir_cf_node_loop
:
387 nir_emit_loop(nir_cf_node_as_loop(node
));
390 case nir_cf_node_block
:
391 nir_emit_block(nir_cf_node_as_block(node
));
395 unreachable("Invalid CFG node block");
401 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
406 /* If the condition has the form !other_condition, use other_condition as
407 * the source, but invert the predicate on the if instruction.
409 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
410 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
412 cond_reg
= get_nir_src(cond
->src
[0].src
);
415 cond_reg
= get_nir_src(if_stmt
->condition
);
418 /* first, put the condition into f0 */
419 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
420 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
421 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
423 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
425 nir_emit_cf_list(&if_stmt
->then_list
);
427 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
428 bld
.emit(BRW_OPCODE_ELSE
);
429 nir_emit_cf_list(&if_stmt
->else_list
);
432 bld
.emit(BRW_OPCODE_ENDIF
);
434 if (devinfo
->gen
< 7)
435 limit_dispatch_width(16, "Non-uniform control flow unsupported "
440 fs_visitor::nir_emit_loop(nir_loop
*loop
)
442 bld
.emit(BRW_OPCODE_DO
);
444 nir_emit_cf_list(&loop
->body
);
446 bld
.emit(BRW_OPCODE_WHILE
);
448 if (devinfo
->gen
< 7)
449 limit_dispatch_width(16, "Non-uniform control flow unsupported "
454 fs_visitor::nir_emit_block(nir_block
*block
)
456 nir_foreach_instr(instr
, block
) {
457 nir_emit_instr(instr
);
462 fs_visitor::nir_emit_instr(nir_instr
*instr
)
464 const fs_builder abld
= bld
.annotate(NULL
, instr
);
466 switch (instr
->type
) {
467 case nir_instr_type_alu
:
468 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
471 case nir_instr_type_deref
:
472 unreachable("All derefs should've been lowered");
475 case nir_instr_type_intrinsic
:
477 case MESA_SHADER_VERTEX
:
478 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 case MESA_SHADER_TESS_CTRL
:
481 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
483 case MESA_SHADER_TESS_EVAL
:
484 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
486 case MESA_SHADER_GEOMETRY
:
487 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
489 case MESA_SHADER_FRAGMENT
:
490 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
492 case MESA_SHADER_COMPUTE
:
493 case MESA_SHADER_KERNEL
:
494 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
497 unreachable("unsupported shader stage");
501 case nir_instr_type_tex
:
502 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
505 case nir_instr_type_load_const
:
506 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
509 case nir_instr_type_ssa_undef
:
510 /* We create a new VGRF for undefs on every use (by handling
511 * them in get_nir_src()), rather than for each definition.
512 * This helps register coalescing eliminate MOVs from undef.
516 case nir_instr_type_jump
:
517 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
521 unreachable("unknown instruction type");
526 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
530 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
531 const fs_reg
&result
)
533 if (!instr
->src
[0].src
.is_ssa
||
534 !instr
->src
[0].src
.ssa
->parent_instr
)
537 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
540 nir_alu_instr
*src0
=
541 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
543 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
544 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
547 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
549 /* Element type to extract.*/
550 const brw_reg_type type
= brw_int_type(
551 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
552 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
554 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
555 op0
.type
= brw_type_for_nir_type(devinfo
,
556 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
557 nir_src_bit_size(src0
->src
[0].src
)));
558 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
560 bld
.MOV(result
, subscript(op0
, type
, element
));
565 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
566 const fs_reg
&result
)
568 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
569 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
572 if (!nir_src_is_const(instr
->src
[1].src
) ||
573 !nir_src_is_const(instr
->src
[2].src
))
576 const float value1
= nir_src_as_float(instr
->src
[1].src
);
577 const float value2
= nir_src_as_float(instr
->src
[2].src
);
578 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
581 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
582 assert(value1
== -value2
);
584 fs_reg tmp
= vgrf(glsl_type::int_type
);
586 if (devinfo
->gen
>= 12) {
587 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
588 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
590 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
592 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
593 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
595 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
597 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
598 g1
, brw_imm_uw(0x3f80));
601 bld
.MOV(tmp
, negate(tmp
));
603 } else if (devinfo
->gen
>= 6) {
604 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
605 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
607 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
609 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
610 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
612 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
614 * This negation looks like it's safe in practice, because bits 0:4 will
615 * surely be TRIANGLES
618 if (value1
== -1.0f
) {
622 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
623 g0
, brw_imm_uw(0x3f80));
625 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
626 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
628 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
630 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
631 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
633 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
635 * This negation looks like it's safe in practice, because bits 0:4 will
636 * surely be TRIANGLES
639 if (value1
== -1.0f
) {
643 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
645 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
651 emit_find_msb_using_lzd(const fs_builder
&bld
,
652 const fs_reg
&result
,
660 /* LZD of an absolute value source almost always does the right
661 * thing. There are two problem values:
663 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
664 * 0. However, findMSB(int(0x80000000)) == 30.
666 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
667 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
669 * For a value of zero or negative one, -1 will be returned.
671 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
672 * findMSB(-(1<<x)) should return x-1.
674 * For all negative number cases, including 0x80000000 and
675 * 0xffffffff, the correct value is obtained from LZD if instead of
676 * negating the (already negative) value the logical-not is used. A
677 * conditonal logical-not can be achieved in two instructions.
679 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
681 bld
.ASR(temp
, src
, brw_imm_d(31));
682 bld
.XOR(temp
, temp
, src
);
685 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
686 retype(temp
, BRW_REGISTER_TYPE_UD
));
688 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
689 * from the LSB side. Subtract the result from 31 to convert the MSB
690 * count into an LSB count. If no bits are set, LZD will return 32.
691 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
693 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
694 inst
->src
[0].negate
= true;
698 brw_rnd_mode_from_nir_op (const nir_op op
) {
700 case nir_op_f2f16_rtz
:
701 return BRW_RND_MODE_RTZ
;
702 case nir_op_f2f16_rtne
:
703 return BRW_RND_MODE_RTNE
;
705 unreachable("Operation doesn't support rounding mode");
710 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
712 if (nir_has_any_rounding_mode_rtne(execution_mode
))
713 return BRW_RND_MODE_RTNE
;
714 if (nir_has_any_rounding_mode_rtz(execution_mode
))
715 return BRW_RND_MODE_RTZ
;
716 return BRW_RND_MODE_UNSPECIFIED
;
720 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
721 nir_alu_instr
*instr
,
726 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
728 result
.type
= brw_type_for_nir_type(devinfo
,
729 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
730 nir_dest_bit_size(instr
->dest
.dest
)));
732 assert(!instr
->dest
.saturate
);
734 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
735 /* We don't lower to source modifiers so they should not exist. */
736 assert(!instr
->src
[i
].abs
);
737 assert(!instr
->src
[i
].negate
);
739 op
[i
] = get_nir_src(instr
->src
[i
].src
);
740 op
[i
].type
= brw_type_for_nir_type(devinfo
,
741 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
742 nir_src_bit_size(instr
->src
[i
].src
)));
745 /* Move and vecN instrutions may still be vectored. Return the raw,
746 * vectored source and destination so that fs_visitor::nir_emit_alu can
747 * handle it. Other callers should not have to handle these kinds of
760 /* At this point, we have dealt with any instruction that operates on
761 * more than a single channel. Therefore, we can just adjust the source
762 * and destination registers for that channel and emit the instruction.
764 unsigned channel
= 0;
765 if (nir_op_infos
[instr
->op
].output_size
== 0) {
766 /* Since NIR is doing the scalarizing for us, we should only ever see
767 * vectorized operations with a single channel.
769 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
770 channel
= ffs(instr
->dest
.write_mask
) - 1;
772 result
= offset(result
, bld
, channel
);
775 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
776 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
777 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
784 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
787 for (unsigned i
= 0; i
< 2; i
++) {
788 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
790 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
) {
791 /* The source of the inot is now the source of instr. */
792 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
794 assert(!op
[i
].negate
);
797 op
[i
] = resolve_source_modifiers(op
[i
]);
803 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
805 nir_alu_instr
*instr
)
807 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
810 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
812 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
815 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
816 * of valid size-changing combinations is a bit more complex.
818 * The source restriction is just because I was lazy about generating the
821 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
822 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
825 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
826 * this is float(1 + a).
830 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
832 /* Ignore the saturate modifier, if there is one. The result of the
833 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
835 bld
.ADD(result
, op
, brw_imm_d(1));
841 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
843 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
844 * the source of \c instr that is a \c nir_op_fsign.
847 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
848 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
852 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
853 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
855 if (instr
->op
!= nir_op_fsign
) {
856 const nir_alu_instr
*const fsign_instr
=
857 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
859 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
860 * fsign_src] has the other multiply source. This must be rearranged so
861 * that op[0] is the source of the fsign op[1] is the other multiply
867 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
869 const nir_alu_type t
=
870 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
871 nir_src_bit_size(fsign_instr
->src
[0].src
));
873 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
875 unsigned channel
= 0;
876 if (nir_op_infos
[instr
->op
].output_size
== 0) {
877 /* Since NIR is doing the scalarizing for us, we should only ever see
878 * vectorized operations with a single channel.
880 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
881 channel
= ffs(instr
->dest
.write_mask
) - 1;
884 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
887 if (type_sz(op
[0].type
) == 2) {
888 /* AND(val, 0x8000) gives the sign bit.
890 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
892 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
893 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
895 op
[0].type
= BRW_REGISTER_TYPE_UW
;
896 result
.type
= BRW_REGISTER_TYPE_UW
;
897 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
899 if (instr
->op
== nir_op_fsign
)
900 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
902 /* Use XOR here to get the result sign correct. */
903 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
906 inst
->predicate
= BRW_PREDICATE_NORMAL
;
907 } else if (type_sz(op
[0].type
) == 4) {
908 /* AND(val, 0x80000000) gives the sign bit.
910 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
913 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
915 op
[0].type
= BRW_REGISTER_TYPE_UD
;
916 result
.type
= BRW_REGISTER_TYPE_UD
;
917 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
919 if (instr
->op
== nir_op_fsign
)
920 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
922 /* Use XOR here to get the result sign correct. */
923 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
926 inst
->predicate
= BRW_PREDICATE_NORMAL
;
928 /* For doubles we do the same but we need to consider:
930 * - 2-src instructions can't operate with 64-bit immediates
931 * - The sign is encoded in the high 32-bit of each DF
932 * - We need to produce a DF result.
935 fs_reg zero
= vgrf(glsl_type::double_type
);
936 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
937 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
939 bld
.MOV(result
, zero
);
941 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
942 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
943 brw_imm_ud(0x80000000u
));
945 if (instr
->op
== nir_op_fsign
) {
946 set_predicate(BRW_PREDICATE_NORMAL
,
947 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
949 /* This could be done better in some cases. If the scale is an
950 * immediate with the low 32-bits all 0, emitting a separate XOR and
951 * OR would allow an algebraic optimization to remove the OR. There
952 * are currently zero instances of fsign(double(x))*IMM in shader-db
953 * or any test suite, so it is hard to care at this time.
955 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
956 inst
= bld
.XOR(result_int64
, result_int64
,
957 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
963 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
965 * Checks the operands of a \c nir_op_fmul to determine whether or not
966 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
968 * \param instr The multiplication instruction
970 * \param fsign_src The source of \c instr that may or may not be a
974 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
976 assert(instr
->op
== nir_op_fmul
);
978 nir_alu_instr
*const fsign_instr
=
979 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
983 * 1. instr->src[fsign_src] must be a nir_op_fsign.
984 * 2. The nir_op_fsign can only be used by this multiplication.
985 * 3. The source that is the nir_op_fsign does not have source modifiers.
986 * \c emit_fsign only examines the source modifiers of the source of the
989 * The nir_op_fsign must also not have the saturate modifier, but steps
990 * have already been taken (in nir_opt_algebraic) to ensure that.
992 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
993 is_used_once(fsign_instr
);
997 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1000 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1002 unsigned execution_mode
=
1003 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1006 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1008 switch (instr
->op
) {
1013 fs_reg temp
= result
;
1014 bool need_extra_copy
= false;
1015 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1016 if (!instr
->src
[i
].src
.is_ssa
&&
1017 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1018 need_extra_copy
= true;
1019 temp
= bld
.vgrf(result
.type
, 4);
1024 for (unsigned i
= 0; i
< 4; i
++) {
1025 if (!(instr
->dest
.write_mask
& (1 << i
)))
1028 if (instr
->op
== nir_op_mov
) {
1029 inst
= bld
.MOV(offset(temp
, bld
, i
),
1030 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1032 inst
= bld
.MOV(offset(temp
, bld
, i
),
1033 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1037 /* In this case the source and destination registers were the same,
1038 * so we need to insert an extra set of moves in order to deal with
1041 if (need_extra_copy
) {
1042 for (unsigned i
= 0; i
< 4; i
++) {
1043 if (!(instr
->dest
.write_mask
& (1 << i
)))
1046 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1054 if (optimize_extract_to_float(instr
, result
))
1056 inst
= bld
.MOV(result
, op
[0]);
1059 case nir_op_f2f16_rtne
:
1060 case nir_op_f2f16_rtz
:
1061 case nir_op_f2f16
: {
1062 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1064 if (nir_op_f2f16
== instr
->op
)
1065 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1067 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1069 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1070 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1072 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1073 * on the HW gen, it is a special hw opcode or just a MOV, and
1074 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1076 * But if we want to use that opcode, we need to provide support on
1077 * different optimizations and lowerings. As right now HF support is
1078 * only for gen8+, it will be better to use directly the MOV, and use
1079 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1081 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1082 inst
= bld
.MOV(result
, op
[0]);
1093 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1095 op
[0].type
= BRW_REGISTER_TYPE_D
;
1096 op
[0].negate
= !op
[0].negate
;
1119 if (result
.type
== BRW_REGISTER_TYPE_B
||
1120 result
.type
== BRW_REGISTER_TYPE_UB
||
1121 result
.type
== BRW_REGISTER_TYPE_HF
)
1122 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1124 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1125 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1126 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1127 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1129 inst
= bld
.MOV(result
, op
[0]);
1133 inst
= bld
.MOV(result
, op
[0]);
1134 inst
->saturate
= true;
1139 op
[0].negate
= true;
1140 inst
= bld
.MOV(result
, op
[0]);
1145 op
[0].negate
= false;
1147 inst
= bld
.MOV(result
, op
[0]);
1151 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1153 brw_rnd_mode_from_execution_mode(execution_mode
);
1154 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1158 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1159 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1161 inst
= bld
.MOV(result
, op
[0]);
1165 emit_fsign(bld
, instr
, result
, op
, 0);
1169 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1173 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1177 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1181 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1185 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1189 if (fs_key
->high_quality_derivatives
) {
1190 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1192 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1195 case nir_op_fddx_fine
:
1196 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1198 case nir_op_fddx_coarse
:
1199 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1202 if (fs_key
->high_quality_derivatives
) {
1203 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1205 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1208 case nir_op_fddy_fine
:
1209 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1211 case nir_op_fddy_coarse
:
1212 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1216 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1218 brw_rnd_mode_from_execution_mode(execution_mode
);
1219 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1224 inst
= bld
.ADD(result
, op
[0], op
[1]);
1227 case nir_op_iadd_sat
:
1228 case nir_op_uadd_sat
:
1229 inst
= bld
.ADD(result
, op
[0], op
[1]);
1230 inst
->saturate
= true;
1233 case nir_op_isub_sat
:
1234 bld
.emit(SHADER_OPCODE_ISUB_SAT
, result
, op
[0], op
[1]);
1237 case nir_op_usub_sat
:
1238 bld
.emit(SHADER_OPCODE_USUB_SAT
, result
, op
[0], op
[1]);
1243 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1244 inst
= bld
.AVG(result
, op
[0], op
[1]);
1248 case nir_op_uhadd
: {
1249 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1250 fs_reg tmp
= bld
.vgrf(result
.type
);
1252 if (devinfo
->gen
>= 8) {
1253 op
[0] = resolve_source_modifiers(op
[0]);
1254 op
[1] = resolve_source_modifiers(op
[1]);
1257 /* AVG(x, y) - ((x ^ y) & 1) */
1258 bld
.XOR(tmp
, op
[0], op
[1]);
1259 bld
.AND(tmp
, tmp
, retype(brw_imm_ud(1), result
.type
));
1260 bld
.AVG(result
, op
[0], op
[1]);
1261 inst
= bld
.ADD(result
, result
, tmp
);
1262 inst
->src
[1].negate
= true;
1267 for (unsigned i
= 0; i
< 2; i
++) {
1268 if (can_fuse_fmul_fsign(instr
, i
)) {
1269 emit_fsign(bld
, instr
, result
, op
, i
);
1274 /* We emit the rounding mode after the previous fsign optimization since
1275 * it won't result in a MUL, but will try to negate the value by other
1278 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1280 brw_rnd_mode_from_execution_mode(execution_mode
);
1281 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1285 inst
= bld
.MUL(result
, op
[0], op
[1]);
1288 case nir_op_imul_2x32_64
:
1289 case nir_op_umul_2x32_64
:
1290 bld
.MUL(result
, op
[0], op
[1]);
1293 case nir_op_imul_32x16
:
1294 case nir_op_umul_32x16
: {
1295 const bool ud
= instr
->op
== nir_op_umul_32x16
;
1297 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1299 /* Before Gen7, the order of the 32-bit source and the 16-bit source was
1300 * swapped. The extension isn't enabled on those platforms, so don't
1301 * pretend to support the differences.
1303 assert(devinfo
->gen
>= 7);
1305 if (op
[1].file
== IMM
)
1306 op
[1] = ud
? brw_imm_uw(op
[1].ud
) : brw_imm_w(op
[1].d
);
1308 const enum brw_reg_type word_type
=
1309 ud
? BRW_REGISTER_TYPE_UW
: BRW_REGISTER_TYPE_W
;
1311 op
[1] = subscript(op
[1], word_type
, 0);
1314 const enum brw_reg_type dword_type
=
1315 ud
? BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_D
;
1317 bld
.MUL(result
, retype(op
[0], dword_type
), op
[1]);
1322 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1323 bld
.MUL(result
, op
[0], op
[1]);
1326 case nir_op_imul_high
:
1327 case nir_op_umul_high
:
1328 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1329 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1334 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1335 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1338 case nir_op_uadd_carry
:
1339 unreachable("Should have been lowered by carry_to_arith().");
1341 case nir_op_usub_borrow
:
1342 unreachable("Should have been lowered by borrow_to_arith().");
1346 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1347 * appears that our hardware just does the right thing for signed
1350 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1351 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1355 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1356 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1358 /* Math instructions don't support conditional mod */
1359 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1360 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1362 /* Now, we need to determine if signs of the sources are different.
1363 * When we XOR the sources, the top bit is 0 if they are the same and 1
1364 * if they are different. We can then use a conditional modifier to
1365 * turn that into a predicate. This leads us to an XOR.l instruction.
1367 * Technically, according to the PRM, you're not allowed to use .l on a
1368 * XOR instruction. However, emperical experiments and Curro's reading
1369 * of the simulator source both indicate that it's safe.
1371 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1372 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1373 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1374 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1376 /* If the result of the initial remainder operation is non-zero and the
1377 * two sources have different signs, add in a copy of op[1] to get the
1378 * final integer modulus value.
1380 inst
= bld
.ADD(result
, result
, op
[1]);
1381 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1388 case nir_op_fneu32
: {
1389 fs_reg dest
= result
;
1391 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1393 dest
= bld
.vgrf(op
[0].type
, 1);
1395 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1397 if (bit_size
> 32) {
1398 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1399 } else if(bit_size
< 32) {
1400 /* When we convert the result to 32-bit we need to be careful and do
1401 * it as a signed conversion to get sign extension (for 32-bit true)
1403 const brw_reg_type src_type
=
1404 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1406 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1416 case nir_op_ine32
: {
1417 fs_reg dest
= result
;
1419 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1420 * type. So we convert both operands for the comparison.
1423 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1424 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1426 const uint32_t bit_size
= type_sz(temp_op
[0].type
) * 8;
1428 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1430 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1431 brw_cmod_for_nir_comparison(instr
->op
));
1433 if (bit_size
> 32) {
1434 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1435 } else if (bit_size
< 32) {
1436 /* When we convert the result to 32-bit we need to be careful and do
1437 * it as a signed conversion to get sign extension (for 32-bit true)
1439 const brw_reg_type src_type
=
1440 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1442 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1448 if (devinfo
->gen
>= 8) {
1449 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1451 if (inot_src_instr
!= NULL
&&
1452 (inot_src_instr
->op
== nir_op_ior
||
1453 inot_src_instr
->op
== nir_op_ixor
||
1454 inot_src_instr
->op
== nir_op_iand
)) {
1455 /* The sources of the source logical instruction are now the
1456 * sources of the instruction that will be generated.
1458 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1459 resolve_inot_sources(bld
, inot_src_instr
, op
);
1461 /* Smash all of the sources and destination to be signed. This
1462 * doesn't matter for the operation of the instruction, but cmod
1463 * propagation fails on unsigned sources with negation (due to
1464 * fs_inst::can_do_cmod returning false).
1467 brw_type_for_nir_type(devinfo
,
1468 (nir_alu_type
)(nir_type_int
|
1469 nir_dest_bit_size(instr
->dest
.dest
)));
1471 brw_type_for_nir_type(devinfo
,
1472 (nir_alu_type
)(nir_type_int
|
1473 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1475 brw_type_for_nir_type(devinfo
,
1476 (nir_alu_type
)(nir_type_int
|
1477 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1479 /* For XOR, only invert one of the sources. Arbitrarily choose
1482 op
[0].negate
= !op
[0].negate
;
1483 if (inot_src_instr
->op
!= nir_op_ixor
)
1484 op
[1].negate
= !op
[1].negate
;
1486 switch (inot_src_instr
->op
) {
1488 bld
.AND(result
, op
[0], op
[1]);
1492 bld
.OR(result
, op
[0], op
[1]);
1496 bld
.XOR(result
, op
[0], op
[1]);
1500 unreachable("impossible opcode");
1503 op
[0] = resolve_source_modifiers(op
[0]);
1505 bld
.NOT(result
, op
[0]);
1508 if (devinfo
->gen
>= 8) {
1509 resolve_inot_sources(bld
, instr
, op
);
1511 bld
.XOR(result
, op
[0], op
[1]);
1514 if (devinfo
->gen
>= 8) {
1515 resolve_inot_sources(bld
, instr
, op
);
1517 bld
.OR(result
, op
[0], op
[1]);
1520 if (devinfo
->gen
>= 8) {
1521 resolve_inot_sources(bld
, instr
, op
);
1523 bld
.AND(result
, op
[0], op
[1]);
1529 case nir_op_b32all_fequal2
:
1530 case nir_op_b32all_iequal2
:
1531 case nir_op_b32all_fequal3
:
1532 case nir_op_b32all_iequal3
:
1533 case nir_op_b32all_fequal4
:
1534 case nir_op_b32all_iequal4
:
1535 case nir_op_b32any_fnequal2
:
1536 case nir_op_b32any_inequal2
:
1537 case nir_op_b32any_fnequal3
:
1538 case nir_op_b32any_inequal3
:
1539 case nir_op_b32any_fnequal4
:
1540 case nir_op_b32any_inequal4
:
1541 unreachable("Lowered by nir_lower_alu_reductions");
1544 unreachable("not reached: should be handled by ldexp_to_arith()");
1547 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1551 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1555 case nir_op_f2b32
: {
1556 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1557 if (bit_size
== 64) {
1558 /* two-argument instructions can't take 64-bit immediates */
1562 if (instr
->op
== nir_op_f2b32
) {
1563 zero
= vgrf(glsl_type::double_type
);
1564 tmp
= vgrf(glsl_type::double_type
);
1565 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1567 zero
= vgrf(glsl_type::int64_t_type
);
1568 tmp
= vgrf(glsl_type::int64_t_type
);
1569 bld
.MOV(zero
, brw_imm_q(0));
1572 /* A SIMD16 execution needs to be split in two instructions, so use
1573 * a vgrf instead of the flag register as dst so instruction splitting
1576 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1577 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1580 if (bit_size
== 32) {
1581 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1583 assert(bit_size
== 16);
1584 zero
= instr
->op
== nir_op_f2b32
?
1585 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1587 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1593 inst
= bld
.RNDZ(result
, op
[0]);
1594 if (devinfo
->gen
< 6) {
1595 set_condmod(BRW_CONDITIONAL_R
, inst
);
1596 set_predicate(BRW_PREDICATE_NORMAL
,
1597 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1598 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1602 case nir_op_fceil
: {
1603 op
[0].negate
= !op
[0].negate
;
1604 fs_reg temp
= vgrf(glsl_type::float_type
);
1605 bld
.RNDD(temp
, op
[0]);
1607 inst
= bld
.MOV(result
, temp
);
1611 inst
= bld
.RNDD(result
, op
[0]);
1614 inst
= bld
.FRC(result
, op
[0]);
1616 case nir_op_fround_even
:
1617 inst
= bld
.RNDE(result
, op
[0]);
1618 if (devinfo
->gen
< 6) {
1619 set_condmod(BRW_CONDITIONAL_R
, inst
);
1620 set_predicate(BRW_PREDICATE_NORMAL
,
1621 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1622 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1626 case nir_op_fquantize2f16
: {
1627 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1628 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1629 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1631 /* The destination stride must be at least as big as the source stride. */
1632 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1635 /* Check for denormal */
1636 fs_reg abs_src0
= op
[0];
1637 abs_src0
.abs
= true;
1638 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1640 /* Get the appropriately signed zero */
1641 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1642 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1643 brw_imm_ud(0x80000000));
1644 /* Do the actual F32 -> F16 -> F32 conversion */
1645 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1646 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1647 /* Select that or zero based on normal status */
1648 inst
= bld
.SEL(result
, zero
, tmp32
);
1649 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1656 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1662 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1665 case nir_op_pack_snorm_2x16
:
1666 case nir_op_pack_snorm_4x8
:
1667 case nir_op_pack_unorm_2x16
:
1668 case nir_op_pack_unorm_4x8
:
1669 case nir_op_unpack_snorm_2x16
:
1670 case nir_op_unpack_snorm_4x8
:
1671 case nir_op_unpack_unorm_2x16
:
1672 case nir_op_unpack_unorm_4x8
:
1673 case nir_op_unpack_half_2x16
:
1674 case nir_op_pack_half_2x16
:
1675 unreachable("not reached: should be handled by lower_packing_builtins");
1677 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1678 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1680 case nir_op_unpack_half_2x16_split_x
:
1681 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1682 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1685 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1686 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1688 case nir_op_unpack_half_2x16_split_y
:
1689 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1690 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1693 case nir_op_pack_64_2x32_split
:
1694 case nir_op_pack_32_2x16_split
:
1695 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1698 case nir_op_unpack_64_2x32_split_x
:
1699 case nir_op_unpack_64_2x32_split_y
: {
1700 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1701 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1703 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1707 case nir_op_unpack_32_2x16_split_x
:
1708 case nir_op_unpack_32_2x16_split_y
: {
1709 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1710 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1712 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1717 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1720 case nir_op_bitfield_reverse
:
1721 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1722 bld
.BFREV(result
, op
[0]);
1725 case nir_op_bit_count
:
1726 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1727 bld
.CBIT(result
, op
[0]);
1730 case nir_op_ufind_msb
: {
1731 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1732 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1737 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1738 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1741 case nir_op_ifind_msb
: {
1742 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1744 if (devinfo
->gen
< 7) {
1745 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1747 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1749 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1750 * count from the LSB side. If FBH didn't return an error
1751 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1752 * count into an LSB count.
1754 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1756 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1757 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1758 inst
->src
[0].negate
= true;
1763 case nir_op_find_lsb
:
1764 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1766 if (devinfo
->gen
< 7) {
1767 fs_reg temp
= vgrf(glsl_type::int_type
);
1769 /* (x & -x) generates a value that consists of only the LSB of x.
1770 * For all powers of 2, findMSB(y) == findLSB(y).
1772 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1773 fs_reg negated_src
= src
;
1775 /* One must be negated, and the other must be non-negated. It
1776 * doesn't matter which is which.
1778 negated_src
.negate
= true;
1781 bld
.AND(temp
, src
, negated_src
);
1782 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1784 bld
.FBL(result
, op
[0]);
1788 case nir_op_ubitfield_extract
:
1789 case nir_op_ibitfield_extract
:
1790 unreachable("should have been lowered");
1793 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1794 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1797 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1798 bld
.BFI1(result
, op
[0], op
[1]);
1801 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1802 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1805 case nir_op_bitfield_insert
:
1806 unreachable("not reached: should have been lowered");
1809 bld
.SHL(result
, op
[0], op
[1]);
1812 bld
.ASR(result
, op
[0], op
[1]);
1815 bld
.SHR(result
, op
[0], op
[1]);
1819 bld
.ROL(result
, op
[0], op
[1]);
1822 bld
.ROR(result
, op
[0], op
[1]);
1825 case nir_op_pack_half_2x16_split
:
1826 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1830 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1832 brw_rnd_mode_from_execution_mode(execution_mode
);
1833 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1837 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1841 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1843 brw_rnd_mode_from_execution_mode(execution_mode
);
1844 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1848 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1851 case nir_op_b32csel
:
1852 if (optimize_frontfacing_ternary(instr
, result
))
1855 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1856 inst
= bld
.SEL(result
, op
[1], op
[2]);
1857 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1860 case nir_op_extract_u8
:
1861 case nir_op_extract_i8
: {
1862 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1867 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1868 * Use two instructions and a word or DWord intermediate integer type.
1870 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1871 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1873 if (instr
->op
== nir_op_extract_i8
) {
1874 /* If we need to sign extend, extract to a word first */
1875 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1876 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1877 bld
.MOV(result
, w_temp
);
1878 } else if (byte
& 1) {
1879 /* Extract the high byte from the word containing the desired byte
1883 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1886 /* Otherwise use an AND with 0xff and a word type */
1888 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1892 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1893 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1898 case nir_op_extract_u16
:
1899 case nir_op_extract_i16
: {
1900 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1901 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1902 bld
.MOV(result
, subscript(op
[0], type
, word
));
1907 unreachable("unhandled instruction");
1910 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1911 * to sign extend the low bit to 0/~0
1913 if (devinfo
->gen
<= 5 &&
1914 !result
.is_null() &&
1915 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1916 fs_reg masked
= vgrf(glsl_type::int_type
);
1917 bld
.AND(masked
, result
, brw_imm_d(1));
1918 masked
.negate
= true;
1919 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1924 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1925 nir_load_const_instr
*instr
)
1927 const brw_reg_type reg_type
=
1928 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1929 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1931 switch (instr
->def
.bit_size
) {
1933 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1934 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1938 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1939 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1943 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1944 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1948 assert(devinfo
->gen
>= 7);
1949 if (devinfo
->gen
== 7) {
1950 /* We don't get 64-bit integer types until gen8 */
1951 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1952 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1953 setup_imm_df(bld
, instr
->value
[i
].f64
));
1956 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1957 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1962 unreachable("Invalid bit size");
1965 nir_ssa_values
[instr
->def
.index
] = reg
;
1969 fs_visitor::get_nir_src(const nir_src
&src
)
1973 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1974 const brw_reg_type reg_type
=
1975 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1976 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1978 reg
= nir_ssa_values
[src
.ssa
->index
];
1981 /* We don't handle indirects on locals */
1982 assert(src
.reg
.indirect
== NULL
);
1983 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1984 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1987 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1988 /* The only 64-bit type available on gen7 is DF, so use that. */
1989 reg
.type
= BRW_REGISTER_TYPE_DF
;
1991 /* To avoid floating-point denorm flushing problems, set the type by
1992 * default to an integer type - instructions that need floating point
1993 * semantics will set this to F if they need to
1995 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1996 BRW_REGISTER_TYPE_D
);
2003 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2005 * This function should not be called on any value which may be 64 bits.
2006 * We could theoretically support 64-bit on gen8+ but we choose not to
2007 * because it wouldn't work in general (no gen7 support) and there are
2008 * enough restrictions in 64-bit immediates that you can't take the return
2009 * value and treat it the same as the result of get_nir_src().
2012 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2014 assert(nir_src_bit_size(src
) == 32);
2015 return nir_src_is_const(src
) ?
2016 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2020 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2023 const brw_reg_type reg_type
=
2024 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2025 dest
.ssa
.bit_size
== 8 ?
2026 BRW_REGISTER_TYPE_D
:
2027 BRW_REGISTER_TYPE_F
);
2028 nir_ssa_values
[dest
.ssa
.index
] =
2029 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2030 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2031 return nir_ssa_values
[dest
.ssa
.index
];
2033 /* We don't handle indirects on locals */
2034 assert(dest
.reg
.indirect
== NULL
);
2035 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2036 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2041 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2044 for (unsigned i
= 0; i
< 4; i
++) {
2045 if (!((wr_mask
>> i
) & 1))
2048 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2049 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2050 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2051 if (new_inst
->src
[j
].file
== VGRF
)
2052 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2059 emit_pixel_interpolater_send(const fs_builder
&bld
,
2064 glsl_interp_mode interpolation
)
2066 struct brw_wm_prog_data
*wm_prog_data
=
2067 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2069 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2070 /* 2 floats per slot returned */
2071 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2072 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2074 wm_prog_data
->pulls_bary
= true;
2080 * Computes 1 << x, given a D/UD register containing some value x.
2083 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2085 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2087 fs_reg result
= bld
.vgrf(x
.type
, 1);
2088 fs_reg one
= bld
.vgrf(x
.type
, 1);
2090 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2091 bld
.SHL(result
, one
, x
);
2096 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2098 assert(stage
== MESA_SHADER_GEOMETRY
);
2100 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2102 if (gs_compile
->control_data_header_size_bits
== 0)
2105 /* We can only do EndPrimitive() functionality when the control data
2106 * consists of cut bits. Fortunately, the only time it isn't is when the
2107 * output type is points, in which case EndPrimitive() is a no-op.
2109 if (gs_prog_data
->control_data_format
!=
2110 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2114 /* Cut bits use one bit per vertex. */
2115 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2117 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2118 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2120 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2121 * vertex n, 0 otherwise. So all we need to do here is mark bit
2122 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2123 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2124 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2126 * Note that if EndPrimitive() is called before emitting any vertices, this
2127 * will cause us to set bit 31 of the control_data_bits register to 1.
2128 * That's fine because:
2130 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2131 * output, so the hardware will ignore cut bit 31.
2133 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2134 * last vertex, so setting cut bit 31 has no effect (since the primitive
2135 * is automatically ended when the GS terminates).
2137 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2138 * control_data_bits register to 0 when the first vertex is emitted.
2141 const fs_builder abld
= bld
.annotate("end primitive");
2143 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2144 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2145 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2146 fs_reg mask
= intexp2(abld
, prev_count
);
2147 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2148 * attention to the lower 5 bits of its second source argument, so on this
2149 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2150 * ((vertex_count - 1) % 32).
2152 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2156 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2158 assert(stage
== MESA_SHADER_GEOMETRY
);
2159 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2161 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2163 const fs_builder abld
= bld
.annotate("emit control data bits");
2164 const fs_builder fwa_bld
= bld
.exec_all();
2166 /* We use a single UD register to accumulate control data bits (32 bits
2167 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2170 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2171 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2172 * use the Channel Mask phase to enable/disable which DWord within that
2173 * group to write. (Remember, different SIMD8 channels may have emitted
2174 * different numbers of vertices, so we may need per-slot offsets.)
2176 * Channel masking presents an annoying problem: we may have to replicate
2177 * the data up to 4 times:
2179 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2181 * To avoid penalizing shaders that emit a small number of vertices, we
2182 * can avoid these sometimes: if the size of the control data header is
2183 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2184 * land in the same 128-bit group, so we can skip per-slot offsets.
2186 * Similarly, if the control data header is <= 32 bits, there is only one
2187 * DWord, so we can skip channel masks.
2189 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2191 fs_reg channel_mask
, per_slot_offset
;
2193 if (gs_compile
->control_data_header_size_bits
> 32) {
2194 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2195 channel_mask
= vgrf(glsl_type::uint_type
);
2198 if (gs_compile
->control_data_header_size_bits
> 128) {
2199 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2200 per_slot_offset
= vgrf(glsl_type::uint_type
);
2203 /* Figure out which DWord we're trying to write to using the formula:
2205 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2207 * Since bits_per_vertex is a power of two, and is known at compile
2208 * time, this can be optimized to:
2210 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2212 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2213 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2214 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2215 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2216 unsigned log2_bits_per_vertex
=
2217 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2218 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2220 if (per_slot_offset
.file
!= BAD_FILE
) {
2221 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2222 * the appropriate OWord within the control data header.
2224 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2227 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2228 * write to the appropriate DWORD within the OWORD.
2230 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2231 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2232 channel_mask
= intexp2(fwa_bld
, channel
);
2233 /* Then the channel masks need to be in bits 23:16. */
2234 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2237 /* Store the control data bits in the message payload and send it. */
2239 if (channel_mask
.file
!= BAD_FILE
)
2240 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2241 if (per_slot_offset
.file
!= BAD_FILE
)
2244 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2245 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2247 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2248 if (per_slot_offset
.file
!= BAD_FILE
)
2249 sources
[i
++] = per_slot_offset
;
2250 if (channel_mask
.file
!= BAD_FILE
)
2251 sources
[i
++] = channel_mask
;
2253 sources
[i
++] = this->control_data_bits
;
2256 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2257 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2259 /* We need to increment Global Offset by 256-bits to make room for
2260 * Broadwell's extra "Vertex Count" payload at the beginning of the
2261 * URB entry. Since this is an OWord message, Global Offset is counted
2262 * in 128-bit units, so we must set it to 2.
2264 if (gs_prog_data
->static_vertex_count
== -1)
2269 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2272 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2274 /* Note: we are calling this *before* increasing vertex_count, so
2275 * this->vertex_count == vertex_count - 1 in the formula above.
2278 /* Stream mode uses 2 bits per vertex */
2279 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2281 /* Must be a valid stream */
2282 assert(stream_id
< MAX_VERTEX_STREAMS
);
2284 /* Control data bits are initialized to 0 so we don't have to set any
2285 * bits when sending vertices to stream 0.
2290 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2292 /* reg::sid = stream_id */
2293 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2294 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2296 /* reg:shift_count = 2 * (vertex_count - 1) */
2297 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2298 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2300 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2301 * attention to the lower 5 bits of its second source argument, so on this
2302 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2303 * stream_id << ((2 * (vertex_count - 1)) % 32).
2305 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2306 abld
.SHL(mask
, sid
, shift_count
);
2307 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2311 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2314 assert(stage
== MESA_SHADER_GEOMETRY
);
2316 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2318 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2319 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2321 /* Haswell and later hardware ignores the "Render Stream Select" bits
2322 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2323 * and instead sends all primitives down the pipeline for rasterization.
2324 * If the SOL stage is enabled, "Render Stream Select" is honored and
2325 * primitives bound to non-zero streams are discarded after stream output.
2327 * Since the only purpose of primives sent to non-zero streams is to
2328 * be recorded by transform feedback, we can simply discard all geometry
2329 * bound to these streams when transform feedback is disabled.
2331 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2334 /* If we're outputting 32 control data bits or less, then we can wait
2335 * until the shader is over to output them all. Otherwise we need to
2336 * output them as we go. Now is the time to do it, since we're about to
2337 * output the vertex_count'th vertex, so it's guaranteed that the
2338 * control data bits associated with the (vertex_count - 1)th vertex are
2341 if (gs_compile
->control_data_header_size_bits
> 32) {
2342 const fs_builder abld
=
2343 bld
.annotate("emit vertex: emit control data bits");
2345 /* Only emit control data bits if we've finished accumulating a batch
2346 * of 32 bits. This is the case when:
2348 * (vertex_count * bits_per_vertex) % 32 == 0
2350 * (in other words, when the last 5 bits of vertex_count *
2351 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2352 * integer n (which is always the case, since bits_per_vertex is
2353 * always 1 or 2), this is equivalent to requiring that the last 5-n
2354 * bits of vertex_count are 0:
2356 * vertex_count & (2^(5-n) - 1) == 0
2358 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2361 * vertex_count & (32 / bits_per_vertex - 1) == 0
2363 * TODO: If vertex_count is an immediate, we could do some of this math
2364 * at compile time...
2367 abld
.AND(bld
.null_reg_d(), vertex_count
,
2368 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2369 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2371 abld
.IF(BRW_PREDICATE_NORMAL
);
2372 /* If vertex_count is 0, then no control data bits have been
2373 * accumulated yet, so we can skip emitting them.
2375 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2376 BRW_CONDITIONAL_NEQ
);
2377 abld
.IF(BRW_PREDICATE_NORMAL
);
2378 emit_gs_control_data_bits(vertex_count
);
2379 abld
.emit(BRW_OPCODE_ENDIF
);
2381 /* Reset control_data_bits to 0 so we can start accumulating a new
2384 * Note: in the case where vertex_count == 0, this neutralizes the
2385 * effect of any call to EndPrimitive() that the shader may have
2386 * made before outputting its first vertex.
2388 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2389 inst
->force_writemask_all
= true;
2390 abld
.emit(BRW_OPCODE_ENDIF
);
2393 emit_urb_writes(vertex_count
);
2395 /* In stream mode we have to set control data bits for all vertices
2396 * unless we have disabled control data bits completely (which we do
2397 * do for GL_POINTS outputs that don't use streams).
2399 if (gs_compile
->control_data_header_size_bits
> 0 &&
2400 gs_prog_data
->control_data_format
==
2401 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2402 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2407 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2408 const nir_src
&vertex_src
,
2409 unsigned base_offset
,
2410 const nir_src
&offset_src
,
2411 unsigned num_components
,
2412 unsigned first_component
)
2414 assert(type_sz(dst
.type
) == 4);
2415 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2416 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2418 /* TODO: figure out push input layout for invocations == 1 */
2419 if (gs_prog_data
->invocations
== 1 &&
2420 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2421 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2422 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2423 nir_src_as_uint(vertex_src
) * push_reg_count
;
2424 for (unsigned i
= 0; i
< num_components
; i
++) {
2425 bld
.MOV(offset(dst
, bld
, i
),
2426 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2431 /* Resort to the pull model. Ensure the VUE handles are provided. */
2432 assert(gs_prog_data
->base
.include_vue_handles
);
2434 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2435 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2437 if (gs_prog_data
->invocations
== 1) {
2438 if (nir_src_is_const(vertex_src
)) {
2439 /* The vertex index is constant; just select the proper URB handle. */
2441 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2442 BRW_REGISTER_TYPE_UD
);
2444 /* The vertex index is non-constant. We need to use indirect
2445 * addressing to fetch the proper URB handle.
2447 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2448 * indicating that channel <n> should read the handle from
2449 * DWord <n>. We convert that to bytes by multiplying by 4.
2451 * Next, we convert the vertex index to bytes by multiplying
2452 * by 32 (shifting by 5), and add the two together. This is
2453 * the final indirect byte offset.
2455 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2456 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2457 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2458 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2460 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2461 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2462 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2463 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2464 /* Convert vertex_index to bytes (multiply by 32) */
2465 bld
.SHL(vertex_offset_bytes
,
2466 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2468 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2470 /* Use first_icp_handle as the base offset. There is one register
2471 * of URB handles per vertex, so inform the register allocator that
2472 * we might read up to nir->info.gs.vertices_in registers.
2474 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2475 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2476 fs_reg(icp_offset_bytes
),
2477 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2480 assert(gs_prog_data
->invocations
> 1);
2482 if (nir_src_is_const(vertex_src
)) {
2483 unsigned vertex
= nir_src_as_uint(vertex_src
);
2484 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2486 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2487 BRW_REGISTER_TYPE_UD
));
2489 /* The vertex index is non-constant. We need to use indirect
2490 * addressing to fetch the proper URB handle.
2493 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2495 /* Convert vertex_index to bytes (multiply by 4) */
2496 bld
.SHL(icp_offset_bytes
,
2497 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2500 /* Use first_icp_handle as the base offset. There is one DWord
2501 * of URB handles per vertex, so inform the register allocator that
2502 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2504 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2505 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2506 fs_reg(icp_offset_bytes
),
2507 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2513 fs_reg indirect_offset
= get_nir_src(offset_src
);
2515 if (nir_src_is_const(offset_src
)) {
2516 /* Constant indexing - use global offset. */
2517 if (first_component
!= 0) {
2518 unsigned read_components
= num_components
+ first_component
;
2519 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2520 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2521 inst
->size_written
= read_components
*
2522 tmp
.component_size(inst
->exec_size
);
2523 for (unsigned i
= 0; i
< num_components
; i
++) {
2524 bld
.MOV(offset(dst
, bld
, i
),
2525 offset(tmp
, bld
, i
+ first_component
));
2528 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2529 inst
->size_written
= num_components
*
2530 dst
.component_size(inst
->exec_size
);
2532 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2535 /* Indirect indexing - use per-slot offsets as well. */
2536 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2537 unsigned read_components
= num_components
+ first_component
;
2538 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2539 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2540 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2541 if (first_component
!= 0) {
2542 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2544 inst
->size_written
= read_components
*
2545 tmp
.component_size(inst
->exec_size
);
2546 for (unsigned i
= 0; i
< num_components
; i
++) {
2547 bld
.MOV(offset(dst
, bld
, i
),
2548 offset(tmp
, bld
, i
+ first_component
));
2551 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2552 inst
->size_written
= num_components
*
2553 dst
.component_size(inst
->exec_size
);
2555 inst
->offset
= base_offset
;
2561 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2563 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2565 if (nir_src_is_const(*offset_src
)) {
2566 /* The only constant offset we should find is 0. brw_nir.c's
2567 * add_const_offset_to_base() will fold other constant offsets
2568 * into instr->const_index[0].
2570 assert(nir_src_as_uint(*offset_src
) == 0);
2574 return get_nir_src(*offset_src
);
2578 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2579 nir_intrinsic_instr
*instr
)
2581 assert(stage
== MESA_SHADER_VERTEX
);
2584 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2585 dest
= get_nir_dest(instr
->dest
);
2587 switch (instr
->intrinsic
) {
2588 case nir_intrinsic_load_vertex_id
:
2589 case nir_intrinsic_load_base_vertex
:
2590 unreachable("should be lowered by nir_lower_system_values()");
2592 case nir_intrinsic_load_input
: {
2593 assert(nir_dest_bit_size(instr
->dest
) == 32);
2594 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2595 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2596 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2598 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2599 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2603 case nir_intrinsic_load_vertex_id_zero_base
:
2604 case nir_intrinsic_load_instance_id
:
2605 case nir_intrinsic_load_base_instance
:
2606 case nir_intrinsic_load_draw_id
:
2607 case nir_intrinsic_load_first_vertex
:
2608 case nir_intrinsic_load_is_indexed_draw
:
2609 unreachable("lowered by brw_nir_lower_vs_inputs");
2612 nir_emit_intrinsic(bld
, instr
);
2618 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2619 nir_intrinsic_instr
*instr
)
2621 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2622 const nir_src
&vertex_src
= instr
->src
[0];
2623 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2626 if (nir_src_is_const(vertex_src
)) {
2627 /* Emit a MOV to resolve <0,1,0> regioning. */
2628 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2629 unsigned vertex
= nir_src_as_uint(vertex_src
);
2631 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2632 BRW_REGISTER_TYPE_UD
));
2633 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2634 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2635 /* For the common case of only 1 instance, an array index of
2636 * gl_InvocationID means reading g1. Skip all the indirect work.
2638 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2640 /* The vertex index is non-constant. We need to use indirect
2641 * addressing to fetch the proper URB handle.
2643 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2645 /* Each ICP handle is a single DWord (4 bytes) */
2646 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2647 bld
.SHL(vertex_offset_bytes
,
2648 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2651 /* Start at g1. We might read up to 4 registers. */
2652 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2653 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2654 brw_imm_ud(4 * REG_SIZE
));
2661 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2662 nir_intrinsic_instr
*instr
)
2664 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2665 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2666 const nir_src
&vertex_src
= instr
->src
[0];
2668 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2670 if (nir_src_is_const(vertex_src
)) {
2671 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2672 nir_src_as_uint(vertex_src
), 0),
2673 BRW_REGISTER_TYPE_UD
));
2676 /* The vertex index is non-constant. We need to use indirect
2677 * addressing to fetch the proper URB handle.
2679 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2680 * indicating that channel <n> should read the handle from
2681 * DWord <n>. We convert that to bytes by multiplying by 4.
2683 * Next, we convert the vertex index to bytes by multiplying
2684 * by 32 (shifting by 5), and add the two together. This is
2685 * the final indirect byte offset.
2687 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2688 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2689 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2690 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2691 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2693 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2694 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2695 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2696 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2697 /* Convert vertex_index to bytes (multiply by 32) */
2698 bld
.SHL(vertex_offset_bytes
,
2699 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2701 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2703 /* Use first_icp_handle as the base offset. There is one register
2704 * of URB handles per vertex, so inform the register allocator that
2705 * we might read up to nir->info.gs.vertices_in registers.
2707 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2708 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2709 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2715 fs_visitor::get_tcs_output_urb_handle()
2717 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2719 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2720 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2722 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2723 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2728 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2729 nir_intrinsic_instr
*instr
)
2731 assert(stage
== MESA_SHADER_TESS_CTRL
);
2732 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2733 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2734 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2737 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2740 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2741 dst
= get_nir_dest(instr
->dest
);
2743 switch (instr
->intrinsic
) {
2744 case nir_intrinsic_load_primitive_id
:
2745 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2746 : brw_vec1_grf(0, 1)));
2748 case nir_intrinsic_load_invocation_id
:
2749 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2751 case nir_intrinsic_load_patch_vertices_in
:
2752 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2753 brw_imm_d(tcs_key
->input_vertices
));
2756 case nir_intrinsic_control_barrier
: {
2757 if (tcs_prog_data
->instances
== 1)
2760 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2761 fs_reg m0_2
= component(m0
, 2);
2763 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2765 /* Zero the message header */
2766 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2768 if (devinfo
->gen
< 11) {
2769 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2770 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2771 brw_imm_ud(INTEL_MASK(16, 13)));
2773 /* Shift it up to bits 27:24. */
2774 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2776 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2777 brw_imm_ud(INTEL_MASK(30, 24)));
2780 /* Set the Barrier Count and the enable bit */
2781 if (devinfo
->gen
< 11) {
2782 chanbld
.OR(m0_2
, m0_2
,
2783 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2785 chanbld
.OR(m0_2
, m0_2
,
2786 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2789 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2793 case nir_intrinsic_load_input
:
2794 unreachable("nir_lower_io should never give us these.");
2797 case nir_intrinsic_load_per_vertex_input
: {
2798 assert(nir_dest_bit_size(instr
->dest
) == 32);
2799 fs_reg indirect_offset
= get_indirect_offset(instr
);
2800 unsigned imm_offset
= instr
->const_index
[0];
2804 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2805 : get_tcs_single_patch_icp_handle(bld
, instr
);
2807 /* We can only read two double components with each URB read, so
2808 * we send two read messages in that case, each one loading up to
2809 * two double components.
2811 unsigned num_components
= instr
->num_components
;
2812 unsigned first_component
= nir_intrinsic_component(instr
);
2814 if (indirect_offset
.file
== BAD_FILE
) {
2815 /* Constant indexing - use global offset. */
2816 if (first_component
!= 0) {
2817 unsigned read_components
= num_components
+ first_component
;
2818 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2819 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2820 for (unsigned i
= 0; i
< num_components
; i
++) {
2821 bld
.MOV(offset(dst
, bld
, i
),
2822 offset(tmp
, bld
, i
+ first_component
));
2825 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2827 inst
->offset
= imm_offset
;
2830 /* Indirect indexing - use per-slot offsets as well. */
2831 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2832 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2833 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2834 if (first_component
!= 0) {
2835 unsigned read_components
= num_components
+ first_component
;
2836 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2837 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2839 for (unsigned i
= 0; i
< num_components
; i
++) {
2840 bld
.MOV(offset(dst
, bld
, i
),
2841 offset(tmp
, bld
, i
+ first_component
));
2844 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2847 inst
->offset
= imm_offset
;
2850 inst
->size_written
= (num_components
+ first_component
) *
2851 inst
->dst
.component_size(inst
->exec_size
);
2853 /* Copy the temporary to the destination to deal with writemasking.
2855 * Also attempt to deal with gl_PointSize being in the .w component.
2857 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2858 assert(type_sz(dst
.type
) == 4);
2859 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2860 inst
->size_written
= 4 * REG_SIZE
;
2861 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2866 case nir_intrinsic_load_output
:
2867 case nir_intrinsic_load_per_vertex_output
: {
2868 assert(nir_dest_bit_size(instr
->dest
) == 32);
2869 fs_reg indirect_offset
= get_indirect_offset(instr
);
2870 unsigned imm_offset
= instr
->const_index
[0];
2871 unsigned first_component
= nir_intrinsic_component(instr
);
2873 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2876 if (indirect_offset
.file
== BAD_FILE
) {
2877 /* This MOV replicates the output handle to all enabled channels
2878 * is SINGLE_PATCH mode.
2880 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2881 bld
.MOV(patch_handle
, output_handles
);
2884 if (first_component
!= 0) {
2885 unsigned read_components
=
2886 instr
->num_components
+ first_component
;
2887 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2888 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2890 inst
->size_written
= read_components
* REG_SIZE
;
2891 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2892 bld
.MOV(offset(dst
, bld
, i
),
2893 offset(tmp
, bld
, i
+ first_component
));
2896 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2898 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2900 inst
->offset
= imm_offset
;
2904 /* Indirect indexing - use per-slot offsets as well. */
2905 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2906 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2907 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2908 if (first_component
!= 0) {
2909 unsigned read_components
=
2910 instr
->num_components
+ first_component
;
2911 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2912 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2914 inst
->size_written
= read_components
* REG_SIZE
;
2915 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2916 bld
.MOV(offset(dst
, bld
, i
),
2917 offset(tmp
, bld
, i
+ first_component
));
2920 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2922 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2924 inst
->offset
= imm_offset
;
2930 case nir_intrinsic_store_output
:
2931 case nir_intrinsic_store_per_vertex_output
: {
2932 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2933 fs_reg value
= get_nir_src(instr
->src
[0]);
2934 fs_reg indirect_offset
= get_indirect_offset(instr
);
2935 unsigned imm_offset
= instr
->const_index
[0];
2936 unsigned mask
= instr
->const_index
[1];
2937 unsigned header_regs
= 0;
2938 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2941 srcs
[header_regs
++] = output_handles
;
2943 if (indirect_offset
.file
!= BAD_FILE
) {
2944 srcs
[header_regs
++] = indirect_offset
;
2950 unsigned num_components
= util_last_bit(mask
);
2953 /* We can only pack two 64-bit components in a single message, so send
2954 * 2 messages if we have more components
2956 unsigned first_component
= nir_intrinsic_component(instr
);
2957 mask
= mask
<< first_component
;
2959 if (mask
!= WRITEMASK_XYZW
) {
2960 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2961 opcode
= indirect_offset
.file
!= BAD_FILE
?
2962 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2963 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2965 opcode
= indirect_offset
.file
!= BAD_FILE
?
2966 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2967 SHADER_OPCODE_URB_WRITE_SIMD8
;
2970 for (unsigned i
= 0; i
< num_components
; i
++) {
2971 if (!(mask
& (1 << (i
+ first_component
))))
2974 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2977 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2979 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2980 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2982 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2983 inst
->offset
= imm_offset
;
2989 nir_emit_intrinsic(bld
, instr
);
2995 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2996 nir_intrinsic_instr
*instr
)
2998 assert(stage
== MESA_SHADER_TESS_EVAL
);
2999 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3002 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3003 dest
= get_nir_dest(instr
->dest
);
3005 switch (instr
->intrinsic
) {
3006 case nir_intrinsic_load_primitive_id
:
3007 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3009 case nir_intrinsic_load_tess_coord
:
3010 /* gl_TessCoord is part of the payload in g1-3 */
3011 for (unsigned i
= 0; i
< 3; i
++) {
3012 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3016 case nir_intrinsic_load_input
:
3017 case nir_intrinsic_load_per_vertex_input
: {
3018 assert(nir_dest_bit_size(instr
->dest
) == 32);
3019 fs_reg indirect_offset
= get_indirect_offset(instr
);
3020 unsigned imm_offset
= instr
->const_index
[0];
3021 unsigned first_component
= nir_intrinsic_component(instr
);
3024 if (indirect_offset
.file
== BAD_FILE
) {
3025 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3026 * which is 16 registers (since each holds 2 vec4 slots).
3028 const unsigned max_push_slots
= 32;
3029 if (imm_offset
< max_push_slots
) {
3030 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3031 for (int i
= 0; i
< instr
->num_components
; i
++) {
3032 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3033 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3036 tes_prog_data
->base
.urb_read_length
=
3037 MAX2(tes_prog_data
->base
.urb_read_length
,
3038 (imm_offset
/ 2) + 1);
3040 /* Replicate the patch handle to all enabled channels */
3041 const fs_reg srcs
[] = {
3042 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3044 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3045 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3047 if (first_component
!= 0) {
3048 unsigned read_components
=
3049 instr
->num_components
+ first_component
;
3050 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3051 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3053 inst
->size_written
= read_components
* REG_SIZE
;
3054 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3055 bld
.MOV(offset(dest
, bld
, i
),
3056 offset(tmp
, bld
, i
+ first_component
));
3059 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3061 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3064 inst
->offset
= imm_offset
;
3067 /* Indirect indexing - use per-slot offsets as well. */
3069 /* We can only read two double components with each URB read, so
3070 * we send two read messages in that case, each one loading up to
3071 * two double components.
3073 unsigned num_components
= instr
->num_components
;
3074 const fs_reg srcs
[] = {
3075 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3078 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3079 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3081 if (first_component
!= 0) {
3082 unsigned read_components
=
3083 num_components
+ first_component
;
3084 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3085 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3087 for (unsigned i
= 0; i
< num_components
; i
++) {
3088 bld
.MOV(offset(dest
, bld
, i
),
3089 offset(tmp
, bld
, i
+ first_component
));
3092 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3096 inst
->offset
= imm_offset
;
3097 inst
->size_written
= (num_components
+ first_component
) *
3098 inst
->dst
.component_size(inst
->exec_size
);
3103 nir_emit_intrinsic(bld
, instr
);
3109 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3110 nir_intrinsic_instr
*instr
)
3112 assert(stage
== MESA_SHADER_GEOMETRY
);
3113 fs_reg indirect_offset
;
3116 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3117 dest
= get_nir_dest(instr
->dest
);
3119 switch (instr
->intrinsic
) {
3120 case nir_intrinsic_load_primitive_id
:
3121 assert(stage
== MESA_SHADER_GEOMETRY
);
3122 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3123 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3124 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3127 case nir_intrinsic_load_input
:
3128 unreachable("load_input intrinsics are invalid for the GS stage");
3130 case nir_intrinsic_load_per_vertex_input
:
3131 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3132 instr
->src
[1], instr
->num_components
,
3133 nir_intrinsic_component(instr
));
3136 case nir_intrinsic_emit_vertex_with_counter
:
3137 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3140 case nir_intrinsic_end_primitive_with_counter
:
3141 emit_gs_end_primitive(instr
->src
[0]);
3144 case nir_intrinsic_set_vertex_count
:
3145 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3148 case nir_intrinsic_load_invocation_id
: {
3149 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3150 assert(val
.file
!= BAD_FILE
);
3151 dest
.type
= val
.type
;
3157 nir_emit_intrinsic(bld
, instr
);
3163 * Fetch the current render target layer index.
3166 fetch_render_target_array_index(const fs_builder
&bld
)
3168 if (bld
.shader
->devinfo
->gen
>= 12) {
3169 /* The render target array index is provided in the thread payload as
3170 * bits 26:16 of r1.1.
3172 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3173 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 1, 3),
3176 } else if (bld
.shader
->devinfo
->gen
>= 6) {
3177 /* The render target array index is provided in the thread payload as
3178 * bits 26:16 of r0.0.
3180 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3181 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3185 /* Pre-SNB we only ever render into the first layer of the framebuffer
3186 * since layered rendering is not implemented.
3188 return brw_imm_ud(0);
3193 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3194 * framebuffer at the current fragment coordinates and sample index.
3197 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3200 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3202 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3203 const brw_wm_prog_key
*wm_key
=
3204 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3205 assert(!wm_key
->coherent_fb_fetch
);
3206 const struct brw_wm_prog_data
*wm_prog_data
=
3207 brw_wm_prog_data(stage_prog_data
);
3209 /* Calculate the surface index relative to the start of the texture binding
3210 * table block, since that's what the texturing messages expect.
3212 const unsigned surface
= target
+
3213 wm_prog_data
->binding_table
.render_target_read_start
-
3214 wm_prog_data
->base
.binding_table
.texture_start
;
3216 /* Calculate the fragment coordinates. */
3217 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3218 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3219 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3220 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3222 /* Calculate the sample index and MCS payload when multisampling. Luckily
3223 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3224 * shouldn't be necessary to recompile based on whether the framebuffer is
3227 if (wm_key
->multisample_fbo
&&
3228 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3229 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3231 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3232 const fs_reg mcs
= wm_key
->multisample_fbo
?
3233 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3235 /* Use either a normal or a CMS texel fetch message depending on whether
3236 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3237 * message just in case the framebuffer uses 16x multisampling, it should
3238 * be equivalent to the normal CMS fetch for lower multisampling modes.
3240 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3241 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3242 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3244 /* Emit the instruction. */
3245 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3246 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3247 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3248 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3249 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3250 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3251 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3252 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3253 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3255 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3256 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3262 * Actual coherent framebuffer read implemented using the native render target
3263 * read message. Requires SKL+.
3266 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3268 assert(bld
.shader
->devinfo
->gen
>= 9);
3269 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3270 inst
->target
= target
;
3271 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3277 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3279 if (n
&& regs
[0].file
!= BAD_FILE
) {
3283 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3285 for (unsigned i
= 0; i
< n
; i
++)
3293 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3295 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3296 const brw_wm_prog_key
*const key
=
3297 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3298 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3299 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3301 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3302 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3304 else if (l
== FRAG_RESULT_COLOR
)
3305 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3306 MAX2(key
->nr_color_regions
, 1));
3308 else if (l
== FRAG_RESULT_DEPTH
)
3309 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3311 else if (l
== FRAG_RESULT_STENCIL
)
3312 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3314 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3315 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3317 else if (l
>= FRAG_RESULT_DATA0
&&
3318 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3319 return alloc_temporary(v
->bld
, 4,
3320 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3323 unreachable("Invalid location");
3327 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3328 nir_intrinsic_instr
*instr
)
3330 assert(stage
== MESA_SHADER_FRAGMENT
);
3333 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3334 dest
= get_nir_dest(instr
->dest
);
3336 switch (instr
->intrinsic
) {
3337 case nir_intrinsic_load_front_face
:
3338 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3339 *emit_frontfacing_interpolation());
3342 case nir_intrinsic_load_sample_pos
: {
3343 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3344 assert(sample_pos
.file
!= BAD_FILE
);
3345 dest
.type
= sample_pos
.type
;
3346 bld
.MOV(dest
, sample_pos
);
3347 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3351 case nir_intrinsic_load_layer_id
:
3352 dest
.type
= BRW_REGISTER_TYPE_UD
;
3353 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3356 case nir_intrinsic_is_helper_invocation
: {
3357 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3358 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3359 * consideration demoted invocations. That information is stored in
3362 dest
.type
= BRW_REGISTER_TYPE_UD
;
3364 bld
.MOV(dest
, brw_imm_ud(0));
3366 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3367 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3368 mov
->predicate_inverse
= true;
3369 mov
->flag_subreg
= sample_mask_flag_subreg(this);
3373 case nir_intrinsic_load_helper_invocation
:
3374 case nir_intrinsic_load_sample_mask_in
:
3375 case nir_intrinsic_load_sample_id
: {
3376 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3377 fs_reg val
= nir_system_values
[sv
];
3378 assert(val
.file
!= BAD_FILE
);
3379 dest
.type
= val
.type
;
3384 case nir_intrinsic_store_output
: {
3385 const fs_reg src
= get_nir_src(instr
->src
[0]);
3386 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3387 const unsigned location
= nir_intrinsic_base(instr
) +
3388 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3389 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3392 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3393 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3394 offset(src
, bld
, j
));
3399 case nir_intrinsic_load_output
: {
3400 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3401 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3402 assert(l
>= FRAG_RESULT_DATA0
);
3403 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3404 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3405 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3407 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3408 emit_coherent_fb_read(bld
, tmp
, target
);
3410 emit_non_coherent_fb_read(bld
, tmp
, target
);
3412 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3413 bld
.MOV(offset(dest
, bld
, j
),
3414 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3420 case nir_intrinsic_demote
:
3421 case nir_intrinsic_discard
:
3422 case nir_intrinsic_demote_if
:
3423 case nir_intrinsic_discard_if
: {
3424 /* We track our discarded pixels in f0.1/f1.0. By predicating on it, we
3425 * can update just the flag bits that aren't yet discarded. If there's
3426 * no condition, we emit a CMP of g0 != g0, so all currently executing
3427 * channels will get turned off.
3429 fs_inst
*cmp
= NULL
;
3430 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3431 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3432 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3435 alu
->op
!= nir_op_bcsel
&&
3436 (devinfo
->gen
> 5 ||
3437 (alu
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE
||
3438 alu
->op
== nir_op_fneu32
|| alu
->op
== nir_op_feq32
||
3439 alu
->op
== nir_op_flt32
|| alu
->op
== nir_op_fge32
||
3440 alu
->op
== nir_op_ine32
|| alu
->op
== nir_op_ieq32
||
3441 alu
->op
== nir_op_ilt32
|| alu
->op
== nir_op_ige32
||
3442 alu
->op
== nir_op_ult32
|| alu
->op
== nir_op_uge32
)) {
3443 /* Re-emit the instruction that generated the Boolean value, but
3444 * do not store it. Since this instruction will be conditional,
3445 * other instructions that want to use the real Boolean value may
3446 * get garbage. This was a problem for piglit's fs-discard-exit-2
3449 * Ideally we'd detect that the instruction cannot have a
3450 * conditional modifier before emitting the instructions. Alas,
3451 * that is nigh impossible. Instead, we're going to assume the
3452 * instruction (or last instruction) generated can have a
3453 * conditional modifier. If it cannot, fallback to the old-style
3454 * compare, and hope dead code elimination will clean up the
3455 * extra instructions generated.
3457 nir_emit_alu(bld
, alu
, false);
3459 cmp
= (fs_inst
*) instructions
.get_tail();
3460 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3461 if (cmp
->can_do_cmod())
3462 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3466 /* The old sequence that would have been generated is,
3467 * basically, bool_result == false. This is equivalent to
3468 * !bool_result, so negate the old modifier.
3470 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3475 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3476 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3479 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3480 BRW_REGISTER_TYPE_UW
));
3481 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3484 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3485 cmp
->flag_subreg
= sample_mask_flag_subreg(this);
3487 emit_discard_jump();
3489 if (devinfo
->gen
< 7)
3490 limit_dispatch_width(
3491 16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
3495 case nir_intrinsic_load_input
: {
3496 /* load_input is only used for flat inputs */
3497 assert(nir_dest_bit_size(instr
->dest
) == 32);
3498 unsigned base
= nir_intrinsic_base(instr
);
3499 unsigned comp
= nir_intrinsic_component(instr
);
3500 unsigned num_components
= instr
->num_components
;
3502 /* Special case fields in the VUE header */
3503 if (base
== VARYING_SLOT_LAYER
)
3505 else if (base
== VARYING_SLOT_VIEWPORT
)
3508 for (unsigned int i
= 0; i
< num_components
; i
++) {
3509 bld
.MOV(offset(dest
, bld
, i
),
3510 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3515 case nir_intrinsic_load_fs_input_interp_deltas
: {
3516 assert(stage
== MESA_SHADER_FRAGMENT
);
3517 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3518 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3519 nir_intrinsic_component(instr
));
3520 dest
.type
= BRW_REGISTER_TYPE_F
;
3521 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3522 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3523 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3527 case nir_intrinsic_load_barycentric_pixel
:
3528 case nir_intrinsic_load_barycentric_centroid
:
3529 case nir_intrinsic_load_barycentric_sample
: {
3530 /* Use the delta_xy values computed from the payload */
3531 const glsl_interp_mode interp_mode
=
3532 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3533 enum brw_barycentric_mode bary
=
3534 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3535 const fs_reg srcs
[] = { offset(this->delta_xy
[bary
], bld
, 0),
3536 offset(this->delta_xy
[bary
], bld
, 1) };
3537 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3541 case nir_intrinsic_load_barycentric_at_sample
: {
3542 const glsl_interp_mode interpolation
=
3543 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3545 if (nir_src_is_const(instr
->src
[0])) {
3546 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3548 emit_pixel_interpolater_send(bld
,
3549 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3552 brw_imm_ud(msg_data
),
3555 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3556 BRW_REGISTER_TYPE_UD
);
3558 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3559 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3560 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3561 bld
.exec_all().group(1, 0)
3562 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3563 emit_pixel_interpolater_send(bld
,
3564 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3567 component(msg_data
, 0),
3570 /* Make a loop that sends a message to the pixel interpolater
3571 * for the sample number in each live channel. If there are
3572 * multiple channels with the same sample number then these
3573 * will be handled simultaneously with a single interation of
3576 bld
.emit(BRW_OPCODE_DO
);
3578 /* Get the next live sample number into sample_id_reg */
3579 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3581 /* Set the flag register so that we can perform the send
3582 * message on all channels that have the same sample number
3584 bld
.CMP(bld
.null_reg_ud(),
3585 sample_src
, sample_id
,
3586 BRW_CONDITIONAL_EQ
);
3587 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3588 bld
.exec_all().group(1, 0)
3589 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3591 emit_pixel_interpolater_send(bld
,
3592 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3595 component(msg_data
, 0),
3597 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3599 /* Continue the loop if there are any live channels left */
3600 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3602 bld
.emit(BRW_OPCODE_WHILE
));
3608 case nir_intrinsic_load_barycentric_at_offset
: {
3609 const glsl_interp_mode interpolation
=
3610 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3612 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3615 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3616 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3617 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3619 emit_pixel_interpolater_send(bld
,
3620 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3623 brw_imm_ud(off_x
| (off_y
<< 4)),
3626 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3627 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3628 BRW_REGISTER_TYPE_F
);
3629 for (int i
= 0; i
< 2; i
++) {
3630 fs_reg temp
= vgrf(glsl_type::float_type
);
3631 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3632 fs_reg itemp
= vgrf(glsl_type::int_type
);
3634 bld
.MOV(itemp
, temp
);
3636 /* Clamp the upper end of the range to +7/16.
3637 * ARB_gpu_shader5 requires that we support a maximum offset
3638 * of +0.5, which isn't representable in a S0.4 value -- if
3639 * we didn't clamp it, we'd end up with -8/16, which is the
3640 * opposite of what the shader author wanted.
3642 * This is legal due to ARB_gpu_shader5's quantization
3645 * "Not all values of <offset> may be supported; x and y
3646 * offsets may be rounded to fixed-point values with the
3647 * number of fraction bits given by the
3648 * implementation-dependent constant
3649 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3651 set_condmod(BRW_CONDITIONAL_L
,
3652 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3655 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3656 emit_pixel_interpolater_send(bld
,
3666 case nir_intrinsic_load_frag_coord
:
3667 emit_fragcoord_interpolation(dest
);
3670 case nir_intrinsic_load_interpolated_input
: {
3671 assert(instr
->src
[0].ssa
&&
3672 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3673 nir_intrinsic_instr
*bary_intrinsic
=
3674 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3675 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3676 enum glsl_interp_mode interp_mode
=
3677 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3680 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3681 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3682 /* Use the result of the PI message. */
3683 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3685 /* Use the delta_xy values computed from the payload */
3686 enum brw_barycentric_mode bary
=
3687 brw_barycentric_mode(interp_mode
, bary_intrin
);
3688 dst_xy
= this->delta_xy
[bary
];
3691 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3693 component(interp_reg(nir_intrinsic_base(instr
),
3694 nir_intrinsic_component(instr
) + i
), 0);
3695 interp
.type
= BRW_REGISTER_TYPE_F
;
3696 dest
.type
= BRW_REGISTER_TYPE_F
;
3698 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3699 fs_reg tmp
= vgrf(glsl_type::float_type
);
3700 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3701 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3703 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3710 nir_emit_intrinsic(bld
, instr
);
3716 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3717 nir_intrinsic_instr
*instr
)
3719 assert(stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
);
3720 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3723 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3724 dest
= get_nir_dest(instr
->dest
);
3726 switch (instr
->intrinsic
) {
3727 case nir_intrinsic_control_barrier
:
3728 /* The whole workgroup fits in a single HW thread, so all the
3729 * invocations are already executed lock-step. Instead of an actual
3730 * barrier just emit a scheduling fence, that will generate no code.
3732 if (!nir
->info
.cs
.local_size_variable
&&
3733 workgroup_size() <= dispatch_width
) {
3734 bld
.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE
);
3739 cs_prog_data
->uses_barrier
= true;
3742 case nir_intrinsic_load_subgroup_id
:
3743 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3746 case nir_intrinsic_load_local_invocation_id
:
3747 case nir_intrinsic_load_work_group_id
: {
3748 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3749 fs_reg val
= nir_system_values
[sv
];
3750 assert(val
.file
!= BAD_FILE
);
3751 dest
.type
= val
.type
;
3752 for (unsigned i
= 0; i
< 3; i
++)
3753 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3757 case nir_intrinsic_load_num_work_groups
: {
3758 const unsigned surface
=
3759 cs_prog_data
->binding_table
.work_groups_start
;
3761 cs_prog_data
->uses_num_work_groups
= true;
3763 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3764 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3765 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3766 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3768 /* Read the 3 GLuint components of gl_NumWorkGroups */
3769 for (unsigned i
= 0; i
< 3; i
++) {
3770 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3771 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3772 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3777 case nir_intrinsic_shared_atomic_add
:
3778 case nir_intrinsic_shared_atomic_imin
:
3779 case nir_intrinsic_shared_atomic_umin
:
3780 case nir_intrinsic_shared_atomic_imax
:
3781 case nir_intrinsic_shared_atomic_umax
:
3782 case nir_intrinsic_shared_atomic_and
:
3783 case nir_intrinsic_shared_atomic_or
:
3784 case nir_intrinsic_shared_atomic_xor
:
3785 case nir_intrinsic_shared_atomic_exchange
:
3786 case nir_intrinsic_shared_atomic_comp_swap
:
3787 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3789 case nir_intrinsic_shared_atomic_fmin
:
3790 case nir_intrinsic_shared_atomic_fmax
:
3791 case nir_intrinsic_shared_atomic_fcomp_swap
:
3792 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3795 case nir_intrinsic_load_shared
: {
3796 assert(devinfo
->gen
>= 7);
3797 assert(stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
);
3799 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3800 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3801 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3802 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3803 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3805 /* Make dest unsigned because that's what the temporary will be */
3806 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3808 /* Read the vector */
3809 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3810 assert(nir_intrinsic_align(instr
) > 0);
3811 if (nir_dest_bit_size(instr
->dest
) == 32 &&
3812 nir_intrinsic_align(instr
) >= 4) {
3813 assert(nir_dest_num_components(instr
->dest
) <= 4);
3814 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3816 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3817 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3818 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3820 assert(nir_dest_num_components(instr
->dest
) == 1);
3821 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3823 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3824 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3825 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3826 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3831 case nir_intrinsic_store_shared
: {
3832 assert(devinfo
->gen
>= 7);
3833 assert(stage
== MESA_SHADER_COMPUTE
|| stage
== MESA_SHADER_KERNEL
);
3835 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3836 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3837 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3838 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3839 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3841 fs_reg data
= get_nir_src(instr
->src
[0]);
3842 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3844 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3845 assert(nir_intrinsic_write_mask(instr
) ==
3846 (1u << instr
->num_components
) - 1);
3847 assert(nir_intrinsic_align(instr
) > 0);
3848 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
3849 nir_intrinsic_align(instr
) >= 4) {
3850 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3851 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3852 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3853 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3854 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3856 assert(nir_src_num_components(instr
->src
[0]) == 1);
3857 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3859 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3860 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3862 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3863 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3868 case nir_intrinsic_load_local_group_size
: {
3869 assert(compiler
->lower_variable_group_size
);
3870 assert(nir
->info
.cs
.local_size_variable
);
3871 for (unsigned i
= 0; i
< 3; i
++) {
3872 bld
.MOV(retype(offset(dest
, bld
, i
), BRW_REGISTER_TYPE_UD
),
3879 nir_emit_intrinsic(bld
, instr
);
3885 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3886 nir_op op
, brw_reg_type type
)
3888 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3889 switch (type_sz(type
)) {
3891 if (type
== BRW_REGISTER_TYPE_UB
) {
3892 return brw_imm_uw(value
.u8
);
3894 assert(type
== BRW_REGISTER_TYPE_B
);
3895 return brw_imm_w(value
.i8
);
3898 return retype(brw_imm_uw(value
.u16
), type
);
3900 return retype(brw_imm_ud(value
.u32
), type
);
3902 if (type
== BRW_REGISTER_TYPE_DF
)
3903 return setup_imm_df(bld
, value
.f64
);
3905 return retype(brw_imm_u64(value
.u64
), type
);
3907 unreachable("Invalid type size");
3912 brw_op_for_nir_reduction_op(nir_op op
)
3915 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3916 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3917 case nir_op_imul
: return BRW_OPCODE_MUL
;
3918 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3919 case nir_op_imin
: return BRW_OPCODE_SEL
;
3920 case nir_op_umin
: return BRW_OPCODE_SEL
;
3921 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3922 case nir_op_imax
: return BRW_OPCODE_SEL
;
3923 case nir_op_umax
: return BRW_OPCODE_SEL
;
3924 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3925 case nir_op_iand
: return BRW_OPCODE_AND
;
3926 case nir_op_ior
: return BRW_OPCODE_OR
;
3927 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3929 unreachable("Invalid reduction operation");
3933 static brw_conditional_mod
3934 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3937 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3938 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3939 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3940 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3941 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3942 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3943 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3944 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3945 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3946 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3947 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3948 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3949 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3951 unreachable("Invalid reduction operation");
3956 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3957 nir_intrinsic_instr
*instr
)
3959 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3960 fs_reg surf_index
= image
;
3962 if (stage_prog_data
->binding_table
.image_start
> 0) {
3963 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3965 brw_imm_ud(image
.d
+ stage_prog_data
->binding_table
.image_start
);
3967 surf_index
= vgrf(glsl_type::uint_type
);
3968 bld
.ADD(surf_index
, image
,
3969 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3973 return bld
.emit_uniformize(surf_index
);
3977 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3978 nir_intrinsic_instr
*instr
)
3980 /* SSBO stores are weird in that their index is in src[1] */
3981 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3984 if (nir_src_is_const(instr
->src
[src
])) {
3985 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3986 nir_src_as_uint(instr
->src
[src
]);
3987 surf_index
= brw_imm_ud(index
);
3989 surf_index
= vgrf(glsl_type::uint_type
);
3990 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3991 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3994 return bld
.emit_uniformize(surf_index
);
3998 * The offsets we get from NIR act as if each SIMD channel has it's own blob
3999 * of contiguous space. However, if we actually place each SIMD channel in
4000 * it's own space, we end up with terrible cache performance because each SIMD
4001 * channel accesses a different cache line even when they're all accessing the
4002 * same byte offset. To deal with this problem, we swizzle the address using
4003 * a simple algorithm which ensures that any time a SIMD message reads or
4004 * writes the same address, it's all in the same cache line. We have to keep
4005 * the bottom two bits fixed so that we can read/write up to a dword at a time
4006 * and the individual element is contiguous. We do this by splitting the
4007 * address as follows:
4010 * +-------------------------------+------------+----------+
4011 * | Hi address bits | chan index | addr low |
4012 * +-------------------------------+------------+----------+
4014 * In other words, the bottom two address bits stay, and the top 30 get
4015 * shifted up so that we can stick the SIMD channel index in the middle. This
4016 * way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
4017 * at the same logical offset, the scratch read/write instruction acts on
4018 * continuous elements and we get good cache locality.
4021 fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
4022 const fs_reg
&nir_addr
,
4025 const fs_reg
&chan_index
=
4026 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
4027 const unsigned chan_index_bits
= ffs(dispatch_width
) - 1;
4029 fs_reg addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4031 /* In this case, we know the address is aligned to a DWORD and we want
4032 * the final address in DWORDs.
4034 bld
.SHL(addr
, nir_addr
, brw_imm_ud(chan_index_bits
- 2));
4035 bld
.OR(addr
, addr
, chan_index
);
4037 /* This case substantially more annoying because we have to pay
4038 * attention to those pesky two bottom bits.
4040 fs_reg addr_hi
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4041 bld
.AND(addr_hi
, nir_addr
, brw_imm_ud(~0x3u
));
4042 bld
.SHL(addr_hi
, addr_hi
, brw_imm_ud(chan_index_bits
));
4043 fs_reg chan_addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4044 bld
.SHL(chan_addr
, chan_index
, brw_imm_ud(2));
4045 bld
.AND(addr
, nir_addr
, brw_imm_ud(0x3u
));
4046 bld
.OR(addr
, addr
, addr_hi
);
4047 bld
.OR(addr
, addr
, chan_addr
);
4053 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4056 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4057 dest
= get_nir_dest(instr
->dest
);
4059 switch (instr
->intrinsic
) {
4060 case nir_intrinsic_image_load
:
4061 case nir_intrinsic_image_store
:
4062 case nir_intrinsic_image_atomic_add
:
4063 case nir_intrinsic_image_atomic_imin
:
4064 case nir_intrinsic_image_atomic_umin
:
4065 case nir_intrinsic_image_atomic_imax
:
4066 case nir_intrinsic_image_atomic_umax
:
4067 case nir_intrinsic_image_atomic_and
:
4068 case nir_intrinsic_image_atomic_or
:
4069 case nir_intrinsic_image_atomic_xor
:
4070 case nir_intrinsic_image_atomic_exchange
:
4071 case nir_intrinsic_image_atomic_comp_swap
:
4072 case nir_intrinsic_bindless_image_load
:
4073 case nir_intrinsic_bindless_image_store
:
4074 case nir_intrinsic_bindless_image_atomic_add
:
4075 case nir_intrinsic_bindless_image_atomic_imin
:
4076 case nir_intrinsic_bindless_image_atomic_umin
:
4077 case nir_intrinsic_bindless_image_atomic_imax
:
4078 case nir_intrinsic_bindless_image_atomic_umax
:
4079 case nir_intrinsic_bindless_image_atomic_and
:
4080 case nir_intrinsic_bindless_image_atomic_or
:
4081 case nir_intrinsic_bindless_image_atomic_xor
:
4082 case nir_intrinsic_bindless_image_atomic_exchange
:
4083 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4084 /* Get some metadata from the image intrinsic. */
4085 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4087 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4089 switch (instr
->intrinsic
) {
4090 case nir_intrinsic_image_load
:
4091 case nir_intrinsic_image_store
:
4092 case nir_intrinsic_image_atomic_add
:
4093 case nir_intrinsic_image_atomic_imin
:
4094 case nir_intrinsic_image_atomic_umin
:
4095 case nir_intrinsic_image_atomic_imax
:
4096 case nir_intrinsic_image_atomic_umax
:
4097 case nir_intrinsic_image_atomic_and
:
4098 case nir_intrinsic_image_atomic_or
:
4099 case nir_intrinsic_image_atomic_xor
:
4100 case nir_intrinsic_image_atomic_exchange
:
4101 case nir_intrinsic_image_atomic_comp_swap
:
4102 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4103 get_nir_image_intrinsic_image(bld
, instr
);
4108 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4109 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4113 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4114 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4115 brw_imm_ud(nir_image_intrinsic_coord_components(instr
));
4117 /* Emit an image load, store or atomic op. */
4118 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4119 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4120 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4122 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4123 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4124 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4125 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4126 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4127 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4128 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4129 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4130 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4132 unsigned num_srcs
= info
->num_srcs
;
4133 int op
= brw_aop_for_nir_intrinsic(instr
);
4134 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4135 assert(num_srcs
== 4);
4139 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4143 data
= get_nir_src(instr
->src
[3]);
4144 if (num_srcs
>= 5) {
4145 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4146 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4147 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4150 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4152 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4153 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4158 case nir_intrinsic_image_size
:
4159 case nir_intrinsic_bindless_image_size
: {
4160 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4161 * into will handle the binding table index for us in the geneerator.
4162 * Incidentally, this means that we can handle bindless with exactly the
4165 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4166 BRW_REGISTER_TYPE_UD
);
4167 image
= bld
.emit_uniformize(image
);
4169 assert(nir_src_as_uint(instr
->src
[1]) == 0);
4171 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4172 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4173 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4175 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4176 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4177 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4178 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4180 /* Since the image size is always uniform, we can just emit a SIMD8
4181 * query instruction and splat the result out.
4183 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4185 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4186 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4187 tmp
, srcs
, ARRAY_SIZE(srcs
));
4188 inst
->size_written
= 4 * REG_SIZE
;
4190 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4191 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4192 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4193 offset(retype(dest
, tmp
.type
), bld
, c
),
4194 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4196 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4197 component(offset(tmp
, ubld
, c
), 0));
4203 case nir_intrinsic_image_load_raw_intel
: {
4204 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4205 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4206 get_nir_image_intrinsic_image(bld
, instr
);
4207 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4208 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4209 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4212 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4213 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4214 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4218 case nir_intrinsic_image_store_raw_intel
: {
4219 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4220 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4221 get_nir_image_intrinsic_image(bld
, instr
);
4222 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4223 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4224 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4225 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4227 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4228 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4232 case nir_intrinsic_scoped_barrier
:
4233 assert(nir_intrinsic_execution_scope(instr
) == NIR_SCOPE_NONE
);
4235 case nir_intrinsic_group_memory_barrier
:
4236 case nir_intrinsic_memory_barrier_shared
:
4237 case nir_intrinsic_memory_barrier_buffer
:
4238 case nir_intrinsic_memory_barrier_image
:
4239 case nir_intrinsic_memory_barrier
:
4240 case nir_intrinsic_begin_invocation_interlock
:
4241 case nir_intrinsic_end_invocation_interlock
: {
4242 bool l3_fence
, slm_fence
;
4243 const enum opcode opcode
=
4244 instr
->intrinsic
== nir_intrinsic_begin_invocation_interlock
?
4245 SHADER_OPCODE_INTERLOCK
: SHADER_OPCODE_MEMORY_FENCE
;
4247 switch (instr
->intrinsic
) {
4248 case nir_intrinsic_scoped_barrier
: {
4249 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4250 l3_fence
= modes
& (nir_var_shader_out
|
4252 nir_var_mem_global
);
4253 slm_fence
= modes
& nir_var_mem_shared
;
4257 case nir_intrinsic_begin_invocation_interlock
:
4258 case nir_intrinsic_end_invocation_interlock
:
4259 /* For beginInvocationInterlockARB(), we will generate a memory fence
4260 * but with a different opcode so that generator can pick SENDC
4263 * For endInvocationInterlockARB(), we need to insert a memory fence which
4264 * stalls in the shader until the memory transactions prior to that
4265 * fence are complete. This ensures that the shader does not end before
4266 * any writes from its critical section have landed. Otherwise, you can
4267 * end up with a case where the next invocation on that pixel properly
4268 * stalls for previous FS invocation on its pixel to complete but
4269 * doesn't actually wait for the dataport memory transactions from that
4270 * thread to land before submitting its own.
4272 * Handling them here will allow the logic for IVB render cache (see
4273 * below) to be reused.
4280 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4281 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4282 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4283 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4287 if (stage
!= MESA_SHADER_COMPUTE
&& stage
!= MESA_SHADER_KERNEL
)
4290 /* If the workgroup fits in a single HW thread, the messages for SLM are
4291 * processed in-order and the shader itself is already synchronized so
4292 * the memory fence is not necessary.
4294 * TODO: Check if applies for many HW threads sharing same Data Port.
4296 if (!nir
->info
.cs
.local_size_variable
&&
4297 slm_fence
&& workgroup_size() <= dispatch_width
)
4300 /* Prior to Gen11, there's only L3 fence, so emit that instead. */
4301 if (slm_fence
&& devinfo
->gen
< 11) {
4306 /* IVB does typed surface access through the render cache, so we need
4309 const bool needs_render_fence
=
4310 devinfo
->gen
== 7 && !devinfo
->is_haswell
;
4312 /* Be conservative in Gen11+ and always stall in a fence. Since there
4313 * are two different fences, and shader might want to synchronize
4316 * TODO: Use scope and visibility information for the barriers from NIR
4317 * to make a better decision on whether we need to stall.
4319 const bool stall
= devinfo
->gen
>= 11 || needs_render_fence
||
4320 instr
->intrinsic
== nir_intrinsic_end_invocation_interlock
;
4322 const bool commit_enable
= stall
||
4323 devinfo
->gen
>= 10; /* HSD ES # 1404612949 */
4325 unsigned fence_regs_count
= 0;
4326 fs_reg fence_regs
[2] = {};
4328 const fs_builder ubld
= bld
.group(8, 0);
4333 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4335 brw_imm_ud(commit_enable
),
4336 brw_imm_ud(/* bti */ 0));
4337 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4339 fence_regs
[fence_regs_count
++] = fence
->dst
;
4341 if (needs_render_fence
) {
4342 fs_inst
*render_fence
=
4344 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4346 brw_imm_ud(commit_enable
),
4347 brw_imm_ud(/* bti */ 0));
4348 render_fence
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4350 fence_regs
[fence_regs_count
++] = render_fence
->dst
;
4355 assert(opcode
== SHADER_OPCODE_MEMORY_FENCE
);
4358 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4360 brw_imm_ud(commit_enable
),
4361 brw_imm_ud(GEN7_BTI_SLM
));
4362 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4364 fence_regs
[fence_regs_count
++] = fence
->dst
;
4367 assert(fence_regs_count
<= 2);
4369 if (stall
|| fence_regs_count
== 0) {
4370 ubld
.exec_all().group(1, 0).emit(
4371 FS_OPCODE_SCHEDULING_FENCE
, ubld
.null_reg_ud(),
4372 fence_regs
, fence_regs_count
);
4378 case nir_intrinsic_memory_barrier_tcs_patch
:
4381 case nir_intrinsic_shader_clock
: {
4382 /* We cannot do anything if there is an event, so ignore it for now */
4383 const fs_reg shader_clock
= get_timestamp(bld
);
4384 const fs_reg srcs
[] = { component(shader_clock
, 0),
4385 component(shader_clock
, 1) };
4386 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4390 case nir_intrinsic_image_samples
:
4391 /* The driver does not support multi-sampled images. */
4392 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4395 case nir_intrinsic_load_uniform
: {
4396 /* Offsets are in bytes but they should always aligned to
4399 assert(instr
->const_index
[0] % 4 == 0 ||
4400 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4402 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4404 if (nir_src_is_const(instr
->src
[0])) {
4405 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4406 assert(load_offset
% type_sz(dest
.type
) == 0);
4407 /* For 16-bit types we add the module of the const_index[0]
4408 * offset to access to not 32-bit aligned element
4410 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4412 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4413 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4416 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4417 BRW_REGISTER_TYPE_UD
);
4419 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4420 * go past the end of the uniform. In order to keep the n'th
4421 * component from running past, we subtract off the size of all but
4422 * one component of the vector.
4424 assert(instr
->const_index
[1] >=
4425 instr
->num_components
* (int) type_sz(dest
.type
));
4426 unsigned read_size
= instr
->const_index
[1] -
4427 (instr
->num_components
- 1) * type_sz(dest
.type
);
4429 bool supports_64bit_indirects
=
4430 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4432 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4433 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4434 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4435 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4436 indirect
, brw_imm_ud(read_size
));
4439 const unsigned num_mov_indirects
=
4440 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4441 /* We read a little bit less per MOV INDIRECT, as they are now
4442 * 32-bits ones instead of 64-bit. Fix read_size then.
4444 const unsigned read_size_32bit
= read_size
-
4445 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4446 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4447 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4448 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4449 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4450 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4451 indirect
, brw_imm_ud(read_size_32bit
));
4459 case nir_intrinsic_load_ubo
: {
4461 if (nir_src_is_const(instr
->src
[0])) {
4462 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4463 nir_src_as_uint(instr
->src
[0]);
4464 surf_index
= brw_imm_ud(index
);
4466 /* The block index is not a constant. Evaluate the index expression
4467 * per-channel and add the base UBO index; we have to select a value
4468 * from any live channel.
4470 surf_index
= vgrf(glsl_type::uint_type
);
4471 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4472 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4473 surf_index
= bld
.emit_uniformize(surf_index
);
4476 if (!nir_src_is_const(instr
->src
[1])) {
4477 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4478 BRW_REGISTER_TYPE_UD
);
4480 for (int i
= 0; i
< instr
->num_components
; i
++)
4481 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4482 base_offset
, i
* type_sz(dest
.type
));
4484 prog_data
->has_ubo_pull
= true;
4486 /* Even if we are loading doubles, a pull constant load will load
4487 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4488 * need to load a full dvec4 we will have to emit 2 loads. This is
4489 * similar to demote_pull_constants(), except that in that case we
4490 * see individual accesses to each component of the vector and then
4491 * we let CSE deal with duplicate loads. Here we see a vector access
4492 * and we have to split it if necessary.
4494 const unsigned type_size
= type_sz(dest
.type
);
4495 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4497 /* See if we've selected this as a push constant candidate */
4498 if (nir_src_is_const(instr
->src
[0])) {
4499 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4500 const unsigned offset_256b
= load_offset
/ 32;
4503 for (int i
= 0; i
< 4; i
++) {
4504 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4505 if (range
->block
== ubo_block
&&
4506 offset_256b
>= range
->start
&&
4507 offset_256b
< range
->start
+ range
->length
) {
4509 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4510 push_reg
.offset
= load_offset
- 32 * range
->start
;
4515 if (push_reg
.file
!= BAD_FILE
) {
4516 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4517 bld
.MOV(offset(dest
, bld
, i
),
4518 byte_offset(push_reg
, i
* type_size
));
4524 prog_data
->has_ubo_pull
= true;
4526 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4527 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4528 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4530 for (unsigned c
= 0; c
< instr
->num_components
;) {
4531 const unsigned base
= load_offset
+ c
* type_size
;
4532 /* Number of usable components in the next block-aligned load. */
4533 const unsigned count
= MIN2(instr
->num_components
- c
,
4534 (block_sz
- base
% block_sz
) / type_size
);
4536 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4537 packed_consts
, surf_index
,
4538 brw_imm_ud(base
& ~(block_sz
- 1)));
4540 const fs_reg consts
=
4541 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4544 for (unsigned d
= 0; d
< count
; d
++)
4545 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4553 case nir_intrinsic_load_global
: {
4554 assert(devinfo
->gen
>= 8);
4556 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4557 assert(nir_intrinsic_align(instr
) > 0);
4558 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4559 nir_intrinsic_align(instr
) >= 4) {
4560 assert(nir_dest_num_components(instr
->dest
) <= 4);
4561 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4563 get_nir_src(instr
->src
[0]), /* Address */
4564 fs_reg(), /* No source data */
4565 brw_imm_ud(instr
->num_components
));
4566 inst
->size_written
= instr
->num_components
*
4567 inst
->dst
.component_size(inst
->exec_size
);
4569 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4570 assert(nir_dest_num_components(instr
->dest
) == 1);
4571 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4572 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4574 get_nir_src(instr
->src
[0]), /* Address */
4575 fs_reg(), /* No source data */
4576 brw_imm_ud(bit_size
));
4577 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4582 case nir_intrinsic_store_global
:
4583 assert(devinfo
->gen
>= 8);
4585 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4586 assert(nir_intrinsic_write_mask(instr
) ==
4587 (1u << instr
->num_components
) - 1);
4588 assert(nir_intrinsic_align(instr
) > 0);
4589 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4590 nir_intrinsic_align(instr
) >= 4) {
4591 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4592 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4594 get_nir_src(instr
->src
[1]), /* Address */
4595 get_nir_src(instr
->src
[0]), /* Data */
4596 brw_imm_ud(instr
->num_components
));
4598 assert(nir_src_num_components(instr
->src
[0]) == 1);
4599 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4600 brw_reg_type data_type
=
4601 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4602 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4603 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4604 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4606 get_nir_src(instr
->src
[1]), /* Address */
4608 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4612 case nir_intrinsic_global_atomic_add
:
4613 case nir_intrinsic_global_atomic_imin
:
4614 case nir_intrinsic_global_atomic_umin
:
4615 case nir_intrinsic_global_atomic_imax
:
4616 case nir_intrinsic_global_atomic_umax
:
4617 case nir_intrinsic_global_atomic_and
:
4618 case nir_intrinsic_global_atomic_or
:
4619 case nir_intrinsic_global_atomic_xor
:
4620 case nir_intrinsic_global_atomic_exchange
:
4621 case nir_intrinsic_global_atomic_comp_swap
:
4622 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4624 case nir_intrinsic_global_atomic_fmin
:
4625 case nir_intrinsic_global_atomic_fmax
:
4626 case nir_intrinsic_global_atomic_fcomp_swap
:
4627 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4630 case nir_intrinsic_load_ssbo
: {
4631 assert(devinfo
->gen
>= 7);
4633 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4634 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4635 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4636 get_nir_ssbo_intrinsic_index(bld
, instr
);
4637 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4638 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4640 /* Make dest unsigned because that's what the temporary will be */
4641 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4643 /* Read the vector */
4644 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4645 assert(nir_intrinsic_align(instr
) > 0);
4646 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4647 nir_intrinsic_align(instr
) >= 4) {
4648 assert(nir_dest_num_components(instr
->dest
) <= 4);
4649 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4651 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4652 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4653 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4655 assert(nir_dest_num_components(instr
->dest
) == 1);
4656 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4658 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4659 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4660 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4661 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4666 case nir_intrinsic_store_ssbo
: {
4667 assert(devinfo
->gen
>= 7);
4669 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4670 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4671 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4672 get_nir_ssbo_intrinsic_index(bld
, instr
);
4673 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4674 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4676 fs_reg data
= get_nir_src(instr
->src
[0]);
4677 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4679 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4680 assert(nir_intrinsic_write_mask(instr
) ==
4681 (1u << instr
->num_components
) - 1);
4682 assert(nir_intrinsic_align(instr
) > 0);
4683 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4684 nir_intrinsic_align(instr
) >= 4) {
4685 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4686 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4687 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4688 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4689 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4691 assert(nir_src_num_components(instr
->src
[0]) == 1);
4692 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4694 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4695 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4697 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4698 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4703 case nir_intrinsic_store_output
: {
4704 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4705 fs_reg src
= get_nir_src(instr
->src
[0]);
4707 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4708 unsigned num_components
= instr
->num_components
;
4709 unsigned first_component
= nir_intrinsic_component(instr
);
4711 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4712 4 * store_offset
), src
.type
);
4713 for (unsigned j
= 0; j
< num_components
; j
++) {
4714 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4715 offset(src
, bld
, j
));
4720 case nir_intrinsic_ssbo_atomic_add
:
4721 case nir_intrinsic_ssbo_atomic_imin
:
4722 case nir_intrinsic_ssbo_atomic_umin
:
4723 case nir_intrinsic_ssbo_atomic_imax
:
4724 case nir_intrinsic_ssbo_atomic_umax
:
4725 case nir_intrinsic_ssbo_atomic_and
:
4726 case nir_intrinsic_ssbo_atomic_or
:
4727 case nir_intrinsic_ssbo_atomic_xor
:
4728 case nir_intrinsic_ssbo_atomic_exchange
:
4729 case nir_intrinsic_ssbo_atomic_comp_swap
:
4730 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4732 case nir_intrinsic_ssbo_atomic_fmin
:
4733 case nir_intrinsic_ssbo_atomic_fmax
:
4734 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4735 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4738 case nir_intrinsic_get_buffer_size
: {
4739 assert(nir_src_num_components(instr
->src
[0]) == 1);
4740 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4741 nir_src_as_uint(instr
->src
[0]) : 0;
4743 /* A resinfo's sampler message is used to get the buffer size. The
4744 * SIMD8's writeback message consists of four registers and SIMD16's
4745 * writeback message consists of 8 destination registers (two per each
4746 * component). Because we are only interested on the first channel of
4747 * the first returned component, where resinfo returns the buffer size
4748 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4749 * the dispatch width.
4751 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4752 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4753 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4756 ubld
.MOV(src_payload
, brw_imm_d(0));
4758 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4759 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4760 src_payload
, brw_imm_ud(index
));
4761 inst
->header_size
= 0;
4763 inst
->size_written
= 4 * REG_SIZE
;
4765 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4767 * "Out-of-bounds checking is always performed at a DWord granularity. If
4768 * any part of the DWord is out-of-bounds then the whole DWord is
4769 * considered out-of-bounds."
4771 * This implies that types with size smaller than 4-bytes need to be
4772 * padded if they don't complete the last dword of the buffer. But as we
4773 * need to maintain the original size we need to reverse the padding
4774 * calculation to return the correct size to know the number of elements
4775 * of an unsized array. As we stored in the last two bits of the surface
4776 * size the needed padding for the buffer, we calculate here the
4777 * original buffer_size reversing the surface_size calculation:
4779 * surface_size = isl_align(buffer_size, 4) +
4780 * (isl_align(buffer_size) - buffer_size)
4782 * buffer_size = surface_size & ~3 - surface_size & 3
4785 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4786 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4787 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4789 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4790 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4791 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4793 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4797 case nir_intrinsic_load_scratch
: {
4798 assert(devinfo
->gen
>= 7);
4800 assert(nir_dest_num_components(instr
->dest
) == 1);
4801 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4802 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4804 if (devinfo
->gen
>= 8) {
4805 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4806 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4808 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4811 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4812 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4813 const fs_reg nir_addr
= get_nir_src(instr
->src
[0]);
4815 /* Make dest unsigned because that's what the temporary will be */
4816 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4818 /* Read the vector */
4819 assert(nir_dest_num_components(instr
->dest
) == 1);
4820 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4821 assert(nir_intrinsic_align(instr
) > 0);
4822 if (nir_dest_bit_size(instr
->dest
) >= 4 &&
4823 nir_intrinsic_align(instr
) >= 4) {
4824 /* The offset for a DWORD scattered message is in dwords. */
4825 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4826 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4828 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
,
4829 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4831 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4832 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4834 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4835 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4836 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4837 bld
.MOV(dest
, read_result
);
4842 case nir_intrinsic_store_scratch
: {
4843 assert(devinfo
->gen
>= 7);
4845 assert(nir_src_num_components(instr
->src
[0]) == 1);
4846 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4847 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4849 if (devinfo
->gen
>= 8) {
4850 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4851 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4853 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4856 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4857 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4858 const fs_reg nir_addr
= get_nir_src(instr
->src
[1]);
4860 fs_reg data
= get_nir_src(instr
->src
[0]);
4861 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4863 assert(nir_src_num_components(instr
->src
[0]) == 1);
4864 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4865 assert(nir_intrinsic_write_mask(instr
) == 1);
4866 assert(nir_intrinsic_align(instr
) > 0);
4867 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4868 nir_intrinsic_align(instr
) >= 4) {
4869 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4871 /* The offset for a DWORD scattered message is in dwords. */
4872 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4873 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4875 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
,
4876 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4878 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4879 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4881 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4882 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4884 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4885 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4890 case nir_intrinsic_load_subgroup_size
:
4891 /* This should only happen for fragment shaders because every other case
4892 * is lowered in NIR so we can optimize on it.
4894 assert(stage
== MESA_SHADER_FRAGMENT
);
4895 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4898 case nir_intrinsic_load_subgroup_invocation
:
4899 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4900 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4903 case nir_intrinsic_load_subgroup_eq_mask
:
4904 case nir_intrinsic_load_subgroup_ge_mask
:
4905 case nir_intrinsic_load_subgroup_gt_mask
:
4906 case nir_intrinsic_load_subgroup_le_mask
:
4907 case nir_intrinsic_load_subgroup_lt_mask
:
4908 unreachable("not reached");
4910 case nir_intrinsic_vote_any
: {
4911 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4913 /* The any/all predicates do not consider channel enables. To prevent
4914 * dead channels from affecting the result, we initialize the flag with
4915 * with the identity value for the logical operation.
4917 if (dispatch_width
== 32) {
4918 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4919 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4922 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4924 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4926 /* For some reason, the any/all predicates don't work properly with
4927 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4928 * doesn't read the correct subset of the flag register and you end up
4929 * getting garbage in the second half. Work around this by using a pair
4930 * of 1-wide MOVs and scattering the result.
4932 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4933 ubld
.MOV(res1
, brw_imm_d(0));
4934 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4935 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4936 BRW_PREDICATE_ALIGN1_ANY32H
,
4937 ubld
.MOV(res1
, brw_imm_d(-1)));
4939 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4942 case nir_intrinsic_vote_all
: {
4943 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4945 /* The any/all predicates do not consider channel enables. To prevent
4946 * dead channels from affecting the result, we initialize the flag with
4947 * with the identity value for the logical operation.
4949 if (dispatch_width
== 32) {
4950 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4951 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4952 brw_imm_ud(0xffffffff));
4954 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4956 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4958 /* For some reason, the any/all predicates don't work properly with
4959 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4960 * doesn't read the correct subset of the flag register and you end up
4961 * getting garbage in the second half. Work around this by using a pair
4962 * of 1-wide MOVs and scattering the result.
4964 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4965 ubld
.MOV(res1
, brw_imm_d(0));
4966 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4967 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4968 BRW_PREDICATE_ALIGN1_ALL32H
,
4969 ubld
.MOV(res1
, brw_imm_d(-1)));
4971 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4974 case nir_intrinsic_vote_feq
:
4975 case nir_intrinsic_vote_ieq
: {
4976 fs_reg value
= get_nir_src(instr
->src
[0]);
4977 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4978 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4979 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4980 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4983 fs_reg uniformized
= bld
.emit_uniformize(value
);
4984 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4986 /* The any/all predicates do not consider channel enables. To prevent
4987 * dead channels from affecting the result, we initialize the flag with
4988 * with the identity value for the logical operation.
4990 if (dispatch_width
== 32) {
4991 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4992 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4993 brw_imm_ud(0xffffffff));
4995 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4997 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4999 /* For some reason, the any/all predicates don't work properly with
5000 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
5001 * doesn't read the correct subset of the flag register and you end up
5002 * getting garbage in the second half. Work around this by using a pair
5003 * of 1-wide MOVs and scattering the result.
5005 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
5006 ubld
.MOV(res1
, brw_imm_d(0));
5007 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
5008 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
5009 BRW_PREDICATE_ALIGN1_ALL32H
,
5010 ubld
.MOV(res1
, brw_imm_d(-1)));
5012 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
5016 case nir_intrinsic_ballot
: {
5017 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
5018 BRW_REGISTER_TYPE_UD
);
5019 struct brw_reg flag
= brw_flag_reg(0, 0);
5020 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
5021 * as f0.0. This is a problem for fragment programs as we currently use
5022 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
5023 * programs yet so this isn't a problem. When we do, something will
5026 if (dispatch_width
== 32)
5027 flag
.type
= BRW_REGISTER_TYPE_UD
;
5029 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
5030 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
5032 if (instr
->dest
.ssa
.bit_size
> 32) {
5033 dest
.type
= BRW_REGISTER_TYPE_UQ
;
5035 dest
.type
= BRW_REGISTER_TYPE_UD
;
5037 bld
.MOV(dest
, flag
);
5041 case nir_intrinsic_read_invocation
: {
5042 const fs_reg value
= get_nir_src(instr
->src
[0]);
5043 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
5044 fs_reg tmp
= bld
.vgrf(value
.type
);
5046 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
5047 bld
.emit_uniformize(invocation
));
5049 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
5053 case nir_intrinsic_read_first_invocation
: {
5054 const fs_reg value
= get_nir_src(instr
->src
[0]);
5055 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
5059 case nir_intrinsic_shuffle
: {
5060 const fs_reg value
= get_nir_src(instr
->src
[0]);
5061 const fs_reg index
= get_nir_src(instr
->src
[1]);
5063 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
5067 case nir_intrinsic_first_invocation
: {
5068 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5069 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
5070 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
5071 fs_reg(component(tmp
, 0)));
5075 case nir_intrinsic_quad_broadcast
: {
5076 const fs_reg value
= get_nir_src(instr
->src
[0]);
5077 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
5079 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
5080 value
, brw_imm_ud(index
), brw_imm_ud(4));
5084 case nir_intrinsic_quad_swap_horizontal
: {
5085 const fs_reg value
= get_nir_src(instr
->src
[0]);
5086 const fs_reg tmp
= bld
.vgrf(value
.type
);
5087 if (devinfo
->gen
<= 7) {
5088 /* The hardware doesn't seem to support these crazy regions with
5089 * compressed instructions on gen7 and earlier so we fall back to
5090 * using quad swizzles. Fortunately, we don't support 64-bit
5091 * anything in Vulkan on gen7.
5093 assert(nir_src_bit_size(instr
->src
[0]) == 32);
5094 const fs_builder ubld
= bld
.exec_all();
5095 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5096 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
5097 bld
.MOV(retype(dest
, value
.type
), tmp
);
5099 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
5101 const fs_reg src_left
= horiz_stride(value
, 2);
5102 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
5103 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
5104 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
5106 ubld
.MOV(tmp_left
, src_right
);
5107 ubld
.MOV(tmp_right
, src_left
);
5110 bld
.MOV(retype(dest
, value
.type
), tmp
);
5114 case nir_intrinsic_quad_swap_vertical
: {
5115 const fs_reg value
= get_nir_src(instr
->src
[0]);
5116 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5117 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5118 const fs_reg tmp
= bld
.vgrf(value
.type
);
5119 const fs_builder ubld
= bld
.exec_all();
5120 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5121 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5122 bld
.MOV(retype(dest
, value
.type
), tmp
);
5124 /* For larger data types, we have to either emit dispatch_width many
5125 * MOVs or else fall back to doing indirects.
5127 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5128 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5130 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5135 case nir_intrinsic_quad_swap_diagonal
: {
5136 const fs_reg value
= get_nir_src(instr
->src
[0]);
5137 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5138 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5139 const fs_reg tmp
= bld
.vgrf(value
.type
);
5140 const fs_builder ubld
= bld
.exec_all();
5141 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5142 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5143 bld
.MOV(retype(dest
, value
.type
), tmp
);
5145 /* For larger data types, we have to either emit dispatch_width many
5146 * MOVs or else fall back to doing indirects.
5148 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5149 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5151 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5156 case nir_intrinsic_reduce
: {
5157 fs_reg src
= get_nir_src(instr
->src
[0]);
5158 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5159 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5160 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5161 cluster_size
= dispatch_width
;
5163 /* Figure out the source type */
5164 src
.type
= brw_type_for_nir_type(devinfo
,
5165 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5166 nir_src_bit_size(instr
->src
[0])));
5168 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5169 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5170 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5172 /* There are a couple of register region issues that make things
5173 * complicated for 8-bit types:
5175 * 1. Only raw moves are allowed to write to a packed 8-bit
5177 * 2. If we use a strided destination, the efficient way to do scan
5178 * operations ends up using strides that are too big to encode in
5181 * To get around these issues, we just do all 8-bit scan operations in
5182 * 16 bits. It's actually fewer instructions than what we'd have to do
5183 * if we were trying to do it in native 8-bit types and the results are
5184 * the same once we truncate to 8 bits at the end.
5186 brw_reg_type scan_type
= src
.type
;
5187 if (type_sz(scan_type
) == 1)
5188 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5190 /* Set up a register for all of our scratching around and initialize it
5191 * to reduction operation's identity value.
5193 fs_reg scan
= bld
.vgrf(scan_type
);
5194 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5196 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5198 dest
.type
= src
.type
;
5199 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5200 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5201 * the distance between clusters is at least 2 GRFs. In this case,
5202 * we don't need the weird striding of the CLUSTER_BROADCAST
5203 * instruction and can just do regular MOVs.
5205 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5206 const unsigned groups
=
5207 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5208 const unsigned group_size
= dispatch_width
/ groups
;
5209 for (unsigned i
= 0; i
< groups
; i
++) {
5210 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5211 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5212 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5213 component(scan
, comp
));
5216 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5217 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5222 case nir_intrinsic_inclusive_scan
:
5223 case nir_intrinsic_exclusive_scan
: {
5224 fs_reg src
= get_nir_src(instr
->src
[0]);
5225 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5227 /* Figure out the source type */
5228 src
.type
= brw_type_for_nir_type(devinfo
,
5229 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5230 nir_src_bit_size(instr
->src
[0])));
5232 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5233 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5234 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5236 /* There are a couple of register region issues that make things
5237 * complicated for 8-bit types:
5239 * 1. Only raw moves are allowed to write to a packed 8-bit
5241 * 2. If we use a strided destination, the efficient way to do scan
5242 * operations ends up using strides that are too big to encode in
5245 * To get around these issues, we just do all 8-bit scan operations in
5246 * 16 bits. It's actually fewer instructions than what we'd have to do
5247 * if we were trying to do it in native 8-bit types and the results are
5248 * the same once we truncate to 8 bits at the end.
5250 brw_reg_type scan_type
= src
.type
;
5251 if (type_sz(scan_type
) == 1)
5252 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5254 /* Set up a register for all of our scratching around and initialize it
5255 * to reduction operation's identity value.
5257 fs_reg scan
= bld
.vgrf(scan_type
);
5258 const fs_builder allbld
= bld
.exec_all();
5259 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5261 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5262 /* Exclusive scan is a bit harder because we have to do an annoying
5263 * shift of the contents before we can begin. To make things worse,
5264 * we can't do this with a normal stride; we have to use indirects.
5266 fs_reg shifted
= bld
.vgrf(scan_type
);
5267 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5268 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5270 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5271 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5275 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5277 bld
.MOV(retype(dest
, src
.type
), scan
);
5282 unreachable("unknown intrinsic");
5287 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5288 int op
, nir_intrinsic_instr
*instr
)
5290 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5291 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5292 * appear to exist. However, if you look at Vol 2a, there are no message
5293 * descriptors provided for Qword atomic ops except for A64 messages.
5295 assert(nir_dest_bit_size(instr
->dest
) == 32);
5298 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5299 dest
= get_nir_dest(instr
->dest
);
5301 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5302 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5303 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5304 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5305 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5308 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5309 data
= get_nir_src(instr
->src
[2]);
5311 if (op
== BRW_AOP_CMPWR
) {
5312 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5313 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5314 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5317 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5319 /* Emit the actual atomic operation */
5321 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5322 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5326 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5327 int op
, nir_intrinsic_instr
*instr
)
5330 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5331 dest
= get_nir_dest(instr
->dest
);
5333 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5334 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5335 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5336 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5337 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5339 fs_reg data
= get_nir_src(instr
->src
[2]);
5340 if (op
== BRW_AOP_FCMPWR
) {
5341 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5342 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5343 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5346 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5348 /* Emit the actual atomic operation */
5350 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5351 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5355 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5356 int op
, nir_intrinsic_instr
*instr
)
5359 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5360 dest
= get_nir_dest(instr
->dest
);
5362 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5363 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5364 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5365 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5368 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5369 data
= get_nir_src(instr
->src
[1]);
5370 if (op
== BRW_AOP_CMPWR
) {
5371 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5372 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5373 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5376 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5378 /* Get the offset */
5379 if (nir_src_is_const(instr
->src
[0])) {
5380 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5381 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5383 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5384 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5385 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5386 brw_imm_ud(instr
->const_index
[0]));
5389 /* Emit the actual atomic operation operation */
5391 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5392 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5396 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5397 int op
, nir_intrinsic_instr
*instr
)
5400 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5401 dest
= get_nir_dest(instr
->dest
);
5403 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5404 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5405 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5406 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5408 fs_reg data
= get_nir_src(instr
->src
[1]);
5409 if (op
== BRW_AOP_FCMPWR
) {
5410 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5411 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5412 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5415 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5417 /* Get the offset */
5418 if (nir_src_is_const(instr
->src
[0])) {
5419 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5420 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5422 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5423 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5424 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5425 brw_imm_ud(instr
->const_index
[0]));
5428 /* Emit the actual atomic operation operation */
5430 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5431 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5435 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5436 int op
, nir_intrinsic_instr
*instr
)
5439 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5440 dest
= get_nir_dest(instr
->dest
);
5442 fs_reg addr
= get_nir_src(instr
->src
[0]);
5445 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5446 data
= get_nir_src(instr
->src
[1]);
5448 if (op
== BRW_AOP_CMPWR
) {
5449 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5450 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5451 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5455 if (nir_dest_bit_size(instr
->dest
) == 64) {
5456 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5457 dest
, addr
, data
, brw_imm_ud(op
));
5459 assert(nir_dest_bit_size(instr
->dest
) == 32);
5460 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5461 dest
, addr
, data
, brw_imm_ud(op
));
5466 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5467 int op
, nir_intrinsic_instr
*instr
)
5469 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5470 fs_reg dest
= get_nir_dest(instr
->dest
);
5472 fs_reg addr
= get_nir_src(instr
->src
[0]);
5474 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5475 fs_reg data
= get_nir_src(instr
->src
[1]);
5477 if (op
== BRW_AOP_FCMPWR
) {
5478 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5479 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5480 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5484 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5485 dest
, addr
, data
, brw_imm_ud(op
));
5489 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5491 unsigned texture
= instr
->texture_index
;
5492 unsigned sampler
= instr
->sampler_index
;
5494 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5496 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5497 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5499 int lod_components
= 0;
5501 /* The hardware requires a LOD for buffer textures */
5502 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5503 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5505 uint32_t header_bits
= 0;
5506 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5507 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5508 switch (instr
->src
[i
].src_type
) {
5509 case nir_tex_src_bias
:
5510 srcs
[TEX_LOGICAL_SRC_LOD
] =
5511 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5513 case nir_tex_src_comparator
:
5514 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5516 case nir_tex_src_coord
:
5517 switch (instr
->op
) {
5519 case nir_texop_txf_ms
:
5520 case nir_texop_txf_ms_mcs
:
5521 case nir_texop_samples_identical
:
5522 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5525 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5529 case nir_tex_src_ddx
:
5530 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5531 lod_components
= nir_tex_instr_src_size(instr
, i
);
5533 case nir_tex_src_ddy
:
5534 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5536 case nir_tex_src_lod
:
5537 switch (instr
->op
) {
5539 srcs
[TEX_LOGICAL_SRC_LOD
] =
5540 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5543 srcs
[TEX_LOGICAL_SRC_LOD
] =
5544 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5547 srcs
[TEX_LOGICAL_SRC_LOD
] =
5548 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5552 case nir_tex_src_min_lod
:
5553 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5554 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5556 case nir_tex_src_ms_index
:
5557 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5560 case nir_tex_src_offset
: {
5561 uint32_t offset_bits
= 0;
5562 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5563 header_bits
|= offset_bits
;
5565 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5566 retype(src
, BRW_REGISTER_TYPE_D
);
5571 case nir_tex_src_projector
:
5572 unreachable("should be lowered");
5574 case nir_tex_src_texture_offset
: {
5575 /* Emit code to evaluate the actual indexing expression */
5576 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5577 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5578 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5582 case nir_tex_src_sampler_offset
: {
5583 /* Emit code to evaluate the actual indexing expression */
5584 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5585 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5586 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5590 case nir_tex_src_texture_handle
:
5591 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5592 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5593 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5596 case nir_tex_src_sampler_handle
:
5597 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5598 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5599 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5602 case nir_tex_src_ms_mcs
:
5603 assert(instr
->op
== nir_texop_txf_ms
);
5604 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5607 case nir_tex_src_plane
: {
5608 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5609 const uint32_t texture_index
=
5610 instr
->texture_index
+
5611 stage_prog_data
->binding_table
.plane_start
[plane
] -
5612 stage_prog_data
->binding_table
.texture_start
;
5614 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5619 unreachable("unknown texture source");
5623 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5624 (instr
->op
== nir_texop_txf_ms
||
5625 instr
->op
== nir_texop_samples_identical
)) {
5626 if (devinfo
->gen
>= 7 &&
5627 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5628 srcs
[TEX_LOGICAL_SRC_MCS
] =
5629 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5630 instr
->coord_components
,
5631 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5632 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5634 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5638 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5639 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5642 switch (instr
->op
) {
5644 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5647 opcode
= FS_OPCODE_TXB_LOGICAL
;
5650 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5653 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5656 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5658 case nir_texop_txf_ms
:
5659 if ((key_tex
->msaa_16
& (1 << sampler
)))
5660 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5662 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5664 case nir_texop_txf_ms_mcs
:
5665 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5667 case nir_texop_query_levels
:
5669 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5672 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5675 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5676 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5678 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5680 case nir_texop_texture_samples
:
5681 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5683 case nir_texop_samples_identical
: {
5684 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5686 /* If mcs is an immediate value, it means there is no MCS. In that case
5687 * just return false.
5689 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5690 bld
.MOV(dst
, brw_imm_ud(0u));
5691 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5692 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5693 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5694 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5695 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5697 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5698 BRW_CONDITIONAL_EQ
);
5703 unreachable("unknown texture opcode");
5706 if (instr
->op
== nir_texop_tg4
) {
5707 if (instr
->component
== 1 &&
5708 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5709 /* gather4 sampler is broken for green channel on RG32F --
5710 * we must ask for blue instead.
5712 header_bits
|= 2 << 16;
5714 header_bits
|= instr
->component
<< 16;
5718 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5719 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5720 inst
->offset
= header_bits
;
5722 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5723 if (devinfo
->gen
>= 9 &&
5724 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5725 unsigned write_mask
= instr
->dest
.is_ssa
?
5726 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5727 (1 << dest_size
) - 1;
5728 assert(write_mask
!= 0); /* dead code should have been eliminated */
5729 inst
->size_written
= util_last_bit(write_mask
) *
5730 inst
->dst
.component_size(inst
->exec_size
);
5732 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5735 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5736 inst
->shadow_compare
= true;
5738 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5739 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5742 for (unsigned i
= 0; i
< dest_size
; i
++)
5743 nir_dest
[i
] = offset(dst
, bld
, i
);
5745 if (instr
->op
== nir_texop_query_levels
) {
5746 /* # levels is in .w */
5747 nir_dest
[0] = offset(dst
, bld
, 3);
5748 } else if (instr
->op
== nir_texop_txs
&&
5749 dest_size
>= 3 && devinfo
->gen
< 7) {
5750 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5751 fs_reg depth
= offset(dst
, bld
, 2);
5752 nir_dest
[2] = vgrf(glsl_type::int_type
);
5753 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5756 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5760 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5762 switch (instr
->type
) {
5763 case nir_jump_break
:
5764 bld
.emit(BRW_OPCODE_BREAK
);
5766 case nir_jump_continue
:
5767 bld
.emit(BRW_OPCODE_CONTINUE
);
5769 case nir_jump_return
:
5771 unreachable("unknown jump");
5776 * This helper takes a source register and un/shuffles it into the destination
5779 * If source type size is smaller than destination type size the operation
5780 * needed is a component shuffle. The opposite case would be an unshuffle. If
5781 * source/destination type size is equal a shuffle is done that would be
5782 * equivalent to a simple MOV.
5784 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5785 * components .xyz 16-bit vector on SIMD8 would be.
5787 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5788 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5790 * This helper will return the following 2 32-bit components with the 16-bit
5793 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5794 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5796 * For unshuffle, the example would be the opposite, a 64-bit type source
5797 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5800 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5801 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5802 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5803 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5805 * The returned result would be the following 4 32-bit components unshuffled:
5807 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5808 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5809 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5810 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5812 * - Source and destination register must not be overlapped.
5813 * - components units are measured in terms of the smaller type between
5814 * source and destination because we are un/shuffling the smaller
5815 * components from/into the bigger ones.
5816 * - first_component parameter allows skipping source components.
5819 shuffle_src_to_dst(const fs_builder
&bld
,
5822 uint32_t first_component
,
5823 uint32_t components
)
5825 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5826 assert(!regions_overlap(dst
,
5827 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5828 offset(src
, bld
, first_component
),
5829 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5830 for (unsigned i
= 0; i
< components
; i
++) {
5831 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5832 offset(src
, bld
, i
+ first_component
));
5834 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5835 /* Source is shuffled into destination */
5836 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5837 assert(!regions_overlap(dst
,
5838 type_sz(dst
.type
) * bld
.dispatch_width() *
5839 DIV_ROUND_UP(components
, size_ratio
),
5840 offset(src
, bld
, first_component
),
5841 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5843 brw_reg_type shuffle_type
=
5844 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5845 BRW_REGISTER_TYPE_D
);
5846 for (unsigned i
= 0; i
< components
; i
++) {
5847 fs_reg shuffle_component_i
=
5848 subscript(offset(dst
, bld
, i
/ size_ratio
),
5849 shuffle_type
, i
% size_ratio
);
5850 bld
.MOV(shuffle_component_i
,
5851 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5854 /* Source is unshuffled into destination */
5855 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5856 assert(!regions_overlap(dst
,
5857 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5858 offset(src
, bld
, first_component
/ size_ratio
),
5859 type_sz(src
.type
) * bld
.dispatch_width() *
5860 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5863 brw_reg_type shuffle_type
=
5864 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5865 BRW_REGISTER_TYPE_D
);
5866 for (unsigned i
= 0; i
< components
; i
++) {
5867 fs_reg shuffle_component_i
=
5868 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5869 shuffle_type
, (first_component
+ i
) % size_ratio
);
5870 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5871 shuffle_component_i
);
5877 shuffle_from_32bit_read(const fs_builder
&bld
,
5880 uint32_t first_component
,
5881 uint32_t components
)
5883 assert(type_sz(src
.type
) == 4);
5885 /* This function takes components in units of the destination type while
5886 * shuffle_src_to_dst takes components in units of the smallest type
5888 if (type_sz(dst
.type
) > 4) {
5889 assert(type_sz(dst
.type
) == 8);
5890 first_component
*= 2;
5894 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5898 setup_imm_df(const fs_builder
&bld
, double v
)
5900 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5901 assert(devinfo
->gen
>= 7);
5903 if (devinfo
->gen
>= 8)
5904 return brw_imm_df(v
);
5906 /* gen7.5 does not support DF immediates straighforward but the DIM
5907 * instruction allows to set the 64-bit immediate value.
5909 if (devinfo
->is_haswell
) {
5910 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5911 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5912 ubld
.DIM(dst
, brw_imm_df(v
));
5913 return component(dst
, 0);
5916 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5917 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5918 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5920 * Alternatively, we could also produce a normal VGRF (without stride 0)
5921 * by writing to all the channels in the VGRF, however, that would hit the
5922 * gen7 bug where we have to split writes that span more than 1 register
5923 * into instructions with a width of 4 (otherwise the write to the second
5924 * register written runs into an execmask hardware bug) which isn't very
5937 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5938 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5939 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5940 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5942 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5946 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5948 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5949 bld
.MOV(tmp
, brw_imm_w(v
));
5954 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5956 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5957 bld
.MOV(tmp
, brw_imm_uw(v
));