2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
45 last_scratch
= ALIGN(nir
->scratch_size
, 4) * dispatch_width
;
47 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
, true);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add a uniform for the thread local id. It must be the last uniform
107 assert(uniforms
== prog_data
->nr_params
);
108 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
109 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
110 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 case nir_intrinsic_load_base_vertex
:
127 unreachable("should be lowered by nir_lower_system_values().");
129 case nir_intrinsic_load_vertex_id_zero_base
:
130 case nir_intrinsic_load_is_indexed_draw
:
131 case nir_intrinsic_load_first_vertex
:
132 case nir_intrinsic_load_instance_id
:
133 case nir_intrinsic_load_base_instance
:
134 case nir_intrinsic_load_draw_id
:
135 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
137 case nir_intrinsic_load_invocation_id
:
138 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
140 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
141 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
142 if (reg
->file
== BAD_FILE
) {
143 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
144 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
145 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
146 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
151 case nir_intrinsic_load_sample_pos
:
152 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
154 if (reg
->file
== BAD_FILE
)
155 *reg
= *v
->emit_samplepos_setup();
158 case nir_intrinsic_load_sample_id
:
159 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
160 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
161 if (reg
->file
== BAD_FILE
)
162 *reg
= *v
->emit_sampleid_setup();
165 case nir_intrinsic_load_sample_mask_in
:
166 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
167 assert(v
->devinfo
->gen
>= 7);
168 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
169 if (reg
->file
== BAD_FILE
)
170 *reg
= *v
->emit_samplemaskin_setup();
173 case nir_intrinsic_load_work_group_id
:
174 assert(v
->stage
== MESA_SHADER_COMPUTE
);
175 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
176 if (reg
->file
== BAD_FILE
)
177 *reg
= *v
->emit_cs_work_group_id_setup();
180 case nir_intrinsic_load_helper_invocation
:
181 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
182 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
183 if (reg
->file
== BAD_FILE
) {
184 const fs_builder abld
=
185 v
->bld
.annotate("gl_HelperInvocation", NULL
);
187 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
188 * pixel mask is in g1.7 of the thread payload.
190 * We move the per-channel pixel enable bit to the low bit of each
191 * channel by shifting the byte containing the pixel mask by the
192 * vector immediate 0x76543210UV.
194 * The region of <1,8,0> reads only 1 byte (the pixel masks for
195 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
196 * masks for 2 and 3) in SIMD16.
198 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
200 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
201 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
202 hbld
.SHR(offset(shifted
, hbld
, i
),
203 stride(retype(brw_vec1_grf(1 + i
, 7),
204 BRW_REGISTER_TYPE_UB
),
206 brw_imm_v(0x76543210));
209 /* A set bit in the pixel mask means the channel is enabled, but
210 * that is the opposite of gl_HelperInvocation so we need to invert
213 * The negate source-modifier bit of logical instructions on Gen8+
214 * performs 1's complement negation, so we can use that instead of
217 fs_reg inverted
= negate(shifted
);
218 if (v
->devinfo
->gen
< 8) {
219 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
220 abld
.NOT(inverted
, shifted
);
223 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
224 * with 1 and negating.
226 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
227 abld
.AND(anded
, inverted
, brw_imm_uw(1));
229 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
230 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
244 fs_visitor::nir_emit_system_values()
246 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
247 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
248 nir_system_values
[i
] = fs_reg();
251 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
252 * never end up using it.
255 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
256 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
257 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
259 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
260 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
261 if (dispatch_width
> 8)
262 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
263 if (dispatch_width
> 16) {
264 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
265 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
269 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
270 nir_foreach_block(block
, impl
)
271 emit_system_values_block(block
, this);
275 * Returns a type based on a reference_type (word, float, half-float) and a
278 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
280 * @FIXME: 64-bit return types are always DF on integer types to maintain
281 * compability with uses of DF previously to the introduction of int64
285 brw_reg_type_from_bit_size(const unsigned bit_size
,
286 const brw_reg_type reference_type
)
288 switch(reference_type
) {
289 case BRW_REGISTER_TYPE_HF
:
290 case BRW_REGISTER_TYPE_F
:
291 case BRW_REGISTER_TYPE_DF
:
294 return BRW_REGISTER_TYPE_HF
;
296 return BRW_REGISTER_TYPE_F
;
298 return BRW_REGISTER_TYPE_DF
;
300 unreachable("Invalid bit size");
302 case BRW_REGISTER_TYPE_B
:
303 case BRW_REGISTER_TYPE_W
:
304 case BRW_REGISTER_TYPE_D
:
305 case BRW_REGISTER_TYPE_Q
:
308 return BRW_REGISTER_TYPE_B
;
310 return BRW_REGISTER_TYPE_W
;
312 return BRW_REGISTER_TYPE_D
;
314 return BRW_REGISTER_TYPE_Q
;
316 unreachable("Invalid bit size");
318 case BRW_REGISTER_TYPE_UB
:
319 case BRW_REGISTER_TYPE_UW
:
320 case BRW_REGISTER_TYPE_UD
:
321 case BRW_REGISTER_TYPE_UQ
:
324 return BRW_REGISTER_TYPE_UB
;
326 return BRW_REGISTER_TYPE_UW
;
328 return BRW_REGISTER_TYPE_UD
;
330 return BRW_REGISTER_TYPE_UQ
;
332 unreachable("Invalid bit size");
335 unreachable("Unknown type");
340 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
342 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
343 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
344 nir_locals
[i
] = fs_reg();
347 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
348 unsigned array_elems
=
349 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
350 unsigned size
= array_elems
* reg
->num_components
;
351 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
352 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
353 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
356 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
359 nir_emit_cf_list(&impl
->body
);
363 fs_visitor::nir_emit_cf_list(exec_list
*list
)
365 exec_list_validate(list
);
366 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
367 switch (node
->type
) {
369 nir_emit_if(nir_cf_node_as_if(node
));
372 case nir_cf_node_loop
:
373 nir_emit_loop(nir_cf_node_as_loop(node
));
376 case nir_cf_node_block
:
377 nir_emit_block(nir_cf_node_as_block(node
));
381 unreachable("Invalid CFG node block");
387 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
392 /* If the condition has the form !other_condition, use other_condition as
393 * the source, but invert the predicate on the if instruction.
395 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
396 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
397 assert(!cond
->src
[0].negate
);
398 assert(!cond
->src
[0].abs
);
401 cond_reg
= get_nir_src(cond
->src
[0].src
);
404 cond_reg
= get_nir_src(if_stmt
->condition
);
407 /* first, put the condition into f0 */
408 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
409 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
410 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
412 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
414 nir_emit_cf_list(&if_stmt
->then_list
);
416 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
417 bld
.emit(BRW_OPCODE_ELSE
);
418 nir_emit_cf_list(&if_stmt
->else_list
);
421 bld
.emit(BRW_OPCODE_ENDIF
);
423 if (devinfo
->gen
< 7)
424 limit_dispatch_width(16, "Non-uniform control flow unsupported "
429 fs_visitor::nir_emit_loop(nir_loop
*loop
)
431 bld
.emit(BRW_OPCODE_DO
);
433 nir_emit_cf_list(&loop
->body
);
435 bld
.emit(BRW_OPCODE_WHILE
);
437 if (devinfo
->gen
< 7)
438 limit_dispatch_width(16, "Non-uniform control flow unsupported "
443 fs_visitor::nir_emit_block(nir_block
*block
)
445 nir_foreach_instr(instr
, block
) {
446 nir_emit_instr(instr
);
451 fs_visitor::nir_emit_instr(nir_instr
*instr
)
453 const fs_builder abld
= bld
.annotate(NULL
, instr
);
455 switch (instr
->type
) {
456 case nir_instr_type_alu
:
457 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
460 case nir_instr_type_deref
:
461 unreachable("All derefs should've been lowered");
464 case nir_instr_type_intrinsic
:
466 case MESA_SHADER_VERTEX
:
467 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_CTRL
:
470 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_TESS_EVAL
:
473 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_GEOMETRY
:
476 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_FRAGMENT
:
479 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
481 case MESA_SHADER_COMPUTE
:
482 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
485 unreachable("unsupported shader stage");
489 case nir_instr_type_tex
:
490 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
493 case nir_instr_type_load_const
:
494 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
497 case nir_instr_type_ssa_undef
:
498 /* We create a new VGRF for undefs on every use (by handling
499 * them in get_nir_src()), rather than for each definition.
500 * This helps register coalescing eliminate MOVs from undef.
504 case nir_instr_type_jump
:
505 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
509 unreachable("unknown instruction type");
514 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
518 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
519 const fs_reg
&result
)
521 if (!instr
->src
[0].src
.is_ssa
||
522 !instr
->src
[0].src
.ssa
->parent_instr
)
525 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
528 nir_alu_instr
*src0
=
529 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
531 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
532 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
535 /* If either opcode has source modifiers, bail.
537 * TODO: We can potentially handle source modifiers if both of the opcodes
538 * we're combining are signed integers.
540 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
541 src0
->src
[0].abs
|| src0
->src
[0].negate
)
544 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
546 /* Element type to extract.*/
547 const brw_reg_type type
= brw_int_type(
548 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
549 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
551 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
552 op0
.type
= brw_type_for_nir_type(devinfo
,
553 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
554 nir_src_bit_size(src0
->src
[0].src
)));
555 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
557 set_saturate(instr
->dest
.saturate
,
558 bld
.MOV(result
, subscript(op0
, type
, element
)));
563 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
564 const fs_reg
&result
)
566 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
567 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
570 if (!nir_src_is_const(instr
->src
[1].src
) ||
571 !nir_src_is_const(instr
->src
[2].src
))
574 const float value1
= nir_src_as_float(instr
->src
[1].src
);
575 const float value2
= nir_src_as_float(instr
->src
[2].src
);
576 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
579 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
580 assert(value1
== -value2
);
582 fs_reg tmp
= vgrf(glsl_type::int_type
);
584 if (devinfo
->gen
>= 12) {
585 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
586 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
588 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
590 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
591 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
593 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
595 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
596 g1
, brw_imm_uw(0x3f80));
599 bld
.MOV(tmp
, negate(tmp
));
601 } else if (devinfo
->gen
>= 6) {
602 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
603 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
605 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
607 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
608 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
610 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
612 * This negation looks like it's safe in practice, because bits 0:4 will
613 * surely be TRIANGLES
616 if (value1
== -1.0f
) {
620 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
621 g0
, brw_imm_uw(0x3f80));
623 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
624 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
626 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
628 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
629 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
631 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
633 * This negation looks like it's safe in practice, because bits 0:4 will
634 * surely be TRIANGLES
637 if (value1
== -1.0f
) {
641 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
643 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
649 emit_find_msb_using_lzd(const fs_builder
&bld
,
650 const fs_reg
&result
,
658 /* LZD of an absolute value source almost always does the right
659 * thing. There are two problem values:
661 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
662 * 0. However, findMSB(int(0x80000000)) == 30.
664 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
665 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
667 * For a value of zero or negative one, -1 will be returned.
669 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
670 * findMSB(-(1<<x)) should return x-1.
672 * For all negative number cases, including 0x80000000 and
673 * 0xffffffff, the correct value is obtained from LZD if instead of
674 * negating the (already negative) value the logical-not is used. A
675 * conditonal logical-not can be achieved in two instructions.
677 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
679 bld
.ASR(temp
, src
, brw_imm_d(31));
680 bld
.XOR(temp
, temp
, src
);
683 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
684 retype(temp
, BRW_REGISTER_TYPE_UD
));
686 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
687 * from the LSB side. Subtract the result from 31 to convert the MSB
688 * count into an LSB count. If no bits are set, LZD will return 32.
689 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
691 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
692 inst
->src
[0].negate
= true;
696 brw_rnd_mode_from_nir_op (const nir_op op
) {
698 case nir_op_f2f16_rtz
:
699 return BRW_RND_MODE_RTZ
;
700 case nir_op_f2f16_rtne
:
701 return BRW_RND_MODE_RTNE
;
703 unreachable("Operation doesn't support rounding mode");
708 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
710 if (nir_has_any_rounding_mode_rtne(execution_mode
))
711 return BRW_RND_MODE_RTNE
;
712 if (nir_has_any_rounding_mode_rtz(execution_mode
))
713 return BRW_RND_MODE_RTZ
;
714 return BRW_RND_MODE_UNSPECIFIED
;
718 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
719 nir_alu_instr
*instr
,
724 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
726 result
.type
= brw_type_for_nir_type(devinfo
,
727 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
728 nir_dest_bit_size(instr
->dest
.dest
)));
730 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
731 op
[i
] = get_nir_src(instr
->src
[i
].src
);
732 op
[i
].type
= brw_type_for_nir_type(devinfo
,
733 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
734 nir_src_bit_size(instr
->src
[i
].src
)));
735 op
[i
].abs
= instr
->src
[i
].abs
;
736 op
[i
].negate
= instr
->src
[i
].negate
;
739 /* Move and vecN instrutions may still be vectored. Return the raw,
740 * vectored source and destination so that fs_visitor::nir_emit_alu can
741 * handle it. Other callers should not have to handle these kinds of
754 /* At this point, we have dealt with any instruction that operates on
755 * more than a single channel. Therefore, we can just adjust the source
756 * and destination registers for that channel and emit the instruction.
758 unsigned channel
= 0;
759 if (nir_op_infos
[instr
->op
].output_size
== 0) {
760 /* Since NIR is doing the scalarizing for us, we should only ever see
761 * vectorized operations with a single channel.
763 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
764 channel
= ffs(instr
->dest
.write_mask
) - 1;
766 result
= offset(result
, bld
, channel
);
769 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
770 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
771 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
778 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
781 for (unsigned i
= 0; i
< 2; i
++) {
782 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
784 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
785 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
786 /* The source of the inot is now the source of instr. */
787 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
789 assert(!op
[i
].negate
);
792 op
[i
] = resolve_source_modifiers(op
[i
]);
798 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
800 nir_alu_instr
*instr
)
802 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
805 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
807 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
810 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
811 * of valid size-changing combinations is a bit more complex.
813 * The source restriction is just because I was lazy about generating the
816 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
817 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
820 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
821 * this is float(1 + a).
825 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
827 /* Ignore the saturate modifier, if there is one. The result of the
828 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
830 bld
.ADD(result
, op
, brw_imm_d(1));
836 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
838 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
839 * the source of \c instr that is a \c nir_op_fsign.
842 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
843 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
847 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
848 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
850 if (instr
->op
!= nir_op_fsign
) {
851 const nir_alu_instr
*const fsign_instr
=
852 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
854 assert(!fsign_instr
->dest
.saturate
);
856 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
857 * fsign_src] has the other multiply source. This must be rearranged so
858 * that op[0] is the source of the fsign op[1] is the other multiply
864 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
866 const nir_alu_type t
=
867 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
868 nir_src_bit_size(fsign_instr
->src
[0].src
));
870 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
871 op
[0].abs
= fsign_instr
->src
[0].abs
;
872 op
[0].negate
= fsign_instr
->src
[0].negate
;
874 unsigned channel
= 0;
875 if (nir_op_infos
[instr
->op
].output_size
== 0) {
876 /* Since NIR is doing the scalarizing for us, we should only ever see
877 * vectorized operations with a single channel.
879 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
880 channel
= ffs(instr
->dest
.write_mask
) - 1;
883 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
885 assert(!instr
->dest
.saturate
);
889 /* Straightforward since the source can be assumed to be either strictly
890 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
892 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
894 if (instr
->op
== nir_op_fsign
) {
895 inst
= (op
[0].negate
)
896 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
897 : bld
.MOV(result
, brw_imm_f(1.0f
));
899 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
900 inst
= bld
.MOV(result
, op
[1]);
903 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
904 } else if (type_sz(op
[0].type
) == 2) {
905 /* AND(val, 0x8000) gives the sign bit.
907 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
909 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
910 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
912 op
[0].type
= BRW_REGISTER_TYPE_UW
;
913 result
.type
= BRW_REGISTER_TYPE_UW
;
914 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
916 if (instr
->op
== nir_op_fsign
)
917 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
919 /* Use XOR here to get the result sign correct. */
920 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
923 inst
->predicate
= BRW_PREDICATE_NORMAL
;
924 } else if (type_sz(op
[0].type
) == 4) {
925 /* AND(val, 0x80000000) gives the sign bit.
927 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
930 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
932 op
[0].type
= BRW_REGISTER_TYPE_UD
;
933 result
.type
= BRW_REGISTER_TYPE_UD
;
934 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
936 if (instr
->op
== nir_op_fsign
)
937 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
939 /* Use XOR here to get the result sign correct. */
940 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
943 inst
->predicate
= BRW_PREDICATE_NORMAL
;
945 /* For doubles we do the same but we need to consider:
947 * - 2-src instructions can't operate with 64-bit immediates
948 * - The sign is encoded in the high 32-bit of each DF
949 * - We need to produce a DF result.
952 fs_reg zero
= vgrf(glsl_type::double_type
);
953 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
954 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
956 bld
.MOV(result
, zero
);
958 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
959 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
960 brw_imm_ud(0x80000000u
));
962 if (instr
->op
== nir_op_fsign
) {
963 set_predicate(BRW_PREDICATE_NORMAL
,
964 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
966 /* This could be done better in some cases. If the scale is an
967 * immediate with the low 32-bits all 0, emitting a separate XOR and
968 * OR would allow an algebraic optimization to remove the OR. There
969 * are currently zero instances of fsign(double(x))*IMM in shader-db
970 * or any test suite, so it is hard to care at this time.
972 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
973 inst
= bld
.XOR(result_int64
, result_int64
,
974 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
980 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
982 * Checks the operands of a \c nir_op_fmul to determine whether or not
983 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
985 * \param instr The multiplication instruction
987 * \param fsign_src The source of \c instr that may or may not be a
991 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
993 assert(instr
->op
== nir_op_fmul
);
995 nir_alu_instr
*const fsign_instr
=
996 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
1000 * 1. instr->src[fsign_src] must be a nir_op_fsign.
1001 * 2. The nir_op_fsign can only be used by this multiplication.
1002 * 3. The source that is the nir_op_fsign does not have source modifiers.
1003 * \c emit_fsign only examines the source modifiers of the source of the
1006 * The nir_op_fsign must also not have the saturate modifier, but steps
1007 * have already been taken (in nir_opt_algebraic) to ensure that.
1009 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
1010 is_used_once(fsign_instr
) &&
1011 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
1015 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1018 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1020 unsigned execution_mode
=
1021 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1024 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1026 switch (instr
->op
) {
1031 fs_reg temp
= result
;
1032 bool need_extra_copy
= false;
1033 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1034 if (!instr
->src
[i
].src
.is_ssa
&&
1035 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1036 need_extra_copy
= true;
1037 temp
= bld
.vgrf(result
.type
, 4);
1042 for (unsigned i
= 0; i
< 4; i
++) {
1043 if (!(instr
->dest
.write_mask
& (1 << i
)))
1046 if (instr
->op
== nir_op_mov
) {
1047 inst
= bld
.MOV(offset(temp
, bld
, i
),
1048 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1050 inst
= bld
.MOV(offset(temp
, bld
, i
),
1051 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1053 inst
->saturate
= instr
->dest
.saturate
;
1056 /* In this case the source and destination registers were the same,
1057 * so we need to insert an extra set of moves in order to deal with
1060 if (need_extra_copy
) {
1061 for (unsigned i
= 0; i
< 4; i
++) {
1062 if (!(instr
->dest
.write_mask
& (1 << i
)))
1065 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1073 if (optimize_extract_to_float(instr
, result
))
1075 inst
= bld
.MOV(result
, op
[0]);
1076 inst
->saturate
= instr
->dest
.saturate
;
1079 case nir_op_f2f16_rtne
:
1080 case nir_op_f2f16_rtz
:
1081 case nir_op_f2f16
: {
1082 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1084 if (nir_op_f2f16
== instr
->op
)
1085 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1087 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1089 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1090 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1092 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1093 * on the HW gen, it is a special hw opcode or just a MOV, and
1094 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1096 * But if we want to use that opcode, we need to provide support on
1097 * different optimizations and lowerings. As right now HF support is
1098 * only for gen8+, it will be better to use directly the MOV, and use
1099 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1101 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1102 inst
= bld
.MOV(result
, op
[0]);
1103 inst
->saturate
= instr
->dest
.saturate
;
1114 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1116 op
[0].type
= BRW_REGISTER_TYPE_D
;
1117 op
[0].negate
= !op
[0].negate
;
1140 if (result
.type
== BRW_REGISTER_TYPE_B
||
1141 result
.type
== BRW_REGISTER_TYPE_UB
||
1142 result
.type
== BRW_REGISTER_TYPE_HF
)
1143 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1145 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1146 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1147 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1148 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1150 inst
= bld
.MOV(result
, op
[0]);
1151 inst
->saturate
= instr
->dest
.saturate
;
1155 inst
= bld
.MOV(result
, op
[0]);
1156 inst
->saturate
= true;
1161 op
[0].negate
= true;
1162 inst
= bld
.MOV(result
, op
[0]);
1163 if (instr
->op
== nir_op_fneg
)
1164 inst
->saturate
= instr
->dest
.saturate
;
1169 op
[0].negate
= false;
1171 inst
= bld
.MOV(result
, op
[0]);
1172 if (instr
->op
== nir_op_fabs
)
1173 inst
->saturate
= instr
->dest
.saturate
;
1177 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1179 brw_rnd_mode_from_execution_mode(execution_mode
);
1180 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1184 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1185 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1187 inst
= bld
.MOV(result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1192 emit_fsign(bld
, instr
, result
, op
, 0);
1196 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1197 inst
->saturate
= instr
->dest
.saturate
;
1201 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1206 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1207 inst
->saturate
= instr
->dest
.saturate
;
1211 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1212 inst
->saturate
= instr
->dest
.saturate
;
1216 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1217 inst
->saturate
= instr
->dest
.saturate
;
1221 if (fs_key
->high_quality_derivatives
) {
1222 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1224 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1226 inst
->saturate
= instr
->dest
.saturate
;
1228 case nir_op_fddx_fine
:
1229 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1230 inst
->saturate
= instr
->dest
.saturate
;
1232 case nir_op_fddx_coarse
:
1233 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1234 inst
->saturate
= instr
->dest
.saturate
;
1237 if (fs_key
->high_quality_derivatives
) {
1238 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1240 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1242 inst
->saturate
= instr
->dest
.saturate
;
1244 case nir_op_fddy_fine
:
1245 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1246 inst
->saturate
= instr
->dest
.saturate
;
1248 case nir_op_fddy_coarse
:
1249 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1250 inst
->saturate
= instr
->dest
.saturate
;
1254 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1256 brw_rnd_mode_from_execution_mode(execution_mode
);
1257 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1262 inst
= bld
.ADD(result
, op
[0], op
[1]);
1263 inst
->saturate
= instr
->dest
.saturate
;
1266 case nir_op_iadd_sat
:
1267 case nir_op_uadd_sat
:
1268 inst
= bld
.ADD(result
, op
[0], op
[1]);
1269 inst
->saturate
= true;
1272 case nir_op_isub_sat
:
1273 bld
.emit(SHADER_OPCODE_ISUB_SAT
, result
, op
[0], op
[1]);
1276 case nir_op_usub_sat
:
1277 bld
.emit(SHADER_OPCODE_USUB_SAT
, result
, op
[0], op
[1]);
1282 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1283 inst
= bld
.AVG(result
, op
[0], op
[1]);
1287 case nir_op_uhadd
: {
1288 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1289 fs_reg tmp
= bld
.vgrf(result
.type
);
1291 if (devinfo
->gen
>= 8) {
1292 op
[0] = resolve_source_modifiers(op
[0]);
1293 op
[1] = resolve_source_modifiers(op
[1]);
1296 /* AVG(x, y) - ((x ^ y) & 1) */
1297 bld
.XOR(tmp
, op
[0], op
[1]);
1298 bld
.AND(tmp
, tmp
, retype(brw_imm_ud(1), result
.type
));
1299 bld
.AVG(result
, op
[0], op
[1]);
1300 inst
= bld
.ADD(result
, result
, tmp
);
1301 inst
->src
[1].negate
= true;
1306 for (unsigned i
= 0; i
< 2; i
++) {
1307 if (can_fuse_fmul_fsign(instr
, i
)) {
1308 emit_fsign(bld
, instr
, result
, op
, i
);
1313 /* We emit the rounding mode after the previous fsign optimization since
1314 * it won't result in a MUL, but will try to negate the value by other
1317 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1319 brw_rnd_mode_from_execution_mode(execution_mode
);
1320 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1324 inst
= bld
.MUL(result
, op
[0], op
[1]);
1325 inst
->saturate
= instr
->dest
.saturate
;
1328 case nir_op_imul_2x32_64
:
1329 case nir_op_umul_2x32_64
:
1330 bld
.MUL(result
, op
[0], op
[1]);
1333 case nir_op_imul_32x16
:
1334 case nir_op_umul_32x16
: {
1335 const bool ud
= instr
->op
== nir_op_umul_32x16
;
1337 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1339 /* Before Gen7, the order of the 32-bit source and the 16-bit source was
1340 * swapped. The extension isn't enabled on those platforms, so don't
1341 * pretend to support the differences.
1343 assert(devinfo
->gen
>= 7);
1345 if (op
[1].file
== IMM
)
1346 op
[1] = ud
? brw_imm_uw(op
[1].ud
) : brw_imm_w(op
[1].d
);
1348 const enum brw_reg_type word_type
=
1349 ud
? BRW_REGISTER_TYPE_UW
: BRW_REGISTER_TYPE_W
;
1351 op
[1] = subscript(op
[1], word_type
, 0);
1354 const enum brw_reg_type dword_type
=
1355 ud
? BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_D
;
1357 bld
.MUL(result
, retype(op
[0], dword_type
), op
[1]);
1362 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1363 bld
.MUL(result
, op
[0], op
[1]);
1366 case nir_op_imul_high
:
1367 case nir_op_umul_high
:
1368 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1369 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1374 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1375 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1378 case nir_op_uadd_carry
:
1379 unreachable("Should have been lowered by carry_to_arith().");
1381 case nir_op_usub_borrow
:
1382 unreachable("Should have been lowered by borrow_to_arith().");
1386 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1387 * appears that our hardware just does the right thing for signed
1390 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1391 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1395 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1396 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1398 /* Math instructions don't support conditional mod */
1399 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1400 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1402 /* Now, we need to determine if signs of the sources are different.
1403 * When we XOR the sources, the top bit is 0 if they are the same and 1
1404 * if they are different. We can then use a conditional modifier to
1405 * turn that into a predicate. This leads us to an XOR.l instruction.
1407 * Technically, according to the PRM, you're not allowed to use .l on a
1408 * XOR instruction. However, emperical experiments and Curro's reading
1409 * of the simulator source both indicate that it's safe.
1411 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1412 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1413 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1414 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1416 /* If the result of the initial remainder operation is non-zero and the
1417 * two sources have different signs, add in a copy of op[1] to get the
1418 * final integer modulus value.
1420 inst
= bld
.ADD(result
, result
, op
[1]);
1421 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1428 case nir_op_fne32
: {
1429 fs_reg dest
= result
;
1431 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1433 dest
= bld
.vgrf(op
[0].type
, 1);
1435 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1437 if (bit_size
> 32) {
1438 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1439 } else if(bit_size
< 32) {
1440 /* When we convert the result to 32-bit we need to be careful and do
1441 * it as a signed conversion to get sign extension (for 32-bit true)
1443 const brw_reg_type src_type
=
1444 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1446 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1456 case nir_op_ine32
: {
1457 fs_reg dest
= result
;
1459 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1460 * type. So we convert both operands for the comparison.
1463 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1464 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1466 const uint32_t bit_size
= type_sz(temp_op
[0].type
) * 8;
1468 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1470 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1471 brw_cmod_for_nir_comparison(instr
->op
));
1473 if (bit_size
> 32) {
1474 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1475 } else if (bit_size
< 32) {
1476 /* When we convert the result to 32-bit we need to be careful and do
1477 * it as a signed conversion to get sign extension (for 32-bit true)
1479 const brw_reg_type src_type
=
1480 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1482 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1488 if (devinfo
->gen
>= 8) {
1489 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1491 if (inot_src_instr
!= NULL
&&
1492 (inot_src_instr
->op
== nir_op_ior
||
1493 inot_src_instr
->op
== nir_op_ixor
||
1494 inot_src_instr
->op
== nir_op_iand
) &&
1495 !inot_src_instr
->src
[0].abs
&&
1496 !inot_src_instr
->src
[0].negate
&&
1497 !inot_src_instr
->src
[1].abs
&&
1498 !inot_src_instr
->src
[1].negate
) {
1499 /* The sources of the source logical instruction are now the
1500 * sources of the instruction that will be generated.
1502 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1503 resolve_inot_sources(bld
, inot_src_instr
, op
);
1505 /* Smash all of the sources and destination to be signed. This
1506 * doesn't matter for the operation of the instruction, but cmod
1507 * propagation fails on unsigned sources with negation (due to
1508 * fs_inst::can_do_cmod returning false).
1511 brw_type_for_nir_type(devinfo
,
1512 (nir_alu_type
)(nir_type_int
|
1513 nir_dest_bit_size(instr
->dest
.dest
)));
1515 brw_type_for_nir_type(devinfo
,
1516 (nir_alu_type
)(nir_type_int
|
1517 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1519 brw_type_for_nir_type(devinfo
,
1520 (nir_alu_type
)(nir_type_int
|
1521 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1523 /* For XOR, only invert one of the sources. Arbitrarily choose
1526 op
[0].negate
= !op
[0].negate
;
1527 if (inot_src_instr
->op
!= nir_op_ixor
)
1528 op
[1].negate
= !op
[1].negate
;
1530 switch (inot_src_instr
->op
) {
1532 bld
.AND(result
, op
[0], op
[1]);
1536 bld
.OR(result
, op
[0], op
[1]);
1540 bld
.XOR(result
, op
[0], op
[1]);
1544 unreachable("impossible opcode");
1547 op
[0] = resolve_source_modifiers(op
[0]);
1549 bld
.NOT(result
, op
[0]);
1552 if (devinfo
->gen
>= 8) {
1553 resolve_inot_sources(bld
, instr
, op
);
1555 bld
.XOR(result
, op
[0], op
[1]);
1558 if (devinfo
->gen
>= 8) {
1559 resolve_inot_sources(bld
, instr
, op
);
1561 bld
.OR(result
, op
[0], op
[1]);
1564 if (devinfo
->gen
>= 8) {
1565 resolve_inot_sources(bld
, instr
, op
);
1567 bld
.AND(result
, op
[0], op
[1]);
1573 case nir_op_b32all_fequal2
:
1574 case nir_op_b32all_iequal2
:
1575 case nir_op_b32all_fequal3
:
1576 case nir_op_b32all_iequal3
:
1577 case nir_op_b32all_fequal4
:
1578 case nir_op_b32all_iequal4
:
1579 case nir_op_b32any_fnequal2
:
1580 case nir_op_b32any_inequal2
:
1581 case nir_op_b32any_fnequal3
:
1582 case nir_op_b32any_inequal3
:
1583 case nir_op_b32any_fnequal4
:
1584 case nir_op_b32any_inequal4
:
1585 unreachable("Lowered by nir_lower_alu_reductions");
1587 case nir_op_fnoise1_1
:
1588 case nir_op_fnoise1_2
:
1589 case nir_op_fnoise1_3
:
1590 case nir_op_fnoise1_4
:
1591 case nir_op_fnoise2_1
:
1592 case nir_op_fnoise2_2
:
1593 case nir_op_fnoise2_3
:
1594 case nir_op_fnoise2_4
:
1595 case nir_op_fnoise3_1
:
1596 case nir_op_fnoise3_2
:
1597 case nir_op_fnoise3_3
:
1598 case nir_op_fnoise3_4
:
1599 case nir_op_fnoise4_1
:
1600 case nir_op_fnoise4_2
:
1601 case nir_op_fnoise4_3
:
1602 case nir_op_fnoise4_4
:
1603 unreachable("not reached: should be handled by lower_noise");
1606 unreachable("not reached: should be handled by ldexp_to_arith()");
1609 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1610 inst
->saturate
= instr
->dest
.saturate
;
1614 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1615 inst
->saturate
= instr
->dest
.saturate
;
1619 case nir_op_f2b32
: {
1620 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1621 if (bit_size
== 64) {
1622 /* two-argument instructions can't take 64-bit immediates */
1626 if (instr
->op
== nir_op_f2b32
) {
1627 zero
= vgrf(glsl_type::double_type
);
1628 tmp
= vgrf(glsl_type::double_type
);
1629 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1631 zero
= vgrf(glsl_type::int64_t_type
);
1632 tmp
= vgrf(glsl_type::int64_t_type
);
1633 bld
.MOV(zero
, brw_imm_q(0));
1636 /* A SIMD16 execution needs to be split in two instructions, so use
1637 * a vgrf instead of the flag register as dst so instruction splitting
1640 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1641 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1644 if (bit_size
== 32) {
1645 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1647 assert(bit_size
== 16);
1648 zero
= instr
->op
== nir_op_f2b32
?
1649 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1651 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1657 inst
= bld
.RNDZ(result
, op
[0]);
1658 if (devinfo
->gen
< 6) {
1659 set_condmod(BRW_CONDITIONAL_R
, inst
);
1660 set_predicate(BRW_PREDICATE_NORMAL
,
1661 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1662 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1664 inst
->saturate
= instr
->dest
.saturate
;
1667 case nir_op_fceil
: {
1668 op
[0].negate
= !op
[0].negate
;
1669 fs_reg temp
= vgrf(glsl_type::float_type
);
1670 bld
.RNDD(temp
, op
[0]);
1672 inst
= bld
.MOV(result
, temp
);
1673 inst
->saturate
= instr
->dest
.saturate
;
1677 inst
= bld
.RNDD(result
, op
[0]);
1678 inst
->saturate
= instr
->dest
.saturate
;
1681 inst
= bld
.FRC(result
, op
[0]);
1682 inst
->saturate
= instr
->dest
.saturate
;
1684 case nir_op_fround_even
:
1685 inst
= bld
.RNDE(result
, op
[0]);
1686 if (devinfo
->gen
< 6) {
1687 set_condmod(BRW_CONDITIONAL_R
, inst
);
1688 set_predicate(BRW_PREDICATE_NORMAL
,
1689 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1690 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1692 inst
->saturate
= instr
->dest
.saturate
;
1695 case nir_op_fquantize2f16
: {
1696 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1697 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1698 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1700 /* The destination stride must be at least as big as the source stride. */
1701 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1704 /* Check for denormal */
1705 fs_reg abs_src0
= op
[0];
1706 abs_src0
.abs
= true;
1707 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1709 /* Get the appropriately signed zero */
1710 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1711 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1712 brw_imm_ud(0x80000000));
1713 /* Do the actual F32 -> F16 -> F32 conversion */
1714 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1715 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1716 /* Select that or zero based on normal status */
1717 inst
= bld
.SEL(result
, zero
, tmp32
);
1718 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1719 inst
->saturate
= instr
->dest
.saturate
;
1726 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1727 inst
->saturate
= instr
->dest
.saturate
;
1733 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1734 inst
->saturate
= instr
->dest
.saturate
;
1737 case nir_op_pack_snorm_2x16
:
1738 case nir_op_pack_snorm_4x8
:
1739 case nir_op_pack_unorm_2x16
:
1740 case nir_op_pack_unorm_4x8
:
1741 case nir_op_unpack_snorm_2x16
:
1742 case nir_op_unpack_snorm_4x8
:
1743 case nir_op_unpack_unorm_2x16
:
1744 case nir_op_unpack_unorm_4x8
:
1745 case nir_op_unpack_half_2x16
:
1746 case nir_op_pack_half_2x16
:
1747 unreachable("not reached: should be handled by lower_packing_builtins");
1749 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1750 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1752 case nir_op_unpack_half_2x16_split_x
:
1753 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1754 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1755 inst
->saturate
= instr
->dest
.saturate
;
1758 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1759 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1761 case nir_op_unpack_half_2x16_split_y
:
1762 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1763 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1764 inst
->saturate
= instr
->dest
.saturate
;
1767 case nir_op_pack_64_2x32_split
:
1768 case nir_op_pack_32_2x16_split
:
1769 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1772 case nir_op_unpack_64_2x32_split_x
:
1773 case nir_op_unpack_64_2x32_split_y
: {
1774 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1775 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1777 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1781 case nir_op_unpack_32_2x16_split_x
:
1782 case nir_op_unpack_32_2x16_split_y
: {
1783 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1784 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1786 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1791 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1792 inst
->saturate
= instr
->dest
.saturate
;
1795 case nir_op_bitfield_reverse
:
1796 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1797 bld
.BFREV(result
, op
[0]);
1800 case nir_op_bit_count
:
1801 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1802 bld
.CBIT(result
, op
[0]);
1805 case nir_op_ufind_msb
: {
1806 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1807 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1812 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1813 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1816 case nir_op_ifind_msb
: {
1817 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1819 if (devinfo
->gen
< 7) {
1820 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1822 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1824 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1825 * count from the LSB side. If FBH didn't return an error
1826 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1827 * count into an LSB count.
1829 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1831 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1832 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1833 inst
->src
[0].negate
= true;
1838 case nir_op_find_lsb
:
1839 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1841 if (devinfo
->gen
< 7) {
1842 fs_reg temp
= vgrf(glsl_type::int_type
);
1844 /* (x & -x) generates a value that consists of only the LSB of x.
1845 * For all powers of 2, findMSB(y) == findLSB(y).
1847 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1848 fs_reg negated_src
= src
;
1850 /* One must be negated, and the other must be non-negated. It
1851 * doesn't matter which is which.
1853 negated_src
.negate
= true;
1856 bld
.AND(temp
, src
, negated_src
);
1857 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1859 bld
.FBL(result
, op
[0]);
1863 case nir_op_ubitfield_extract
:
1864 case nir_op_ibitfield_extract
:
1865 unreachable("should have been lowered");
1868 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1869 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1872 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1873 bld
.BFI1(result
, op
[0], op
[1]);
1876 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1877 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1880 case nir_op_bitfield_insert
:
1881 unreachable("not reached: should have been lowered");
1884 bld
.SHL(result
, op
[0], op
[1]);
1887 bld
.ASR(result
, op
[0], op
[1]);
1890 bld
.SHR(result
, op
[0], op
[1]);
1894 bld
.ROL(result
, op
[0], op
[1]);
1897 bld
.ROR(result
, op
[0], op
[1]);
1900 case nir_op_pack_half_2x16_split
:
1901 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1905 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1907 brw_rnd_mode_from_execution_mode(execution_mode
);
1908 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1912 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1913 inst
->saturate
= instr
->dest
.saturate
;
1917 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1919 brw_rnd_mode_from_execution_mode(execution_mode
);
1920 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1924 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1925 inst
->saturate
= instr
->dest
.saturate
;
1928 case nir_op_b32csel
:
1929 if (optimize_frontfacing_ternary(instr
, result
))
1932 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1933 inst
= bld
.SEL(result
, op
[1], op
[2]);
1934 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1937 case nir_op_extract_u8
:
1938 case nir_op_extract_i8
: {
1939 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1944 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1945 * Use two instructions and a word or DWord intermediate integer type.
1947 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1948 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1950 if (instr
->op
== nir_op_extract_i8
) {
1951 /* If we need to sign extend, extract to a word first */
1952 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1953 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1954 bld
.MOV(result
, w_temp
);
1955 } else if (byte
& 1) {
1956 /* Extract the high byte from the word containing the desired byte
1960 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1963 /* Otherwise use an AND with 0xff and a word type */
1965 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1969 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1970 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1975 case nir_op_extract_u16
:
1976 case nir_op_extract_i16
: {
1977 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1978 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1979 bld
.MOV(result
, subscript(op
[0], type
, word
));
1984 unreachable("unhandled instruction");
1987 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1988 * to sign extend the low bit to 0/~0
1990 if (devinfo
->gen
<= 5 &&
1991 !result
.is_null() &&
1992 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1993 fs_reg masked
= vgrf(glsl_type::int_type
);
1994 bld
.AND(masked
, result
, brw_imm_d(1));
1995 masked
.negate
= true;
1996 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
2001 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
2002 nir_load_const_instr
*instr
)
2004 const brw_reg_type reg_type
=
2005 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
2006 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
2008 switch (instr
->def
.bit_size
) {
2010 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2011 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
2015 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2016 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
2020 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2021 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
2025 assert(devinfo
->gen
>= 7);
2026 if (devinfo
->gen
== 7) {
2027 /* We don't get 64-bit integer types until gen8 */
2028 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
2029 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
2030 setup_imm_df(bld
, instr
->value
[i
].f64
));
2033 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2034 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
2039 unreachable("Invalid bit size");
2042 nir_ssa_values
[instr
->def
.index
] = reg
;
2046 fs_visitor::get_nir_src(const nir_src
&src
)
2050 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
2051 const brw_reg_type reg_type
=
2052 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
2053 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
2055 reg
= nir_ssa_values
[src
.ssa
->index
];
2058 /* We don't handle indirects on locals */
2059 assert(src
.reg
.indirect
== NULL
);
2060 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
2061 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
2064 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
2065 /* The only 64-bit type available on gen7 is DF, so use that. */
2066 reg
.type
= BRW_REGISTER_TYPE_DF
;
2068 /* To avoid floating-point denorm flushing problems, set the type by
2069 * default to an integer type - instructions that need floating point
2070 * semantics will set this to F if they need to
2072 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
2073 BRW_REGISTER_TYPE_D
);
2080 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2082 * This function should not be called on any value which may be 64 bits.
2083 * We could theoretically support 64-bit on gen8+ but we choose not to
2084 * because it wouldn't work in general (no gen7 support) and there are
2085 * enough restrictions in 64-bit immediates that you can't take the return
2086 * value and treat it the same as the result of get_nir_src().
2089 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2091 assert(nir_src_bit_size(src
) == 32);
2092 return nir_src_is_const(src
) ?
2093 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2097 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2100 const brw_reg_type reg_type
=
2101 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2102 dest
.ssa
.bit_size
== 8 ?
2103 BRW_REGISTER_TYPE_D
:
2104 BRW_REGISTER_TYPE_F
);
2105 nir_ssa_values
[dest
.ssa
.index
] =
2106 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2107 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2108 return nir_ssa_values
[dest
.ssa
.index
];
2110 /* We don't handle indirects on locals */
2111 assert(dest
.reg
.indirect
== NULL
);
2112 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2113 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2118 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2121 for (unsigned i
= 0; i
< 4; i
++) {
2122 if (!((wr_mask
>> i
) & 1))
2125 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2126 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2127 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2128 if (new_inst
->src
[j
].file
== VGRF
)
2129 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2136 emit_pixel_interpolater_send(const fs_builder
&bld
,
2141 glsl_interp_mode interpolation
)
2143 struct brw_wm_prog_data
*wm_prog_data
=
2144 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2146 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2147 /* 2 floats per slot returned */
2148 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2149 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2151 wm_prog_data
->pulls_bary
= true;
2157 * Computes 1 << x, given a D/UD register containing some value x.
2160 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2162 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2164 fs_reg result
= bld
.vgrf(x
.type
, 1);
2165 fs_reg one
= bld
.vgrf(x
.type
, 1);
2167 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2168 bld
.SHL(result
, one
, x
);
2173 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2175 assert(stage
== MESA_SHADER_GEOMETRY
);
2177 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2179 if (gs_compile
->control_data_header_size_bits
== 0)
2182 /* We can only do EndPrimitive() functionality when the control data
2183 * consists of cut bits. Fortunately, the only time it isn't is when the
2184 * output type is points, in which case EndPrimitive() is a no-op.
2186 if (gs_prog_data
->control_data_format
!=
2187 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2191 /* Cut bits use one bit per vertex. */
2192 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2194 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2195 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2197 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2198 * vertex n, 0 otherwise. So all we need to do here is mark bit
2199 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2200 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2201 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2203 * Note that if EndPrimitive() is called before emitting any vertices, this
2204 * will cause us to set bit 31 of the control_data_bits register to 1.
2205 * That's fine because:
2207 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2208 * output, so the hardware will ignore cut bit 31.
2210 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2211 * last vertex, so setting cut bit 31 has no effect (since the primitive
2212 * is automatically ended when the GS terminates).
2214 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2215 * control_data_bits register to 0 when the first vertex is emitted.
2218 const fs_builder abld
= bld
.annotate("end primitive");
2220 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2221 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2222 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2223 fs_reg mask
= intexp2(abld
, prev_count
);
2224 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2225 * attention to the lower 5 bits of its second source argument, so on this
2226 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2227 * ((vertex_count - 1) % 32).
2229 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2233 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2235 assert(stage
== MESA_SHADER_GEOMETRY
);
2236 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2238 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2240 const fs_builder abld
= bld
.annotate("emit control data bits");
2241 const fs_builder fwa_bld
= bld
.exec_all();
2243 /* We use a single UD register to accumulate control data bits (32 bits
2244 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2247 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2248 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2249 * use the Channel Mask phase to enable/disable which DWord within that
2250 * group to write. (Remember, different SIMD8 channels may have emitted
2251 * different numbers of vertices, so we may need per-slot offsets.)
2253 * Channel masking presents an annoying problem: we may have to replicate
2254 * the data up to 4 times:
2256 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2258 * To avoid penalizing shaders that emit a small number of vertices, we
2259 * can avoid these sometimes: if the size of the control data header is
2260 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2261 * land in the same 128-bit group, so we can skip per-slot offsets.
2263 * Similarly, if the control data header is <= 32 bits, there is only one
2264 * DWord, so we can skip channel masks.
2266 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2268 fs_reg channel_mask
, per_slot_offset
;
2270 if (gs_compile
->control_data_header_size_bits
> 32) {
2271 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2272 channel_mask
= vgrf(glsl_type::uint_type
);
2275 if (gs_compile
->control_data_header_size_bits
> 128) {
2276 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2277 per_slot_offset
= vgrf(glsl_type::uint_type
);
2280 /* Figure out which DWord we're trying to write to using the formula:
2282 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2284 * Since bits_per_vertex is a power of two, and is known at compile
2285 * time, this can be optimized to:
2287 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2289 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2290 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2291 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2292 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2293 unsigned log2_bits_per_vertex
=
2294 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2295 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2297 if (per_slot_offset
.file
!= BAD_FILE
) {
2298 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2299 * the appropriate OWord within the control data header.
2301 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2304 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2305 * write to the appropriate DWORD within the OWORD.
2307 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2308 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2309 channel_mask
= intexp2(fwa_bld
, channel
);
2310 /* Then the channel masks need to be in bits 23:16. */
2311 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2314 /* Store the control data bits in the message payload and send it. */
2316 if (channel_mask
.file
!= BAD_FILE
)
2317 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2318 if (per_slot_offset
.file
!= BAD_FILE
)
2321 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2322 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2324 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2325 if (per_slot_offset
.file
!= BAD_FILE
)
2326 sources
[i
++] = per_slot_offset
;
2327 if (channel_mask
.file
!= BAD_FILE
)
2328 sources
[i
++] = channel_mask
;
2330 sources
[i
++] = this->control_data_bits
;
2333 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2334 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2336 /* We need to increment Global Offset by 256-bits to make room for
2337 * Broadwell's extra "Vertex Count" payload at the beginning of the
2338 * URB entry. Since this is an OWord message, Global Offset is counted
2339 * in 128-bit units, so we must set it to 2.
2341 if (gs_prog_data
->static_vertex_count
== -1)
2346 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2349 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2351 /* Note: we are calling this *before* increasing vertex_count, so
2352 * this->vertex_count == vertex_count - 1 in the formula above.
2355 /* Stream mode uses 2 bits per vertex */
2356 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2358 /* Must be a valid stream */
2359 assert(stream_id
< MAX_VERTEX_STREAMS
);
2361 /* Control data bits are initialized to 0 so we don't have to set any
2362 * bits when sending vertices to stream 0.
2367 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2369 /* reg::sid = stream_id */
2370 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2371 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2373 /* reg:shift_count = 2 * (vertex_count - 1) */
2374 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2375 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2377 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2378 * attention to the lower 5 bits of its second source argument, so on this
2379 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2380 * stream_id << ((2 * (vertex_count - 1)) % 32).
2382 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2383 abld
.SHL(mask
, sid
, shift_count
);
2384 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2388 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2391 assert(stage
== MESA_SHADER_GEOMETRY
);
2393 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2395 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2396 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2398 /* Haswell and later hardware ignores the "Render Stream Select" bits
2399 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2400 * and instead sends all primitives down the pipeline for rasterization.
2401 * If the SOL stage is enabled, "Render Stream Select" is honored and
2402 * primitives bound to non-zero streams are discarded after stream output.
2404 * Since the only purpose of primives sent to non-zero streams is to
2405 * be recorded by transform feedback, we can simply discard all geometry
2406 * bound to these streams when transform feedback is disabled.
2408 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2411 /* If we're outputting 32 control data bits or less, then we can wait
2412 * until the shader is over to output them all. Otherwise we need to
2413 * output them as we go. Now is the time to do it, since we're about to
2414 * output the vertex_count'th vertex, so it's guaranteed that the
2415 * control data bits associated with the (vertex_count - 1)th vertex are
2418 if (gs_compile
->control_data_header_size_bits
> 32) {
2419 const fs_builder abld
=
2420 bld
.annotate("emit vertex: emit control data bits");
2422 /* Only emit control data bits if we've finished accumulating a batch
2423 * of 32 bits. This is the case when:
2425 * (vertex_count * bits_per_vertex) % 32 == 0
2427 * (in other words, when the last 5 bits of vertex_count *
2428 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2429 * integer n (which is always the case, since bits_per_vertex is
2430 * always 1 or 2), this is equivalent to requiring that the last 5-n
2431 * bits of vertex_count are 0:
2433 * vertex_count & (2^(5-n) - 1) == 0
2435 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2438 * vertex_count & (32 / bits_per_vertex - 1) == 0
2440 * TODO: If vertex_count is an immediate, we could do some of this math
2441 * at compile time...
2444 abld
.AND(bld
.null_reg_d(), vertex_count
,
2445 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2446 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2448 abld
.IF(BRW_PREDICATE_NORMAL
);
2449 /* If vertex_count is 0, then no control data bits have been
2450 * accumulated yet, so we can skip emitting them.
2452 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2453 BRW_CONDITIONAL_NEQ
);
2454 abld
.IF(BRW_PREDICATE_NORMAL
);
2455 emit_gs_control_data_bits(vertex_count
);
2456 abld
.emit(BRW_OPCODE_ENDIF
);
2458 /* Reset control_data_bits to 0 so we can start accumulating a new
2461 * Note: in the case where vertex_count == 0, this neutralizes the
2462 * effect of any call to EndPrimitive() that the shader may have
2463 * made before outputting its first vertex.
2465 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2466 inst
->force_writemask_all
= true;
2467 abld
.emit(BRW_OPCODE_ENDIF
);
2470 emit_urb_writes(vertex_count
);
2472 /* In stream mode we have to set control data bits for all vertices
2473 * unless we have disabled control data bits completely (which we do
2474 * do for GL_POINTS outputs that don't use streams).
2476 if (gs_compile
->control_data_header_size_bits
> 0 &&
2477 gs_prog_data
->control_data_format
==
2478 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2479 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2484 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2485 const nir_src
&vertex_src
,
2486 unsigned base_offset
,
2487 const nir_src
&offset_src
,
2488 unsigned num_components
,
2489 unsigned first_component
)
2491 assert(type_sz(dst
.type
) == 4);
2492 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2493 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2495 /* TODO: figure out push input layout for invocations == 1 */
2496 if (gs_prog_data
->invocations
== 1 &&
2497 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2498 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2499 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2500 nir_src_as_uint(vertex_src
) * push_reg_count
;
2501 for (unsigned i
= 0; i
< num_components
; i
++) {
2502 bld
.MOV(offset(dst
, bld
, i
),
2503 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2508 /* Resort to the pull model. Ensure the VUE handles are provided. */
2509 assert(gs_prog_data
->base
.include_vue_handles
);
2511 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2512 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2514 if (gs_prog_data
->invocations
== 1) {
2515 if (nir_src_is_const(vertex_src
)) {
2516 /* The vertex index is constant; just select the proper URB handle. */
2518 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2519 BRW_REGISTER_TYPE_UD
);
2521 /* The vertex index is non-constant. We need to use indirect
2522 * addressing to fetch the proper URB handle.
2524 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2525 * indicating that channel <n> should read the handle from
2526 * DWord <n>. We convert that to bytes by multiplying by 4.
2528 * Next, we convert the vertex index to bytes by multiplying
2529 * by 32 (shifting by 5), and add the two together. This is
2530 * the final indirect byte offset.
2532 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2533 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2534 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2535 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2537 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2538 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2539 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2540 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2541 /* Convert vertex_index to bytes (multiply by 32) */
2542 bld
.SHL(vertex_offset_bytes
,
2543 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2545 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2547 /* Use first_icp_handle as the base offset. There is one register
2548 * of URB handles per vertex, so inform the register allocator that
2549 * we might read up to nir->info.gs.vertices_in registers.
2551 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2552 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2553 fs_reg(icp_offset_bytes
),
2554 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2557 assert(gs_prog_data
->invocations
> 1);
2559 if (nir_src_is_const(vertex_src
)) {
2560 unsigned vertex
= nir_src_as_uint(vertex_src
);
2561 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2563 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2564 BRW_REGISTER_TYPE_UD
));
2566 /* The vertex index is non-constant. We need to use indirect
2567 * addressing to fetch the proper URB handle.
2570 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2572 /* Convert vertex_index to bytes (multiply by 4) */
2573 bld
.SHL(icp_offset_bytes
,
2574 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2577 /* Use first_icp_handle as the base offset. There is one DWord
2578 * of URB handles per vertex, so inform the register allocator that
2579 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2581 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2582 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2583 fs_reg(icp_offset_bytes
),
2584 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2590 fs_reg indirect_offset
= get_nir_src(offset_src
);
2592 if (nir_src_is_const(offset_src
)) {
2593 /* Constant indexing - use global offset. */
2594 if (first_component
!= 0) {
2595 unsigned read_components
= num_components
+ first_component
;
2596 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2597 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2598 inst
->size_written
= read_components
*
2599 tmp
.component_size(inst
->exec_size
);
2600 for (unsigned i
= 0; i
< num_components
; i
++) {
2601 bld
.MOV(offset(dst
, bld
, i
),
2602 offset(tmp
, bld
, i
+ first_component
));
2605 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2606 inst
->size_written
= num_components
*
2607 dst
.component_size(inst
->exec_size
);
2609 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2612 /* Indirect indexing - use per-slot offsets as well. */
2613 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2614 unsigned read_components
= num_components
+ first_component
;
2615 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2616 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2617 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2618 if (first_component
!= 0) {
2619 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2621 inst
->size_written
= read_components
*
2622 tmp
.component_size(inst
->exec_size
);
2623 for (unsigned i
= 0; i
< num_components
; i
++) {
2624 bld
.MOV(offset(dst
, bld
, i
),
2625 offset(tmp
, bld
, i
+ first_component
));
2628 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2629 inst
->size_written
= num_components
*
2630 dst
.component_size(inst
->exec_size
);
2632 inst
->offset
= base_offset
;
2638 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2640 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2642 if (nir_src_is_const(*offset_src
)) {
2643 /* The only constant offset we should find is 0. brw_nir.c's
2644 * add_const_offset_to_base() will fold other constant offsets
2645 * into instr->const_index[0].
2647 assert(nir_src_as_uint(*offset_src
) == 0);
2651 return get_nir_src(*offset_src
);
2655 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2656 nir_intrinsic_instr
*instr
)
2658 assert(stage
== MESA_SHADER_VERTEX
);
2661 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2662 dest
= get_nir_dest(instr
->dest
);
2664 switch (instr
->intrinsic
) {
2665 case nir_intrinsic_load_vertex_id
:
2666 case nir_intrinsic_load_base_vertex
:
2667 unreachable("should be lowered by nir_lower_system_values()");
2669 case nir_intrinsic_load_input
: {
2670 assert(nir_dest_bit_size(instr
->dest
) == 32);
2671 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2672 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2673 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2675 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2676 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2680 case nir_intrinsic_load_vertex_id_zero_base
:
2681 case nir_intrinsic_load_instance_id
:
2682 case nir_intrinsic_load_base_instance
:
2683 case nir_intrinsic_load_draw_id
:
2684 case nir_intrinsic_load_first_vertex
:
2685 case nir_intrinsic_load_is_indexed_draw
:
2686 unreachable("lowered by brw_nir_lower_vs_inputs");
2689 nir_emit_intrinsic(bld
, instr
);
2695 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2696 nir_intrinsic_instr
*instr
)
2698 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2699 const nir_src
&vertex_src
= instr
->src
[0];
2700 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2703 if (nir_src_is_const(vertex_src
)) {
2704 /* Emit a MOV to resolve <0,1,0> regioning. */
2705 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2706 unsigned vertex
= nir_src_as_uint(vertex_src
);
2708 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2709 BRW_REGISTER_TYPE_UD
));
2710 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2711 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2712 /* For the common case of only 1 instance, an array index of
2713 * gl_InvocationID means reading g1. Skip all the indirect work.
2715 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2717 /* The vertex index is non-constant. We need to use indirect
2718 * addressing to fetch the proper URB handle.
2720 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2722 /* Each ICP handle is a single DWord (4 bytes) */
2723 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2724 bld
.SHL(vertex_offset_bytes
,
2725 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2728 /* Start at g1. We might read up to 4 registers. */
2729 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2730 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2731 brw_imm_ud(4 * REG_SIZE
));
2738 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2739 nir_intrinsic_instr
*instr
)
2741 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2742 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2743 const nir_src
&vertex_src
= instr
->src
[0];
2745 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2747 if (nir_src_is_const(vertex_src
)) {
2748 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2749 nir_src_as_uint(vertex_src
), 0),
2750 BRW_REGISTER_TYPE_UD
));
2753 /* The vertex index is non-constant. We need to use indirect
2754 * addressing to fetch the proper URB handle.
2756 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2757 * indicating that channel <n> should read the handle from
2758 * DWord <n>. We convert that to bytes by multiplying by 4.
2760 * Next, we convert the vertex index to bytes by multiplying
2761 * by 32 (shifting by 5), and add the two together. This is
2762 * the final indirect byte offset.
2764 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2765 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2766 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2767 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2768 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2770 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2771 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2772 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2773 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2774 /* Convert vertex_index to bytes (multiply by 32) */
2775 bld
.SHL(vertex_offset_bytes
,
2776 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2778 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2780 /* Use first_icp_handle as the base offset. There is one register
2781 * of URB handles per vertex, so inform the register allocator that
2782 * we might read up to nir->info.gs.vertices_in registers.
2784 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2785 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2786 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2792 fs_visitor::get_tcs_output_urb_handle()
2794 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2796 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2797 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2799 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2800 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2805 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2806 nir_intrinsic_instr
*instr
)
2808 assert(stage
== MESA_SHADER_TESS_CTRL
);
2809 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2810 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2811 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2814 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2817 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2818 dst
= get_nir_dest(instr
->dest
);
2820 switch (instr
->intrinsic
) {
2821 case nir_intrinsic_load_primitive_id
:
2822 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2823 : brw_vec1_grf(0, 1)));
2825 case nir_intrinsic_load_invocation_id
:
2826 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2828 case nir_intrinsic_load_patch_vertices_in
:
2829 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2830 brw_imm_d(tcs_key
->input_vertices
));
2833 case nir_intrinsic_control_barrier
: {
2834 if (tcs_prog_data
->instances
== 1)
2837 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2838 fs_reg m0_2
= component(m0
, 2);
2840 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2842 /* Zero the message header */
2843 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2845 if (devinfo
->gen
< 11) {
2846 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2847 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2848 brw_imm_ud(INTEL_MASK(16, 13)));
2850 /* Shift it up to bits 27:24. */
2851 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2853 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2854 brw_imm_ud(INTEL_MASK(30, 24)));
2857 /* Set the Barrier Count and the enable bit */
2858 if (devinfo
->gen
< 11) {
2859 chanbld
.OR(m0_2
, m0_2
,
2860 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2862 chanbld
.OR(m0_2
, m0_2
,
2863 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2866 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2870 case nir_intrinsic_load_input
:
2871 unreachable("nir_lower_io should never give us these.");
2874 case nir_intrinsic_load_per_vertex_input
: {
2875 assert(nir_dest_bit_size(instr
->dest
) == 32);
2876 fs_reg indirect_offset
= get_indirect_offset(instr
);
2877 unsigned imm_offset
= instr
->const_index
[0];
2881 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2882 : get_tcs_single_patch_icp_handle(bld
, instr
);
2884 /* We can only read two double components with each URB read, so
2885 * we send two read messages in that case, each one loading up to
2886 * two double components.
2888 unsigned num_components
= instr
->num_components
;
2889 unsigned first_component
= nir_intrinsic_component(instr
);
2891 if (indirect_offset
.file
== BAD_FILE
) {
2892 /* Constant indexing - use global offset. */
2893 if (first_component
!= 0) {
2894 unsigned read_components
= num_components
+ first_component
;
2895 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2896 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2897 for (unsigned i
= 0; i
< num_components
; i
++) {
2898 bld
.MOV(offset(dst
, bld
, i
),
2899 offset(tmp
, bld
, i
+ first_component
));
2902 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2904 inst
->offset
= imm_offset
;
2907 /* Indirect indexing - use per-slot offsets as well. */
2908 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2909 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2910 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2911 if (first_component
!= 0) {
2912 unsigned read_components
= num_components
+ first_component
;
2913 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2914 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2916 for (unsigned i
= 0; i
< num_components
; i
++) {
2917 bld
.MOV(offset(dst
, bld
, i
),
2918 offset(tmp
, bld
, i
+ first_component
));
2921 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2924 inst
->offset
= imm_offset
;
2927 inst
->size_written
= (num_components
+ first_component
) *
2928 inst
->dst
.component_size(inst
->exec_size
);
2930 /* Copy the temporary to the destination to deal with writemasking.
2932 * Also attempt to deal with gl_PointSize being in the .w component.
2934 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2935 assert(type_sz(dst
.type
) == 4);
2936 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2937 inst
->size_written
= 4 * REG_SIZE
;
2938 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2943 case nir_intrinsic_load_output
:
2944 case nir_intrinsic_load_per_vertex_output
: {
2945 assert(nir_dest_bit_size(instr
->dest
) == 32);
2946 fs_reg indirect_offset
= get_indirect_offset(instr
);
2947 unsigned imm_offset
= instr
->const_index
[0];
2948 unsigned first_component
= nir_intrinsic_component(instr
);
2950 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2953 if (indirect_offset
.file
== BAD_FILE
) {
2954 /* This MOV replicates the output handle to all enabled channels
2955 * is SINGLE_PATCH mode.
2957 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2958 bld
.MOV(patch_handle
, output_handles
);
2961 if (first_component
!= 0) {
2962 unsigned read_components
=
2963 instr
->num_components
+ first_component
;
2964 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2965 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2967 inst
->size_written
= read_components
* REG_SIZE
;
2968 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2969 bld
.MOV(offset(dst
, bld
, i
),
2970 offset(tmp
, bld
, i
+ first_component
));
2973 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2975 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2977 inst
->offset
= imm_offset
;
2981 /* Indirect indexing - use per-slot offsets as well. */
2982 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2983 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2984 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2985 if (first_component
!= 0) {
2986 unsigned read_components
=
2987 instr
->num_components
+ first_component
;
2988 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2989 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2991 inst
->size_written
= read_components
* REG_SIZE
;
2992 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2993 bld
.MOV(offset(dst
, bld
, i
),
2994 offset(tmp
, bld
, i
+ first_component
));
2997 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2999 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3001 inst
->offset
= imm_offset
;
3007 case nir_intrinsic_store_output
:
3008 case nir_intrinsic_store_per_vertex_output
: {
3009 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3010 fs_reg value
= get_nir_src(instr
->src
[0]);
3011 fs_reg indirect_offset
= get_indirect_offset(instr
);
3012 unsigned imm_offset
= instr
->const_index
[0];
3013 unsigned mask
= instr
->const_index
[1];
3014 unsigned header_regs
= 0;
3015 struct brw_reg output_handles
= get_tcs_output_urb_handle();
3018 srcs
[header_regs
++] = output_handles
;
3020 if (indirect_offset
.file
!= BAD_FILE
) {
3021 srcs
[header_regs
++] = indirect_offset
;
3027 unsigned num_components
= util_last_bit(mask
);
3030 /* We can only pack two 64-bit components in a single message, so send
3031 * 2 messages if we have more components
3033 unsigned first_component
= nir_intrinsic_component(instr
);
3034 mask
= mask
<< first_component
;
3036 if (mask
!= WRITEMASK_XYZW
) {
3037 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
3038 opcode
= indirect_offset
.file
!= BAD_FILE
?
3039 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
3040 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
3042 opcode
= indirect_offset
.file
!= BAD_FILE
?
3043 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
3044 SHADER_OPCODE_URB_WRITE_SIMD8
;
3047 for (unsigned i
= 0; i
< num_components
; i
++) {
3048 if (!(mask
& (1 << (i
+ first_component
))))
3051 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
3054 unsigned mlen
= header_regs
+ num_components
+ first_component
;
3056 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
3057 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
3059 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
3060 inst
->offset
= imm_offset
;
3066 nir_emit_intrinsic(bld
, instr
);
3072 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
3073 nir_intrinsic_instr
*instr
)
3075 assert(stage
== MESA_SHADER_TESS_EVAL
);
3076 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3079 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3080 dest
= get_nir_dest(instr
->dest
);
3082 switch (instr
->intrinsic
) {
3083 case nir_intrinsic_load_primitive_id
:
3084 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3086 case nir_intrinsic_load_tess_coord
:
3087 /* gl_TessCoord is part of the payload in g1-3 */
3088 for (unsigned i
= 0; i
< 3; i
++) {
3089 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3093 case nir_intrinsic_load_input
:
3094 case nir_intrinsic_load_per_vertex_input
: {
3095 assert(nir_dest_bit_size(instr
->dest
) == 32);
3096 fs_reg indirect_offset
= get_indirect_offset(instr
);
3097 unsigned imm_offset
= instr
->const_index
[0];
3098 unsigned first_component
= nir_intrinsic_component(instr
);
3101 if (indirect_offset
.file
== BAD_FILE
) {
3102 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3103 * which is 16 registers (since each holds 2 vec4 slots).
3105 const unsigned max_push_slots
= 32;
3106 if (imm_offset
< max_push_slots
) {
3107 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3108 for (int i
= 0; i
< instr
->num_components
; i
++) {
3109 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3110 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3113 tes_prog_data
->base
.urb_read_length
=
3114 MAX2(tes_prog_data
->base
.urb_read_length
,
3115 (imm_offset
/ 2) + 1);
3117 /* Replicate the patch handle to all enabled channels */
3118 const fs_reg srcs
[] = {
3119 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3121 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3122 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3124 if (first_component
!= 0) {
3125 unsigned read_components
=
3126 instr
->num_components
+ first_component
;
3127 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3128 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3130 inst
->size_written
= read_components
* REG_SIZE
;
3131 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3132 bld
.MOV(offset(dest
, bld
, i
),
3133 offset(tmp
, bld
, i
+ first_component
));
3136 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3138 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3141 inst
->offset
= imm_offset
;
3144 /* Indirect indexing - use per-slot offsets as well. */
3146 /* We can only read two double components with each URB read, so
3147 * we send two read messages in that case, each one loading up to
3148 * two double components.
3150 unsigned num_components
= instr
->num_components
;
3151 const fs_reg srcs
[] = {
3152 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3155 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3156 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3158 if (first_component
!= 0) {
3159 unsigned read_components
=
3160 num_components
+ first_component
;
3161 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3162 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3164 for (unsigned i
= 0; i
< num_components
; i
++) {
3165 bld
.MOV(offset(dest
, bld
, i
),
3166 offset(tmp
, bld
, i
+ first_component
));
3169 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3173 inst
->offset
= imm_offset
;
3174 inst
->size_written
= (num_components
+ first_component
) *
3175 inst
->dst
.component_size(inst
->exec_size
);
3180 nir_emit_intrinsic(bld
, instr
);
3186 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3187 nir_intrinsic_instr
*instr
)
3189 assert(stage
== MESA_SHADER_GEOMETRY
);
3190 fs_reg indirect_offset
;
3193 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3194 dest
= get_nir_dest(instr
->dest
);
3196 switch (instr
->intrinsic
) {
3197 case nir_intrinsic_load_primitive_id
:
3198 assert(stage
== MESA_SHADER_GEOMETRY
);
3199 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3200 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3201 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3204 case nir_intrinsic_load_input
:
3205 unreachable("load_input intrinsics are invalid for the GS stage");
3207 case nir_intrinsic_load_per_vertex_input
:
3208 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3209 instr
->src
[1], instr
->num_components
,
3210 nir_intrinsic_component(instr
));
3213 case nir_intrinsic_emit_vertex_with_counter
:
3214 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3217 case nir_intrinsic_end_primitive_with_counter
:
3218 emit_gs_end_primitive(instr
->src
[0]);
3221 case nir_intrinsic_set_vertex_count
:
3222 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3225 case nir_intrinsic_load_invocation_id
: {
3226 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3227 assert(val
.file
!= BAD_FILE
);
3228 dest
.type
= val
.type
;
3234 nir_emit_intrinsic(bld
, instr
);
3240 * Fetch the current render target layer index.
3243 fetch_render_target_array_index(const fs_builder
&bld
)
3245 if (bld
.shader
->devinfo
->gen
>= 6) {
3246 /* The render target array index is provided in the thread payload as
3247 * bits 26:16 of r0.0.
3249 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3250 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3254 /* Pre-SNB we only ever render into the first layer of the framebuffer
3255 * since layered rendering is not implemented.
3257 return brw_imm_ud(0);
3262 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3263 * framebuffer at the current fragment coordinates and sample index.
3266 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3269 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3271 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3272 const brw_wm_prog_key
*wm_key
=
3273 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3274 assert(!wm_key
->coherent_fb_fetch
);
3275 const struct brw_wm_prog_data
*wm_prog_data
=
3276 brw_wm_prog_data(stage_prog_data
);
3278 /* Calculate the surface index relative to the start of the texture binding
3279 * table block, since that's what the texturing messages expect.
3281 const unsigned surface
= target
+
3282 wm_prog_data
->binding_table
.render_target_read_start
-
3283 wm_prog_data
->base
.binding_table
.texture_start
;
3285 /* Calculate the fragment coordinates. */
3286 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3287 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3288 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3289 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3291 /* Calculate the sample index and MCS payload when multisampling. Luckily
3292 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3293 * shouldn't be necessary to recompile based on whether the framebuffer is
3296 if (wm_key
->multisample_fbo
&&
3297 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3298 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3300 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3301 const fs_reg mcs
= wm_key
->multisample_fbo
?
3302 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3304 /* Use either a normal or a CMS texel fetch message depending on whether
3305 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3306 * message just in case the framebuffer uses 16x multisampling, it should
3307 * be equivalent to the normal CMS fetch for lower multisampling modes.
3309 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3310 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3311 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3313 /* Emit the instruction. */
3314 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3315 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3316 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3317 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3318 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3319 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3320 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3321 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3322 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3324 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3325 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3331 * Actual coherent framebuffer read implemented using the native render target
3332 * read message. Requires SKL+.
3335 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3337 assert(bld
.shader
->devinfo
->gen
>= 9);
3338 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3339 inst
->target
= target
;
3340 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3346 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3348 if (n
&& regs
[0].file
!= BAD_FILE
) {
3352 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3354 for (unsigned i
= 0; i
< n
; i
++)
3362 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3364 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3365 const brw_wm_prog_key
*const key
=
3366 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3367 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3368 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3370 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3371 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3373 else if (l
== FRAG_RESULT_COLOR
)
3374 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3375 MAX2(key
->nr_color_regions
, 1));
3377 else if (l
== FRAG_RESULT_DEPTH
)
3378 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3380 else if (l
== FRAG_RESULT_STENCIL
)
3381 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3383 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3384 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3386 else if (l
>= FRAG_RESULT_DATA0
&&
3387 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3388 return alloc_temporary(v
->bld
, 4,
3389 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3392 unreachable("Invalid location");
3396 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3397 nir_intrinsic_instr
*instr
)
3399 assert(stage
== MESA_SHADER_FRAGMENT
);
3402 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3403 dest
= get_nir_dest(instr
->dest
);
3405 switch (instr
->intrinsic
) {
3406 case nir_intrinsic_load_front_face
:
3407 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3408 *emit_frontfacing_interpolation());
3411 case nir_intrinsic_load_sample_pos
: {
3412 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3413 assert(sample_pos
.file
!= BAD_FILE
);
3414 dest
.type
= sample_pos
.type
;
3415 bld
.MOV(dest
, sample_pos
);
3416 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3420 case nir_intrinsic_load_layer_id
:
3421 dest
.type
= BRW_REGISTER_TYPE_UD
;
3422 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3425 case nir_intrinsic_is_helper_invocation
: {
3426 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3427 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3428 * consideration demoted invocations. That information is stored in
3431 dest
.type
= BRW_REGISTER_TYPE_UD
;
3433 bld
.MOV(dest
, brw_imm_ud(0));
3435 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3436 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3437 mov
->predicate_inverse
= true;
3438 mov
->flag_subreg
= sample_mask_flag_subreg(this);
3442 case nir_intrinsic_load_helper_invocation
:
3443 case nir_intrinsic_load_sample_mask_in
:
3444 case nir_intrinsic_load_sample_id
: {
3445 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3446 fs_reg val
= nir_system_values
[sv
];
3447 assert(val
.file
!= BAD_FILE
);
3448 dest
.type
= val
.type
;
3453 case nir_intrinsic_store_output
: {
3454 const fs_reg src
= get_nir_src(instr
->src
[0]);
3455 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3456 const unsigned location
= nir_intrinsic_base(instr
) +
3457 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3458 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3461 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3462 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3463 offset(src
, bld
, j
));
3468 case nir_intrinsic_load_output
: {
3469 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3470 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3471 assert(l
>= FRAG_RESULT_DATA0
);
3472 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3473 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3474 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3476 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3477 emit_coherent_fb_read(bld
, tmp
, target
);
3479 emit_non_coherent_fb_read(bld
, tmp
, target
);
3481 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3482 bld
.MOV(offset(dest
, bld
, j
),
3483 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3489 case nir_intrinsic_demote
:
3490 case nir_intrinsic_discard
:
3491 case nir_intrinsic_demote_if
:
3492 case nir_intrinsic_discard_if
: {
3493 /* We track our discarded pixels in f0.1. By predicating on it, we can
3494 * update just the flag bits that aren't yet discarded. If there's no
3495 * condition, we emit a CMP of g0 != g0, so all currently executing
3496 * channels will get turned off.
3498 fs_inst
*cmp
= NULL
;
3499 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3500 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3501 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3504 alu
->op
!= nir_op_bcsel
&&
3505 alu
->op
!= nir_op_inot
&&
3506 (devinfo
->gen
> 5 ||
3507 (alu
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE
||
3508 alu
->op
== nir_op_fne32
|| alu
->op
== nir_op_feq32
||
3509 alu
->op
== nir_op_flt32
|| alu
->op
== nir_op_fge32
||
3510 alu
->op
== nir_op_ine32
|| alu
->op
== nir_op_ieq32
||
3511 alu
->op
== nir_op_ilt32
|| alu
->op
== nir_op_ige32
||
3512 alu
->op
== nir_op_ult32
|| alu
->op
== nir_op_uge32
)) {
3513 /* Re-emit the instruction that generated the Boolean value, but
3514 * do not store it. Since this instruction will be conditional,
3515 * other instructions that want to use the real Boolean value may
3516 * get garbage. This was a problem for piglit's fs-discard-exit-2
3519 * Ideally we'd detect that the instruction cannot have a
3520 * conditional modifier before emitting the instructions. Alas,
3521 * that is nigh impossible. Instead, we're going to assume the
3522 * instruction (or last instruction) generated can have a
3523 * conditional modifier. If it cannot, fallback to the old-style
3524 * compare, and hope dead code elimination will clean up the
3525 * extra instructions generated.
3527 nir_emit_alu(bld
, alu
, false);
3529 cmp
= (fs_inst
*) instructions
.get_tail();
3530 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3531 if (cmp
->can_do_cmod())
3532 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3536 /* The old sequence that would have been generated is,
3537 * basically, bool_result == false. This is equivalent to
3538 * !bool_result, so negate the old modifier.
3540 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3545 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3546 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3549 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3550 BRW_REGISTER_TYPE_UW
));
3551 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3554 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3555 cmp
->flag_subreg
= sample_mask_flag_subreg(this);
3557 if (devinfo
->gen
>= 6) {
3558 /* Due to the way we implement discard, the jump will only happen
3559 * when the whole quad is discarded. So we can do this even for
3560 * demote as it won't break its uniformity promises.
3562 emit_discard_jump();
3565 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
3569 case nir_intrinsic_load_input
: {
3570 /* load_input is only used for flat inputs */
3571 assert(nir_dest_bit_size(instr
->dest
) == 32);
3572 unsigned base
= nir_intrinsic_base(instr
);
3573 unsigned comp
= nir_intrinsic_component(instr
);
3574 unsigned num_components
= instr
->num_components
;
3576 /* Special case fields in the VUE header */
3577 if (base
== VARYING_SLOT_LAYER
)
3579 else if (base
== VARYING_SLOT_VIEWPORT
)
3582 for (unsigned int i
= 0; i
< num_components
; i
++) {
3583 bld
.MOV(offset(dest
, bld
, i
),
3584 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3589 case nir_intrinsic_load_fs_input_interp_deltas
: {
3590 assert(stage
== MESA_SHADER_FRAGMENT
);
3591 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3592 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3593 nir_intrinsic_component(instr
));
3594 dest
.type
= BRW_REGISTER_TYPE_F
;
3595 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3596 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3597 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3601 case nir_intrinsic_load_barycentric_pixel
:
3602 case nir_intrinsic_load_barycentric_centroid
:
3603 case nir_intrinsic_load_barycentric_sample
: {
3604 /* Use the delta_xy values computed from the payload */
3605 const glsl_interp_mode interp_mode
=
3606 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3607 enum brw_barycentric_mode bary
=
3608 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3609 const fs_reg srcs
[] = { offset(this->delta_xy
[bary
], bld
, 0),
3610 offset(this->delta_xy
[bary
], bld
, 1) };
3611 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3615 case nir_intrinsic_load_barycentric_at_sample
: {
3616 const glsl_interp_mode interpolation
=
3617 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3619 if (nir_src_is_const(instr
->src
[0])) {
3620 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3622 emit_pixel_interpolater_send(bld
,
3623 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3626 brw_imm_ud(msg_data
),
3629 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3630 BRW_REGISTER_TYPE_UD
);
3632 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3633 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3634 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3635 bld
.exec_all().group(1, 0)
3636 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3637 emit_pixel_interpolater_send(bld
,
3638 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3641 component(msg_data
, 0),
3644 /* Make a loop that sends a message to the pixel interpolater
3645 * for the sample number in each live channel. If there are
3646 * multiple channels with the same sample number then these
3647 * will be handled simultaneously with a single interation of
3650 bld
.emit(BRW_OPCODE_DO
);
3652 /* Get the next live sample number into sample_id_reg */
3653 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3655 /* Set the flag register so that we can perform the send
3656 * message on all channels that have the same sample number
3658 bld
.CMP(bld
.null_reg_ud(),
3659 sample_src
, sample_id
,
3660 BRW_CONDITIONAL_EQ
);
3661 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3662 bld
.exec_all().group(1, 0)
3663 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3665 emit_pixel_interpolater_send(bld
,
3666 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3669 component(msg_data
, 0),
3671 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3673 /* Continue the loop if there are any live channels left */
3674 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3676 bld
.emit(BRW_OPCODE_WHILE
));
3682 case nir_intrinsic_load_barycentric_at_offset
: {
3683 const glsl_interp_mode interpolation
=
3684 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3686 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3689 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3690 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3691 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3693 emit_pixel_interpolater_send(bld
,
3694 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3697 brw_imm_ud(off_x
| (off_y
<< 4)),
3700 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3701 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3702 BRW_REGISTER_TYPE_F
);
3703 for (int i
= 0; i
< 2; i
++) {
3704 fs_reg temp
= vgrf(glsl_type::float_type
);
3705 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3706 fs_reg itemp
= vgrf(glsl_type::int_type
);
3708 bld
.MOV(itemp
, temp
);
3710 /* Clamp the upper end of the range to +7/16.
3711 * ARB_gpu_shader5 requires that we support a maximum offset
3712 * of +0.5, which isn't representable in a S0.4 value -- if
3713 * we didn't clamp it, we'd end up with -8/16, which is the
3714 * opposite of what the shader author wanted.
3716 * This is legal due to ARB_gpu_shader5's quantization
3719 * "Not all values of <offset> may be supported; x and y
3720 * offsets may be rounded to fixed-point values with the
3721 * number of fraction bits given by the
3722 * implementation-dependent constant
3723 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3725 set_condmod(BRW_CONDITIONAL_L
,
3726 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3729 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3730 emit_pixel_interpolater_send(bld
,
3740 case nir_intrinsic_load_frag_coord
:
3741 emit_fragcoord_interpolation(dest
);
3744 case nir_intrinsic_load_interpolated_input
: {
3745 assert(instr
->src
[0].ssa
&&
3746 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3747 nir_intrinsic_instr
*bary_intrinsic
=
3748 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3749 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3750 enum glsl_interp_mode interp_mode
=
3751 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3754 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3755 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3756 /* Use the result of the PI message. */
3757 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3759 /* Use the delta_xy values computed from the payload */
3760 enum brw_barycentric_mode bary
=
3761 brw_barycentric_mode(interp_mode
, bary_intrin
);
3762 dst_xy
= this->delta_xy
[bary
];
3765 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3767 component(interp_reg(nir_intrinsic_base(instr
),
3768 nir_intrinsic_component(instr
) + i
), 0);
3769 interp
.type
= BRW_REGISTER_TYPE_F
;
3770 dest
.type
= BRW_REGISTER_TYPE_F
;
3772 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3773 fs_reg tmp
= vgrf(glsl_type::float_type
);
3774 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3775 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3777 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3784 nir_emit_intrinsic(bld
, instr
);
3790 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3791 nir_intrinsic_instr
*instr
)
3793 assert(stage
== MESA_SHADER_COMPUTE
);
3794 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3797 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3798 dest
= get_nir_dest(instr
->dest
);
3800 switch (instr
->intrinsic
) {
3801 case nir_intrinsic_control_barrier
:
3802 /* The whole workgroup fits in a single HW thread, so all the
3803 * invocations are already executed lock-step. Instead of an actual
3804 * barrier just emit a scheduling fence, that will generate no code.
3806 if (workgroup_size() <= dispatch_width
) {
3807 bld
.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE
);
3812 cs_prog_data
->uses_barrier
= true;
3815 case nir_intrinsic_load_subgroup_id
:
3816 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3819 case nir_intrinsic_load_local_invocation_id
:
3820 case nir_intrinsic_load_work_group_id
: {
3821 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3822 fs_reg val
= nir_system_values
[sv
];
3823 assert(val
.file
!= BAD_FILE
);
3824 dest
.type
= val
.type
;
3825 for (unsigned i
= 0; i
< 3; i
++)
3826 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3830 case nir_intrinsic_load_num_work_groups
: {
3831 const unsigned surface
=
3832 cs_prog_data
->binding_table
.work_groups_start
;
3834 cs_prog_data
->uses_num_work_groups
= true;
3836 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3837 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3838 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3839 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3841 /* Read the 3 GLuint components of gl_NumWorkGroups */
3842 for (unsigned i
= 0; i
< 3; i
++) {
3843 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3844 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3845 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3850 case nir_intrinsic_shared_atomic_add
:
3851 case nir_intrinsic_shared_atomic_imin
:
3852 case nir_intrinsic_shared_atomic_umin
:
3853 case nir_intrinsic_shared_atomic_imax
:
3854 case nir_intrinsic_shared_atomic_umax
:
3855 case nir_intrinsic_shared_atomic_and
:
3856 case nir_intrinsic_shared_atomic_or
:
3857 case nir_intrinsic_shared_atomic_xor
:
3858 case nir_intrinsic_shared_atomic_exchange
:
3859 case nir_intrinsic_shared_atomic_comp_swap
:
3860 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3862 case nir_intrinsic_shared_atomic_fmin
:
3863 case nir_intrinsic_shared_atomic_fmax
:
3864 case nir_intrinsic_shared_atomic_fcomp_swap
:
3865 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3868 case nir_intrinsic_load_shared
: {
3869 assert(devinfo
->gen
>= 7);
3870 assert(stage
== MESA_SHADER_COMPUTE
);
3872 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3873 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3874 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3875 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3876 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3878 /* Make dest unsigned because that's what the temporary will be */
3879 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3881 /* Read the vector */
3882 if (nir_intrinsic_align(instr
) >= 4) {
3883 assert(nir_dest_bit_size(instr
->dest
) == 32);
3884 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3886 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3887 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3888 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3890 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3891 assert(nir_dest_num_components(instr
->dest
) == 1);
3892 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3894 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3895 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3896 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3897 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3902 case nir_intrinsic_store_shared
: {
3903 assert(devinfo
->gen
>= 7);
3904 assert(stage
== MESA_SHADER_COMPUTE
);
3906 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3907 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3908 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3909 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3910 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3912 fs_reg data
= get_nir_src(instr
->src
[0]);
3913 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3915 assert(nir_intrinsic_write_mask(instr
) ==
3916 (1u << instr
->num_components
) - 1);
3917 if (nir_intrinsic_align(instr
) >= 4) {
3918 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3919 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3920 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3921 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3922 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3923 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3925 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3926 assert(nir_src_num_components(instr
->src
[0]) == 1);
3927 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3929 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3930 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3932 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3933 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3939 nir_emit_intrinsic(bld
, instr
);
3945 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3946 nir_op op
, brw_reg_type type
)
3948 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3949 switch (type_sz(type
)) {
3951 if (type
== BRW_REGISTER_TYPE_UB
) {
3952 return brw_imm_uw(value
.u8
);
3954 assert(type
== BRW_REGISTER_TYPE_B
);
3955 return brw_imm_w(value
.i8
);
3958 return retype(brw_imm_uw(value
.u16
), type
);
3960 return retype(brw_imm_ud(value
.u32
), type
);
3962 if (type
== BRW_REGISTER_TYPE_DF
)
3963 return setup_imm_df(bld
, value
.f64
);
3965 return retype(brw_imm_u64(value
.u64
), type
);
3967 unreachable("Invalid type size");
3972 brw_op_for_nir_reduction_op(nir_op op
)
3975 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3976 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3977 case nir_op_imul
: return BRW_OPCODE_MUL
;
3978 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3979 case nir_op_imin
: return BRW_OPCODE_SEL
;
3980 case nir_op_umin
: return BRW_OPCODE_SEL
;
3981 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3982 case nir_op_imax
: return BRW_OPCODE_SEL
;
3983 case nir_op_umax
: return BRW_OPCODE_SEL
;
3984 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3985 case nir_op_iand
: return BRW_OPCODE_AND
;
3986 case nir_op_ior
: return BRW_OPCODE_OR
;
3987 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3989 unreachable("Invalid reduction operation");
3993 static brw_conditional_mod
3994 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3997 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3998 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3999 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
4000 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
4001 case nir_op_imin
: return BRW_CONDITIONAL_L
;
4002 case nir_op_umin
: return BRW_CONDITIONAL_L
;
4003 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
4004 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
4005 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
4006 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
4007 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
4008 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
4009 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
4011 unreachable("Invalid reduction operation");
4016 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
4017 nir_intrinsic_instr
*instr
)
4019 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
4020 fs_reg surf_index
= image
;
4022 if (stage_prog_data
->binding_table
.image_start
> 0) {
4023 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
4025 brw_imm_ud(image
.d
+ stage_prog_data
->binding_table
.image_start
);
4027 surf_index
= vgrf(glsl_type::uint_type
);
4028 bld
.ADD(surf_index
, image
,
4029 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
4033 return bld
.emit_uniformize(surf_index
);
4037 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
4038 nir_intrinsic_instr
*instr
)
4040 /* SSBO stores are weird in that their index is in src[1] */
4041 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
4044 if (nir_src_is_const(instr
->src
[src
])) {
4045 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4046 nir_src_as_uint(instr
->src
[src
]);
4047 surf_index
= brw_imm_ud(index
);
4049 surf_index
= vgrf(glsl_type::uint_type
);
4050 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
4051 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4054 return bld
.emit_uniformize(surf_index
);
4058 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
4060 switch (nir_intrinsic_image_dim(instr
)) {
4061 case GLSL_SAMPLER_DIM_1D
:
4062 return 1 + nir_intrinsic_image_array(instr
);
4063 case GLSL_SAMPLER_DIM_2D
:
4064 case GLSL_SAMPLER_DIM_RECT
:
4065 return 2 + nir_intrinsic_image_array(instr
);
4066 case GLSL_SAMPLER_DIM_3D
:
4067 case GLSL_SAMPLER_DIM_CUBE
:
4069 case GLSL_SAMPLER_DIM_BUF
:
4071 case GLSL_SAMPLER_DIM_MS
:
4072 return 2 + nir_intrinsic_image_array(instr
);
4074 unreachable("Invalid image dimension");
4079 * The offsets we get from NIR act as if each SIMD channel has it's own blob
4080 * of contiguous space. However, if we actually place each SIMD channel in
4081 * it's own space, we end up with terrible cache performance because each SIMD
4082 * channel accesses a different cache line even when they're all accessing the
4083 * same byte offset. To deal with this problem, we swizzle the address using
4084 * a simple algorithm which ensures that any time a SIMD message reads or
4085 * writes the same address, it's all in the same cache line. We have to keep
4086 * the bottom two bits fixed so that we can read/write up to a dword at a time
4087 * and the individual element is contiguous. We do this by splitting the
4088 * address as follows:
4091 * +-------------------------------+------------+----------+
4092 * | Hi address bits | chan index | addr low |
4093 * +-------------------------------+------------+----------+
4095 * In other words, the bottom two address bits stay, and the top 30 get
4096 * shifted up so that we can stick the SIMD channel index in the middle. This
4097 * way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
4098 * at the same logical offset, the scratch read/write instruction acts on
4099 * continuous elements and we get good cache locality.
4102 fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
4103 const fs_reg
&nir_addr
,
4106 const fs_reg
&chan_index
=
4107 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
4108 const unsigned chan_index_bits
= ffs(dispatch_width
) - 1;
4110 fs_reg addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4112 /* In this case, we know the address is aligned to a DWORD and we want
4113 * the final address in DWORDs.
4115 bld
.SHL(addr
, nir_addr
, brw_imm_ud(chan_index_bits
- 2));
4116 bld
.OR(addr
, addr
, chan_index
);
4118 /* This case substantially more annoying because we have to pay
4119 * attention to those pesky two bottom bits.
4121 fs_reg addr_hi
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4122 bld
.AND(addr_hi
, nir_addr
, brw_imm_ud(~0x3u
));
4123 bld
.SHL(addr_hi
, addr_hi
, brw_imm_ud(chan_index_bits
));
4124 fs_reg chan_addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4125 bld
.SHL(chan_addr
, chan_index
, brw_imm_ud(2));
4126 bld
.AND(addr
, nir_addr
, brw_imm_ud(0x3u
));
4127 bld
.OR(addr
, addr
, addr_hi
);
4128 bld
.OR(addr
, addr
, chan_addr
);
4134 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4137 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4138 dest
= get_nir_dest(instr
->dest
);
4140 switch (instr
->intrinsic
) {
4141 case nir_intrinsic_image_load
:
4142 case nir_intrinsic_image_store
:
4143 case nir_intrinsic_image_atomic_add
:
4144 case nir_intrinsic_image_atomic_imin
:
4145 case nir_intrinsic_image_atomic_umin
:
4146 case nir_intrinsic_image_atomic_imax
:
4147 case nir_intrinsic_image_atomic_umax
:
4148 case nir_intrinsic_image_atomic_and
:
4149 case nir_intrinsic_image_atomic_or
:
4150 case nir_intrinsic_image_atomic_xor
:
4151 case nir_intrinsic_image_atomic_exchange
:
4152 case nir_intrinsic_image_atomic_comp_swap
:
4153 case nir_intrinsic_bindless_image_load
:
4154 case nir_intrinsic_bindless_image_store
:
4155 case nir_intrinsic_bindless_image_atomic_add
:
4156 case nir_intrinsic_bindless_image_atomic_imin
:
4157 case nir_intrinsic_bindless_image_atomic_umin
:
4158 case nir_intrinsic_bindless_image_atomic_imax
:
4159 case nir_intrinsic_bindless_image_atomic_umax
:
4160 case nir_intrinsic_bindless_image_atomic_and
:
4161 case nir_intrinsic_bindless_image_atomic_or
:
4162 case nir_intrinsic_bindless_image_atomic_xor
:
4163 case nir_intrinsic_bindless_image_atomic_exchange
:
4164 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4165 if (stage
== MESA_SHADER_FRAGMENT
&&
4166 instr
->intrinsic
!= nir_intrinsic_image_load
)
4167 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4169 /* Get some metadata from the image intrinsic. */
4170 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4172 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4174 switch (instr
->intrinsic
) {
4175 case nir_intrinsic_image_load
:
4176 case nir_intrinsic_image_store
:
4177 case nir_intrinsic_image_atomic_add
:
4178 case nir_intrinsic_image_atomic_imin
:
4179 case nir_intrinsic_image_atomic_umin
:
4180 case nir_intrinsic_image_atomic_imax
:
4181 case nir_intrinsic_image_atomic_umax
:
4182 case nir_intrinsic_image_atomic_and
:
4183 case nir_intrinsic_image_atomic_or
:
4184 case nir_intrinsic_image_atomic_xor
:
4185 case nir_intrinsic_image_atomic_exchange
:
4186 case nir_intrinsic_image_atomic_comp_swap
:
4187 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4188 get_nir_image_intrinsic_image(bld
, instr
);
4193 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4194 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4198 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4199 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4200 brw_imm_ud(image_intrinsic_coord_components(instr
));
4202 /* Emit an image load, store or atomic op. */
4203 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4204 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4205 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4207 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4208 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4209 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4210 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4211 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4212 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4213 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4214 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4215 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4217 unsigned num_srcs
= info
->num_srcs
;
4218 int op
= brw_aop_for_nir_intrinsic(instr
);
4219 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4220 assert(num_srcs
== 4);
4224 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4228 data
= get_nir_src(instr
->src
[3]);
4229 if (num_srcs
>= 5) {
4230 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4231 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4232 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4235 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4237 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4238 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4243 case nir_intrinsic_image_size
:
4244 case nir_intrinsic_bindless_image_size
: {
4245 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4246 * into will handle the binding table index for us in the geneerator.
4247 * Incidentally, this means that we can handle bindless with exactly the
4250 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4251 BRW_REGISTER_TYPE_UD
);
4252 image
= bld
.emit_uniformize(image
);
4254 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4255 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4256 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4258 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4259 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4260 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4261 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4263 /* Since the image size is always uniform, we can just emit a SIMD8
4264 * query instruction and splat the result out.
4266 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4268 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4269 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4270 tmp
, srcs
, ARRAY_SIZE(srcs
));
4271 inst
->size_written
= 4 * REG_SIZE
;
4273 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4274 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4275 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4276 offset(retype(dest
, tmp
.type
), bld
, c
),
4277 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4279 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4280 component(offset(tmp
, ubld
, c
), 0));
4286 case nir_intrinsic_image_load_raw_intel
: {
4287 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4288 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4289 get_nir_image_intrinsic_image(bld
, instr
);
4290 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4291 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4292 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4295 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4296 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4297 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4301 case nir_intrinsic_image_store_raw_intel
: {
4302 if (stage
== MESA_SHADER_FRAGMENT
)
4303 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4305 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4306 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4307 get_nir_image_intrinsic_image(bld
, instr
);
4308 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4309 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4310 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4311 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4313 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4314 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4318 case nir_intrinsic_scoped_memory_barrier
:
4319 case nir_intrinsic_group_memory_barrier
:
4320 case nir_intrinsic_memory_barrier_shared
:
4321 case nir_intrinsic_memory_barrier_buffer
:
4322 case nir_intrinsic_memory_barrier_image
:
4323 case nir_intrinsic_memory_barrier
: {
4324 bool l3_fence
, slm_fence
;
4325 if (instr
->intrinsic
== nir_intrinsic_scoped_memory_barrier
) {
4326 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4327 l3_fence
= modes
& (nir_var_shader_out
|
4329 nir_var_mem_global
);
4330 slm_fence
= modes
& nir_var_mem_shared
;
4332 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4333 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4334 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4335 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4338 if (stage
!= MESA_SHADER_COMPUTE
)
4341 /* If the workgroup fits in a single HW thread, the messages for SLM are
4342 * processed in-order and the shader itself is already synchronized so
4343 * the memory fence is not necessary.
4345 * TODO: Check if applies for many HW threads sharing same Data Port.
4347 if (slm_fence
&& workgroup_size() <= dispatch_width
)
4350 /* Prior to Gen11, there's only L3 fence, so emit that instead. */
4351 if (slm_fence
&& devinfo
->gen
< 11) {
4356 /* Be conservative in Gen11+ and always stall in a fence. Since there
4357 * are two different fences, and shader might want to synchronize
4360 * TODO: Improve NIR so that scope and visibility information for the
4361 * barriers is available here to make a better decision.
4363 * TODO: When emitting more than one fence, it might help emit all
4364 * the fences first and then generate the stall moves.
4366 const bool stall
= devinfo
->gen
>= 11;
4368 const fs_builder ubld
= bld
.group(8, 0);
4369 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4372 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4373 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4374 /* bti */ brw_imm_ud(0))
4375 ->size_written
= 2 * REG_SIZE
;
4379 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4380 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4381 brw_imm_ud(GEN7_BTI_SLM
))
4382 ->size_written
= 2 * REG_SIZE
;
4385 if (!l3_fence
&& !slm_fence
)
4386 ubld
.emit(FS_OPCODE_SCHEDULING_FENCE
);
4391 case nir_intrinsic_memory_barrier_tcs_patch
:
4394 case nir_intrinsic_shader_clock
: {
4395 /* We cannot do anything if there is an event, so ignore it for now */
4396 const fs_reg shader_clock
= get_timestamp(bld
);
4397 const fs_reg srcs
[] = { component(shader_clock
, 0),
4398 component(shader_clock
, 1) };
4399 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4403 case nir_intrinsic_image_samples
:
4404 /* The driver does not support multi-sampled images. */
4405 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4408 case nir_intrinsic_load_uniform
: {
4409 /* Offsets are in bytes but they should always aligned to
4412 assert(instr
->const_index
[0] % 4 == 0 ||
4413 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4415 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4417 if (nir_src_is_const(instr
->src
[0])) {
4418 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4419 assert(load_offset
% type_sz(dest
.type
) == 0);
4420 /* For 16-bit types we add the module of the const_index[0]
4421 * offset to access to not 32-bit aligned element
4423 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4425 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4426 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4429 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4430 BRW_REGISTER_TYPE_UD
);
4432 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4433 * go past the end of the uniform. In order to keep the n'th
4434 * component from running past, we subtract off the size of all but
4435 * one component of the vector.
4437 assert(instr
->const_index
[1] >=
4438 instr
->num_components
* (int) type_sz(dest
.type
));
4439 unsigned read_size
= instr
->const_index
[1] -
4440 (instr
->num_components
- 1) * type_sz(dest
.type
);
4442 bool supports_64bit_indirects
=
4443 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4445 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4446 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4447 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4448 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4449 indirect
, brw_imm_ud(read_size
));
4452 const unsigned num_mov_indirects
=
4453 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4454 /* We read a little bit less per MOV INDIRECT, as they are now
4455 * 32-bits ones instead of 64-bit. Fix read_size then.
4457 const unsigned read_size_32bit
= read_size
-
4458 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4459 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4460 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4461 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4462 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4463 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4464 indirect
, brw_imm_ud(read_size_32bit
));
4472 case nir_intrinsic_load_ubo
: {
4474 if (nir_src_is_const(instr
->src
[0])) {
4475 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4476 nir_src_as_uint(instr
->src
[0]);
4477 surf_index
= brw_imm_ud(index
);
4479 /* The block index is not a constant. Evaluate the index expression
4480 * per-channel and add the base UBO index; we have to select a value
4481 * from any live channel.
4483 surf_index
= vgrf(glsl_type::uint_type
);
4484 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4485 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4486 surf_index
= bld
.emit_uniformize(surf_index
);
4489 if (!nir_src_is_const(instr
->src
[1])) {
4490 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4491 BRW_REGISTER_TYPE_UD
);
4493 for (int i
= 0; i
< instr
->num_components
; i
++)
4494 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4495 base_offset
, i
* type_sz(dest
.type
));
4497 prog_data
->has_ubo_pull
= true;
4499 /* Even if we are loading doubles, a pull constant load will load
4500 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4501 * need to load a full dvec4 we will have to emit 2 loads. This is
4502 * similar to demote_pull_constants(), except that in that case we
4503 * see individual accesses to each component of the vector and then
4504 * we let CSE deal with duplicate loads. Here we see a vector access
4505 * and we have to split it if necessary.
4507 const unsigned type_size
= type_sz(dest
.type
);
4508 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4510 /* See if we've selected this as a push constant candidate */
4511 if (nir_src_is_const(instr
->src
[0])) {
4512 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4513 const unsigned offset_256b
= load_offset
/ 32;
4516 for (int i
= 0; i
< 4; i
++) {
4517 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4518 if (range
->block
== ubo_block
&&
4519 offset_256b
>= range
->start
&&
4520 offset_256b
< range
->start
+ range
->length
) {
4522 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4523 push_reg
.offset
= load_offset
- 32 * range
->start
;
4528 if (push_reg
.file
!= BAD_FILE
) {
4529 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4530 bld
.MOV(offset(dest
, bld
, i
),
4531 byte_offset(push_reg
, i
* type_size
));
4537 prog_data
->has_ubo_pull
= true;
4539 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4540 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4541 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4543 for (unsigned c
= 0; c
< instr
->num_components
;) {
4544 const unsigned base
= load_offset
+ c
* type_size
;
4545 /* Number of usable components in the next block-aligned load. */
4546 const unsigned count
= MIN2(instr
->num_components
- c
,
4547 (block_sz
- base
% block_sz
) / type_size
);
4549 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4550 packed_consts
, surf_index
,
4551 brw_imm_ud(base
& ~(block_sz
- 1)));
4553 const fs_reg consts
=
4554 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4557 for (unsigned d
= 0; d
< count
; d
++)
4558 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4566 case nir_intrinsic_load_global
: {
4567 assert(devinfo
->gen
>= 8);
4569 if (nir_intrinsic_align(instr
) >= 4) {
4570 assert(nir_dest_bit_size(instr
->dest
) == 32);
4571 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4573 get_nir_src(instr
->src
[0]), /* Address */
4574 fs_reg(), /* No source data */
4575 brw_imm_ud(instr
->num_components
));
4576 inst
->size_written
= instr
->num_components
*
4577 inst
->dst
.component_size(inst
->exec_size
);
4579 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4580 assert(bit_size
<= 32);
4581 assert(nir_dest_num_components(instr
->dest
) == 1);
4582 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4583 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4585 get_nir_src(instr
->src
[0]), /* Address */
4586 fs_reg(), /* No source data */
4587 brw_imm_ud(bit_size
));
4588 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4593 case nir_intrinsic_store_global
:
4594 assert(devinfo
->gen
>= 8);
4596 if (stage
== MESA_SHADER_FRAGMENT
)
4597 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4599 if (nir_intrinsic_align(instr
) >= 4) {
4600 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4601 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4603 get_nir_src(instr
->src
[1]), /* Address */
4604 get_nir_src(instr
->src
[0]), /* Data */
4605 brw_imm_ud(instr
->num_components
));
4607 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4608 assert(bit_size
<= 32);
4609 assert(nir_src_num_components(instr
->src
[0]) == 1);
4610 brw_reg_type data_type
=
4611 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4612 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4613 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4614 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4616 get_nir_src(instr
->src
[1]), /* Address */
4618 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4622 case nir_intrinsic_global_atomic_add
:
4623 case nir_intrinsic_global_atomic_imin
:
4624 case nir_intrinsic_global_atomic_umin
:
4625 case nir_intrinsic_global_atomic_imax
:
4626 case nir_intrinsic_global_atomic_umax
:
4627 case nir_intrinsic_global_atomic_and
:
4628 case nir_intrinsic_global_atomic_or
:
4629 case nir_intrinsic_global_atomic_xor
:
4630 case nir_intrinsic_global_atomic_exchange
:
4631 case nir_intrinsic_global_atomic_comp_swap
:
4632 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4634 case nir_intrinsic_global_atomic_fmin
:
4635 case nir_intrinsic_global_atomic_fmax
:
4636 case nir_intrinsic_global_atomic_fcomp_swap
:
4637 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4640 case nir_intrinsic_load_ssbo
: {
4641 assert(devinfo
->gen
>= 7);
4643 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4644 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4645 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4646 get_nir_ssbo_intrinsic_index(bld
, instr
);
4647 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4648 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4650 /* Make dest unsigned because that's what the temporary will be */
4651 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4653 /* Read the vector */
4654 if (nir_intrinsic_align(instr
) >= 4) {
4655 assert(nir_dest_bit_size(instr
->dest
) == 32);
4656 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4658 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4659 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4660 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4662 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4663 assert(nir_dest_num_components(instr
->dest
) == 1);
4664 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4666 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4667 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4668 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4669 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4674 case nir_intrinsic_store_ssbo
: {
4675 assert(devinfo
->gen
>= 7);
4677 if (stage
== MESA_SHADER_FRAGMENT
)
4678 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4680 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4681 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4682 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4683 get_nir_ssbo_intrinsic_index(bld
, instr
);
4684 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4685 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4687 fs_reg data
= get_nir_src(instr
->src
[0]);
4688 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4690 assert(nir_intrinsic_write_mask(instr
) ==
4691 (1u << instr
->num_components
) - 1);
4692 if (nir_intrinsic_align(instr
) >= 4) {
4693 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4694 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4695 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4696 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4697 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4698 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4700 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4701 assert(nir_src_num_components(instr
->src
[0]) == 1);
4702 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4704 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4705 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4707 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4708 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4713 case nir_intrinsic_store_output
: {
4714 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4715 fs_reg src
= get_nir_src(instr
->src
[0]);
4717 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4718 unsigned num_components
= instr
->num_components
;
4719 unsigned first_component
= nir_intrinsic_component(instr
);
4721 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4722 4 * store_offset
), src
.type
);
4723 for (unsigned j
= 0; j
< num_components
; j
++) {
4724 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4725 offset(src
, bld
, j
));
4730 case nir_intrinsic_ssbo_atomic_add
:
4731 case nir_intrinsic_ssbo_atomic_imin
:
4732 case nir_intrinsic_ssbo_atomic_umin
:
4733 case nir_intrinsic_ssbo_atomic_imax
:
4734 case nir_intrinsic_ssbo_atomic_umax
:
4735 case nir_intrinsic_ssbo_atomic_and
:
4736 case nir_intrinsic_ssbo_atomic_or
:
4737 case nir_intrinsic_ssbo_atomic_xor
:
4738 case nir_intrinsic_ssbo_atomic_exchange
:
4739 case nir_intrinsic_ssbo_atomic_comp_swap
:
4740 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4742 case nir_intrinsic_ssbo_atomic_fmin
:
4743 case nir_intrinsic_ssbo_atomic_fmax
:
4744 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4745 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4748 case nir_intrinsic_get_buffer_size
: {
4749 assert(nir_src_num_components(instr
->src
[0]) == 1);
4750 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4751 nir_src_as_uint(instr
->src
[0]) : 0;
4753 /* A resinfo's sampler message is used to get the buffer size. The
4754 * SIMD8's writeback message consists of four registers and SIMD16's
4755 * writeback message consists of 8 destination registers (two per each
4756 * component). Because we are only interested on the first channel of
4757 * the first returned component, where resinfo returns the buffer size
4758 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4759 * the dispatch width.
4761 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4762 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4763 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4766 ubld
.MOV(src_payload
, brw_imm_d(0));
4768 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4769 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4770 src_payload
, brw_imm_ud(index
));
4771 inst
->header_size
= 0;
4773 inst
->size_written
= 4 * REG_SIZE
;
4775 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4777 * "Out-of-bounds checking is always performed at a DWord granularity. If
4778 * any part of the DWord is out-of-bounds then the whole DWord is
4779 * considered out-of-bounds."
4781 * This implies that types with size smaller than 4-bytes need to be
4782 * padded if they don't complete the last dword of the buffer. But as we
4783 * need to maintain the original size we need to reverse the padding
4784 * calculation to return the correct size to know the number of elements
4785 * of an unsized array. As we stored in the last two bits of the surface
4786 * size the needed padding for the buffer, we calculate here the
4787 * original buffer_size reversing the surface_size calculation:
4789 * surface_size = isl_align(buffer_size, 4) +
4790 * (isl_align(buffer_size) - buffer_size)
4792 * buffer_size = surface_size & ~3 - surface_size & 3
4795 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4796 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4797 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4799 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4800 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4801 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4803 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4807 case nir_intrinsic_load_scratch
: {
4808 assert(devinfo
->gen
>= 7);
4810 assert(nir_dest_num_components(instr
->dest
) == 1);
4811 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4812 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4814 if (devinfo
->gen
>= 8) {
4815 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4816 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4818 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4821 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4822 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4823 const fs_reg nir_addr
= get_nir_src(instr
->src
[0]);
4825 /* Make dest unsigned because that's what the temporary will be */
4826 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4828 /* Read the vector */
4829 if (nir_intrinsic_align(instr
) >= 4) {
4830 assert(nir_dest_bit_size(instr
->dest
) == 32);
4832 /* The offset for a DWORD scattered message is in dwords. */
4833 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4834 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4836 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
,
4837 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4839 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4841 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4842 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4844 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4845 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4846 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4847 bld
.MOV(dest
, read_result
);
4852 case nir_intrinsic_store_scratch
: {
4853 assert(devinfo
->gen
>= 7);
4855 assert(nir_src_num_components(instr
->src
[0]) == 1);
4856 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4857 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4859 if (devinfo
->gen
>= 8) {
4860 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4861 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4863 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4866 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4867 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4868 const fs_reg nir_addr
= get_nir_src(instr
->src
[1]);
4870 fs_reg data
= get_nir_src(instr
->src
[0]);
4871 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4873 assert(nir_intrinsic_write_mask(instr
) ==
4874 (1u << instr
->num_components
) - 1);
4875 if (nir_intrinsic_align(instr
) >= 4) {
4876 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4877 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4879 /* The offset for a DWORD scattered message is in dwords. */
4880 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4881 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4883 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
,
4884 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4886 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4888 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4889 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4891 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4892 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4894 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4895 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4900 case nir_intrinsic_load_subgroup_size
:
4901 /* This should only happen for fragment shaders because every other case
4902 * is lowered in NIR so we can optimize on it.
4904 assert(stage
== MESA_SHADER_FRAGMENT
);
4905 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4908 case nir_intrinsic_load_subgroup_invocation
:
4909 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4910 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4913 case nir_intrinsic_load_subgroup_eq_mask
:
4914 case nir_intrinsic_load_subgroup_ge_mask
:
4915 case nir_intrinsic_load_subgroup_gt_mask
:
4916 case nir_intrinsic_load_subgroup_le_mask
:
4917 case nir_intrinsic_load_subgroup_lt_mask
:
4918 unreachable("not reached");
4920 case nir_intrinsic_vote_any
: {
4921 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4923 /* The any/all predicates do not consider channel enables. To prevent
4924 * dead channels from affecting the result, we initialize the flag with
4925 * with the identity value for the logical operation.
4927 if (dispatch_width
== 32) {
4928 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4929 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4932 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4934 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4936 /* For some reason, the any/all predicates don't work properly with
4937 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4938 * doesn't read the correct subset of the flag register and you end up
4939 * getting garbage in the second half. Work around this by using a pair
4940 * of 1-wide MOVs and scattering the result.
4942 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4943 ubld
.MOV(res1
, brw_imm_d(0));
4944 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4945 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4946 BRW_PREDICATE_ALIGN1_ANY32H
,
4947 ubld
.MOV(res1
, brw_imm_d(-1)));
4949 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4952 case nir_intrinsic_vote_all
: {
4953 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4955 /* The any/all predicates do not consider channel enables. To prevent
4956 * dead channels from affecting the result, we initialize the flag with
4957 * with the identity value for the logical operation.
4959 if (dispatch_width
== 32) {
4960 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4961 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4962 brw_imm_ud(0xffffffff));
4964 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4966 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4968 /* For some reason, the any/all predicates don't work properly with
4969 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4970 * doesn't read the correct subset of the flag register and you end up
4971 * getting garbage in the second half. Work around this by using a pair
4972 * of 1-wide MOVs and scattering the result.
4974 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4975 ubld
.MOV(res1
, brw_imm_d(0));
4976 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4977 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4978 BRW_PREDICATE_ALIGN1_ALL32H
,
4979 ubld
.MOV(res1
, brw_imm_d(-1)));
4981 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4984 case nir_intrinsic_vote_feq
:
4985 case nir_intrinsic_vote_ieq
: {
4986 fs_reg value
= get_nir_src(instr
->src
[0]);
4987 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4988 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4989 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4990 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4993 fs_reg uniformized
= bld
.emit_uniformize(value
);
4994 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4996 /* The any/all predicates do not consider channel enables. To prevent
4997 * dead channels from affecting the result, we initialize the flag with
4998 * with the identity value for the logical operation.
5000 if (dispatch_width
== 32) {
5001 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
5002 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
5003 brw_imm_ud(0xffffffff));
5005 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
5007 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
5009 /* For some reason, the any/all predicates don't work properly with
5010 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
5011 * doesn't read the correct subset of the flag register and you end up
5012 * getting garbage in the second half. Work around this by using a pair
5013 * of 1-wide MOVs and scattering the result.
5015 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
5016 ubld
.MOV(res1
, brw_imm_d(0));
5017 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
5018 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
5019 BRW_PREDICATE_ALIGN1_ALL32H
,
5020 ubld
.MOV(res1
, brw_imm_d(-1)));
5022 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
5026 case nir_intrinsic_ballot
: {
5027 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
5028 BRW_REGISTER_TYPE_UD
);
5029 struct brw_reg flag
= brw_flag_reg(0, 0);
5030 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
5031 * as f0.0. This is a problem for fragment programs as we currently use
5032 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
5033 * programs yet so this isn't a problem. When we do, something will
5036 if (dispatch_width
== 32)
5037 flag
.type
= BRW_REGISTER_TYPE_UD
;
5039 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
5040 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
5042 if (instr
->dest
.ssa
.bit_size
> 32) {
5043 dest
.type
= BRW_REGISTER_TYPE_UQ
;
5045 dest
.type
= BRW_REGISTER_TYPE_UD
;
5047 bld
.MOV(dest
, flag
);
5051 case nir_intrinsic_read_invocation
: {
5052 const fs_reg value
= get_nir_src(instr
->src
[0]);
5053 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
5054 fs_reg tmp
= bld
.vgrf(value
.type
);
5056 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
5057 bld
.emit_uniformize(invocation
));
5059 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
5063 case nir_intrinsic_read_first_invocation
: {
5064 const fs_reg value
= get_nir_src(instr
->src
[0]);
5065 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
5069 case nir_intrinsic_shuffle
: {
5070 const fs_reg value
= get_nir_src(instr
->src
[0]);
5071 const fs_reg index
= get_nir_src(instr
->src
[1]);
5073 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
5077 case nir_intrinsic_first_invocation
: {
5078 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5079 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
5080 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
5081 fs_reg(component(tmp
, 0)));
5085 case nir_intrinsic_quad_broadcast
: {
5086 const fs_reg value
= get_nir_src(instr
->src
[0]);
5087 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
5089 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
5090 value
, brw_imm_ud(index
), brw_imm_ud(4));
5094 case nir_intrinsic_quad_swap_horizontal
: {
5095 const fs_reg value
= get_nir_src(instr
->src
[0]);
5096 const fs_reg tmp
= bld
.vgrf(value
.type
);
5097 if (devinfo
->gen
<= 7) {
5098 /* The hardware doesn't seem to support these crazy regions with
5099 * compressed instructions on gen7 and earlier so we fall back to
5100 * using quad swizzles. Fortunately, we don't support 64-bit
5101 * anything in Vulkan on gen7.
5103 assert(nir_src_bit_size(instr
->src
[0]) == 32);
5104 const fs_builder ubld
= bld
.exec_all();
5105 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5106 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
5107 bld
.MOV(retype(dest
, value
.type
), tmp
);
5109 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
5111 const fs_reg src_left
= horiz_stride(value
, 2);
5112 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
5113 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
5114 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
5116 ubld
.MOV(tmp_left
, src_right
);
5117 ubld
.MOV(tmp_right
, src_left
);
5120 bld
.MOV(retype(dest
, value
.type
), tmp
);
5124 case nir_intrinsic_quad_swap_vertical
: {
5125 const fs_reg value
= get_nir_src(instr
->src
[0]);
5126 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5127 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5128 const fs_reg tmp
= bld
.vgrf(value
.type
);
5129 const fs_builder ubld
= bld
.exec_all();
5130 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5131 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5132 bld
.MOV(retype(dest
, value
.type
), tmp
);
5134 /* For larger data types, we have to either emit dispatch_width many
5135 * MOVs or else fall back to doing indirects.
5137 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5138 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5140 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5145 case nir_intrinsic_quad_swap_diagonal
: {
5146 const fs_reg value
= get_nir_src(instr
->src
[0]);
5147 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5148 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5149 const fs_reg tmp
= bld
.vgrf(value
.type
);
5150 const fs_builder ubld
= bld
.exec_all();
5151 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5152 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5153 bld
.MOV(retype(dest
, value
.type
), tmp
);
5155 /* For larger data types, we have to either emit dispatch_width many
5156 * MOVs or else fall back to doing indirects.
5158 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5159 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5161 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5166 case nir_intrinsic_reduce
: {
5167 fs_reg src
= get_nir_src(instr
->src
[0]);
5168 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5169 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5170 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5171 cluster_size
= dispatch_width
;
5173 /* Figure out the source type */
5174 src
.type
= brw_type_for_nir_type(devinfo
,
5175 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5176 nir_src_bit_size(instr
->src
[0])));
5178 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5179 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5180 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5182 /* There are a couple of register region issues that make things
5183 * complicated for 8-bit types:
5185 * 1. Only raw moves are allowed to write to a packed 8-bit
5187 * 2. If we use a strided destination, the efficient way to do scan
5188 * operations ends up using strides that are too big to encode in
5191 * To get around these issues, we just do all 8-bit scan operations in
5192 * 16 bits. It's actually fewer instructions than what we'd have to do
5193 * if we were trying to do it in native 8-bit types and the results are
5194 * the same once we truncate to 8 bits at the end.
5196 brw_reg_type scan_type
= src
.type
;
5197 if (type_sz(scan_type
) == 1)
5198 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5200 /* Set up a register for all of our scratching around and initialize it
5201 * to reduction operation's identity value.
5203 fs_reg scan
= bld
.vgrf(scan_type
);
5204 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5206 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5208 dest
.type
= src
.type
;
5209 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5210 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5211 * the distance between clusters is at least 2 GRFs. In this case,
5212 * we don't need the weird striding of the CLUSTER_BROADCAST
5213 * instruction and can just do regular MOVs.
5215 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5216 const unsigned groups
=
5217 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5218 const unsigned group_size
= dispatch_width
/ groups
;
5219 for (unsigned i
= 0; i
< groups
; i
++) {
5220 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5221 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5222 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5223 component(scan
, comp
));
5226 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5227 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5232 case nir_intrinsic_inclusive_scan
:
5233 case nir_intrinsic_exclusive_scan
: {
5234 fs_reg src
= get_nir_src(instr
->src
[0]);
5235 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5237 /* Figure out the source type */
5238 src
.type
= brw_type_for_nir_type(devinfo
,
5239 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5240 nir_src_bit_size(instr
->src
[0])));
5242 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5243 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5244 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5246 /* There are a couple of register region issues that make things
5247 * complicated for 8-bit types:
5249 * 1. Only raw moves are allowed to write to a packed 8-bit
5251 * 2. If we use a strided destination, the efficient way to do scan
5252 * operations ends up using strides that are too big to encode in
5255 * To get around these issues, we just do all 8-bit scan operations in
5256 * 16 bits. It's actually fewer instructions than what we'd have to do
5257 * if we were trying to do it in native 8-bit types and the results are
5258 * the same once we truncate to 8 bits at the end.
5260 brw_reg_type scan_type
= src
.type
;
5261 if (type_sz(scan_type
) == 1)
5262 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5264 /* Set up a register for all of our scratching around and initialize it
5265 * to reduction operation's identity value.
5267 fs_reg scan
= bld
.vgrf(scan_type
);
5268 const fs_builder allbld
= bld
.exec_all();
5269 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5271 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5272 /* Exclusive scan is a bit harder because we have to do an annoying
5273 * shift of the contents before we can begin. To make things worse,
5274 * we can't do this with a normal stride; we have to use indirects.
5276 fs_reg shifted
= bld
.vgrf(scan_type
);
5277 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5278 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5280 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5281 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5285 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5287 bld
.MOV(retype(dest
, src
.type
), scan
);
5291 case nir_intrinsic_begin_invocation_interlock
: {
5292 const fs_builder ubld
= bld
.group(8, 0);
5293 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5295 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5296 ->size_written
= 2 * REG_SIZE
;
5300 case nir_intrinsic_end_invocation_interlock
: {
5301 /* For endInvocationInterlock(), we need to insert a memory fence which
5302 * stalls in the shader until the memory transactions prior to that
5303 * fence are complete. This ensures that the shader does not end before
5304 * any writes from its critical section have landed. Otherwise, you can
5305 * end up with a case where the next invocation on that pixel properly
5306 * stalls for previous FS invocation on its pixel to complete but
5307 * doesn't actually wait for the dataport memory transactions from that
5308 * thread to land before submitting its own.
5310 const fs_builder ubld
= bld
.group(8, 0);
5311 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5312 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5313 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5314 ->size_written
= 2 * REG_SIZE
;
5319 unreachable("unknown intrinsic");
5324 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5325 int op
, nir_intrinsic_instr
*instr
)
5327 if (stage
== MESA_SHADER_FRAGMENT
)
5328 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5330 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5331 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5332 * appear to exist. However, if you look at Vol 2a, there are no message
5333 * descriptors provided for Qword atomic ops except for A64 messages.
5335 assert(nir_dest_bit_size(instr
->dest
) == 32);
5338 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5339 dest
= get_nir_dest(instr
->dest
);
5341 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5342 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5343 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5344 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5345 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5348 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5349 data
= get_nir_src(instr
->src
[2]);
5351 if (op
== BRW_AOP_CMPWR
) {
5352 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5353 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5354 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5357 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5359 /* Emit the actual atomic operation */
5361 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5362 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5366 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5367 int op
, nir_intrinsic_instr
*instr
)
5369 if (stage
== MESA_SHADER_FRAGMENT
)
5370 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5373 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5374 dest
= get_nir_dest(instr
->dest
);
5376 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5377 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5378 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5379 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5380 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5382 fs_reg data
= get_nir_src(instr
->src
[2]);
5383 if (op
== BRW_AOP_FCMPWR
) {
5384 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5385 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5386 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5389 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5391 /* Emit the actual atomic operation */
5393 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5394 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5398 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5399 int op
, nir_intrinsic_instr
*instr
)
5402 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5403 dest
= get_nir_dest(instr
->dest
);
5405 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5406 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5407 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5408 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5411 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5412 data
= get_nir_src(instr
->src
[1]);
5413 if (op
== BRW_AOP_CMPWR
) {
5414 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5415 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5416 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5419 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5421 /* Get the offset */
5422 if (nir_src_is_const(instr
->src
[0])) {
5423 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5424 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5426 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5427 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5428 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5429 brw_imm_ud(instr
->const_index
[0]));
5432 /* Emit the actual atomic operation operation */
5434 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5435 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5439 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5440 int op
, nir_intrinsic_instr
*instr
)
5443 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5444 dest
= get_nir_dest(instr
->dest
);
5446 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5447 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5448 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5449 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5451 fs_reg data
= get_nir_src(instr
->src
[1]);
5452 if (op
== BRW_AOP_FCMPWR
) {
5453 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5454 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5455 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5458 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5460 /* Get the offset */
5461 if (nir_src_is_const(instr
->src
[0])) {
5462 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5463 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5465 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5466 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5467 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5468 brw_imm_ud(instr
->const_index
[0]));
5471 /* Emit the actual atomic operation operation */
5473 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5474 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5478 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5479 int op
, nir_intrinsic_instr
*instr
)
5481 if (stage
== MESA_SHADER_FRAGMENT
)
5482 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5485 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5486 dest
= get_nir_dest(instr
->dest
);
5488 fs_reg addr
= get_nir_src(instr
->src
[0]);
5491 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5492 data
= get_nir_src(instr
->src
[1]);
5494 if (op
== BRW_AOP_CMPWR
) {
5495 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5496 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5497 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5501 if (nir_dest_bit_size(instr
->dest
) == 64) {
5502 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5503 dest
, addr
, data
, brw_imm_ud(op
));
5505 assert(nir_dest_bit_size(instr
->dest
) == 32);
5506 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5507 dest
, addr
, data
, brw_imm_ud(op
));
5512 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5513 int op
, nir_intrinsic_instr
*instr
)
5515 if (stage
== MESA_SHADER_FRAGMENT
)
5516 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5518 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5519 fs_reg dest
= get_nir_dest(instr
->dest
);
5521 fs_reg addr
= get_nir_src(instr
->src
[0]);
5523 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5524 fs_reg data
= get_nir_src(instr
->src
[1]);
5526 if (op
== BRW_AOP_FCMPWR
) {
5527 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5528 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5529 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5533 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5534 dest
, addr
, data
, brw_imm_ud(op
));
5538 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5540 unsigned texture
= instr
->texture_index
;
5541 unsigned sampler
= instr
->sampler_index
;
5543 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5545 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5546 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5548 int lod_components
= 0;
5550 /* The hardware requires a LOD for buffer textures */
5551 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5552 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5554 uint32_t header_bits
= 0;
5555 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5556 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5557 switch (instr
->src
[i
].src_type
) {
5558 case nir_tex_src_bias
:
5559 srcs
[TEX_LOGICAL_SRC_LOD
] =
5560 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5562 case nir_tex_src_comparator
:
5563 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5565 case nir_tex_src_coord
:
5566 switch (instr
->op
) {
5568 case nir_texop_txf_ms
:
5569 case nir_texop_txf_ms_mcs
:
5570 case nir_texop_samples_identical
:
5571 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5574 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5578 case nir_tex_src_ddx
:
5579 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5580 lod_components
= nir_tex_instr_src_size(instr
, i
);
5582 case nir_tex_src_ddy
:
5583 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5585 case nir_tex_src_lod
:
5586 switch (instr
->op
) {
5588 srcs
[TEX_LOGICAL_SRC_LOD
] =
5589 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5592 srcs
[TEX_LOGICAL_SRC_LOD
] =
5593 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5596 srcs
[TEX_LOGICAL_SRC_LOD
] =
5597 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5601 case nir_tex_src_min_lod
:
5602 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5603 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5605 case nir_tex_src_ms_index
:
5606 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5609 case nir_tex_src_offset
: {
5610 uint32_t offset_bits
= 0;
5611 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5612 header_bits
|= offset_bits
;
5614 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5615 retype(src
, BRW_REGISTER_TYPE_D
);
5620 case nir_tex_src_projector
:
5621 unreachable("should be lowered");
5623 case nir_tex_src_texture_offset
: {
5624 /* Emit code to evaluate the actual indexing expression */
5625 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5626 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5627 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5631 case nir_tex_src_sampler_offset
: {
5632 /* Emit code to evaluate the actual indexing expression */
5633 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5634 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5635 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5639 case nir_tex_src_texture_handle
:
5640 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5641 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5642 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5645 case nir_tex_src_sampler_handle
:
5646 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5647 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5648 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5651 case nir_tex_src_ms_mcs
:
5652 assert(instr
->op
== nir_texop_txf_ms
);
5653 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5656 case nir_tex_src_plane
: {
5657 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5658 const uint32_t texture_index
=
5659 instr
->texture_index
+
5660 stage_prog_data
->binding_table
.plane_start
[plane
] -
5661 stage_prog_data
->binding_table
.texture_start
;
5663 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5668 unreachable("unknown texture source");
5672 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5673 (instr
->op
== nir_texop_txf_ms
||
5674 instr
->op
== nir_texop_samples_identical
)) {
5675 if (devinfo
->gen
>= 7 &&
5676 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5677 srcs
[TEX_LOGICAL_SRC_MCS
] =
5678 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5679 instr
->coord_components
,
5680 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5681 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5683 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5687 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5688 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5691 switch (instr
->op
) {
5693 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5696 opcode
= FS_OPCODE_TXB_LOGICAL
;
5699 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5702 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5705 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5707 case nir_texop_txf_ms
:
5708 if ((key_tex
->msaa_16
& (1 << sampler
)))
5709 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5711 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5713 case nir_texop_txf_ms_mcs
:
5714 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5716 case nir_texop_query_levels
:
5718 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5721 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5724 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5725 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5727 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5729 case nir_texop_texture_samples
:
5730 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5732 case nir_texop_samples_identical
: {
5733 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5735 /* If mcs is an immediate value, it means there is no MCS. In that case
5736 * just return false.
5738 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5739 bld
.MOV(dst
, brw_imm_ud(0u));
5740 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5741 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5742 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5743 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5744 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5746 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5747 BRW_CONDITIONAL_EQ
);
5752 unreachable("unknown texture opcode");
5755 if (instr
->op
== nir_texop_tg4
) {
5756 if (instr
->component
== 1 &&
5757 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5758 /* gather4 sampler is broken for green channel on RG32F --
5759 * we must ask for blue instead.
5761 header_bits
|= 2 << 16;
5763 header_bits
|= instr
->component
<< 16;
5767 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5768 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5769 inst
->offset
= header_bits
;
5771 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5772 if (devinfo
->gen
>= 9 &&
5773 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5774 unsigned write_mask
= instr
->dest
.is_ssa
?
5775 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5776 (1 << dest_size
) - 1;
5777 assert(write_mask
!= 0); /* dead code should have been eliminated */
5778 inst
->size_written
= util_last_bit(write_mask
) *
5779 inst
->dst
.component_size(inst
->exec_size
);
5781 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5784 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5785 inst
->shadow_compare
= true;
5787 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5788 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5791 for (unsigned i
= 0; i
< dest_size
; i
++)
5792 nir_dest
[i
] = offset(dst
, bld
, i
);
5794 if (instr
->op
== nir_texop_query_levels
) {
5795 /* # levels is in .w */
5796 nir_dest
[0] = offset(dst
, bld
, 3);
5797 } else if (instr
->op
== nir_texop_txs
&&
5798 dest_size
>= 3 && devinfo
->gen
< 7) {
5799 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5800 fs_reg depth
= offset(dst
, bld
, 2);
5801 nir_dest
[2] = vgrf(glsl_type::int_type
);
5802 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5805 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5809 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5811 switch (instr
->type
) {
5812 case nir_jump_break
:
5813 bld
.emit(BRW_OPCODE_BREAK
);
5815 case nir_jump_continue
:
5816 bld
.emit(BRW_OPCODE_CONTINUE
);
5818 case nir_jump_return
:
5820 unreachable("unknown jump");
5825 * This helper takes a source register and un/shuffles it into the destination
5828 * If source type size is smaller than destination type size the operation
5829 * needed is a component shuffle. The opposite case would be an unshuffle. If
5830 * source/destination type size is equal a shuffle is done that would be
5831 * equivalent to a simple MOV.
5833 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5834 * components .xyz 16-bit vector on SIMD8 would be.
5836 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5837 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5839 * This helper will return the following 2 32-bit components with the 16-bit
5842 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5843 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5845 * For unshuffle, the example would be the opposite, a 64-bit type source
5846 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5849 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5850 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5851 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5852 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5854 * The returned result would be the following 4 32-bit components unshuffled:
5856 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5857 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5858 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5859 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5861 * - Source and destination register must not be overlapped.
5862 * - components units are measured in terms of the smaller type between
5863 * source and destination because we are un/shuffling the smaller
5864 * components from/into the bigger ones.
5865 * - first_component parameter allows skipping source components.
5868 shuffle_src_to_dst(const fs_builder
&bld
,
5871 uint32_t first_component
,
5872 uint32_t components
)
5874 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5875 assert(!regions_overlap(dst
,
5876 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5877 offset(src
, bld
, first_component
),
5878 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5879 for (unsigned i
= 0; i
< components
; i
++) {
5880 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5881 offset(src
, bld
, i
+ first_component
));
5883 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5884 /* Source is shuffled into destination */
5885 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5886 assert(!regions_overlap(dst
,
5887 type_sz(dst
.type
) * bld
.dispatch_width() *
5888 DIV_ROUND_UP(components
, size_ratio
),
5889 offset(src
, bld
, first_component
),
5890 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5892 brw_reg_type shuffle_type
=
5893 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5894 BRW_REGISTER_TYPE_D
);
5895 for (unsigned i
= 0; i
< components
; i
++) {
5896 fs_reg shuffle_component_i
=
5897 subscript(offset(dst
, bld
, i
/ size_ratio
),
5898 shuffle_type
, i
% size_ratio
);
5899 bld
.MOV(shuffle_component_i
,
5900 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5903 /* Source is unshuffled into destination */
5904 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5905 assert(!regions_overlap(dst
,
5906 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5907 offset(src
, bld
, first_component
/ size_ratio
),
5908 type_sz(src
.type
) * bld
.dispatch_width() *
5909 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5912 brw_reg_type shuffle_type
=
5913 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5914 BRW_REGISTER_TYPE_D
);
5915 for (unsigned i
= 0; i
< components
; i
++) {
5916 fs_reg shuffle_component_i
=
5917 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5918 shuffle_type
, (first_component
+ i
) % size_ratio
);
5919 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5920 shuffle_component_i
);
5926 shuffle_from_32bit_read(const fs_builder
&bld
,
5929 uint32_t first_component
,
5930 uint32_t components
)
5932 assert(type_sz(src
.type
) == 4);
5934 /* This function takes components in units of the destination type while
5935 * shuffle_src_to_dst takes components in units of the smallest type
5937 if (type_sz(dst
.type
) > 4) {
5938 assert(type_sz(dst
.type
) == 8);
5939 first_component
*= 2;
5943 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5947 setup_imm_df(const fs_builder
&bld
, double v
)
5949 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5950 assert(devinfo
->gen
>= 7);
5952 if (devinfo
->gen
>= 8)
5953 return brw_imm_df(v
);
5955 /* gen7.5 does not support DF immediates straighforward but the DIM
5956 * instruction allows to set the 64-bit immediate value.
5958 if (devinfo
->is_haswell
) {
5959 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5960 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5961 ubld
.DIM(dst
, brw_imm_df(v
));
5962 return component(dst
, 0);
5965 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5966 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5967 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5969 * Alternatively, we could also produce a normal VGRF (without stride 0)
5970 * by writing to all the channels in the VGRF, however, that would hit the
5971 * gen7 bug where we have to split writes that span more than 1 register
5972 * into instructions with a width of 4 (otherwise the write to the second
5973 * register written runs into an execmask hardware bug) which isn't very
5986 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5987 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5988 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5989 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5991 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5995 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5997 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5998 bld
.MOV(tmp
, brw_imm_w(v
));
6003 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
6005 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
6006 bld
.MOV(tmp
, brw_imm_uw(v
));