2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
, true);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
389 /* If the condition has the form !other_condition, use other_condition as
390 * the source, but invert the predicate on the if instruction.
392 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
393 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
394 assert(!cond
->src
[0].negate
);
395 assert(!cond
->src
[0].abs
);
398 cond_reg
= get_nir_src(cond
->src
[0].src
);
401 cond_reg
= get_nir_src(if_stmt
->condition
);
404 /* first, put the condition into f0 */
405 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
406 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
409 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
411 nir_emit_cf_list(&if_stmt
->then_list
);
413 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
414 bld
.emit(BRW_OPCODE_ELSE
);
415 nir_emit_cf_list(&if_stmt
->else_list
);
418 bld
.emit(BRW_OPCODE_ENDIF
);
420 if (devinfo
->gen
< 7)
421 limit_dispatch_width(16, "Non-uniform control flow unsupported "
426 fs_visitor::nir_emit_loop(nir_loop
*loop
)
428 bld
.emit(BRW_OPCODE_DO
);
430 nir_emit_cf_list(&loop
->body
);
432 bld
.emit(BRW_OPCODE_WHILE
);
434 if (devinfo
->gen
< 7)
435 limit_dispatch_width(16, "Non-uniform control flow unsupported "
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
457 case nir_instr_type_deref
:
458 unreachable("All derefs should've been lowered");
461 case nir_instr_type_intrinsic
:
463 case MESA_SHADER_VERTEX
:
464 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_TESS_CTRL
:
467 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_EVAL
:
470 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_GEOMETRY
:
473 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_FRAGMENT
:
476 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_COMPUTE
:
479 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
482 unreachable("unsupported shader stage");
486 case nir_instr_type_tex
:
487 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
490 case nir_instr_type_load_const
:
491 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
494 case nir_instr_type_ssa_undef
:
495 /* We create a new VGRF for undefs on every use (by handling
496 * them in get_nir_src()), rather than for each definition.
497 * This helps register coalescing eliminate MOVs from undef.
501 case nir_instr_type_jump
:
502 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
506 unreachable("unknown instruction type");
511 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
515 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
516 const fs_reg
&result
)
518 if (!instr
->src
[0].src
.is_ssa
||
519 !instr
->src
[0].src
.ssa
->parent_instr
)
522 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
525 nir_alu_instr
*src0
=
526 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
528 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
529 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
532 /* If either opcode has source modifiers, bail.
534 * TODO: We can potentially handle source modifiers if both of the opcodes
535 * we're combining are signed integers.
537 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
538 src0
->src
[0].abs
|| src0
->src
[0].negate
)
541 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
543 /* Element type to extract.*/
544 const brw_reg_type type
= brw_int_type(
545 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
546 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
548 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
549 op0
.type
= brw_type_for_nir_type(devinfo
,
550 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
551 nir_src_bit_size(src0
->src
[0].src
)));
552 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
554 set_saturate(instr
->dest
.saturate
,
555 bld
.MOV(result
, subscript(op0
, type
, element
)));
560 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
561 const fs_reg
&result
)
563 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
564 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
567 if (!nir_src_is_const(instr
->src
[1].src
) ||
568 !nir_src_is_const(instr
->src
[2].src
))
571 const float value1
= nir_src_as_float(instr
->src
[1].src
);
572 const float value2
= nir_src_as_float(instr
->src
[2].src
);
573 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
576 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
577 assert(value1
== -value2
);
579 fs_reg tmp
= vgrf(glsl_type::int_type
);
581 if (devinfo
->gen
>= 6) {
582 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
583 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
585 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
587 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
588 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
590 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
592 * This negation looks like it's safe in practice, because bits 0:4 will
593 * surely be TRIANGLES
596 if (value1
== -1.0f
) {
600 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
601 g0
, brw_imm_uw(0x3f80));
603 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
604 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
606 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
608 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
609 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
611 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
613 * This negation looks like it's safe in practice, because bits 0:4 will
614 * surely be TRIANGLES
617 if (value1
== -1.0f
) {
621 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
623 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
629 emit_find_msb_using_lzd(const fs_builder
&bld
,
630 const fs_reg
&result
,
638 /* LZD of an absolute value source almost always does the right
639 * thing. There are two problem values:
641 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
642 * 0. However, findMSB(int(0x80000000)) == 30.
644 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
645 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
647 * For a value of zero or negative one, -1 will be returned.
649 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
650 * findMSB(-(1<<x)) should return x-1.
652 * For all negative number cases, including 0x80000000 and
653 * 0xffffffff, the correct value is obtained from LZD if instead of
654 * negating the (already negative) value the logical-not is used. A
655 * conditonal logical-not can be achieved in two instructions.
657 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
659 bld
.ASR(temp
, src
, brw_imm_d(31));
660 bld
.XOR(temp
, temp
, src
);
663 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
664 retype(temp
, BRW_REGISTER_TYPE_UD
));
666 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
667 * from the LSB side. Subtract the result from 31 to convert the MSB
668 * count into an LSB count. If no bits are set, LZD will return 32.
669 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
671 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
672 inst
->src
[0].negate
= true;
676 brw_rnd_mode_from_nir_op (const nir_op op
) {
678 case nir_op_f2f16_rtz
:
679 return BRW_RND_MODE_RTZ
;
680 case nir_op_f2f16_rtne
:
681 return BRW_RND_MODE_RTNE
;
683 unreachable("Operation doesn't support rounding mode");
688 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
689 nir_alu_instr
*instr
,
694 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
696 result
.type
= brw_type_for_nir_type(devinfo
,
697 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
698 nir_dest_bit_size(instr
->dest
.dest
)));
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 op
[i
] = get_nir_src(instr
->src
[i
].src
);
702 op
[i
].type
= brw_type_for_nir_type(devinfo
,
703 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
704 nir_src_bit_size(instr
->src
[i
].src
)));
705 op
[i
].abs
= instr
->src
[i
].abs
;
706 op
[i
].negate
= instr
->src
[i
].negate
;
709 /* Move and vecN instrutions may still be vectored. Return the raw,
710 * vectored source and destination so that fs_visitor::nir_emit_alu can
711 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) == 2) {
875 /* AND(val, 0x8000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
879 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
880 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
882 op
[0].type
= BRW_REGISTER_TYPE_UW
;
883 result
.type
= BRW_REGISTER_TYPE_UW
;
884 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
886 if (instr
->op
== nir_op_fsign
)
887 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
889 /* Use XOR here to get the result sign correct. */
890 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
894 } else if (type_sz(op
[0].type
) == 4) {
895 /* AND(val, 0x80000000) gives the sign bit.
897 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
900 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 op
[0].type
= BRW_REGISTER_TYPE_UD
;
903 result
.type
= BRW_REGISTER_TYPE_UD
;
904 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
906 if (instr
->op
== nir_op_fsign
)
907 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
909 /* Use XOR here to get the result sign correct. */
910 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
915 /* For doubles we do the same but we need to consider:
917 * - 2-src instructions can't operate with 64-bit immediates
918 * - The sign is encoded in the high 32-bit of each DF
919 * - We need to produce a DF result.
922 fs_reg zero
= vgrf(glsl_type::double_type
);
923 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
924 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
926 bld
.MOV(result
, zero
);
928 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
929 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
930 brw_imm_ud(0x80000000u
));
932 if (instr
->op
== nir_op_fsign
) {
933 set_predicate(BRW_PREDICATE_NORMAL
,
934 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
936 /* This could be done better in some cases. If the scale is an
937 * immediate with the low 32-bits all 0, emitting a separate XOR and
938 * OR would allow an algebraic optimization to remove the OR. There
939 * are currently zero instances of fsign(double(x))*IMM in shader-db
940 * or any test suite, so it is hard to care at this time.
942 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
943 inst
= bld
.XOR(result_int64
, result_int64
,
944 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
950 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
952 * Checks the operands of a \c nir_op_fmul to determine whether or not
953 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
955 * \param instr The multiplication instruction
957 * \param fsign_src The source of \c instr that may or may not be a
961 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
963 assert(instr
->op
== nir_op_fmul
);
965 nir_alu_instr
*const fsign_instr
=
966 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
970 * 1. instr->src[fsign_src] must be a nir_op_fsign.
971 * 2. The nir_op_fsign can only be used by this multiplication.
972 * 3. The source that is the nir_op_fsign does not have source modifiers.
973 * \c emit_fsign only examines the source modifiers of the source of the
976 * The nir_op_fsign must also not have the saturate modifier, but steps
977 * have already been taken (in nir_opt_algebraic) to ensure that.
979 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
980 is_used_once(fsign_instr
) &&
981 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
985 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
988 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
992 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
999 fs_reg temp
= result
;
1000 bool need_extra_copy
= false;
1001 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1002 if (!instr
->src
[i
].src
.is_ssa
&&
1003 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1004 need_extra_copy
= true;
1005 temp
= bld
.vgrf(result
.type
, 4);
1010 for (unsigned i
= 0; i
< 4; i
++) {
1011 if (!(instr
->dest
.write_mask
& (1 << i
)))
1014 if (instr
->op
== nir_op_mov
) {
1015 inst
= bld
.MOV(offset(temp
, bld
, i
),
1016 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1018 inst
= bld
.MOV(offset(temp
, bld
, i
),
1019 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1021 inst
->saturate
= instr
->dest
.saturate
;
1024 /* In this case the source and destination registers were the same,
1025 * so we need to insert an extra set of moves in order to deal with
1028 if (need_extra_copy
) {
1029 for (unsigned i
= 0; i
< 4; i
++) {
1030 if (!(instr
->dest
.write_mask
& (1 << i
)))
1033 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1041 if (optimize_extract_to_float(instr
, result
))
1043 inst
= bld
.MOV(result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1047 case nir_op_f2f16_rtne
:
1048 case nir_op_f2f16_rtz
:
1049 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1050 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1053 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1054 * on the HW gen, it is a special hw opcode or just a MOV, and
1055 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1057 * But if we want to use that opcode, we need to provide support on
1058 * different optimizations and lowerings. As right now HF support is
1059 * only for gen8+, it will be better to use directly the MOV, and use
1060 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1062 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1063 inst
= bld
.MOV(result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1074 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1076 op
[0].type
= BRW_REGISTER_TYPE_D
;
1077 op
[0].negate
= !op
[0].negate
;
1101 if (result
.type
== BRW_REGISTER_TYPE_B
||
1102 result
.type
== BRW_REGISTER_TYPE_UB
||
1103 result
.type
== BRW_REGISTER_TYPE_HF
)
1104 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1106 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1107 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1108 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1109 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1111 inst
= bld
.MOV(result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 inst
= bld
.MOV(result
, op
[0]);
1117 inst
->saturate
= true;
1122 op
[0].negate
= true;
1123 inst
= bld
.MOV(result
, op
[0]);
1124 if (instr
->op
== nir_op_fneg
)
1125 inst
->saturate
= instr
->dest
.saturate
;
1130 op
[0].negate
= false;
1132 inst
= bld
.MOV(result
, op
[0]);
1133 if (instr
->op
== nir_op_fabs
)
1134 inst
->saturate
= instr
->dest
.saturate
;
1138 emit_fsign(bld
, instr
, result
, op
, 0);
1142 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1143 inst
->saturate
= instr
->dest
.saturate
;
1147 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1148 inst
->saturate
= instr
->dest
.saturate
;
1152 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1162 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1163 inst
->saturate
= instr
->dest
.saturate
;
1167 if (fs_key
->high_quality_derivatives
) {
1168 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1170 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1172 inst
->saturate
= instr
->dest
.saturate
;
1174 case nir_op_fddx_fine
:
1175 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1176 inst
->saturate
= instr
->dest
.saturate
;
1178 case nir_op_fddx_coarse
:
1179 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 if (fs_key
->high_quality_derivatives
) {
1184 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1186 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1190 case nir_op_fddy_fine
:
1191 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1192 inst
->saturate
= instr
->dest
.saturate
;
1194 case nir_op_fddy_coarse
:
1195 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1196 inst
->saturate
= instr
->dest
.saturate
;
1201 inst
= bld
.ADD(result
, op
[0], op
[1]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1205 case nir_op_uadd_sat
:
1206 inst
= bld
.ADD(result
, op
[0], op
[1]);
1207 inst
->saturate
= true;
1211 for (unsigned i
= 0; i
< 2; i
++) {
1212 if (can_fuse_fmul_fsign(instr
, i
)) {
1213 emit_fsign(bld
, instr
, result
, op
, i
);
1218 inst
= bld
.MUL(result
, op
[0], op
[1]);
1219 inst
->saturate
= instr
->dest
.saturate
;
1222 case nir_op_imul_2x32_64
:
1223 case nir_op_umul_2x32_64
:
1224 bld
.MUL(result
, op
[0], op
[1]);
1228 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1229 bld
.MUL(result
, op
[0], op
[1]);
1232 case nir_op_imul_high
:
1233 case nir_op_umul_high
:
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1240 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1241 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1244 case nir_op_uadd_carry
:
1245 unreachable("Should have been lowered by carry_to_arith().");
1247 case nir_op_usub_borrow
:
1248 unreachable("Should have been lowered by borrow_to_arith().");
1252 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1253 * appears that our hardware just does the right thing for signed
1256 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1257 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1261 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1262 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1264 /* Math instructions don't support conditional mod */
1265 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1266 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1268 /* Now, we need to determine if signs of the sources are different.
1269 * When we XOR the sources, the top bit is 0 if they are the same and 1
1270 * if they are different. We can then use a conditional modifier to
1271 * turn that into a predicate. This leads us to an XOR.l instruction.
1273 * Technically, according to the PRM, you're not allowed to use .l on a
1274 * XOR instruction. However, emperical experiments and Curro's reading
1275 * of the simulator source both indicate that it's safe.
1277 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1278 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1279 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1280 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1282 /* If the result of the initial remainder operation is non-zero and the
1283 * two sources have different signs, add in a copy of op[1] to get the
1284 * final integer modulus value.
1286 inst
= bld
.ADD(result
, result
, op
[1]);
1287 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1294 case nir_op_fne32
: {
1295 fs_reg dest
= result
;
1297 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1299 dest
= bld
.vgrf(op
[0].type
, 1);
1301 brw_conditional_mod cond
;
1302 switch (instr
->op
) {
1304 cond
= BRW_CONDITIONAL_L
;
1307 cond
= BRW_CONDITIONAL_GE
;
1310 cond
= BRW_CONDITIONAL_Z
;
1313 cond
= BRW_CONDITIONAL_NZ
;
1316 unreachable("bad opcode");
1319 bld
.CMP(dest
, op
[0], op
[1], cond
);
1321 if (bit_size
> 32) {
1322 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1323 } else if(bit_size
< 32) {
1324 /* When we convert the result to 32-bit we need to be careful and do
1325 * it as a signed conversion to get sign extension (for 32-bit true)
1327 const brw_reg_type src_type
=
1328 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1330 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1340 case nir_op_ine32
: {
1341 fs_reg dest
= result
;
1343 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1345 dest
= bld
.vgrf(op
[0].type
, 1);
1347 brw_conditional_mod cond
;
1348 switch (instr
->op
) {
1351 cond
= BRW_CONDITIONAL_L
;
1355 cond
= BRW_CONDITIONAL_GE
;
1358 cond
= BRW_CONDITIONAL_Z
;
1361 cond
= BRW_CONDITIONAL_NZ
;
1364 unreachable("bad opcode");
1366 bld
.CMP(dest
, op
[0], op
[1], cond
);
1368 if (bit_size
> 32) {
1369 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1370 } else if (bit_size
< 32) {
1371 /* When we convert the result to 32-bit we need to be careful and do
1372 * it as a signed conversion to get sign extension (for 32-bit true)
1374 const brw_reg_type src_type
=
1375 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1377 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1383 if (devinfo
->gen
>= 8) {
1384 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1386 if (inot_src_instr
!= NULL
&&
1387 (inot_src_instr
->op
== nir_op_ior
||
1388 inot_src_instr
->op
== nir_op_ixor
||
1389 inot_src_instr
->op
== nir_op_iand
) &&
1390 !inot_src_instr
->src
[0].abs
&&
1391 !inot_src_instr
->src
[0].negate
&&
1392 !inot_src_instr
->src
[1].abs
&&
1393 !inot_src_instr
->src
[1].negate
) {
1394 /* The sources of the source logical instruction are now the
1395 * sources of the instruction that will be generated.
1397 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1398 resolve_inot_sources(bld
, inot_src_instr
, op
);
1400 /* Smash all of the sources and destination to be signed. This
1401 * doesn't matter for the operation of the instruction, but cmod
1402 * propagation fails on unsigned sources with negation (due to
1403 * fs_inst::can_do_cmod returning false).
1406 brw_type_for_nir_type(devinfo
,
1407 (nir_alu_type
)(nir_type_int
|
1408 nir_dest_bit_size(instr
->dest
.dest
)));
1410 brw_type_for_nir_type(devinfo
,
1411 (nir_alu_type
)(nir_type_int
|
1412 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1414 brw_type_for_nir_type(devinfo
,
1415 (nir_alu_type
)(nir_type_int
|
1416 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1418 /* For XOR, only invert one of the sources. Arbitrarily choose
1421 op
[0].negate
= !op
[0].negate
;
1422 if (inot_src_instr
->op
!= nir_op_ixor
)
1423 op
[1].negate
= !op
[1].negate
;
1425 switch (inot_src_instr
->op
) {
1427 bld
.AND(result
, op
[0], op
[1]);
1431 bld
.OR(result
, op
[0], op
[1]);
1435 bld
.XOR(result
, op
[0], op
[1]);
1439 unreachable("impossible opcode");
1442 op
[0] = resolve_source_modifiers(op
[0]);
1444 bld
.NOT(result
, op
[0]);
1447 if (devinfo
->gen
>= 8) {
1448 resolve_inot_sources(bld
, instr
, op
);
1450 bld
.XOR(result
, op
[0], op
[1]);
1453 if (devinfo
->gen
>= 8) {
1454 resolve_inot_sources(bld
, instr
, op
);
1456 bld
.OR(result
, op
[0], op
[1]);
1459 if (devinfo
->gen
>= 8) {
1460 resolve_inot_sources(bld
, instr
, op
);
1462 bld
.AND(result
, op
[0], op
[1]);
1468 case nir_op_b32all_fequal2
:
1469 case nir_op_b32all_iequal2
:
1470 case nir_op_b32all_fequal3
:
1471 case nir_op_b32all_iequal3
:
1472 case nir_op_b32all_fequal4
:
1473 case nir_op_b32all_iequal4
:
1474 case nir_op_b32any_fnequal2
:
1475 case nir_op_b32any_inequal2
:
1476 case nir_op_b32any_fnequal3
:
1477 case nir_op_b32any_inequal3
:
1478 case nir_op_b32any_fnequal4
:
1479 case nir_op_b32any_inequal4
:
1480 unreachable("Lowered by nir_lower_alu_reductions");
1482 case nir_op_fnoise1_1
:
1483 case nir_op_fnoise1_2
:
1484 case nir_op_fnoise1_3
:
1485 case nir_op_fnoise1_4
:
1486 case nir_op_fnoise2_1
:
1487 case nir_op_fnoise2_2
:
1488 case nir_op_fnoise2_3
:
1489 case nir_op_fnoise2_4
:
1490 case nir_op_fnoise3_1
:
1491 case nir_op_fnoise3_2
:
1492 case nir_op_fnoise3_3
:
1493 case nir_op_fnoise3_4
:
1494 case nir_op_fnoise4_1
:
1495 case nir_op_fnoise4_2
:
1496 case nir_op_fnoise4_3
:
1497 case nir_op_fnoise4_4
:
1498 unreachable("not reached: should be handled by lower_noise");
1501 unreachable("not reached: should be handled by ldexp_to_arith()");
1504 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1505 inst
->saturate
= instr
->dest
.saturate
;
1509 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1510 inst
->saturate
= instr
->dest
.saturate
;
1514 case nir_op_f2b32
: {
1515 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1516 if (bit_size
== 64) {
1517 /* two-argument instructions can't take 64-bit immediates */
1521 if (instr
->op
== nir_op_f2b32
) {
1522 zero
= vgrf(glsl_type::double_type
);
1523 tmp
= vgrf(glsl_type::double_type
);
1524 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1526 zero
= vgrf(glsl_type::int64_t_type
);
1527 tmp
= vgrf(glsl_type::int64_t_type
);
1528 bld
.MOV(zero
, brw_imm_q(0));
1531 /* A SIMD16 execution needs to be split in two instructions, so use
1532 * a vgrf instead of the flag register as dst so instruction splitting
1535 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1536 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1539 if (bit_size
== 32) {
1540 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1542 assert(bit_size
== 16);
1543 zero
= instr
->op
== nir_op_f2b32
?
1544 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1546 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1552 inst
= bld
.RNDZ(result
, op
[0]);
1553 inst
->saturate
= instr
->dest
.saturate
;
1556 case nir_op_fceil
: {
1557 op
[0].negate
= !op
[0].negate
;
1558 fs_reg temp
= vgrf(glsl_type::float_type
);
1559 bld
.RNDD(temp
, op
[0]);
1561 inst
= bld
.MOV(result
, temp
);
1562 inst
->saturate
= instr
->dest
.saturate
;
1566 inst
= bld
.RNDD(result
, op
[0]);
1567 inst
->saturate
= instr
->dest
.saturate
;
1570 inst
= bld
.FRC(result
, op
[0]);
1571 inst
->saturate
= instr
->dest
.saturate
;
1573 case nir_op_fround_even
:
1574 inst
= bld
.RNDE(result
, op
[0]);
1575 inst
->saturate
= instr
->dest
.saturate
;
1578 case nir_op_fquantize2f16
: {
1579 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1580 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1581 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1583 /* The destination stride must be at least as big as the source stride. */
1584 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1587 /* Check for denormal */
1588 fs_reg abs_src0
= op
[0];
1589 abs_src0
.abs
= true;
1590 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1592 /* Get the appropriately signed zero */
1593 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1594 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1595 brw_imm_ud(0x80000000));
1596 /* Do the actual F32 -> F16 -> F32 conversion */
1597 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1598 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1599 /* Select that or zero based on normal status */
1600 inst
= bld
.SEL(result
, zero
, tmp32
);
1601 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1602 inst
->saturate
= instr
->dest
.saturate
;
1609 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1610 inst
->saturate
= instr
->dest
.saturate
;
1616 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1617 inst
->saturate
= instr
->dest
.saturate
;
1620 case nir_op_pack_snorm_2x16
:
1621 case nir_op_pack_snorm_4x8
:
1622 case nir_op_pack_unorm_2x16
:
1623 case nir_op_pack_unorm_4x8
:
1624 case nir_op_unpack_snorm_2x16
:
1625 case nir_op_unpack_snorm_4x8
:
1626 case nir_op_unpack_unorm_2x16
:
1627 case nir_op_unpack_unorm_4x8
:
1628 case nir_op_unpack_half_2x16
:
1629 case nir_op_pack_half_2x16
:
1630 unreachable("not reached: should be handled by lower_packing_builtins");
1632 case nir_op_unpack_half_2x16_split_x
:
1633 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1634 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1635 inst
->saturate
= instr
->dest
.saturate
;
1637 case nir_op_unpack_half_2x16_split_y
:
1638 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1639 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1640 inst
->saturate
= instr
->dest
.saturate
;
1643 case nir_op_pack_64_2x32_split
:
1644 case nir_op_pack_32_2x16_split
:
1645 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1648 case nir_op_unpack_64_2x32_split_x
:
1649 case nir_op_unpack_64_2x32_split_y
: {
1650 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1651 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1653 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1657 case nir_op_unpack_32_2x16_split_x
:
1658 case nir_op_unpack_32_2x16_split_y
: {
1659 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1660 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1662 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1667 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1668 inst
->saturate
= instr
->dest
.saturate
;
1671 case nir_op_bitfield_reverse
:
1672 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1673 bld
.BFREV(result
, op
[0]);
1676 case nir_op_bit_count
:
1677 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1678 bld
.CBIT(result
, op
[0]);
1681 case nir_op_ufind_msb
: {
1682 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1683 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1687 case nir_op_ifind_msb
: {
1688 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1690 if (devinfo
->gen
< 7) {
1691 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1693 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1695 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1696 * count from the LSB side. If FBH didn't return an error
1697 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1698 * count into an LSB count.
1700 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1702 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1703 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1704 inst
->src
[0].negate
= true;
1709 case nir_op_find_lsb
:
1710 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1712 if (devinfo
->gen
< 7) {
1713 fs_reg temp
= vgrf(glsl_type::int_type
);
1715 /* (x & -x) generates a value that consists of only the LSB of x.
1716 * For all powers of 2, findMSB(y) == findLSB(y).
1718 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1719 fs_reg negated_src
= src
;
1721 /* One must be negated, and the other must be non-negated. It
1722 * doesn't matter which is which.
1724 negated_src
.negate
= true;
1727 bld
.AND(temp
, src
, negated_src
);
1728 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1730 bld
.FBL(result
, op
[0]);
1734 case nir_op_ubitfield_extract
:
1735 case nir_op_ibitfield_extract
:
1736 unreachable("should have been lowered");
1739 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1740 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1743 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1744 bld
.BFI1(result
, op
[0], op
[1]);
1747 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1748 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1751 case nir_op_bitfield_insert
:
1752 unreachable("not reached: should have been lowered");
1755 bld
.SHL(result
, op
[0], op
[1]);
1758 bld
.ASR(result
, op
[0], op
[1]);
1761 bld
.SHR(result
, op
[0], op
[1]);
1764 case nir_op_pack_half_2x16_split
:
1765 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1769 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1770 inst
->saturate
= instr
->dest
.saturate
;
1774 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1775 inst
->saturate
= instr
->dest
.saturate
;
1778 case nir_op_b32csel
:
1779 if (optimize_frontfacing_ternary(instr
, result
))
1782 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1783 inst
= bld
.SEL(result
, op
[1], op
[2]);
1784 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1787 case nir_op_extract_u8
:
1788 case nir_op_extract_i8
: {
1789 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1794 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1795 * Use two instructions and a word or DWord intermediate integer type.
1797 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1798 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1800 if (instr
->op
== nir_op_extract_i8
) {
1801 /* If we need to sign extend, extract to a word first */
1802 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1803 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1804 bld
.MOV(result
, w_temp
);
1805 } else if (byte
& 1) {
1806 /* Extract the high byte from the word containing the desired byte
1810 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1813 /* Otherwise use an AND with 0xff and a word type */
1815 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1819 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1820 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1825 case nir_op_extract_u16
:
1826 case nir_op_extract_i16
: {
1827 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1828 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1829 bld
.MOV(result
, subscript(op
[0], type
, word
));
1834 unreachable("unhandled instruction");
1837 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1838 * to sign extend the low bit to 0/~0
1840 if (devinfo
->gen
<= 5 &&
1841 !result
.is_null() &&
1842 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1843 fs_reg masked
= vgrf(glsl_type::int_type
);
1844 bld
.AND(masked
, result
, brw_imm_d(1));
1845 masked
.negate
= true;
1846 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1851 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1852 nir_load_const_instr
*instr
)
1854 const brw_reg_type reg_type
=
1855 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1856 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1858 switch (instr
->def
.bit_size
) {
1860 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1861 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1865 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1866 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1870 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1871 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1875 assert(devinfo
->gen
>= 7);
1876 if (devinfo
->gen
== 7) {
1877 /* We don't get 64-bit integer types until gen8 */
1878 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1879 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1880 setup_imm_df(bld
, instr
->value
[i
].f64
));
1883 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1884 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1889 unreachable("Invalid bit size");
1892 nir_ssa_values
[instr
->def
.index
] = reg
;
1896 fs_visitor::get_nir_src(const nir_src
&src
)
1900 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1901 const brw_reg_type reg_type
=
1902 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1903 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1905 reg
= nir_ssa_values
[src
.ssa
->index
];
1908 /* We don't handle indirects on locals */
1909 assert(src
.reg
.indirect
== NULL
);
1910 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1911 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1914 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1915 /* The only 64-bit type available on gen7 is DF, so use that. */
1916 reg
.type
= BRW_REGISTER_TYPE_DF
;
1918 /* To avoid floating-point denorm flushing problems, set the type by
1919 * default to an integer type - instructions that need floating point
1920 * semantics will set this to F if they need to
1922 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1923 BRW_REGISTER_TYPE_D
);
1930 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1932 * This function should not be called on any value which may be 64 bits.
1933 * We could theoretically support 64-bit on gen8+ but we choose not to
1934 * because it wouldn't work in general (no gen7 support) and there are
1935 * enough restrictions in 64-bit immediates that you can't take the return
1936 * value and treat it the same as the result of get_nir_src().
1939 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1941 assert(nir_src_bit_size(src
) == 32);
1942 return nir_src_is_const(src
) ?
1943 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1947 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1950 const brw_reg_type reg_type
=
1951 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1952 dest
.ssa
.bit_size
== 8 ?
1953 BRW_REGISTER_TYPE_D
:
1954 BRW_REGISTER_TYPE_F
);
1955 nir_ssa_values
[dest
.ssa
.index
] =
1956 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1957 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
1958 return nir_ssa_values
[dest
.ssa
.index
];
1960 /* We don't handle indirects on locals */
1961 assert(dest
.reg
.indirect
== NULL
);
1962 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1963 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1968 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1971 for (unsigned i
= 0; i
< 4; i
++) {
1972 if (!((wr_mask
>> i
) & 1))
1975 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1976 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1977 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1978 if (new_inst
->src
[j
].file
== VGRF
)
1979 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1986 emit_pixel_interpolater_send(const fs_builder
&bld
,
1991 glsl_interp_mode interpolation
)
1993 struct brw_wm_prog_data
*wm_prog_data
=
1994 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1996 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1997 /* 2 floats per slot returned */
1998 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1999 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2001 wm_prog_data
->pulls_bary
= true;
2007 * Computes 1 << x, given a D/UD register containing some value x.
2010 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2012 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2014 fs_reg result
= bld
.vgrf(x
.type
, 1);
2015 fs_reg one
= bld
.vgrf(x
.type
, 1);
2017 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2018 bld
.SHL(result
, one
, x
);
2023 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2025 assert(stage
== MESA_SHADER_GEOMETRY
);
2027 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2029 if (gs_compile
->control_data_header_size_bits
== 0)
2032 /* We can only do EndPrimitive() functionality when the control data
2033 * consists of cut bits. Fortunately, the only time it isn't is when the
2034 * output type is points, in which case EndPrimitive() is a no-op.
2036 if (gs_prog_data
->control_data_format
!=
2037 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2041 /* Cut bits use one bit per vertex. */
2042 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2044 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2045 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2047 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2048 * vertex n, 0 otherwise. So all we need to do here is mark bit
2049 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2050 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2051 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2053 * Note that if EndPrimitive() is called before emitting any vertices, this
2054 * will cause us to set bit 31 of the control_data_bits register to 1.
2055 * That's fine because:
2057 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2058 * output, so the hardware will ignore cut bit 31.
2060 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2061 * last vertex, so setting cut bit 31 has no effect (since the primitive
2062 * is automatically ended when the GS terminates).
2064 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2065 * control_data_bits register to 0 when the first vertex is emitted.
2068 const fs_builder abld
= bld
.annotate("end primitive");
2070 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2071 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2072 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2073 fs_reg mask
= intexp2(abld
, prev_count
);
2074 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2075 * attention to the lower 5 bits of its second source argument, so on this
2076 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2077 * ((vertex_count - 1) % 32).
2079 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2083 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2085 assert(stage
== MESA_SHADER_GEOMETRY
);
2086 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2088 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2090 const fs_builder abld
= bld
.annotate("emit control data bits");
2091 const fs_builder fwa_bld
= bld
.exec_all();
2093 /* We use a single UD register to accumulate control data bits (32 bits
2094 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2097 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2098 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2099 * use the Channel Mask phase to enable/disable which DWord within that
2100 * group to write. (Remember, different SIMD8 channels may have emitted
2101 * different numbers of vertices, so we may need per-slot offsets.)
2103 * Channel masking presents an annoying problem: we may have to replicate
2104 * the data up to 4 times:
2106 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2108 * To avoid penalizing shaders that emit a small number of vertices, we
2109 * can avoid these sometimes: if the size of the control data header is
2110 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2111 * land in the same 128-bit group, so we can skip per-slot offsets.
2113 * Similarly, if the control data header is <= 32 bits, there is only one
2114 * DWord, so we can skip channel masks.
2116 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2118 fs_reg channel_mask
, per_slot_offset
;
2120 if (gs_compile
->control_data_header_size_bits
> 32) {
2121 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2122 channel_mask
= vgrf(glsl_type::uint_type
);
2125 if (gs_compile
->control_data_header_size_bits
> 128) {
2126 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2127 per_slot_offset
= vgrf(glsl_type::uint_type
);
2130 /* Figure out which DWord we're trying to write to using the formula:
2132 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2134 * Since bits_per_vertex is a power of two, and is known at compile
2135 * time, this can be optimized to:
2137 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2139 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2140 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2141 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2142 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2143 unsigned log2_bits_per_vertex
=
2144 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2145 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2147 if (per_slot_offset
.file
!= BAD_FILE
) {
2148 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2149 * the appropriate OWord within the control data header.
2151 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2154 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2155 * write to the appropriate DWORD within the OWORD.
2157 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2158 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2159 channel_mask
= intexp2(fwa_bld
, channel
);
2160 /* Then the channel masks need to be in bits 23:16. */
2161 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2164 /* Store the control data bits in the message payload and send it. */
2166 if (channel_mask
.file
!= BAD_FILE
)
2167 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2168 if (per_slot_offset
.file
!= BAD_FILE
)
2171 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2172 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2174 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2175 if (per_slot_offset
.file
!= BAD_FILE
)
2176 sources
[i
++] = per_slot_offset
;
2177 if (channel_mask
.file
!= BAD_FILE
)
2178 sources
[i
++] = channel_mask
;
2180 sources
[i
++] = this->control_data_bits
;
2183 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2184 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2186 /* We need to increment Global Offset by 256-bits to make room for
2187 * Broadwell's extra "Vertex Count" payload at the beginning of the
2188 * URB entry. Since this is an OWord message, Global Offset is counted
2189 * in 128-bit units, so we must set it to 2.
2191 if (gs_prog_data
->static_vertex_count
== -1)
2196 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2199 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2201 /* Note: we are calling this *before* increasing vertex_count, so
2202 * this->vertex_count == vertex_count - 1 in the formula above.
2205 /* Stream mode uses 2 bits per vertex */
2206 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2208 /* Must be a valid stream */
2209 assert(stream_id
< MAX_VERTEX_STREAMS
);
2211 /* Control data bits are initialized to 0 so we don't have to set any
2212 * bits when sending vertices to stream 0.
2217 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2219 /* reg::sid = stream_id */
2220 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2221 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2223 /* reg:shift_count = 2 * (vertex_count - 1) */
2224 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2225 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2227 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2228 * attention to the lower 5 bits of its second source argument, so on this
2229 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2230 * stream_id << ((2 * (vertex_count - 1)) % 32).
2232 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2233 abld
.SHL(mask
, sid
, shift_count
);
2234 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2238 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2241 assert(stage
== MESA_SHADER_GEOMETRY
);
2243 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2245 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2246 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2248 /* Haswell and later hardware ignores the "Render Stream Select" bits
2249 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2250 * and instead sends all primitives down the pipeline for rasterization.
2251 * If the SOL stage is enabled, "Render Stream Select" is honored and
2252 * primitives bound to non-zero streams are discarded after stream output.
2254 * Since the only purpose of primives sent to non-zero streams is to
2255 * be recorded by transform feedback, we can simply discard all geometry
2256 * bound to these streams when transform feedback is disabled.
2258 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2261 /* If we're outputting 32 control data bits or less, then we can wait
2262 * until the shader is over to output them all. Otherwise we need to
2263 * output them as we go. Now is the time to do it, since we're about to
2264 * output the vertex_count'th vertex, so it's guaranteed that the
2265 * control data bits associated with the (vertex_count - 1)th vertex are
2268 if (gs_compile
->control_data_header_size_bits
> 32) {
2269 const fs_builder abld
=
2270 bld
.annotate("emit vertex: emit control data bits");
2272 /* Only emit control data bits if we've finished accumulating a batch
2273 * of 32 bits. This is the case when:
2275 * (vertex_count * bits_per_vertex) % 32 == 0
2277 * (in other words, when the last 5 bits of vertex_count *
2278 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2279 * integer n (which is always the case, since bits_per_vertex is
2280 * always 1 or 2), this is equivalent to requiring that the last 5-n
2281 * bits of vertex_count are 0:
2283 * vertex_count & (2^(5-n) - 1) == 0
2285 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2288 * vertex_count & (32 / bits_per_vertex - 1) == 0
2290 * TODO: If vertex_count is an immediate, we could do some of this math
2291 * at compile time...
2294 abld
.AND(bld
.null_reg_d(), vertex_count
,
2295 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2296 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2298 abld
.IF(BRW_PREDICATE_NORMAL
);
2299 /* If vertex_count is 0, then no control data bits have been
2300 * accumulated yet, so we can skip emitting them.
2302 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2303 BRW_CONDITIONAL_NEQ
);
2304 abld
.IF(BRW_PREDICATE_NORMAL
);
2305 emit_gs_control_data_bits(vertex_count
);
2306 abld
.emit(BRW_OPCODE_ENDIF
);
2308 /* Reset control_data_bits to 0 so we can start accumulating a new
2311 * Note: in the case where vertex_count == 0, this neutralizes the
2312 * effect of any call to EndPrimitive() that the shader may have
2313 * made before outputting its first vertex.
2315 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2316 inst
->force_writemask_all
= true;
2317 abld
.emit(BRW_OPCODE_ENDIF
);
2320 emit_urb_writes(vertex_count
);
2322 /* In stream mode we have to set control data bits for all vertices
2323 * unless we have disabled control data bits completely (which we do
2324 * do for GL_POINTS outputs that don't use streams).
2326 if (gs_compile
->control_data_header_size_bits
> 0 &&
2327 gs_prog_data
->control_data_format
==
2328 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2329 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2334 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2335 const nir_src
&vertex_src
,
2336 unsigned base_offset
,
2337 const nir_src
&offset_src
,
2338 unsigned num_components
,
2339 unsigned first_component
)
2341 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2342 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2344 /* TODO: figure out push input layout for invocations == 1 */
2345 /* TODO: make this work with 64-bit inputs */
2346 if (gs_prog_data
->invocations
== 1 &&
2347 type_sz(dst
.type
) <= 4 &&
2348 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2349 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2350 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2351 nir_src_as_uint(vertex_src
) * push_reg_count
;
2352 for (unsigned i
= 0; i
< num_components
; i
++) {
2353 bld
.MOV(offset(dst
, bld
, i
),
2354 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2359 /* Resort to the pull model. Ensure the VUE handles are provided. */
2360 assert(gs_prog_data
->base
.include_vue_handles
);
2362 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2363 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2365 if (gs_prog_data
->invocations
== 1) {
2366 if (nir_src_is_const(vertex_src
)) {
2367 /* The vertex index is constant; just select the proper URB handle. */
2369 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2370 BRW_REGISTER_TYPE_UD
);
2372 /* The vertex index is non-constant. We need to use indirect
2373 * addressing to fetch the proper URB handle.
2375 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2376 * indicating that channel <n> should read the handle from
2377 * DWord <n>. We convert that to bytes by multiplying by 4.
2379 * Next, we convert the vertex index to bytes by multiplying
2380 * by 32 (shifting by 5), and add the two together. This is
2381 * the final indirect byte offset.
2383 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2384 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2385 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2386 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2388 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2389 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2390 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2391 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2392 /* Convert vertex_index to bytes (multiply by 32) */
2393 bld
.SHL(vertex_offset_bytes
,
2394 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2396 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2398 /* Use first_icp_handle as the base offset. There is one register
2399 * of URB handles per vertex, so inform the register allocator that
2400 * we might read up to nir->info.gs.vertices_in registers.
2402 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2403 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2404 fs_reg(icp_offset_bytes
),
2405 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2408 assert(gs_prog_data
->invocations
> 1);
2410 if (nir_src_is_const(vertex_src
)) {
2411 unsigned vertex
= nir_src_as_uint(vertex_src
);
2412 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2414 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2415 BRW_REGISTER_TYPE_UD
));
2417 /* The vertex index is non-constant. We need to use indirect
2418 * addressing to fetch the proper URB handle.
2421 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2423 /* Convert vertex_index to bytes (multiply by 4) */
2424 bld
.SHL(icp_offset_bytes
,
2425 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2428 /* Use first_icp_handle as the base offset. There is one DWord
2429 * of URB handles per vertex, so inform the register allocator that
2430 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2432 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2433 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2434 fs_reg(icp_offset_bytes
),
2435 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2442 fs_reg tmp_dst
= dst
;
2443 fs_reg indirect_offset
= get_nir_src(offset_src
);
2444 unsigned num_iterations
= 1;
2445 unsigned orig_num_components
= num_components
;
2447 if (type_sz(dst
.type
) == 8) {
2448 if (num_components
> 2) {
2452 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2454 first_component
= first_component
/ 2;
2457 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2458 if (nir_src_is_const(offset_src
)) {
2459 /* Constant indexing - use global offset. */
2460 if (first_component
!= 0) {
2461 unsigned read_components
= num_components
+ first_component
;
2462 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2463 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2464 inst
->size_written
= read_components
*
2465 tmp
.component_size(inst
->exec_size
);
2466 for (unsigned i
= 0; i
< num_components
; i
++) {
2467 bld
.MOV(offset(tmp_dst
, bld
, i
),
2468 offset(tmp
, bld
, i
+ first_component
));
2471 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2473 inst
->size_written
= num_components
*
2474 tmp_dst
.component_size(inst
->exec_size
);
2476 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2479 /* Indirect indexing - use per-slot offsets as well. */
2480 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2481 unsigned read_components
= num_components
+ first_component
;
2482 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2483 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2484 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2485 if (first_component
!= 0) {
2486 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2488 inst
->size_written
= read_components
*
2489 tmp
.component_size(inst
->exec_size
);
2490 for (unsigned i
= 0; i
< num_components
; i
++) {
2491 bld
.MOV(offset(tmp_dst
, bld
, i
),
2492 offset(tmp
, bld
, i
+ first_component
));
2495 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2497 inst
->size_written
= num_components
*
2498 tmp_dst
.component_size(inst
->exec_size
);
2500 inst
->offset
= base_offset
;
2504 if (type_sz(dst
.type
) == 8) {
2505 shuffle_from_32bit_read(bld
,
2506 offset(dst
, bld
, iter
* 2),
2507 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2512 if (num_iterations
> 1) {
2513 num_components
= orig_num_components
- 2;
2514 if(nir_src_is_const(offset_src
)) {
2517 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2518 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2519 indirect_offset
= new_indirect
;
2526 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2528 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2530 if (nir_src_is_const(*offset_src
)) {
2531 /* The only constant offset we should find is 0. brw_nir.c's
2532 * add_const_offset_to_base() will fold other constant offsets
2533 * into instr->const_index[0].
2535 assert(nir_src_as_uint(*offset_src
) == 0);
2539 return get_nir_src(*offset_src
);
2543 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2544 nir_intrinsic_instr
*instr
)
2546 assert(stage
== MESA_SHADER_VERTEX
);
2549 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2550 dest
= get_nir_dest(instr
->dest
);
2552 switch (instr
->intrinsic
) {
2553 case nir_intrinsic_load_vertex_id
:
2554 case nir_intrinsic_load_base_vertex
:
2555 unreachable("should be lowered by nir_lower_system_values()");
2557 case nir_intrinsic_load_input
: {
2558 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2559 unsigned first_component
= nir_intrinsic_component(instr
);
2560 unsigned num_components
= instr
->num_components
;
2562 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2564 if (type_sz(dest
.type
) == 8)
2565 first_component
/= 2;
2567 /* For 16-bit support maybe a temporary will be needed to copy from
2570 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2571 first_component
, num_components
);
2575 case nir_intrinsic_load_vertex_id_zero_base
:
2576 case nir_intrinsic_load_instance_id
:
2577 case nir_intrinsic_load_base_instance
:
2578 case nir_intrinsic_load_draw_id
:
2579 case nir_intrinsic_load_first_vertex
:
2580 case nir_intrinsic_load_is_indexed_draw
:
2581 unreachable("lowered by brw_nir_lower_vs_inputs");
2584 nir_emit_intrinsic(bld
, instr
);
2590 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2591 nir_intrinsic_instr
*instr
)
2593 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2594 const nir_src
&vertex_src
= instr
->src
[0];
2595 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2598 if (nir_src_is_const(vertex_src
)) {
2599 /* Emit a MOV to resolve <0,1,0> regioning. */
2600 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2601 unsigned vertex
= nir_src_as_uint(vertex_src
);
2603 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2604 BRW_REGISTER_TYPE_UD
));
2605 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2606 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2607 /* For the common case of only 1 instance, an array index of
2608 * gl_InvocationID means reading g1. Skip all the indirect work.
2610 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2612 /* The vertex index is non-constant. We need to use indirect
2613 * addressing to fetch the proper URB handle.
2615 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2617 /* Each ICP handle is a single DWord (4 bytes) */
2618 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2619 bld
.SHL(vertex_offset_bytes
,
2620 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2623 /* Start at g1. We might read up to 4 registers. */
2624 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2625 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2626 brw_imm_ud(4 * REG_SIZE
));
2633 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2634 nir_intrinsic_instr
*instr
)
2636 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2637 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2638 const nir_src
&vertex_src
= instr
->src
[0];
2640 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2642 if (nir_src_is_const(vertex_src
)) {
2643 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2644 nir_src_as_uint(vertex_src
), 0),
2645 BRW_REGISTER_TYPE_UD
));
2648 /* The vertex index is non-constant. We need to use indirect
2649 * addressing to fetch the proper URB handle.
2651 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2652 * indicating that channel <n> should read the handle from
2653 * DWord <n>. We convert that to bytes by multiplying by 4.
2655 * Next, we convert the vertex index to bytes by multiplying
2656 * by 32 (shifting by 5), and add the two together. This is
2657 * the final indirect byte offset.
2659 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2660 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2661 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2662 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2663 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2665 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2666 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2667 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2668 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2669 /* Convert vertex_index to bytes (multiply by 32) */
2670 bld
.SHL(vertex_offset_bytes
,
2671 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2673 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2675 /* Use first_icp_handle as the base offset. There is one register
2676 * of URB handles per vertex, so inform the register allocator that
2677 * we might read up to nir->info.gs.vertices_in registers.
2679 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2680 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2681 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2687 fs_visitor::get_tcs_output_urb_handle()
2689 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2691 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2692 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2694 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2695 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2700 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2701 nir_intrinsic_instr
*instr
)
2703 assert(stage
== MESA_SHADER_TESS_CTRL
);
2704 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2705 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2706 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2709 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2712 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2713 dst
= get_nir_dest(instr
->dest
);
2715 switch (instr
->intrinsic
) {
2716 case nir_intrinsic_load_primitive_id
:
2717 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2718 : brw_vec1_grf(0, 1)));
2720 case nir_intrinsic_load_invocation_id
:
2721 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2723 case nir_intrinsic_load_patch_vertices_in
:
2724 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2725 brw_imm_d(tcs_key
->input_vertices
));
2728 case nir_intrinsic_barrier
: {
2729 if (tcs_prog_data
->instances
== 1)
2732 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2733 fs_reg m0_2
= component(m0
, 2);
2735 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2737 /* Zero the message header */
2738 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2740 if (devinfo
->gen
< 11) {
2741 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2742 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2743 brw_imm_ud(INTEL_MASK(16, 13)));
2745 /* Shift it up to bits 27:24. */
2746 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2748 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2749 brw_imm_ud(INTEL_MASK(30, 24)));
2752 /* Set the Barrier Count and the enable bit */
2753 if (devinfo
->gen
< 11) {
2754 chanbld
.OR(m0_2
, m0_2
,
2755 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2757 chanbld
.OR(m0_2
, m0_2
,
2758 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2761 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2765 case nir_intrinsic_load_input
:
2766 unreachable("nir_lower_io should never give us these.");
2769 case nir_intrinsic_load_per_vertex_input
: {
2770 fs_reg indirect_offset
= get_indirect_offset(instr
);
2771 unsigned imm_offset
= instr
->const_index
[0];
2775 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2776 : get_tcs_single_patch_icp_handle(bld
, instr
);
2778 /* We can only read two double components with each URB read, so
2779 * we send two read messages in that case, each one loading up to
2780 * two double components.
2782 unsigned num_iterations
= 1;
2783 unsigned num_components
= instr
->num_components
;
2784 unsigned first_component
= nir_intrinsic_component(instr
);
2785 fs_reg orig_dst
= dst
;
2786 if (type_sz(dst
.type
) == 8) {
2787 first_component
= first_component
/ 2;
2788 if (instr
->num_components
> 2) {
2793 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2797 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2798 if (indirect_offset
.file
== BAD_FILE
) {
2799 /* Constant indexing - use global offset. */
2800 if (first_component
!= 0) {
2801 unsigned read_components
= num_components
+ first_component
;
2802 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2803 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2804 for (unsigned i
= 0; i
< num_components
; i
++) {
2805 bld
.MOV(offset(dst
, bld
, i
),
2806 offset(tmp
, bld
, i
+ first_component
));
2809 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2811 inst
->offset
= imm_offset
;
2814 /* Indirect indexing - use per-slot offsets as well. */
2815 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2816 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2817 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2818 if (first_component
!= 0) {
2819 unsigned read_components
= num_components
+ first_component
;
2820 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2821 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2823 for (unsigned i
= 0; i
< num_components
; i
++) {
2824 bld
.MOV(offset(dst
, bld
, i
),
2825 offset(tmp
, bld
, i
+ first_component
));
2828 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2831 inst
->offset
= imm_offset
;
2834 inst
->size_written
= (num_components
+ first_component
) *
2835 inst
->dst
.component_size(inst
->exec_size
);
2837 /* If we are reading 64-bit data using 32-bit read messages we need
2838 * build proper 64-bit data elements by shuffling the low and high
2839 * 32-bit components around like we do for other things like UBOs
2842 if (type_sz(dst
.type
) == 8) {
2843 shuffle_from_32bit_read(bld
,
2844 offset(orig_dst
, bld
, iter
* 2),
2845 retype(dst
, BRW_REGISTER_TYPE_D
),
2849 /* Copy the temporary to the destination to deal with writemasking.
2851 * Also attempt to deal with gl_PointSize being in the .w component.
2853 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2854 assert(type_sz(dst
.type
) < 8);
2855 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2856 inst
->size_written
= 4 * REG_SIZE
;
2857 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2860 /* If we are loading double data and we need a second read message
2861 * adjust the write offset
2863 if (num_iterations
> 1) {
2864 num_components
= instr
->num_components
- 2;
2871 case nir_intrinsic_load_output
:
2872 case nir_intrinsic_load_per_vertex_output
: {
2873 fs_reg indirect_offset
= get_indirect_offset(instr
);
2874 unsigned imm_offset
= instr
->const_index
[0];
2875 unsigned first_component
= nir_intrinsic_component(instr
);
2877 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2880 if (indirect_offset
.file
== BAD_FILE
) {
2881 /* This MOV replicates the output handle to all enabled channels
2882 * is SINGLE_PATCH mode.
2884 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2885 bld
.MOV(patch_handle
, output_handles
);
2888 if (first_component
!= 0) {
2889 unsigned read_components
=
2890 instr
->num_components
+ first_component
;
2891 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2892 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2894 inst
->size_written
= read_components
* REG_SIZE
;
2895 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2896 bld
.MOV(offset(dst
, bld
, i
),
2897 offset(tmp
, bld
, i
+ first_component
));
2900 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2902 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2904 inst
->offset
= imm_offset
;
2908 /* Indirect indexing - use per-slot offsets as well. */
2909 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2910 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2911 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2912 if (first_component
!= 0) {
2913 unsigned read_components
=
2914 instr
->num_components
+ first_component
;
2915 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2916 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2918 inst
->size_written
= read_components
* REG_SIZE
;
2919 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2920 bld
.MOV(offset(dst
, bld
, i
),
2921 offset(tmp
, bld
, i
+ first_component
));
2924 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2926 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2928 inst
->offset
= imm_offset
;
2934 case nir_intrinsic_store_output
:
2935 case nir_intrinsic_store_per_vertex_output
: {
2936 fs_reg value
= get_nir_src(instr
->src
[0]);
2937 bool is_64bit
= (instr
->src
[0].is_ssa
?
2938 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2939 fs_reg indirect_offset
= get_indirect_offset(instr
);
2940 unsigned imm_offset
= instr
->const_index
[0];
2941 unsigned mask
= instr
->const_index
[1];
2942 unsigned header_regs
= 0;
2943 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2946 srcs
[header_regs
++] = output_handles
;
2948 if (indirect_offset
.file
!= BAD_FILE
) {
2949 srcs
[header_regs
++] = indirect_offset
;
2955 unsigned num_components
= util_last_bit(mask
);
2958 /* We can only pack two 64-bit components in a single message, so send
2959 * 2 messages if we have more components
2961 unsigned num_iterations
= 1;
2962 unsigned iter_components
= num_components
;
2963 unsigned first_component
= nir_intrinsic_component(instr
);
2965 first_component
= first_component
/ 2;
2966 if (instr
->num_components
> 2) {
2968 iter_components
= 2;
2972 mask
= mask
<< first_component
;
2974 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2975 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2976 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2977 opcode
= indirect_offset
.file
!= BAD_FILE
?
2978 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2979 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2980 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2981 /* Expand the 64-bit mask to 32-bit channels. We only handle
2982 * two channels in each iteration, so we only care about X/Y.
2984 unsigned mask32
= 0;
2985 if (mask
& WRITEMASK_X
)
2986 mask32
|= WRITEMASK_XY
;
2987 if (mask
& WRITEMASK_Y
)
2988 mask32
|= WRITEMASK_ZW
;
2990 /* If the mask does not include any of the channels X or Y there
2991 * is nothing to do in this iteration. Move on to the next couple
2992 * of 64-bit channels.
3000 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
3001 opcode
= indirect_offset
.file
!= BAD_FILE
?
3002 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
3003 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
3005 opcode
= indirect_offset
.file
!= BAD_FILE
?
3006 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
3007 SHADER_OPCODE_URB_WRITE_SIMD8
;
3010 for (unsigned i
= 0; i
< iter_components
; i
++) {
3011 if (!(mask
& (1 << (i
+ first_component
))))
3015 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
3017 /* We need to shuffle the 64-bit data to match the layout
3018 * expected by our 32-bit URB write messages. We use a temporary
3021 unsigned channel
= iter
* 2 + i
;
3022 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
3024 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
3025 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
3026 offset(dest
, bld
, 1);
3031 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
3032 (is_64bit
? 2 * first_component
: first_component
);
3034 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
3035 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
3037 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
3038 inst
->offset
= imm_offset
;
3041 /* If this is a 64-bit attribute, select the next two 64-bit channels
3042 * to be handled in the next iteration.
3053 nir_emit_intrinsic(bld
, instr
);
3059 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
3060 nir_intrinsic_instr
*instr
)
3062 assert(stage
== MESA_SHADER_TESS_EVAL
);
3063 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3066 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3067 dest
= get_nir_dest(instr
->dest
);
3069 switch (instr
->intrinsic
) {
3070 case nir_intrinsic_load_primitive_id
:
3071 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3073 case nir_intrinsic_load_tess_coord
:
3074 /* gl_TessCoord is part of the payload in g1-3 */
3075 for (unsigned i
= 0; i
< 3; i
++) {
3076 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3080 case nir_intrinsic_load_input
:
3081 case nir_intrinsic_load_per_vertex_input
: {
3082 fs_reg indirect_offset
= get_indirect_offset(instr
);
3083 unsigned imm_offset
= instr
->const_index
[0];
3084 unsigned first_component
= nir_intrinsic_component(instr
);
3086 if (type_sz(dest
.type
) == 8) {
3087 first_component
= first_component
/ 2;
3091 if (indirect_offset
.file
== BAD_FILE
) {
3092 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3093 * which is 16 registers (since each holds 2 vec4 slots).
3095 unsigned slot_count
= 1;
3096 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
3099 const unsigned max_push_slots
= 32;
3100 if (imm_offset
+ slot_count
<= max_push_slots
) {
3101 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3102 for (int i
= 0; i
< instr
->num_components
; i
++) {
3103 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
3104 i
+ first_component
;
3105 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3108 tes_prog_data
->base
.urb_read_length
=
3109 MAX2(tes_prog_data
->base
.urb_read_length
,
3110 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
3112 /* Replicate the patch handle to all enabled channels */
3113 const fs_reg srcs
[] = {
3114 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3116 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3117 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3119 if (first_component
!= 0) {
3120 unsigned read_components
=
3121 instr
->num_components
+ first_component
;
3122 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3123 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3125 inst
->size_written
= read_components
* REG_SIZE
;
3126 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3127 bld
.MOV(offset(dest
, bld
, i
),
3128 offset(tmp
, bld
, i
+ first_component
));
3131 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3133 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3136 inst
->offset
= imm_offset
;
3139 /* Indirect indexing - use per-slot offsets as well. */
3141 /* We can only read two double components with each URB read, so
3142 * we send two read messages in that case, each one loading up to
3143 * two double components.
3145 unsigned num_iterations
= 1;
3146 unsigned num_components
= instr
->num_components
;
3147 fs_reg orig_dest
= dest
;
3148 if (type_sz(dest
.type
) == 8) {
3149 if (instr
->num_components
> 2) {
3153 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3157 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3158 const fs_reg srcs
[] = {
3159 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3162 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3163 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3165 if (first_component
!= 0) {
3166 unsigned read_components
=
3167 num_components
+ first_component
;
3168 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3169 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3171 for (unsigned i
= 0; i
< num_components
; i
++) {
3172 bld
.MOV(offset(dest
, bld
, i
),
3173 offset(tmp
, bld
, i
+ first_component
));
3176 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3180 inst
->offset
= imm_offset
;
3181 inst
->size_written
= (num_components
+ first_component
) *
3182 inst
->dst
.component_size(inst
->exec_size
);
3184 /* If we are reading 64-bit data using 32-bit read messages we need
3185 * build proper 64-bit data elements by shuffling the low and high
3186 * 32-bit components around like we do for other things like UBOs
3189 if (type_sz(dest
.type
) == 8) {
3190 shuffle_from_32bit_read(bld
,
3191 offset(orig_dest
, bld
, iter
* 2),
3192 retype(dest
, BRW_REGISTER_TYPE_D
),
3196 /* If we are loading double data and we need a second read message
3199 if (num_iterations
> 1) {
3200 num_components
= instr
->num_components
- 2;
3208 nir_emit_intrinsic(bld
, instr
);
3214 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3215 nir_intrinsic_instr
*instr
)
3217 assert(stage
== MESA_SHADER_GEOMETRY
);
3218 fs_reg indirect_offset
;
3221 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3222 dest
= get_nir_dest(instr
->dest
);
3224 switch (instr
->intrinsic
) {
3225 case nir_intrinsic_load_primitive_id
:
3226 assert(stage
== MESA_SHADER_GEOMETRY
);
3227 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3228 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3229 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3232 case nir_intrinsic_load_input
:
3233 unreachable("load_input intrinsics are invalid for the GS stage");
3235 case nir_intrinsic_load_per_vertex_input
:
3236 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3237 instr
->src
[1], instr
->num_components
,
3238 nir_intrinsic_component(instr
));
3241 case nir_intrinsic_emit_vertex_with_counter
:
3242 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3245 case nir_intrinsic_end_primitive_with_counter
:
3246 emit_gs_end_primitive(instr
->src
[0]);
3249 case nir_intrinsic_set_vertex_count
:
3250 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3253 case nir_intrinsic_load_invocation_id
: {
3254 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3255 assert(val
.file
!= BAD_FILE
);
3256 dest
.type
= val
.type
;
3262 nir_emit_intrinsic(bld
, instr
);
3268 * Fetch the current render target layer index.
3271 fetch_render_target_array_index(const fs_builder
&bld
)
3273 if (bld
.shader
->devinfo
->gen
>= 6) {
3274 /* The render target array index is provided in the thread payload as
3275 * bits 26:16 of r0.0.
3277 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3278 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3282 /* Pre-SNB we only ever render into the first layer of the framebuffer
3283 * since layered rendering is not implemented.
3285 return brw_imm_ud(0);
3290 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3291 * framebuffer at the current fragment coordinates and sample index.
3294 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3297 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3299 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3300 const brw_wm_prog_key
*wm_key
=
3301 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3302 assert(!wm_key
->coherent_fb_fetch
);
3303 const struct brw_wm_prog_data
*wm_prog_data
=
3304 brw_wm_prog_data(stage_prog_data
);
3306 /* Calculate the surface index relative to the start of the texture binding
3307 * table block, since that's what the texturing messages expect.
3309 const unsigned surface
= target
+
3310 wm_prog_data
->binding_table
.render_target_read_start
-
3311 wm_prog_data
->base
.binding_table
.texture_start
;
3313 /* Calculate the fragment coordinates. */
3314 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3315 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3316 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3317 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3319 /* Calculate the sample index and MCS payload when multisampling. Luckily
3320 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3321 * shouldn't be necessary to recompile based on whether the framebuffer is
3324 if (wm_key
->multisample_fbo
&&
3325 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3326 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3328 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3329 const fs_reg mcs
= wm_key
->multisample_fbo
?
3330 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3332 /* Use either a normal or a CMS texel fetch message depending on whether
3333 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3334 * message just in case the framebuffer uses 16x multisampling, it should
3335 * be equivalent to the normal CMS fetch for lower multisampling modes.
3337 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3338 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3339 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3341 /* Emit the instruction. */
3342 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3343 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3344 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3345 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3346 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3347 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3348 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3349 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3350 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3352 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3353 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3359 * Actual coherent framebuffer read implemented using the native render target
3360 * read message. Requires SKL+.
3363 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3365 assert(bld
.shader
->devinfo
->gen
>= 9);
3366 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3367 inst
->target
= target
;
3368 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3374 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3376 if (n
&& regs
[0].file
!= BAD_FILE
) {
3380 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3382 for (unsigned i
= 0; i
< n
; i
++)
3390 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3392 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3393 const brw_wm_prog_key
*const key
=
3394 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3395 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3396 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3398 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3399 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3401 else if (l
== FRAG_RESULT_COLOR
)
3402 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3403 MAX2(key
->nr_color_regions
, 1));
3405 else if (l
== FRAG_RESULT_DEPTH
)
3406 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3408 else if (l
== FRAG_RESULT_STENCIL
)
3409 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3411 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3412 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3414 else if (l
>= FRAG_RESULT_DATA0
&&
3415 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3416 return alloc_temporary(v
->bld
, 4,
3417 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3420 unreachable("Invalid location");
3424 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3425 nir_intrinsic_instr
*instr
)
3427 assert(stage
== MESA_SHADER_FRAGMENT
);
3430 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3431 dest
= get_nir_dest(instr
->dest
);
3433 switch (instr
->intrinsic
) {
3434 case nir_intrinsic_load_front_face
:
3435 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3436 *emit_frontfacing_interpolation());
3439 case nir_intrinsic_load_sample_pos
: {
3440 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3441 assert(sample_pos
.file
!= BAD_FILE
);
3442 dest
.type
= sample_pos
.type
;
3443 bld
.MOV(dest
, sample_pos
);
3444 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3448 case nir_intrinsic_load_layer_id
:
3449 dest
.type
= BRW_REGISTER_TYPE_UD
;
3450 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3453 case nir_intrinsic_load_helper_invocation
:
3454 case nir_intrinsic_load_sample_mask_in
:
3455 case nir_intrinsic_load_sample_id
: {
3456 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3457 fs_reg val
= nir_system_values
[sv
];
3458 assert(val
.file
!= BAD_FILE
);
3459 dest
.type
= val
.type
;
3464 case nir_intrinsic_store_output
: {
3465 const fs_reg src
= get_nir_src(instr
->src
[0]);
3466 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3467 const unsigned location
= nir_intrinsic_base(instr
) +
3468 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3469 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3472 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3473 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3474 offset(src
, bld
, j
));
3479 case nir_intrinsic_load_output
: {
3480 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3481 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3482 assert(l
>= FRAG_RESULT_DATA0
);
3483 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3484 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3485 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3487 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3488 emit_coherent_fb_read(bld
, tmp
, target
);
3490 emit_non_coherent_fb_read(bld
, tmp
, target
);
3492 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3493 bld
.MOV(offset(dest
, bld
, j
),
3494 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3500 case nir_intrinsic_discard
:
3501 case nir_intrinsic_discard_if
: {
3502 /* We track our discarded pixels in f0.1. By predicating on it, we can
3503 * update just the flag bits that aren't yet discarded. If there's no
3504 * condition, we emit a CMP of g0 != g0, so all currently executing
3505 * channels will get turned off.
3507 fs_inst
*cmp
= NULL
;
3508 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3509 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3512 alu
->op
!= nir_op_bcsel
&&
3513 alu
->op
!= nir_op_inot
) {
3514 /* Re-emit the instruction that generated the Boolean value, but
3515 * do not store it. Since this instruction will be conditional,
3516 * other instructions that want to use the real Boolean value may
3517 * get garbage. This was a problem for piglit's fs-discard-exit-2
3520 * Ideally we'd detect that the instruction cannot have a
3521 * conditional modifier before emitting the instructions. Alas,
3522 * that is nigh impossible. Instead, we're going to assume the
3523 * instruction (or last instruction) generated can have a
3524 * conditional modifier. If it cannot, fallback to the old-style
3525 * compare, and hope dead code elimination will clean up the
3526 * extra instructions generated.
3528 nir_emit_alu(bld
, alu
, false);
3530 cmp
= (fs_inst
*) instructions
.get_tail();
3531 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3532 if (cmp
->can_do_cmod())
3533 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3537 /* The old sequence that would have been generated is,
3538 * basically, bool_result == false. This is equivalent to
3539 * !bool_result, so negate the old modifier.
3541 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3546 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3547 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3550 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3551 BRW_REGISTER_TYPE_UW
));
3552 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3555 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3556 cmp
->flag_subreg
= 1;
3558 if (devinfo
->gen
>= 6) {
3559 emit_discard_jump();
3562 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3566 case nir_intrinsic_load_input
: {
3567 /* load_input is only used for flat inputs */
3568 unsigned base
= nir_intrinsic_base(instr
);
3569 unsigned comp
= nir_intrinsic_component(instr
);
3570 unsigned num_components
= instr
->num_components
;
3571 fs_reg orig_dest
= dest
;
3572 enum brw_reg_type type
= dest
.type
;
3574 /* Special case fields in the VUE header */
3575 if (base
== VARYING_SLOT_LAYER
)
3577 else if (base
== VARYING_SLOT_VIEWPORT
)
3580 if (nir_dest_bit_size(instr
->dest
) == 64) {
3581 /* const_index is in 32-bit type size units that could not be aligned
3582 * with DF. We need to read the double vector as if it was a float
3583 * vector of twice the number of components to fetch the right data.
3585 type
= BRW_REGISTER_TYPE_F
;
3586 num_components
*= 2;
3587 dest
= bld
.vgrf(type
, num_components
);
3590 for (unsigned int i
= 0; i
< num_components
; i
++) {
3591 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3592 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3595 if (nir_dest_bit_size(instr
->dest
) == 64) {
3596 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3597 instr
->num_components
);
3602 case nir_intrinsic_load_barycentric_pixel
:
3603 case nir_intrinsic_load_barycentric_centroid
:
3604 case nir_intrinsic_load_barycentric_sample
:
3605 /* Do nothing - load_interpolated_input handling will handle it later. */
3608 case nir_intrinsic_load_barycentric_at_sample
: {
3609 const glsl_interp_mode interpolation
=
3610 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3612 if (nir_src_is_const(instr
->src
[0])) {
3613 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3615 emit_pixel_interpolater_send(bld
,
3616 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3619 brw_imm_ud(msg_data
),
3622 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3623 BRW_REGISTER_TYPE_UD
);
3625 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3626 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3627 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3628 bld
.exec_all().group(1, 0)
3629 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3630 emit_pixel_interpolater_send(bld
,
3631 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3637 /* Make a loop that sends a message to the pixel interpolater
3638 * for the sample number in each live channel. If there are
3639 * multiple channels with the same sample number then these
3640 * will be handled simultaneously with a single interation of
3643 bld
.emit(BRW_OPCODE_DO
);
3645 /* Get the next live sample number into sample_id_reg */
3646 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3648 /* Set the flag register so that we can perform the send
3649 * message on all channels that have the same sample number
3651 bld
.CMP(bld
.null_reg_ud(),
3652 sample_src
, sample_id
,
3653 BRW_CONDITIONAL_EQ
);
3654 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3655 bld
.exec_all().group(1, 0)
3656 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3658 emit_pixel_interpolater_send(bld
,
3659 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3662 component(msg_data
, 0),
3664 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3666 /* Continue the loop if there are any live channels left */
3667 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3669 bld
.emit(BRW_OPCODE_WHILE
));
3675 case nir_intrinsic_load_barycentric_at_offset
: {
3676 const glsl_interp_mode interpolation
=
3677 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3679 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3682 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3683 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3684 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3686 emit_pixel_interpolater_send(bld
,
3687 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3690 brw_imm_ud(off_x
| (off_y
<< 4)),
3693 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3694 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3695 BRW_REGISTER_TYPE_F
);
3696 for (int i
= 0; i
< 2; i
++) {
3697 fs_reg temp
= vgrf(glsl_type::float_type
);
3698 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3699 fs_reg itemp
= vgrf(glsl_type::int_type
);
3701 bld
.MOV(itemp
, temp
);
3703 /* Clamp the upper end of the range to +7/16.
3704 * ARB_gpu_shader5 requires that we support a maximum offset
3705 * of +0.5, which isn't representable in a S0.4 value -- if
3706 * we didn't clamp it, we'd end up with -8/16, which is the
3707 * opposite of what the shader author wanted.
3709 * This is legal due to ARB_gpu_shader5's quantization
3712 * "Not all values of <offset> may be supported; x and y
3713 * offsets may be rounded to fixed-point values with the
3714 * number of fraction bits given by the
3715 * implementation-dependent constant
3716 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3718 set_condmod(BRW_CONDITIONAL_L
,
3719 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3722 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3723 emit_pixel_interpolater_send(bld
,
3733 case nir_intrinsic_load_interpolated_input
: {
3734 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3735 emit_fragcoord_interpolation(dest
);
3739 assert(instr
->src
[0].ssa
&&
3740 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3741 nir_intrinsic_instr
*bary_intrinsic
=
3742 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3743 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3744 enum glsl_interp_mode interp_mode
=
3745 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3748 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3749 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3750 /* Use the result of the PI message */
3751 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3753 /* Use the delta_xy values computed from the payload */
3754 enum brw_barycentric_mode bary
=
3755 brw_barycentric_mode(interp_mode
, bary_intrin
);
3757 dst_xy
= this->delta_xy
[bary
];
3760 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3762 interp_reg(nir_intrinsic_base(instr
),
3763 nir_intrinsic_component(instr
) + i
);
3764 interp
.type
= BRW_REGISTER_TYPE_F
;
3765 dest
.type
= BRW_REGISTER_TYPE_F
;
3767 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3768 fs_reg tmp
= vgrf(glsl_type::float_type
);
3769 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3770 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3772 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3779 nir_emit_intrinsic(bld
, instr
);
3785 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3787 if (nir_src_is_const(instr
->src
[src
])) {
3788 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3791 else if (add_val
== -1)
3799 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3800 nir_intrinsic_instr
*instr
)
3802 assert(stage
== MESA_SHADER_COMPUTE
);
3803 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3806 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3807 dest
= get_nir_dest(instr
->dest
);
3809 switch (instr
->intrinsic
) {
3810 case nir_intrinsic_barrier
:
3812 cs_prog_data
->uses_barrier
= true;
3815 case nir_intrinsic_load_subgroup_id
:
3816 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3819 case nir_intrinsic_load_local_invocation_id
:
3820 case nir_intrinsic_load_work_group_id
: {
3821 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3822 fs_reg val
= nir_system_values
[sv
];
3823 assert(val
.file
!= BAD_FILE
);
3824 dest
.type
= val
.type
;
3825 for (unsigned i
= 0; i
< 3; i
++)
3826 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3830 case nir_intrinsic_load_num_work_groups
: {
3831 const unsigned surface
=
3832 cs_prog_data
->binding_table
.work_groups_start
;
3834 cs_prog_data
->uses_num_work_groups
= true;
3836 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3837 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3838 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3839 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3841 /* Read the 3 GLuint components of gl_NumWorkGroups */
3842 for (unsigned i
= 0; i
< 3; i
++) {
3843 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3844 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3845 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3850 case nir_intrinsic_shared_atomic_add
:
3851 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3853 case nir_intrinsic_shared_atomic_imin
:
3854 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3856 case nir_intrinsic_shared_atomic_umin
:
3857 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3859 case nir_intrinsic_shared_atomic_imax
:
3860 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3862 case nir_intrinsic_shared_atomic_umax
:
3863 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3865 case nir_intrinsic_shared_atomic_and
:
3866 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3868 case nir_intrinsic_shared_atomic_or
:
3869 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3871 case nir_intrinsic_shared_atomic_xor
:
3872 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3874 case nir_intrinsic_shared_atomic_exchange
:
3875 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3877 case nir_intrinsic_shared_atomic_comp_swap
:
3878 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3880 case nir_intrinsic_shared_atomic_fmin
:
3881 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3883 case nir_intrinsic_shared_atomic_fmax
:
3884 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3886 case nir_intrinsic_shared_atomic_fcomp_swap
:
3887 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3890 case nir_intrinsic_load_shared
: {
3891 assert(devinfo
->gen
>= 7);
3892 assert(stage
== MESA_SHADER_COMPUTE
);
3894 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3895 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3896 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3897 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3898 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3900 /* Make dest unsigned because that's what the temporary will be */
3901 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3903 /* Read the vector */
3904 if (nir_intrinsic_align(instr
) >= 4) {
3905 assert(nir_dest_bit_size(instr
->dest
) == 32);
3906 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3908 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3909 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3910 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3912 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3913 assert(nir_dest_num_components(instr
->dest
) == 1);
3914 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3916 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3917 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3918 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3919 bld
.MOV(dest
, read_result
);
3924 case nir_intrinsic_store_shared
: {
3925 assert(devinfo
->gen
>= 7);
3926 assert(stage
== MESA_SHADER_COMPUTE
);
3928 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3929 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3930 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3931 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3932 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3934 fs_reg data
= get_nir_src(instr
->src
[0]);
3935 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3937 assert(nir_intrinsic_write_mask(instr
) ==
3938 (1u << instr
->num_components
) - 1);
3939 if (nir_intrinsic_align(instr
) >= 4) {
3940 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3941 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3942 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3943 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3944 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3945 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3947 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3948 assert(nir_src_num_components(instr
->src
[0]) == 1);
3949 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3951 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3952 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3954 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3955 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3961 nir_emit_intrinsic(bld
, instr
);
3967 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3968 nir_op op
, brw_reg_type type
)
3970 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3971 switch (type_sz(type
)) {
3973 assert(type
!= BRW_REGISTER_TYPE_HF
);
3974 return retype(brw_imm_uw(value
.u16
), type
);
3976 return retype(brw_imm_ud(value
.u32
), type
);
3978 if (type
== BRW_REGISTER_TYPE_DF
)
3979 return setup_imm_df(bld
, value
.f64
);
3981 return retype(brw_imm_u64(value
.u64
), type
);
3983 unreachable("Invalid type size");
3988 brw_op_for_nir_reduction_op(nir_op op
)
3991 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3992 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3993 case nir_op_imul
: return BRW_OPCODE_MUL
;
3994 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3995 case nir_op_imin
: return BRW_OPCODE_SEL
;
3996 case nir_op_umin
: return BRW_OPCODE_SEL
;
3997 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3998 case nir_op_imax
: return BRW_OPCODE_SEL
;
3999 case nir_op_umax
: return BRW_OPCODE_SEL
;
4000 case nir_op_fmax
: return BRW_OPCODE_SEL
;
4001 case nir_op_iand
: return BRW_OPCODE_AND
;
4002 case nir_op_ior
: return BRW_OPCODE_OR
;
4003 case nir_op_ixor
: return BRW_OPCODE_XOR
;
4005 unreachable("Invalid reduction operation");
4009 static brw_conditional_mod
4010 brw_cond_mod_for_nir_reduction_op(nir_op op
)
4013 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
4014 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
4015 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
4016 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
4017 case nir_op_imin
: return BRW_CONDITIONAL_L
;
4018 case nir_op_umin
: return BRW_CONDITIONAL_L
;
4019 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
4020 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
4021 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
4022 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
4023 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
4024 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
4025 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
4027 unreachable("Invalid reduction operation");
4032 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
4033 nir_intrinsic_instr
*instr
)
4035 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
4037 if (stage_prog_data
->binding_table
.image_start
> 0) {
4038 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
4039 image
.d
+= stage_prog_data
->binding_table
.image_start
;
4041 bld
.ADD(image
, image
,
4042 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
4046 return bld
.emit_uniformize(image
);
4050 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
4051 nir_intrinsic_instr
*instr
)
4053 /* SSBO stores are weird in that their index is in src[1] */
4054 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
4057 if (nir_src_is_const(instr
->src
[src
])) {
4058 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4059 nir_src_as_uint(instr
->src
[src
]);
4060 surf_index
= brw_imm_ud(index
);
4062 surf_index
= vgrf(glsl_type::uint_type
);
4063 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
4064 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4067 return bld
.emit_uniformize(surf_index
);
4071 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
4073 switch (nir_intrinsic_image_dim(instr
)) {
4074 case GLSL_SAMPLER_DIM_1D
:
4075 return 1 + nir_intrinsic_image_array(instr
);
4076 case GLSL_SAMPLER_DIM_2D
:
4077 case GLSL_SAMPLER_DIM_RECT
:
4078 return 2 + nir_intrinsic_image_array(instr
);
4079 case GLSL_SAMPLER_DIM_3D
:
4080 case GLSL_SAMPLER_DIM_CUBE
:
4082 case GLSL_SAMPLER_DIM_BUF
:
4084 case GLSL_SAMPLER_DIM_MS
:
4085 return 2 + nir_intrinsic_image_array(instr
);
4087 unreachable("Invalid image dimension");
4092 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4095 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4096 dest
= get_nir_dest(instr
->dest
);
4098 switch (instr
->intrinsic
) {
4099 case nir_intrinsic_image_load
:
4100 case nir_intrinsic_image_store
:
4101 case nir_intrinsic_image_atomic_add
:
4102 case nir_intrinsic_image_atomic_min
:
4103 case nir_intrinsic_image_atomic_max
:
4104 case nir_intrinsic_image_atomic_and
:
4105 case nir_intrinsic_image_atomic_or
:
4106 case nir_intrinsic_image_atomic_xor
:
4107 case nir_intrinsic_image_atomic_exchange
:
4108 case nir_intrinsic_image_atomic_comp_swap
:
4109 case nir_intrinsic_bindless_image_load
:
4110 case nir_intrinsic_bindless_image_store
:
4111 case nir_intrinsic_bindless_image_atomic_add
:
4112 case nir_intrinsic_bindless_image_atomic_min
:
4113 case nir_intrinsic_bindless_image_atomic_max
:
4114 case nir_intrinsic_bindless_image_atomic_and
:
4115 case nir_intrinsic_bindless_image_atomic_or
:
4116 case nir_intrinsic_bindless_image_atomic_xor
:
4117 case nir_intrinsic_bindless_image_atomic_exchange
:
4118 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4119 if (stage
== MESA_SHADER_FRAGMENT
&&
4120 instr
->intrinsic
!= nir_intrinsic_image_load
)
4121 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4123 /* Get some metadata from the image intrinsic. */
4124 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4125 const GLenum format
= nir_intrinsic_format(instr
);
4127 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4129 switch (instr
->intrinsic
) {
4130 case nir_intrinsic_image_load
:
4131 case nir_intrinsic_image_store
:
4132 case nir_intrinsic_image_atomic_add
:
4133 case nir_intrinsic_image_atomic_min
:
4134 case nir_intrinsic_image_atomic_max
:
4135 case nir_intrinsic_image_atomic_and
:
4136 case nir_intrinsic_image_atomic_or
:
4137 case nir_intrinsic_image_atomic_xor
:
4138 case nir_intrinsic_image_atomic_exchange
:
4139 case nir_intrinsic_image_atomic_comp_swap
:
4140 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4141 get_nir_image_intrinsic_image(bld
, instr
);
4146 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4147 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4151 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4152 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4153 brw_imm_ud(image_intrinsic_coord_components(instr
));
4155 /* Emit an image load, store or atomic op. */
4156 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4157 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4158 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4160 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4161 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4162 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4163 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4164 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4165 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4166 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4167 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4168 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4171 unsigned num_srcs
= info
->num_srcs
;
4173 switch (instr
->intrinsic
) {
4174 case nir_intrinsic_image_atomic_add
:
4175 case nir_intrinsic_bindless_image_atomic_add
:
4176 assert(num_srcs
== 4);
4178 op
= get_op_for_atomic_add(instr
, 3);
4180 if (op
!= BRW_AOP_ADD
)
4183 case nir_intrinsic_image_atomic_min
:
4184 case nir_intrinsic_bindless_image_atomic_min
:
4185 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4186 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
4188 case nir_intrinsic_image_atomic_max
:
4189 case nir_intrinsic_bindless_image_atomic_max
:
4190 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4191 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
4193 case nir_intrinsic_image_atomic_and
:
4194 case nir_intrinsic_bindless_image_atomic_and
:
4197 case nir_intrinsic_image_atomic_or
:
4198 case nir_intrinsic_bindless_image_atomic_or
:
4201 case nir_intrinsic_image_atomic_xor
:
4202 case nir_intrinsic_bindless_image_atomic_xor
:
4205 case nir_intrinsic_image_atomic_exchange
:
4206 case nir_intrinsic_bindless_image_atomic_exchange
:
4209 case nir_intrinsic_image_atomic_comp_swap
:
4210 case nir_intrinsic_bindless_image_atomic_comp_swap
:
4214 unreachable("Not reachable.");
4217 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4221 data
= get_nir_src(instr
->src
[3]);
4222 if (num_srcs
>= 5) {
4223 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4224 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4225 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4228 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4230 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4231 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4236 case nir_intrinsic_image_size
:
4237 case nir_intrinsic_bindless_image_size
: {
4238 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4239 * into will handle the binding table index for us in the geneerator.
4240 * Incidentally, this means that we can handle bindless with exactly the
4243 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4244 BRW_REGISTER_TYPE_UD
);
4245 image
= bld
.emit_uniformize(image
);
4247 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4248 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4249 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4251 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4252 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4253 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4254 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4256 /* Since the image size is always uniform, we can just emit a SIMD8
4257 * query instruction and splat the result out.
4259 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4261 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4262 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4263 tmp
, srcs
, ARRAY_SIZE(srcs
));
4264 inst
->size_written
= 4 * REG_SIZE
;
4266 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4267 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4268 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4269 offset(retype(dest
, tmp
.type
), bld
, c
),
4270 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4272 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4273 component(offset(tmp
, ubld
, c
), 0));
4279 case nir_intrinsic_image_load_raw_intel
: {
4280 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4281 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4282 get_nir_image_intrinsic_image(bld
, instr
);
4283 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4284 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4285 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4288 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4289 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4290 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4294 case nir_intrinsic_image_store_raw_intel
: {
4295 if (stage
== MESA_SHADER_FRAGMENT
)
4296 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4298 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4299 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4300 get_nir_image_intrinsic_image(bld
, instr
);
4301 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4302 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4303 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4304 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4306 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4307 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4311 case nir_intrinsic_group_memory_barrier
:
4312 case nir_intrinsic_memory_barrier_shared
:
4313 case nir_intrinsic_memory_barrier_atomic_counter
:
4314 case nir_intrinsic_memory_barrier_buffer
:
4315 case nir_intrinsic_memory_barrier_image
:
4316 case nir_intrinsic_memory_barrier
: {
4317 const fs_builder ubld
= bld
.group(8, 0);
4318 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4319 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4320 brw_vec8_grf(0, 0), brw_imm_ud(0))
4321 ->size_written
= 2 * REG_SIZE
;
4325 case nir_intrinsic_shader_clock
: {
4326 /* We cannot do anything if there is an event, so ignore it for now */
4327 const fs_reg shader_clock
= get_timestamp(bld
);
4328 const fs_reg srcs
[] = { component(shader_clock
, 0),
4329 component(shader_clock
, 1) };
4330 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4334 case nir_intrinsic_image_samples
:
4335 /* The driver does not support multi-sampled images. */
4336 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4339 case nir_intrinsic_load_uniform
: {
4340 /* Offsets are in bytes but they should always aligned to
4343 assert(instr
->const_index
[0] % 4 == 0 ||
4344 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4346 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4348 if (nir_src_is_const(instr
->src
[0])) {
4349 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4350 assert(load_offset
% type_sz(dest
.type
) == 0);
4351 /* For 16-bit types we add the module of the const_index[0]
4352 * offset to access to not 32-bit aligned element
4354 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4356 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4357 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4360 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4361 BRW_REGISTER_TYPE_UD
);
4363 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4364 * go past the end of the uniform. In order to keep the n'th
4365 * component from running past, we subtract off the size of all but
4366 * one component of the vector.
4368 assert(instr
->const_index
[1] >=
4369 instr
->num_components
* (int) type_sz(dest
.type
));
4370 unsigned read_size
= instr
->const_index
[1] -
4371 (instr
->num_components
- 1) * type_sz(dest
.type
);
4373 bool supports_64bit_indirects
=
4374 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4376 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4377 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4378 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4379 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4380 indirect
, brw_imm_ud(read_size
));
4383 const unsigned num_mov_indirects
=
4384 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4385 /* We read a little bit less per MOV INDIRECT, as they are now
4386 * 32-bits ones instead of 64-bit. Fix read_size then.
4388 const unsigned read_size_32bit
= read_size
-
4389 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4390 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4391 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4392 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4393 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4394 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4395 indirect
, brw_imm_ud(read_size_32bit
));
4403 case nir_intrinsic_load_ubo
: {
4405 if (nir_src_is_const(instr
->src
[0])) {
4406 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4407 nir_src_as_uint(instr
->src
[0]);
4408 surf_index
= brw_imm_ud(index
);
4410 /* The block index is not a constant. Evaluate the index expression
4411 * per-channel and add the base UBO index; we have to select a value
4412 * from any live channel.
4414 surf_index
= vgrf(glsl_type::uint_type
);
4415 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4416 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4417 surf_index
= bld
.emit_uniformize(surf_index
);
4420 if (!nir_src_is_const(instr
->src
[1])) {
4421 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4422 BRW_REGISTER_TYPE_UD
);
4424 for (int i
= 0; i
< instr
->num_components
; i
++)
4425 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4426 base_offset
, i
* type_sz(dest
.type
));
4428 /* Even if we are loading doubles, a pull constant load will load
4429 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4430 * need to load a full dvec4 we will have to emit 2 loads. This is
4431 * similar to demote_pull_constants(), except that in that case we
4432 * see individual accesses to each component of the vector and then
4433 * we let CSE deal with duplicate loads. Here we see a vector access
4434 * and we have to split it if necessary.
4436 const unsigned type_size
= type_sz(dest
.type
);
4437 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4439 /* See if we've selected this as a push constant candidate */
4440 if (nir_src_is_const(instr
->src
[0])) {
4441 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4442 const unsigned offset_256b
= load_offset
/ 32;
4445 for (int i
= 0; i
< 4; i
++) {
4446 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4447 if (range
->block
== ubo_block
&&
4448 offset_256b
>= range
->start
&&
4449 offset_256b
< range
->start
+ range
->length
) {
4451 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4452 push_reg
.offset
= load_offset
- 32 * range
->start
;
4457 if (push_reg
.file
!= BAD_FILE
) {
4458 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4459 bld
.MOV(offset(dest
, bld
, i
),
4460 byte_offset(push_reg
, i
* type_size
));
4466 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4467 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4468 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4470 for (unsigned c
= 0; c
< instr
->num_components
;) {
4471 const unsigned base
= load_offset
+ c
* type_size
;
4472 /* Number of usable components in the next block-aligned load. */
4473 const unsigned count
= MIN2(instr
->num_components
- c
,
4474 (block_sz
- base
% block_sz
) / type_size
);
4476 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4477 packed_consts
, surf_index
,
4478 brw_imm_ud(base
& ~(block_sz
- 1)));
4480 const fs_reg consts
=
4481 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4484 for (unsigned d
= 0; d
< count
; d
++)
4485 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4493 case nir_intrinsic_load_global
: {
4494 assert(devinfo
->gen
>= 8);
4496 if (nir_intrinsic_align(instr
) >= 4) {
4497 assert(nir_dest_bit_size(instr
->dest
) == 32);
4498 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4500 get_nir_src(instr
->src
[0]), /* Address */
4501 fs_reg(), /* No source data */
4502 brw_imm_ud(instr
->num_components
));
4503 inst
->size_written
= instr
->num_components
*
4504 inst
->dst
.component_size(inst
->exec_size
);
4506 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4507 assert(bit_size
<= 32);
4508 assert(nir_dest_num_components(instr
->dest
) == 1);
4509 brw_reg_type data_type
=
4510 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4511 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4512 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4514 get_nir_src(instr
->src
[0]), /* Address */
4515 fs_reg(), /* No source data */
4516 brw_imm_ud(bit_size
));
4517 bld
.MOV(retype(dest
, data_type
), tmp
);
4522 case nir_intrinsic_store_global
:
4523 assert(devinfo
->gen
>= 8);
4525 if (stage
== MESA_SHADER_FRAGMENT
)
4526 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4528 if (nir_intrinsic_align(instr
) >= 4) {
4529 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4530 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4532 get_nir_src(instr
->src
[1]), /* Address */
4533 get_nir_src(instr
->src
[0]), /* Data */
4534 brw_imm_ud(instr
->num_components
));
4536 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4537 assert(bit_size
<= 32);
4538 assert(nir_src_num_components(instr
->src
[0]) == 1);
4539 brw_reg_type data_type
=
4540 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4541 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4542 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4543 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4545 get_nir_src(instr
->src
[1]), /* Address */
4547 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4551 case nir_intrinsic_global_atomic_add
:
4552 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4554 case nir_intrinsic_global_atomic_imin
:
4555 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4557 case nir_intrinsic_global_atomic_umin
:
4558 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4560 case nir_intrinsic_global_atomic_imax
:
4561 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4563 case nir_intrinsic_global_atomic_umax
:
4564 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4566 case nir_intrinsic_global_atomic_and
:
4567 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4569 case nir_intrinsic_global_atomic_or
:
4570 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4572 case nir_intrinsic_global_atomic_xor
:
4573 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4575 case nir_intrinsic_global_atomic_exchange
:
4576 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4578 case nir_intrinsic_global_atomic_comp_swap
:
4579 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4581 case nir_intrinsic_global_atomic_fmin
:
4582 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4584 case nir_intrinsic_global_atomic_fmax
:
4585 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4587 case nir_intrinsic_global_atomic_fcomp_swap
:
4588 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4591 case nir_intrinsic_load_ssbo
: {
4592 assert(devinfo
->gen
>= 7);
4594 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4595 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4596 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4597 get_nir_ssbo_intrinsic_index(bld
, instr
);
4598 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4599 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4601 /* Make dest unsigned because that's what the temporary will be */
4602 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4604 /* Read the vector */
4605 if (nir_intrinsic_align(instr
) >= 4) {
4606 assert(nir_dest_bit_size(instr
->dest
) == 32);
4607 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4609 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4610 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4611 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4613 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4614 assert(nir_dest_num_components(instr
->dest
) == 1);
4615 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4617 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4618 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4619 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4620 bld
.MOV(dest
, read_result
);
4625 case nir_intrinsic_store_ssbo
: {
4626 assert(devinfo
->gen
>= 7);
4628 if (stage
== MESA_SHADER_FRAGMENT
)
4629 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4631 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4632 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4633 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4634 get_nir_ssbo_intrinsic_index(bld
, instr
);
4635 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4636 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4638 fs_reg data
= get_nir_src(instr
->src
[0]);
4639 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4641 assert(nir_intrinsic_write_mask(instr
) ==
4642 (1u << instr
->num_components
) - 1);
4643 if (nir_intrinsic_align(instr
) >= 4) {
4644 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4645 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4646 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4647 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4648 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4649 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4651 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4652 assert(nir_src_num_components(instr
->src
[0]) == 1);
4653 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4655 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4656 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4658 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4659 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4664 case nir_intrinsic_store_output
: {
4665 fs_reg src
= get_nir_src(instr
->src
[0]);
4667 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4668 unsigned num_components
= instr
->num_components
;
4669 unsigned first_component
= nir_intrinsic_component(instr
);
4670 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4671 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4672 num_components
*= 2;
4675 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4676 4 * store_offset
), src
.type
);
4677 for (unsigned j
= 0; j
< num_components
; j
++) {
4678 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4679 offset(src
, bld
, j
));
4684 case nir_intrinsic_ssbo_atomic_add
:
4685 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4687 case nir_intrinsic_ssbo_atomic_imin
:
4688 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4690 case nir_intrinsic_ssbo_atomic_umin
:
4691 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4693 case nir_intrinsic_ssbo_atomic_imax
:
4694 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4696 case nir_intrinsic_ssbo_atomic_umax
:
4697 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4699 case nir_intrinsic_ssbo_atomic_and
:
4700 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4702 case nir_intrinsic_ssbo_atomic_or
:
4703 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4705 case nir_intrinsic_ssbo_atomic_xor
:
4706 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4708 case nir_intrinsic_ssbo_atomic_exchange
:
4709 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4711 case nir_intrinsic_ssbo_atomic_comp_swap
:
4712 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4714 case nir_intrinsic_ssbo_atomic_fmin
:
4715 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4717 case nir_intrinsic_ssbo_atomic_fmax
:
4718 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4720 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4721 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4724 case nir_intrinsic_get_buffer_size
: {
4725 assert(nir_src_num_components(instr
->src
[0]) == 1);
4726 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4727 nir_src_as_uint(instr
->src
[0]) : 0;
4729 /* A resinfo's sampler message is used to get the buffer size. The
4730 * SIMD8's writeback message consists of four registers and SIMD16's
4731 * writeback message consists of 8 destination registers (two per each
4732 * component). Because we are only interested on the first channel of
4733 * the first returned component, where resinfo returns the buffer size
4734 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4735 * the dispatch width.
4737 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4738 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4739 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4742 ubld
.MOV(src_payload
, brw_imm_d(0));
4744 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4745 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4746 src_payload
, brw_imm_ud(index
));
4747 inst
->header_size
= 0;
4749 inst
->size_written
= 4 * REG_SIZE
;
4751 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4753 * "Out-of-bounds checking is always performed at a DWord granularity. If
4754 * any part of the DWord is out-of-bounds then the whole DWord is
4755 * considered out-of-bounds."
4757 * This implies that types with size smaller than 4-bytes need to be
4758 * padded if they don't complete the last dword of the buffer. But as we
4759 * need to maintain the original size we need to reverse the padding
4760 * calculation to return the correct size to know the number of elements
4761 * of an unsized array. As we stored in the last two bits of the surface
4762 * size the needed padding for the buffer, we calculate here the
4763 * original buffer_size reversing the surface_size calculation:
4765 * surface_size = isl_align(buffer_size, 4) +
4766 * (isl_align(buffer_size) - buffer_size)
4768 * buffer_size = surface_size & ~3 - surface_size & 3
4771 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4772 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4773 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4775 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4776 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4777 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4779 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4783 case nir_intrinsic_load_subgroup_invocation
:
4784 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4785 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4788 case nir_intrinsic_load_subgroup_eq_mask
:
4789 case nir_intrinsic_load_subgroup_ge_mask
:
4790 case nir_intrinsic_load_subgroup_gt_mask
:
4791 case nir_intrinsic_load_subgroup_le_mask
:
4792 case nir_intrinsic_load_subgroup_lt_mask
:
4793 unreachable("not reached");
4795 case nir_intrinsic_vote_any
: {
4796 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4798 /* The any/all predicates do not consider channel enables. To prevent
4799 * dead channels from affecting the result, we initialize the flag with
4800 * with the identity value for the logical operation.
4802 if (dispatch_width
== 32) {
4803 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4804 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4807 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4809 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4811 /* For some reason, the any/all predicates don't work properly with
4812 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4813 * doesn't read the correct subset of the flag register and you end up
4814 * getting garbage in the second half. Work around this by using a pair
4815 * of 1-wide MOVs and scattering the result.
4817 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4818 ubld
.MOV(res1
, brw_imm_d(0));
4819 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4820 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4821 BRW_PREDICATE_ALIGN1_ANY32H
,
4822 ubld
.MOV(res1
, brw_imm_d(-1)));
4824 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4827 case nir_intrinsic_vote_all
: {
4828 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4830 /* The any/all predicates do not consider channel enables. To prevent
4831 * dead channels from affecting the result, we initialize the flag with
4832 * with the identity value for the logical operation.
4834 if (dispatch_width
== 32) {
4835 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4836 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4837 brw_imm_ud(0xffffffff));
4839 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4841 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4843 /* For some reason, the any/all predicates don't work properly with
4844 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4845 * doesn't read the correct subset of the flag register and you end up
4846 * getting garbage in the second half. Work around this by using a pair
4847 * of 1-wide MOVs and scattering the result.
4849 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4850 ubld
.MOV(res1
, brw_imm_d(0));
4851 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4852 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4853 BRW_PREDICATE_ALIGN1_ALL32H
,
4854 ubld
.MOV(res1
, brw_imm_d(-1)));
4856 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4859 case nir_intrinsic_vote_feq
:
4860 case nir_intrinsic_vote_ieq
: {
4861 fs_reg value
= get_nir_src(instr
->src
[0]);
4862 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4863 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4864 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4865 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4868 fs_reg uniformized
= bld
.emit_uniformize(value
);
4869 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4871 /* The any/all predicates do not consider channel enables. To prevent
4872 * dead channels from affecting the result, we initialize the flag with
4873 * with the identity value for the logical operation.
4875 if (dispatch_width
== 32) {
4876 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4877 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4878 brw_imm_ud(0xffffffff));
4880 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4882 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4884 /* For some reason, the any/all predicates don't work properly with
4885 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4886 * doesn't read the correct subset of the flag register and you end up
4887 * getting garbage in the second half. Work around this by using a pair
4888 * of 1-wide MOVs and scattering the result.
4890 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4891 ubld
.MOV(res1
, brw_imm_d(0));
4892 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4893 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4894 BRW_PREDICATE_ALIGN1_ALL32H
,
4895 ubld
.MOV(res1
, brw_imm_d(-1)));
4897 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4901 case nir_intrinsic_ballot
: {
4902 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4903 BRW_REGISTER_TYPE_UD
);
4904 struct brw_reg flag
= brw_flag_reg(0, 0);
4905 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4906 * as f0.0. This is a problem for fragment programs as we currently use
4907 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4908 * programs yet so this isn't a problem. When we do, something will
4911 if (dispatch_width
== 32)
4912 flag
.type
= BRW_REGISTER_TYPE_UD
;
4914 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4915 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4917 if (instr
->dest
.ssa
.bit_size
> 32) {
4918 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4920 dest
.type
= BRW_REGISTER_TYPE_UD
;
4922 bld
.MOV(dest
, flag
);
4926 case nir_intrinsic_read_invocation
: {
4927 const fs_reg value
= get_nir_src(instr
->src
[0]);
4928 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4929 fs_reg tmp
= bld
.vgrf(value
.type
);
4931 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4932 bld
.emit_uniformize(invocation
));
4934 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4938 case nir_intrinsic_read_first_invocation
: {
4939 const fs_reg value
= get_nir_src(instr
->src
[0]);
4940 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4944 case nir_intrinsic_shuffle
: {
4945 const fs_reg value
= get_nir_src(instr
->src
[0]);
4946 const fs_reg index
= get_nir_src(instr
->src
[1]);
4948 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4952 case nir_intrinsic_first_invocation
: {
4953 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4954 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4955 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4956 fs_reg(component(tmp
, 0)));
4960 case nir_intrinsic_quad_broadcast
: {
4961 const fs_reg value
= get_nir_src(instr
->src
[0]);
4962 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4964 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4965 value
, brw_imm_ud(index
), brw_imm_ud(4));
4969 case nir_intrinsic_quad_swap_horizontal
: {
4970 const fs_reg value
= get_nir_src(instr
->src
[0]);
4971 const fs_reg tmp
= bld
.vgrf(value
.type
);
4972 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4974 const fs_reg src_left
= horiz_stride(value
, 2);
4975 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4976 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4977 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4979 ubld
.MOV(tmp_left
, src_right
);
4980 ubld
.MOV(tmp_right
, src_left
);
4982 bld
.MOV(retype(dest
, value
.type
), tmp
);
4986 case nir_intrinsic_quad_swap_vertical
: {
4987 const fs_reg value
= get_nir_src(instr
->src
[0]);
4988 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4989 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4990 const fs_reg tmp
= bld
.vgrf(value
.type
);
4991 const fs_builder ubld
= bld
.exec_all();
4992 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4993 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4994 bld
.MOV(retype(dest
, value
.type
), tmp
);
4996 /* For larger data types, we have to either emit dispatch_width many
4997 * MOVs or else fall back to doing indirects.
4999 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5000 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5002 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5007 case nir_intrinsic_quad_swap_diagonal
: {
5008 const fs_reg value
= get_nir_src(instr
->src
[0]);
5009 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5010 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5011 const fs_reg tmp
= bld
.vgrf(value
.type
);
5012 const fs_builder ubld
= bld
.exec_all();
5013 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5014 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5015 bld
.MOV(retype(dest
, value
.type
), tmp
);
5017 /* For larger data types, we have to either emit dispatch_width many
5018 * MOVs or else fall back to doing indirects.
5020 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5021 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5023 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5028 case nir_intrinsic_reduce
: {
5029 fs_reg src
= get_nir_src(instr
->src
[0]);
5030 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5031 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5032 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5033 cluster_size
= dispatch_width
;
5035 /* Figure out the source type */
5036 src
.type
= brw_type_for_nir_type(devinfo
,
5037 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5038 nir_src_bit_size(instr
->src
[0])));
5040 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5041 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5042 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5044 /* Set up a register for all of our scratching around and initialize it
5045 * to reduction operation's identity value.
5047 fs_reg scan
= bld
.vgrf(src
.type
);
5048 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5050 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5052 dest
.type
= src
.type
;
5053 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5054 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5055 * the distance between clusters is at least 2 GRFs. In this case,
5056 * we don't need the weird striding of the CLUSTER_BROADCAST
5057 * instruction and can just do regular MOVs.
5059 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5060 const unsigned groups
=
5061 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5062 const unsigned group_size
= dispatch_width
/ groups
;
5063 for (unsigned i
= 0; i
< groups
; i
++) {
5064 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5065 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5066 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5067 component(scan
, comp
));
5070 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5071 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5076 case nir_intrinsic_inclusive_scan
:
5077 case nir_intrinsic_exclusive_scan
: {
5078 fs_reg src
= get_nir_src(instr
->src
[0]);
5079 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5081 /* Figure out the source type */
5082 src
.type
= brw_type_for_nir_type(devinfo
,
5083 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5084 nir_src_bit_size(instr
->src
[0])));
5086 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5087 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5088 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5090 /* Set up a register for all of our scratching around and initialize it
5091 * to reduction operation's identity value.
5093 fs_reg scan
= bld
.vgrf(src
.type
);
5094 const fs_builder allbld
= bld
.exec_all();
5095 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5097 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5098 /* Exclusive scan is a bit harder because we have to do an annoying
5099 * shift of the contents before we can begin. To make things worse,
5100 * we can't do this with a normal stride; we have to use indirects.
5102 fs_reg shifted
= bld
.vgrf(src
.type
);
5103 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5104 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5106 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5107 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5111 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5113 bld
.MOV(retype(dest
, src
.type
), scan
);
5117 case nir_intrinsic_begin_invocation_interlock
: {
5118 const fs_builder ubld
= bld
.group(8, 0);
5119 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5121 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5122 ->size_written
= 2 * REG_SIZE
;
5126 case nir_intrinsic_end_invocation_interlock
: {
5127 /* For endInvocationInterlock(), we need to insert a memory fence which
5128 * stalls in the shader until the memory transactions prior to that
5129 * fence are complete. This ensures that the shader does not end before
5130 * any writes from its critical section have landed. Otherwise, you can
5131 * end up with a case where the next invocation on that pixel properly
5132 * stalls for previous FS invocation on its pixel to complete but
5133 * doesn't actually wait for the dataport memory transactions from that
5134 * thread to land before submitting its own.
5136 const fs_builder ubld
= bld
.group(8, 0);
5137 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5138 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5139 brw_vec8_grf(0, 0), brw_imm_ud(1))
5140 ->size_written
= 2 * REG_SIZE
;
5145 unreachable("unknown intrinsic");
5150 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5151 int op
, nir_intrinsic_instr
*instr
)
5153 if (stage
== MESA_SHADER_FRAGMENT
)
5154 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5156 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5157 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5158 * appear to exist. However, if you look at Vol 2a, there are no message
5159 * descriptors provided for Qword atomic ops except for A64 messages.
5161 assert(nir_dest_bit_size(instr
->dest
) == 32);
5164 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5165 dest
= get_nir_dest(instr
->dest
);
5167 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5168 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5169 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5170 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5171 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5174 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5175 data
= get_nir_src(instr
->src
[2]);
5177 if (op
== BRW_AOP_CMPWR
) {
5178 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5179 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5180 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5183 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5185 /* Emit the actual atomic operation */
5187 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5188 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5192 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5193 int op
, nir_intrinsic_instr
*instr
)
5195 if (stage
== MESA_SHADER_FRAGMENT
)
5196 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5199 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5200 dest
= get_nir_dest(instr
->dest
);
5202 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5203 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5204 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5205 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5206 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5208 fs_reg data
= get_nir_src(instr
->src
[2]);
5209 if (op
== BRW_AOP_FCMPWR
) {
5210 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5211 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5212 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5215 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5217 /* Emit the actual atomic operation */
5219 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5220 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5224 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5225 int op
, nir_intrinsic_instr
*instr
)
5228 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5229 dest
= get_nir_dest(instr
->dest
);
5231 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5232 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5233 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5234 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5237 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5238 data
= get_nir_src(instr
->src
[1]);
5239 if (op
== BRW_AOP_CMPWR
) {
5240 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5241 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5242 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5245 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5247 /* Get the offset */
5248 if (nir_src_is_const(instr
->src
[0])) {
5249 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5250 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5252 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5253 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5254 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5255 brw_imm_ud(instr
->const_index
[0]));
5258 /* Emit the actual atomic operation operation */
5260 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5261 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5265 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5266 int op
, nir_intrinsic_instr
*instr
)
5269 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5270 dest
= get_nir_dest(instr
->dest
);
5272 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5273 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5274 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5275 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5277 fs_reg data
= get_nir_src(instr
->src
[1]);
5278 if (op
== BRW_AOP_FCMPWR
) {
5279 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5280 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5281 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5284 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5286 /* Get the offset */
5287 if (nir_src_is_const(instr
->src
[0])) {
5288 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5289 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5291 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5292 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5293 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5294 brw_imm_ud(instr
->const_index
[0]));
5297 /* Emit the actual atomic operation operation */
5299 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5300 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5304 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5305 int op
, nir_intrinsic_instr
*instr
)
5307 if (stage
== MESA_SHADER_FRAGMENT
)
5308 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5311 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5312 dest
= get_nir_dest(instr
->dest
);
5314 fs_reg addr
= get_nir_src(instr
->src
[0]);
5317 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5318 data
= get_nir_src(instr
->src
[1]);
5320 if (op
== BRW_AOP_CMPWR
) {
5321 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5322 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5323 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5327 if (nir_dest_bit_size(instr
->dest
) == 64) {
5328 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5329 dest
, addr
, data
, brw_imm_ud(op
));
5331 assert(nir_dest_bit_size(instr
->dest
) == 32);
5332 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5333 dest
, addr
, data
, brw_imm_ud(op
));
5338 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5339 int op
, nir_intrinsic_instr
*instr
)
5341 if (stage
== MESA_SHADER_FRAGMENT
)
5342 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5344 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5345 fs_reg dest
= get_nir_dest(instr
->dest
);
5347 fs_reg addr
= get_nir_src(instr
->src
[0]);
5349 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5350 fs_reg data
= get_nir_src(instr
->src
[1]);
5352 if (op
== BRW_AOP_FCMPWR
) {
5353 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5354 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5355 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5359 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5360 dest
, addr
, data
, brw_imm_ud(op
));
5364 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5366 unsigned texture
= instr
->texture_index
;
5367 unsigned sampler
= instr
->sampler_index
;
5369 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5371 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5372 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5374 int lod_components
= 0;
5376 /* The hardware requires a LOD for buffer textures */
5377 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5378 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5380 uint32_t header_bits
= 0;
5381 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5382 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5383 switch (instr
->src
[i
].src_type
) {
5384 case nir_tex_src_bias
:
5385 srcs
[TEX_LOGICAL_SRC_LOD
] =
5386 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5388 case nir_tex_src_comparator
:
5389 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5391 case nir_tex_src_coord
:
5392 switch (instr
->op
) {
5394 case nir_texop_txf_ms
:
5395 case nir_texop_txf_ms_mcs
:
5396 case nir_texop_samples_identical
:
5397 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5400 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5404 case nir_tex_src_ddx
:
5405 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5406 lod_components
= nir_tex_instr_src_size(instr
, i
);
5408 case nir_tex_src_ddy
:
5409 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5411 case nir_tex_src_lod
:
5412 switch (instr
->op
) {
5414 srcs
[TEX_LOGICAL_SRC_LOD
] =
5415 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5418 srcs
[TEX_LOGICAL_SRC_LOD
] =
5419 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5422 srcs
[TEX_LOGICAL_SRC_LOD
] =
5423 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5427 case nir_tex_src_min_lod
:
5428 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5429 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5431 case nir_tex_src_ms_index
:
5432 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5435 case nir_tex_src_offset
: {
5436 uint32_t offset_bits
= 0;
5437 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5438 header_bits
|= offset_bits
;
5440 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5441 retype(src
, BRW_REGISTER_TYPE_D
);
5446 case nir_tex_src_projector
:
5447 unreachable("should be lowered");
5449 case nir_tex_src_texture_offset
: {
5450 /* Emit code to evaluate the actual indexing expression */
5451 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5452 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5453 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5457 case nir_tex_src_sampler_offset
: {
5458 /* Emit code to evaluate the actual indexing expression */
5459 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5460 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5461 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5465 case nir_tex_src_texture_handle
:
5466 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5467 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5468 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5471 case nir_tex_src_sampler_handle
:
5472 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5473 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5474 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5477 case nir_tex_src_ms_mcs
:
5478 assert(instr
->op
== nir_texop_txf_ms
);
5479 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5482 case nir_tex_src_plane
: {
5483 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5484 const uint32_t texture_index
=
5485 instr
->texture_index
+
5486 stage_prog_data
->binding_table
.plane_start
[plane
] -
5487 stage_prog_data
->binding_table
.texture_start
;
5489 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5494 unreachable("unknown texture source");
5498 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5499 (instr
->op
== nir_texop_txf_ms
||
5500 instr
->op
== nir_texop_samples_identical
)) {
5501 if (devinfo
->gen
>= 7 &&
5502 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5503 srcs
[TEX_LOGICAL_SRC_MCS
] =
5504 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5505 instr
->coord_components
,
5506 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5507 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5509 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5513 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5514 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5517 switch (instr
->op
) {
5519 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5522 opcode
= FS_OPCODE_TXB_LOGICAL
;
5525 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5528 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5531 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5533 case nir_texop_txf_ms
:
5534 if ((key_tex
->msaa_16
& (1 << sampler
)))
5535 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5537 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5539 case nir_texop_txf_ms_mcs
:
5540 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5542 case nir_texop_query_levels
:
5544 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5547 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5550 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5551 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5553 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5555 case nir_texop_texture_samples
:
5556 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5558 case nir_texop_samples_identical
: {
5559 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5561 /* If mcs is an immediate value, it means there is no MCS. In that case
5562 * just return false.
5564 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5565 bld
.MOV(dst
, brw_imm_ud(0u));
5566 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5567 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5568 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5569 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5570 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5572 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5573 BRW_CONDITIONAL_EQ
);
5578 unreachable("unknown texture opcode");
5581 if (instr
->op
== nir_texop_tg4
) {
5582 if (instr
->component
== 1 &&
5583 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5584 /* gather4 sampler is broken for green channel on RG32F --
5585 * we must ask for blue instead.
5587 header_bits
|= 2 << 16;
5589 header_bits
|= instr
->component
<< 16;
5593 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5594 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5595 inst
->offset
= header_bits
;
5597 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5598 if (devinfo
->gen
>= 9 &&
5599 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5600 unsigned write_mask
= instr
->dest
.is_ssa
?
5601 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5602 (1 << dest_size
) - 1;
5603 assert(write_mask
!= 0); /* dead code should have been eliminated */
5604 inst
->size_written
= util_last_bit(write_mask
) *
5605 inst
->dst
.component_size(inst
->exec_size
);
5607 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5610 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5611 inst
->shadow_compare
= true;
5613 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5614 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5617 for (unsigned i
= 0; i
< dest_size
; i
++)
5618 nir_dest
[i
] = offset(dst
, bld
, i
);
5620 if (instr
->op
== nir_texop_query_levels
) {
5621 /* # levels is in .w */
5622 nir_dest
[0] = offset(dst
, bld
, 3);
5623 } else if (instr
->op
== nir_texop_txs
&&
5624 dest_size
>= 3 && devinfo
->gen
< 7) {
5625 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5626 fs_reg depth
= offset(dst
, bld
, 2);
5627 nir_dest
[2] = vgrf(glsl_type::int_type
);
5628 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5631 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5635 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5637 switch (instr
->type
) {
5638 case nir_jump_break
:
5639 bld
.emit(BRW_OPCODE_BREAK
);
5641 case nir_jump_continue
:
5642 bld
.emit(BRW_OPCODE_CONTINUE
);
5644 case nir_jump_return
:
5646 unreachable("unknown jump");
5651 * This helper takes a source register and un/shuffles it into the destination
5654 * If source type size is smaller than destination type size the operation
5655 * needed is a component shuffle. The opposite case would be an unshuffle. If
5656 * source/destination type size is equal a shuffle is done that would be
5657 * equivalent to a simple MOV.
5659 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5660 * components .xyz 16-bit vector on SIMD8 would be.
5662 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5663 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5665 * This helper will return the following 2 32-bit components with the 16-bit
5668 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5669 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5671 * For unshuffle, the example would be the opposite, a 64-bit type source
5672 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5675 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5676 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5677 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5678 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5680 * The returned result would be the following 4 32-bit components unshuffled:
5682 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5683 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5684 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5685 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5687 * - Source and destination register must not be overlapped.
5688 * - components units are measured in terms of the smaller type between
5689 * source and destination because we are un/shuffling the smaller
5690 * components from/into the bigger ones.
5691 * - first_component parameter allows skipping source components.
5694 shuffle_src_to_dst(const fs_builder
&bld
,
5697 uint32_t first_component
,
5698 uint32_t components
)
5700 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5701 assert(!regions_overlap(dst
,
5702 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5703 offset(src
, bld
, first_component
),
5704 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5705 for (unsigned i
= 0; i
< components
; i
++) {
5706 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5707 offset(src
, bld
, i
+ first_component
));
5709 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5710 /* Source is shuffled into destination */
5711 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5712 assert(!regions_overlap(dst
,
5713 type_sz(dst
.type
) * bld
.dispatch_width() *
5714 DIV_ROUND_UP(components
, size_ratio
),
5715 offset(src
, bld
, first_component
),
5716 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5718 brw_reg_type shuffle_type
=
5719 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5720 BRW_REGISTER_TYPE_D
);
5721 for (unsigned i
= 0; i
< components
; i
++) {
5722 fs_reg shuffle_component_i
=
5723 subscript(offset(dst
, bld
, i
/ size_ratio
),
5724 shuffle_type
, i
% size_ratio
);
5725 bld
.MOV(shuffle_component_i
,
5726 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5729 /* Source is unshuffled into destination */
5730 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5731 assert(!regions_overlap(dst
,
5732 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5733 offset(src
, bld
, first_component
/ size_ratio
),
5734 type_sz(src
.type
) * bld
.dispatch_width() *
5735 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5738 brw_reg_type shuffle_type
=
5739 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5740 BRW_REGISTER_TYPE_D
);
5741 for (unsigned i
= 0; i
< components
; i
++) {
5742 fs_reg shuffle_component_i
=
5743 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5744 shuffle_type
, (first_component
+ i
) % size_ratio
);
5745 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5746 shuffle_component_i
);
5752 shuffle_from_32bit_read(const fs_builder
&bld
,
5755 uint32_t first_component
,
5756 uint32_t components
)
5758 assert(type_sz(src
.type
) == 4);
5760 /* This function takes components in units of the destination type while
5761 * shuffle_src_to_dst takes components in units of the smallest type
5763 if (type_sz(dst
.type
) > 4) {
5764 assert(type_sz(dst
.type
) == 8);
5765 first_component
*= 2;
5769 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5773 shuffle_for_32bit_write(const fs_builder
&bld
,
5775 uint32_t first_component
,
5776 uint32_t components
)
5778 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5779 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5780 /* This function takes components in units of the source type while
5781 * shuffle_src_to_dst takes components in units of the smallest type
5783 if (type_sz(src
.type
) > 4) {
5784 assert(type_sz(src
.type
) == 8);
5785 first_component
*= 2;
5789 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5795 setup_imm_df(const fs_builder
&bld
, double v
)
5797 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5798 assert(devinfo
->gen
>= 7);
5800 if (devinfo
->gen
>= 8)
5801 return brw_imm_df(v
);
5803 /* gen7.5 does not support DF immediates straighforward but the DIM
5804 * instruction allows to set the 64-bit immediate value.
5806 if (devinfo
->is_haswell
) {
5807 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5808 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5809 ubld
.DIM(dst
, brw_imm_df(v
));
5810 return component(dst
, 0);
5813 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5814 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5815 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5817 * Alternatively, we could also produce a normal VGRF (without stride 0)
5818 * by writing to all the channels in the VGRF, however, that would hit the
5819 * gen7 bug where we have to split writes that span more than 1 register
5820 * into instructions with a width of 4 (otherwise the write to the second
5821 * register written runs into an execmask hardware bug) which isn't very
5834 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5835 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5836 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5837 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5839 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5843 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5845 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5846 bld
.MOV(tmp
, brw_imm_w(v
));
5851 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5853 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5854 bld
.MOV(tmp
, brw_imm_uw(v
));