2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
45 last_scratch
= ALIGN(nir
->scratch_size
, 4) * dispatch_width
;
47 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
, true);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add uniforms for builtins after regular NIR uniforms. */
105 assert(uniforms
== prog_data
->nr_params
);
108 if (brw_cs_prog_data(prog_data
)->uses_variable_group_size
) {
109 param
= brw_stage_prog_data_add_params(prog_data
, 3);
110 for (unsigned i
= 0; i
< 3; i
++) {
111 param
[i
] = (BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
+ i
);
112 group_size
[i
] = fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
116 /* Subgroup ID must be the last uniform on the list. This will make
117 * easier later to split between cross thread and per thread
120 param
= brw_stage_prog_data_add_params(prog_data
, 1);
121 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
122 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
127 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
131 nir_foreach_instr(instr
, block
) {
132 if (instr
->type
!= nir_instr_type_intrinsic
)
135 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
136 switch (intrin
->intrinsic
) {
137 case nir_intrinsic_load_vertex_id
:
138 case nir_intrinsic_load_base_vertex
:
139 unreachable("should be lowered by nir_lower_system_values().");
141 case nir_intrinsic_load_vertex_id_zero_base
:
142 case nir_intrinsic_load_is_indexed_draw
:
143 case nir_intrinsic_load_first_vertex
:
144 case nir_intrinsic_load_instance_id
:
145 case nir_intrinsic_load_base_instance
:
146 case nir_intrinsic_load_draw_id
:
147 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
149 case nir_intrinsic_load_invocation_id
:
150 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
152 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
154 if (reg
->file
== BAD_FILE
) {
155 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
156 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
157 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
158 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
163 case nir_intrinsic_load_sample_pos
:
164 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplepos_setup();
170 case nir_intrinsic_load_sample_id
:
171 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_sampleid_setup();
177 case nir_intrinsic_load_sample_mask_in
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 assert(v
->devinfo
->gen
>= 7);
180 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
181 if (reg
->file
== BAD_FILE
)
182 *reg
= *v
->emit_samplemaskin_setup();
185 case nir_intrinsic_load_work_group_id
:
186 assert(v
->stage
== MESA_SHADER_COMPUTE
);
187 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
188 if (reg
->file
== BAD_FILE
)
189 *reg
= *v
->emit_cs_work_group_id_setup();
192 case nir_intrinsic_load_helper_invocation
:
193 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
194 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
195 if (reg
->file
== BAD_FILE
) {
196 const fs_builder abld
=
197 v
->bld
.annotate("gl_HelperInvocation", NULL
);
199 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
200 * pixel mask is in g1.7 of the thread payload.
202 * We move the per-channel pixel enable bit to the low bit of each
203 * channel by shifting the byte containing the pixel mask by the
204 * vector immediate 0x76543210UV.
206 * The region of <1,8,0> reads only 1 byte (the pixel masks for
207 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
208 * masks for 2 and 3) in SIMD16.
210 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
212 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
213 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
214 hbld
.SHR(offset(shifted
, hbld
, i
),
215 stride(retype(brw_vec1_grf(1 + i
, 7),
216 BRW_REGISTER_TYPE_UB
),
218 brw_imm_v(0x76543210));
221 /* A set bit in the pixel mask means the channel is enabled, but
222 * that is the opposite of gl_HelperInvocation so we need to invert
225 * The negate source-modifier bit of logical instructions on Gen8+
226 * performs 1's complement negation, so we can use that instead of
229 fs_reg inverted
= negate(shifted
);
230 if (v
->devinfo
->gen
< 8) {
231 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
232 abld
.NOT(inverted
, shifted
);
235 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
236 * with 1 and negating.
238 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
239 abld
.AND(anded
, inverted
, brw_imm_uw(1));
241 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
242 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
256 fs_visitor::nir_emit_system_values()
258 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
259 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
260 nir_system_values
[i
] = fs_reg();
263 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
264 * never end up using it.
267 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
268 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
269 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
271 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
272 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
273 if (dispatch_width
> 8)
274 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
275 if (dispatch_width
> 16) {
276 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
277 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
281 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
282 nir_foreach_block(block
, impl
)
283 emit_system_values_block(block
, this);
287 * Returns a type based on a reference_type (word, float, half-float) and a
290 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
292 * @FIXME: 64-bit return types are always DF on integer types to maintain
293 * compability with uses of DF previously to the introduction of int64
297 brw_reg_type_from_bit_size(const unsigned bit_size
,
298 const brw_reg_type reference_type
)
300 switch(reference_type
) {
301 case BRW_REGISTER_TYPE_HF
:
302 case BRW_REGISTER_TYPE_F
:
303 case BRW_REGISTER_TYPE_DF
:
306 return BRW_REGISTER_TYPE_HF
;
308 return BRW_REGISTER_TYPE_F
;
310 return BRW_REGISTER_TYPE_DF
;
312 unreachable("Invalid bit size");
314 case BRW_REGISTER_TYPE_B
:
315 case BRW_REGISTER_TYPE_W
:
316 case BRW_REGISTER_TYPE_D
:
317 case BRW_REGISTER_TYPE_Q
:
320 return BRW_REGISTER_TYPE_B
;
322 return BRW_REGISTER_TYPE_W
;
324 return BRW_REGISTER_TYPE_D
;
326 return BRW_REGISTER_TYPE_Q
;
328 unreachable("Invalid bit size");
330 case BRW_REGISTER_TYPE_UB
:
331 case BRW_REGISTER_TYPE_UW
:
332 case BRW_REGISTER_TYPE_UD
:
333 case BRW_REGISTER_TYPE_UQ
:
336 return BRW_REGISTER_TYPE_UB
;
338 return BRW_REGISTER_TYPE_UW
;
340 return BRW_REGISTER_TYPE_UD
;
342 return BRW_REGISTER_TYPE_UQ
;
344 unreachable("Invalid bit size");
347 unreachable("Unknown type");
352 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
354 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
355 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
356 nir_locals
[i
] = fs_reg();
359 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
360 unsigned array_elems
=
361 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
362 unsigned size
= array_elems
* reg
->num_components
;
363 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
364 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
365 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
368 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
371 nir_emit_cf_list(&impl
->body
);
375 fs_visitor::nir_emit_cf_list(exec_list
*list
)
377 exec_list_validate(list
);
378 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
379 switch (node
->type
) {
381 nir_emit_if(nir_cf_node_as_if(node
));
384 case nir_cf_node_loop
:
385 nir_emit_loop(nir_cf_node_as_loop(node
));
388 case nir_cf_node_block
:
389 nir_emit_block(nir_cf_node_as_block(node
));
393 unreachable("Invalid CFG node block");
399 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
404 /* If the condition has the form !other_condition, use other_condition as
405 * the source, but invert the predicate on the if instruction.
407 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
408 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
409 assert(!cond
->src
[0].negate
);
410 assert(!cond
->src
[0].abs
);
413 cond_reg
= get_nir_src(cond
->src
[0].src
);
416 cond_reg
= get_nir_src(if_stmt
->condition
);
419 /* first, put the condition into f0 */
420 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
421 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
422 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
424 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
426 nir_emit_cf_list(&if_stmt
->then_list
);
428 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
429 bld
.emit(BRW_OPCODE_ELSE
);
430 nir_emit_cf_list(&if_stmt
->else_list
);
433 bld
.emit(BRW_OPCODE_ENDIF
);
435 if (devinfo
->gen
< 7)
436 limit_dispatch_width(16, "Non-uniform control flow unsupported "
441 fs_visitor::nir_emit_loop(nir_loop
*loop
)
443 bld
.emit(BRW_OPCODE_DO
);
445 nir_emit_cf_list(&loop
->body
);
447 bld
.emit(BRW_OPCODE_WHILE
);
449 if (devinfo
->gen
< 7)
450 limit_dispatch_width(16, "Non-uniform control flow unsupported "
455 fs_visitor::nir_emit_block(nir_block
*block
)
457 nir_foreach_instr(instr
, block
) {
458 nir_emit_instr(instr
);
463 fs_visitor::nir_emit_instr(nir_instr
*instr
)
465 const fs_builder abld
= bld
.annotate(NULL
, instr
);
467 switch (instr
->type
) {
468 case nir_instr_type_alu
:
469 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
472 case nir_instr_type_deref
:
473 unreachable("All derefs should've been lowered");
476 case nir_instr_type_intrinsic
:
478 case MESA_SHADER_VERTEX
:
479 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
481 case MESA_SHADER_TESS_CTRL
:
482 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
484 case MESA_SHADER_TESS_EVAL
:
485 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
487 case MESA_SHADER_GEOMETRY
:
488 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
490 case MESA_SHADER_FRAGMENT
:
491 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
493 case MESA_SHADER_COMPUTE
:
494 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
497 unreachable("unsupported shader stage");
501 case nir_instr_type_tex
:
502 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
505 case nir_instr_type_load_const
:
506 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
509 case nir_instr_type_ssa_undef
:
510 /* We create a new VGRF for undefs on every use (by handling
511 * them in get_nir_src()), rather than for each definition.
512 * This helps register coalescing eliminate MOVs from undef.
516 case nir_instr_type_jump
:
517 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
521 unreachable("unknown instruction type");
526 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
530 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
531 const fs_reg
&result
)
533 if (!instr
->src
[0].src
.is_ssa
||
534 !instr
->src
[0].src
.ssa
->parent_instr
)
537 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
540 nir_alu_instr
*src0
=
541 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
543 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
544 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
547 /* If either opcode has source modifiers, bail.
549 * TODO: We can potentially handle source modifiers if both of the opcodes
550 * we're combining are signed integers.
552 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
553 src0
->src
[0].abs
|| src0
->src
[0].negate
)
556 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
558 /* Element type to extract.*/
559 const brw_reg_type type
= brw_int_type(
560 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
561 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
563 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
564 op0
.type
= brw_type_for_nir_type(devinfo
,
565 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
566 nir_src_bit_size(src0
->src
[0].src
)));
567 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
569 set_saturate(instr
->dest
.saturate
,
570 bld
.MOV(result
, subscript(op0
, type
, element
)));
575 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
576 const fs_reg
&result
)
578 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
579 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
582 if (!nir_src_is_const(instr
->src
[1].src
) ||
583 !nir_src_is_const(instr
->src
[2].src
))
586 const float value1
= nir_src_as_float(instr
->src
[1].src
);
587 const float value2
= nir_src_as_float(instr
->src
[2].src
);
588 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
591 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
592 assert(value1
== -value2
);
594 fs_reg tmp
= vgrf(glsl_type::int_type
);
596 if (devinfo
->gen
>= 12) {
597 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
598 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
600 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
602 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
603 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
605 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
607 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
608 g1
, brw_imm_uw(0x3f80));
611 bld
.MOV(tmp
, negate(tmp
));
613 } else if (devinfo
->gen
>= 6) {
614 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
615 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
617 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
619 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
620 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
622 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
624 * This negation looks like it's safe in practice, because bits 0:4 will
625 * surely be TRIANGLES
628 if (value1
== -1.0f
) {
632 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
633 g0
, brw_imm_uw(0x3f80));
635 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
636 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
638 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
640 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
641 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
643 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
645 * This negation looks like it's safe in practice, because bits 0:4 will
646 * surely be TRIANGLES
649 if (value1
== -1.0f
) {
653 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
655 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
661 emit_find_msb_using_lzd(const fs_builder
&bld
,
662 const fs_reg
&result
,
670 /* LZD of an absolute value source almost always does the right
671 * thing. There are two problem values:
673 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
674 * 0. However, findMSB(int(0x80000000)) == 30.
676 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
677 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
679 * For a value of zero or negative one, -1 will be returned.
681 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
682 * findMSB(-(1<<x)) should return x-1.
684 * For all negative number cases, including 0x80000000 and
685 * 0xffffffff, the correct value is obtained from LZD if instead of
686 * negating the (already negative) value the logical-not is used. A
687 * conditonal logical-not can be achieved in two instructions.
689 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
691 bld
.ASR(temp
, src
, brw_imm_d(31));
692 bld
.XOR(temp
, temp
, src
);
695 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
696 retype(temp
, BRW_REGISTER_TYPE_UD
));
698 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
699 * from the LSB side. Subtract the result from 31 to convert the MSB
700 * count into an LSB count. If no bits are set, LZD will return 32.
701 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
703 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
704 inst
->src
[0].negate
= true;
708 brw_rnd_mode_from_nir_op (const nir_op op
) {
710 case nir_op_f2f16_rtz
:
711 return BRW_RND_MODE_RTZ
;
712 case nir_op_f2f16_rtne
:
713 return BRW_RND_MODE_RTNE
;
715 unreachable("Operation doesn't support rounding mode");
720 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
722 if (nir_has_any_rounding_mode_rtne(execution_mode
))
723 return BRW_RND_MODE_RTNE
;
724 if (nir_has_any_rounding_mode_rtz(execution_mode
))
725 return BRW_RND_MODE_RTZ
;
726 return BRW_RND_MODE_UNSPECIFIED
;
730 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
731 nir_alu_instr
*instr
,
736 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
738 result
.type
= brw_type_for_nir_type(devinfo
,
739 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
740 nir_dest_bit_size(instr
->dest
.dest
)));
742 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
743 op
[i
] = get_nir_src(instr
->src
[i
].src
);
744 op
[i
].type
= brw_type_for_nir_type(devinfo
,
745 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
746 nir_src_bit_size(instr
->src
[i
].src
)));
747 op
[i
].abs
= instr
->src
[i
].abs
;
748 op
[i
].negate
= instr
->src
[i
].negate
;
751 /* Move and vecN instrutions may still be vectored. Return the raw,
752 * vectored source and destination so that fs_visitor::nir_emit_alu can
753 * handle it. Other callers should not have to handle these kinds of
766 /* At this point, we have dealt with any instruction that operates on
767 * more than a single channel. Therefore, we can just adjust the source
768 * and destination registers for that channel and emit the instruction.
770 unsigned channel
= 0;
771 if (nir_op_infos
[instr
->op
].output_size
== 0) {
772 /* Since NIR is doing the scalarizing for us, we should only ever see
773 * vectorized operations with a single channel.
775 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
776 channel
= ffs(instr
->dest
.write_mask
) - 1;
778 result
= offset(result
, bld
, channel
);
781 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
782 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
783 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
790 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
793 for (unsigned i
= 0; i
< 2; i
++) {
794 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
796 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
797 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
798 /* The source of the inot is now the source of instr. */
799 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
801 assert(!op
[i
].negate
);
804 op
[i
] = resolve_source_modifiers(op
[i
]);
810 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
812 nir_alu_instr
*instr
)
814 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
817 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
819 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
822 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
823 * of valid size-changing combinations is a bit more complex.
825 * The source restriction is just because I was lazy about generating the
828 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
829 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
832 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
833 * this is float(1 + a).
837 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
839 /* Ignore the saturate modifier, if there is one. The result of the
840 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
842 bld
.ADD(result
, op
, brw_imm_d(1));
848 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
850 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
851 * the source of \c instr that is a \c nir_op_fsign.
854 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
855 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
859 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
860 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
862 if (instr
->op
!= nir_op_fsign
) {
863 const nir_alu_instr
*const fsign_instr
=
864 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
866 assert(!fsign_instr
->dest
.saturate
);
868 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
869 * fsign_src] has the other multiply source. This must be rearranged so
870 * that op[0] is the source of the fsign op[1] is the other multiply
876 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
878 const nir_alu_type t
=
879 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
880 nir_src_bit_size(fsign_instr
->src
[0].src
));
882 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
883 op
[0].abs
= fsign_instr
->src
[0].abs
;
884 op
[0].negate
= fsign_instr
->src
[0].negate
;
886 unsigned channel
= 0;
887 if (nir_op_infos
[instr
->op
].output_size
== 0) {
888 /* Since NIR is doing the scalarizing for us, we should only ever see
889 * vectorized operations with a single channel.
891 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
892 channel
= ffs(instr
->dest
.write_mask
) - 1;
895 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
897 /* Resolve any source modifiers. We could do slightly better on Gen8+
898 * if the only source modifier is negation, but *shrug*.
900 if (op
[1].negate
|| op
[1].abs
) {
901 fs_reg tmp
= bld
.vgrf(op
[1].type
);
907 assert(!instr
->dest
.saturate
);
911 /* Straightforward since the source can be assumed to be either strictly
912 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
914 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
916 if (instr
->op
== nir_op_fsign
) {
917 inst
= (op
[0].negate
)
918 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
919 : bld
.MOV(result
, brw_imm_f(1.0f
));
921 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
922 inst
= bld
.MOV(result
, op
[1]);
925 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
926 } else if (type_sz(op
[0].type
) == 2) {
927 /* AND(val, 0x8000) gives the sign bit.
929 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
931 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
932 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
934 op
[0].type
= BRW_REGISTER_TYPE_UW
;
935 result
.type
= BRW_REGISTER_TYPE_UW
;
936 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
938 if (instr
->op
== nir_op_fsign
)
939 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
941 /* Use XOR here to get the result sign correct. */
942 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
945 inst
->predicate
= BRW_PREDICATE_NORMAL
;
946 } else if (type_sz(op
[0].type
) == 4) {
947 /* AND(val, 0x80000000) gives the sign bit.
949 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
952 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
954 op
[0].type
= BRW_REGISTER_TYPE_UD
;
955 result
.type
= BRW_REGISTER_TYPE_UD
;
956 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
958 if (instr
->op
== nir_op_fsign
)
959 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
961 /* Use XOR here to get the result sign correct. */
962 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
965 inst
->predicate
= BRW_PREDICATE_NORMAL
;
967 /* For doubles we do the same but we need to consider:
969 * - 2-src instructions can't operate with 64-bit immediates
970 * - The sign is encoded in the high 32-bit of each DF
971 * - We need to produce a DF result.
974 fs_reg zero
= vgrf(glsl_type::double_type
);
975 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
976 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
978 bld
.MOV(result
, zero
);
980 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
981 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
982 brw_imm_ud(0x80000000u
));
984 if (instr
->op
== nir_op_fsign
) {
985 set_predicate(BRW_PREDICATE_NORMAL
,
986 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
988 /* This could be done better in some cases. If the scale is an
989 * immediate with the low 32-bits all 0, emitting a separate XOR and
990 * OR would allow an algebraic optimization to remove the OR. There
991 * are currently zero instances of fsign(double(x))*IMM in shader-db
992 * or any test suite, so it is hard to care at this time.
994 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
995 inst
= bld
.XOR(result_int64
, result_int64
,
996 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
1002 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
1004 * Checks the operands of a \c nir_op_fmul to determine whether or not
1005 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
1007 * \param instr The multiplication instruction
1009 * \param fsign_src The source of \c instr that may or may not be a
1013 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
1015 assert(instr
->op
== nir_op_fmul
);
1017 nir_alu_instr
*const fsign_instr
=
1018 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
1022 * 1. instr->src[fsign_src] must be a nir_op_fsign.
1023 * 2. The nir_op_fsign can only be used by this multiplication.
1024 * 3. The source that is the nir_op_fsign does not have source modifiers.
1025 * \c emit_fsign only examines the source modifiers of the source of the
1028 * The nir_op_fsign must also not have the saturate modifier, but steps
1029 * have already been taken (in nir_opt_algebraic) to ensure that.
1031 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
1032 is_used_once(fsign_instr
) &&
1033 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
1037 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1040 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1042 unsigned execution_mode
=
1043 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1046 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1048 switch (instr
->op
) {
1053 fs_reg temp
= result
;
1054 bool need_extra_copy
= false;
1055 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1056 if (!instr
->src
[i
].src
.is_ssa
&&
1057 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1058 need_extra_copy
= true;
1059 temp
= bld
.vgrf(result
.type
, 4);
1064 for (unsigned i
= 0; i
< 4; i
++) {
1065 if (!(instr
->dest
.write_mask
& (1 << i
)))
1068 if (instr
->op
== nir_op_mov
) {
1069 inst
= bld
.MOV(offset(temp
, bld
, i
),
1070 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1072 inst
= bld
.MOV(offset(temp
, bld
, i
),
1073 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1075 inst
->saturate
= instr
->dest
.saturate
;
1078 /* In this case the source and destination registers were the same,
1079 * so we need to insert an extra set of moves in order to deal with
1082 if (need_extra_copy
) {
1083 for (unsigned i
= 0; i
< 4; i
++) {
1084 if (!(instr
->dest
.write_mask
& (1 << i
)))
1087 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1095 if (optimize_extract_to_float(instr
, result
))
1097 inst
= bld
.MOV(result
, op
[0]);
1098 inst
->saturate
= instr
->dest
.saturate
;
1101 case nir_op_f2f16_rtne
:
1102 case nir_op_f2f16_rtz
:
1103 case nir_op_f2f16
: {
1104 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1106 if (nir_op_f2f16
== instr
->op
)
1107 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1109 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1111 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1112 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1114 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1115 * on the HW gen, it is a special hw opcode or just a MOV, and
1116 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1118 * But if we want to use that opcode, we need to provide support on
1119 * different optimizations and lowerings. As right now HF support is
1120 * only for gen8+, it will be better to use directly the MOV, and use
1121 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1123 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1124 inst
= bld
.MOV(result
, op
[0]);
1125 inst
->saturate
= instr
->dest
.saturate
;
1136 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1138 op
[0].type
= BRW_REGISTER_TYPE_D
;
1139 op
[0].negate
= !op
[0].negate
;
1162 if (result
.type
== BRW_REGISTER_TYPE_B
||
1163 result
.type
== BRW_REGISTER_TYPE_UB
||
1164 result
.type
== BRW_REGISTER_TYPE_HF
)
1165 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1167 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1168 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1169 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1170 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1172 inst
= bld
.MOV(result
, op
[0]);
1173 inst
->saturate
= instr
->dest
.saturate
;
1177 inst
= bld
.MOV(result
, op
[0]);
1178 inst
->saturate
= true;
1183 op
[0].negate
= true;
1184 inst
= bld
.MOV(result
, op
[0]);
1185 if (instr
->op
== nir_op_fneg
)
1186 inst
->saturate
= instr
->dest
.saturate
;
1191 op
[0].negate
= false;
1193 inst
= bld
.MOV(result
, op
[0]);
1194 if (instr
->op
== nir_op_fabs
)
1195 inst
->saturate
= instr
->dest
.saturate
;
1199 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1201 brw_rnd_mode_from_execution_mode(execution_mode
);
1202 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1206 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1207 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1209 inst
= bld
.MOV(result
, op
[0]);
1210 inst
->saturate
= instr
->dest
.saturate
;
1214 emit_fsign(bld
, instr
, result
, op
, 0);
1218 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1219 inst
->saturate
= instr
->dest
.saturate
;
1223 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1224 inst
->saturate
= instr
->dest
.saturate
;
1228 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1229 inst
->saturate
= instr
->dest
.saturate
;
1233 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1234 inst
->saturate
= instr
->dest
.saturate
;
1238 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1239 inst
->saturate
= instr
->dest
.saturate
;
1243 if (fs_key
->high_quality_derivatives
) {
1244 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1246 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1248 inst
->saturate
= instr
->dest
.saturate
;
1250 case nir_op_fddx_fine
:
1251 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1252 inst
->saturate
= instr
->dest
.saturate
;
1254 case nir_op_fddx_coarse
:
1255 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1256 inst
->saturate
= instr
->dest
.saturate
;
1259 if (fs_key
->high_quality_derivatives
) {
1260 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1262 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1264 inst
->saturate
= instr
->dest
.saturate
;
1266 case nir_op_fddy_fine
:
1267 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1268 inst
->saturate
= instr
->dest
.saturate
;
1270 case nir_op_fddy_coarse
:
1271 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1272 inst
->saturate
= instr
->dest
.saturate
;
1276 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1278 brw_rnd_mode_from_execution_mode(execution_mode
);
1279 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1284 inst
= bld
.ADD(result
, op
[0], op
[1]);
1285 inst
->saturate
= instr
->dest
.saturate
;
1288 case nir_op_iadd_sat
:
1289 case nir_op_uadd_sat
:
1290 inst
= bld
.ADD(result
, op
[0], op
[1]);
1291 inst
->saturate
= true;
1294 case nir_op_isub_sat
:
1295 bld
.emit(SHADER_OPCODE_ISUB_SAT
, result
, op
[0], op
[1]);
1298 case nir_op_usub_sat
:
1299 bld
.emit(SHADER_OPCODE_USUB_SAT
, result
, op
[0], op
[1]);
1304 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1305 inst
= bld
.AVG(result
, op
[0], op
[1]);
1309 case nir_op_uhadd
: {
1310 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1311 fs_reg tmp
= bld
.vgrf(result
.type
);
1313 if (devinfo
->gen
>= 8) {
1314 op
[0] = resolve_source_modifiers(op
[0]);
1315 op
[1] = resolve_source_modifiers(op
[1]);
1318 /* AVG(x, y) - ((x ^ y) & 1) */
1319 bld
.XOR(tmp
, op
[0], op
[1]);
1320 bld
.AND(tmp
, tmp
, retype(brw_imm_ud(1), result
.type
));
1321 bld
.AVG(result
, op
[0], op
[1]);
1322 inst
= bld
.ADD(result
, result
, tmp
);
1323 inst
->src
[1].negate
= true;
1328 for (unsigned i
= 0; i
< 2; i
++) {
1329 if (can_fuse_fmul_fsign(instr
, i
)) {
1330 emit_fsign(bld
, instr
, result
, op
, i
);
1335 /* We emit the rounding mode after the previous fsign optimization since
1336 * it won't result in a MUL, but will try to negate the value by other
1339 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1341 brw_rnd_mode_from_execution_mode(execution_mode
);
1342 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1346 inst
= bld
.MUL(result
, op
[0], op
[1]);
1347 inst
->saturate
= instr
->dest
.saturate
;
1350 case nir_op_imul_2x32_64
:
1351 case nir_op_umul_2x32_64
:
1352 bld
.MUL(result
, op
[0], op
[1]);
1355 case nir_op_imul_32x16
:
1356 case nir_op_umul_32x16
: {
1357 const bool ud
= instr
->op
== nir_op_umul_32x16
;
1359 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1361 /* Before Gen7, the order of the 32-bit source and the 16-bit source was
1362 * swapped. The extension isn't enabled on those platforms, so don't
1363 * pretend to support the differences.
1365 assert(devinfo
->gen
>= 7);
1367 if (op
[1].file
== IMM
)
1368 op
[1] = ud
? brw_imm_uw(op
[1].ud
) : brw_imm_w(op
[1].d
);
1370 const enum brw_reg_type word_type
=
1371 ud
? BRW_REGISTER_TYPE_UW
: BRW_REGISTER_TYPE_W
;
1373 op
[1] = subscript(op
[1], word_type
, 0);
1376 const enum brw_reg_type dword_type
=
1377 ud
? BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_D
;
1379 bld
.MUL(result
, retype(op
[0], dword_type
), op
[1]);
1384 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1385 bld
.MUL(result
, op
[0], op
[1]);
1388 case nir_op_imul_high
:
1389 case nir_op_umul_high
:
1390 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1391 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1396 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1397 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1400 case nir_op_uadd_carry
:
1401 unreachable("Should have been lowered by carry_to_arith().");
1403 case nir_op_usub_borrow
:
1404 unreachable("Should have been lowered by borrow_to_arith().");
1408 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1409 * appears that our hardware just does the right thing for signed
1412 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1413 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1417 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1418 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1420 /* Math instructions don't support conditional mod */
1421 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1422 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1424 /* Now, we need to determine if signs of the sources are different.
1425 * When we XOR the sources, the top bit is 0 if they are the same and 1
1426 * if they are different. We can then use a conditional modifier to
1427 * turn that into a predicate. This leads us to an XOR.l instruction.
1429 * Technically, according to the PRM, you're not allowed to use .l on a
1430 * XOR instruction. However, emperical experiments and Curro's reading
1431 * of the simulator source both indicate that it's safe.
1433 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1434 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1435 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1436 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1438 /* If the result of the initial remainder operation is non-zero and the
1439 * two sources have different signs, add in a copy of op[1] to get the
1440 * final integer modulus value.
1442 inst
= bld
.ADD(result
, result
, op
[1]);
1443 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1450 case nir_op_fne32
: {
1451 fs_reg dest
= result
;
1453 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1455 dest
= bld
.vgrf(op
[0].type
, 1);
1457 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1459 if (bit_size
> 32) {
1460 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1461 } else if(bit_size
< 32) {
1462 /* When we convert the result to 32-bit we need to be careful and do
1463 * it as a signed conversion to get sign extension (for 32-bit true)
1465 const brw_reg_type src_type
=
1466 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1468 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1478 case nir_op_ine32
: {
1479 fs_reg dest
= result
;
1481 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1482 * type. So we convert both operands for the comparison.
1485 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1486 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1488 const uint32_t bit_size
= type_sz(temp_op
[0].type
) * 8;
1490 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1492 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1493 brw_cmod_for_nir_comparison(instr
->op
));
1495 if (bit_size
> 32) {
1496 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1497 } else if (bit_size
< 32) {
1498 /* When we convert the result to 32-bit we need to be careful and do
1499 * it as a signed conversion to get sign extension (for 32-bit true)
1501 const brw_reg_type src_type
=
1502 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1504 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1510 if (devinfo
->gen
>= 8) {
1511 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1513 if (inot_src_instr
!= NULL
&&
1514 (inot_src_instr
->op
== nir_op_ior
||
1515 inot_src_instr
->op
== nir_op_ixor
||
1516 inot_src_instr
->op
== nir_op_iand
) &&
1517 !inot_src_instr
->src
[0].abs
&&
1518 !inot_src_instr
->src
[0].negate
&&
1519 !inot_src_instr
->src
[1].abs
&&
1520 !inot_src_instr
->src
[1].negate
) {
1521 /* The sources of the source logical instruction are now the
1522 * sources of the instruction that will be generated.
1524 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1525 resolve_inot_sources(bld
, inot_src_instr
, op
);
1527 /* Smash all of the sources and destination to be signed. This
1528 * doesn't matter for the operation of the instruction, but cmod
1529 * propagation fails on unsigned sources with negation (due to
1530 * fs_inst::can_do_cmod returning false).
1533 brw_type_for_nir_type(devinfo
,
1534 (nir_alu_type
)(nir_type_int
|
1535 nir_dest_bit_size(instr
->dest
.dest
)));
1537 brw_type_for_nir_type(devinfo
,
1538 (nir_alu_type
)(nir_type_int
|
1539 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1541 brw_type_for_nir_type(devinfo
,
1542 (nir_alu_type
)(nir_type_int
|
1543 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1545 /* For XOR, only invert one of the sources. Arbitrarily choose
1548 op
[0].negate
= !op
[0].negate
;
1549 if (inot_src_instr
->op
!= nir_op_ixor
)
1550 op
[1].negate
= !op
[1].negate
;
1552 switch (inot_src_instr
->op
) {
1554 bld
.AND(result
, op
[0], op
[1]);
1558 bld
.OR(result
, op
[0], op
[1]);
1562 bld
.XOR(result
, op
[0], op
[1]);
1566 unreachable("impossible opcode");
1569 op
[0] = resolve_source_modifiers(op
[0]);
1571 bld
.NOT(result
, op
[0]);
1574 if (devinfo
->gen
>= 8) {
1575 resolve_inot_sources(bld
, instr
, op
);
1577 bld
.XOR(result
, op
[0], op
[1]);
1580 if (devinfo
->gen
>= 8) {
1581 resolve_inot_sources(bld
, instr
, op
);
1583 bld
.OR(result
, op
[0], op
[1]);
1586 if (devinfo
->gen
>= 8) {
1587 resolve_inot_sources(bld
, instr
, op
);
1589 bld
.AND(result
, op
[0], op
[1]);
1595 case nir_op_b32all_fequal2
:
1596 case nir_op_b32all_iequal2
:
1597 case nir_op_b32all_fequal3
:
1598 case nir_op_b32all_iequal3
:
1599 case nir_op_b32all_fequal4
:
1600 case nir_op_b32all_iequal4
:
1601 case nir_op_b32any_fnequal2
:
1602 case nir_op_b32any_inequal2
:
1603 case nir_op_b32any_fnequal3
:
1604 case nir_op_b32any_inequal3
:
1605 case nir_op_b32any_fnequal4
:
1606 case nir_op_b32any_inequal4
:
1607 unreachable("Lowered by nir_lower_alu_reductions");
1610 unreachable("not reached: should be handled by ldexp_to_arith()");
1613 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1614 inst
->saturate
= instr
->dest
.saturate
;
1618 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1619 inst
->saturate
= instr
->dest
.saturate
;
1623 case nir_op_f2b32
: {
1624 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1625 if (bit_size
== 64) {
1626 /* two-argument instructions can't take 64-bit immediates */
1630 if (instr
->op
== nir_op_f2b32
) {
1631 zero
= vgrf(glsl_type::double_type
);
1632 tmp
= vgrf(glsl_type::double_type
);
1633 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1635 zero
= vgrf(glsl_type::int64_t_type
);
1636 tmp
= vgrf(glsl_type::int64_t_type
);
1637 bld
.MOV(zero
, brw_imm_q(0));
1640 /* A SIMD16 execution needs to be split in two instructions, so use
1641 * a vgrf instead of the flag register as dst so instruction splitting
1644 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1645 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1648 if (bit_size
== 32) {
1649 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1651 assert(bit_size
== 16);
1652 zero
= instr
->op
== nir_op_f2b32
?
1653 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1655 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1661 inst
= bld
.RNDZ(result
, op
[0]);
1662 if (devinfo
->gen
< 6) {
1663 set_condmod(BRW_CONDITIONAL_R
, inst
);
1664 set_predicate(BRW_PREDICATE_NORMAL
,
1665 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1666 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1668 inst
->saturate
= instr
->dest
.saturate
;
1671 case nir_op_fceil
: {
1672 op
[0].negate
= !op
[0].negate
;
1673 fs_reg temp
= vgrf(glsl_type::float_type
);
1674 bld
.RNDD(temp
, op
[0]);
1676 inst
= bld
.MOV(result
, temp
);
1677 inst
->saturate
= instr
->dest
.saturate
;
1681 inst
= bld
.RNDD(result
, op
[0]);
1682 inst
->saturate
= instr
->dest
.saturate
;
1685 inst
= bld
.FRC(result
, op
[0]);
1686 inst
->saturate
= instr
->dest
.saturate
;
1688 case nir_op_fround_even
:
1689 inst
= bld
.RNDE(result
, op
[0]);
1690 if (devinfo
->gen
< 6) {
1691 set_condmod(BRW_CONDITIONAL_R
, inst
);
1692 set_predicate(BRW_PREDICATE_NORMAL
,
1693 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1694 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1696 inst
->saturate
= instr
->dest
.saturate
;
1699 case nir_op_fquantize2f16
: {
1700 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1701 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1702 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1704 /* The destination stride must be at least as big as the source stride. */
1705 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1708 /* Check for denormal */
1709 fs_reg abs_src0
= op
[0];
1710 abs_src0
.abs
= true;
1711 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1713 /* Get the appropriately signed zero */
1714 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1715 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1716 brw_imm_ud(0x80000000));
1717 /* Do the actual F32 -> F16 -> F32 conversion */
1718 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1719 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1720 /* Select that or zero based on normal status */
1721 inst
= bld
.SEL(result
, zero
, tmp32
);
1722 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1723 inst
->saturate
= instr
->dest
.saturate
;
1730 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1731 inst
->saturate
= instr
->dest
.saturate
;
1737 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1738 inst
->saturate
= instr
->dest
.saturate
;
1741 case nir_op_pack_snorm_2x16
:
1742 case nir_op_pack_snorm_4x8
:
1743 case nir_op_pack_unorm_2x16
:
1744 case nir_op_pack_unorm_4x8
:
1745 case nir_op_unpack_snorm_2x16
:
1746 case nir_op_unpack_snorm_4x8
:
1747 case nir_op_unpack_unorm_2x16
:
1748 case nir_op_unpack_unorm_4x8
:
1749 case nir_op_unpack_half_2x16
:
1750 case nir_op_pack_half_2x16
:
1751 unreachable("not reached: should be handled by lower_packing_builtins");
1753 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1754 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1756 case nir_op_unpack_half_2x16_split_x
:
1757 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1758 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1759 inst
->saturate
= instr
->dest
.saturate
;
1762 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1763 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1765 case nir_op_unpack_half_2x16_split_y
:
1766 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1767 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1768 inst
->saturate
= instr
->dest
.saturate
;
1771 case nir_op_pack_64_2x32_split
:
1772 case nir_op_pack_32_2x16_split
:
1773 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1776 case nir_op_unpack_64_2x32_split_x
:
1777 case nir_op_unpack_64_2x32_split_y
: {
1778 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1779 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1781 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1785 case nir_op_unpack_32_2x16_split_x
:
1786 case nir_op_unpack_32_2x16_split_y
: {
1787 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1788 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1790 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1795 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1796 inst
->saturate
= instr
->dest
.saturate
;
1799 case nir_op_bitfield_reverse
:
1800 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1801 bld
.BFREV(result
, op
[0]);
1804 case nir_op_bit_count
:
1805 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1806 bld
.CBIT(result
, op
[0]);
1809 case nir_op_ufind_msb
: {
1810 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1811 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1816 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1817 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1820 case nir_op_ifind_msb
: {
1821 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1823 if (devinfo
->gen
< 7) {
1824 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1826 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1828 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1829 * count from the LSB side. If FBH didn't return an error
1830 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1831 * count into an LSB count.
1833 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1835 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1836 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1837 inst
->src
[0].negate
= true;
1842 case nir_op_find_lsb
:
1843 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1845 if (devinfo
->gen
< 7) {
1846 fs_reg temp
= vgrf(glsl_type::int_type
);
1848 /* (x & -x) generates a value that consists of only the LSB of x.
1849 * For all powers of 2, findMSB(y) == findLSB(y).
1851 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1852 fs_reg negated_src
= src
;
1854 /* One must be negated, and the other must be non-negated. It
1855 * doesn't matter which is which.
1857 negated_src
.negate
= true;
1860 bld
.AND(temp
, src
, negated_src
);
1861 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1863 bld
.FBL(result
, op
[0]);
1867 case nir_op_ubitfield_extract
:
1868 case nir_op_ibitfield_extract
:
1869 unreachable("should have been lowered");
1872 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1873 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1876 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1877 bld
.BFI1(result
, op
[0], op
[1]);
1880 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1881 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1884 case nir_op_bitfield_insert
:
1885 unreachable("not reached: should have been lowered");
1888 bld
.SHL(result
, op
[0], op
[1]);
1891 bld
.ASR(result
, op
[0], op
[1]);
1894 bld
.SHR(result
, op
[0], op
[1]);
1898 bld
.ROL(result
, op
[0], op
[1]);
1901 bld
.ROR(result
, op
[0], op
[1]);
1904 case nir_op_pack_half_2x16_split
:
1905 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1909 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1911 brw_rnd_mode_from_execution_mode(execution_mode
);
1912 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1916 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1917 inst
->saturate
= instr
->dest
.saturate
;
1921 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1923 brw_rnd_mode_from_execution_mode(execution_mode
);
1924 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1928 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1929 inst
->saturate
= instr
->dest
.saturate
;
1932 case nir_op_b32csel
:
1933 if (optimize_frontfacing_ternary(instr
, result
))
1936 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1937 inst
= bld
.SEL(result
, op
[1], op
[2]);
1938 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1941 case nir_op_extract_u8
:
1942 case nir_op_extract_i8
: {
1943 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1948 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1949 * Use two instructions and a word or DWord intermediate integer type.
1951 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1952 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1954 if (instr
->op
== nir_op_extract_i8
) {
1955 /* If we need to sign extend, extract to a word first */
1956 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1957 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1958 bld
.MOV(result
, w_temp
);
1959 } else if (byte
& 1) {
1960 /* Extract the high byte from the word containing the desired byte
1964 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1967 /* Otherwise use an AND with 0xff and a word type */
1969 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1973 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1974 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1979 case nir_op_extract_u16
:
1980 case nir_op_extract_i16
: {
1981 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1982 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1983 bld
.MOV(result
, subscript(op
[0], type
, word
));
1988 unreachable("unhandled instruction");
1991 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1992 * to sign extend the low bit to 0/~0
1994 if (devinfo
->gen
<= 5 &&
1995 !result
.is_null() &&
1996 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1997 fs_reg masked
= vgrf(glsl_type::int_type
);
1998 bld
.AND(masked
, result
, brw_imm_d(1));
1999 masked
.negate
= true;
2000 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
2005 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
2006 nir_load_const_instr
*instr
)
2008 const brw_reg_type reg_type
=
2009 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
2010 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
2012 switch (instr
->def
.bit_size
) {
2014 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2015 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
2019 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2020 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
2024 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2025 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
2029 assert(devinfo
->gen
>= 7);
2030 if (devinfo
->gen
== 7) {
2031 /* We don't get 64-bit integer types until gen8 */
2032 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
2033 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
2034 setup_imm_df(bld
, instr
->value
[i
].f64
));
2037 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
2038 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
2043 unreachable("Invalid bit size");
2046 nir_ssa_values
[instr
->def
.index
] = reg
;
2050 fs_visitor::get_nir_src(const nir_src
&src
)
2054 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
2055 const brw_reg_type reg_type
=
2056 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
2057 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
2059 reg
= nir_ssa_values
[src
.ssa
->index
];
2062 /* We don't handle indirects on locals */
2063 assert(src
.reg
.indirect
== NULL
);
2064 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
2065 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
2068 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
2069 /* The only 64-bit type available on gen7 is DF, so use that. */
2070 reg
.type
= BRW_REGISTER_TYPE_DF
;
2072 /* To avoid floating-point denorm flushing problems, set the type by
2073 * default to an integer type - instructions that need floating point
2074 * semantics will set this to F if they need to
2076 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
2077 BRW_REGISTER_TYPE_D
);
2084 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2086 * This function should not be called on any value which may be 64 bits.
2087 * We could theoretically support 64-bit on gen8+ but we choose not to
2088 * because it wouldn't work in general (no gen7 support) and there are
2089 * enough restrictions in 64-bit immediates that you can't take the return
2090 * value and treat it the same as the result of get_nir_src().
2093 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2095 assert(nir_src_bit_size(src
) == 32);
2096 return nir_src_is_const(src
) ?
2097 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2101 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2104 const brw_reg_type reg_type
=
2105 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2106 dest
.ssa
.bit_size
== 8 ?
2107 BRW_REGISTER_TYPE_D
:
2108 BRW_REGISTER_TYPE_F
);
2109 nir_ssa_values
[dest
.ssa
.index
] =
2110 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2111 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2112 return nir_ssa_values
[dest
.ssa
.index
];
2114 /* We don't handle indirects on locals */
2115 assert(dest
.reg
.indirect
== NULL
);
2116 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2117 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2122 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2125 for (unsigned i
= 0; i
< 4; i
++) {
2126 if (!((wr_mask
>> i
) & 1))
2129 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2130 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2131 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2132 if (new_inst
->src
[j
].file
== VGRF
)
2133 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2140 emit_pixel_interpolater_send(const fs_builder
&bld
,
2145 glsl_interp_mode interpolation
)
2147 struct brw_wm_prog_data
*wm_prog_data
=
2148 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2150 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2151 /* 2 floats per slot returned */
2152 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2153 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2155 wm_prog_data
->pulls_bary
= true;
2161 * Computes 1 << x, given a D/UD register containing some value x.
2164 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2166 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2168 fs_reg result
= bld
.vgrf(x
.type
, 1);
2169 fs_reg one
= bld
.vgrf(x
.type
, 1);
2171 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2172 bld
.SHL(result
, one
, x
);
2177 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2179 assert(stage
== MESA_SHADER_GEOMETRY
);
2181 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2183 if (gs_compile
->control_data_header_size_bits
== 0)
2186 /* We can only do EndPrimitive() functionality when the control data
2187 * consists of cut bits. Fortunately, the only time it isn't is when the
2188 * output type is points, in which case EndPrimitive() is a no-op.
2190 if (gs_prog_data
->control_data_format
!=
2191 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2195 /* Cut bits use one bit per vertex. */
2196 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2198 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2199 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2201 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2202 * vertex n, 0 otherwise. So all we need to do here is mark bit
2203 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2204 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2205 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2207 * Note that if EndPrimitive() is called before emitting any vertices, this
2208 * will cause us to set bit 31 of the control_data_bits register to 1.
2209 * That's fine because:
2211 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2212 * output, so the hardware will ignore cut bit 31.
2214 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2215 * last vertex, so setting cut bit 31 has no effect (since the primitive
2216 * is automatically ended when the GS terminates).
2218 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2219 * control_data_bits register to 0 when the first vertex is emitted.
2222 const fs_builder abld
= bld
.annotate("end primitive");
2224 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2225 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2226 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2227 fs_reg mask
= intexp2(abld
, prev_count
);
2228 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2229 * attention to the lower 5 bits of its second source argument, so on this
2230 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2231 * ((vertex_count - 1) % 32).
2233 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2237 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2239 assert(stage
== MESA_SHADER_GEOMETRY
);
2240 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2242 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2244 const fs_builder abld
= bld
.annotate("emit control data bits");
2245 const fs_builder fwa_bld
= bld
.exec_all();
2247 /* We use a single UD register to accumulate control data bits (32 bits
2248 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2251 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2252 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2253 * use the Channel Mask phase to enable/disable which DWord within that
2254 * group to write. (Remember, different SIMD8 channels may have emitted
2255 * different numbers of vertices, so we may need per-slot offsets.)
2257 * Channel masking presents an annoying problem: we may have to replicate
2258 * the data up to 4 times:
2260 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2262 * To avoid penalizing shaders that emit a small number of vertices, we
2263 * can avoid these sometimes: if the size of the control data header is
2264 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2265 * land in the same 128-bit group, so we can skip per-slot offsets.
2267 * Similarly, if the control data header is <= 32 bits, there is only one
2268 * DWord, so we can skip channel masks.
2270 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2272 fs_reg channel_mask
, per_slot_offset
;
2274 if (gs_compile
->control_data_header_size_bits
> 32) {
2275 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2276 channel_mask
= vgrf(glsl_type::uint_type
);
2279 if (gs_compile
->control_data_header_size_bits
> 128) {
2280 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2281 per_slot_offset
= vgrf(glsl_type::uint_type
);
2284 /* Figure out which DWord we're trying to write to using the formula:
2286 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2288 * Since bits_per_vertex is a power of two, and is known at compile
2289 * time, this can be optimized to:
2291 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2293 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2294 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2295 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2296 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2297 unsigned log2_bits_per_vertex
=
2298 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2299 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2301 if (per_slot_offset
.file
!= BAD_FILE
) {
2302 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2303 * the appropriate OWord within the control data header.
2305 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2308 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2309 * write to the appropriate DWORD within the OWORD.
2311 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2312 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2313 channel_mask
= intexp2(fwa_bld
, channel
);
2314 /* Then the channel masks need to be in bits 23:16. */
2315 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2318 /* Store the control data bits in the message payload and send it. */
2320 if (channel_mask
.file
!= BAD_FILE
)
2321 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2322 if (per_slot_offset
.file
!= BAD_FILE
)
2325 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2326 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2328 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2329 if (per_slot_offset
.file
!= BAD_FILE
)
2330 sources
[i
++] = per_slot_offset
;
2331 if (channel_mask
.file
!= BAD_FILE
)
2332 sources
[i
++] = channel_mask
;
2334 sources
[i
++] = this->control_data_bits
;
2337 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2338 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2340 /* We need to increment Global Offset by 256-bits to make room for
2341 * Broadwell's extra "Vertex Count" payload at the beginning of the
2342 * URB entry. Since this is an OWord message, Global Offset is counted
2343 * in 128-bit units, so we must set it to 2.
2345 if (gs_prog_data
->static_vertex_count
== -1)
2350 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2353 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2355 /* Note: we are calling this *before* increasing vertex_count, so
2356 * this->vertex_count == vertex_count - 1 in the formula above.
2359 /* Stream mode uses 2 bits per vertex */
2360 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2362 /* Must be a valid stream */
2363 assert(stream_id
< MAX_VERTEX_STREAMS
);
2365 /* Control data bits are initialized to 0 so we don't have to set any
2366 * bits when sending vertices to stream 0.
2371 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2373 /* reg::sid = stream_id */
2374 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2375 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2377 /* reg:shift_count = 2 * (vertex_count - 1) */
2378 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2379 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2381 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2382 * attention to the lower 5 bits of its second source argument, so on this
2383 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2384 * stream_id << ((2 * (vertex_count - 1)) % 32).
2386 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2387 abld
.SHL(mask
, sid
, shift_count
);
2388 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2392 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2395 assert(stage
== MESA_SHADER_GEOMETRY
);
2397 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2399 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2400 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2402 /* Haswell and later hardware ignores the "Render Stream Select" bits
2403 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2404 * and instead sends all primitives down the pipeline for rasterization.
2405 * If the SOL stage is enabled, "Render Stream Select" is honored and
2406 * primitives bound to non-zero streams are discarded after stream output.
2408 * Since the only purpose of primives sent to non-zero streams is to
2409 * be recorded by transform feedback, we can simply discard all geometry
2410 * bound to these streams when transform feedback is disabled.
2412 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2415 /* If we're outputting 32 control data bits or less, then we can wait
2416 * until the shader is over to output them all. Otherwise we need to
2417 * output them as we go. Now is the time to do it, since we're about to
2418 * output the vertex_count'th vertex, so it's guaranteed that the
2419 * control data bits associated with the (vertex_count - 1)th vertex are
2422 if (gs_compile
->control_data_header_size_bits
> 32) {
2423 const fs_builder abld
=
2424 bld
.annotate("emit vertex: emit control data bits");
2426 /* Only emit control data bits if we've finished accumulating a batch
2427 * of 32 bits. This is the case when:
2429 * (vertex_count * bits_per_vertex) % 32 == 0
2431 * (in other words, when the last 5 bits of vertex_count *
2432 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2433 * integer n (which is always the case, since bits_per_vertex is
2434 * always 1 or 2), this is equivalent to requiring that the last 5-n
2435 * bits of vertex_count are 0:
2437 * vertex_count & (2^(5-n) - 1) == 0
2439 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2442 * vertex_count & (32 / bits_per_vertex - 1) == 0
2444 * TODO: If vertex_count is an immediate, we could do some of this math
2445 * at compile time...
2448 abld
.AND(bld
.null_reg_d(), vertex_count
,
2449 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2450 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2452 abld
.IF(BRW_PREDICATE_NORMAL
);
2453 /* If vertex_count is 0, then no control data bits have been
2454 * accumulated yet, so we can skip emitting them.
2456 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2457 BRW_CONDITIONAL_NEQ
);
2458 abld
.IF(BRW_PREDICATE_NORMAL
);
2459 emit_gs_control_data_bits(vertex_count
);
2460 abld
.emit(BRW_OPCODE_ENDIF
);
2462 /* Reset control_data_bits to 0 so we can start accumulating a new
2465 * Note: in the case where vertex_count == 0, this neutralizes the
2466 * effect of any call to EndPrimitive() that the shader may have
2467 * made before outputting its first vertex.
2469 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2470 inst
->force_writemask_all
= true;
2471 abld
.emit(BRW_OPCODE_ENDIF
);
2474 emit_urb_writes(vertex_count
);
2476 /* In stream mode we have to set control data bits for all vertices
2477 * unless we have disabled control data bits completely (which we do
2478 * do for GL_POINTS outputs that don't use streams).
2480 if (gs_compile
->control_data_header_size_bits
> 0 &&
2481 gs_prog_data
->control_data_format
==
2482 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2483 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2488 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2489 const nir_src
&vertex_src
,
2490 unsigned base_offset
,
2491 const nir_src
&offset_src
,
2492 unsigned num_components
,
2493 unsigned first_component
)
2495 assert(type_sz(dst
.type
) == 4);
2496 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2497 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2499 /* TODO: figure out push input layout for invocations == 1 */
2500 if (gs_prog_data
->invocations
== 1 &&
2501 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2502 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2503 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2504 nir_src_as_uint(vertex_src
) * push_reg_count
;
2505 for (unsigned i
= 0; i
< num_components
; i
++) {
2506 bld
.MOV(offset(dst
, bld
, i
),
2507 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2512 /* Resort to the pull model. Ensure the VUE handles are provided. */
2513 assert(gs_prog_data
->base
.include_vue_handles
);
2515 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2516 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2518 if (gs_prog_data
->invocations
== 1) {
2519 if (nir_src_is_const(vertex_src
)) {
2520 /* The vertex index is constant; just select the proper URB handle. */
2522 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2523 BRW_REGISTER_TYPE_UD
);
2525 /* The vertex index is non-constant. We need to use indirect
2526 * addressing to fetch the proper URB handle.
2528 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2529 * indicating that channel <n> should read the handle from
2530 * DWord <n>. We convert that to bytes by multiplying by 4.
2532 * Next, we convert the vertex index to bytes by multiplying
2533 * by 32 (shifting by 5), and add the two together. This is
2534 * the final indirect byte offset.
2536 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2537 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2538 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2539 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2541 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2542 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2543 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2544 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2545 /* Convert vertex_index to bytes (multiply by 32) */
2546 bld
.SHL(vertex_offset_bytes
,
2547 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2549 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2551 /* Use first_icp_handle as the base offset. There is one register
2552 * of URB handles per vertex, so inform the register allocator that
2553 * we might read up to nir->info.gs.vertices_in registers.
2555 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2556 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2557 fs_reg(icp_offset_bytes
),
2558 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2561 assert(gs_prog_data
->invocations
> 1);
2563 if (nir_src_is_const(vertex_src
)) {
2564 unsigned vertex
= nir_src_as_uint(vertex_src
);
2565 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2567 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2568 BRW_REGISTER_TYPE_UD
));
2570 /* The vertex index is non-constant. We need to use indirect
2571 * addressing to fetch the proper URB handle.
2574 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2576 /* Convert vertex_index to bytes (multiply by 4) */
2577 bld
.SHL(icp_offset_bytes
,
2578 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2581 /* Use first_icp_handle as the base offset. There is one DWord
2582 * of URB handles per vertex, so inform the register allocator that
2583 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2585 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2586 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2587 fs_reg(icp_offset_bytes
),
2588 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2594 fs_reg indirect_offset
= get_nir_src(offset_src
);
2596 if (nir_src_is_const(offset_src
)) {
2597 /* Constant indexing - use global offset. */
2598 if (first_component
!= 0) {
2599 unsigned read_components
= num_components
+ first_component
;
2600 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2601 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2602 inst
->size_written
= read_components
*
2603 tmp
.component_size(inst
->exec_size
);
2604 for (unsigned i
= 0; i
< num_components
; i
++) {
2605 bld
.MOV(offset(dst
, bld
, i
),
2606 offset(tmp
, bld
, i
+ first_component
));
2609 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2610 inst
->size_written
= num_components
*
2611 dst
.component_size(inst
->exec_size
);
2613 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2616 /* Indirect indexing - use per-slot offsets as well. */
2617 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2618 unsigned read_components
= num_components
+ first_component
;
2619 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2620 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2621 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2622 if (first_component
!= 0) {
2623 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2625 inst
->size_written
= read_components
*
2626 tmp
.component_size(inst
->exec_size
);
2627 for (unsigned i
= 0; i
< num_components
; i
++) {
2628 bld
.MOV(offset(dst
, bld
, i
),
2629 offset(tmp
, bld
, i
+ first_component
));
2632 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2633 inst
->size_written
= num_components
*
2634 dst
.component_size(inst
->exec_size
);
2636 inst
->offset
= base_offset
;
2642 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2644 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2646 if (nir_src_is_const(*offset_src
)) {
2647 /* The only constant offset we should find is 0. brw_nir.c's
2648 * add_const_offset_to_base() will fold other constant offsets
2649 * into instr->const_index[0].
2651 assert(nir_src_as_uint(*offset_src
) == 0);
2655 return get_nir_src(*offset_src
);
2659 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2660 nir_intrinsic_instr
*instr
)
2662 assert(stage
== MESA_SHADER_VERTEX
);
2665 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2666 dest
= get_nir_dest(instr
->dest
);
2668 switch (instr
->intrinsic
) {
2669 case nir_intrinsic_load_vertex_id
:
2670 case nir_intrinsic_load_base_vertex
:
2671 unreachable("should be lowered by nir_lower_system_values()");
2673 case nir_intrinsic_load_input
: {
2674 assert(nir_dest_bit_size(instr
->dest
) == 32);
2675 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2676 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2677 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2679 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2680 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2684 case nir_intrinsic_load_vertex_id_zero_base
:
2685 case nir_intrinsic_load_instance_id
:
2686 case nir_intrinsic_load_base_instance
:
2687 case nir_intrinsic_load_draw_id
:
2688 case nir_intrinsic_load_first_vertex
:
2689 case nir_intrinsic_load_is_indexed_draw
:
2690 unreachable("lowered by brw_nir_lower_vs_inputs");
2693 nir_emit_intrinsic(bld
, instr
);
2699 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2700 nir_intrinsic_instr
*instr
)
2702 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2703 const nir_src
&vertex_src
= instr
->src
[0];
2704 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2707 if (nir_src_is_const(vertex_src
)) {
2708 /* Emit a MOV to resolve <0,1,0> regioning. */
2709 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2710 unsigned vertex
= nir_src_as_uint(vertex_src
);
2712 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2713 BRW_REGISTER_TYPE_UD
));
2714 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2715 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2716 /* For the common case of only 1 instance, an array index of
2717 * gl_InvocationID means reading g1. Skip all the indirect work.
2719 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2721 /* The vertex index is non-constant. We need to use indirect
2722 * addressing to fetch the proper URB handle.
2724 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2726 /* Each ICP handle is a single DWord (4 bytes) */
2727 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2728 bld
.SHL(vertex_offset_bytes
,
2729 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2732 /* Start at g1. We might read up to 4 registers. */
2733 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2734 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2735 brw_imm_ud(4 * REG_SIZE
));
2742 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2743 nir_intrinsic_instr
*instr
)
2745 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2746 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2747 const nir_src
&vertex_src
= instr
->src
[0];
2749 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2751 if (nir_src_is_const(vertex_src
)) {
2752 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2753 nir_src_as_uint(vertex_src
), 0),
2754 BRW_REGISTER_TYPE_UD
));
2757 /* The vertex index is non-constant. We need to use indirect
2758 * addressing to fetch the proper URB handle.
2760 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2761 * indicating that channel <n> should read the handle from
2762 * DWord <n>. We convert that to bytes by multiplying by 4.
2764 * Next, we convert the vertex index to bytes by multiplying
2765 * by 32 (shifting by 5), and add the two together. This is
2766 * the final indirect byte offset.
2768 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2769 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2770 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2771 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2772 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2774 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2775 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2776 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2777 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2778 /* Convert vertex_index to bytes (multiply by 32) */
2779 bld
.SHL(vertex_offset_bytes
,
2780 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2782 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2784 /* Use first_icp_handle as the base offset. There is one register
2785 * of URB handles per vertex, so inform the register allocator that
2786 * we might read up to nir->info.gs.vertices_in registers.
2788 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2789 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2790 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2796 fs_visitor::get_tcs_output_urb_handle()
2798 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2800 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2801 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2803 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2804 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2809 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2810 nir_intrinsic_instr
*instr
)
2812 assert(stage
== MESA_SHADER_TESS_CTRL
);
2813 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2814 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2815 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2818 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2821 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2822 dst
= get_nir_dest(instr
->dest
);
2824 switch (instr
->intrinsic
) {
2825 case nir_intrinsic_load_primitive_id
:
2826 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2827 : brw_vec1_grf(0, 1)));
2829 case nir_intrinsic_load_invocation_id
:
2830 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2832 case nir_intrinsic_load_patch_vertices_in
:
2833 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2834 brw_imm_d(tcs_key
->input_vertices
));
2837 case nir_intrinsic_control_barrier
: {
2838 if (tcs_prog_data
->instances
== 1)
2841 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2842 fs_reg m0_2
= component(m0
, 2);
2844 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2846 /* Zero the message header */
2847 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2849 if (devinfo
->gen
< 11) {
2850 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2851 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2852 brw_imm_ud(INTEL_MASK(16, 13)));
2854 /* Shift it up to bits 27:24. */
2855 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2857 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2858 brw_imm_ud(INTEL_MASK(30, 24)));
2861 /* Set the Barrier Count and the enable bit */
2862 if (devinfo
->gen
< 11) {
2863 chanbld
.OR(m0_2
, m0_2
,
2864 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2866 chanbld
.OR(m0_2
, m0_2
,
2867 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2870 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2874 case nir_intrinsic_load_input
:
2875 unreachable("nir_lower_io should never give us these.");
2878 case nir_intrinsic_load_per_vertex_input
: {
2879 assert(nir_dest_bit_size(instr
->dest
) == 32);
2880 fs_reg indirect_offset
= get_indirect_offset(instr
);
2881 unsigned imm_offset
= instr
->const_index
[0];
2885 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2886 : get_tcs_single_patch_icp_handle(bld
, instr
);
2888 /* We can only read two double components with each URB read, so
2889 * we send two read messages in that case, each one loading up to
2890 * two double components.
2892 unsigned num_components
= instr
->num_components
;
2893 unsigned first_component
= nir_intrinsic_component(instr
);
2895 if (indirect_offset
.file
== BAD_FILE
) {
2896 /* Constant indexing - use global offset. */
2897 if (first_component
!= 0) {
2898 unsigned read_components
= num_components
+ first_component
;
2899 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2900 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2901 for (unsigned i
= 0; i
< num_components
; i
++) {
2902 bld
.MOV(offset(dst
, bld
, i
),
2903 offset(tmp
, bld
, i
+ first_component
));
2906 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2908 inst
->offset
= imm_offset
;
2911 /* Indirect indexing - use per-slot offsets as well. */
2912 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2913 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2914 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2915 if (first_component
!= 0) {
2916 unsigned read_components
= num_components
+ first_component
;
2917 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2918 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2920 for (unsigned i
= 0; i
< num_components
; i
++) {
2921 bld
.MOV(offset(dst
, bld
, i
),
2922 offset(tmp
, bld
, i
+ first_component
));
2925 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2928 inst
->offset
= imm_offset
;
2931 inst
->size_written
= (num_components
+ first_component
) *
2932 inst
->dst
.component_size(inst
->exec_size
);
2934 /* Copy the temporary to the destination to deal with writemasking.
2936 * Also attempt to deal with gl_PointSize being in the .w component.
2938 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2939 assert(type_sz(dst
.type
) == 4);
2940 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2941 inst
->size_written
= 4 * REG_SIZE
;
2942 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2947 case nir_intrinsic_load_output
:
2948 case nir_intrinsic_load_per_vertex_output
: {
2949 assert(nir_dest_bit_size(instr
->dest
) == 32);
2950 fs_reg indirect_offset
= get_indirect_offset(instr
);
2951 unsigned imm_offset
= instr
->const_index
[0];
2952 unsigned first_component
= nir_intrinsic_component(instr
);
2954 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2957 if (indirect_offset
.file
== BAD_FILE
) {
2958 /* This MOV replicates the output handle to all enabled channels
2959 * is SINGLE_PATCH mode.
2961 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2962 bld
.MOV(patch_handle
, output_handles
);
2965 if (first_component
!= 0) {
2966 unsigned read_components
=
2967 instr
->num_components
+ first_component
;
2968 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2969 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2971 inst
->size_written
= read_components
* REG_SIZE
;
2972 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2973 bld
.MOV(offset(dst
, bld
, i
),
2974 offset(tmp
, bld
, i
+ first_component
));
2977 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2979 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2981 inst
->offset
= imm_offset
;
2985 /* Indirect indexing - use per-slot offsets as well. */
2986 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2987 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2988 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2989 if (first_component
!= 0) {
2990 unsigned read_components
=
2991 instr
->num_components
+ first_component
;
2992 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2993 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2995 inst
->size_written
= read_components
* REG_SIZE
;
2996 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2997 bld
.MOV(offset(dst
, bld
, i
),
2998 offset(tmp
, bld
, i
+ first_component
));
3001 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
3003 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3005 inst
->offset
= imm_offset
;
3011 case nir_intrinsic_store_output
:
3012 case nir_intrinsic_store_per_vertex_output
: {
3013 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3014 fs_reg value
= get_nir_src(instr
->src
[0]);
3015 fs_reg indirect_offset
= get_indirect_offset(instr
);
3016 unsigned imm_offset
= instr
->const_index
[0];
3017 unsigned mask
= instr
->const_index
[1];
3018 unsigned header_regs
= 0;
3019 struct brw_reg output_handles
= get_tcs_output_urb_handle();
3022 srcs
[header_regs
++] = output_handles
;
3024 if (indirect_offset
.file
!= BAD_FILE
) {
3025 srcs
[header_regs
++] = indirect_offset
;
3031 unsigned num_components
= util_last_bit(mask
);
3034 /* We can only pack two 64-bit components in a single message, so send
3035 * 2 messages if we have more components
3037 unsigned first_component
= nir_intrinsic_component(instr
);
3038 mask
= mask
<< first_component
;
3040 if (mask
!= WRITEMASK_XYZW
) {
3041 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
3042 opcode
= indirect_offset
.file
!= BAD_FILE
?
3043 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
3044 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
3046 opcode
= indirect_offset
.file
!= BAD_FILE
?
3047 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
3048 SHADER_OPCODE_URB_WRITE_SIMD8
;
3051 for (unsigned i
= 0; i
< num_components
; i
++) {
3052 if (!(mask
& (1 << (i
+ first_component
))))
3055 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
3058 unsigned mlen
= header_regs
+ num_components
+ first_component
;
3060 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
3061 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
3063 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
3064 inst
->offset
= imm_offset
;
3070 nir_emit_intrinsic(bld
, instr
);
3076 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
3077 nir_intrinsic_instr
*instr
)
3079 assert(stage
== MESA_SHADER_TESS_EVAL
);
3080 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3083 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3084 dest
= get_nir_dest(instr
->dest
);
3086 switch (instr
->intrinsic
) {
3087 case nir_intrinsic_load_primitive_id
:
3088 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3090 case nir_intrinsic_load_tess_coord
:
3091 /* gl_TessCoord is part of the payload in g1-3 */
3092 for (unsigned i
= 0; i
< 3; i
++) {
3093 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3097 case nir_intrinsic_load_input
:
3098 case nir_intrinsic_load_per_vertex_input
: {
3099 assert(nir_dest_bit_size(instr
->dest
) == 32);
3100 fs_reg indirect_offset
= get_indirect_offset(instr
);
3101 unsigned imm_offset
= instr
->const_index
[0];
3102 unsigned first_component
= nir_intrinsic_component(instr
);
3105 if (indirect_offset
.file
== BAD_FILE
) {
3106 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3107 * which is 16 registers (since each holds 2 vec4 slots).
3109 const unsigned max_push_slots
= 32;
3110 if (imm_offset
< max_push_slots
) {
3111 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3112 for (int i
= 0; i
< instr
->num_components
; i
++) {
3113 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3114 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3117 tes_prog_data
->base
.urb_read_length
=
3118 MAX2(tes_prog_data
->base
.urb_read_length
,
3119 (imm_offset
/ 2) + 1);
3121 /* Replicate the patch handle to all enabled channels */
3122 const fs_reg srcs
[] = {
3123 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3125 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3126 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3128 if (first_component
!= 0) {
3129 unsigned read_components
=
3130 instr
->num_components
+ first_component
;
3131 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3132 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3134 inst
->size_written
= read_components
* REG_SIZE
;
3135 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3136 bld
.MOV(offset(dest
, bld
, i
),
3137 offset(tmp
, bld
, i
+ first_component
));
3140 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3142 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3145 inst
->offset
= imm_offset
;
3148 /* Indirect indexing - use per-slot offsets as well. */
3150 /* We can only read two double components with each URB read, so
3151 * we send two read messages in that case, each one loading up to
3152 * two double components.
3154 unsigned num_components
= instr
->num_components
;
3155 const fs_reg srcs
[] = {
3156 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3159 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3160 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3162 if (first_component
!= 0) {
3163 unsigned read_components
=
3164 num_components
+ first_component
;
3165 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3166 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3168 for (unsigned i
= 0; i
< num_components
; i
++) {
3169 bld
.MOV(offset(dest
, bld
, i
),
3170 offset(tmp
, bld
, i
+ first_component
));
3173 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3177 inst
->offset
= imm_offset
;
3178 inst
->size_written
= (num_components
+ first_component
) *
3179 inst
->dst
.component_size(inst
->exec_size
);
3184 nir_emit_intrinsic(bld
, instr
);
3190 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3191 nir_intrinsic_instr
*instr
)
3193 assert(stage
== MESA_SHADER_GEOMETRY
);
3194 fs_reg indirect_offset
;
3197 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3198 dest
= get_nir_dest(instr
->dest
);
3200 switch (instr
->intrinsic
) {
3201 case nir_intrinsic_load_primitive_id
:
3202 assert(stage
== MESA_SHADER_GEOMETRY
);
3203 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3204 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3205 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3208 case nir_intrinsic_load_input
:
3209 unreachable("load_input intrinsics are invalid for the GS stage");
3211 case nir_intrinsic_load_per_vertex_input
:
3212 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3213 instr
->src
[1], instr
->num_components
,
3214 nir_intrinsic_component(instr
));
3217 case nir_intrinsic_emit_vertex_with_counter
:
3218 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3221 case nir_intrinsic_end_primitive_with_counter
:
3222 emit_gs_end_primitive(instr
->src
[0]);
3225 case nir_intrinsic_set_vertex_count
:
3226 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3229 case nir_intrinsic_load_invocation_id
: {
3230 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3231 assert(val
.file
!= BAD_FILE
);
3232 dest
.type
= val
.type
;
3238 nir_emit_intrinsic(bld
, instr
);
3244 * Fetch the current render target layer index.
3247 fetch_render_target_array_index(const fs_builder
&bld
)
3249 if (bld
.shader
->devinfo
->gen
>= 6) {
3250 /* The render target array index is provided in the thread payload as
3251 * bits 26:16 of r0.0.
3253 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3254 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3258 /* Pre-SNB we only ever render into the first layer of the framebuffer
3259 * since layered rendering is not implemented.
3261 return brw_imm_ud(0);
3266 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3267 * framebuffer at the current fragment coordinates and sample index.
3270 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3273 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3275 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3276 const brw_wm_prog_key
*wm_key
=
3277 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3278 assert(!wm_key
->coherent_fb_fetch
);
3279 const struct brw_wm_prog_data
*wm_prog_data
=
3280 brw_wm_prog_data(stage_prog_data
);
3282 /* Calculate the surface index relative to the start of the texture binding
3283 * table block, since that's what the texturing messages expect.
3285 const unsigned surface
= target
+
3286 wm_prog_data
->binding_table
.render_target_read_start
-
3287 wm_prog_data
->base
.binding_table
.texture_start
;
3289 /* Calculate the fragment coordinates. */
3290 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3291 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3292 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3293 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3295 /* Calculate the sample index and MCS payload when multisampling. Luckily
3296 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3297 * shouldn't be necessary to recompile based on whether the framebuffer is
3300 if (wm_key
->multisample_fbo
&&
3301 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3302 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3304 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3305 const fs_reg mcs
= wm_key
->multisample_fbo
?
3306 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3308 /* Use either a normal or a CMS texel fetch message depending on whether
3309 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3310 * message just in case the framebuffer uses 16x multisampling, it should
3311 * be equivalent to the normal CMS fetch for lower multisampling modes.
3313 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3314 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3315 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3317 /* Emit the instruction. */
3318 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3319 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3320 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3321 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3322 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3323 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3324 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3325 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3326 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3328 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3329 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3335 * Actual coherent framebuffer read implemented using the native render target
3336 * read message. Requires SKL+.
3339 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3341 assert(bld
.shader
->devinfo
->gen
>= 9);
3342 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3343 inst
->target
= target
;
3344 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3350 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3352 if (n
&& regs
[0].file
!= BAD_FILE
) {
3356 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3358 for (unsigned i
= 0; i
< n
; i
++)
3366 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3368 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3369 const brw_wm_prog_key
*const key
=
3370 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3371 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3372 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3374 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3375 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3377 else if (l
== FRAG_RESULT_COLOR
)
3378 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3379 MAX2(key
->nr_color_regions
, 1));
3381 else if (l
== FRAG_RESULT_DEPTH
)
3382 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3384 else if (l
== FRAG_RESULT_STENCIL
)
3385 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3387 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3388 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3390 else if (l
>= FRAG_RESULT_DATA0
&&
3391 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3392 return alloc_temporary(v
->bld
, 4,
3393 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3396 unreachable("Invalid location");
3400 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3401 nir_intrinsic_instr
*instr
)
3403 assert(stage
== MESA_SHADER_FRAGMENT
);
3406 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3407 dest
= get_nir_dest(instr
->dest
);
3409 switch (instr
->intrinsic
) {
3410 case nir_intrinsic_load_front_face
:
3411 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3412 *emit_frontfacing_interpolation());
3415 case nir_intrinsic_load_sample_pos
: {
3416 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3417 assert(sample_pos
.file
!= BAD_FILE
);
3418 dest
.type
= sample_pos
.type
;
3419 bld
.MOV(dest
, sample_pos
);
3420 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3424 case nir_intrinsic_load_layer_id
:
3425 dest
.type
= BRW_REGISTER_TYPE_UD
;
3426 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3429 case nir_intrinsic_is_helper_invocation
: {
3430 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3431 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3432 * consideration demoted invocations. That information is stored in
3435 dest
.type
= BRW_REGISTER_TYPE_UD
;
3437 bld
.MOV(dest
, brw_imm_ud(0));
3439 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3440 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3441 mov
->predicate_inverse
= true;
3442 mov
->flag_subreg
= sample_mask_flag_subreg(this);
3446 case nir_intrinsic_load_helper_invocation
:
3447 case nir_intrinsic_load_sample_mask_in
:
3448 case nir_intrinsic_load_sample_id
: {
3449 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3450 fs_reg val
= nir_system_values
[sv
];
3451 assert(val
.file
!= BAD_FILE
);
3452 dest
.type
= val
.type
;
3457 case nir_intrinsic_store_output
: {
3458 const fs_reg src
= get_nir_src(instr
->src
[0]);
3459 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3460 const unsigned location
= nir_intrinsic_base(instr
) +
3461 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3462 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3465 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3466 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3467 offset(src
, bld
, j
));
3472 case nir_intrinsic_load_output
: {
3473 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3474 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3475 assert(l
>= FRAG_RESULT_DATA0
);
3476 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3477 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3478 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3480 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3481 emit_coherent_fb_read(bld
, tmp
, target
);
3483 emit_non_coherent_fb_read(bld
, tmp
, target
);
3485 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3486 bld
.MOV(offset(dest
, bld
, j
),
3487 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3493 case nir_intrinsic_demote
:
3494 case nir_intrinsic_discard
:
3495 case nir_intrinsic_demote_if
:
3496 case nir_intrinsic_discard_if
: {
3497 /* We track our discarded pixels in f0.1/f1.0. By predicating on it, we
3498 * can update just the flag bits that aren't yet discarded. If there's
3499 * no condition, we emit a CMP of g0 != g0, so all currently executing
3500 * channels will get turned off.
3502 fs_inst
*cmp
= NULL
;
3503 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3504 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3505 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3508 alu
->op
!= nir_op_bcsel
&&
3509 (devinfo
->gen
> 5 ||
3510 (alu
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE
||
3511 alu
->op
== nir_op_fne32
|| alu
->op
== nir_op_feq32
||
3512 alu
->op
== nir_op_flt32
|| alu
->op
== nir_op_fge32
||
3513 alu
->op
== nir_op_ine32
|| alu
->op
== nir_op_ieq32
||
3514 alu
->op
== nir_op_ilt32
|| alu
->op
== nir_op_ige32
||
3515 alu
->op
== nir_op_ult32
|| alu
->op
== nir_op_uge32
)) {
3516 /* Re-emit the instruction that generated the Boolean value, but
3517 * do not store it. Since this instruction will be conditional,
3518 * other instructions that want to use the real Boolean value may
3519 * get garbage. This was a problem for piglit's fs-discard-exit-2
3522 * Ideally we'd detect that the instruction cannot have a
3523 * conditional modifier before emitting the instructions. Alas,
3524 * that is nigh impossible. Instead, we're going to assume the
3525 * instruction (or last instruction) generated can have a
3526 * conditional modifier. If it cannot, fallback to the old-style
3527 * compare, and hope dead code elimination will clean up the
3528 * extra instructions generated.
3530 nir_emit_alu(bld
, alu
, false);
3532 cmp
= (fs_inst
*) instructions
.get_tail();
3533 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3534 if (cmp
->can_do_cmod())
3535 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3539 /* The old sequence that would have been generated is,
3540 * basically, bool_result == false. This is equivalent to
3541 * !bool_result, so negate the old modifier.
3543 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3548 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3549 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3552 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3553 BRW_REGISTER_TYPE_UW
));
3554 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3557 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3558 cmp
->flag_subreg
= sample_mask_flag_subreg(this);
3560 if (devinfo
->gen
>= 6) {
3561 /* Due to the way we implement discard, the jump will only happen
3562 * when the whole quad is discarded. So we can do this even for
3563 * demote as it won't break its uniformity promises.
3565 emit_discard_jump();
3568 if (devinfo
->gen
< 7)
3569 limit_dispatch_width(
3570 16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
3574 case nir_intrinsic_load_input
: {
3575 /* load_input is only used for flat inputs */
3576 assert(nir_dest_bit_size(instr
->dest
) == 32);
3577 unsigned base
= nir_intrinsic_base(instr
);
3578 unsigned comp
= nir_intrinsic_component(instr
);
3579 unsigned num_components
= instr
->num_components
;
3581 /* Special case fields in the VUE header */
3582 if (base
== VARYING_SLOT_LAYER
)
3584 else if (base
== VARYING_SLOT_VIEWPORT
)
3587 for (unsigned int i
= 0; i
< num_components
; i
++) {
3588 bld
.MOV(offset(dest
, bld
, i
),
3589 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3594 case nir_intrinsic_load_fs_input_interp_deltas
: {
3595 assert(stage
== MESA_SHADER_FRAGMENT
);
3596 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3597 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3598 nir_intrinsic_component(instr
));
3599 dest
.type
= BRW_REGISTER_TYPE_F
;
3600 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3601 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3602 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3606 case nir_intrinsic_load_barycentric_pixel
:
3607 case nir_intrinsic_load_barycentric_centroid
:
3608 case nir_intrinsic_load_barycentric_sample
: {
3609 /* Use the delta_xy values computed from the payload */
3610 const glsl_interp_mode interp_mode
=
3611 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3612 enum brw_barycentric_mode bary
=
3613 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3614 const fs_reg srcs
[] = { offset(this->delta_xy
[bary
], bld
, 0),
3615 offset(this->delta_xy
[bary
], bld
, 1) };
3616 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3620 case nir_intrinsic_load_barycentric_at_sample
: {
3621 const glsl_interp_mode interpolation
=
3622 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3624 if (nir_src_is_const(instr
->src
[0])) {
3625 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3627 emit_pixel_interpolater_send(bld
,
3628 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3631 brw_imm_ud(msg_data
),
3634 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3635 BRW_REGISTER_TYPE_UD
);
3637 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3638 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3639 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3640 bld
.exec_all().group(1, 0)
3641 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3642 emit_pixel_interpolater_send(bld
,
3643 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3646 component(msg_data
, 0),
3649 /* Make a loop that sends a message to the pixel interpolater
3650 * for the sample number in each live channel. If there are
3651 * multiple channels with the same sample number then these
3652 * will be handled simultaneously with a single interation of
3655 bld
.emit(BRW_OPCODE_DO
);
3657 /* Get the next live sample number into sample_id_reg */
3658 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3660 /* Set the flag register so that we can perform the send
3661 * message on all channels that have the same sample number
3663 bld
.CMP(bld
.null_reg_ud(),
3664 sample_src
, sample_id
,
3665 BRW_CONDITIONAL_EQ
);
3666 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3667 bld
.exec_all().group(1, 0)
3668 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3670 emit_pixel_interpolater_send(bld
,
3671 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3674 component(msg_data
, 0),
3676 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3678 /* Continue the loop if there are any live channels left */
3679 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3681 bld
.emit(BRW_OPCODE_WHILE
));
3687 case nir_intrinsic_load_barycentric_at_offset
: {
3688 const glsl_interp_mode interpolation
=
3689 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3691 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3694 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3695 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3696 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3698 emit_pixel_interpolater_send(bld
,
3699 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3702 brw_imm_ud(off_x
| (off_y
<< 4)),
3705 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3706 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3707 BRW_REGISTER_TYPE_F
);
3708 for (int i
= 0; i
< 2; i
++) {
3709 fs_reg temp
= vgrf(glsl_type::float_type
);
3710 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3711 fs_reg itemp
= vgrf(glsl_type::int_type
);
3713 bld
.MOV(itemp
, temp
);
3715 /* Clamp the upper end of the range to +7/16.
3716 * ARB_gpu_shader5 requires that we support a maximum offset
3717 * of +0.5, which isn't representable in a S0.4 value -- if
3718 * we didn't clamp it, we'd end up with -8/16, which is the
3719 * opposite of what the shader author wanted.
3721 * This is legal due to ARB_gpu_shader5's quantization
3724 * "Not all values of <offset> may be supported; x and y
3725 * offsets may be rounded to fixed-point values with the
3726 * number of fraction bits given by the
3727 * implementation-dependent constant
3728 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3730 set_condmod(BRW_CONDITIONAL_L
,
3731 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3734 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3735 emit_pixel_interpolater_send(bld
,
3745 case nir_intrinsic_load_frag_coord
:
3746 emit_fragcoord_interpolation(dest
);
3749 case nir_intrinsic_load_interpolated_input
: {
3750 assert(instr
->src
[0].ssa
&&
3751 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3752 nir_intrinsic_instr
*bary_intrinsic
=
3753 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3754 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3755 enum glsl_interp_mode interp_mode
=
3756 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3759 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3760 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3761 /* Use the result of the PI message. */
3762 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3764 /* Use the delta_xy values computed from the payload */
3765 enum brw_barycentric_mode bary
=
3766 brw_barycentric_mode(interp_mode
, bary_intrin
);
3767 dst_xy
= this->delta_xy
[bary
];
3770 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3772 component(interp_reg(nir_intrinsic_base(instr
),
3773 nir_intrinsic_component(instr
) + i
), 0);
3774 interp
.type
= BRW_REGISTER_TYPE_F
;
3775 dest
.type
= BRW_REGISTER_TYPE_F
;
3777 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3778 fs_reg tmp
= vgrf(glsl_type::float_type
);
3779 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3780 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3782 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3789 nir_emit_intrinsic(bld
, instr
);
3795 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3796 nir_intrinsic_instr
*instr
)
3798 assert(stage
== MESA_SHADER_COMPUTE
);
3799 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3802 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3803 dest
= get_nir_dest(instr
->dest
);
3805 switch (instr
->intrinsic
) {
3806 case nir_intrinsic_control_barrier
:
3807 /* The whole workgroup fits in a single HW thread, so all the
3808 * invocations are already executed lock-step. Instead of an actual
3809 * barrier just emit a scheduling fence, that will generate no code.
3811 if (!cs_prog_data
->uses_variable_group_size
&&
3812 workgroup_size() <= dispatch_width
) {
3813 bld
.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE
);
3818 cs_prog_data
->uses_barrier
= true;
3821 case nir_intrinsic_load_subgroup_id
:
3822 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3825 case nir_intrinsic_load_local_invocation_id
:
3826 case nir_intrinsic_load_work_group_id
: {
3827 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3828 fs_reg val
= nir_system_values
[sv
];
3829 assert(val
.file
!= BAD_FILE
);
3830 dest
.type
= val
.type
;
3831 for (unsigned i
= 0; i
< 3; i
++)
3832 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3836 case nir_intrinsic_load_num_work_groups
: {
3837 const unsigned surface
=
3838 cs_prog_data
->binding_table
.work_groups_start
;
3840 cs_prog_data
->uses_num_work_groups
= true;
3842 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3843 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3844 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3845 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3847 /* Read the 3 GLuint components of gl_NumWorkGroups */
3848 for (unsigned i
= 0; i
< 3; i
++) {
3849 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3850 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3851 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3856 case nir_intrinsic_shared_atomic_add
:
3857 case nir_intrinsic_shared_atomic_imin
:
3858 case nir_intrinsic_shared_atomic_umin
:
3859 case nir_intrinsic_shared_atomic_imax
:
3860 case nir_intrinsic_shared_atomic_umax
:
3861 case nir_intrinsic_shared_atomic_and
:
3862 case nir_intrinsic_shared_atomic_or
:
3863 case nir_intrinsic_shared_atomic_xor
:
3864 case nir_intrinsic_shared_atomic_exchange
:
3865 case nir_intrinsic_shared_atomic_comp_swap
:
3866 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3868 case nir_intrinsic_shared_atomic_fmin
:
3869 case nir_intrinsic_shared_atomic_fmax
:
3870 case nir_intrinsic_shared_atomic_fcomp_swap
:
3871 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3874 case nir_intrinsic_load_shared
: {
3875 assert(devinfo
->gen
>= 7);
3876 assert(stage
== MESA_SHADER_COMPUTE
);
3878 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3879 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3880 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3881 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3882 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3884 /* Make dest unsigned because that's what the temporary will be */
3885 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3887 /* Read the vector */
3888 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3889 assert(nir_intrinsic_align(instr
) > 0);
3890 if (nir_dest_bit_size(instr
->dest
) == 32 &&
3891 nir_intrinsic_align(instr
) >= 4) {
3892 assert(nir_dest_num_components(instr
->dest
) <= 4);
3893 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3895 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3896 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3897 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3899 assert(nir_dest_num_components(instr
->dest
) == 1);
3900 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3902 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3903 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3904 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3905 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3910 case nir_intrinsic_store_shared
: {
3911 assert(devinfo
->gen
>= 7);
3912 assert(stage
== MESA_SHADER_COMPUTE
);
3914 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3915 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3916 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3917 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3918 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3920 fs_reg data
= get_nir_src(instr
->src
[0]);
3921 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3923 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3924 assert(nir_intrinsic_write_mask(instr
) ==
3925 (1u << instr
->num_components
) - 1);
3926 assert(nir_intrinsic_align(instr
) > 0);
3927 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
3928 nir_intrinsic_align(instr
) >= 4) {
3929 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3930 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3931 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3932 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3933 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3935 assert(nir_src_num_components(instr
->src
[0]) == 1);
3936 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3938 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3939 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3941 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3942 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3947 case nir_intrinsic_load_local_group_size
: {
3948 for (unsigned i
= 0; i
< 3; i
++) {
3949 bld
.MOV(retype(offset(dest
, bld
, i
), BRW_REGISTER_TYPE_UD
),
3956 nir_emit_intrinsic(bld
, instr
);
3962 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3963 nir_op op
, brw_reg_type type
)
3965 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3966 switch (type_sz(type
)) {
3968 if (type
== BRW_REGISTER_TYPE_UB
) {
3969 return brw_imm_uw(value
.u8
);
3971 assert(type
== BRW_REGISTER_TYPE_B
);
3972 return brw_imm_w(value
.i8
);
3975 return retype(brw_imm_uw(value
.u16
), type
);
3977 return retype(brw_imm_ud(value
.u32
), type
);
3979 if (type
== BRW_REGISTER_TYPE_DF
)
3980 return setup_imm_df(bld
, value
.f64
);
3982 return retype(brw_imm_u64(value
.u64
), type
);
3984 unreachable("Invalid type size");
3989 brw_op_for_nir_reduction_op(nir_op op
)
3992 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3993 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3994 case nir_op_imul
: return BRW_OPCODE_MUL
;
3995 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3996 case nir_op_imin
: return BRW_OPCODE_SEL
;
3997 case nir_op_umin
: return BRW_OPCODE_SEL
;
3998 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3999 case nir_op_imax
: return BRW_OPCODE_SEL
;
4000 case nir_op_umax
: return BRW_OPCODE_SEL
;
4001 case nir_op_fmax
: return BRW_OPCODE_SEL
;
4002 case nir_op_iand
: return BRW_OPCODE_AND
;
4003 case nir_op_ior
: return BRW_OPCODE_OR
;
4004 case nir_op_ixor
: return BRW_OPCODE_XOR
;
4006 unreachable("Invalid reduction operation");
4010 static brw_conditional_mod
4011 brw_cond_mod_for_nir_reduction_op(nir_op op
)
4014 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
4015 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
4016 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
4017 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
4018 case nir_op_imin
: return BRW_CONDITIONAL_L
;
4019 case nir_op_umin
: return BRW_CONDITIONAL_L
;
4020 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
4021 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
4022 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
4023 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
4024 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
4025 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
4026 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
4028 unreachable("Invalid reduction operation");
4033 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
4034 nir_intrinsic_instr
*instr
)
4036 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
4037 fs_reg surf_index
= image
;
4039 if (stage_prog_data
->binding_table
.image_start
> 0) {
4040 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
4042 brw_imm_ud(image
.d
+ stage_prog_data
->binding_table
.image_start
);
4044 surf_index
= vgrf(glsl_type::uint_type
);
4045 bld
.ADD(surf_index
, image
,
4046 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
4050 return bld
.emit_uniformize(surf_index
);
4054 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
4055 nir_intrinsic_instr
*instr
)
4057 /* SSBO stores are weird in that their index is in src[1] */
4058 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
4061 if (nir_src_is_const(instr
->src
[src
])) {
4062 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4063 nir_src_as_uint(instr
->src
[src
]);
4064 surf_index
= brw_imm_ud(index
);
4066 surf_index
= vgrf(glsl_type::uint_type
);
4067 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
4068 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4071 return bld
.emit_uniformize(surf_index
);
4075 * The offsets we get from NIR act as if each SIMD channel has it's own blob
4076 * of contiguous space. However, if we actually place each SIMD channel in
4077 * it's own space, we end up with terrible cache performance because each SIMD
4078 * channel accesses a different cache line even when they're all accessing the
4079 * same byte offset. To deal with this problem, we swizzle the address using
4080 * a simple algorithm which ensures that any time a SIMD message reads or
4081 * writes the same address, it's all in the same cache line. We have to keep
4082 * the bottom two bits fixed so that we can read/write up to a dword at a time
4083 * and the individual element is contiguous. We do this by splitting the
4084 * address as follows:
4087 * +-------------------------------+------------+----------+
4088 * | Hi address bits | chan index | addr low |
4089 * +-------------------------------+------------+----------+
4091 * In other words, the bottom two address bits stay, and the top 30 get
4092 * shifted up so that we can stick the SIMD channel index in the middle. This
4093 * way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
4094 * at the same logical offset, the scratch read/write instruction acts on
4095 * continuous elements and we get good cache locality.
4098 fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
4099 const fs_reg
&nir_addr
,
4102 const fs_reg
&chan_index
=
4103 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
4104 const unsigned chan_index_bits
= ffs(dispatch_width
) - 1;
4106 fs_reg addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4108 /* In this case, we know the address is aligned to a DWORD and we want
4109 * the final address in DWORDs.
4111 bld
.SHL(addr
, nir_addr
, brw_imm_ud(chan_index_bits
- 2));
4112 bld
.OR(addr
, addr
, chan_index
);
4114 /* This case substantially more annoying because we have to pay
4115 * attention to those pesky two bottom bits.
4117 fs_reg addr_hi
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4118 bld
.AND(addr_hi
, nir_addr
, brw_imm_ud(~0x3u
));
4119 bld
.SHL(addr_hi
, addr_hi
, brw_imm_ud(chan_index_bits
));
4120 fs_reg chan_addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4121 bld
.SHL(chan_addr
, chan_index
, brw_imm_ud(2));
4122 bld
.AND(addr
, nir_addr
, brw_imm_ud(0x3u
));
4123 bld
.OR(addr
, addr
, addr_hi
);
4124 bld
.OR(addr
, addr
, chan_addr
);
4130 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4133 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4134 dest
= get_nir_dest(instr
->dest
);
4136 switch (instr
->intrinsic
) {
4137 case nir_intrinsic_image_load
:
4138 case nir_intrinsic_image_store
:
4139 case nir_intrinsic_image_atomic_add
:
4140 case nir_intrinsic_image_atomic_imin
:
4141 case nir_intrinsic_image_atomic_umin
:
4142 case nir_intrinsic_image_atomic_imax
:
4143 case nir_intrinsic_image_atomic_umax
:
4144 case nir_intrinsic_image_atomic_and
:
4145 case nir_intrinsic_image_atomic_or
:
4146 case nir_intrinsic_image_atomic_xor
:
4147 case nir_intrinsic_image_atomic_exchange
:
4148 case nir_intrinsic_image_atomic_comp_swap
:
4149 case nir_intrinsic_bindless_image_load
:
4150 case nir_intrinsic_bindless_image_store
:
4151 case nir_intrinsic_bindless_image_atomic_add
:
4152 case nir_intrinsic_bindless_image_atomic_imin
:
4153 case nir_intrinsic_bindless_image_atomic_umin
:
4154 case nir_intrinsic_bindless_image_atomic_imax
:
4155 case nir_intrinsic_bindless_image_atomic_umax
:
4156 case nir_intrinsic_bindless_image_atomic_and
:
4157 case nir_intrinsic_bindless_image_atomic_or
:
4158 case nir_intrinsic_bindless_image_atomic_xor
:
4159 case nir_intrinsic_bindless_image_atomic_exchange
:
4160 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4161 if (stage
== MESA_SHADER_FRAGMENT
&&
4162 instr
->intrinsic
!= nir_intrinsic_image_load
)
4163 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4165 /* Get some metadata from the image intrinsic. */
4166 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4168 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4170 switch (instr
->intrinsic
) {
4171 case nir_intrinsic_image_load
:
4172 case nir_intrinsic_image_store
:
4173 case nir_intrinsic_image_atomic_add
:
4174 case nir_intrinsic_image_atomic_imin
:
4175 case nir_intrinsic_image_atomic_umin
:
4176 case nir_intrinsic_image_atomic_imax
:
4177 case nir_intrinsic_image_atomic_umax
:
4178 case nir_intrinsic_image_atomic_and
:
4179 case nir_intrinsic_image_atomic_or
:
4180 case nir_intrinsic_image_atomic_xor
:
4181 case nir_intrinsic_image_atomic_exchange
:
4182 case nir_intrinsic_image_atomic_comp_swap
:
4183 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4184 get_nir_image_intrinsic_image(bld
, instr
);
4189 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4190 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4194 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4195 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4196 brw_imm_ud(nir_image_intrinsic_coord_components(instr
));
4198 /* Emit an image load, store or atomic op. */
4199 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4200 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4201 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4203 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4204 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4205 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4206 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4207 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4208 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4209 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4210 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4211 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4213 unsigned num_srcs
= info
->num_srcs
;
4214 int op
= brw_aop_for_nir_intrinsic(instr
);
4215 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4216 assert(num_srcs
== 4);
4220 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4224 data
= get_nir_src(instr
->src
[3]);
4225 if (num_srcs
>= 5) {
4226 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4227 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4228 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4231 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4233 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4234 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4239 case nir_intrinsic_image_size
:
4240 case nir_intrinsic_bindless_image_size
: {
4241 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4242 * into will handle the binding table index for us in the geneerator.
4243 * Incidentally, this means that we can handle bindless with exactly the
4246 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4247 BRW_REGISTER_TYPE_UD
);
4248 image
= bld
.emit_uniformize(image
);
4250 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4251 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4252 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4254 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4255 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4256 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4257 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4259 /* Since the image size is always uniform, we can just emit a SIMD8
4260 * query instruction and splat the result out.
4262 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4264 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4265 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4266 tmp
, srcs
, ARRAY_SIZE(srcs
));
4267 inst
->size_written
= 4 * REG_SIZE
;
4269 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4270 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4271 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4272 offset(retype(dest
, tmp
.type
), bld
, c
),
4273 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4275 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4276 component(offset(tmp
, ubld
, c
), 0));
4282 case nir_intrinsic_image_load_raw_intel
: {
4283 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4284 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4285 get_nir_image_intrinsic_image(bld
, instr
);
4286 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4287 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4288 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4291 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4292 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4293 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4297 case nir_intrinsic_image_store_raw_intel
: {
4298 if (stage
== MESA_SHADER_FRAGMENT
)
4299 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4301 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4302 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4303 get_nir_image_intrinsic_image(bld
, instr
);
4304 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4305 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4306 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4307 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4309 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4310 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4314 case nir_intrinsic_scoped_memory_barrier
:
4315 case nir_intrinsic_group_memory_barrier
:
4316 case nir_intrinsic_memory_barrier_shared
:
4317 case nir_intrinsic_memory_barrier_buffer
:
4318 case nir_intrinsic_memory_barrier_image
:
4319 case nir_intrinsic_memory_barrier
: {
4320 bool l3_fence
, slm_fence
;
4321 if (instr
->intrinsic
== nir_intrinsic_scoped_memory_barrier
) {
4322 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4323 l3_fence
= modes
& (nir_var_shader_out
|
4325 nir_var_mem_global
);
4326 slm_fence
= modes
& nir_var_mem_shared
;
4328 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4329 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4330 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4331 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4334 if (stage
!= MESA_SHADER_COMPUTE
)
4337 /* If the workgroup fits in a single HW thread, the messages for SLM are
4338 * processed in-order and the shader itself is already synchronized so
4339 * the memory fence is not necessary.
4341 * TODO: Check if applies for many HW threads sharing same Data Port.
4343 if (!brw_cs_prog_data(prog_data
)->uses_variable_group_size
&&
4344 slm_fence
&& workgroup_size() <= dispatch_width
)
4347 /* Prior to Gen11, there's only L3 fence, so emit that instead. */
4348 if (slm_fence
&& devinfo
->gen
< 11) {
4353 /* Be conservative in Gen11+ and always stall in a fence. Since there
4354 * are two different fences, and shader might want to synchronize
4357 * TODO: Improve NIR so that scope and visibility information for the
4358 * barriers is available here to make a better decision.
4360 * TODO: When emitting more than one fence, it might help emit all
4361 * the fences first and then generate the stall moves.
4363 const bool stall
= devinfo
->gen
>= 11;
4365 const fs_builder ubld
= bld
.group(8, 0);
4366 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4369 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4370 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4371 /* bti */ brw_imm_ud(0))
4372 ->size_written
= 2 * REG_SIZE
;
4376 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4377 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4378 brw_imm_ud(GEN7_BTI_SLM
))
4379 ->size_written
= 2 * REG_SIZE
;
4382 if (!l3_fence
&& !slm_fence
)
4383 ubld
.emit(FS_OPCODE_SCHEDULING_FENCE
);
4388 case nir_intrinsic_memory_barrier_tcs_patch
:
4391 case nir_intrinsic_shader_clock
: {
4392 /* We cannot do anything if there is an event, so ignore it for now */
4393 const fs_reg shader_clock
= get_timestamp(bld
);
4394 const fs_reg srcs
[] = { component(shader_clock
, 0),
4395 component(shader_clock
, 1) };
4396 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4400 case nir_intrinsic_image_samples
:
4401 /* The driver does not support multi-sampled images. */
4402 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4405 case nir_intrinsic_load_uniform
: {
4406 /* Offsets are in bytes but they should always aligned to
4409 assert(instr
->const_index
[0] % 4 == 0 ||
4410 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4412 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4414 if (nir_src_is_const(instr
->src
[0])) {
4415 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4416 assert(load_offset
% type_sz(dest
.type
) == 0);
4417 /* For 16-bit types we add the module of the const_index[0]
4418 * offset to access to not 32-bit aligned element
4420 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4422 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4423 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4426 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4427 BRW_REGISTER_TYPE_UD
);
4429 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4430 * go past the end of the uniform. In order to keep the n'th
4431 * component from running past, we subtract off the size of all but
4432 * one component of the vector.
4434 assert(instr
->const_index
[1] >=
4435 instr
->num_components
* (int) type_sz(dest
.type
));
4436 unsigned read_size
= instr
->const_index
[1] -
4437 (instr
->num_components
- 1) * type_sz(dest
.type
);
4439 bool supports_64bit_indirects
=
4440 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4442 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4443 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4444 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4445 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4446 indirect
, brw_imm_ud(read_size
));
4449 const unsigned num_mov_indirects
=
4450 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4451 /* We read a little bit less per MOV INDIRECT, as they are now
4452 * 32-bits ones instead of 64-bit. Fix read_size then.
4454 const unsigned read_size_32bit
= read_size
-
4455 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4456 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4457 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4458 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4459 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4460 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4461 indirect
, brw_imm_ud(read_size_32bit
));
4469 case nir_intrinsic_load_ubo
: {
4471 if (nir_src_is_const(instr
->src
[0])) {
4472 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4473 nir_src_as_uint(instr
->src
[0]);
4474 surf_index
= brw_imm_ud(index
);
4476 /* The block index is not a constant. Evaluate the index expression
4477 * per-channel and add the base UBO index; we have to select a value
4478 * from any live channel.
4480 surf_index
= vgrf(glsl_type::uint_type
);
4481 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4482 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4483 surf_index
= bld
.emit_uniformize(surf_index
);
4486 if (!nir_src_is_const(instr
->src
[1])) {
4487 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4488 BRW_REGISTER_TYPE_UD
);
4490 for (int i
= 0; i
< instr
->num_components
; i
++)
4491 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4492 base_offset
, i
* type_sz(dest
.type
));
4494 prog_data
->has_ubo_pull
= true;
4496 /* Even if we are loading doubles, a pull constant load will load
4497 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4498 * need to load a full dvec4 we will have to emit 2 loads. This is
4499 * similar to demote_pull_constants(), except that in that case we
4500 * see individual accesses to each component of the vector and then
4501 * we let CSE deal with duplicate loads. Here we see a vector access
4502 * and we have to split it if necessary.
4504 const unsigned type_size
= type_sz(dest
.type
);
4505 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4507 /* See if we've selected this as a push constant candidate */
4508 if (nir_src_is_const(instr
->src
[0])) {
4509 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4510 const unsigned offset_256b
= load_offset
/ 32;
4513 for (int i
= 0; i
< 4; i
++) {
4514 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4515 if (range
->block
== ubo_block
&&
4516 offset_256b
>= range
->start
&&
4517 offset_256b
< range
->start
+ range
->length
) {
4519 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4520 push_reg
.offset
= load_offset
- 32 * range
->start
;
4525 if (push_reg
.file
!= BAD_FILE
) {
4526 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4527 bld
.MOV(offset(dest
, bld
, i
),
4528 byte_offset(push_reg
, i
* type_size
));
4534 prog_data
->has_ubo_pull
= true;
4536 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4537 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4538 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4540 for (unsigned c
= 0; c
< instr
->num_components
;) {
4541 const unsigned base
= load_offset
+ c
* type_size
;
4542 /* Number of usable components in the next block-aligned load. */
4543 const unsigned count
= MIN2(instr
->num_components
- c
,
4544 (block_sz
- base
% block_sz
) / type_size
);
4546 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4547 packed_consts
, surf_index
,
4548 brw_imm_ud(base
& ~(block_sz
- 1)));
4550 const fs_reg consts
=
4551 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4554 for (unsigned d
= 0; d
< count
; d
++)
4555 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4563 case nir_intrinsic_load_global
: {
4564 assert(devinfo
->gen
>= 8);
4566 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4567 assert(nir_intrinsic_align(instr
) > 0);
4568 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4569 nir_intrinsic_align(instr
) >= 4) {
4570 assert(nir_dest_num_components(instr
->dest
) <= 4);
4571 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4573 get_nir_src(instr
->src
[0]), /* Address */
4574 fs_reg(), /* No source data */
4575 brw_imm_ud(instr
->num_components
));
4576 inst
->size_written
= instr
->num_components
*
4577 inst
->dst
.component_size(inst
->exec_size
);
4579 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4580 assert(nir_dest_num_components(instr
->dest
) == 1);
4581 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4582 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4584 get_nir_src(instr
->src
[0]), /* Address */
4585 fs_reg(), /* No source data */
4586 brw_imm_ud(bit_size
));
4587 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4592 case nir_intrinsic_store_global
:
4593 assert(devinfo
->gen
>= 8);
4595 if (stage
== MESA_SHADER_FRAGMENT
)
4596 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4598 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4599 assert(nir_intrinsic_write_mask(instr
) ==
4600 (1u << instr
->num_components
) - 1);
4601 assert(nir_intrinsic_align(instr
) > 0);
4602 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4603 nir_intrinsic_align(instr
) >= 4) {
4604 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4605 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4607 get_nir_src(instr
->src
[1]), /* Address */
4608 get_nir_src(instr
->src
[0]), /* Data */
4609 brw_imm_ud(instr
->num_components
));
4611 assert(nir_src_num_components(instr
->src
[0]) == 1);
4612 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4613 brw_reg_type data_type
=
4614 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4615 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4616 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4617 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4619 get_nir_src(instr
->src
[1]), /* Address */
4621 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4625 case nir_intrinsic_global_atomic_add
:
4626 case nir_intrinsic_global_atomic_imin
:
4627 case nir_intrinsic_global_atomic_umin
:
4628 case nir_intrinsic_global_atomic_imax
:
4629 case nir_intrinsic_global_atomic_umax
:
4630 case nir_intrinsic_global_atomic_and
:
4631 case nir_intrinsic_global_atomic_or
:
4632 case nir_intrinsic_global_atomic_xor
:
4633 case nir_intrinsic_global_atomic_exchange
:
4634 case nir_intrinsic_global_atomic_comp_swap
:
4635 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4637 case nir_intrinsic_global_atomic_fmin
:
4638 case nir_intrinsic_global_atomic_fmax
:
4639 case nir_intrinsic_global_atomic_fcomp_swap
:
4640 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4643 case nir_intrinsic_load_ssbo
: {
4644 assert(devinfo
->gen
>= 7);
4646 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4647 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4648 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4649 get_nir_ssbo_intrinsic_index(bld
, instr
);
4650 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4651 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4653 /* Make dest unsigned because that's what the temporary will be */
4654 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4656 /* Read the vector */
4657 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4658 assert(nir_intrinsic_align(instr
) > 0);
4659 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4660 nir_intrinsic_align(instr
) >= 4) {
4661 assert(nir_dest_num_components(instr
->dest
) <= 4);
4662 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4664 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4665 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4666 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4668 assert(nir_dest_num_components(instr
->dest
) == 1);
4669 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4671 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4672 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4673 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4674 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4679 case nir_intrinsic_store_ssbo
: {
4680 assert(devinfo
->gen
>= 7);
4682 if (stage
== MESA_SHADER_FRAGMENT
)
4683 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4685 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4686 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4687 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4688 get_nir_ssbo_intrinsic_index(bld
, instr
);
4689 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4690 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4692 fs_reg data
= get_nir_src(instr
->src
[0]);
4693 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4695 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4696 assert(nir_intrinsic_write_mask(instr
) ==
4697 (1u << instr
->num_components
) - 1);
4698 assert(nir_intrinsic_align(instr
) > 0);
4699 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4700 nir_intrinsic_align(instr
) >= 4) {
4701 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4702 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4703 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4704 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4705 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4707 assert(nir_src_num_components(instr
->src
[0]) == 1);
4708 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4710 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4711 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4713 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4714 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4719 case nir_intrinsic_store_output
: {
4720 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4721 fs_reg src
= get_nir_src(instr
->src
[0]);
4723 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4724 unsigned num_components
= instr
->num_components
;
4725 unsigned first_component
= nir_intrinsic_component(instr
);
4727 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4728 4 * store_offset
), src
.type
);
4729 for (unsigned j
= 0; j
< num_components
; j
++) {
4730 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4731 offset(src
, bld
, j
));
4736 case nir_intrinsic_ssbo_atomic_add
:
4737 case nir_intrinsic_ssbo_atomic_imin
:
4738 case nir_intrinsic_ssbo_atomic_umin
:
4739 case nir_intrinsic_ssbo_atomic_imax
:
4740 case nir_intrinsic_ssbo_atomic_umax
:
4741 case nir_intrinsic_ssbo_atomic_and
:
4742 case nir_intrinsic_ssbo_atomic_or
:
4743 case nir_intrinsic_ssbo_atomic_xor
:
4744 case nir_intrinsic_ssbo_atomic_exchange
:
4745 case nir_intrinsic_ssbo_atomic_comp_swap
:
4746 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4748 case nir_intrinsic_ssbo_atomic_fmin
:
4749 case nir_intrinsic_ssbo_atomic_fmax
:
4750 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4751 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4754 case nir_intrinsic_get_buffer_size
: {
4755 assert(nir_src_num_components(instr
->src
[0]) == 1);
4756 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4757 nir_src_as_uint(instr
->src
[0]) : 0;
4759 /* A resinfo's sampler message is used to get the buffer size. The
4760 * SIMD8's writeback message consists of four registers and SIMD16's
4761 * writeback message consists of 8 destination registers (two per each
4762 * component). Because we are only interested on the first channel of
4763 * the first returned component, where resinfo returns the buffer size
4764 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4765 * the dispatch width.
4767 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4768 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4769 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4772 ubld
.MOV(src_payload
, brw_imm_d(0));
4774 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4775 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4776 src_payload
, brw_imm_ud(index
));
4777 inst
->header_size
= 0;
4779 inst
->size_written
= 4 * REG_SIZE
;
4781 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4783 * "Out-of-bounds checking is always performed at a DWord granularity. If
4784 * any part of the DWord is out-of-bounds then the whole DWord is
4785 * considered out-of-bounds."
4787 * This implies that types with size smaller than 4-bytes need to be
4788 * padded if they don't complete the last dword of the buffer. But as we
4789 * need to maintain the original size we need to reverse the padding
4790 * calculation to return the correct size to know the number of elements
4791 * of an unsized array. As we stored in the last two bits of the surface
4792 * size the needed padding for the buffer, we calculate here the
4793 * original buffer_size reversing the surface_size calculation:
4795 * surface_size = isl_align(buffer_size, 4) +
4796 * (isl_align(buffer_size) - buffer_size)
4798 * buffer_size = surface_size & ~3 - surface_size & 3
4801 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4802 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4803 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4805 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4806 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4807 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4809 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4813 case nir_intrinsic_load_scratch
: {
4814 assert(devinfo
->gen
>= 7);
4816 assert(nir_dest_num_components(instr
->dest
) == 1);
4817 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4818 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4820 if (devinfo
->gen
>= 8) {
4821 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4822 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4824 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4827 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4828 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4829 const fs_reg nir_addr
= get_nir_src(instr
->src
[0]);
4831 /* Make dest unsigned because that's what the temporary will be */
4832 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4834 /* Read the vector */
4835 assert(nir_dest_num_components(instr
->dest
) == 1);
4836 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4837 assert(nir_intrinsic_align(instr
) > 1);
4838 if (nir_dest_bit_size(instr
->dest
) >= 4 &&
4839 nir_intrinsic_align(instr
) >= 4) {
4840 /* The offset for a DWORD scattered message is in dwords. */
4841 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4842 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4844 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
,
4845 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4847 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4848 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4850 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4851 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4852 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4853 bld
.MOV(dest
, read_result
);
4858 case nir_intrinsic_store_scratch
: {
4859 assert(devinfo
->gen
>= 7);
4861 assert(nir_src_num_components(instr
->src
[0]) == 1);
4862 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4863 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4865 if (devinfo
->gen
>= 8) {
4866 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4867 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4869 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4872 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4873 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4874 const fs_reg nir_addr
= get_nir_src(instr
->src
[1]);
4876 fs_reg data
= get_nir_src(instr
->src
[0]);
4877 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4879 assert(nir_src_num_components(instr
->src
[0]) == 1);
4880 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4881 assert(nir_intrinsic_write_mask(instr
) == 1);
4882 assert(nir_intrinsic_align(instr
) > 1);
4883 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4884 nir_intrinsic_align(instr
) >= 4) {
4885 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4887 /* The offset for a DWORD scattered message is in dwords. */
4888 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4889 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4891 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
,
4892 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4894 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4895 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4897 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4898 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4900 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4901 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4906 case nir_intrinsic_load_subgroup_size
:
4907 /* This should only happen for fragment shaders because every other case
4908 * is lowered in NIR so we can optimize on it.
4910 assert(stage
== MESA_SHADER_FRAGMENT
);
4911 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4914 case nir_intrinsic_load_subgroup_invocation
:
4915 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4916 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4919 case nir_intrinsic_load_subgroup_eq_mask
:
4920 case nir_intrinsic_load_subgroup_ge_mask
:
4921 case nir_intrinsic_load_subgroup_gt_mask
:
4922 case nir_intrinsic_load_subgroup_le_mask
:
4923 case nir_intrinsic_load_subgroup_lt_mask
:
4924 unreachable("not reached");
4926 case nir_intrinsic_vote_any
: {
4927 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4929 /* The any/all predicates do not consider channel enables. To prevent
4930 * dead channels from affecting the result, we initialize the flag with
4931 * with the identity value for the logical operation.
4933 if (dispatch_width
== 32) {
4934 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4935 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4938 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4940 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4942 /* For some reason, the any/all predicates don't work properly with
4943 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4944 * doesn't read the correct subset of the flag register and you end up
4945 * getting garbage in the second half. Work around this by using a pair
4946 * of 1-wide MOVs and scattering the result.
4948 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4949 ubld
.MOV(res1
, brw_imm_d(0));
4950 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4951 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4952 BRW_PREDICATE_ALIGN1_ANY32H
,
4953 ubld
.MOV(res1
, brw_imm_d(-1)));
4955 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4958 case nir_intrinsic_vote_all
: {
4959 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4961 /* The any/all predicates do not consider channel enables. To prevent
4962 * dead channels from affecting the result, we initialize the flag with
4963 * with the identity value for the logical operation.
4965 if (dispatch_width
== 32) {
4966 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4967 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4968 brw_imm_ud(0xffffffff));
4970 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4972 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4974 /* For some reason, the any/all predicates don't work properly with
4975 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4976 * doesn't read the correct subset of the flag register and you end up
4977 * getting garbage in the second half. Work around this by using a pair
4978 * of 1-wide MOVs and scattering the result.
4980 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4981 ubld
.MOV(res1
, brw_imm_d(0));
4982 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4983 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4984 BRW_PREDICATE_ALIGN1_ALL32H
,
4985 ubld
.MOV(res1
, brw_imm_d(-1)));
4987 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4990 case nir_intrinsic_vote_feq
:
4991 case nir_intrinsic_vote_ieq
: {
4992 fs_reg value
= get_nir_src(instr
->src
[0]);
4993 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4994 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4995 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4996 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4999 fs_reg uniformized
= bld
.emit_uniformize(value
);
5000 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5002 /* The any/all predicates do not consider channel enables. To prevent
5003 * dead channels from affecting the result, we initialize the flag with
5004 * with the identity value for the logical operation.
5006 if (dispatch_width
== 32) {
5007 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
5008 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
5009 brw_imm_ud(0xffffffff));
5011 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
5013 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
5015 /* For some reason, the any/all predicates don't work properly with
5016 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
5017 * doesn't read the correct subset of the flag register and you end up
5018 * getting garbage in the second half. Work around this by using a pair
5019 * of 1-wide MOVs and scattering the result.
5021 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
5022 ubld
.MOV(res1
, brw_imm_d(0));
5023 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
5024 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
5025 BRW_PREDICATE_ALIGN1_ALL32H
,
5026 ubld
.MOV(res1
, brw_imm_d(-1)));
5028 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
5032 case nir_intrinsic_ballot
: {
5033 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
5034 BRW_REGISTER_TYPE_UD
);
5035 struct brw_reg flag
= brw_flag_reg(0, 0);
5036 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
5037 * as f0.0. This is a problem for fragment programs as we currently use
5038 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
5039 * programs yet so this isn't a problem. When we do, something will
5042 if (dispatch_width
== 32)
5043 flag
.type
= BRW_REGISTER_TYPE_UD
;
5045 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
5046 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
5048 if (instr
->dest
.ssa
.bit_size
> 32) {
5049 dest
.type
= BRW_REGISTER_TYPE_UQ
;
5051 dest
.type
= BRW_REGISTER_TYPE_UD
;
5053 bld
.MOV(dest
, flag
);
5057 case nir_intrinsic_read_invocation
: {
5058 const fs_reg value
= get_nir_src(instr
->src
[0]);
5059 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
5060 fs_reg tmp
= bld
.vgrf(value
.type
);
5062 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
5063 bld
.emit_uniformize(invocation
));
5065 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
5069 case nir_intrinsic_read_first_invocation
: {
5070 const fs_reg value
= get_nir_src(instr
->src
[0]);
5071 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
5075 case nir_intrinsic_shuffle
: {
5076 const fs_reg value
= get_nir_src(instr
->src
[0]);
5077 const fs_reg index
= get_nir_src(instr
->src
[1]);
5079 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
5083 case nir_intrinsic_first_invocation
: {
5084 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5085 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
5086 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
5087 fs_reg(component(tmp
, 0)));
5091 case nir_intrinsic_quad_broadcast
: {
5092 const fs_reg value
= get_nir_src(instr
->src
[0]);
5093 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
5095 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
5096 value
, brw_imm_ud(index
), brw_imm_ud(4));
5100 case nir_intrinsic_quad_swap_horizontal
: {
5101 const fs_reg value
= get_nir_src(instr
->src
[0]);
5102 const fs_reg tmp
= bld
.vgrf(value
.type
);
5103 if (devinfo
->gen
<= 7) {
5104 /* The hardware doesn't seem to support these crazy regions with
5105 * compressed instructions on gen7 and earlier so we fall back to
5106 * using quad swizzles. Fortunately, we don't support 64-bit
5107 * anything in Vulkan on gen7.
5109 assert(nir_src_bit_size(instr
->src
[0]) == 32);
5110 const fs_builder ubld
= bld
.exec_all();
5111 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5112 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
5113 bld
.MOV(retype(dest
, value
.type
), tmp
);
5115 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
5117 const fs_reg src_left
= horiz_stride(value
, 2);
5118 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
5119 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
5120 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
5122 ubld
.MOV(tmp_left
, src_right
);
5123 ubld
.MOV(tmp_right
, src_left
);
5126 bld
.MOV(retype(dest
, value
.type
), tmp
);
5130 case nir_intrinsic_quad_swap_vertical
: {
5131 const fs_reg value
= get_nir_src(instr
->src
[0]);
5132 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5133 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5134 const fs_reg tmp
= bld
.vgrf(value
.type
);
5135 const fs_builder ubld
= bld
.exec_all();
5136 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5137 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5138 bld
.MOV(retype(dest
, value
.type
), tmp
);
5140 /* For larger data types, we have to either emit dispatch_width many
5141 * MOVs or else fall back to doing indirects.
5143 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5144 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5146 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5151 case nir_intrinsic_quad_swap_diagonal
: {
5152 const fs_reg value
= get_nir_src(instr
->src
[0]);
5153 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5154 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5155 const fs_reg tmp
= bld
.vgrf(value
.type
);
5156 const fs_builder ubld
= bld
.exec_all();
5157 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5158 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5159 bld
.MOV(retype(dest
, value
.type
), tmp
);
5161 /* For larger data types, we have to either emit dispatch_width many
5162 * MOVs or else fall back to doing indirects.
5164 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5165 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5167 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5172 case nir_intrinsic_reduce
: {
5173 fs_reg src
= get_nir_src(instr
->src
[0]);
5174 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5175 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5176 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5177 cluster_size
= dispatch_width
;
5179 /* Figure out the source type */
5180 src
.type
= brw_type_for_nir_type(devinfo
,
5181 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5182 nir_src_bit_size(instr
->src
[0])));
5184 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5185 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5186 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5188 /* There are a couple of register region issues that make things
5189 * complicated for 8-bit types:
5191 * 1. Only raw moves are allowed to write to a packed 8-bit
5193 * 2. If we use a strided destination, the efficient way to do scan
5194 * operations ends up using strides that are too big to encode in
5197 * To get around these issues, we just do all 8-bit scan operations in
5198 * 16 bits. It's actually fewer instructions than what we'd have to do
5199 * if we were trying to do it in native 8-bit types and the results are
5200 * the same once we truncate to 8 bits at the end.
5202 brw_reg_type scan_type
= src
.type
;
5203 if (type_sz(scan_type
) == 1)
5204 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5206 /* Set up a register for all of our scratching around and initialize it
5207 * to reduction operation's identity value.
5209 fs_reg scan
= bld
.vgrf(scan_type
);
5210 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5212 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5214 dest
.type
= src
.type
;
5215 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5216 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5217 * the distance between clusters is at least 2 GRFs. In this case,
5218 * we don't need the weird striding of the CLUSTER_BROADCAST
5219 * instruction and can just do regular MOVs.
5221 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5222 const unsigned groups
=
5223 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5224 const unsigned group_size
= dispatch_width
/ groups
;
5225 for (unsigned i
= 0; i
< groups
; i
++) {
5226 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5227 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5228 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5229 component(scan
, comp
));
5232 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5233 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5238 case nir_intrinsic_inclusive_scan
:
5239 case nir_intrinsic_exclusive_scan
: {
5240 fs_reg src
= get_nir_src(instr
->src
[0]);
5241 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5243 /* Figure out the source type */
5244 src
.type
= brw_type_for_nir_type(devinfo
,
5245 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5246 nir_src_bit_size(instr
->src
[0])));
5248 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5249 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5250 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5252 /* There are a couple of register region issues that make things
5253 * complicated for 8-bit types:
5255 * 1. Only raw moves are allowed to write to a packed 8-bit
5257 * 2. If we use a strided destination, the efficient way to do scan
5258 * operations ends up using strides that are too big to encode in
5261 * To get around these issues, we just do all 8-bit scan operations in
5262 * 16 bits. It's actually fewer instructions than what we'd have to do
5263 * if we were trying to do it in native 8-bit types and the results are
5264 * the same once we truncate to 8 bits at the end.
5266 brw_reg_type scan_type
= src
.type
;
5267 if (type_sz(scan_type
) == 1)
5268 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5270 /* Set up a register for all of our scratching around and initialize it
5271 * to reduction operation's identity value.
5273 fs_reg scan
= bld
.vgrf(scan_type
);
5274 const fs_builder allbld
= bld
.exec_all();
5275 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5277 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5278 /* Exclusive scan is a bit harder because we have to do an annoying
5279 * shift of the contents before we can begin. To make things worse,
5280 * we can't do this with a normal stride; we have to use indirects.
5282 fs_reg shifted
= bld
.vgrf(scan_type
);
5283 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5284 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5286 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5287 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5291 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5293 bld
.MOV(retype(dest
, src
.type
), scan
);
5297 case nir_intrinsic_begin_invocation_interlock
: {
5298 const fs_builder ubld
= bld
.group(8, 0);
5299 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5301 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5302 ->size_written
= 2 * REG_SIZE
;
5306 case nir_intrinsic_end_invocation_interlock
: {
5307 /* For endInvocationInterlock(), we need to insert a memory fence which
5308 * stalls in the shader until the memory transactions prior to that
5309 * fence are complete. This ensures that the shader does not end before
5310 * any writes from its critical section have landed. Otherwise, you can
5311 * end up with a case where the next invocation on that pixel properly
5312 * stalls for previous FS invocation on its pixel to complete but
5313 * doesn't actually wait for the dataport memory transactions from that
5314 * thread to land before submitting its own.
5316 const fs_builder ubld
= bld
.group(8, 0);
5317 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5318 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5319 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5320 ->size_written
= 2 * REG_SIZE
;
5325 unreachable("unknown intrinsic");
5330 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5331 int op
, nir_intrinsic_instr
*instr
)
5333 if (stage
== MESA_SHADER_FRAGMENT
)
5334 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5336 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5337 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5338 * appear to exist. However, if you look at Vol 2a, there are no message
5339 * descriptors provided for Qword atomic ops except for A64 messages.
5341 assert(nir_dest_bit_size(instr
->dest
) == 32);
5344 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5345 dest
= get_nir_dest(instr
->dest
);
5347 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5348 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5349 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5350 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5351 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5354 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5355 data
= get_nir_src(instr
->src
[2]);
5357 if (op
== BRW_AOP_CMPWR
) {
5358 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5359 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5360 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5363 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5365 /* Emit the actual atomic operation */
5367 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5368 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5372 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5373 int op
, nir_intrinsic_instr
*instr
)
5375 if (stage
== MESA_SHADER_FRAGMENT
)
5376 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5379 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5380 dest
= get_nir_dest(instr
->dest
);
5382 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5383 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5384 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5385 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5386 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5388 fs_reg data
= get_nir_src(instr
->src
[2]);
5389 if (op
== BRW_AOP_FCMPWR
) {
5390 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5391 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5392 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5395 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5397 /* Emit the actual atomic operation */
5399 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5400 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5404 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5405 int op
, nir_intrinsic_instr
*instr
)
5408 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5409 dest
= get_nir_dest(instr
->dest
);
5411 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5412 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5413 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5414 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5417 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5418 data
= get_nir_src(instr
->src
[1]);
5419 if (op
== BRW_AOP_CMPWR
) {
5420 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5421 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5422 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5425 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5427 /* Get the offset */
5428 if (nir_src_is_const(instr
->src
[0])) {
5429 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5430 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5432 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5433 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5434 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5435 brw_imm_ud(instr
->const_index
[0]));
5438 /* Emit the actual atomic operation operation */
5440 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5441 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5445 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5446 int op
, nir_intrinsic_instr
*instr
)
5449 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5450 dest
= get_nir_dest(instr
->dest
);
5452 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5453 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5454 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5455 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5457 fs_reg data
= get_nir_src(instr
->src
[1]);
5458 if (op
== BRW_AOP_FCMPWR
) {
5459 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5460 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5461 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5464 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5466 /* Get the offset */
5467 if (nir_src_is_const(instr
->src
[0])) {
5468 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5469 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5471 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5472 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5473 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5474 brw_imm_ud(instr
->const_index
[0]));
5477 /* Emit the actual atomic operation operation */
5479 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5480 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5484 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5485 int op
, nir_intrinsic_instr
*instr
)
5487 if (stage
== MESA_SHADER_FRAGMENT
)
5488 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5491 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5492 dest
= get_nir_dest(instr
->dest
);
5494 fs_reg addr
= get_nir_src(instr
->src
[0]);
5497 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5498 data
= get_nir_src(instr
->src
[1]);
5500 if (op
== BRW_AOP_CMPWR
) {
5501 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5502 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5503 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5507 if (nir_dest_bit_size(instr
->dest
) == 64) {
5508 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5509 dest
, addr
, data
, brw_imm_ud(op
));
5511 assert(nir_dest_bit_size(instr
->dest
) == 32);
5512 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5513 dest
, addr
, data
, brw_imm_ud(op
));
5518 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5519 int op
, nir_intrinsic_instr
*instr
)
5521 if (stage
== MESA_SHADER_FRAGMENT
)
5522 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5524 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5525 fs_reg dest
= get_nir_dest(instr
->dest
);
5527 fs_reg addr
= get_nir_src(instr
->src
[0]);
5529 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5530 fs_reg data
= get_nir_src(instr
->src
[1]);
5532 if (op
== BRW_AOP_FCMPWR
) {
5533 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5534 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5535 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5539 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5540 dest
, addr
, data
, brw_imm_ud(op
));
5544 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5546 unsigned texture
= instr
->texture_index
;
5547 unsigned sampler
= instr
->sampler_index
;
5549 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5551 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5552 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5554 int lod_components
= 0;
5556 /* The hardware requires a LOD for buffer textures */
5557 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5558 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5560 uint32_t header_bits
= 0;
5561 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5562 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5563 switch (instr
->src
[i
].src_type
) {
5564 case nir_tex_src_bias
:
5565 srcs
[TEX_LOGICAL_SRC_LOD
] =
5566 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5568 case nir_tex_src_comparator
:
5569 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5571 case nir_tex_src_coord
:
5572 switch (instr
->op
) {
5574 case nir_texop_txf_ms
:
5575 case nir_texop_txf_ms_mcs
:
5576 case nir_texop_samples_identical
:
5577 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5580 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5584 case nir_tex_src_ddx
:
5585 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5586 lod_components
= nir_tex_instr_src_size(instr
, i
);
5588 case nir_tex_src_ddy
:
5589 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5591 case nir_tex_src_lod
:
5592 switch (instr
->op
) {
5594 srcs
[TEX_LOGICAL_SRC_LOD
] =
5595 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5598 srcs
[TEX_LOGICAL_SRC_LOD
] =
5599 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5602 srcs
[TEX_LOGICAL_SRC_LOD
] =
5603 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5607 case nir_tex_src_min_lod
:
5608 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5609 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5611 case nir_tex_src_ms_index
:
5612 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5615 case nir_tex_src_offset
: {
5616 uint32_t offset_bits
= 0;
5617 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5618 header_bits
|= offset_bits
;
5620 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5621 retype(src
, BRW_REGISTER_TYPE_D
);
5626 case nir_tex_src_projector
:
5627 unreachable("should be lowered");
5629 case nir_tex_src_texture_offset
: {
5630 /* Emit code to evaluate the actual indexing expression */
5631 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5632 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5633 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5637 case nir_tex_src_sampler_offset
: {
5638 /* Emit code to evaluate the actual indexing expression */
5639 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5640 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5641 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5645 case nir_tex_src_texture_handle
:
5646 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5647 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5648 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5651 case nir_tex_src_sampler_handle
:
5652 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5653 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5654 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5657 case nir_tex_src_ms_mcs
:
5658 assert(instr
->op
== nir_texop_txf_ms
);
5659 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5662 case nir_tex_src_plane
: {
5663 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5664 const uint32_t texture_index
=
5665 instr
->texture_index
+
5666 stage_prog_data
->binding_table
.plane_start
[plane
] -
5667 stage_prog_data
->binding_table
.texture_start
;
5669 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5674 unreachable("unknown texture source");
5678 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5679 (instr
->op
== nir_texop_txf_ms
||
5680 instr
->op
== nir_texop_samples_identical
)) {
5681 if (devinfo
->gen
>= 7 &&
5682 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5683 srcs
[TEX_LOGICAL_SRC_MCS
] =
5684 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5685 instr
->coord_components
,
5686 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5687 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5689 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5693 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5694 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5697 switch (instr
->op
) {
5699 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5702 opcode
= FS_OPCODE_TXB_LOGICAL
;
5705 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5708 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5711 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5713 case nir_texop_txf_ms
:
5714 if ((key_tex
->msaa_16
& (1 << sampler
)))
5715 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5717 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5719 case nir_texop_txf_ms_mcs
:
5720 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5722 case nir_texop_query_levels
:
5724 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5727 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5730 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5731 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5733 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5735 case nir_texop_texture_samples
:
5736 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5738 case nir_texop_samples_identical
: {
5739 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5741 /* If mcs is an immediate value, it means there is no MCS. In that case
5742 * just return false.
5744 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5745 bld
.MOV(dst
, brw_imm_ud(0u));
5746 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5747 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5748 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5749 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5750 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5752 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5753 BRW_CONDITIONAL_EQ
);
5758 unreachable("unknown texture opcode");
5761 if (instr
->op
== nir_texop_tg4
) {
5762 if (instr
->component
== 1 &&
5763 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5764 /* gather4 sampler is broken for green channel on RG32F --
5765 * we must ask for blue instead.
5767 header_bits
|= 2 << 16;
5769 header_bits
|= instr
->component
<< 16;
5773 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5774 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5775 inst
->offset
= header_bits
;
5777 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5778 if (devinfo
->gen
>= 9 &&
5779 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5780 unsigned write_mask
= instr
->dest
.is_ssa
?
5781 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5782 (1 << dest_size
) - 1;
5783 assert(write_mask
!= 0); /* dead code should have been eliminated */
5784 inst
->size_written
= util_last_bit(write_mask
) *
5785 inst
->dst
.component_size(inst
->exec_size
);
5787 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5790 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5791 inst
->shadow_compare
= true;
5793 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5794 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5797 for (unsigned i
= 0; i
< dest_size
; i
++)
5798 nir_dest
[i
] = offset(dst
, bld
, i
);
5800 if (instr
->op
== nir_texop_query_levels
) {
5801 /* # levels is in .w */
5802 nir_dest
[0] = offset(dst
, bld
, 3);
5803 } else if (instr
->op
== nir_texop_txs
&&
5804 dest_size
>= 3 && devinfo
->gen
< 7) {
5805 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5806 fs_reg depth
= offset(dst
, bld
, 2);
5807 nir_dest
[2] = vgrf(glsl_type::int_type
);
5808 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5811 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5815 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5817 switch (instr
->type
) {
5818 case nir_jump_break
:
5819 bld
.emit(BRW_OPCODE_BREAK
);
5821 case nir_jump_continue
:
5822 bld
.emit(BRW_OPCODE_CONTINUE
);
5824 case nir_jump_return
:
5826 unreachable("unknown jump");
5831 * This helper takes a source register and un/shuffles it into the destination
5834 * If source type size is smaller than destination type size the operation
5835 * needed is a component shuffle. The opposite case would be an unshuffle. If
5836 * source/destination type size is equal a shuffle is done that would be
5837 * equivalent to a simple MOV.
5839 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5840 * components .xyz 16-bit vector on SIMD8 would be.
5842 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5843 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5845 * This helper will return the following 2 32-bit components with the 16-bit
5848 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5849 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5851 * For unshuffle, the example would be the opposite, a 64-bit type source
5852 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5855 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5856 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5857 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5858 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5860 * The returned result would be the following 4 32-bit components unshuffled:
5862 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5863 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5864 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5865 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5867 * - Source and destination register must not be overlapped.
5868 * - components units are measured in terms of the smaller type between
5869 * source and destination because we are un/shuffling the smaller
5870 * components from/into the bigger ones.
5871 * - first_component parameter allows skipping source components.
5874 shuffle_src_to_dst(const fs_builder
&bld
,
5877 uint32_t first_component
,
5878 uint32_t components
)
5880 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5881 assert(!regions_overlap(dst
,
5882 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5883 offset(src
, bld
, first_component
),
5884 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5885 for (unsigned i
= 0; i
< components
; i
++) {
5886 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5887 offset(src
, bld
, i
+ first_component
));
5889 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5890 /* Source is shuffled into destination */
5891 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5892 assert(!regions_overlap(dst
,
5893 type_sz(dst
.type
) * bld
.dispatch_width() *
5894 DIV_ROUND_UP(components
, size_ratio
),
5895 offset(src
, bld
, first_component
),
5896 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5898 brw_reg_type shuffle_type
=
5899 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5900 BRW_REGISTER_TYPE_D
);
5901 for (unsigned i
= 0; i
< components
; i
++) {
5902 fs_reg shuffle_component_i
=
5903 subscript(offset(dst
, bld
, i
/ size_ratio
),
5904 shuffle_type
, i
% size_ratio
);
5905 bld
.MOV(shuffle_component_i
,
5906 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5909 /* Source is unshuffled into destination */
5910 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5911 assert(!regions_overlap(dst
,
5912 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5913 offset(src
, bld
, first_component
/ size_ratio
),
5914 type_sz(src
.type
) * bld
.dispatch_width() *
5915 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5918 brw_reg_type shuffle_type
=
5919 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5920 BRW_REGISTER_TYPE_D
);
5921 for (unsigned i
= 0; i
< components
; i
++) {
5922 fs_reg shuffle_component_i
=
5923 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5924 shuffle_type
, (first_component
+ i
) % size_ratio
);
5925 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5926 shuffle_component_i
);
5932 shuffle_from_32bit_read(const fs_builder
&bld
,
5935 uint32_t first_component
,
5936 uint32_t components
)
5938 assert(type_sz(src
.type
) == 4);
5940 /* This function takes components in units of the destination type while
5941 * shuffle_src_to_dst takes components in units of the smallest type
5943 if (type_sz(dst
.type
) > 4) {
5944 assert(type_sz(dst
.type
) == 8);
5945 first_component
*= 2;
5949 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5953 setup_imm_df(const fs_builder
&bld
, double v
)
5955 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5956 assert(devinfo
->gen
>= 7);
5958 if (devinfo
->gen
>= 8)
5959 return brw_imm_df(v
);
5961 /* gen7.5 does not support DF immediates straighforward but the DIM
5962 * instruction allows to set the 64-bit immediate value.
5964 if (devinfo
->is_haswell
) {
5965 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5966 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5967 ubld
.DIM(dst
, brw_imm_df(v
));
5968 return component(dst
, 0);
5971 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5972 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5973 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5975 * Alternatively, we could also produce a normal VGRF (without stride 0)
5976 * by writing to all the channels in the VGRF, however, that would hit the
5977 * gen7 bug where we have to split writes that span more than 1 register
5978 * into instructions with a width of 4 (otherwise the write to the second
5979 * register written runs into an execmask hardware bug) which isn't very
5992 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5993 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5994 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5995 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5997 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
6001 setup_imm_b(const fs_builder
&bld
, int8_t v
)
6003 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
6004 bld
.MOV(tmp
, brw_imm_w(v
));
6009 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
6011 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
6012 bld
.MOV(tmp
, brw_imm_uw(v
));