2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
45 last_scratch
= ALIGN(nir
->scratch_size
, 4) * dispatch_width
;
47 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
, true);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add a uniform for the thread local id. It must be the last uniform
107 assert(uniforms
== prog_data
->nr_params
);
108 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
109 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
110 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 case nir_intrinsic_load_base_vertex
:
127 unreachable("should be lowered by nir_lower_system_values().");
129 case nir_intrinsic_load_vertex_id_zero_base
:
130 case nir_intrinsic_load_is_indexed_draw
:
131 case nir_intrinsic_load_first_vertex
:
132 case nir_intrinsic_load_instance_id
:
133 case nir_intrinsic_load_base_instance
:
134 case nir_intrinsic_load_draw_id
:
135 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
137 case nir_intrinsic_load_invocation_id
:
138 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
140 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
141 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
142 if (reg
->file
== BAD_FILE
) {
143 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
144 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
145 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
146 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
151 case nir_intrinsic_load_sample_pos
:
152 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
154 if (reg
->file
== BAD_FILE
)
155 *reg
= *v
->emit_samplepos_setup();
158 case nir_intrinsic_load_sample_id
:
159 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
160 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
161 if (reg
->file
== BAD_FILE
)
162 *reg
= *v
->emit_sampleid_setup();
165 case nir_intrinsic_load_sample_mask_in
:
166 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
167 assert(v
->devinfo
->gen
>= 7);
168 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
169 if (reg
->file
== BAD_FILE
)
170 *reg
= *v
->emit_samplemaskin_setup();
173 case nir_intrinsic_load_work_group_id
:
174 assert(v
->stage
== MESA_SHADER_COMPUTE
);
175 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
176 if (reg
->file
== BAD_FILE
)
177 *reg
= *v
->emit_cs_work_group_id_setup();
180 case nir_intrinsic_load_helper_invocation
:
181 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
182 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
183 if (reg
->file
== BAD_FILE
) {
184 const fs_builder abld
=
185 v
->bld
.annotate("gl_HelperInvocation", NULL
);
187 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
188 * pixel mask is in g1.7 of the thread payload.
190 * We move the per-channel pixel enable bit to the low bit of each
191 * channel by shifting the byte containing the pixel mask by the
192 * vector immediate 0x76543210UV.
194 * The region of <1,8,0> reads only 1 byte (the pixel masks for
195 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
196 * masks for 2 and 3) in SIMD16.
198 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
200 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
201 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
202 hbld
.SHR(offset(shifted
, hbld
, i
),
203 stride(retype(brw_vec1_grf(1 + i
, 7),
204 BRW_REGISTER_TYPE_UB
),
206 brw_imm_v(0x76543210));
209 /* A set bit in the pixel mask means the channel is enabled, but
210 * that is the opposite of gl_HelperInvocation so we need to invert
213 * The negate source-modifier bit of logical instructions on Gen8+
214 * performs 1's complement negation, so we can use that instead of
217 fs_reg inverted
= negate(shifted
);
218 if (v
->devinfo
->gen
< 8) {
219 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
220 abld
.NOT(inverted
, shifted
);
223 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
224 * with 1 and negating.
226 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
227 abld
.AND(anded
, inverted
, brw_imm_uw(1));
229 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
230 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
244 fs_visitor::nir_emit_system_values()
246 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
247 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
248 nir_system_values
[i
] = fs_reg();
251 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
252 * never end up using it.
255 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
256 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
257 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
259 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
260 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
261 if (dispatch_width
> 8)
262 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
263 if (dispatch_width
> 16) {
264 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
265 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
269 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
270 nir_foreach_block(block
, impl
)
271 emit_system_values_block(block
, this);
275 * Returns a type based on a reference_type (word, float, half-float) and a
278 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
280 * @FIXME: 64-bit return types are always DF on integer types to maintain
281 * compability with uses of DF previously to the introduction of int64
285 brw_reg_type_from_bit_size(const unsigned bit_size
,
286 const brw_reg_type reference_type
)
288 switch(reference_type
) {
289 case BRW_REGISTER_TYPE_HF
:
290 case BRW_REGISTER_TYPE_F
:
291 case BRW_REGISTER_TYPE_DF
:
294 return BRW_REGISTER_TYPE_HF
;
296 return BRW_REGISTER_TYPE_F
;
298 return BRW_REGISTER_TYPE_DF
;
300 unreachable("Invalid bit size");
302 case BRW_REGISTER_TYPE_B
:
303 case BRW_REGISTER_TYPE_W
:
304 case BRW_REGISTER_TYPE_D
:
305 case BRW_REGISTER_TYPE_Q
:
308 return BRW_REGISTER_TYPE_B
;
310 return BRW_REGISTER_TYPE_W
;
312 return BRW_REGISTER_TYPE_D
;
314 return BRW_REGISTER_TYPE_Q
;
316 unreachable("Invalid bit size");
318 case BRW_REGISTER_TYPE_UB
:
319 case BRW_REGISTER_TYPE_UW
:
320 case BRW_REGISTER_TYPE_UD
:
321 case BRW_REGISTER_TYPE_UQ
:
324 return BRW_REGISTER_TYPE_UB
;
326 return BRW_REGISTER_TYPE_UW
;
328 return BRW_REGISTER_TYPE_UD
;
330 return BRW_REGISTER_TYPE_UQ
;
332 unreachable("Invalid bit size");
335 unreachable("Unknown type");
340 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
342 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
343 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
344 nir_locals
[i
] = fs_reg();
347 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
348 unsigned array_elems
=
349 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
350 unsigned size
= array_elems
* reg
->num_components
;
351 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
352 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
353 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
356 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
359 nir_emit_cf_list(&impl
->body
);
363 fs_visitor::nir_emit_cf_list(exec_list
*list
)
365 exec_list_validate(list
);
366 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
367 switch (node
->type
) {
369 nir_emit_if(nir_cf_node_as_if(node
));
372 case nir_cf_node_loop
:
373 nir_emit_loop(nir_cf_node_as_loop(node
));
376 case nir_cf_node_block
:
377 nir_emit_block(nir_cf_node_as_block(node
));
381 unreachable("Invalid CFG node block");
387 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
392 /* If the condition has the form !other_condition, use other_condition as
393 * the source, but invert the predicate on the if instruction.
395 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
396 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
397 assert(!cond
->src
[0].negate
);
398 assert(!cond
->src
[0].abs
);
401 cond_reg
= get_nir_src(cond
->src
[0].src
);
404 cond_reg
= get_nir_src(if_stmt
->condition
);
407 /* first, put the condition into f0 */
408 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
409 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
410 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
412 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
414 nir_emit_cf_list(&if_stmt
->then_list
);
416 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
417 bld
.emit(BRW_OPCODE_ELSE
);
418 nir_emit_cf_list(&if_stmt
->else_list
);
421 bld
.emit(BRW_OPCODE_ENDIF
);
423 if (devinfo
->gen
< 7)
424 limit_dispatch_width(16, "Non-uniform control flow unsupported "
429 fs_visitor::nir_emit_loop(nir_loop
*loop
)
431 bld
.emit(BRW_OPCODE_DO
);
433 nir_emit_cf_list(&loop
->body
);
435 bld
.emit(BRW_OPCODE_WHILE
);
437 if (devinfo
->gen
< 7)
438 limit_dispatch_width(16, "Non-uniform control flow unsupported "
443 fs_visitor::nir_emit_block(nir_block
*block
)
445 nir_foreach_instr(instr
, block
) {
446 nir_emit_instr(instr
);
451 fs_visitor::nir_emit_instr(nir_instr
*instr
)
453 const fs_builder abld
= bld
.annotate(NULL
, instr
);
455 switch (instr
->type
) {
456 case nir_instr_type_alu
:
457 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
460 case nir_instr_type_deref
:
461 unreachable("All derefs should've been lowered");
464 case nir_instr_type_intrinsic
:
466 case MESA_SHADER_VERTEX
:
467 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_CTRL
:
470 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_TESS_EVAL
:
473 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_GEOMETRY
:
476 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_FRAGMENT
:
479 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
481 case MESA_SHADER_COMPUTE
:
482 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
485 unreachable("unsupported shader stage");
489 case nir_instr_type_tex
:
490 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
493 case nir_instr_type_load_const
:
494 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
497 case nir_instr_type_ssa_undef
:
498 /* We create a new VGRF for undefs on every use (by handling
499 * them in get_nir_src()), rather than for each definition.
500 * This helps register coalescing eliminate MOVs from undef.
504 case nir_instr_type_jump
:
505 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
509 unreachable("unknown instruction type");
514 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
518 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
519 const fs_reg
&result
)
521 if (!instr
->src
[0].src
.is_ssa
||
522 !instr
->src
[0].src
.ssa
->parent_instr
)
525 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
528 nir_alu_instr
*src0
=
529 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
531 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
532 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
535 /* If either opcode has source modifiers, bail.
537 * TODO: We can potentially handle source modifiers if both of the opcodes
538 * we're combining are signed integers.
540 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
541 src0
->src
[0].abs
|| src0
->src
[0].negate
)
544 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
546 /* Element type to extract.*/
547 const brw_reg_type type
= brw_int_type(
548 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
549 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
551 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
552 op0
.type
= brw_type_for_nir_type(devinfo
,
553 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
554 nir_src_bit_size(src0
->src
[0].src
)));
555 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
557 set_saturate(instr
->dest
.saturate
,
558 bld
.MOV(result
, subscript(op0
, type
, element
)));
563 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
564 const fs_reg
&result
)
566 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
567 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
570 if (!nir_src_is_const(instr
->src
[1].src
) ||
571 !nir_src_is_const(instr
->src
[2].src
))
574 const float value1
= nir_src_as_float(instr
->src
[1].src
);
575 const float value2
= nir_src_as_float(instr
->src
[2].src
);
576 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
579 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
580 assert(value1
== -value2
);
582 fs_reg tmp
= vgrf(glsl_type::int_type
);
584 if (devinfo
->gen
>= 12) {
585 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
586 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
588 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
590 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
591 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
593 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
595 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
596 g1
, brw_imm_uw(0x3f80));
599 bld
.MOV(tmp
, negate(tmp
));
601 } else if (devinfo
->gen
>= 6) {
602 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
603 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
605 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
607 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
608 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
610 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
612 * This negation looks like it's safe in practice, because bits 0:4 will
613 * surely be TRIANGLES
616 if (value1
== -1.0f
) {
620 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
621 g0
, brw_imm_uw(0x3f80));
623 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
624 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
626 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
628 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
629 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
631 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
633 * This negation looks like it's safe in practice, because bits 0:4 will
634 * surely be TRIANGLES
637 if (value1
== -1.0f
) {
641 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
643 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
649 emit_find_msb_using_lzd(const fs_builder
&bld
,
650 const fs_reg
&result
,
658 /* LZD of an absolute value source almost always does the right
659 * thing. There are two problem values:
661 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
662 * 0. However, findMSB(int(0x80000000)) == 30.
664 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
665 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
667 * For a value of zero or negative one, -1 will be returned.
669 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
670 * findMSB(-(1<<x)) should return x-1.
672 * For all negative number cases, including 0x80000000 and
673 * 0xffffffff, the correct value is obtained from LZD if instead of
674 * negating the (already negative) value the logical-not is used. A
675 * conditonal logical-not can be achieved in two instructions.
677 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
679 bld
.ASR(temp
, src
, brw_imm_d(31));
680 bld
.XOR(temp
, temp
, src
);
683 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
684 retype(temp
, BRW_REGISTER_TYPE_UD
));
686 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
687 * from the LSB side. Subtract the result from 31 to convert the MSB
688 * count into an LSB count. If no bits are set, LZD will return 32.
689 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
691 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
692 inst
->src
[0].negate
= true;
696 brw_rnd_mode_from_nir_op (const nir_op op
) {
698 case nir_op_f2f16_rtz
:
699 return BRW_RND_MODE_RTZ
;
700 case nir_op_f2f16_rtne
:
701 return BRW_RND_MODE_RTNE
;
703 unreachable("Operation doesn't support rounding mode");
708 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
710 if (nir_has_any_rounding_mode_rtne(execution_mode
))
711 return BRW_RND_MODE_RTNE
;
712 if (nir_has_any_rounding_mode_rtz(execution_mode
))
713 return BRW_RND_MODE_RTZ
;
714 return BRW_RND_MODE_UNSPECIFIED
;
718 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
719 nir_alu_instr
*instr
,
724 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
726 result
.type
= brw_type_for_nir_type(devinfo
,
727 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
728 nir_dest_bit_size(instr
->dest
.dest
)));
730 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
731 op
[i
] = get_nir_src(instr
->src
[i
].src
);
732 op
[i
].type
= brw_type_for_nir_type(devinfo
,
733 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
734 nir_src_bit_size(instr
->src
[i
].src
)));
735 op
[i
].abs
= instr
->src
[i
].abs
;
736 op
[i
].negate
= instr
->src
[i
].negate
;
739 /* Move and vecN instrutions may still be vectored. Return the raw,
740 * vectored source and destination so that fs_visitor::nir_emit_alu can
741 * handle it. Other callers should not have to handle these kinds of
754 /* At this point, we have dealt with any instruction that operates on
755 * more than a single channel. Therefore, we can just adjust the source
756 * and destination registers for that channel and emit the instruction.
758 unsigned channel
= 0;
759 if (nir_op_infos
[instr
->op
].output_size
== 0) {
760 /* Since NIR is doing the scalarizing for us, we should only ever see
761 * vectorized operations with a single channel.
763 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
764 channel
= ffs(instr
->dest
.write_mask
) - 1;
766 result
= offset(result
, bld
, channel
);
769 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
770 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
771 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
778 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
781 for (unsigned i
= 0; i
< 2; i
++) {
782 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
784 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
785 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
786 /* The source of the inot is now the source of instr. */
787 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
789 assert(!op
[i
].negate
);
792 op
[i
] = resolve_source_modifiers(op
[i
]);
798 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
800 nir_alu_instr
*instr
)
802 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
805 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
807 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
810 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
811 * of valid size-changing combinations is a bit more complex.
813 * The source restriction is just because I was lazy about generating the
816 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
817 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
820 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
821 * this is float(1 + a).
825 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
827 /* Ignore the saturate modifier, if there is one. The result of the
828 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
830 bld
.ADD(result
, op
, brw_imm_d(1));
836 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
838 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
839 * the source of \c instr that is a \c nir_op_fsign.
842 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
843 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
847 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
848 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
850 if (instr
->op
!= nir_op_fsign
) {
851 const nir_alu_instr
*const fsign_instr
=
852 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
854 assert(!fsign_instr
->dest
.saturate
);
856 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
857 * fsign_src] has the other multiply source. This must be rearranged so
858 * that op[0] is the source of the fsign op[1] is the other multiply
864 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
866 const nir_alu_type t
=
867 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
868 nir_src_bit_size(fsign_instr
->src
[0].src
));
870 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
871 op
[0].abs
= fsign_instr
->src
[0].abs
;
872 op
[0].negate
= fsign_instr
->src
[0].negate
;
874 unsigned channel
= 0;
875 if (nir_op_infos
[instr
->op
].output_size
== 0) {
876 /* Since NIR is doing the scalarizing for us, we should only ever see
877 * vectorized operations with a single channel.
879 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
880 channel
= ffs(instr
->dest
.write_mask
) - 1;
883 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
885 assert(!instr
->dest
.saturate
);
889 /* Straightforward since the source can be assumed to be either strictly
890 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
892 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
894 if (instr
->op
== nir_op_fsign
) {
895 inst
= (op
[0].negate
)
896 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
897 : bld
.MOV(result
, brw_imm_f(1.0f
));
899 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
900 inst
= bld
.MOV(result
, op
[1]);
903 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
904 } else if (type_sz(op
[0].type
) == 2) {
905 /* AND(val, 0x8000) gives the sign bit.
907 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
909 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
910 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
912 op
[0].type
= BRW_REGISTER_TYPE_UW
;
913 result
.type
= BRW_REGISTER_TYPE_UW
;
914 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
916 if (instr
->op
== nir_op_fsign
)
917 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
919 /* Use XOR here to get the result sign correct. */
920 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
923 inst
->predicate
= BRW_PREDICATE_NORMAL
;
924 } else if (type_sz(op
[0].type
) == 4) {
925 /* AND(val, 0x80000000) gives the sign bit.
927 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
930 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
932 op
[0].type
= BRW_REGISTER_TYPE_UD
;
933 result
.type
= BRW_REGISTER_TYPE_UD
;
934 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
936 if (instr
->op
== nir_op_fsign
)
937 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
939 /* Use XOR here to get the result sign correct. */
940 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
943 inst
->predicate
= BRW_PREDICATE_NORMAL
;
945 /* For doubles we do the same but we need to consider:
947 * - 2-src instructions can't operate with 64-bit immediates
948 * - The sign is encoded in the high 32-bit of each DF
949 * - We need to produce a DF result.
952 fs_reg zero
= vgrf(glsl_type::double_type
);
953 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
954 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
956 bld
.MOV(result
, zero
);
958 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
959 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
960 brw_imm_ud(0x80000000u
));
962 if (instr
->op
== nir_op_fsign
) {
963 set_predicate(BRW_PREDICATE_NORMAL
,
964 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
966 /* This could be done better in some cases. If the scale is an
967 * immediate with the low 32-bits all 0, emitting a separate XOR and
968 * OR would allow an algebraic optimization to remove the OR. There
969 * are currently zero instances of fsign(double(x))*IMM in shader-db
970 * or any test suite, so it is hard to care at this time.
972 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
973 inst
= bld
.XOR(result_int64
, result_int64
,
974 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
980 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
982 * Checks the operands of a \c nir_op_fmul to determine whether or not
983 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
985 * \param instr The multiplication instruction
987 * \param fsign_src The source of \c instr that may or may not be a
991 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
993 assert(instr
->op
== nir_op_fmul
);
995 nir_alu_instr
*const fsign_instr
=
996 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
1000 * 1. instr->src[fsign_src] must be a nir_op_fsign.
1001 * 2. The nir_op_fsign can only be used by this multiplication.
1002 * 3. The source that is the nir_op_fsign does not have source modifiers.
1003 * \c emit_fsign only examines the source modifiers of the source of the
1006 * The nir_op_fsign must also not have the saturate modifier, but steps
1007 * have already been taken (in nir_opt_algebraic) to ensure that.
1009 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
1010 is_used_once(fsign_instr
) &&
1011 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
1015 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1018 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1020 unsigned execution_mode
=
1021 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1024 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1026 switch (instr
->op
) {
1031 fs_reg temp
= result
;
1032 bool need_extra_copy
= false;
1033 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1034 if (!instr
->src
[i
].src
.is_ssa
&&
1035 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1036 need_extra_copy
= true;
1037 temp
= bld
.vgrf(result
.type
, 4);
1042 for (unsigned i
= 0; i
< 4; i
++) {
1043 if (!(instr
->dest
.write_mask
& (1 << i
)))
1046 if (instr
->op
== nir_op_mov
) {
1047 inst
= bld
.MOV(offset(temp
, bld
, i
),
1048 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1050 inst
= bld
.MOV(offset(temp
, bld
, i
),
1051 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1053 inst
->saturate
= instr
->dest
.saturate
;
1056 /* In this case the source and destination registers were the same,
1057 * so we need to insert an extra set of moves in order to deal with
1060 if (need_extra_copy
) {
1061 for (unsigned i
= 0; i
< 4; i
++) {
1062 if (!(instr
->dest
.write_mask
& (1 << i
)))
1065 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1073 if (optimize_extract_to_float(instr
, result
))
1075 inst
= bld
.MOV(result
, op
[0]);
1076 inst
->saturate
= instr
->dest
.saturate
;
1079 case nir_op_f2f16_rtne
:
1080 case nir_op_f2f16_rtz
:
1081 case nir_op_f2f16
: {
1082 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1084 if (nir_op_f2f16
== instr
->op
)
1085 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1087 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1089 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1090 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1092 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1093 * on the HW gen, it is a special hw opcode or just a MOV, and
1094 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1096 * But if we want to use that opcode, we need to provide support on
1097 * different optimizations and lowerings. As right now HF support is
1098 * only for gen8+, it will be better to use directly the MOV, and use
1099 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1101 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1102 inst
= bld
.MOV(result
, op
[0]);
1103 inst
->saturate
= instr
->dest
.saturate
;
1114 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1116 op
[0].type
= BRW_REGISTER_TYPE_D
;
1117 op
[0].negate
= !op
[0].negate
;
1140 if (result
.type
== BRW_REGISTER_TYPE_B
||
1141 result
.type
== BRW_REGISTER_TYPE_UB
||
1142 result
.type
== BRW_REGISTER_TYPE_HF
)
1143 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1145 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1146 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1147 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1148 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1150 inst
= bld
.MOV(result
, op
[0]);
1151 inst
->saturate
= instr
->dest
.saturate
;
1155 inst
= bld
.MOV(result
, op
[0]);
1156 inst
->saturate
= true;
1161 op
[0].negate
= true;
1162 inst
= bld
.MOV(result
, op
[0]);
1163 if (instr
->op
== nir_op_fneg
)
1164 inst
->saturate
= instr
->dest
.saturate
;
1169 op
[0].negate
= false;
1171 inst
= bld
.MOV(result
, op
[0]);
1172 if (instr
->op
== nir_op_fabs
)
1173 inst
->saturate
= instr
->dest
.saturate
;
1177 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1179 brw_rnd_mode_from_execution_mode(execution_mode
);
1180 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1184 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1185 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1187 inst
= bld
.MOV(result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1192 emit_fsign(bld
, instr
, result
, op
, 0);
1196 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1197 inst
->saturate
= instr
->dest
.saturate
;
1201 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1206 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1207 inst
->saturate
= instr
->dest
.saturate
;
1211 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1212 inst
->saturate
= instr
->dest
.saturate
;
1216 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1217 inst
->saturate
= instr
->dest
.saturate
;
1221 if (fs_key
->high_quality_derivatives
) {
1222 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1224 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1226 inst
->saturate
= instr
->dest
.saturate
;
1228 case nir_op_fddx_fine
:
1229 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1230 inst
->saturate
= instr
->dest
.saturate
;
1232 case nir_op_fddx_coarse
:
1233 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1234 inst
->saturate
= instr
->dest
.saturate
;
1237 if (fs_key
->high_quality_derivatives
) {
1238 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1240 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1242 inst
->saturate
= instr
->dest
.saturate
;
1244 case nir_op_fddy_fine
:
1245 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1246 inst
->saturate
= instr
->dest
.saturate
;
1248 case nir_op_fddy_coarse
:
1249 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1250 inst
->saturate
= instr
->dest
.saturate
;
1254 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1256 brw_rnd_mode_from_execution_mode(execution_mode
);
1257 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1262 inst
= bld
.ADD(result
, op
[0], op
[1]);
1263 inst
->saturate
= instr
->dest
.saturate
;
1266 case nir_op_uadd_sat
:
1267 inst
= bld
.ADD(result
, op
[0], op
[1]);
1268 inst
->saturate
= true;
1272 for (unsigned i
= 0; i
< 2; i
++) {
1273 if (can_fuse_fmul_fsign(instr
, i
)) {
1274 emit_fsign(bld
, instr
, result
, op
, i
);
1279 /* We emit the rounding mode after the previous fsign optimization since
1280 * it won't result in a MUL, but will try to negate the value by other
1283 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1285 brw_rnd_mode_from_execution_mode(execution_mode
);
1286 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1290 inst
= bld
.MUL(result
, op
[0], op
[1]);
1291 inst
->saturate
= instr
->dest
.saturate
;
1294 case nir_op_imul_2x32_64
:
1295 case nir_op_umul_2x32_64
:
1296 bld
.MUL(result
, op
[0], op
[1]);
1300 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1301 bld
.MUL(result
, op
[0], op
[1]);
1304 case nir_op_imul_high
:
1305 case nir_op_umul_high
:
1306 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1307 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1312 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1313 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1316 case nir_op_uadd_carry
:
1317 unreachable("Should have been lowered by carry_to_arith().");
1319 case nir_op_usub_borrow
:
1320 unreachable("Should have been lowered by borrow_to_arith().");
1324 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1325 * appears that our hardware just does the right thing for signed
1328 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1329 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1333 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1334 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1336 /* Math instructions don't support conditional mod */
1337 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1338 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1340 /* Now, we need to determine if signs of the sources are different.
1341 * When we XOR the sources, the top bit is 0 if they are the same and 1
1342 * if they are different. We can then use a conditional modifier to
1343 * turn that into a predicate. This leads us to an XOR.l instruction.
1345 * Technically, according to the PRM, you're not allowed to use .l on a
1346 * XOR instruction. However, emperical experiments and Curro's reading
1347 * of the simulator source both indicate that it's safe.
1349 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1350 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1351 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1352 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1354 /* If the result of the initial remainder operation is non-zero and the
1355 * two sources have different signs, add in a copy of op[1] to get the
1356 * final integer modulus value.
1358 inst
= bld
.ADD(result
, result
, op
[1]);
1359 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1366 case nir_op_fne32
: {
1367 fs_reg dest
= result
;
1369 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1371 dest
= bld
.vgrf(op
[0].type
, 1);
1373 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1375 if (bit_size
> 32) {
1376 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1377 } else if(bit_size
< 32) {
1378 /* When we convert the result to 32-bit we need to be careful and do
1379 * it as a signed conversion to get sign extension (for 32-bit true)
1381 const brw_reg_type src_type
=
1382 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1384 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1394 case nir_op_ine32
: {
1395 fs_reg dest
= result
;
1397 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1398 * type. So we convert both operands for the comparison.
1401 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1402 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1404 const uint32_t bit_size
= type_sz(temp_op
[0].type
) * 8;
1406 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1408 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1409 brw_cmod_for_nir_comparison(instr
->op
));
1411 if (bit_size
> 32) {
1412 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1413 } else if (bit_size
< 32) {
1414 /* When we convert the result to 32-bit we need to be careful and do
1415 * it as a signed conversion to get sign extension (for 32-bit true)
1417 const brw_reg_type src_type
=
1418 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1420 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1426 if (devinfo
->gen
>= 8) {
1427 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1429 if (inot_src_instr
!= NULL
&&
1430 (inot_src_instr
->op
== nir_op_ior
||
1431 inot_src_instr
->op
== nir_op_ixor
||
1432 inot_src_instr
->op
== nir_op_iand
) &&
1433 !inot_src_instr
->src
[0].abs
&&
1434 !inot_src_instr
->src
[0].negate
&&
1435 !inot_src_instr
->src
[1].abs
&&
1436 !inot_src_instr
->src
[1].negate
) {
1437 /* The sources of the source logical instruction are now the
1438 * sources of the instruction that will be generated.
1440 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1441 resolve_inot_sources(bld
, inot_src_instr
, op
);
1443 /* Smash all of the sources and destination to be signed. This
1444 * doesn't matter for the operation of the instruction, but cmod
1445 * propagation fails on unsigned sources with negation (due to
1446 * fs_inst::can_do_cmod returning false).
1449 brw_type_for_nir_type(devinfo
,
1450 (nir_alu_type
)(nir_type_int
|
1451 nir_dest_bit_size(instr
->dest
.dest
)));
1453 brw_type_for_nir_type(devinfo
,
1454 (nir_alu_type
)(nir_type_int
|
1455 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1457 brw_type_for_nir_type(devinfo
,
1458 (nir_alu_type
)(nir_type_int
|
1459 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1461 /* For XOR, only invert one of the sources. Arbitrarily choose
1464 op
[0].negate
= !op
[0].negate
;
1465 if (inot_src_instr
->op
!= nir_op_ixor
)
1466 op
[1].negate
= !op
[1].negate
;
1468 switch (inot_src_instr
->op
) {
1470 bld
.AND(result
, op
[0], op
[1]);
1474 bld
.OR(result
, op
[0], op
[1]);
1478 bld
.XOR(result
, op
[0], op
[1]);
1482 unreachable("impossible opcode");
1485 op
[0] = resolve_source_modifiers(op
[0]);
1487 bld
.NOT(result
, op
[0]);
1490 if (devinfo
->gen
>= 8) {
1491 resolve_inot_sources(bld
, instr
, op
);
1493 bld
.XOR(result
, op
[0], op
[1]);
1496 if (devinfo
->gen
>= 8) {
1497 resolve_inot_sources(bld
, instr
, op
);
1499 bld
.OR(result
, op
[0], op
[1]);
1502 if (devinfo
->gen
>= 8) {
1503 resolve_inot_sources(bld
, instr
, op
);
1505 bld
.AND(result
, op
[0], op
[1]);
1511 case nir_op_b32all_fequal2
:
1512 case nir_op_b32all_iequal2
:
1513 case nir_op_b32all_fequal3
:
1514 case nir_op_b32all_iequal3
:
1515 case nir_op_b32all_fequal4
:
1516 case nir_op_b32all_iequal4
:
1517 case nir_op_b32any_fnequal2
:
1518 case nir_op_b32any_inequal2
:
1519 case nir_op_b32any_fnequal3
:
1520 case nir_op_b32any_inequal3
:
1521 case nir_op_b32any_fnequal4
:
1522 case nir_op_b32any_inequal4
:
1523 unreachable("Lowered by nir_lower_alu_reductions");
1525 case nir_op_fnoise1_1
:
1526 case nir_op_fnoise1_2
:
1527 case nir_op_fnoise1_3
:
1528 case nir_op_fnoise1_4
:
1529 case nir_op_fnoise2_1
:
1530 case nir_op_fnoise2_2
:
1531 case nir_op_fnoise2_3
:
1532 case nir_op_fnoise2_4
:
1533 case nir_op_fnoise3_1
:
1534 case nir_op_fnoise3_2
:
1535 case nir_op_fnoise3_3
:
1536 case nir_op_fnoise3_4
:
1537 case nir_op_fnoise4_1
:
1538 case nir_op_fnoise4_2
:
1539 case nir_op_fnoise4_3
:
1540 case nir_op_fnoise4_4
:
1541 unreachable("not reached: should be handled by lower_noise");
1544 unreachable("not reached: should be handled by ldexp_to_arith()");
1547 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1548 inst
->saturate
= instr
->dest
.saturate
;
1552 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1553 inst
->saturate
= instr
->dest
.saturate
;
1557 case nir_op_f2b32
: {
1558 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1559 if (bit_size
== 64) {
1560 /* two-argument instructions can't take 64-bit immediates */
1564 if (instr
->op
== nir_op_f2b32
) {
1565 zero
= vgrf(glsl_type::double_type
);
1566 tmp
= vgrf(glsl_type::double_type
);
1567 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1569 zero
= vgrf(glsl_type::int64_t_type
);
1570 tmp
= vgrf(glsl_type::int64_t_type
);
1571 bld
.MOV(zero
, brw_imm_q(0));
1574 /* A SIMD16 execution needs to be split in two instructions, so use
1575 * a vgrf instead of the flag register as dst so instruction splitting
1578 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1579 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1582 if (bit_size
== 32) {
1583 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1585 assert(bit_size
== 16);
1586 zero
= instr
->op
== nir_op_f2b32
?
1587 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1589 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1595 inst
= bld
.RNDZ(result
, op
[0]);
1596 if (devinfo
->gen
< 6) {
1597 set_condmod(BRW_CONDITIONAL_R
, inst
);
1598 set_predicate(BRW_PREDICATE_NORMAL
,
1599 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1600 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1602 inst
->saturate
= instr
->dest
.saturate
;
1605 case nir_op_fceil
: {
1606 op
[0].negate
= !op
[0].negate
;
1607 fs_reg temp
= vgrf(glsl_type::float_type
);
1608 bld
.RNDD(temp
, op
[0]);
1610 inst
= bld
.MOV(result
, temp
);
1611 inst
->saturate
= instr
->dest
.saturate
;
1615 inst
= bld
.RNDD(result
, op
[0]);
1616 inst
->saturate
= instr
->dest
.saturate
;
1619 inst
= bld
.FRC(result
, op
[0]);
1620 inst
->saturate
= instr
->dest
.saturate
;
1622 case nir_op_fround_even
:
1623 inst
= bld
.RNDE(result
, op
[0]);
1624 if (devinfo
->gen
< 6) {
1625 set_condmod(BRW_CONDITIONAL_R
, inst
);
1626 set_predicate(BRW_PREDICATE_NORMAL
,
1627 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1628 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1630 inst
->saturate
= instr
->dest
.saturate
;
1633 case nir_op_fquantize2f16
: {
1634 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1635 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1636 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1638 /* The destination stride must be at least as big as the source stride. */
1639 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1642 /* Check for denormal */
1643 fs_reg abs_src0
= op
[0];
1644 abs_src0
.abs
= true;
1645 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1647 /* Get the appropriately signed zero */
1648 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1649 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1650 brw_imm_ud(0x80000000));
1651 /* Do the actual F32 -> F16 -> F32 conversion */
1652 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1653 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1654 /* Select that or zero based on normal status */
1655 inst
= bld
.SEL(result
, zero
, tmp32
);
1656 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1657 inst
->saturate
= instr
->dest
.saturate
;
1664 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1665 inst
->saturate
= instr
->dest
.saturate
;
1671 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1672 inst
->saturate
= instr
->dest
.saturate
;
1675 case nir_op_pack_snorm_2x16
:
1676 case nir_op_pack_snorm_4x8
:
1677 case nir_op_pack_unorm_2x16
:
1678 case nir_op_pack_unorm_4x8
:
1679 case nir_op_unpack_snorm_2x16
:
1680 case nir_op_unpack_snorm_4x8
:
1681 case nir_op_unpack_unorm_2x16
:
1682 case nir_op_unpack_unorm_4x8
:
1683 case nir_op_unpack_half_2x16
:
1684 case nir_op_pack_half_2x16
:
1685 unreachable("not reached: should be handled by lower_packing_builtins");
1687 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1688 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1690 case nir_op_unpack_half_2x16_split_x
:
1691 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1692 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1693 inst
->saturate
= instr
->dest
.saturate
;
1696 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1697 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1699 case nir_op_unpack_half_2x16_split_y
:
1700 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1701 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1702 inst
->saturate
= instr
->dest
.saturate
;
1705 case nir_op_pack_64_2x32_split
:
1706 case nir_op_pack_32_2x16_split
:
1707 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1710 case nir_op_unpack_64_2x32_split_x
:
1711 case nir_op_unpack_64_2x32_split_y
: {
1712 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1713 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1715 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1719 case nir_op_unpack_32_2x16_split_x
:
1720 case nir_op_unpack_32_2x16_split_y
: {
1721 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1722 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1724 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1729 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1730 inst
->saturate
= instr
->dest
.saturate
;
1733 case nir_op_bitfield_reverse
:
1734 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1735 bld
.BFREV(result
, op
[0]);
1738 case nir_op_bit_count
:
1739 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1740 bld
.CBIT(result
, op
[0]);
1743 case nir_op_ufind_msb
: {
1744 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1745 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1749 case nir_op_ifind_msb
: {
1750 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1752 if (devinfo
->gen
< 7) {
1753 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1755 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1757 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1758 * count from the LSB side. If FBH didn't return an error
1759 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1760 * count into an LSB count.
1762 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1764 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1765 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1766 inst
->src
[0].negate
= true;
1771 case nir_op_find_lsb
:
1772 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1774 if (devinfo
->gen
< 7) {
1775 fs_reg temp
= vgrf(glsl_type::int_type
);
1777 /* (x & -x) generates a value that consists of only the LSB of x.
1778 * For all powers of 2, findMSB(y) == findLSB(y).
1780 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1781 fs_reg negated_src
= src
;
1783 /* One must be negated, and the other must be non-negated. It
1784 * doesn't matter which is which.
1786 negated_src
.negate
= true;
1789 bld
.AND(temp
, src
, negated_src
);
1790 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1792 bld
.FBL(result
, op
[0]);
1796 case nir_op_ubitfield_extract
:
1797 case nir_op_ibitfield_extract
:
1798 unreachable("should have been lowered");
1801 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1802 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1805 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1806 bld
.BFI1(result
, op
[0], op
[1]);
1809 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1810 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1813 case nir_op_bitfield_insert
:
1814 unreachable("not reached: should have been lowered");
1817 bld
.SHL(result
, op
[0], op
[1]);
1820 bld
.ASR(result
, op
[0], op
[1]);
1823 bld
.SHR(result
, op
[0], op
[1]);
1827 bld
.ROL(result
, op
[0], op
[1]);
1830 bld
.ROR(result
, op
[0], op
[1]);
1833 case nir_op_pack_half_2x16_split
:
1834 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1838 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1840 brw_rnd_mode_from_execution_mode(execution_mode
);
1841 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1845 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1846 inst
->saturate
= instr
->dest
.saturate
;
1850 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1852 brw_rnd_mode_from_execution_mode(execution_mode
);
1853 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1857 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1858 inst
->saturate
= instr
->dest
.saturate
;
1861 case nir_op_b32csel
:
1862 if (optimize_frontfacing_ternary(instr
, result
))
1865 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1866 inst
= bld
.SEL(result
, op
[1], op
[2]);
1867 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1870 case nir_op_extract_u8
:
1871 case nir_op_extract_i8
: {
1872 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1877 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1878 * Use two instructions and a word or DWord intermediate integer type.
1880 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1881 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1883 if (instr
->op
== nir_op_extract_i8
) {
1884 /* If we need to sign extend, extract to a word first */
1885 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1886 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1887 bld
.MOV(result
, w_temp
);
1888 } else if (byte
& 1) {
1889 /* Extract the high byte from the word containing the desired byte
1893 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1896 /* Otherwise use an AND with 0xff and a word type */
1898 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1902 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1903 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1908 case nir_op_extract_u16
:
1909 case nir_op_extract_i16
: {
1910 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1911 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1912 bld
.MOV(result
, subscript(op
[0], type
, word
));
1917 unreachable("unhandled instruction");
1920 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1921 * to sign extend the low bit to 0/~0
1923 if (devinfo
->gen
<= 5 &&
1924 !result
.is_null() &&
1925 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1926 fs_reg masked
= vgrf(glsl_type::int_type
);
1927 bld
.AND(masked
, result
, brw_imm_d(1));
1928 masked
.negate
= true;
1929 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1934 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1935 nir_load_const_instr
*instr
)
1937 const brw_reg_type reg_type
=
1938 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1939 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1941 switch (instr
->def
.bit_size
) {
1943 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1944 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1948 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1949 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1953 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1954 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1958 assert(devinfo
->gen
>= 7);
1959 if (devinfo
->gen
== 7) {
1960 /* We don't get 64-bit integer types until gen8 */
1961 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1962 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1963 setup_imm_df(bld
, instr
->value
[i
].f64
));
1966 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1967 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1972 unreachable("Invalid bit size");
1975 nir_ssa_values
[instr
->def
.index
] = reg
;
1979 fs_visitor::get_nir_src(const nir_src
&src
)
1983 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1984 const brw_reg_type reg_type
=
1985 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1986 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1988 reg
= nir_ssa_values
[src
.ssa
->index
];
1991 /* We don't handle indirects on locals */
1992 assert(src
.reg
.indirect
== NULL
);
1993 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1994 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1997 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1998 /* The only 64-bit type available on gen7 is DF, so use that. */
1999 reg
.type
= BRW_REGISTER_TYPE_DF
;
2001 /* To avoid floating-point denorm flushing problems, set the type by
2002 * default to an integer type - instructions that need floating point
2003 * semantics will set this to F if they need to
2005 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
2006 BRW_REGISTER_TYPE_D
);
2013 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2015 * This function should not be called on any value which may be 64 bits.
2016 * We could theoretically support 64-bit on gen8+ but we choose not to
2017 * because it wouldn't work in general (no gen7 support) and there are
2018 * enough restrictions in 64-bit immediates that you can't take the return
2019 * value and treat it the same as the result of get_nir_src().
2022 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2024 assert(nir_src_bit_size(src
) == 32);
2025 return nir_src_is_const(src
) ?
2026 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2030 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2033 const brw_reg_type reg_type
=
2034 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2035 dest
.ssa
.bit_size
== 8 ?
2036 BRW_REGISTER_TYPE_D
:
2037 BRW_REGISTER_TYPE_F
);
2038 nir_ssa_values
[dest
.ssa
.index
] =
2039 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2040 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2041 return nir_ssa_values
[dest
.ssa
.index
];
2043 /* We don't handle indirects on locals */
2044 assert(dest
.reg
.indirect
== NULL
);
2045 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2046 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2051 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2054 for (unsigned i
= 0; i
< 4; i
++) {
2055 if (!((wr_mask
>> i
) & 1))
2058 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2059 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2060 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2061 if (new_inst
->src
[j
].file
== VGRF
)
2062 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2069 emit_pixel_interpolater_send(const fs_builder
&bld
,
2074 glsl_interp_mode interpolation
)
2076 struct brw_wm_prog_data
*wm_prog_data
=
2077 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2079 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2080 /* 2 floats per slot returned */
2081 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2082 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2084 wm_prog_data
->pulls_bary
= true;
2090 * Computes 1 << x, given a D/UD register containing some value x.
2093 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2095 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2097 fs_reg result
= bld
.vgrf(x
.type
, 1);
2098 fs_reg one
= bld
.vgrf(x
.type
, 1);
2100 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2101 bld
.SHL(result
, one
, x
);
2106 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2108 assert(stage
== MESA_SHADER_GEOMETRY
);
2110 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2112 if (gs_compile
->control_data_header_size_bits
== 0)
2115 /* We can only do EndPrimitive() functionality when the control data
2116 * consists of cut bits. Fortunately, the only time it isn't is when the
2117 * output type is points, in which case EndPrimitive() is a no-op.
2119 if (gs_prog_data
->control_data_format
!=
2120 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2124 /* Cut bits use one bit per vertex. */
2125 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2127 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2128 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2130 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2131 * vertex n, 0 otherwise. So all we need to do here is mark bit
2132 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2133 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2134 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2136 * Note that if EndPrimitive() is called before emitting any vertices, this
2137 * will cause us to set bit 31 of the control_data_bits register to 1.
2138 * That's fine because:
2140 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2141 * output, so the hardware will ignore cut bit 31.
2143 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2144 * last vertex, so setting cut bit 31 has no effect (since the primitive
2145 * is automatically ended when the GS terminates).
2147 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2148 * control_data_bits register to 0 when the first vertex is emitted.
2151 const fs_builder abld
= bld
.annotate("end primitive");
2153 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2154 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2155 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2156 fs_reg mask
= intexp2(abld
, prev_count
);
2157 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2158 * attention to the lower 5 bits of its second source argument, so on this
2159 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2160 * ((vertex_count - 1) % 32).
2162 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2166 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2168 assert(stage
== MESA_SHADER_GEOMETRY
);
2169 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2171 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2173 const fs_builder abld
= bld
.annotate("emit control data bits");
2174 const fs_builder fwa_bld
= bld
.exec_all();
2176 /* We use a single UD register to accumulate control data bits (32 bits
2177 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2180 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2181 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2182 * use the Channel Mask phase to enable/disable which DWord within that
2183 * group to write. (Remember, different SIMD8 channels may have emitted
2184 * different numbers of vertices, so we may need per-slot offsets.)
2186 * Channel masking presents an annoying problem: we may have to replicate
2187 * the data up to 4 times:
2189 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2191 * To avoid penalizing shaders that emit a small number of vertices, we
2192 * can avoid these sometimes: if the size of the control data header is
2193 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2194 * land in the same 128-bit group, so we can skip per-slot offsets.
2196 * Similarly, if the control data header is <= 32 bits, there is only one
2197 * DWord, so we can skip channel masks.
2199 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2201 fs_reg channel_mask
, per_slot_offset
;
2203 if (gs_compile
->control_data_header_size_bits
> 32) {
2204 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2205 channel_mask
= vgrf(glsl_type::uint_type
);
2208 if (gs_compile
->control_data_header_size_bits
> 128) {
2209 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2210 per_slot_offset
= vgrf(glsl_type::uint_type
);
2213 /* Figure out which DWord we're trying to write to using the formula:
2215 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2217 * Since bits_per_vertex is a power of two, and is known at compile
2218 * time, this can be optimized to:
2220 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2222 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2223 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2224 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2225 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2226 unsigned log2_bits_per_vertex
=
2227 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2228 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2230 if (per_slot_offset
.file
!= BAD_FILE
) {
2231 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2232 * the appropriate OWord within the control data header.
2234 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2237 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2238 * write to the appropriate DWORD within the OWORD.
2240 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2241 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2242 channel_mask
= intexp2(fwa_bld
, channel
);
2243 /* Then the channel masks need to be in bits 23:16. */
2244 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2247 /* Store the control data bits in the message payload and send it. */
2249 if (channel_mask
.file
!= BAD_FILE
)
2250 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2251 if (per_slot_offset
.file
!= BAD_FILE
)
2254 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2255 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2257 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2258 if (per_slot_offset
.file
!= BAD_FILE
)
2259 sources
[i
++] = per_slot_offset
;
2260 if (channel_mask
.file
!= BAD_FILE
)
2261 sources
[i
++] = channel_mask
;
2263 sources
[i
++] = this->control_data_bits
;
2266 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2267 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2269 /* We need to increment Global Offset by 256-bits to make room for
2270 * Broadwell's extra "Vertex Count" payload at the beginning of the
2271 * URB entry. Since this is an OWord message, Global Offset is counted
2272 * in 128-bit units, so we must set it to 2.
2274 if (gs_prog_data
->static_vertex_count
== -1)
2279 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2282 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2284 /* Note: we are calling this *before* increasing vertex_count, so
2285 * this->vertex_count == vertex_count - 1 in the formula above.
2288 /* Stream mode uses 2 bits per vertex */
2289 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2291 /* Must be a valid stream */
2292 assert(stream_id
< MAX_VERTEX_STREAMS
);
2294 /* Control data bits are initialized to 0 so we don't have to set any
2295 * bits when sending vertices to stream 0.
2300 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2302 /* reg::sid = stream_id */
2303 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2304 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2306 /* reg:shift_count = 2 * (vertex_count - 1) */
2307 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2308 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2310 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2311 * attention to the lower 5 bits of its second source argument, so on this
2312 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2313 * stream_id << ((2 * (vertex_count - 1)) % 32).
2315 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2316 abld
.SHL(mask
, sid
, shift_count
);
2317 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2321 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2324 assert(stage
== MESA_SHADER_GEOMETRY
);
2326 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2328 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2329 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2331 /* Haswell and later hardware ignores the "Render Stream Select" bits
2332 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2333 * and instead sends all primitives down the pipeline for rasterization.
2334 * If the SOL stage is enabled, "Render Stream Select" is honored and
2335 * primitives bound to non-zero streams are discarded after stream output.
2337 * Since the only purpose of primives sent to non-zero streams is to
2338 * be recorded by transform feedback, we can simply discard all geometry
2339 * bound to these streams when transform feedback is disabled.
2341 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2344 /* If we're outputting 32 control data bits or less, then we can wait
2345 * until the shader is over to output them all. Otherwise we need to
2346 * output them as we go. Now is the time to do it, since we're about to
2347 * output the vertex_count'th vertex, so it's guaranteed that the
2348 * control data bits associated with the (vertex_count - 1)th vertex are
2351 if (gs_compile
->control_data_header_size_bits
> 32) {
2352 const fs_builder abld
=
2353 bld
.annotate("emit vertex: emit control data bits");
2355 /* Only emit control data bits if we've finished accumulating a batch
2356 * of 32 bits. This is the case when:
2358 * (vertex_count * bits_per_vertex) % 32 == 0
2360 * (in other words, when the last 5 bits of vertex_count *
2361 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2362 * integer n (which is always the case, since bits_per_vertex is
2363 * always 1 or 2), this is equivalent to requiring that the last 5-n
2364 * bits of vertex_count are 0:
2366 * vertex_count & (2^(5-n) - 1) == 0
2368 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2371 * vertex_count & (32 / bits_per_vertex - 1) == 0
2373 * TODO: If vertex_count is an immediate, we could do some of this math
2374 * at compile time...
2377 abld
.AND(bld
.null_reg_d(), vertex_count
,
2378 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2379 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2381 abld
.IF(BRW_PREDICATE_NORMAL
);
2382 /* If vertex_count is 0, then no control data bits have been
2383 * accumulated yet, so we can skip emitting them.
2385 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2386 BRW_CONDITIONAL_NEQ
);
2387 abld
.IF(BRW_PREDICATE_NORMAL
);
2388 emit_gs_control_data_bits(vertex_count
);
2389 abld
.emit(BRW_OPCODE_ENDIF
);
2391 /* Reset control_data_bits to 0 so we can start accumulating a new
2394 * Note: in the case where vertex_count == 0, this neutralizes the
2395 * effect of any call to EndPrimitive() that the shader may have
2396 * made before outputting its first vertex.
2398 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2399 inst
->force_writemask_all
= true;
2400 abld
.emit(BRW_OPCODE_ENDIF
);
2403 emit_urb_writes(vertex_count
);
2405 /* In stream mode we have to set control data bits for all vertices
2406 * unless we have disabled control data bits completely (which we do
2407 * do for GL_POINTS outputs that don't use streams).
2409 if (gs_compile
->control_data_header_size_bits
> 0 &&
2410 gs_prog_data
->control_data_format
==
2411 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2412 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2417 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2418 const nir_src
&vertex_src
,
2419 unsigned base_offset
,
2420 const nir_src
&offset_src
,
2421 unsigned num_components
,
2422 unsigned first_component
)
2424 assert(type_sz(dst
.type
) == 4);
2425 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2426 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2428 /* TODO: figure out push input layout for invocations == 1 */
2429 if (gs_prog_data
->invocations
== 1 &&
2430 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2431 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2432 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2433 nir_src_as_uint(vertex_src
) * push_reg_count
;
2434 for (unsigned i
= 0; i
< num_components
; i
++) {
2435 bld
.MOV(offset(dst
, bld
, i
),
2436 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2441 /* Resort to the pull model. Ensure the VUE handles are provided. */
2442 assert(gs_prog_data
->base
.include_vue_handles
);
2444 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2445 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2447 if (gs_prog_data
->invocations
== 1) {
2448 if (nir_src_is_const(vertex_src
)) {
2449 /* The vertex index is constant; just select the proper URB handle. */
2451 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2452 BRW_REGISTER_TYPE_UD
);
2454 /* The vertex index is non-constant. We need to use indirect
2455 * addressing to fetch the proper URB handle.
2457 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2458 * indicating that channel <n> should read the handle from
2459 * DWord <n>. We convert that to bytes by multiplying by 4.
2461 * Next, we convert the vertex index to bytes by multiplying
2462 * by 32 (shifting by 5), and add the two together. This is
2463 * the final indirect byte offset.
2465 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2466 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2467 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2468 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2470 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2471 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2472 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2473 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2474 /* Convert vertex_index to bytes (multiply by 32) */
2475 bld
.SHL(vertex_offset_bytes
,
2476 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2478 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2480 /* Use first_icp_handle as the base offset. There is one register
2481 * of URB handles per vertex, so inform the register allocator that
2482 * we might read up to nir->info.gs.vertices_in registers.
2484 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2485 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2486 fs_reg(icp_offset_bytes
),
2487 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2490 assert(gs_prog_data
->invocations
> 1);
2492 if (nir_src_is_const(vertex_src
)) {
2493 unsigned vertex
= nir_src_as_uint(vertex_src
);
2494 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2496 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2497 BRW_REGISTER_TYPE_UD
));
2499 /* The vertex index is non-constant. We need to use indirect
2500 * addressing to fetch the proper URB handle.
2503 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2505 /* Convert vertex_index to bytes (multiply by 4) */
2506 bld
.SHL(icp_offset_bytes
,
2507 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2510 /* Use first_icp_handle as the base offset. There is one DWord
2511 * of URB handles per vertex, so inform the register allocator that
2512 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2514 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2515 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2516 fs_reg(icp_offset_bytes
),
2517 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2523 fs_reg indirect_offset
= get_nir_src(offset_src
);
2525 if (nir_src_is_const(offset_src
)) {
2526 /* Constant indexing - use global offset. */
2527 if (first_component
!= 0) {
2528 unsigned read_components
= num_components
+ first_component
;
2529 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2530 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2531 inst
->size_written
= read_components
*
2532 tmp
.component_size(inst
->exec_size
);
2533 for (unsigned i
= 0; i
< num_components
; i
++) {
2534 bld
.MOV(offset(dst
, bld
, i
),
2535 offset(tmp
, bld
, i
+ first_component
));
2538 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2539 inst
->size_written
= num_components
*
2540 dst
.component_size(inst
->exec_size
);
2542 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2545 /* Indirect indexing - use per-slot offsets as well. */
2546 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2547 unsigned read_components
= num_components
+ first_component
;
2548 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2549 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2550 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2551 if (first_component
!= 0) {
2552 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2554 inst
->size_written
= read_components
*
2555 tmp
.component_size(inst
->exec_size
);
2556 for (unsigned i
= 0; i
< num_components
; i
++) {
2557 bld
.MOV(offset(dst
, bld
, i
),
2558 offset(tmp
, bld
, i
+ first_component
));
2561 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2562 inst
->size_written
= num_components
*
2563 dst
.component_size(inst
->exec_size
);
2565 inst
->offset
= base_offset
;
2571 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2573 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2575 if (nir_src_is_const(*offset_src
)) {
2576 /* The only constant offset we should find is 0. brw_nir.c's
2577 * add_const_offset_to_base() will fold other constant offsets
2578 * into instr->const_index[0].
2580 assert(nir_src_as_uint(*offset_src
) == 0);
2584 return get_nir_src(*offset_src
);
2588 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2589 nir_intrinsic_instr
*instr
)
2591 assert(stage
== MESA_SHADER_VERTEX
);
2594 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2595 dest
= get_nir_dest(instr
->dest
);
2597 switch (instr
->intrinsic
) {
2598 case nir_intrinsic_load_vertex_id
:
2599 case nir_intrinsic_load_base_vertex
:
2600 unreachable("should be lowered by nir_lower_system_values()");
2602 case nir_intrinsic_load_input
: {
2603 assert(nir_dest_bit_size(instr
->dest
) == 32);
2604 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2605 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2606 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2608 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2609 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2613 case nir_intrinsic_load_vertex_id_zero_base
:
2614 case nir_intrinsic_load_instance_id
:
2615 case nir_intrinsic_load_base_instance
:
2616 case nir_intrinsic_load_draw_id
:
2617 case nir_intrinsic_load_first_vertex
:
2618 case nir_intrinsic_load_is_indexed_draw
:
2619 unreachable("lowered by brw_nir_lower_vs_inputs");
2622 nir_emit_intrinsic(bld
, instr
);
2628 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2629 nir_intrinsic_instr
*instr
)
2631 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2632 const nir_src
&vertex_src
= instr
->src
[0];
2633 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2636 if (nir_src_is_const(vertex_src
)) {
2637 /* Emit a MOV to resolve <0,1,0> regioning. */
2638 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2639 unsigned vertex
= nir_src_as_uint(vertex_src
);
2641 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2642 BRW_REGISTER_TYPE_UD
));
2643 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2644 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2645 /* For the common case of only 1 instance, an array index of
2646 * gl_InvocationID means reading g1. Skip all the indirect work.
2648 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2650 /* The vertex index is non-constant. We need to use indirect
2651 * addressing to fetch the proper URB handle.
2653 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2655 /* Each ICP handle is a single DWord (4 bytes) */
2656 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2657 bld
.SHL(vertex_offset_bytes
,
2658 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2661 /* Start at g1. We might read up to 4 registers. */
2662 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2663 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2664 brw_imm_ud(4 * REG_SIZE
));
2671 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2672 nir_intrinsic_instr
*instr
)
2674 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2675 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2676 const nir_src
&vertex_src
= instr
->src
[0];
2678 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2680 if (nir_src_is_const(vertex_src
)) {
2681 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2682 nir_src_as_uint(vertex_src
), 0),
2683 BRW_REGISTER_TYPE_UD
));
2686 /* The vertex index is non-constant. We need to use indirect
2687 * addressing to fetch the proper URB handle.
2689 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2690 * indicating that channel <n> should read the handle from
2691 * DWord <n>. We convert that to bytes by multiplying by 4.
2693 * Next, we convert the vertex index to bytes by multiplying
2694 * by 32 (shifting by 5), and add the two together. This is
2695 * the final indirect byte offset.
2697 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2698 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2699 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2700 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2701 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2703 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2704 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2705 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2706 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2707 /* Convert vertex_index to bytes (multiply by 32) */
2708 bld
.SHL(vertex_offset_bytes
,
2709 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2711 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2713 /* Use first_icp_handle as the base offset. There is one register
2714 * of URB handles per vertex, so inform the register allocator that
2715 * we might read up to nir->info.gs.vertices_in registers.
2717 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2718 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2719 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2725 fs_visitor::get_tcs_output_urb_handle()
2727 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2729 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2730 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2732 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2733 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2738 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2739 nir_intrinsic_instr
*instr
)
2741 assert(stage
== MESA_SHADER_TESS_CTRL
);
2742 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2743 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2744 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2747 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2750 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2751 dst
= get_nir_dest(instr
->dest
);
2753 switch (instr
->intrinsic
) {
2754 case nir_intrinsic_load_primitive_id
:
2755 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2756 : brw_vec1_grf(0, 1)));
2758 case nir_intrinsic_load_invocation_id
:
2759 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2761 case nir_intrinsic_load_patch_vertices_in
:
2762 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2763 brw_imm_d(tcs_key
->input_vertices
));
2766 case nir_intrinsic_control_barrier
: {
2767 if (tcs_prog_data
->instances
== 1)
2770 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2771 fs_reg m0_2
= component(m0
, 2);
2773 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2775 /* Zero the message header */
2776 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2778 if (devinfo
->gen
< 11) {
2779 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2780 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2781 brw_imm_ud(INTEL_MASK(16, 13)));
2783 /* Shift it up to bits 27:24. */
2784 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2786 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2787 brw_imm_ud(INTEL_MASK(30, 24)));
2790 /* Set the Barrier Count and the enable bit */
2791 if (devinfo
->gen
< 11) {
2792 chanbld
.OR(m0_2
, m0_2
,
2793 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2795 chanbld
.OR(m0_2
, m0_2
,
2796 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2799 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2803 case nir_intrinsic_load_input
:
2804 unreachable("nir_lower_io should never give us these.");
2807 case nir_intrinsic_load_per_vertex_input
: {
2808 assert(nir_dest_bit_size(instr
->dest
) == 32);
2809 fs_reg indirect_offset
= get_indirect_offset(instr
);
2810 unsigned imm_offset
= instr
->const_index
[0];
2814 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2815 : get_tcs_single_patch_icp_handle(bld
, instr
);
2817 /* We can only read two double components with each URB read, so
2818 * we send two read messages in that case, each one loading up to
2819 * two double components.
2821 unsigned num_components
= instr
->num_components
;
2822 unsigned first_component
= nir_intrinsic_component(instr
);
2824 if (indirect_offset
.file
== BAD_FILE
) {
2825 /* Constant indexing - use global offset. */
2826 if (first_component
!= 0) {
2827 unsigned read_components
= num_components
+ first_component
;
2828 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2829 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2830 for (unsigned i
= 0; i
< num_components
; i
++) {
2831 bld
.MOV(offset(dst
, bld
, i
),
2832 offset(tmp
, bld
, i
+ first_component
));
2835 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2837 inst
->offset
= imm_offset
;
2840 /* Indirect indexing - use per-slot offsets as well. */
2841 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2842 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2843 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2844 if (first_component
!= 0) {
2845 unsigned read_components
= num_components
+ first_component
;
2846 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2847 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2849 for (unsigned i
= 0; i
< num_components
; i
++) {
2850 bld
.MOV(offset(dst
, bld
, i
),
2851 offset(tmp
, bld
, i
+ first_component
));
2854 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2857 inst
->offset
= imm_offset
;
2860 inst
->size_written
= (num_components
+ first_component
) *
2861 inst
->dst
.component_size(inst
->exec_size
);
2863 /* Copy the temporary to the destination to deal with writemasking.
2865 * Also attempt to deal with gl_PointSize being in the .w component.
2867 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2868 assert(type_sz(dst
.type
) == 4);
2869 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2870 inst
->size_written
= 4 * REG_SIZE
;
2871 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2876 case nir_intrinsic_load_output
:
2877 case nir_intrinsic_load_per_vertex_output
: {
2878 assert(nir_dest_bit_size(instr
->dest
) == 32);
2879 fs_reg indirect_offset
= get_indirect_offset(instr
);
2880 unsigned imm_offset
= instr
->const_index
[0];
2881 unsigned first_component
= nir_intrinsic_component(instr
);
2883 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2886 if (indirect_offset
.file
== BAD_FILE
) {
2887 /* This MOV replicates the output handle to all enabled channels
2888 * is SINGLE_PATCH mode.
2890 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2891 bld
.MOV(patch_handle
, output_handles
);
2894 if (first_component
!= 0) {
2895 unsigned read_components
=
2896 instr
->num_components
+ first_component
;
2897 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2898 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2900 inst
->size_written
= read_components
* REG_SIZE
;
2901 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2902 bld
.MOV(offset(dst
, bld
, i
),
2903 offset(tmp
, bld
, i
+ first_component
));
2906 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2908 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2910 inst
->offset
= imm_offset
;
2914 /* Indirect indexing - use per-slot offsets as well. */
2915 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2916 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2917 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2918 if (first_component
!= 0) {
2919 unsigned read_components
=
2920 instr
->num_components
+ first_component
;
2921 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2922 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2924 inst
->size_written
= read_components
* REG_SIZE
;
2925 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2926 bld
.MOV(offset(dst
, bld
, i
),
2927 offset(tmp
, bld
, i
+ first_component
));
2930 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2932 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2934 inst
->offset
= imm_offset
;
2940 case nir_intrinsic_store_output
:
2941 case nir_intrinsic_store_per_vertex_output
: {
2942 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2943 fs_reg value
= get_nir_src(instr
->src
[0]);
2944 fs_reg indirect_offset
= get_indirect_offset(instr
);
2945 unsigned imm_offset
= instr
->const_index
[0];
2946 unsigned mask
= instr
->const_index
[1];
2947 unsigned header_regs
= 0;
2948 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2951 srcs
[header_regs
++] = output_handles
;
2953 if (indirect_offset
.file
!= BAD_FILE
) {
2954 srcs
[header_regs
++] = indirect_offset
;
2960 unsigned num_components
= util_last_bit(mask
);
2963 /* We can only pack two 64-bit components in a single message, so send
2964 * 2 messages if we have more components
2966 unsigned first_component
= nir_intrinsic_component(instr
);
2967 mask
= mask
<< first_component
;
2969 if (mask
!= WRITEMASK_XYZW
) {
2970 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2971 opcode
= indirect_offset
.file
!= BAD_FILE
?
2972 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2973 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2975 opcode
= indirect_offset
.file
!= BAD_FILE
?
2976 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2977 SHADER_OPCODE_URB_WRITE_SIMD8
;
2980 for (unsigned i
= 0; i
< num_components
; i
++) {
2981 if (!(mask
& (1 << (i
+ first_component
))))
2984 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2987 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2989 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2990 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2992 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2993 inst
->offset
= imm_offset
;
2999 nir_emit_intrinsic(bld
, instr
);
3005 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
3006 nir_intrinsic_instr
*instr
)
3008 assert(stage
== MESA_SHADER_TESS_EVAL
);
3009 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3012 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3013 dest
= get_nir_dest(instr
->dest
);
3015 switch (instr
->intrinsic
) {
3016 case nir_intrinsic_load_primitive_id
:
3017 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3019 case nir_intrinsic_load_tess_coord
:
3020 /* gl_TessCoord is part of the payload in g1-3 */
3021 for (unsigned i
= 0; i
< 3; i
++) {
3022 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3026 case nir_intrinsic_load_input
:
3027 case nir_intrinsic_load_per_vertex_input
: {
3028 assert(nir_dest_bit_size(instr
->dest
) == 32);
3029 fs_reg indirect_offset
= get_indirect_offset(instr
);
3030 unsigned imm_offset
= instr
->const_index
[0];
3031 unsigned first_component
= nir_intrinsic_component(instr
);
3034 if (indirect_offset
.file
== BAD_FILE
) {
3035 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3036 * which is 16 registers (since each holds 2 vec4 slots).
3038 const unsigned max_push_slots
= 32;
3039 if (imm_offset
< max_push_slots
) {
3040 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3041 for (int i
= 0; i
< instr
->num_components
; i
++) {
3042 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3043 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3046 tes_prog_data
->base
.urb_read_length
=
3047 MAX2(tes_prog_data
->base
.urb_read_length
,
3048 (imm_offset
/ 2) + 1);
3050 /* Replicate the patch handle to all enabled channels */
3051 const fs_reg srcs
[] = {
3052 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3054 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3055 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3057 if (first_component
!= 0) {
3058 unsigned read_components
=
3059 instr
->num_components
+ first_component
;
3060 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3061 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3063 inst
->size_written
= read_components
* REG_SIZE
;
3064 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3065 bld
.MOV(offset(dest
, bld
, i
),
3066 offset(tmp
, bld
, i
+ first_component
));
3069 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3071 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3074 inst
->offset
= imm_offset
;
3077 /* Indirect indexing - use per-slot offsets as well. */
3079 /* We can only read two double components with each URB read, so
3080 * we send two read messages in that case, each one loading up to
3081 * two double components.
3083 unsigned num_components
= instr
->num_components
;
3084 const fs_reg srcs
[] = {
3085 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3088 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3089 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3091 if (first_component
!= 0) {
3092 unsigned read_components
=
3093 num_components
+ first_component
;
3094 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3095 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3097 for (unsigned i
= 0; i
< num_components
; i
++) {
3098 bld
.MOV(offset(dest
, bld
, i
),
3099 offset(tmp
, bld
, i
+ first_component
));
3102 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3106 inst
->offset
= imm_offset
;
3107 inst
->size_written
= (num_components
+ first_component
) *
3108 inst
->dst
.component_size(inst
->exec_size
);
3113 nir_emit_intrinsic(bld
, instr
);
3119 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3120 nir_intrinsic_instr
*instr
)
3122 assert(stage
== MESA_SHADER_GEOMETRY
);
3123 fs_reg indirect_offset
;
3126 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3127 dest
= get_nir_dest(instr
->dest
);
3129 switch (instr
->intrinsic
) {
3130 case nir_intrinsic_load_primitive_id
:
3131 assert(stage
== MESA_SHADER_GEOMETRY
);
3132 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3133 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3134 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3137 case nir_intrinsic_load_input
:
3138 unreachable("load_input intrinsics are invalid for the GS stage");
3140 case nir_intrinsic_load_per_vertex_input
:
3141 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3142 instr
->src
[1], instr
->num_components
,
3143 nir_intrinsic_component(instr
));
3146 case nir_intrinsic_emit_vertex_with_counter
:
3147 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3150 case nir_intrinsic_end_primitive_with_counter
:
3151 emit_gs_end_primitive(instr
->src
[0]);
3154 case nir_intrinsic_set_vertex_count
:
3155 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3158 case nir_intrinsic_load_invocation_id
: {
3159 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3160 assert(val
.file
!= BAD_FILE
);
3161 dest
.type
= val
.type
;
3167 nir_emit_intrinsic(bld
, instr
);
3173 * Fetch the current render target layer index.
3176 fetch_render_target_array_index(const fs_builder
&bld
)
3178 if (bld
.shader
->devinfo
->gen
>= 6) {
3179 /* The render target array index is provided in the thread payload as
3180 * bits 26:16 of r0.0.
3182 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3183 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3187 /* Pre-SNB we only ever render into the first layer of the framebuffer
3188 * since layered rendering is not implemented.
3190 return brw_imm_ud(0);
3195 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3196 * framebuffer at the current fragment coordinates and sample index.
3199 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3202 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3204 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3205 const brw_wm_prog_key
*wm_key
=
3206 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3207 assert(!wm_key
->coherent_fb_fetch
);
3208 const struct brw_wm_prog_data
*wm_prog_data
=
3209 brw_wm_prog_data(stage_prog_data
);
3211 /* Calculate the surface index relative to the start of the texture binding
3212 * table block, since that's what the texturing messages expect.
3214 const unsigned surface
= target
+
3215 wm_prog_data
->binding_table
.render_target_read_start
-
3216 wm_prog_data
->base
.binding_table
.texture_start
;
3218 /* Calculate the fragment coordinates. */
3219 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3220 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3221 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3222 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3224 /* Calculate the sample index and MCS payload when multisampling. Luckily
3225 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3226 * shouldn't be necessary to recompile based on whether the framebuffer is
3229 if (wm_key
->multisample_fbo
&&
3230 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3231 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3233 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3234 const fs_reg mcs
= wm_key
->multisample_fbo
?
3235 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3237 /* Use either a normal or a CMS texel fetch message depending on whether
3238 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3239 * message just in case the framebuffer uses 16x multisampling, it should
3240 * be equivalent to the normal CMS fetch for lower multisampling modes.
3242 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3243 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3244 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3246 /* Emit the instruction. */
3247 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3248 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3249 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3250 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3251 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3252 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3253 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3254 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3255 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3257 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3258 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3264 * Actual coherent framebuffer read implemented using the native render target
3265 * read message. Requires SKL+.
3268 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3270 assert(bld
.shader
->devinfo
->gen
>= 9);
3271 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3272 inst
->target
= target
;
3273 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3279 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3281 if (n
&& regs
[0].file
!= BAD_FILE
) {
3285 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3287 for (unsigned i
= 0; i
< n
; i
++)
3295 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3297 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3298 const brw_wm_prog_key
*const key
=
3299 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3300 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3301 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3303 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3304 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3306 else if (l
== FRAG_RESULT_COLOR
)
3307 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3308 MAX2(key
->nr_color_regions
, 1));
3310 else if (l
== FRAG_RESULT_DEPTH
)
3311 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3313 else if (l
== FRAG_RESULT_STENCIL
)
3314 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3316 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3317 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3319 else if (l
>= FRAG_RESULT_DATA0
&&
3320 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3321 return alloc_temporary(v
->bld
, 4,
3322 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3325 unreachable("Invalid location");
3329 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3330 nir_intrinsic_instr
*instr
)
3332 assert(stage
== MESA_SHADER_FRAGMENT
);
3335 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3336 dest
= get_nir_dest(instr
->dest
);
3338 switch (instr
->intrinsic
) {
3339 case nir_intrinsic_load_front_face
:
3340 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3341 *emit_frontfacing_interpolation());
3344 case nir_intrinsic_load_sample_pos
: {
3345 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3346 assert(sample_pos
.file
!= BAD_FILE
);
3347 dest
.type
= sample_pos
.type
;
3348 bld
.MOV(dest
, sample_pos
);
3349 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3353 case nir_intrinsic_load_layer_id
:
3354 dest
.type
= BRW_REGISTER_TYPE_UD
;
3355 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3358 case nir_intrinsic_is_helper_invocation
: {
3359 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3360 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3361 * consideration demoted invocations. That information is stored in
3364 dest
.type
= BRW_REGISTER_TYPE_UD
;
3366 bld
.MOV(dest
, brw_imm_ud(0));
3368 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3369 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3370 mov
->predicate_inverse
= true;
3371 mov
->flag_subreg
= 1;
3375 case nir_intrinsic_load_helper_invocation
:
3376 case nir_intrinsic_load_sample_mask_in
:
3377 case nir_intrinsic_load_sample_id
: {
3378 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3379 fs_reg val
= nir_system_values
[sv
];
3380 assert(val
.file
!= BAD_FILE
);
3381 dest
.type
= val
.type
;
3386 case nir_intrinsic_store_output
: {
3387 const fs_reg src
= get_nir_src(instr
->src
[0]);
3388 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3389 const unsigned location
= nir_intrinsic_base(instr
) +
3390 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3391 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3394 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3395 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3396 offset(src
, bld
, j
));
3401 case nir_intrinsic_load_output
: {
3402 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3403 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3404 assert(l
>= FRAG_RESULT_DATA0
);
3405 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3406 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3407 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3409 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3410 emit_coherent_fb_read(bld
, tmp
, target
);
3412 emit_non_coherent_fb_read(bld
, tmp
, target
);
3414 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3415 bld
.MOV(offset(dest
, bld
, j
),
3416 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3422 case nir_intrinsic_demote
:
3423 case nir_intrinsic_discard
:
3424 case nir_intrinsic_demote_if
:
3425 case nir_intrinsic_discard_if
: {
3426 /* We track our discarded pixels in f0.1. By predicating on it, we can
3427 * update just the flag bits that aren't yet discarded. If there's no
3428 * condition, we emit a CMP of g0 != g0, so all currently executing
3429 * channels will get turned off.
3431 fs_inst
*cmp
= NULL
;
3432 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3433 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3434 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3437 alu
->op
!= nir_op_bcsel
&&
3438 alu
->op
!= nir_op_inot
&&
3439 (devinfo
->gen
> 5 ||
3440 (alu
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE
||
3441 alu
->op
== nir_op_fne32
|| alu
->op
== nir_op_feq32
||
3442 alu
->op
== nir_op_flt32
|| alu
->op
== nir_op_fge32
||
3443 alu
->op
== nir_op_ine32
|| alu
->op
== nir_op_ieq32
||
3444 alu
->op
== nir_op_ilt32
|| alu
->op
== nir_op_ige32
||
3445 alu
->op
== nir_op_ult32
|| alu
->op
== nir_op_uge32
)) {
3446 /* Re-emit the instruction that generated the Boolean value, but
3447 * do not store it. Since this instruction will be conditional,
3448 * other instructions that want to use the real Boolean value may
3449 * get garbage. This was a problem for piglit's fs-discard-exit-2
3452 * Ideally we'd detect that the instruction cannot have a
3453 * conditional modifier before emitting the instructions. Alas,
3454 * that is nigh impossible. Instead, we're going to assume the
3455 * instruction (or last instruction) generated can have a
3456 * conditional modifier. If it cannot, fallback to the old-style
3457 * compare, and hope dead code elimination will clean up the
3458 * extra instructions generated.
3460 nir_emit_alu(bld
, alu
, false);
3462 cmp
= (fs_inst
*) instructions
.get_tail();
3463 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3464 if (cmp
->can_do_cmod())
3465 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3469 /* The old sequence that would have been generated is,
3470 * basically, bool_result == false. This is equivalent to
3471 * !bool_result, so negate the old modifier.
3473 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3478 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3479 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3482 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3483 BRW_REGISTER_TYPE_UW
));
3484 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3487 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3488 cmp
->flag_subreg
= 1;
3490 if (devinfo
->gen
>= 6) {
3491 /* Due to the way we implement discard, the jump will only happen
3492 * when the whole quad is discarded. So we can do this even for
3493 * demote as it won't break its uniformity promises.
3495 emit_discard_jump();
3498 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
3502 case nir_intrinsic_load_input
: {
3503 /* load_input is only used for flat inputs */
3504 assert(nir_dest_bit_size(instr
->dest
) == 32);
3505 unsigned base
= nir_intrinsic_base(instr
);
3506 unsigned comp
= nir_intrinsic_component(instr
);
3507 unsigned num_components
= instr
->num_components
;
3509 /* Special case fields in the VUE header */
3510 if (base
== VARYING_SLOT_LAYER
)
3512 else if (base
== VARYING_SLOT_VIEWPORT
)
3515 for (unsigned int i
= 0; i
< num_components
; i
++) {
3516 bld
.MOV(offset(dest
, bld
, i
),
3517 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3522 case nir_intrinsic_load_fs_input_interp_deltas
: {
3523 assert(stage
== MESA_SHADER_FRAGMENT
);
3524 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3525 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3526 nir_intrinsic_component(instr
));
3527 dest
.type
= BRW_REGISTER_TYPE_F
;
3528 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3529 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3530 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3534 case nir_intrinsic_load_barycentric_pixel
:
3535 case nir_intrinsic_load_barycentric_centroid
:
3536 case nir_intrinsic_load_barycentric_sample
: {
3537 /* Use the delta_xy values computed from the payload */
3538 const glsl_interp_mode interp_mode
=
3539 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3540 enum brw_barycentric_mode bary
=
3541 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3542 const fs_reg srcs
[] = { offset(this->delta_xy
[bary
], bld
, 0),
3543 offset(this->delta_xy
[bary
], bld
, 1) };
3544 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3548 case nir_intrinsic_load_barycentric_at_sample
: {
3549 const glsl_interp_mode interpolation
=
3550 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3552 if (nir_src_is_const(instr
->src
[0])) {
3553 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3555 emit_pixel_interpolater_send(bld
,
3556 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3559 brw_imm_ud(msg_data
),
3562 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3563 BRW_REGISTER_TYPE_UD
);
3565 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3566 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3567 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3568 bld
.exec_all().group(1, 0)
3569 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3570 emit_pixel_interpolater_send(bld
,
3571 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3574 component(msg_data
, 0),
3577 /* Make a loop that sends a message to the pixel interpolater
3578 * for the sample number in each live channel. If there are
3579 * multiple channels with the same sample number then these
3580 * will be handled simultaneously with a single interation of
3583 bld
.emit(BRW_OPCODE_DO
);
3585 /* Get the next live sample number into sample_id_reg */
3586 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3588 /* Set the flag register so that we can perform the send
3589 * message on all channels that have the same sample number
3591 bld
.CMP(bld
.null_reg_ud(),
3592 sample_src
, sample_id
,
3593 BRW_CONDITIONAL_EQ
);
3594 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3595 bld
.exec_all().group(1, 0)
3596 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3598 emit_pixel_interpolater_send(bld
,
3599 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3602 component(msg_data
, 0),
3604 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3606 /* Continue the loop if there are any live channels left */
3607 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3609 bld
.emit(BRW_OPCODE_WHILE
));
3615 case nir_intrinsic_load_barycentric_at_offset
: {
3616 const glsl_interp_mode interpolation
=
3617 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3619 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3622 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3623 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3624 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3626 emit_pixel_interpolater_send(bld
,
3627 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3630 brw_imm_ud(off_x
| (off_y
<< 4)),
3633 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3634 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3635 BRW_REGISTER_TYPE_F
);
3636 for (int i
= 0; i
< 2; i
++) {
3637 fs_reg temp
= vgrf(glsl_type::float_type
);
3638 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3639 fs_reg itemp
= vgrf(glsl_type::int_type
);
3641 bld
.MOV(itemp
, temp
);
3643 /* Clamp the upper end of the range to +7/16.
3644 * ARB_gpu_shader5 requires that we support a maximum offset
3645 * of +0.5, which isn't representable in a S0.4 value -- if
3646 * we didn't clamp it, we'd end up with -8/16, which is the
3647 * opposite of what the shader author wanted.
3649 * This is legal due to ARB_gpu_shader5's quantization
3652 * "Not all values of <offset> may be supported; x and y
3653 * offsets may be rounded to fixed-point values with the
3654 * number of fraction bits given by the
3655 * implementation-dependent constant
3656 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3658 set_condmod(BRW_CONDITIONAL_L
,
3659 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3662 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3663 emit_pixel_interpolater_send(bld
,
3673 case nir_intrinsic_load_frag_coord
:
3674 emit_fragcoord_interpolation(dest
);
3677 case nir_intrinsic_load_interpolated_input
: {
3678 assert(instr
->src
[0].ssa
&&
3679 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3680 nir_intrinsic_instr
*bary_intrinsic
=
3681 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3682 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3683 enum glsl_interp_mode interp_mode
=
3684 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3687 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3688 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3689 /* Use the result of the PI message. */
3690 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3692 /* Use the delta_xy values computed from the payload */
3693 enum brw_barycentric_mode bary
=
3694 brw_barycentric_mode(interp_mode
, bary_intrin
);
3695 dst_xy
= this->delta_xy
[bary
];
3698 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3700 component(interp_reg(nir_intrinsic_base(instr
),
3701 nir_intrinsic_component(instr
) + i
), 0);
3702 interp
.type
= BRW_REGISTER_TYPE_F
;
3703 dest
.type
= BRW_REGISTER_TYPE_F
;
3705 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3706 fs_reg tmp
= vgrf(glsl_type::float_type
);
3707 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3708 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3710 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3717 nir_emit_intrinsic(bld
, instr
);
3723 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3724 nir_intrinsic_instr
*instr
)
3726 assert(stage
== MESA_SHADER_COMPUTE
);
3727 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3730 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3731 dest
= get_nir_dest(instr
->dest
);
3733 switch (instr
->intrinsic
) {
3734 case nir_intrinsic_control_barrier
:
3735 /* The whole workgroup fits in a single HW thread, so all the
3736 * invocations are already executed lock-step. Instead of an actual
3737 * barrier just emit a scheduling fence, that will generate no code.
3739 if (workgroup_size() <= dispatch_width
) {
3740 bld
.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE
);
3745 cs_prog_data
->uses_barrier
= true;
3748 case nir_intrinsic_load_subgroup_id
:
3749 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3752 case nir_intrinsic_load_local_invocation_id
:
3753 case nir_intrinsic_load_work_group_id
: {
3754 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3755 fs_reg val
= nir_system_values
[sv
];
3756 assert(val
.file
!= BAD_FILE
);
3757 dest
.type
= val
.type
;
3758 for (unsigned i
= 0; i
< 3; i
++)
3759 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3763 case nir_intrinsic_load_num_work_groups
: {
3764 const unsigned surface
=
3765 cs_prog_data
->binding_table
.work_groups_start
;
3767 cs_prog_data
->uses_num_work_groups
= true;
3769 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3770 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3771 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3772 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3774 /* Read the 3 GLuint components of gl_NumWorkGroups */
3775 for (unsigned i
= 0; i
< 3; i
++) {
3776 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3777 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3778 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3783 case nir_intrinsic_shared_atomic_add
:
3784 case nir_intrinsic_shared_atomic_imin
:
3785 case nir_intrinsic_shared_atomic_umin
:
3786 case nir_intrinsic_shared_atomic_imax
:
3787 case nir_intrinsic_shared_atomic_umax
:
3788 case nir_intrinsic_shared_atomic_and
:
3789 case nir_intrinsic_shared_atomic_or
:
3790 case nir_intrinsic_shared_atomic_xor
:
3791 case nir_intrinsic_shared_atomic_exchange
:
3792 case nir_intrinsic_shared_atomic_comp_swap
:
3793 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3795 case nir_intrinsic_shared_atomic_fmin
:
3796 case nir_intrinsic_shared_atomic_fmax
:
3797 case nir_intrinsic_shared_atomic_fcomp_swap
:
3798 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3801 case nir_intrinsic_load_shared
: {
3802 assert(devinfo
->gen
>= 7);
3803 assert(stage
== MESA_SHADER_COMPUTE
);
3805 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3806 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3807 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3808 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3809 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3811 /* Make dest unsigned because that's what the temporary will be */
3812 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3814 /* Read the vector */
3815 if (nir_intrinsic_align(instr
) >= 4) {
3816 assert(nir_dest_bit_size(instr
->dest
) == 32);
3817 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3819 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3820 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3821 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3823 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3824 assert(nir_dest_num_components(instr
->dest
) == 1);
3825 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3827 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3828 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3829 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3830 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3835 case nir_intrinsic_store_shared
: {
3836 assert(devinfo
->gen
>= 7);
3837 assert(stage
== MESA_SHADER_COMPUTE
);
3839 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3840 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3841 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3842 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3843 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3845 fs_reg data
= get_nir_src(instr
->src
[0]);
3846 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3848 assert(nir_intrinsic_write_mask(instr
) ==
3849 (1u << instr
->num_components
) - 1);
3850 if (nir_intrinsic_align(instr
) >= 4) {
3851 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3852 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3853 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3854 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3855 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3856 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3858 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3859 assert(nir_src_num_components(instr
->src
[0]) == 1);
3860 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3862 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3863 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3865 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3866 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3872 nir_emit_intrinsic(bld
, instr
);
3878 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3879 nir_op op
, brw_reg_type type
)
3881 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3882 switch (type_sz(type
)) {
3884 if (type
== BRW_REGISTER_TYPE_UB
) {
3885 return brw_imm_uw(value
.u8
);
3887 assert(type
== BRW_REGISTER_TYPE_B
);
3888 return brw_imm_w(value
.i8
);
3891 return retype(brw_imm_uw(value
.u16
), type
);
3893 return retype(brw_imm_ud(value
.u32
), type
);
3895 if (type
== BRW_REGISTER_TYPE_DF
)
3896 return setup_imm_df(bld
, value
.f64
);
3898 return retype(brw_imm_u64(value
.u64
), type
);
3900 unreachable("Invalid type size");
3905 brw_op_for_nir_reduction_op(nir_op op
)
3908 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3909 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3910 case nir_op_imul
: return BRW_OPCODE_MUL
;
3911 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3912 case nir_op_imin
: return BRW_OPCODE_SEL
;
3913 case nir_op_umin
: return BRW_OPCODE_SEL
;
3914 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3915 case nir_op_imax
: return BRW_OPCODE_SEL
;
3916 case nir_op_umax
: return BRW_OPCODE_SEL
;
3917 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3918 case nir_op_iand
: return BRW_OPCODE_AND
;
3919 case nir_op_ior
: return BRW_OPCODE_OR
;
3920 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3922 unreachable("Invalid reduction operation");
3926 static brw_conditional_mod
3927 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3930 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3931 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3932 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3933 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3934 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3935 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3936 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3937 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3938 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3939 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3940 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3941 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3942 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3944 unreachable("Invalid reduction operation");
3949 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3950 nir_intrinsic_instr
*instr
)
3952 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3953 fs_reg surf_index
= image
;
3955 if (stage_prog_data
->binding_table
.image_start
> 0) {
3956 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3958 brw_imm_ud(image
.d
+ stage_prog_data
->binding_table
.image_start
);
3960 surf_index
= vgrf(glsl_type::uint_type
);
3961 bld
.ADD(surf_index
, image
,
3962 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3966 return bld
.emit_uniformize(surf_index
);
3970 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3971 nir_intrinsic_instr
*instr
)
3973 /* SSBO stores are weird in that their index is in src[1] */
3974 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3977 if (nir_src_is_const(instr
->src
[src
])) {
3978 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3979 nir_src_as_uint(instr
->src
[src
]);
3980 surf_index
= brw_imm_ud(index
);
3982 surf_index
= vgrf(glsl_type::uint_type
);
3983 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3984 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3987 return bld
.emit_uniformize(surf_index
);
3991 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3993 switch (nir_intrinsic_image_dim(instr
)) {
3994 case GLSL_SAMPLER_DIM_1D
:
3995 return 1 + nir_intrinsic_image_array(instr
);
3996 case GLSL_SAMPLER_DIM_2D
:
3997 case GLSL_SAMPLER_DIM_RECT
:
3998 return 2 + nir_intrinsic_image_array(instr
);
3999 case GLSL_SAMPLER_DIM_3D
:
4000 case GLSL_SAMPLER_DIM_CUBE
:
4002 case GLSL_SAMPLER_DIM_BUF
:
4004 case GLSL_SAMPLER_DIM_MS
:
4005 return 2 + nir_intrinsic_image_array(instr
);
4007 unreachable("Invalid image dimension");
4012 * The offsets we get from NIR act as if each SIMD channel has it's own blob
4013 * of contiguous space. However, if we actually place each SIMD channel in
4014 * it's own space, we end up with terrible cache performance because each SIMD
4015 * channel accesses a different cache line even when they're all accessing the
4016 * same byte offset. To deal with this problem, we swizzle the address using
4017 * a simple algorithm which ensures that any time a SIMD message reads or
4018 * writes the same address, it's all in the same cache line. We have to keep
4019 * the bottom two bits fixed so that we can read/write up to a dword at a time
4020 * and the individual element is contiguous. We do this by splitting the
4021 * address as follows:
4024 * +-------------------------------+------------+----------+
4025 * | Hi address bits | chan index | addr low |
4026 * +-------------------------------+------------+----------+
4028 * In other words, the bottom two address bits stay, and the top 30 get
4029 * shifted up so that we can stick the SIMD channel index in the middle. This
4030 * way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
4031 * at the same logical offset, the scratch read/write instruction acts on
4032 * continuous elements and we get good cache locality.
4035 fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
4036 const fs_reg
&nir_addr
,
4039 const fs_reg
&chan_index
=
4040 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
4041 const unsigned chan_index_bits
= ffs(dispatch_width
) - 1;
4043 fs_reg addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4045 /* In this case, we know the address is aligned to a DWORD and we want
4046 * the final address in DWORDs.
4048 bld
.SHL(addr
, nir_addr
, brw_imm_ud(chan_index_bits
- 2));
4049 bld
.OR(addr
, addr
, chan_index
);
4051 /* This case substantially more annoying because we have to pay
4052 * attention to those pesky two bottom bits.
4054 fs_reg addr_hi
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4055 bld
.AND(addr_hi
, nir_addr
, brw_imm_ud(~0x3u
));
4056 bld
.SHL(addr_hi
, addr_hi
, brw_imm_ud(chan_index_bits
));
4057 fs_reg chan_addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4058 bld
.SHL(chan_addr
, chan_index
, brw_imm_ud(2));
4059 bld
.AND(addr
, nir_addr
, brw_imm_ud(0x3u
));
4060 bld
.OR(addr
, addr
, addr_hi
);
4061 bld
.OR(addr
, addr
, chan_addr
);
4067 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4070 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4071 dest
= get_nir_dest(instr
->dest
);
4073 switch (instr
->intrinsic
) {
4074 case nir_intrinsic_image_load
:
4075 case nir_intrinsic_image_store
:
4076 case nir_intrinsic_image_atomic_add
:
4077 case nir_intrinsic_image_atomic_imin
:
4078 case nir_intrinsic_image_atomic_umin
:
4079 case nir_intrinsic_image_atomic_imax
:
4080 case nir_intrinsic_image_atomic_umax
:
4081 case nir_intrinsic_image_atomic_and
:
4082 case nir_intrinsic_image_atomic_or
:
4083 case nir_intrinsic_image_atomic_xor
:
4084 case nir_intrinsic_image_atomic_exchange
:
4085 case nir_intrinsic_image_atomic_comp_swap
:
4086 case nir_intrinsic_bindless_image_load
:
4087 case nir_intrinsic_bindless_image_store
:
4088 case nir_intrinsic_bindless_image_atomic_add
:
4089 case nir_intrinsic_bindless_image_atomic_imin
:
4090 case nir_intrinsic_bindless_image_atomic_umin
:
4091 case nir_intrinsic_bindless_image_atomic_imax
:
4092 case nir_intrinsic_bindless_image_atomic_umax
:
4093 case nir_intrinsic_bindless_image_atomic_and
:
4094 case nir_intrinsic_bindless_image_atomic_or
:
4095 case nir_intrinsic_bindless_image_atomic_xor
:
4096 case nir_intrinsic_bindless_image_atomic_exchange
:
4097 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4098 if (stage
== MESA_SHADER_FRAGMENT
&&
4099 instr
->intrinsic
!= nir_intrinsic_image_load
)
4100 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4102 /* Get some metadata from the image intrinsic. */
4103 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4105 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4107 switch (instr
->intrinsic
) {
4108 case nir_intrinsic_image_load
:
4109 case nir_intrinsic_image_store
:
4110 case nir_intrinsic_image_atomic_add
:
4111 case nir_intrinsic_image_atomic_imin
:
4112 case nir_intrinsic_image_atomic_umin
:
4113 case nir_intrinsic_image_atomic_imax
:
4114 case nir_intrinsic_image_atomic_umax
:
4115 case nir_intrinsic_image_atomic_and
:
4116 case nir_intrinsic_image_atomic_or
:
4117 case nir_intrinsic_image_atomic_xor
:
4118 case nir_intrinsic_image_atomic_exchange
:
4119 case nir_intrinsic_image_atomic_comp_swap
:
4120 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4121 get_nir_image_intrinsic_image(bld
, instr
);
4126 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4127 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4131 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4132 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4133 brw_imm_ud(image_intrinsic_coord_components(instr
));
4135 /* Emit an image load, store or atomic op. */
4136 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4137 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4138 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4140 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4141 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4142 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4143 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4144 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4145 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4146 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4147 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4148 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4150 unsigned num_srcs
= info
->num_srcs
;
4151 int op
= brw_aop_for_nir_intrinsic(instr
);
4152 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4153 assert(num_srcs
== 4);
4157 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4161 data
= get_nir_src(instr
->src
[3]);
4162 if (num_srcs
>= 5) {
4163 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4164 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4165 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4168 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4170 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4171 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4176 case nir_intrinsic_image_size
:
4177 case nir_intrinsic_bindless_image_size
: {
4178 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4179 * into will handle the binding table index for us in the geneerator.
4180 * Incidentally, this means that we can handle bindless with exactly the
4183 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4184 BRW_REGISTER_TYPE_UD
);
4185 image
= bld
.emit_uniformize(image
);
4187 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4188 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4189 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4191 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4192 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4193 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4194 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4196 /* Since the image size is always uniform, we can just emit a SIMD8
4197 * query instruction and splat the result out.
4199 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4201 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4202 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4203 tmp
, srcs
, ARRAY_SIZE(srcs
));
4204 inst
->size_written
= 4 * REG_SIZE
;
4206 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4207 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4208 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4209 offset(retype(dest
, tmp
.type
), bld
, c
),
4210 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4212 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4213 component(offset(tmp
, ubld
, c
), 0));
4219 case nir_intrinsic_image_load_raw_intel
: {
4220 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4221 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4222 get_nir_image_intrinsic_image(bld
, instr
);
4223 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4224 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4225 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4228 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4229 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4230 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4234 case nir_intrinsic_image_store_raw_intel
: {
4235 if (stage
== MESA_SHADER_FRAGMENT
)
4236 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4238 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4239 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4240 get_nir_image_intrinsic_image(bld
, instr
);
4241 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4242 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4243 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4244 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4246 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4247 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4251 case nir_intrinsic_scoped_memory_barrier
:
4252 case nir_intrinsic_group_memory_barrier
:
4253 case nir_intrinsic_memory_barrier_shared
:
4254 case nir_intrinsic_memory_barrier_buffer
:
4255 case nir_intrinsic_memory_barrier_image
:
4256 case nir_intrinsic_memory_barrier
: {
4257 bool l3_fence
, slm_fence
;
4258 if (instr
->intrinsic
== nir_intrinsic_scoped_memory_barrier
) {
4259 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4260 l3_fence
= modes
& (nir_var_shader_out
|
4262 nir_var_mem_global
);
4263 slm_fence
= modes
& nir_var_mem_shared
;
4265 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4266 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4267 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4268 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4271 if (stage
!= MESA_SHADER_COMPUTE
)
4274 /* If the workgroup fits in a single HW thread, the messages for SLM are
4275 * processed in-order and the shader itself is already synchronized so
4276 * the memory fence is not necessary.
4278 * TODO: Check if applies for many HW threads sharing same Data Port.
4280 if (slm_fence
&& workgroup_size() <= dispatch_width
)
4283 /* Prior to Gen11, there's only L3 fence, so emit that instead. */
4284 if (slm_fence
&& devinfo
->gen
< 11) {
4289 /* Be conservative in Gen11+ and always stall in a fence. Since there
4290 * are two different fences, and shader might want to synchronize
4293 * TODO: Improve NIR so that scope and visibility information for the
4294 * barriers is available here to make a better decision.
4296 * TODO: When emitting more than one fence, it might help emit all
4297 * the fences first and then generate the stall moves.
4299 const bool stall
= devinfo
->gen
>= 11;
4301 const fs_builder ubld
= bld
.group(8, 0);
4302 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4305 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4306 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4307 /* bti */ brw_imm_ud(0))
4308 ->size_written
= 2 * REG_SIZE
;
4312 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4313 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4314 brw_imm_ud(GEN7_BTI_SLM
))
4315 ->size_written
= 2 * REG_SIZE
;
4318 if (!l3_fence
&& !slm_fence
)
4319 ubld
.emit(FS_OPCODE_SCHEDULING_FENCE
);
4324 case nir_intrinsic_memory_barrier_tcs_patch
:
4327 case nir_intrinsic_shader_clock
: {
4328 /* We cannot do anything if there is an event, so ignore it for now */
4329 const fs_reg shader_clock
= get_timestamp(bld
);
4330 const fs_reg srcs
[] = { component(shader_clock
, 0),
4331 component(shader_clock
, 1) };
4332 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4336 case nir_intrinsic_image_samples
:
4337 /* The driver does not support multi-sampled images. */
4338 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4341 case nir_intrinsic_load_uniform
: {
4342 /* Offsets are in bytes but they should always aligned to
4345 assert(instr
->const_index
[0] % 4 == 0 ||
4346 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4348 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4350 if (nir_src_is_const(instr
->src
[0])) {
4351 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4352 assert(load_offset
% type_sz(dest
.type
) == 0);
4353 /* For 16-bit types we add the module of the const_index[0]
4354 * offset to access to not 32-bit aligned element
4356 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4358 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4359 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4362 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4363 BRW_REGISTER_TYPE_UD
);
4365 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4366 * go past the end of the uniform. In order to keep the n'th
4367 * component from running past, we subtract off the size of all but
4368 * one component of the vector.
4370 assert(instr
->const_index
[1] >=
4371 instr
->num_components
* (int) type_sz(dest
.type
));
4372 unsigned read_size
= instr
->const_index
[1] -
4373 (instr
->num_components
- 1) * type_sz(dest
.type
);
4375 bool supports_64bit_indirects
=
4376 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4378 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4379 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4380 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4381 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4382 indirect
, brw_imm_ud(read_size
));
4385 const unsigned num_mov_indirects
=
4386 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4387 /* We read a little bit less per MOV INDIRECT, as they are now
4388 * 32-bits ones instead of 64-bit. Fix read_size then.
4390 const unsigned read_size_32bit
= read_size
-
4391 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4392 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4393 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4394 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4395 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4396 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4397 indirect
, brw_imm_ud(read_size_32bit
));
4405 case nir_intrinsic_load_ubo
: {
4407 if (nir_src_is_const(instr
->src
[0])) {
4408 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4409 nir_src_as_uint(instr
->src
[0]);
4410 surf_index
= brw_imm_ud(index
);
4412 /* The block index is not a constant. Evaluate the index expression
4413 * per-channel and add the base UBO index; we have to select a value
4414 * from any live channel.
4416 surf_index
= vgrf(glsl_type::uint_type
);
4417 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4418 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4419 surf_index
= bld
.emit_uniformize(surf_index
);
4422 if (!nir_src_is_const(instr
->src
[1])) {
4423 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4424 BRW_REGISTER_TYPE_UD
);
4426 for (int i
= 0; i
< instr
->num_components
; i
++)
4427 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4428 base_offset
, i
* type_sz(dest
.type
));
4430 prog_data
->has_ubo_pull
= true;
4432 /* Even if we are loading doubles, a pull constant load will load
4433 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4434 * need to load a full dvec4 we will have to emit 2 loads. This is
4435 * similar to demote_pull_constants(), except that in that case we
4436 * see individual accesses to each component of the vector and then
4437 * we let CSE deal with duplicate loads. Here we see a vector access
4438 * and we have to split it if necessary.
4440 const unsigned type_size
= type_sz(dest
.type
);
4441 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4443 /* See if we've selected this as a push constant candidate */
4444 if (nir_src_is_const(instr
->src
[0])) {
4445 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4446 const unsigned offset_256b
= load_offset
/ 32;
4449 for (int i
= 0; i
< 4; i
++) {
4450 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4451 if (range
->block
== ubo_block
&&
4452 offset_256b
>= range
->start
&&
4453 offset_256b
< range
->start
+ range
->length
) {
4455 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4456 push_reg
.offset
= load_offset
- 32 * range
->start
;
4461 if (push_reg
.file
!= BAD_FILE
) {
4462 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4463 bld
.MOV(offset(dest
, bld
, i
),
4464 byte_offset(push_reg
, i
* type_size
));
4470 prog_data
->has_ubo_pull
= true;
4472 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4473 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4474 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4476 for (unsigned c
= 0; c
< instr
->num_components
;) {
4477 const unsigned base
= load_offset
+ c
* type_size
;
4478 /* Number of usable components in the next block-aligned load. */
4479 const unsigned count
= MIN2(instr
->num_components
- c
,
4480 (block_sz
- base
% block_sz
) / type_size
);
4482 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4483 packed_consts
, surf_index
,
4484 brw_imm_ud(base
& ~(block_sz
- 1)));
4486 const fs_reg consts
=
4487 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4490 for (unsigned d
= 0; d
< count
; d
++)
4491 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4499 case nir_intrinsic_load_global
: {
4500 assert(devinfo
->gen
>= 8);
4502 if (nir_intrinsic_align(instr
) >= 4) {
4503 assert(nir_dest_bit_size(instr
->dest
) == 32);
4504 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4506 get_nir_src(instr
->src
[0]), /* Address */
4507 fs_reg(), /* No source data */
4508 brw_imm_ud(instr
->num_components
));
4509 inst
->size_written
= instr
->num_components
*
4510 inst
->dst
.component_size(inst
->exec_size
);
4512 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4513 assert(bit_size
<= 32);
4514 assert(nir_dest_num_components(instr
->dest
) == 1);
4515 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4516 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4518 get_nir_src(instr
->src
[0]), /* Address */
4519 fs_reg(), /* No source data */
4520 brw_imm_ud(bit_size
));
4521 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4526 case nir_intrinsic_store_global
:
4527 assert(devinfo
->gen
>= 8);
4529 if (stage
== MESA_SHADER_FRAGMENT
)
4530 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4532 if (nir_intrinsic_align(instr
) >= 4) {
4533 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4534 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4536 get_nir_src(instr
->src
[1]), /* Address */
4537 get_nir_src(instr
->src
[0]), /* Data */
4538 brw_imm_ud(instr
->num_components
));
4540 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4541 assert(bit_size
<= 32);
4542 assert(nir_src_num_components(instr
->src
[0]) == 1);
4543 brw_reg_type data_type
=
4544 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4545 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4546 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4547 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4549 get_nir_src(instr
->src
[1]), /* Address */
4551 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4555 case nir_intrinsic_global_atomic_add
:
4556 case nir_intrinsic_global_atomic_imin
:
4557 case nir_intrinsic_global_atomic_umin
:
4558 case nir_intrinsic_global_atomic_imax
:
4559 case nir_intrinsic_global_atomic_umax
:
4560 case nir_intrinsic_global_atomic_and
:
4561 case nir_intrinsic_global_atomic_or
:
4562 case nir_intrinsic_global_atomic_xor
:
4563 case nir_intrinsic_global_atomic_exchange
:
4564 case nir_intrinsic_global_atomic_comp_swap
:
4565 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4567 case nir_intrinsic_global_atomic_fmin
:
4568 case nir_intrinsic_global_atomic_fmax
:
4569 case nir_intrinsic_global_atomic_fcomp_swap
:
4570 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4573 case nir_intrinsic_load_ssbo
: {
4574 assert(devinfo
->gen
>= 7);
4576 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4577 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4578 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4579 get_nir_ssbo_intrinsic_index(bld
, instr
);
4580 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4581 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4583 /* Make dest unsigned because that's what the temporary will be */
4584 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4586 /* Read the vector */
4587 if (nir_intrinsic_align(instr
) >= 4) {
4588 assert(nir_dest_bit_size(instr
->dest
) == 32);
4589 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4591 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4592 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4593 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4595 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4596 assert(nir_dest_num_components(instr
->dest
) == 1);
4597 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4599 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4600 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4601 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4602 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4607 case nir_intrinsic_store_ssbo
: {
4608 assert(devinfo
->gen
>= 7);
4610 if (stage
== MESA_SHADER_FRAGMENT
)
4611 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4613 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4614 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4615 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4616 get_nir_ssbo_intrinsic_index(bld
, instr
);
4617 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4618 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4620 fs_reg data
= get_nir_src(instr
->src
[0]);
4621 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4623 assert(nir_intrinsic_write_mask(instr
) ==
4624 (1u << instr
->num_components
) - 1);
4625 if (nir_intrinsic_align(instr
) >= 4) {
4626 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4627 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4628 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4629 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4630 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4631 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4633 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4634 assert(nir_src_num_components(instr
->src
[0]) == 1);
4635 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4637 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4638 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4640 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4641 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4646 case nir_intrinsic_store_output
: {
4647 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4648 fs_reg src
= get_nir_src(instr
->src
[0]);
4650 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4651 unsigned num_components
= instr
->num_components
;
4652 unsigned first_component
= nir_intrinsic_component(instr
);
4654 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4655 4 * store_offset
), src
.type
);
4656 for (unsigned j
= 0; j
< num_components
; j
++) {
4657 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4658 offset(src
, bld
, j
));
4663 case nir_intrinsic_ssbo_atomic_add
:
4664 case nir_intrinsic_ssbo_atomic_imin
:
4665 case nir_intrinsic_ssbo_atomic_umin
:
4666 case nir_intrinsic_ssbo_atomic_imax
:
4667 case nir_intrinsic_ssbo_atomic_umax
:
4668 case nir_intrinsic_ssbo_atomic_and
:
4669 case nir_intrinsic_ssbo_atomic_or
:
4670 case nir_intrinsic_ssbo_atomic_xor
:
4671 case nir_intrinsic_ssbo_atomic_exchange
:
4672 case nir_intrinsic_ssbo_atomic_comp_swap
:
4673 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4675 case nir_intrinsic_ssbo_atomic_fmin
:
4676 case nir_intrinsic_ssbo_atomic_fmax
:
4677 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4678 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4681 case nir_intrinsic_get_buffer_size
: {
4682 assert(nir_src_num_components(instr
->src
[0]) == 1);
4683 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4684 nir_src_as_uint(instr
->src
[0]) : 0;
4686 /* A resinfo's sampler message is used to get the buffer size. The
4687 * SIMD8's writeback message consists of four registers and SIMD16's
4688 * writeback message consists of 8 destination registers (two per each
4689 * component). Because we are only interested on the first channel of
4690 * the first returned component, where resinfo returns the buffer size
4691 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4692 * the dispatch width.
4694 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4695 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4696 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4699 ubld
.MOV(src_payload
, brw_imm_d(0));
4701 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4702 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4703 src_payload
, brw_imm_ud(index
));
4704 inst
->header_size
= 0;
4706 inst
->size_written
= 4 * REG_SIZE
;
4708 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4710 * "Out-of-bounds checking is always performed at a DWord granularity. If
4711 * any part of the DWord is out-of-bounds then the whole DWord is
4712 * considered out-of-bounds."
4714 * This implies that types with size smaller than 4-bytes need to be
4715 * padded if they don't complete the last dword of the buffer. But as we
4716 * need to maintain the original size we need to reverse the padding
4717 * calculation to return the correct size to know the number of elements
4718 * of an unsized array. As we stored in the last two bits of the surface
4719 * size the needed padding for the buffer, we calculate here the
4720 * original buffer_size reversing the surface_size calculation:
4722 * surface_size = isl_align(buffer_size, 4) +
4723 * (isl_align(buffer_size) - buffer_size)
4725 * buffer_size = surface_size & ~3 - surface_size & 3
4728 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4729 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4730 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4732 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4733 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4734 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4736 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4740 case nir_intrinsic_load_scratch
: {
4741 assert(devinfo
->gen
>= 7);
4743 assert(nir_dest_num_components(instr
->dest
) == 1);
4744 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4745 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4747 if (devinfo
->gen
>= 8) {
4748 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4749 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4751 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4754 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4755 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4756 const fs_reg nir_addr
= get_nir_src(instr
->src
[0]);
4758 /* Make dest unsigned because that's what the temporary will be */
4759 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4761 /* Read the vector */
4762 if (nir_intrinsic_align(instr
) >= 4) {
4763 assert(nir_dest_bit_size(instr
->dest
) == 32);
4765 /* The offset for a DWORD scattered message is in dwords. */
4766 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4767 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4769 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
,
4770 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4772 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4774 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4775 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4777 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4778 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4779 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4780 bld
.MOV(dest
, read_result
);
4785 case nir_intrinsic_store_scratch
: {
4786 assert(devinfo
->gen
>= 7);
4788 assert(nir_src_num_components(instr
->src
[0]) == 1);
4789 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4790 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4792 if (devinfo
->gen
>= 8) {
4793 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4794 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4796 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4799 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4800 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4801 const fs_reg nir_addr
= get_nir_src(instr
->src
[1]);
4803 fs_reg data
= get_nir_src(instr
->src
[0]);
4804 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4806 assert(nir_intrinsic_write_mask(instr
) ==
4807 (1u << instr
->num_components
) - 1);
4808 if (nir_intrinsic_align(instr
) >= 4) {
4809 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4810 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4812 /* The offset for a DWORD scattered message is in dwords. */
4813 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4814 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4816 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
,
4817 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4819 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4821 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4822 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4824 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4825 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4827 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4828 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4833 case nir_intrinsic_load_subgroup_size
:
4834 /* This should only happen for fragment shaders because every other case
4835 * is lowered in NIR so we can optimize on it.
4837 assert(stage
== MESA_SHADER_FRAGMENT
);
4838 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4841 case nir_intrinsic_load_subgroup_invocation
:
4842 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4843 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4846 case nir_intrinsic_load_subgroup_eq_mask
:
4847 case nir_intrinsic_load_subgroup_ge_mask
:
4848 case nir_intrinsic_load_subgroup_gt_mask
:
4849 case nir_intrinsic_load_subgroup_le_mask
:
4850 case nir_intrinsic_load_subgroup_lt_mask
:
4851 unreachable("not reached");
4853 case nir_intrinsic_vote_any
: {
4854 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4856 /* The any/all predicates do not consider channel enables. To prevent
4857 * dead channels from affecting the result, we initialize the flag with
4858 * with the identity value for the logical operation.
4860 if (dispatch_width
== 32) {
4861 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4862 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4865 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4867 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4869 /* For some reason, the any/all predicates don't work properly with
4870 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4871 * doesn't read the correct subset of the flag register and you end up
4872 * getting garbage in the second half. Work around this by using a pair
4873 * of 1-wide MOVs and scattering the result.
4875 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4876 ubld
.MOV(res1
, brw_imm_d(0));
4877 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4878 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4879 BRW_PREDICATE_ALIGN1_ANY32H
,
4880 ubld
.MOV(res1
, brw_imm_d(-1)));
4882 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4885 case nir_intrinsic_vote_all
: {
4886 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4888 /* The any/all predicates do not consider channel enables. To prevent
4889 * dead channels from affecting the result, we initialize the flag with
4890 * with the identity value for the logical operation.
4892 if (dispatch_width
== 32) {
4893 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4894 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4895 brw_imm_ud(0xffffffff));
4897 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4899 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4901 /* For some reason, the any/all predicates don't work properly with
4902 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4903 * doesn't read the correct subset of the flag register and you end up
4904 * getting garbage in the second half. Work around this by using a pair
4905 * of 1-wide MOVs and scattering the result.
4907 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4908 ubld
.MOV(res1
, brw_imm_d(0));
4909 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4910 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4911 BRW_PREDICATE_ALIGN1_ALL32H
,
4912 ubld
.MOV(res1
, brw_imm_d(-1)));
4914 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4917 case nir_intrinsic_vote_feq
:
4918 case nir_intrinsic_vote_ieq
: {
4919 fs_reg value
= get_nir_src(instr
->src
[0]);
4920 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4921 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4922 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4923 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4926 fs_reg uniformized
= bld
.emit_uniformize(value
);
4927 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4929 /* The any/all predicates do not consider channel enables. To prevent
4930 * dead channels from affecting the result, we initialize the flag with
4931 * with the identity value for the logical operation.
4933 if (dispatch_width
== 32) {
4934 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4935 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4936 brw_imm_ud(0xffffffff));
4938 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4940 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4942 /* For some reason, the any/all predicates don't work properly with
4943 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4944 * doesn't read the correct subset of the flag register and you end up
4945 * getting garbage in the second half. Work around this by using a pair
4946 * of 1-wide MOVs and scattering the result.
4948 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4949 ubld
.MOV(res1
, brw_imm_d(0));
4950 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4951 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4952 BRW_PREDICATE_ALIGN1_ALL32H
,
4953 ubld
.MOV(res1
, brw_imm_d(-1)));
4955 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4959 case nir_intrinsic_ballot
: {
4960 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4961 BRW_REGISTER_TYPE_UD
);
4962 struct brw_reg flag
= brw_flag_reg(0, 0);
4963 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4964 * as f0.0. This is a problem for fragment programs as we currently use
4965 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4966 * programs yet so this isn't a problem. When we do, something will
4969 if (dispatch_width
== 32)
4970 flag
.type
= BRW_REGISTER_TYPE_UD
;
4972 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4973 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4975 if (instr
->dest
.ssa
.bit_size
> 32) {
4976 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4978 dest
.type
= BRW_REGISTER_TYPE_UD
;
4980 bld
.MOV(dest
, flag
);
4984 case nir_intrinsic_read_invocation
: {
4985 const fs_reg value
= get_nir_src(instr
->src
[0]);
4986 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4987 fs_reg tmp
= bld
.vgrf(value
.type
);
4989 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4990 bld
.emit_uniformize(invocation
));
4992 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4996 case nir_intrinsic_read_first_invocation
: {
4997 const fs_reg value
= get_nir_src(instr
->src
[0]);
4998 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
5002 case nir_intrinsic_shuffle
: {
5003 const fs_reg value
= get_nir_src(instr
->src
[0]);
5004 const fs_reg index
= get_nir_src(instr
->src
[1]);
5006 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
5010 case nir_intrinsic_first_invocation
: {
5011 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5012 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
5013 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
5014 fs_reg(component(tmp
, 0)));
5018 case nir_intrinsic_quad_broadcast
: {
5019 const fs_reg value
= get_nir_src(instr
->src
[0]);
5020 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
5022 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
5023 value
, brw_imm_ud(index
), brw_imm_ud(4));
5027 case nir_intrinsic_quad_swap_horizontal
: {
5028 const fs_reg value
= get_nir_src(instr
->src
[0]);
5029 const fs_reg tmp
= bld
.vgrf(value
.type
);
5030 if (devinfo
->gen
<= 7) {
5031 /* The hardware doesn't seem to support these crazy regions with
5032 * compressed instructions on gen7 and earlier so we fall back to
5033 * using quad swizzles. Fortunately, we don't support 64-bit
5034 * anything in Vulkan on gen7.
5036 assert(nir_src_bit_size(instr
->src
[0]) == 32);
5037 const fs_builder ubld
= bld
.exec_all();
5038 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5039 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
5040 bld
.MOV(retype(dest
, value
.type
), tmp
);
5042 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
5044 const fs_reg src_left
= horiz_stride(value
, 2);
5045 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
5046 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
5047 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
5049 ubld
.MOV(tmp_left
, src_right
);
5050 ubld
.MOV(tmp_right
, src_left
);
5053 bld
.MOV(retype(dest
, value
.type
), tmp
);
5057 case nir_intrinsic_quad_swap_vertical
: {
5058 const fs_reg value
= get_nir_src(instr
->src
[0]);
5059 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5060 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5061 const fs_reg tmp
= bld
.vgrf(value
.type
);
5062 const fs_builder ubld
= bld
.exec_all();
5063 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5064 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5065 bld
.MOV(retype(dest
, value
.type
), tmp
);
5067 /* For larger data types, we have to either emit dispatch_width many
5068 * MOVs or else fall back to doing indirects.
5070 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5071 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5073 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5078 case nir_intrinsic_quad_swap_diagonal
: {
5079 const fs_reg value
= get_nir_src(instr
->src
[0]);
5080 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5081 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5082 const fs_reg tmp
= bld
.vgrf(value
.type
);
5083 const fs_builder ubld
= bld
.exec_all();
5084 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5085 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5086 bld
.MOV(retype(dest
, value
.type
), tmp
);
5088 /* For larger data types, we have to either emit dispatch_width many
5089 * MOVs or else fall back to doing indirects.
5091 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5092 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5094 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5099 case nir_intrinsic_reduce
: {
5100 fs_reg src
= get_nir_src(instr
->src
[0]);
5101 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5102 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5103 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5104 cluster_size
= dispatch_width
;
5106 /* Figure out the source type */
5107 src
.type
= brw_type_for_nir_type(devinfo
,
5108 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5109 nir_src_bit_size(instr
->src
[0])));
5111 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5112 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5113 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5115 /* There are a couple of register region issues that make things
5116 * complicated for 8-bit types:
5118 * 1. Only raw moves are allowed to write to a packed 8-bit
5120 * 2. If we use a strided destination, the efficient way to do scan
5121 * operations ends up using strides that are too big to encode in
5124 * To get around these issues, we just do all 8-bit scan operations in
5125 * 16 bits. It's actually fewer instructions than what we'd have to do
5126 * if we were trying to do it in native 8-bit types and the results are
5127 * the same once we truncate to 8 bits at the end.
5129 brw_reg_type scan_type
= src
.type
;
5130 if (type_sz(scan_type
) == 1)
5131 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5133 /* Set up a register for all of our scratching around and initialize it
5134 * to reduction operation's identity value.
5136 fs_reg scan
= bld
.vgrf(scan_type
);
5137 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5139 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5141 dest
.type
= src
.type
;
5142 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5143 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5144 * the distance between clusters is at least 2 GRFs. In this case,
5145 * we don't need the weird striding of the CLUSTER_BROADCAST
5146 * instruction and can just do regular MOVs.
5148 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5149 const unsigned groups
=
5150 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5151 const unsigned group_size
= dispatch_width
/ groups
;
5152 for (unsigned i
= 0; i
< groups
; i
++) {
5153 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5154 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5155 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5156 component(scan
, comp
));
5159 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5160 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5165 case nir_intrinsic_inclusive_scan
:
5166 case nir_intrinsic_exclusive_scan
: {
5167 fs_reg src
= get_nir_src(instr
->src
[0]);
5168 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5170 /* Figure out the source type */
5171 src
.type
= brw_type_for_nir_type(devinfo
,
5172 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5173 nir_src_bit_size(instr
->src
[0])));
5175 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5176 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5177 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5179 /* There are a couple of register region issues that make things
5180 * complicated for 8-bit types:
5182 * 1. Only raw moves are allowed to write to a packed 8-bit
5184 * 2. If we use a strided destination, the efficient way to do scan
5185 * operations ends up using strides that are too big to encode in
5188 * To get around these issues, we just do all 8-bit scan operations in
5189 * 16 bits. It's actually fewer instructions than what we'd have to do
5190 * if we were trying to do it in native 8-bit types and the results are
5191 * the same once we truncate to 8 bits at the end.
5193 brw_reg_type scan_type
= src
.type
;
5194 if (type_sz(scan_type
) == 1)
5195 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5197 /* Set up a register for all of our scratching around and initialize it
5198 * to reduction operation's identity value.
5200 fs_reg scan
= bld
.vgrf(scan_type
);
5201 const fs_builder allbld
= bld
.exec_all();
5202 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5204 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5205 /* Exclusive scan is a bit harder because we have to do an annoying
5206 * shift of the contents before we can begin. To make things worse,
5207 * we can't do this with a normal stride; we have to use indirects.
5209 fs_reg shifted
= bld
.vgrf(scan_type
);
5210 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5211 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5213 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5214 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5218 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5220 bld
.MOV(retype(dest
, src
.type
), scan
);
5224 case nir_intrinsic_begin_invocation_interlock
: {
5225 const fs_builder ubld
= bld
.group(8, 0);
5226 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5228 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5229 ->size_written
= 2 * REG_SIZE
;
5233 case nir_intrinsic_end_invocation_interlock
: {
5234 /* For endInvocationInterlock(), we need to insert a memory fence which
5235 * stalls in the shader until the memory transactions prior to that
5236 * fence are complete. This ensures that the shader does not end before
5237 * any writes from its critical section have landed. Otherwise, you can
5238 * end up with a case where the next invocation on that pixel properly
5239 * stalls for previous FS invocation on its pixel to complete but
5240 * doesn't actually wait for the dataport memory transactions from that
5241 * thread to land before submitting its own.
5243 const fs_builder ubld
= bld
.group(8, 0);
5244 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5245 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5246 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5247 ->size_written
= 2 * REG_SIZE
;
5252 unreachable("unknown intrinsic");
5257 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5258 int op
, nir_intrinsic_instr
*instr
)
5260 if (stage
== MESA_SHADER_FRAGMENT
)
5261 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5263 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5264 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5265 * appear to exist. However, if you look at Vol 2a, there are no message
5266 * descriptors provided for Qword atomic ops except for A64 messages.
5268 assert(nir_dest_bit_size(instr
->dest
) == 32);
5271 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5272 dest
= get_nir_dest(instr
->dest
);
5274 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5275 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5276 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5277 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5278 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5281 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5282 data
= get_nir_src(instr
->src
[2]);
5284 if (op
== BRW_AOP_CMPWR
) {
5285 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5286 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5287 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5290 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5292 /* Emit the actual atomic operation */
5294 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5295 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5299 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5300 int op
, nir_intrinsic_instr
*instr
)
5302 if (stage
== MESA_SHADER_FRAGMENT
)
5303 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5306 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5307 dest
= get_nir_dest(instr
->dest
);
5309 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5310 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5311 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5312 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5313 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5315 fs_reg data
= get_nir_src(instr
->src
[2]);
5316 if (op
== BRW_AOP_FCMPWR
) {
5317 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5318 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5319 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5322 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5324 /* Emit the actual atomic operation */
5326 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5327 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5331 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5332 int op
, nir_intrinsic_instr
*instr
)
5335 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5336 dest
= get_nir_dest(instr
->dest
);
5338 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5339 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5340 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5341 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5344 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5345 data
= get_nir_src(instr
->src
[1]);
5346 if (op
== BRW_AOP_CMPWR
) {
5347 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5348 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5349 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5352 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5354 /* Get the offset */
5355 if (nir_src_is_const(instr
->src
[0])) {
5356 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5357 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5359 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5360 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5361 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5362 brw_imm_ud(instr
->const_index
[0]));
5365 /* Emit the actual atomic operation operation */
5367 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5368 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5372 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5373 int op
, nir_intrinsic_instr
*instr
)
5376 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5377 dest
= get_nir_dest(instr
->dest
);
5379 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5380 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5381 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5382 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5384 fs_reg data
= get_nir_src(instr
->src
[1]);
5385 if (op
== BRW_AOP_FCMPWR
) {
5386 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5387 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5388 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5391 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5393 /* Get the offset */
5394 if (nir_src_is_const(instr
->src
[0])) {
5395 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5396 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5398 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5399 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5400 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5401 brw_imm_ud(instr
->const_index
[0]));
5404 /* Emit the actual atomic operation operation */
5406 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5407 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5411 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5412 int op
, nir_intrinsic_instr
*instr
)
5414 if (stage
== MESA_SHADER_FRAGMENT
)
5415 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5418 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5419 dest
= get_nir_dest(instr
->dest
);
5421 fs_reg addr
= get_nir_src(instr
->src
[0]);
5424 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5425 data
= get_nir_src(instr
->src
[1]);
5427 if (op
== BRW_AOP_CMPWR
) {
5428 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5429 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5430 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5434 if (nir_dest_bit_size(instr
->dest
) == 64) {
5435 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5436 dest
, addr
, data
, brw_imm_ud(op
));
5438 assert(nir_dest_bit_size(instr
->dest
) == 32);
5439 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5440 dest
, addr
, data
, brw_imm_ud(op
));
5445 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5446 int op
, nir_intrinsic_instr
*instr
)
5448 if (stage
== MESA_SHADER_FRAGMENT
)
5449 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5451 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5452 fs_reg dest
= get_nir_dest(instr
->dest
);
5454 fs_reg addr
= get_nir_src(instr
->src
[0]);
5456 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5457 fs_reg data
= get_nir_src(instr
->src
[1]);
5459 if (op
== BRW_AOP_FCMPWR
) {
5460 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5461 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5462 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5466 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5467 dest
, addr
, data
, brw_imm_ud(op
));
5471 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5473 unsigned texture
= instr
->texture_index
;
5474 unsigned sampler
= instr
->sampler_index
;
5476 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5478 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5479 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5481 int lod_components
= 0;
5483 /* The hardware requires a LOD for buffer textures */
5484 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5485 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5487 uint32_t header_bits
= 0;
5488 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5489 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5490 switch (instr
->src
[i
].src_type
) {
5491 case nir_tex_src_bias
:
5492 srcs
[TEX_LOGICAL_SRC_LOD
] =
5493 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5495 case nir_tex_src_comparator
:
5496 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5498 case nir_tex_src_coord
:
5499 switch (instr
->op
) {
5501 case nir_texop_txf_ms
:
5502 case nir_texop_txf_ms_mcs
:
5503 case nir_texop_samples_identical
:
5504 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5507 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5511 case nir_tex_src_ddx
:
5512 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5513 lod_components
= nir_tex_instr_src_size(instr
, i
);
5515 case nir_tex_src_ddy
:
5516 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5518 case nir_tex_src_lod
:
5519 switch (instr
->op
) {
5521 srcs
[TEX_LOGICAL_SRC_LOD
] =
5522 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5525 srcs
[TEX_LOGICAL_SRC_LOD
] =
5526 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5529 srcs
[TEX_LOGICAL_SRC_LOD
] =
5530 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5534 case nir_tex_src_min_lod
:
5535 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5536 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5538 case nir_tex_src_ms_index
:
5539 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5542 case nir_tex_src_offset
: {
5543 uint32_t offset_bits
= 0;
5544 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5545 header_bits
|= offset_bits
;
5547 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5548 retype(src
, BRW_REGISTER_TYPE_D
);
5553 case nir_tex_src_projector
:
5554 unreachable("should be lowered");
5556 case nir_tex_src_texture_offset
: {
5557 /* Emit code to evaluate the actual indexing expression */
5558 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5559 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5560 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5564 case nir_tex_src_sampler_offset
: {
5565 /* Emit code to evaluate the actual indexing expression */
5566 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5567 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5568 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5572 case nir_tex_src_texture_handle
:
5573 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5574 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5575 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5578 case nir_tex_src_sampler_handle
:
5579 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5580 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5581 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5584 case nir_tex_src_ms_mcs
:
5585 assert(instr
->op
== nir_texop_txf_ms
);
5586 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5589 case nir_tex_src_plane
: {
5590 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5591 const uint32_t texture_index
=
5592 instr
->texture_index
+
5593 stage_prog_data
->binding_table
.plane_start
[plane
] -
5594 stage_prog_data
->binding_table
.texture_start
;
5596 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5601 unreachable("unknown texture source");
5605 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5606 (instr
->op
== nir_texop_txf_ms
||
5607 instr
->op
== nir_texop_samples_identical
)) {
5608 if (devinfo
->gen
>= 7 &&
5609 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5610 srcs
[TEX_LOGICAL_SRC_MCS
] =
5611 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5612 instr
->coord_components
,
5613 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5614 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5616 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5620 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5621 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5624 switch (instr
->op
) {
5626 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5629 opcode
= FS_OPCODE_TXB_LOGICAL
;
5632 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5635 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5638 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5640 case nir_texop_txf_ms
:
5641 if ((key_tex
->msaa_16
& (1 << sampler
)))
5642 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5644 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5646 case nir_texop_txf_ms_mcs
:
5647 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5649 case nir_texop_query_levels
:
5651 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5654 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5657 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5658 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5660 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5662 case nir_texop_texture_samples
:
5663 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5665 case nir_texop_samples_identical
: {
5666 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5668 /* If mcs is an immediate value, it means there is no MCS. In that case
5669 * just return false.
5671 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5672 bld
.MOV(dst
, brw_imm_ud(0u));
5673 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5674 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5675 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5676 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5677 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5679 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5680 BRW_CONDITIONAL_EQ
);
5685 unreachable("unknown texture opcode");
5688 if (instr
->op
== nir_texop_tg4
) {
5689 if (instr
->component
== 1 &&
5690 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5691 /* gather4 sampler is broken for green channel on RG32F --
5692 * we must ask for blue instead.
5694 header_bits
|= 2 << 16;
5696 header_bits
|= instr
->component
<< 16;
5700 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5701 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5702 inst
->offset
= header_bits
;
5704 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5705 if (devinfo
->gen
>= 9 &&
5706 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5707 unsigned write_mask
= instr
->dest
.is_ssa
?
5708 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5709 (1 << dest_size
) - 1;
5710 assert(write_mask
!= 0); /* dead code should have been eliminated */
5711 inst
->size_written
= util_last_bit(write_mask
) *
5712 inst
->dst
.component_size(inst
->exec_size
);
5714 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5717 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5718 inst
->shadow_compare
= true;
5720 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5721 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5724 for (unsigned i
= 0; i
< dest_size
; i
++)
5725 nir_dest
[i
] = offset(dst
, bld
, i
);
5727 if (instr
->op
== nir_texop_query_levels
) {
5728 /* # levels is in .w */
5729 nir_dest
[0] = offset(dst
, bld
, 3);
5730 } else if (instr
->op
== nir_texop_txs
&&
5731 dest_size
>= 3 && devinfo
->gen
< 7) {
5732 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5733 fs_reg depth
= offset(dst
, bld
, 2);
5734 nir_dest
[2] = vgrf(glsl_type::int_type
);
5735 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5738 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5742 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5744 switch (instr
->type
) {
5745 case nir_jump_break
:
5746 bld
.emit(BRW_OPCODE_BREAK
);
5748 case nir_jump_continue
:
5749 bld
.emit(BRW_OPCODE_CONTINUE
);
5751 case nir_jump_return
:
5753 unreachable("unknown jump");
5758 * This helper takes a source register and un/shuffles it into the destination
5761 * If source type size is smaller than destination type size the operation
5762 * needed is a component shuffle. The opposite case would be an unshuffle. If
5763 * source/destination type size is equal a shuffle is done that would be
5764 * equivalent to a simple MOV.
5766 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5767 * components .xyz 16-bit vector on SIMD8 would be.
5769 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5770 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5772 * This helper will return the following 2 32-bit components with the 16-bit
5775 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5776 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5778 * For unshuffle, the example would be the opposite, a 64-bit type source
5779 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5782 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5783 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5784 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5785 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5787 * The returned result would be the following 4 32-bit components unshuffled:
5789 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5790 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5791 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5792 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5794 * - Source and destination register must not be overlapped.
5795 * - components units are measured in terms of the smaller type between
5796 * source and destination because we are un/shuffling the smaller
5797 * components from/into the bigger ones.
5798 * - first_component parameter allows skipping source components.
5801 shuffle_src_to_dst(const fs_builder
&bld
,
5804 uint32_t first_component
,
5805 uint32_t components
)
5807 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5808 assert(!regions_overlap(dst
,
5809 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5810 offset(src
, bld
, first_component
),
5811 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5812 for (unsigned i
= 0; i
< components
; i
++) {
5813 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5814 offset(src
, bld
, i
+ first_component
));
5816 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5817 /* Source is shuffled into destination */
5818 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5819 assert(!regions_overlap(dst
,
5820 type_sz(dst
.type
) * bld
.dispatch_width() *
5821 DIV_ROUND_UP(components
, size_ratio
),
5822 offset(src
, bld
, first_component
),
5823 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5825 brw_reg_type shuffle_type
=
5826 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5827 BRW_REGISTER_TYPE_D
);
5828 for (unsigned i
= 0; i
< components
; i
++) {
5829 fs_reg shuffle_component_i
=
5830 subscript(offset(dst
, bld
, i
/ size_ratio
),
5831 shuffle_type
, i
% size_ratio
);
5832 bld
.MOV(shuffle_component_i
,
5833 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5836 /* Source is unshuffled into destination */
5837 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5838 assert(!regions_overlap(dst
,
5839 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5840 offset(src
, bld
, first_component
/ size_ratio
),
5841 type_sz(src
.type
) * bld
.dispatch_width() *
5842 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5845 brw_reg_type shuffle_type
=
5846 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5847 BRW_REGISTER_TYPE_D
);
5848 for (unsigned i
= 0; i
< components
; i
++) {
5849 fs_reg shuffle_component_i
=
5850 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5851 shuffle_type
, (first_component
+ i
) % size_ratio
);
5852 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5853 shuffle_component_i
);
5859 shuffle_from_32bit_read(const fs_builder
&bld
,
5862 uint32_t first_component
,
5863 uint32_t components
)
5865 assert(type_sz(src
.type
) == 4);
5867 /* This function takes components in units of the destination type while
5868 * shuffle_src_to_dst takes components in units of the smallest type
5870 if (type_sz(dst
.type
) > 4) {
5871 assert(type_sz(dst
.type
) == 8);
5872 first_component
*= 2;
5876 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5880 setup_imm_df(const fs_builder
&bld
, double v
)
5882 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5883 assert(devinfo
->gen
>= 7);
5885 if (devinfo
->gen
>= 8)
5886 return brw_imm_df(v
);
5888 /* gen7.5 does not support DF immediates straighforward but the DIM
5889 * instruction allows to set the 64-bit immediate value.
5891 if (devinfo
->is_haswell
) {
5892 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5893 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5894 ubld
.DIM(dst
, brw_imm_df(v
));
5895 return component(dst
, 0);
5898 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5899 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5900 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5902 * Alternatively, we could also produce a normal VGRF (without stride 0)
5903 * by writing to all the channels in the VGRF, however, that would hit the
5904 * gen7 bug where we have to split writes that span more than 1 register
5905 * into instructions with a width of 4 (otherwise the write to the second
5906 * register written runs into an execmask hardware bug) which isn't very
5919 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5920 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5921 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5922 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5924 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5928 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5930 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5931 bld
.MOV(tmp
, brw_imm_w(v
));
5936 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5938 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5939 bld
.MOV(tmp
, brw_imm_uw(v
));