2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
46 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
50 fs_visitor::nir_setup_outputs()
52 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
55 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
57 /* Calculate the size of output registers in a separate pass, before
58 * allocating them. With ARB_enhanced_layouts, multiple output variables
59 * may occupy the same slot, but have different type sizes.
61 nir_foreach_variable(var
, &nir
->outputs
) {
62 const int loc
= var
->data
.driver_location
;
63 const unsigned var_vec4s
=
64 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
65 : type_size_vec4(var
->type
, true);
66 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
69 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
70 if (vec4s
[loc
] == 0) {
75 unsigned reg_size
= vec4s
[loc
];
77 /* Check if there are any ranges that start within this range and extend
78 * past it. If so, include them in this allocation.
80 for (unsigned i
= 1; i
< reg_size
; i
++)
81 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
83 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
84 for (unsigned i
= 0; i
< reg_size
; i
++)
85 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
92 fs_visitor::nir_setup_uniforms()
94 /* Only the first compile gets to set up uniforms. */
95 if (push_constant_loc
) {
96 assert(pull_constant_loc
);
100 uniforms
= nir
->num_uniforms
/ 4;
102 if (stage
== MESA_SHADER_COMPUTE
) {
103 /* Add a uniform for the thread local id. It must be the last uniform
106 assert(uniforms
== prog_data
->nr_params
);
107 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
108 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
109 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
114 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
118 nir_foreach_instr(instr
, block
) {
119 if (instr
->type
!= nir_instr_type_intrinsic
)
122 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
123 switch (intrin
->intrinsic
) {
124 case nir_intrinsic_load_vertex_id
:
125 case nir_intrinsic_load_base_vertex
:
126 unreachable("should be lowered by nir_lower_system_values().");
128 case nir_intrinsic_load_vertex_id_zero_base
:
129 case nir_intrinsic_load_is_indexed_draw
:
130 case nir_intrinsic_load_first_vertex
:
131 case nir_intrinsic_load_instance_id
:
132 case nir_intrinsic_load_base_instance
:
133 case nir_intrinsic_load_draw_id
:
134 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
136 case nir_intrinsic_load_invocation_id
:
137 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
139 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
141 if (reg
->file
== BAD_FILE
) {
142 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
143 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
144 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
145 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
150 case nir_intrinsic_load_sample_pos
:
151 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
152 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
153 if (reg
->file
== BAD_FILE
)
154 *reg
= *v
->emit_samplepos_setup();
157 case nir_intrinsic_load_sample_id
:
158 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
159 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
160 if (reg
->file
== BAD_FILE
)
161 *reg
= *v
->emit_sampleid_setup();
164 case nir_intrinsic_load_sample_mask_in
:
165 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
166 assert(v
->devinfo
->gen
>= 7);
167 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
168 if (reg
->file
== BAD_FILE
)
169 *reg
= *v
->emit_samplemaskin_setup();
172 case nir_intrinsic_load_work_group_id
:
173 assert(v
->stage
== MESA_SHADER_COMPUTE
);
174 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
175 if (reg
->file
== BAD_FILE
)
176 *reg
= *v
->emit_cs_work_group_id_setup();
179 case nir_intrinsic_load_helper_invocation
:
180 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
182 if (reg
->file
== BAD_FILE
) {
183 const fs_builder abld
=
184 v
->bld
.annotate("gl_HelperInvocation", NULL
);
186 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
187 * pixel mask is in g1.7 of the thread payload.
189 * We move the per-channel pixel enable bit to the low bit of each
190 * channel by shifting the byte containing the pixel mask by the
191 * vector immediate 0x76543210UV.
193 * The region of <1,8,0> reads only 1 byte (the pixel masks for
194 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
195 * masks for 2 and 3) in SIMD16.
197 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
199 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
200 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
201 hbld
.SHR(offset(shifted
, hbld
, i
),
202 stride(retype(brw_vec1_grf(1 + i
, 7),
203 BRW_REGISTER_TYPE_UB
),
205 brw_imm_v(0x76543210));
208 /* A set bit in the pixel mask means the channel is enabled, but
209 * that is the opposite of gl_HelperInvocation so we need to invert
212 * The negate source-modifier bit of logical instructions on Gen8+
213 * performs 1's complement negation, so we can use that instead of
216 fs_reg inverted
= negate(shifted
);
217 if (v
->devinfo
->gen
< 8) {
218 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
219 abld
.NOT(inverted
, shifted
);
222 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
223 * with 1 and negating.
225 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
226 abld
.AND(anded
, inverted
, brw_imm_uw(1));
228 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
229 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
243 fs_visitor::nir_emit_system_values()
245 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
246 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
247 nir_system_values
[i
] = fs_reg();
250 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
251 * never end up using it.
254 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
255 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
256 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
258 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
259 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
260 if (dispatch_width
> 8)
261 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
262 if (dispatch_width
> 16) {
263 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
264 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
268 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
269 nir_foreach_block(block
, impl
)
270 emit_system_values_block(block
, this);
274 * Returns a type based on a reference_type (word, float, half-float) and a
277 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
279 * @FIXME: 64-bit return types are always DF on integer types to maintain
280 * compability with uses of DF previously to the introduction of int64
284 brw_reg_type_from_bit_size(const unsigned bit_size
,
285 const brw_reg_type reference_type
)
287 switch(reference_type
) {
288 case BRW_REGISTER_TYPE_HF
:
289 case BRW_REGISTER_TYPE_F
:
290 case BRW_REGISTER_TYPE_DF
:
293 return BRW_REGISTER_TYPE_HF
;
295 return BRW_REGISTER_TYPE_F
;
297 return BRW_REGISTER_TYPE_DF
;
299 unreachable("Invalid bit size");
301 case BRW_REGISTER_TYPE_B
:
302 case BRW_REGISTER_TYPE_W
:
303 case BRW_REGISTER_TYPE_D
:
304 case BRW_REGISTER_TYPE_Q
:
307 return BRW_REGISTER_TYPE_B
;
309 return BRW_REGISTER_TYPE_W
;
311 return BRW_REGISTER_TYPE_D
;
313 return BRW_REGISTER_TYPE_Q
;
315 unreachable("Invalid bit size");
317 case BRW_REGISTER_TYPE_UB
:
318 case BRW_REGISTER_TYPE_UW
:
319 case BRW_REGISTER_TYPE_UD
:
320 case BRW_REGISTER_TYPE_UQ
:
323 return BRW_REGISTER_TYPE_UB
;
325 return BRW_REGISTER_TYPE_UW
;
327 return BRW_REGISTER_TYPE_UD
;
329 return BRW_REGISTER_TYPE_UQ
;
331 unreachable("Invalid bit size");
334 unreachable("Unknown type");
339 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
341 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
342 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
343 nir_locals
[i
] = fs_reg();
346 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
347 unsigned array_elems
=
348 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
349 unsigned size
= array_elems
* reg
->num_components
;
350 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
351 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
352 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
355 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
358 nir_emit_cf_list(&impl
->body
);
362 fs_visitor::nir_emit_cf_list(exec_list
*list
)
364 exec_list_validate(list
);
365 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
366 switch (node
->type
) {
368 nir_emit_if(nir_cf_node_as_if(node
));
371 case nir_cf_node_loop
:
372 nir_emit_loop(nir_cf_node_as_loop(node
));
375 case nir_cf_node_block
:
376 nir_emit_block(nir_cf_node_as_block(node
));
380 unreachable("Invalid CFG node block");
386 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
391 /* If the condition has the form !other_condition, use other_condition as
392 * the source, but invert the predicate on the if instruction.
394 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
395 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
396 assert(!cond
->src
[0].negate
);
397 assert(!cond
->src
[0].abs
);
400 cond_reg
= get_nir_src(cond
->src
[0].src
);
403 cond_reg
= get_nir_src(if_stmt
->condition
);
406 /* first, put the condition into f0 */
407 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
408 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
411 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
413 nir_emit_cf_list(&if_stmt
->then_list
);
415 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
416 bld
.emit(BRW_OPCODE_ELSE
);
417 nir_emit_cf_list(&if_stmt
->else_list
);
420 bld
.emit(BRW_OPCODE_ENDIF
);
422 if (devinfo
->gen
< 7)
423 limit_dispatch_width(16, "Non-uniform control flow unsupported "
428 fs_visitor::nir_emit_loop(nir_loop
*loop
)
430 bld
.emit(BRW_OPCODE_DO
);
432 nir_emit_cf_list(&loop
->body
);
434 bld
.emit(BRW_OPCODE_WHILE
);
436 if (devinfo
->gen
< 7)
437 limit_dispatch_width(16, "Non-uniform control flow unsupported "
442 fs_visitor::nir_emit_block(nir_block
*block
)
444 nir_foreach_instr(instr
, block
) {
445 nir_emit_instr(instr
);
450 fs_visitor::nir_emit_instr(nir_instr
*instr
)
452 const fs_builder abld
= bld
.annotate(NULL
, instr
);
454 switch (instr
->type
) {
455 case nir_instr_type_alu
:
456 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
459 case nir_instr_type_deref
:
460 unreachable("All derefs should've been lowered");
463 case nir_instr_type_intrinsic
:
465 case MESA_SHADER_VERTEX
:
466 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_TESS_CTRL
:
469 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_TESS_EVAL
:
472 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_GEOMETRY
:
475 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
477 case MESA_SHADER_FRAGMENT
:
478 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 case MESA_SHADER_COMPUTE
:
481 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
484 unreachable("unsupported shader stage");
488 case nir_instr_type_tex
:
489 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
492 case nir_instr_type_load_const
:
493 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
496 case nir_instr_type_ssa_undef
:
497 /* We create a new VGRF for undefs on every use (by handling
498 * them in get_nir_src()), rather than for each definition.
499 * This helps register coalescing eliminate MOVs from undef.
503 case nir_instr_type_jump
:
504 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
508 unreachable("unknown instruction type");
513 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
517 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
518 const fs_reg
&result
)
520 if (!instr
->src
[0].src
.is_ssa
||
521 !instr
->src
[0].src
.ssa
->parent_instr
)
524 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
527 nir_alu_instr
*src0
=
528 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
530 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
531 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
534 /* If either opcode has source modifiers, bail.
536 * TODO: We can potentially handle source modifiers if both of the opcodes
537 * we're combining are signed integers.
539 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
540 src0
->src
[0].abs
|| src0
->src
[0].negate
)
543 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
545 /* Element type to extract.*/
546 const brw_reg_type type
= brw_int_type(
547 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
548 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
550 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
551 op0
.type
= brw_type_for_nir_type(devinfo
,
552 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
553 nir_src_bit_size(src0
->src
[0].src
)));
554 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
556 set_saturate(instr
->dest
.saturate
,
557 bld
.MOV(result
, subscript(op0
, type
, element
)));
562 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
563 const fs_reg
&result
)
565 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
566 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
569 if (!nir_src_is_const(instr
->src
[1].src
) ||
570 !nir_src_is_const(instr
->src
[2].src
))
573 const float value1
= nir_src_as_float(instr
->src
[1].src
);
574 const float value2
= nir_src_as_float(instr
->src
[2].src
);
575 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
578 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
579 assert(value1
== -value2
);
581 fs_reg tmp
= vgrf(glsl_type::int_type
);
583 if (devinfo
->gen
>= 6) {
584 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
585 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
587 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
589 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
590 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
592 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
594 * This negation looks like it's safe in practice, because bits 0:4 will
595 * surely be TRIANGLES
598 if (value1
== -1.0f
) {
602 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
603 g0
, brw_imm_uw(0x3f80));
605 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
606 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
608 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
610 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
611 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
613 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
615 * This negation looks like it's safe in practice, because bits 0:4 will
616 * surely be TRIANGLES
619 if (value1
== -1.0f
) {
623 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
625 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
631 emit_find_msb_using_lzd(const fs_builder
&bld
,
632 const fs_reg
&result
,
640 /* LZD of an absolute value source almost always does the right
641 * thing. There are two problem values:
643 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
644 * 0. However, findMSB(int(0x80000000)) == 30.
646 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
647 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
649 * For a value of zero or negative one, -1 will be returned.
651 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
652 * findMSB(-(1<<x)) should return x-1.
654 * For all negative number cases, including 0x80000000 and
655 * 0xffffffff, the correct value is obtained from LZD if instead of
656 * negating the (already negative) value the logical-not is used. A
657 * conditonal logical-not can be achieved in two instructions.
659 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
661 bld
.ASR(temp
, src
, brw_imm_d(31));
662 bld
.XOR(temp
, temp
, src
);
665 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
666 retype(temp
, BRW_REGISTER_TYPE_UD
));
668 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
669 * from the LSB side. Subtract the result from 31 to convert the MSB
670 * count into an LSB count. If no bits are set, LZD will return 32.
671 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
673 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
674 inst
->src
[0].negate
= true;
678 brw_rnd_mode_from_nir_op (const nir_op op
) {
680 case nir_op_f2f16_rtz
:
681 return BRW_RND_MODE_RTZ
;
682 case nir_op_f2f16_rtne
:
683 return BRW_RND_MODE_RTNE
;
685 unreachable("Operation doesn't support rounding mode");
690 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
691 nir_alu_instr
*instr
,
696 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
698 result
.type
= brw_type_for_nir_type(devinfo
,
699 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
700 nir_dest_bit_size(instr
->dest
.dest
)));
702 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
703 op
[i
] = get_nir_src(instr
->src
[i
].src
);
704 op
[i
].type
= brw_type_for_nir_type(devinfo
,
705 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
706 nir_src_bit_size(instr
->src
[i
].src
)));
707 op
[i
].abs
= instr
->src
[i
].abs
;
708 op
[i
].negate
= instr
->src
[i
].negate
;
711 /* Move and vecN instrutions may still be vectored. Return the raw,
712 * vectored source and destination so that fs_visitor::nir_emit_alu can
713 * handle it. Other callers should not have to handle these kinds of
726 /* At this point, we have dealt with any instruction that operates on
727 * more than a single channel. Therefore, we can just adjust the source
728 * and destination registers for that channel and emit the instruction.
730 unsigned channel
= 0;
731 if (nir_op_infos
[instr
->op
].output_size
== 0) {
732 /* Since NIR is doing the scalarizing for us, we should only ever see
733 * vectorized operations with a single channel.
735 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
736 channel
= ffs(instr
->dest
.write_mask
) - 1;
738 result
= offset(result
, bld
, channel
);
741 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
742 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
743 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
750 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
753 for (unsigned i
= 0; i
< 2; i
++) {
754 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
756 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
757 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
758 /* The source of the inot is now the source of instr. */
759 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
761 assert(!op
[i
].negate
);
764 op
[i
] = resolve_source_modifiers(op
[i
]);
770 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
772 nir_alu_instr
*instr
)
774 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
777 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
779 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
782 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
783 * of valid size-changing combinations is a bit more complex.
785 * The source restriction is just because I was lazy about generating the
788 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
789 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
792 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
793 * this is float(1 + a).
797 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
799 /* Ignore the saturate modifier, if there is one. The result of the
800 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
802 bld
.ADD(result
, op
, brw_imm_d(1));
808 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
810 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
811 * the source of \c instr that is a \c nir_op_fsign.
814 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
815 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
819 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
820 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
822 if (instr
->op
!= nir_op_fsign
) {
823 const nir_alu_instr
*const fsign_instr
=
824 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
826 assert(!fsign_instr
->dest
.saturate
);
828 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
829 * fsign_src] has the other multiply source. This must be rearranged so
830 * that op[0] is the source of the fsign op[1] is the other multiply
836 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
838 const nir_alu_type t
=
839 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
840 nir_src_bit_size(fsign_instr
->src
[0].src
));
842 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
843 op
[0].abs
= fsign_instr
->src
[0].abs
;
844 op
[0].negate
= fsign_instr
->src
[0].negate
;
846 unsigned channel
= 0;
847 if (nir_op_infos
[instr
->op
].output_size
== 0) {
848 /* Since NIR is doing the scalarizing for us, we should only ever see
849 * vectorized operations with a single channel.
851 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
852 channel
= ffs(instr
->dest
.write_mask
) - 1;
855 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
857 assert(!instr
->dest
.saturate
);
861 /* Straightforward since the source can be assumed to be either strictly
862 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
864 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
866 if (instr
->op
== nir_op_fsign
) {
867 inst
= (op
[0].negate
)
868 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
869 : bld
.MOV(result
, brw_imm_f(1.0f
));
871 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
872 inst
= bld
.MOV(result
, op
[1]);
875 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
876 } else if (type_sz(op
[0].type
) == 2) {
877 /* AND(val, 0x8000) gives the sign bit.
879 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
881 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
882 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
884 op
[0].type
= BRW_REGISTER_TYPE_UW
;
885 result
.type
= BRW_REGISTER_TYPE_UW
;
886 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
888 if (instr
->op
== nir_op_fsign
)
889 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
891 /* Use XOR here to get the result sign correct. */
892 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
895 inst
->predicate
= BRW_PREDICATE_NORMAL
;
896 } else if (type_sz(op
[0].type
) == 4) {
897 /* AND(val, 0x80000000) gives the sign bit.
899 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
902 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
904 op
[0].type
= BRW_REGISTER_TYPE_UD
;
905 result
.type
= BRW_REGISTER_TYPE_UD
;
906 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
908 if (instr
->op
== nir_op_fsign
)
909 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
911 /* Use XOR here to get the result sign correct. */
912 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
915 inst
->predicate
= BRW_PREDICATE_NORMAL
;
917 /* For doubles we do the same but we need to consider:
919 * - 2-src instructions can't operate with 64-bit immediates
920 * - The sign is encoded in the high 32-bit of each DF
921 * - We need to produce a DF result.
924 fs_reg zero
= vgrf(glsl_type::double_type
);
925 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
926 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
928 bld
.MOV(result
, zero
);
930 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
931 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
932 brw_imm_ud(0x80000000u
));
934 if (instr
->op
== nir_op_fsign
) {
935 set_predicate(BRW_PREDICATE_NORMAL
,
936 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
938 /* This could be done better in some cases. If the scale is an
939 * immediate with the low 32-bits all 0, emitting a separate XOR and
940 * OR would allow an algebraic optimization to remove the OR. There
941 * are currently zero instances of fsign(double(x))*IMM in shader-db
942 * or any test suite, so it is hard to care at this time.
944 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
945 inst
= bld
.XOR(result_int64
, result_int64
,
946 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
952 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
954 * Checks the operands of a \c nir_op_fmul to determine whether or not
955 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
957 * \param instr The multiplication instruction
959 * \param fsign_src The source of \c instr that may or may not be a
963 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
965 assert(instr
->op
== nir_op_fmul
);
967 nir_alu_instr
*const fsign_instr
=
968 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
972 * 1. instr->src[fsign_src] must be a nir_op_fsign.
973 * 2. The nir_op_fsign can only be used by this multiplication.
974 * 3. The source that is the nir_op_fsign does not have source modifiers.
975 * \c emit_fsign only examines the source modifiers of the source of the
978 * The nir_op_fsign must also not have the saturate modifier, but steps
979 * have already been taken (in nir_opt_algebraic) to ensure that.
981 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
982 is_used_once(fsign_instr
) &&
983 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
987 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
990 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
994 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1001 fs_reg temp
= result
;
1002 bool need_extra_copy
= false;
1003 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1004 if (!instr
->src
[i
].src
.is_ssa
&&
1005 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1006 need_extra_copy
= true;
1007 temp
= bld
.vgrf(result
.type
, 4);
1012 for (unsigned i
= 0; i
< 4; i
++) {
1013 if (!(instr
->dest
.write_mask
& (1 << i
)))
1016 if (instr
->op
== nir_op_mov
) {
1017 inst
= bld
.MOV(offset(temp
, bld
, i
),
1018 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1020 inst
= bld
.MOV(offset(temp
, bld
, i
),
1021 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1023 inst
->saturate
= instr
->dest
.saturate
;
1026 /* In this case the source and destination registers were the same,
1027 * so we need to insert an extra set of moves in order to deal with
1030 if (need_extra_copy
) {
1031 for (unsigned i
= 0; i
< 4; i
++) {
1032 if (!(instr
->dest
.write_mask
& (1 << i
)))
1035 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1043 if (optimize_extract_to_float(instr
, result
))
1045 inst
= bld
.MOV(result
, op
[0]);
1046 inst
->saturate
= instr
->dest
.saturate
;
1049 case nir_op_f2f16_rtne
:
1050 case nir_op_f2f16_rtz
:
1051 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1052 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1055 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1056 * on the HW gen, it is a special hw opcode or just a MOV, and
1057 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1059 * But if we want to use that opcode, we need to provide support on
1060 * different optimizations and lowerings. As right now HF support is
1061 * only for gen8+, it will be better to use directly the MOV, and use
1062 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1064 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1065 inst
= bld
.MOV(result
, op
[0]);
1066 inst
->saturate
= instr
->dest
.saturate
;
1076 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1078 op
[0].type
= BRW_REGISTER_TYPE_D
;
1079 op
[0].negate
= !op
[0].negate
;
1103 if (result
.type
== BRW_REGISTER_TYPE_B
||
1104 result
.type
== BRW_REGISTER_TYPE_UB
||
1105 result
.type
== BRW_REGISTER_TYPE_HF
)
1106 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1108 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1109 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1110 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1111 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1113 inst
= bld
.MOV(result
, op
[0]);
1114 inst
->saturate
= instr
->dest
.saturate
;
1118 inst
= bld
.MOV(result
, op
[0]);
1119 inst
->saturate
= true;
1124 op
[0].negate
= true;
1125 inst
= bld
.MOV(result
, op
[0]);
1126 if (instr
->op
== nir_op_fneg
)
1127 inst
->saturate
= instr
->dest
.saturate
;
1132 op
[0].negate
= false;
1134 inst
= bld
.MOV(result
, op
[0]);
1135 if (instr
->op
== nir_op_fabs
)
1136 inst
->saturate
= instr
->dest
.saturate
;
1140 emit_fsign(bld
, instr
, result
, op
, 0);
1144 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1145 inst
->saturate
= instr
->dest
.saturate
;
1149 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1150 inst
->saturate
= instr
->dest
.saturate
;
1154 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1155 inst
->saturate
= instr
->dest
.saturate
;
1159 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1160 inst
->saturate
= instr
->dest
.saturate
;
1164 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1165 inst
->saturate
= instr
->dest
.saturate
;
1169 if (fs_key
->high_quality_derivatives
) {
1170 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1172 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1174 inst
->saturate
= instr
->dest
.saturate
;
1176 case nir_op_fddx_fine
:
1177 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1178 inst
->saturate
= instr
->dest
.saturate
;
1180 case nir_op_fddx_coarse
:
1181 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1182 inst
->saturate
= instr
->dest
.saturate
;
1185 if (fs_key
->high_quality_derivatives
) {
1186 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1188 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1190 inst
->saturate
= instr
->dest
.saturate
;
1192 case nir_op_fddy_fine
:
1193 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1194 inst
->saturate
= instr
->dest
.saturate
;
1196 case nir_op_fddy_coarse
:
1197 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1198 inst
->saturate
= instr
->dest
.saturate
;
1203 inst
= bld
.ADD(result
, op
[0], op
[1]);
1204 inst
->saturate
= instr
->dest
.saturate
;
1207 case nir_op_uadd_sat
:
1208 inst
= bld
.ADD(result
, op
[0], op
[1]);
1209 inst
->saturate
= true;
1213 for (unsigned i
= 0; i
< 2; i
++) {
1214 if (can_fuse_fmul_fsign(instr
, i
)) {
1215 emit_fsign(bld
, instr
, result
, op
, i
);
1220 inst
= bld
.MUL(result
, op
[0], op
[1]);
1221 inst
->saturate
= instr
->dest
.saturate
;
1224 case nir_op_imul_2x32_64
:
1225 case nir_op_umul_2x32_64
:
1226 bld
.MUL(result
, op
[0], op
[1]);
1230 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1231 bld
.MUL(result
, op
[0], op
[1]);
1234 case nir_op_imul_high
:
1235 case nir_op_umul_high
:
1236 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1237 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1242 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1243 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1246 case nir_op_uadd_carry
:
1247 unreachable("Should have been lowered by carry_to_arith().");
1249 case nir_op_usub_borrow
:
1250 unreachable("Should have been lowered by borrow_to_arith().");
1254 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1255 * appears that our hardware just does the right thing for signed
1258 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1259 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1263 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1264 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1266 /* Math instructions don't support conditional mod */
1267 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1268 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1270 /* Now, we need to determine if signs of the sources are different.
1271 * When we XOR the sources, the top bit is 0 if they are the same and 1
1272 * if they are different. We can then use a conditional modifier to
1273 * turn that into a predicate. This leads us to an XOR.l instruction.
1275 * Technically, according to the PRM, you're not allowed to use .l on a
1276 * XOR instruction. However, emperical experiments and Curro's reading
1277 * of the simulator source both indicate that it's safe.
1279 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1280 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1281 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1282 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1284 /* If the result of the initial remainder operation is non-zero and the
1285 * two sources have different signs, add in a copy of op[1] to get the
1286 * final integer modulus value.
1288 inst
= bld
.ADD(result
, result
, op
[1]);
1289 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1296 case nir_op_fne32
: {
1297 fs_reg dest
= result
;
1299 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1301 dest
= bld
.vgrf(op
[0].type
, 1);
1303 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1305 if (bit_size
> 32) {
1306 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1307 } else if(bit_size
< 32) {
1308 /* When we convert the result to 32-bit we need to be careful and do
1309 * it as a signed conversion to get sign extension (for 32-bit true)
1311 const brw_reg_type src_type
=
1312 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1314 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1324 case nir_op_ine32
: {
1325 fs_reg dest
= result
;
1327 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1328 * type. So we convert both operands for the comparison.
1331 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1332 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1334 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1336 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1338 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1339 brw_cmod_for_nir_comparison(instr
->op
));
1341 if (bit_size
> 32) {
1342 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1343 } else if (bit_size
< 32) {
1344 /* When we convert the result to 32-bit we need to be careful and do
1345 * it as a signed conversion to get sign extension (for 32-bit true)
1347 const brw_reg_type src_type
=
1348 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1350 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1356 if (devinfo
->gen
>= 8) {
1357 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1359 if (inot_src_instr
!= NULL
&&
1360 (inot_src_instr
->op
== nir_op_ior
||
1361 inot_src_instr
->op
== nir_op_ixor
||
1362 inot_src_instr
->op
== nir_op_iand
) &&
1363 !inot_src_instr
->src
[0].abs
&&
1364 !inot_src_instr
->src
[0].negate
&&
1365 !inot_src_instr
->src
[1].abs
&&
1366 !inot_src_instr
->src
[1].negate
) {
1367 /* The sources of the source logical instruction are now the
1368 * sources of the instruction that will be generated.
1370 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1371 resolve_inot_sources(bld
, inot_src_instr
, op
);
1373 /* Smash all of the sources and destination to be signed. This
1374 * doesn't matter for the operation of the instruction, but cmod
1375 * propagation fails on unsigned sources with negation (due to
1376 * fs_inst::can_do_cmod returning false).
1379 brw_type_for_nir_type(devinfo
,
1380 (nir_alu_type
)(nir_type_int
|
1381 nir_dest_bit_size(instr
->dest
.dest
)));
1383 brw_type_for_nir_type(devinfo
,
1384 (nir_alu_type
)(nir_type_int
|
1385 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1387 brw_type_for_nir_type(devinfo
,
1388 (nir_alu_type
)(nir_type_int
|
1389 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1391 /* For XOR, only invert one of the sources. Arbitrarily choose
1394 op
[0].negate
= !op
[0].negate
;
1395 if (inot_src_instr
->op
!= nir_op_ixor
)
1396 op
[1].negate
= !op
[1].negate
;
1398 switch (inot_src_instr
->op
) {
1400 bld
.AND(result
, op
[0], op
[1]);
1404 bld
.OR(result
, op
[0], op
[1]);
1408 bld
.XOR(result
, op
[0], op
[1]);
1412 unreachable("impossible opcode");
1415 op
[0] = resolve_source_modifiers(op
[0]);
1417 bld
.NOT(result
, op
[0]);
1420 if (devinfo
->gen
>= 8) {
1421 resolve_inot_sources(bld
, instr
, op
);
1423 bld
.XOR(result
, op
[0], op
[1]);
1426 if (devinfo
->gen
>= 8) {
1427 resolve_inot_sources(bld
, instr
, op
);
1429 bld
.OR(result
, op
[0], op
[1]);
1432 if (devinfo
->gen
>= 8) {
1433 resolve_inot_sources(bld
, instr
, op
);
1435 bld
.AND(result
, op
[0], op
[1]);
1441 case nir_op_b32all_fequal2
:
1442 case nir_op_b32all_iequal2
:
1443 case nir_op_b32all_fequal3
:
1444 case nir_op_b32all_iequal3
:
1445 case nir_op_b32all_fequal4
:
1446 case nir_op_b32all_iequal4
:
1447 case nir_op_b32any_fnequal2
:
1448 case nir_op_b32any_inequal2
:
1449 case nir_op_b32any_fnequal3
:
1450 case nir_op_b32any_inequal3
:
1451 case nir_op_b32any_fnequal4
:
1452 case nir_op_b32any_inequal4
:
1453 unreachable("Lowered by nir_lower_alu_reductions");
1455 case nir_op_fnoise1_1
:
1456 case nir_op_fnoise1_2
:
1457 case nir_op_fnoise1_3
:
1458 case nir_op_fnoise1_4
:
1459 case nir_op_fnoise2_1
:
1460 case nir_op_fnoise2_2
:
1461 case nir_op_fnoise2_3
:
1462 case nir_op_fnoise2_4
:
1463 case nir_op_fnoise3_1
:
1464 case nir_op_fnoise3_2
:
1465 case nir_op_fnoise3_3
:
1466 case nir_op_fnoise3_4
:
1467 case nir_op_fnoise4_1
:
1468 case nir_op_fnoise4_2
:
1469 case nir_op_fnoise4_3
:
1470 case nir_op_fnoise4_4
:
1471 unreachable("not reached: should be handled by lower_noise");
1474 unreachable("not reached: should be handled by ldexp_to_arith()");
1477 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1478 inst
->saturate
= instr
->dest
.saturate
;
1482 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1483 inst
->saturate
= instr
->dest
.saturate
;
1487 case nir_op_f2b32
: {
1488 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1489 if (bit_size
== 64) {
1490 /* two-argument instructions can't take 64-bit immediates */
1494 if (instr
->op
== nir_op_f2b32
) {
1495 zero
= vgrf(glsl_type::double_type
);
1496 tmp
= vgrf(glsl_type::double_type
);
1497 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1499 zero
= vgrf(glsl_type::int64_t_type
);
1500 tmp
= vgrf(glsl_type::int64_t_type
);
1501 bld
.MOV(zero
, brw_imm_q(0));
1504 /* A SIMD16 execution needs to be split in two instructions, so use
1505 * a vgrf instead of the flag register as dst so instruction splitting
1508 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1509 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1512 if (bit_size
== 32) {
1513 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1515 assert(bit_size
== 16);
1516 zero
= instr
->op
== nir_op_f2b32
?
1517 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1519 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1525 inst
= bld
.RNDZ(result
, op
[0]);
1526 inst
->saturate
= instr
->dest
.saturate
;
1529 case nir_op_fceil
: {
1530 op
[0].negate
= !op
[0].negate
;
1531 fs_reg temp
= vgrf(glsl_type::float_type
);
1532 bld
.RNDD(temp
, op
[0]);
1534 inst
= bld
.MOV(result
, temp
);
1535 inst
->saturate
= instr
->dest
.saturate
;
1539 inst
= bld
.RNDD(result
, op
[0]);
1540 inst
->saturate
= instr
->dest
.saturate
;
1543 inst
= bld
.FRC(result
, op
[0]);
1544 inst
->saturate
= instr
->dest
.saturate
;
1546 case nir_op_fround_even
:
1547 inst
= bld
.RNDE(result
, op
[0]);
1548 inst
->saturate
= instr
->dest
.saturate
;
1551 case nir_op_fquantize2f16
: {
1552 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1553 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1554 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1556 /* The destination stride must be at least as big as the source stride. */
1557 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1560 /* Check for denormal */
1561 fs_reg abs_src0
= op
[0];
1562 abs_src0
.abs
= true;
1563 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1565 /* Get the appropriately signed zero */
1566 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1567 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1568 brw_imm_ud(0x80000000));
1569 /* Do the actual F32 -> F16 -> F32 conversion */
1570 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1571 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1572 /* Select that or zero based on normal status */
1573 inst
= bld
.SEL(result
, zero
, tmp32
);
1574 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1575 inst
->saturate
= instr
->dest
.saturate
;
1582 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1583 inst
->saturate
= instr
->dest
.saturate
;
1589 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1590 inst
->saturate
= instr
->dest
.saturate
;
1593 case nir_op_pack_snorm_2x16
:
1594 case nir_op_pack_snorm_4x8
:
1595 case nir_op_pack_unorm_2x16
:
1596 case nir_op_pack_unorm_4x8
:
1597 case nir_op_unpack_snorm_2x16
:
1598 case nir_op_unpack_snorm_4x8
:
1599 case nir_op_unpack_unorm_2x16
:
1600 case nir_op_unpack_unorm_4x8
:
1601 case nir_op_unpack_half_2x16
:
1602 case nir_op_pack_half_2x16
:
1603 unreachable("not reached: should be handled by lower_packing_builtins");
1605 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1606 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1607 case nir_op_unpack_half_2x16_split_x
:
1608 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1609 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1610 inst
->saturate
= instr
->dest
.saturate
;
1612 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1613 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1614 case nir_op_unpack_half_2x16_split_y
:
1615 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1616 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1617 inst
->saturate
= instr
->dest
.saturate
;
1620 case nir_op_pack_64_2x32_split
:
1621 case nir_op_pack_32_2x16_split
:
1622 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1625 case nir_op_unpack_64_2x32_split_x
:
1626 case nir_op_unpack_64_2x32_split_y
: {
1627 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1628 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1630 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1634 case nir_op_unpack_32_2x16_split_x
:
1635 case nir_op_unpack_32_2x16_split_y
: {
1636 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1637 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1639 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1644 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1645 inst
->saturate
= instr
->dest
.saturate
;
1648 case nir_op_bitfield_reverse
:
1649 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1650 bld
.BFREV(result
, op
[0]);
1653 case nir_op_bit_count
:
1654 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1655 bld
.CBIT(result
, op
[0]);
1658 case nir_op_ufind_msb
: {
1659 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1660 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1664 case nir_op_ifind_msb
: {
1665 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1667 if (devinfo
->gen
< 7) {
1668 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1670 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1672 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1673 * count from the LSB side. If FBH didn't return an error
1674 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1675 * count into an LSB count.
1677 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1679 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1680 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1681 inst
->src
[0].negate
= true;
1686 case nir_op_find_lsb
:
1687 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1689 if (devinfo
->gen
< 7) {
1690 fs_reg temp
= vgrf(glsl_type::int_type
);
1692 /* (x & -x) generates a value that consists of only the LSB of x.
1693 * For all powers of 2, findMSB(y) == findLSB(y).
1695 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1696 fs_reg negated_src
= src
;
1698 /* One must be negated, and the other must be non-negated. It
1699 * doesn't matter which is which.
1701 negated_src
.negate
= true;
1704 bld
.AND(temp
, src
, negated_src
);
1705 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1707 bld
.FBL(result
, op
[0]);
1711 case nir_op_ubitfield_extract
:
1712 case nir_op_ibitfield_extract
:
1713 unreachable("should have been lowered");
1716 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1717 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1720 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1721 bld
.BFI1(result
, op
[0], op
[1]);
1724 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1725 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1728 case nir_op_bitfield_insert
:
1729 unreachable("not reached: should have been lowered");
1732 bld
.SHL(result
, op
[0], op
[1]);
1735 bld
.ASR(result
, op
[0], op
[1]);
1738 bld
.SHR(result
, op
[0], op
[1]);
1742 bld
.ROL(result
, op
[0], op
[1]);
1745 bld
.ROR(result
, op
[0], op
[1]);
1748 case nir_op_pack_half_2x16_split
:
1749 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1753 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1754 inst
->saturate
= instr
->dest
.saturate
;
1758 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1759 inst
->saturate
= instr
->dest
.saturate
;
1762 case nir_op_b32csel
:
1763 if (optimize_frontfacing_ternary(instr
, result
))
1766 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1767 inst
= bld
.SEL(result
, op
[1], op
[2]);
1768 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1771 case nir_op_extract_u8
:
1772 case nir_op_extract_i8
: {
1773 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1778 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1779 * Use two instructions and a word or DWord intermediate integer type.
1781 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1782 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1784 if (instr
->op
== nir_op_extract_i8
) {
1785 /* If we need to sign extend, extract to a word first */
1786 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1787 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1788 bld
.MOV(result
, w_temp
);
1789 } else if (byte
& 1) {
1790 /* Extract the high byte from the word containing the desired byte
1794 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1797 /* Otherwise use an AND with 0xff and a word type */
1799 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1803 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1804 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1809 case nir_op_extract_u16
:
1810 case nir_op_extract_i16
: {
1811 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1812 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1813 bld
.MOV(result
, subscript(op
[0], type
, word
));
1818 unreachable("unhandled instruction");
1821 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1822 * to sign extend the low bit to 0/~0
1824 if (devinfo
->gen
<= 5 &&
1825 !result
.is_null() &&
1826 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1827 fs_reg masked
= vgrf(glsl_type::int_type
);
1828 bld
.AND(masked
, result
, brw_imm_d(1));
1829 masked
.negate
= true;
1830 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1835 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1836 nir_load_const_instr
*instr
)
1838 const brw_reg_type reg_type
=
1839 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1840 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1842 switch (instr
->def
.bit_size
) {
1844 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1845 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1849 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1850 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1854 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1855 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1859 assert(devinfo
->gen
>= 7);
1860 if (devinfo
->gen
== 7) {
1861 /* We don't get 64-bit integer types until gen8 */
1862 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1863 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1864 setup_imm_df(bld
, instr
->value
[i
].f64
));
1867 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1868 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1873 unreachable("Invalid bit size");
1876 nir_ssa_values
[instr
->def
.index
] = reg
;
1880 fs_visitor::get_nir_src(const nir_src
&src
)
1884 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1885 const brw_reg_type reg_type
=
1886 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1887 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1889 reg
= nir_ssa_values
[src
.ssa
->index
];
1892 /* We don't handle indirects on locals */
1893 assert(src
.reg
.indirect
== NULL
);
1894 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1895 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1898 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1899 /* The only 64-bit type available on gen7 is DF, so use that. */
1900 reg
.type
= BRW_REGISTER_TYPE_DF
;
1902 /* To avoid floating-point denorm flushing problems, set the type by
1903 * default to an integer type - instructions that need floating point
1904 * semantics will set this to F if they need to
1906 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1907 BRW_REGISTER_TYPE_D
);
1914 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1916 * This function should not be called on any value which may be 64 bits.
1917 * We could theoretically support 64-bit on gen8+ but we choose not to
1918 * because it wouldn't work in general (no gen7 support) and there are
1919 * enough restrictions in 64-bit immediates that you can't take the return
1920 * value and treat it the same as the result of get_nir_src().
1923 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1925 assert(nir_src_bit_size(src
) == 32);
1926 return nir_src_is_const(src
) ?
1927 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1931 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1934 const brw_reg_type reg_type
=
1935 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1936 dest
.ssa
.bit_size
== 8 ?
1937 BRW_REGISTER_TYPE_D
:
1938 BRW_REGISTER_TYPE_F
);
1939 nir_ssa_values
[dest
.ssa
.index
] =
1940 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1941 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
1942 return nir_ssa_values
[dest
.ssa
.index
];
1944 /* We don't handle indirects on locals */
1945 assert(dest
.reg
.indirect
== NULL
);
1946 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1947 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1952 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1955 for (unsigned i
= 0; i
< 4; i
++) {
1956 if (!((wr_mask
>> i
) & 1))
1959 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1960 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1961 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1962 if (new_inst
->src
[j
].file
== VGRF
)
1963 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1970 emit_pixel_interpolater_send(const fs_builder
&bld
,
1975 glsl_interp_mode interpolation
)
1977 struct brw_wm_prog_data
*wm_prog_data
=
1978 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1980 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1981 /* 2 floats per slot returned */
1982 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1983 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1985 wm_prog_data
->pulls_bary
= true;
1991 * Computes 1 << x, given a D/UD register containing some value x.
1994 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1996 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1998 fs_reg result
= bld
.vgrf(x
.type
, 1);
1999 fs_reg one
= bld
.vgrf(x
.type
, 1);
2001 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2002 bld
.SHL(result
, one
, x
);
2007 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2009 assert(stage
== MESA_SHADER_GEOMETRY
);
2011 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2013 if (gs_compile
->control_data_header_size_bits
== 0)
2016 /* We can only do EndPrimitive() functionality when the control data
2017 * consists of cut bits. Fortunately, the only time it isn't is when the
2018 * output type is points, in which case EndPrimitive() is a no-op.
2020 if (gs_prog_data
->control_data_format
!=
2021 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2025 /* Cut bits use one bit per vertex. */
2026 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2028 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2029 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2031 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2032 * vertex n, 0 otherwise. So all we need to do here is mark bit
2033 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2034 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2035 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2037 * Note that if EndPrimitive() is called before emitting any vertices, this
2038 * will cause us to set bit 31 of the control_data_bits register to 1.
2039 * That's fine because:
2041 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2042 * output, so the hardware will ignore cut bit 31.
2044 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2045 * last vertex, so setting cut bit 31 has no effect (since the primitive
2046 * is automatically ended when the GS terminates).
2048 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2049 * control_data_bits register to 0 when the first vertex is emitted.
2052 const fs_builder abld
= bld
.annotate("end primitive");
2054 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2055 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2056 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2057 fs_reg mask
= intexp2(abld
, prev_count
);
2058 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2059 * attention to the lower 5 bits of its second source argument, so on this
2060 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2061 * ((vertex_count - 1) % 32).
2063 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2067 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2069 assert(stage
== MESA_SHADER_GEOMETRY
);
2070 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2072 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2074 const fs_builder abld
= bld
.annotate("emit control data bits");
2075 const fs_builder fwa_bld
= bld
.exec_all();
2077 /* We use a single UD register to accumulate control data bits (32 bits
2078 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2081 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2082 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2083 * use the Channel Mask phase to enable/disable which DWord within that
2084 * group to write. (Remember, different SIMD8 channels may have emitted
2085 * different numbers of vertices, so we may need per-slot offsets.)
2087 * Channel masking presents an annoying problem: we may have to replicate
2088 * the data up to 4 times:
2090 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2092 * To avoid penalizing shaders that emit a small number of vertices, we
2093 * can avoid these sometimes: if the size of the control data header is
2094 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2095 * land in the same 128-bit group, so we can skip per-slot offsets.
2097 * Similarly, if the control data header is <= 32 bits, there is only one
2098 * DWord, so we can skip channel masks.
2100 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2102 fs_reg channel_mask
, per_slot_offset
;
2104 if (gs_compile
->control_data_header_size_bits
> 32) {
2105 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2106 channel_mask
= vgrf(glsl_type::uint_type
);
2109 if (gs_compile
->control_data_header_size_bits
> 128) {
2110 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2111 per_slot_offset
= vgrf(glsl_type::uint_type
);
2114 /* Figure out which DWord we're trying to write to using the formula:
2116 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2118 * Since bits_per_vertex is a power of two, and is known at compile
2119 * time, this can be optimized to:
2121 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2123 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2124 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2125 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2126 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2127 unsigned log2_bits_per_vertex
=
2128 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2129 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2131 if (per_slot_offset
.file
!= BAD_FILE
) {
2132 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2133 * the appropriate OWord within the control data header.
2135 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2138 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2139 * write to the appropriate DWORD within the OWORD.
2141 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2142 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2143 channel_mask
= intexp2(fwa_bld
, channel
);
2144 /* Then the channel masks need to be in bits 23:16. */
2145 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2148 /* Store the control data bits in the message payload and send it. */
2150 if (channel_mask
.file
!= BAD_FILE
)
2151 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2152 if (per_slot_offset
.file
!= BAD_FILE
)
2155 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2156 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2158 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2159 if (per_slot_offset
.file
!= BAD_FILE
)
2160 sources
[i
++] = per_slot_offset
;
2161 if (channel_mask
.file
!= BAD_FILE
)
2162 sources
[i
++] = channel_mask
;
2164 sources
[i
++] = this->control_data_bits
;
2167 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2168 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2170 /* We need to increment Global Offset by 256-bits to make room for
2171 * Broadwell's extra "Vertex Count" payload at the beginning of the
2172 * URB entry. Since this is an OWord message, Global Offset is counted
2173 * in 128-bit units, so we must set it to 2.
2175 if (gs_prog_data
->static_vertex_count
== -1)
2180 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2183 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2185 /* Note: we are calling this *before* increasing vertex_count, so
2186 * this->vertex_count == vertex_count - 1 in the formula above.
2189 /* Stream mode uses 2 bits per vertex */
2190 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2192 /* Must be a valid stream */
2193 assert(stream_id
< MAX_VERTEX_STREAMS
);
2195 /* Control data bits are initialized to 0 so we don't have to set any
2196 * bits when sending vertices to stream 0.
2201 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2203 /* reg::sid = stream_id */
2204 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2205 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2207 /* reg:shift_count = 2 * (vertex_count - 1) */
2208 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2209 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2211 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2212 * attention to the lower 5 bits of its second source argument, so on this
2213 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2214 * stream_id << ((2 * (vertex_count - 1)) % 32).
2216 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2217 abld
.SHL(mask
, sid
, shift_count
);
2218 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2222 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2225 assert(stage
== MESA_SHADER_GEOMETRY
);
2227 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2229 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2230 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2232 /* Haswell and later hardware ignores the "Render Stream Select" bits
2233 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2234 * and instead sends all primitives down the pipeline for rasterization.
2235 * If the SOL stage is enabled, "Render Stream Select" is honored and
2236 * primitives bound to non-zero streams are discarded after stream output.
2238 * Since the only purpose of primives sent to non-zero streams is to
2239 * be recorded by transform feedback, we can simply discard all geometry
2240 * bound to these streams when transform feedback is disabled.
2242 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2245 /* If we're outputting 32 control data bits or less, then we can wait
2246 * until the shader is over to output them all. Otherwise we need to
2247 * output them as we go. Now is the time to do it, since we're about to
2248 * output the vertex_count'th vertex, so it's guaranteed that the
2249 * control data bits associated with the (vertex_count - 1)th vertex are
2252 if (gs_compile
->control_data_header_size_bits
> 32) {
2253 const fs_builder abld
=
2254 bld
.annotate("emit vertex: emit control data bits");
2256 /* Only emit control data bits if we've finished accumulating a batch
2257 * of 32 bits. This is the case when:
2259 * (vertex_count * bits_per_vertex) % 32 == 0
2261 * (in other words, when the last 5 bits of vertex_count *
2262 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2263 * integer n (which is always the case, since bits_per_vertex is
2264 * always 1 or 2), this is equivalent to requiring that the last 5-n
2265 * bits of vertex_count are 0:
2267 * vertex_count & (2^(5-n) - 1) == 0
2269 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2272 * vertex_count & (32 / bits_per_vertex - 1) == 0
2274 * TODO: If vertex_count is an immediate, we could do some of this math
2275 * at compile time...
2278 abld
.AND(bld
.null_reg_d(), vertex_count
,
2279 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2280 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2282 abld
.IF(BRW_PREDICATE_NORMAL
);
2283 /* If vertex_count is 0, then no control data bits have been
2284 * accumulated yet, so we can skip emitting them.
2286 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2287 BRW_CONDITIONAL_NEQ
);
2288 abld
.IF(BRW_PREDICATE_NORMAL
);
2289 emit_gs_control_data_bits(vertex_count
);
2290 abld
.emit(BRW_OPCODE_ENDIF
);
2292 /* Reset control_data_bits to 0 so we can start accumulating a new
2295 * Note: in the case where vertex_count == 0, this neutralizes the
2296 * effect of any call to EndPrimitive() that the shader may have
2297 * made before outputting its first vertex.
2299 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2300 inst
->force_writemask_all
= true;
2301 abld
.emit(BRW_OPCODE_ENDIF
);
2304 emit_urb_writes(vertex_count
);
2306 /* In stream mode we have to set control data bits for all vertices
2307 * unless we have disabled control data bits completely (which we do
2308 * do for GL_POINTS outputs that don't use streams).
2310 if (gs_compile
->control_data_header_size_bits
> 0 &&
2311 gs_prog_data
->control_data_format
==
2312 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2313 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2318 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2319 const nir_src
&vertex_src
,
2320 unsigned base_offset
,
2321 const nir_src
&offset_src
,
2322 unsigned num_components
,
2323 unsigned first_component
)
2325 assert(type_sz(dst
.type
) == 4);
2326 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2327 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2329 /* TODO: figure out push input layout for invocations == 1 */
2330 if (gs_prog_data
->invocations
== 1 &&
2331 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2332 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2333 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2334 nir_src_as_uint(vertex_src
) * push_reg_count
;
2335 for (unsigned i
= 0; i
< num_components
; i
++) {
2336 bld
.MOV(offset(dst
, bld
, i
),
2337 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2342 /* Resort to the pull model. Ensure the VUE handles are provided. */
2343 assert(gs_prog_data
->base
.include_vue_handles
);
2345 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2346 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2348 if (gs_prog_data
->invocations
== 1) {
2349 if (nir_src_is_const(vertex_src
)) {
2350 /* The vertex index is constant; just select the proper URB handle. */
2352 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2353 BRW_REGISTER_TYPE_UD
);
2355 /* The vertex index is non-constant. We need to use indirect
2356 * addressing to fetch the proper URB handle.
2358 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2359 * indicating that channel <n> should read the handle from
2360 * DWord <n>. We convert that to bytes by multiplying by 4.
2362 * Next, we convert the vertex index to bytes by multiplying
2363 * by 32 (shifting by 5), and add the two together. This is
2364 * the final indirect byte offset.
2366 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2367 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2368 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2369 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2371 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2372 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2373 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2374 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2375 /* Convert vertex_index to bytes (multiply by 32) */
2376 bld
.SHL(vertex_offset_bytes
,
2377 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2379 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2381 /* Use first_icp_handle as the base offset. There is one register
2382 * of URB handles per vertex, so inform the register allocator that
2383 * we might read up to nir->info.gs.vertices_in registers.
2385 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2386 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2387 fs_reg(icp_offset_bytes
),
2388 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2391 assert(gs_prog_data
->invocations
> 1);
2393 if (nir_src_is_const(vertex_src
)) {
2394 unsigned vertex
= nir_src_as_uint(vertex_src
);
2395 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2397 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2398 BRW_REGISTER_TYPE_UD
));
2400 /* The vertex index is non-constant. We need to use indirect
2401 * addressing to fetch the proper URB handle.
2404 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2406 /* Convert vertex_index to bytes (multiply by 4) */
2407 bld
.SHL(icp_offset_bytes
,
2408 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2411 /* Use first_icp_handle as the base offset. There is one DWord
2412 * of URB handles per vertex, so inform the register allocator that
2413 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2415 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2416 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2417 fs_reg(icp_offset_bytes
),
2418 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2424 fs_reg indirect_offset
= get_nir_src(offset_src
);
2426 if (nir_src_is_const(offset_src
)) {
2427 /* Constant indexing - use global offset. */
2428 if (first_component
!= 0) {
2429 unsigned read_components
= num_components
+ first_component
;
2430 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2431 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2432 inst
->size_written
= read_components
*
2433 tmp
.component_size(inst
->exec_size
);
2434 for (unsigned i
= 0; i
< num_components
; i
++) {
2435 bld
.MOV(offset(dst
, bld
, i
),
2436 offset(tmp
, bld
, i
+ first_component
));
2439 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2440 inst
->size_written
= num_components
*
2441 dst
.component_size(inst
->exec_size
);
2443 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2446 /* Indirect indexing - use per-slot offsets as well. */
2447 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2448 unsigned read_components
= num_components
+ first_component
;
2449 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2450 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2451 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2452 if (first_component
!= 0) {
2453 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2455 inst
->size_written
= read_components
*
2456 tmp
.component_size(inst
->exec_size
);
2457 for (unsigned i
= 0; i
< num_components
; i
++) {
2458 bld
.MOV(offset(dst
, bld
, i
),
2459 offset(tmp
, bld
, i
+ first_component
));
2462 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2463 inst
->size_written
= num_components
*
2464 dst
.component_size(inst
->exec_size
);
2466 inst
->offset
= base_offset
;
2472 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2474 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2476 if (nir_src_is_const(*offset_src
)) {
2477 /* The only constant offset we should find is 0. brw_nir.c's
2478 * add_const_offset_to_base() will fold other constant offsets
2479 * into instr->const_index[0].
2481 assert(nir_src_as_uint(*offset_src
) == 0);
2485 return get_nir_src(*offset_src
);
2489 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2490 nir_intrinsic_instr
*instr
)
2492 assert(stage
== MESA_SHADER_VERTEX
);
2495 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2496 dest
= get_nir_dest(instr
->dest
);
2498 switch (instr
->intrinsic
) {
2499 case nir_intrinsic_load_vertex_id
:
2500 case nir_intrinsic_load_base_vertex
:
2501 unreachable("should be lowered by nir_lower_system_values()");
2503 case nir_intrinsic_load_input
: {
2504 assert(nir_dest_bit_size(instr
->dest
) == 32);
2505 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2506 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2507 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2509 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2510 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2514 case nir_intrinsic_load_vertex_id_zero_base
:
2515 case nir_intrinsic_load_instance_id
:
2516 case nir_intrinsic_load_base_instance
:
2517 case nir_intrinsic_load_draw_id
:
2518 case nir_intrinsic_load_first_vertex
:
2519 case nir_intrinsic_load_is_indexed_draw
:
2520 unreachable("lowered by brw_nir_lower_vs_inputs");
2523 nir_emit_intrinsic(bld
, instr
);
2529 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2530 nir_intrinsic_instr
*instr
)
2532 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2533 const nir_src
&vertex_src
= instr
->src
[0];
2534 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2537 if (nir_src_is_const(vertex_src
)) {
2538 /* Emit a MOV to resolve <0,1,0> regioning. */
2539 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2540 unsigned vertex
= nir_src_as_uint(vertex_src
);
2542 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2543 BRW_REGISTER_TYPE_UD
));
2544 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2545 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2546 /* For the common case of only 1 instance, an array index of
2547 * gl_InvocationID means reading g1. Skip all the indirect work.
2549 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2551 /* The vertex index is non-constant. We need to use indirect
2552 * addressing to fetch the proper URB handle.
2554 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2556 /* Each ICP handle is a single DWord (4 bytes) */
2557 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2558 bld
.SHL(vertex_offset_bytes
,
2559 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2562 /* Start at g1. We might read up to 4 registers. */
2563 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2564 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2565 brw_imm_ud(4 * REG_SIZE
));
2572 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2573 nir_intrinsic_instr
*instr
)
2575 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2576 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2577 const nir_src
&vertex_src
= instr
->src
[0];
2579 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2581 if (nir_src_is_const(vertex_src
)) {
2582 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2583 nir_src_as_uint(vertex_src
), 0),
2584 BRW_REGISTER_TYPE_UD
));
2587 /* The vertex index is non-constant. We need to use indirect
2588 * addressing to fetch the proper URB handle.
2590 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2591 * indicating that channel <n> should read the handle from
2592 * DWord <n>. We convert that to bytes by multiplying by 4.
2594 * Next, we convert the vertex index to bytes by multiplying
2595 * by 32 (shifting by 5), and add the two together. This is
2596 * the final indirect byte offset.
2598 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2599 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2600 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2601 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2602 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2604 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2605 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2606 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2607 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2608 /* Convert vertex_index to bytes (multiply by 32) */
2609 bld
.SHL(vertex_offset_bytes
,
2610 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2612 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2614 /* Use first_icp_handle as the base offset. There is one register
2615 * of URB handles per vertex, so inform the register allocator that
2616 * we might read up to nir->info.gs.vertices_in registers.
2618 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2619 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2620 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2626 fs_visitor::get_tcs_output_urb_handle()
2628 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2630 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2631 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2633 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2634 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2639 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2640 nir_intrinsic_instr
*instr
)
2642 assert(stage
== MESA_SHADER_TESS_CTRL
);
2643 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2644 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2645 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2648 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2651 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2652 dst
= get_nir_dest(instr
->dest
);
2654 switch (instr
->intrinsic
) {
2655 case nir_intrinsic_load_primitive_id
:
2656 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2657 : brw_vec1_grf(0, 1)));
2659 case nir_intrinsic_load_invocation_id
:
2660 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2662 case nir_intrinsic_load_patch_vertices_in
:
2663 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2664 brw_imm_d(tcs_key
->input_vertices
));
2667 case nir_intrinsic_barrier
: {
2668 if (tcs_prog_data
->instances
== 1)
2671 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2672 fs_reg m0_2
= component(m0
, 2);
2674 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2676 /* Zero the message header */
2677 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2679 if (devinfo
->gen
< 11) {
2680 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2681 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2682 brw_imm_ud(INTEL_MASK(16, 13)));
2684 /* Shift it up to bits 27:24. */
2685 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2687 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2688 brw_imm_ud(INTEL_MASK(30, 24)));
2691 /* Set the Barrier Count and the enable bit */
2692 if (devinfo
->gen
< 11) {
2693 chanbld
.OR(m0_2
, m0_2
,
2694 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2696 chanbld
.OR(m0_2
, m0_2
,
2697 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2700 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2704 case nir_intrinsic_load_input
:
2705 unreachable("nir_lower_io should never give us these.");
2708 case nir_intrinsic_load_per_vertex_input
: {
2709 assert(nir_dest_bit_size(instr
->dest
) == 32);
2710 fs_reg indirect_offset
= get_indirect_offset(instr
);
2711 unsigned imm_offset
= instr
->const_index
[0];
2715 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2716 : get_tcs_single_patch_icp_handle(bld
, instr
);
2718 /* We can only read two double components with each URB read, so
2719 * we send two read messages in that case, each one loading up to
2720 * two double components.
2722 unsigned num_components
= instr
->num_components
;
2723 unsigned first_component
= nir_intrinsic_component(instr
);
2725 if (indirect_offset
.file
== BAD_FILE
) {
2726 /* Constant indexing - use global offset. */
2727 if (first_component
!= 0) {
2728 unsigned read_components
= num_components
+ first_component
;
2729 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2730 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2731 for (unsigned i
= 0; i
< num_components
; i
++) {
2732 bld
.MOV(offset(dst
, bld
, i
),
2733 offset(tmp
, bld
, i
+ first_component
));
2736 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2738 inst
->offset
= imm_offset
;
2741 /* Indirect indexing - use per-slot offsets as well. */
2742 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2743 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2744 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2745 if (first_component
!= 0) {
2746 unsigned read_components
= num_components
+ first_component
;
2747 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2748 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2750 for (unsigned i
= 0; i
< num_components
; i
++) {
2751 bld
.MOV(offset(dst
, bld
, i
),
2752 offset(tmp
, bld
, i
+ first_component
));
2755 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2758 inst
->offset
= imm_offset
;
2761 inst
->size_written
= (num_components
+ first_component
) *
2762 inst
->dst
.component_size(inst
->exec_size
);
2764 /* Copy the temporary to the destination to deal with writemasking.
2766 * Also attempt to deal with gl_PointSize being in the .w component.
2768 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2769 assert(type_sz(dst
.type
) == 4);
2770 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2771 inst
->size_written
= 4 * REG_SIZE
;
2772 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2777 case nir_intrinsic_load_output
:
2778 case nir_intrinsic_load_per_vertex_output
: {
2779 assert(nir_dest_bit_size(instr
->dest
) == 32);
2780 fs_reg indirect_offset
= get_indirect_offset(instr
);
2781 unsigned imm_offset
= instr
->const_index
[0];
2782 unsigned first_component
= nir_intrinsic_component(instr
);
2784 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2787 if (indirect_offset
.file
== BAD_FILE
) {
2788 /* This MOV replicates the output handle to all enabled channels
2789 * is SINGLE_PATCH mode.
2791 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2792 bld
.MOV(patch_handle
, output_handles
);
2795 if (first_component
!= 0) {
2796 unsigned read_components
=
2797 instr
->num_components
+ first_component
;
2798 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2799 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2801 inst
->size_written
= read_components
* REG_SIZE
;
2802 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2803 bld
.MOV(offset(dst
, bld
, i
),
2804 offset(tmp
, bld
, i
+ first_component
));
2807 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2809 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2811 inst
->offset
= imm_offset
;
2815 /* Indirect indexing - use per-slot offsets as well. */
2816 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2817 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2818 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2819 if (first_component
!= 0) {
2820 unsigned read_components
=
2821 instr
->num_components
+ first_component
;
2822 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2823 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2825 inst
->size_written
= read_components
* REG_SIZE
;
2826 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2827 bld
.MOV(offset(dst
, bld
, i
),
2828 offset(tmp
, bld
, i
+ first_component
));
2831 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2833 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2835 inst
->offset
= imm_offset
;
2841 case nir_intrinsic_store_output
:
2842 case nir_intrinsic_store_per_vertex_output
: {
2843 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2844 fs_reg value
= get_nir_src(instr
->src
[0]);
2845 fs_reg indirect_offset
= get_indirect_offset(instr
);
2846 unsigned imm_offset
= instr
->const_index
[0];
2847 unsigned mask
= instr
->const_index
[1];
2848 unsigned header_regs
= 0;
2849 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2852 srcs
[header_regs
++] = output_handles
;
2854 if (indirect_offset
.file
!= BAD_FILE
) {
2855 srcs
[header_regs
++] = indirect_offset
;
2861 unsigned num_components
= util_last_bit(mask
);
2864 /* We can only pack two 64-bit components in a single message, so send
2865 * 2 messages if we have more components
2867 unsigned first_component
= nir_intrinsic_component(instr
);
2868 mask
= mask
<< first_component
;
2870 if (mask
!= WRITEMASK_XYZW
) {
2871 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2872 opcode
= indirect_offset
.file
!= BAD_FILE
?
2873 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2874 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2876 opcode
= indirect_offset
.file
!= BAD_FILE
?
2877 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2878 SHADER_OPCODE_URB_WRITE_SIMD8
;
2881 for (unsigned i
= 0; i
< num_components
; i
++) {
2882 if (!(mask
& (1 << (i
+ first_component
))))
2885 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2888 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2890 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2891 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2893 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2894 inst
->offset
= imm_offset
;
2900 nir_emit_intrinsic(bld
, instr
);
2906 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2907 nir_intrinsic_instr
*instr
)
2909 assert(stage
== MESA_SHADER_TESS_EVAL
);
2910 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2913 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2914 dest
= get_nir_dest(instr
->dest
);
2916 switch (instr
->intrinsic
) {
2917 case nir_intrinsic_load_primitive_id
:
2918 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2920 case nir_intrinsic_load_tess_coord
:
2921 /* gl_TessCoord is part of the payload in g1-3 */
2922 for (unsigned i
= 0; i
< 3; i
++) {
2923 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2927 case nir_intrinsic_load_input
:
2928 case nir_intrinsic_load_per_vertex_input
: {
2929 assert(nir_dest_bit_size(instr
->dest
) == 32);
2930 fs_reg indirect_offset
= get_indirect_offset(instr
);
2931 unsigned imm_offset
= instr
->const_index
[0];
2932 unsigned first_component
= nir_intrinsic_component(instr
);
2935 if (indirect_offset
.file
== BAD_FILE
) {
2936 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2937 * which is 16 registers (since each holds 2 vec4 slots).
2939 const unsigned max_push_slots
= 32;
2940 if (imm_offset
< max_push_slots
) {
2941 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2942 for (int i
= 0; i
< instr
->num_components
; i
++) {
2943 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
2944 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2947 tes_prog_data
->base
.urb_read_length
=
2948 MAX2(tes_prog_data
->base
.urb_read_length
,
2949 (imm_offset
/ 2) + 1);
2951 /* Replicate the patch handle to all enabled channels */
2952 const fs_reg srcs
[] = {
2953 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2955 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2956 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2958 if (first_component
!= 0) {
2959 unsigned read_components
=
2960 instr
->num_components
+ first_component
;
2961 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2962 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2964 inst
->size_written
= read_components
* REG_SIZE
;
2965 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2966 bld
.MOV(offset(dest
, bld
, i
),
2967 offset(tmp
, bld
, i
+ first_component
));
2970 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2972 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2975 inst
->offset
= imm_offset
;
2978 /* Indirect indexing - use per-slot offsets as well. */
2980 /* We can only read two double components with each URB read, so
2981 * we send two read messages in that case, each one loading up to
2982 * two double components.
2984 unsigned num_components
= instr
->num_components
;
2985 const fs_reg srcs
[] = {
2986 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2989 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2990 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2992 if (first_component
!= 0) {
2993 unsigned read_components
=
2994 num_components
+ first_component
;
2995 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2996 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2998 for (unsigned i
= 0; i
< num_components
; i
++) {
2999 bld
.MOV(offset(dest
, bld
, i
),
3000 offset(tmp
, bld
, i
+ first_component
));
3003 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3007 inst
->offset
= imm_offset
;
3008 inst
->size_written
= (num_components
+ first_component
) *
3009 inst
->dst
.component_size(inst
->exec_size
);
3014 nir_emit_intrinsic(bld
, instr
);
3020 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3021 nir_intrinsic_instr
*instr
)
3023 assert(stage
== MESA_SHADER_GEOMETRY
);
3024 fs_reg indirect_offset
;
3027 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3028 dest
= get_nir_dest(instr
->dest
);
3030 switch (instr
->intrinsic
) {
3031 case nir_intrinsic_load_primitive_id
:
3032 assert(stage
== MESA_SHADER_GEOMETRY
);
3033 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3034 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3035 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3038 case nir_intrinsic_load_input
:
3039 unreachable("load_input intrinsics are invalid for the GS stage");
3041 case nir_intrinsic_load_per_vertex_input
:
3042 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3043 instr
->src
[1], instr
->num_components
,
3044 nir_intrinsic_component(instr
));
3047 case nir_intrinsic_emit_vertex_with_counter
:
3048 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3051 case nir_intrinsic_end_primitive_with_counter
:
3052 emit_gs_end_primitive(instr
->src
[0]);
3055 case nir_intrinsic_set_vertex_count
:
3056 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3059 case nir_intrinsic_load_invocation_id
: {
3060 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3061 assert(val
.file
!= BAD_FILE
);
3062 dest
.type
= val
.type
;
3068 nir_emit_intrinsic(bld
, instr
);
3074 * Fetch the current render target layer index.
3077 fetch_render_target_array_index(const fs_builder
&bld
)
3079 if (bld
.shader
->devinfo
->gen
>= 6) {
3080 /* The render target array index is provided in the thread payload as
3081 * bits 26:16 of r0.0.
3083 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3084 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3088 /* Pre-SNB we only ever render into the first layer of the framebuffer
3089 * since layered rendering is not implemented.
3091 return brw_imm_ud(0);
3096 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3097 * framebuffer at the current fragment coordinates and sample index.
3100 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3103 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3105 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3106 const brw_wm_prog_key
*wm_key
=
3107 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3108 assert(!wm_key
->coherent_fb_fetch
);
3109 const struct brw_wm_prog_data
*wm_prog_data
=
3110 brw_wm_prog_data(stage_prog_data
);
3112 /* Calculate the surface index relative to the start of the texture binding
3113 * table block, since that's what the texturing messages expect.
3115 const unsigned surface
= target
+
3116 wm_prog_data
->binding_table
.render_target_read_start
-
3117 wm_prog_data
->base
.binding_table
.texture_start
;
3119 /* Calculate the fragment coordinates. */
3120 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3121 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3122 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3123 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3125 /* Calculate the sample index and MCS payload when multisampling. Luckily
3126 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3127 * shouldn't be necessary to recompile based on whether the framebuffer is
3130 if (wm_key
->multisample_fbo
&&
3131 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3132 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3134 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3135 const fs_reg mcs
= wm_key
->multisample_fbo
?
3136 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3138 /* Use either a normal or a CMS texel fetch message depending on whether
3139 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3140 * message just in case the framebuffer uses 16x multisampling, it should
3141 * be equivalent to the normal CMS fetch for lower multisampling modes.
3143 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3144 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3145 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3147 /* Emit the instruction. */
3148 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3149 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3150 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3151 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3152 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3153 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3154 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3155 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3156 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3158 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3159 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3165 * Actual coherent framebuffer read implemented using the native render target
3166 * read message. Requires SKL+.
3169 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3171 assert(bld
.shader
->devinfo
->gen
>= 9);
3172 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3173 inst
->target
= target
;
3174 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3180 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3182 if (n
&& regs
[0].file
!= BAD_FILE
) {
3186 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3188 for (unsigned i
= 0; i
< n
; i
++)
3196 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3198 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3199 const brw_wm_prog_key
*const key
=
3200 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3201 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3202 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3204 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3205 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3207 else if (l
== FRAG_RESULT_COLOR
)
3208 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3209 MAX2(key
->nr_color_regions
, 1));
3211 else if (l
== FRAG_RESULT_DEPTH
)
3212 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3214 else if (l
== FRAG_RESULT_STENCIL
)
3215 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3217 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3218 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3220 else if (l
>= FRAG_RESULT_DATA0
&&
3221 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3222 return alloc_temporary(v
->bld
, 4,
3223 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3226 unreachable("Invalid location");
3229 /* Annoyingly, we get the barycentrics into the shader in a layout that's
3230 * optimized for PLN but it doesn't work nearly as well as one would like for
3231 * manual interpolation.
3234 shuffle_from_pln_layout(const fs_builder
&bld
, fs_reg dest
, fs_reg pln_data
)
3236 dest
.type
= BRW_REGISTER_TYPE_F
;
3237 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3238 const fs_reg dest_u
= offset(dest
, bld
, 0);
3239 const fs_reg dest_v
= offset(dest
, bld
, 1);
3241 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3242 const fs_builder gbld
= bld
.group(8, g
);
3243 gbld
.MOV(horiz_offset(dest_u
, g
* 8),
3244 byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
));
3245 gbld
.MOV(horiz_offset(dest_v
, g
* 8),
3246 byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
));
3251 shuffle_to_pln_layout(const fs_builder
&bld
, fs_reg pln_data
, fs_reg src
)
3253 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3254 src
.type
= BRW_REGISTER_TYPE_F
;
3255 const fs_reg src_u
= offset(src
, bld
, 0);
3256 const fs_reg src_v
= offset(src
, bld
, 1);
3258 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3259 const fs_builder gbld
= bld
.group(8, g
);
3260 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
),
3261 horiz_offset(src_u
, g
* 8));
3262 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
),
3263 horiz_offset(src_v
, g
* 8));
3268 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3269 nir_intrinsic_instr
*instr
)
3271 assert(stage
== MESA_SHADER_FRAGMENT
);
3274 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3275 dest
= get_nir_dest(instr
->dest
);
3277 switch (instr
->intrinsic
) {
3278 case nir_intrinsic_load_front_face
:
3279 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3280 *emit_frontfacing_interpolation());
3283 case nir_intrinsic_load_sample_pos
: {
3284 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3285 assert(sample_pos
.file
!= BAD_FILE
);
3286 dest
.type
= sample_pos
.type
;
3287 bld
.MOV(dest
, sample_pos
);
3288 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3292 case nir_intrinsic_load_layer_id
:
3293 dest
.type
= BRW_REGISTER_TYPE_UD
;
3294 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3297 case nir_intrinsic_is_helper_invocation
: {
3298 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3299 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3300 * consideration demoted invocations. That information is stored in
3303 dest
.type
= BRW_REGISTER_TYPE_UD
;
3305 bld
.MOV(dest
, brw_imm_ud(0));
3307 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3308 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3309 mov
->predicate_inverse
= true;
3310 mov
->flag_subreg
= 1;
3314 case nir_intrinsic_load_helper_invocation
:
3315 case nir_intrinsic_load_sample_mask_in
:
3316 case nir_intrinsic_load_sample_id
: {
3317 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3318 fs_reg val
= nir_system_values
[sv
];
3319 assert(val
.file
!= BAD_FILE
);
3320 dest
.type
= val
.type
;
3325 case nir_intrinsic_store_output
: {
3326 const fs_reg src
= get_nir_src(instr
->src
[0]);
3327 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3328 const unsigned location
= nir_intrinsic_base(instr
) +
3329 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3330 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3333 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3334 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3335 offset(src
, bld
, j
));
3340 case nir_intrinsic_load_output
: {
3341 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3342 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3343 assert(l
>= FRAG_RESULT_DATA0
);
3344 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3345 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3346 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3348 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3349 emit_coherent_fb_read(bld
, tmp
, target
);
3351 emit_non_coherent_fb_read(bld
, tmp
, target
);
3353 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3354 bld
.MOV(offset(dest
, bld
, j
),
3355 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3361 case nir_intrinsic_demote
:
3362 case nir_intrinsic_discard
:
3363 case nir_intrinsic_demote_if
:
3364 case nir_intrinsic_discard_if
: {
3365 /* We track our discarded pixels in f0.1. By predicating on it, we can
3366 * update just the flag bits that aren't yet discarded. If there's no
3367 * condition, we emit a CMP of g0 != g0, so all currently executing
3368 * channels will get turned off.
3370 fs_inst
*cmp
= NULL
;
3371 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3372 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3373 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3376 alu
->op
!= nir_op_bcsel
&&
3377 alu
->op
!= nir_op_inot
) {
3378 /* Re-emit the instruction that generated the Boolean value, but
3379 * do not store it. Since this instruction will be conditional,
3380 * other instructions that want to use the real Boolean value may
3381 * get garbage. This was a problem for piglit's fs-discard-exit-2
3384 * Ideally we'd detect that the instruction cannot have a
3385 * conditional modifier before emitting the instructions. Alas,
3386 * that is nigh impossible. Instead, we're going to assume the
3387 * instruction (or last instruction) generated can have a
3388 * conditional modifier. If it cannot, fallback to the old-style
3389 * compare, and hope dead code elimination will clean up the
3390 * extra instructions generated.
3392 nir_emit_alu(bld
, alu
, false);
3394 cmp
= (fs_inst
*) instructions
.get_tail();
3395 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3396 if (cmp
->can_do_cmod())
3397 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3401 /* The old sequence that would have been generated is,
3402 * basically, bool_result == false. This is equivalent to
3403 * !bool_result, so negate the old modifier.
3405 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3410 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3411 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3414 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3415 BRW_REGISTER_TYPE_UW
));
3416 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3419 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3420 cmp
->flag_subreg
= 1;
3422 if (devinfo
->gen
>= 6) {
3423 /* Due to the way we implement discard, the jump will only happen
3424 * when the whole quad is discarded. So we can do this even for
3425 * demote as it won't break its uniformity promises.
3427 emit_discard_jump();
3430 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.");
3434 case nir_intrinsic_load_input
: {
3435 /* load_input is only used for flat inputs */
3436 assert(nir_dest_bit_size(instr
->dest
) == 32);
3437 unsigned base
= nir_intrinsic_base(instr
);
3438 unsigned comp
= nir_intrinsic_component(instr
);
3439 unsigned num_components
= instr
->num_components
;
3441 /* Special case fields in the VUE header */
3442 if (base
== VARYING_SLOT_LAYER
)
3444 else if (base
== VARYING_SLOT_VIEWPORT
)
3447 for (unsigned int i
= 0; i
< num_components
; i
++) {
3448 bld
.MOV(offset(dest
, bld
, i
),
3449 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3454 case nir_intrinsic_load_fs_input_interp_deltas
: {
3455 assert(stage
== MESA_SHADER_FRAGMENT
);
3456 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3457 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3458 nir_intrinsic_component(instr
));
3459 dest
.type
= BRW_REGISTER_TYPE_F
;
3460 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3461 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3462 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3466 case nir_intrinsic_load_barycentric_pixel
:
3467 case nir_intrinsic_load_barycentric_centroid
:
3468 case nir_intrinsic_load_barycentric_sample
: {
3469 /* Use the delta_xy values computed from the payload */
3470 const glsl_interp_mode interp_mode
=
3471 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3472 enum brw_barycentric_mode bary
=
3473 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3475 shuffle_from_pln_layout(bld
, dest
, this->delta_xy
[bary
]);
3479 case nir_intrinsic_load_barycentric_at_sample
: {
3480 const glsl_interp_mode interpolation
=
3481 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3483 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3484 if (nir_src_is_const(instr
->src
[0])) {
3485 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3487 emit_pixel_interpolater_send(bld
,
3488 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3491 brw_imm_ud(msg_data
),
3494 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3495 BRW_REGISTER_TYPE_UD
);
3497 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3498 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3499 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3500 bld
.exec_all().group(1, 0)
3501 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3502 emit_pixel_interpolater_send(bld
,
3503 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3509 /* Make a loop that sends a message to the pixel interpolater
3510 * for the sample number in each live channel. If there are
3511 * multiple channels with the same sample number then these
3512 * will be handled simultaneously with a single interation of
3515 bld
.emit(BRW_OPCODE_DO
);
3517 /* Get the next live sample number into sample_id_reg */
3518 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3520 /* Set the flag register so that we can perform the send
3521 * message on all channels that have the same sample number
3523 bld
.CMP(bld
.null_reg_ud(),
3524 sample_src
, sample_id
,
3525 BRW_CONDITIONAL_EQ
);
3526 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3527 bld
.exec_all().group(1, 0)
3528 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3530 emit_pixel_interpolater_send(bld
,
3531 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3534 component(msg_data
, 0),
3536 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3538 /* Continue the loop if there are any live channels left */
3539 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3541 bld
.emit(BRW_OPCODE_WHILE
));
3544 shuffle_from_pln_layout(bld
, dest
, tmp
);
3548 case nir_intrinsic_load_barycentric_at_offset
: {
3549 const glsl_interp_mode interpolation
=
3550 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3552 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3554 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3556 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3557 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3558 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3560 emit_pixel_interpolater_send(bld
,
3561 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3564 brw_imm_ud(off_x
| (off_y
<< 4)),
3567 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3568 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3569 BRW_REGISTER_TYPE_F
);
3570 for (int i
= 0; i
< 2; i
++) {
3571 fs_reg temp
= vgrf(glsl_type::float_type
);
3572 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3573 fs_reg itemp
= vgrf(glsl_type::int_type
);
3575 bld
.MOV(itemp
, temp
);
3577 /* Clamp the upper end of the range to +7/16.
3578 * ARB_gpu_shader5 requires that we support a maximum offset
3579 * of +0.5, which isn't representable in a S0.4 value -- if
3580 * we didn't clamp it, we'd end up with -8/16, which is the
3581 * opposite of what the shader author wanted.
3583 * This is legal due to ARB_gpu_shader5's quantization
3586 * "Not all values of <offset> may be supported; x and y
3587 * offsets may be rounded to fixed-point values with the
3588 * number of fraction bits given by the
3589 * implementation-dependent constant
3590 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3592 set_condmod(BRW_CONDITIONAL_L
,
3593 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3596 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3597 emit_pixel_interpolater_send(bld
,
3604 shuffle_from_pln_layout(bld
, dest
, tmp
);
3608 case nir_intrinsic_load_frag_coord
:
3609 emit_fragcoord_interpolation(dest
);
3612 case nir_intrinsic_load_interpolated_input
: {
3613 assert(instr
->src
[0].ssa
&&
3614 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3615 nir_intrinsic_instr
*bary_intrinsic
=
3616 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3617 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3618 enum glsl_interp_mode interp_mode
=
3619 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3622 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3623 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3624 /* Use the result of the PI message. Because the load_barycentric
3625 * intrinsics return a regular vec2 and we need it in PLN layout, we
3626 * have to do a translation. Fortunately, copy-prop cleans this up
3629 dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3630 shuffle_to_pln_layout(bld
, dst_xy
, get_nir_src(instr
->src
[0]));
3632 /* Use the delta_xy values computed from the payload */
3633 enum brw_barycentric_mode bary
=
3634 brw_barycentric_mode(interp_mode
, bary_intrin
);
3636 dst_xy
= this->delta_xy
[bary
];
3639 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3641 component(interp_reg(nir_intrinsic_base(instr
),
3642 nir_intrinsic_component(instr
) + i
), 0);
3643 interp
.type
= BRW_REGISTER_TYPE_F
;
3644 dest
.type
= BRW_REGISTER_TYPE_F
;
3646 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3647 fs_reg tmp
= vgrf(glsl_type::float_type
);
3648 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3649 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3651 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3658 nir_emit_intrinsic(bld
, instr
);
3664 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3665 nir_intrinsic_instr
*instr
)
3667 assert(stage
== MESA_SHADER_COMPUTE
);
3668 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3671 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3672 dest
= get_nir_dest(instr
->dest
);
3674 switch (instr
->intrinsic
) {
3675 case nir_intrinsic_barrier
:
3677 cs_prog_data
->uses_barrier
= true;
3680 case nir_intrinsic_load_subgroup_id
:
3681 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3684 case nir_intrinsic_load_local_invocation_id
:
3685 case nir_intrinsic_load_work_group_id
: {
3686 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3687 fs_reg val
= nir_system_values
[sv
];
3688 assert(val
.file
!= BAD_FILE
);
3689 dest
.type
= val
.type
;
3690 for (unsigned i
= 0; i
< 3; i
++)
3691 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3695 case nir_intrinsic_load_num_work_groups
: {
3696 const unsigned surface
=
3697 cs_prog_data
->binding_table
.work_groups_start
;
3699 cs_prog_data
->uses_num_work_groups
= true;
3701 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3702 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3703 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3704 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3706 /* Read the 3 GLuint components of gl_NumWorkGroups */
3707 for (unsigned i
= 0; i
< 3; i
++) {
3708 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3709 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3710 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3715 case nir_intrinsic_shared_atomic_add
:
3716 case nir_intrinsic_shared_atomic_imin
:
3717 case nir_intrinsic_shared_atomic_umin
:
3718 case nir_intrinsic_shared_atomic_imax
:
3719 case nir_intrinsic_shared_atomic_umax
:
3720 case nir_intrinsic_shared_atomic_and
:
3721 case nir_intrinsic_shared_atomic_or
:
3722 case nir_intrinsic_shared_atomic_xor
:
3723 case nir_intrinsic_shared_atomic_exchange
:
3724 case nir_intrinsic_shared_atomic_comp_swap
:
3725 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3727 case nir_intrinsic_shared_atomic_fmin
:
3728 case nir_intrinsic_shared_atomic_fmax
:
3729 case nir_intrinsic_shared_atomic_fcomp_swap
:
3730 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3733 case nir_intrinsic_load_shared
: {
3734 assert(devinfo
->gen
>= 7);
3735 assert(stage
== MESA_SHADER_COMPUTE
);
3737 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3738 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3739 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3740 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3741 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3743 /* Make dest unsigned because that's what the temporary will be */
3744 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3746 /* Read the vector */
3747 if (nir_intrinsic_align(instr
) >= 4) {
3748 assert(nir_dest_bit_size(instr
->dest
) == 32);
3749 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3751 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3752 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3753 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3755 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3756 assert(nir_dest_num_components(instr
->dest
) == 1);
3757 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3759 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3760 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3761 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3762 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3767 case nir_intrinsic_store_shared
: {
3768 assert(devinfo
->gen
>= 7);
3769 assert(stage
== MESA_SHADER_COMPUTE
);
3771 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3772 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3773 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3774 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3775 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3777 fs_reg data
= get_nir_src(instr
->src
[0]);
3778 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3780 assert(nir_intrinsic_write_mask(instr
) ==
3781 (1u << instr
->num_components
) - 1);
3782 if (nir_intrinsic_align(instr
) >= 4) {
3783 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3784 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3785 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3786 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3787 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3788 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3790 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3791 assert(nir_src_num_components(instr
->src
[0]) == 1);
3792 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3794 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3795 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3797 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3798 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3804 nir_emit_intrinsic(bld
, instr
);
3810 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3811 nir_op op
, brw_reg_type type
)
3813 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3814 switch (type_sz(type
)) {
3816 assert(type
!= BRW_REGISTER_TYPE_HF
);
3817 return retype(brw_imm_uw(value
.u16
), type
);
3819 return retype(brw_imm_ud(value
.u32
), type
);
3821 if (type
== BRW_REGISTER_TYPE_DF
)
3822 return setup_imm_df(bld
, value
.f64
);
3824 return retype(brw_imm_u64(value
.u64
), type
);
3826 unreachable("Invalid type size");
3831 brw_op_for_nir_reduction_op(nir_op op
)
3834 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3835 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3836 case nir_op_imul
: return BRW_OPCODE_MUL
;
3837 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3838 case nir_op_imin
: return BRW_OPCODE_SEL
;
3839 case nir_op_umin
: return BRW_OPCODE_SEL
;
3840 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3841 case nir_op_imax
: return BRW_OPCODE_SEL
;
3842 case nir_op_umax
: return BRW_OPCODE_SEL
;
3843 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3844 case nir_op_iand
: return BRW_OPCODE_AND
;
3845 case nir_op_ior
: return BRW_OPCODE_OR
;
3846 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3848 unreachable("Invalid reduction operation");
3852 static brw_conditional_mod
3853 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3856 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3857 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3858 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3859 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3860 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3861 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3862 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3863 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3864 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3865 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3866 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3867 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3868 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3870 unreachable("Invalid reduction operation");
3875 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3876 nir_intrinsic_instr
*instr
)
3878 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3880 if (stage_prog_data
->binding_table
.image_start
> 0) {
3881 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3882 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3884 bld
.ADD(image
, image
,
3885 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3889 return bld
.emit_uniformize(image
);
3893 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3894 nir_intrinsic_instr
*instr
)
3896 /* SSBO stores are weird in that their index is in src[1] */
3897 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3900 if (nir_src_is_const(instr
->src
[src
])) {
3901 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3902 nir_src_as_uint(instr
->src
[src
]);
3903 surf_index
= brw_imm_ud(index
);
3905 surf_index
= vgrf(glsl_type::uint_type
);
3906 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3907 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3910 return bld
.emit_uniformize(surf_index
);
3914 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3916 switch (nir_intrinsic_image_dim(instr
)) {
3917 case GLSL_SAMPLER_DIM_1D
:
3918 return 1 + nir_intrinsic_image_array(instr
);
3919 case GLSL_SAMPLER_DIM_2D
:
3920 case GLSL_SAMPLER_DIM_RECT
:
3921 return 2 + nir_intrinsic_image_array(instr
);
3922 case GLSL_SAMPLER_DIM_3D
:
3923 case GLSL_SAMPLER_DIM_CUBE
:
3925 case GLSL_SAMPLER_DIM_BUF
:
3927 case GLSL_SAMPLER_DIM_MS
:
3928 return 2 + nir_intrinsic_image_array(instr
);
3930 unreachable("Invalid image dimension");
3935 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3938 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3939 dest
= get_nir_dest(instr
->dest
);
3941 switch (instr
->intrinsic
) {
3942 case nir_intrinsic_image_load
:
3943 case nir_intrinsic_image_store
:
3944 case nir_intrinsic_image_atomic_add
:
3945 case nir_intrinsic_image_atomic_imin
:
3946 case nir_intrinsic_image_atomic_umin
:
3947 case nir_intrinsic_image_atomic_imax
:
3948 case nir_intrinsic_image_atomic_umax
:
3949 case nir_intrinsic_image_atomic_and
:
3950 case nir_intrinsic_image_atomic_or
:
3951 case nir_intrinsic_image_atomic_xor
:
3952 case nir_intrinsic_image_atomic_exchange
:
3953 case nir_intrinsic_image_atomic_comp_swap
:
3954 case nir_intrinsic_bindless_image_load
:
3955 case nir_intrinsic_bindless_image_store
:
3956 case nir_intrinsic_bindless_image_atomic_add
:
3957 case nir_intrinsic_bindless_image_atomic_imin
:
3958 case nir_intrinsic_bindless_image_atomic_umin
:
3959 case nir_intrinsic_bindless_image_atomic_imax
:
3960 case nir_intrinsic_bindless_image_atomic_umax
:
3961 case nir_intrinsic_bindless_image_atomic_and
:
3962 case nir_intrinsic_bindless_image_atomic_or
:
3963 case nir_intrinsic_bindless_image_atomic_xor
:
3964 case nir_intrinsic_bindless_image_atomic_exchange
:
3965 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
3966 if (stage
== MESA_SHADER_FRAGMENT
&&
3967 instr
->intrinsic
!= nir_intrinsic_image_load
)
3968 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3970 /* Get some metadata from the image intrinsic. */
3971 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3973 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3975 switch (instr
->intrinsic
) {
3976 case nir_intrinsic_image_load
:
3977 case nir_intrinsic_image_store
:
3978 case nir_intrinsic_image_atomic_add
:
3979 case nir_intrinsic_image_atomic_imin
:
3980 case nir_intrinsic_image_atomic_umin
:
3981 case nir_intrinsic_image_atomic_imax
:
3982 case nir_intrinsic_image_atomic_umax
:
3983 case nir_intrinsic_image_atomic_and
:
3984 case nir_intrinsic_image_atomic_or
:
3985 case nir_intrinsic_image_atomic_xor
:
3986 case nir_intrinsic_image_atomic_exchange
:
3987 case nir_intrinsic_image_atomic_comp_swap
:
3988 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3989 get_nir_image_intrinsic_image(bld
, instr
);
3994 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
3995 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
3999 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4000 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4001 brw_imm_ud(image_intrinsic_coord_components(instr
));
4003 /* Emit an image load, store or atomic op. */
4004 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4005 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4006 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4008 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4009 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4010 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4011 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4012 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4013 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4014 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4015 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4016 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4018 unsigned num_srcs
= info
->num_srcs
;
4019 int op
= brw_aop_for_nir_intrinsic(instr
);
4020 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4021 assert(num_srcs
== 4);
4025 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4029 data
= get_nir_src(instr
->src
[3]);
4030 if (num_srcs
>= 5) {
4031 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4032 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4033 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4036 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4038 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4039 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4044 case nir_intrinsic_image_size
:
4045 case nir_intrinsic_bindless_image_size
: {
4046 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4047 * into will handle the binding table index for us in the geneerator.
4048 * Incidentally, this means that we can handle bindless with exactly the
4051 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4052 BRW_REGISTER_TYPE_UD
);
4053 image
= bld
.emit_uniformize(image
);
4055 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4056 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4057 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4059 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4060 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4061 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4062 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4064 /* Since the image size is always uniform, we can just emit a SIMD8
4065 * query instruction and splat the result out.
4067 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4069 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4070 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4071 tmp
, srcs
, ARRAY_SIZE(srcs
));
4072 inst
->size_written
= 4 * REG_SIZE
;
4074 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4075 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4076 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4077 offset(retype(dest
, tmp
.type
), bld
, c
),
4078 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4080 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4081 component(offset(tmp
, ubld
, c
), 0));
4087 case nir_intrinsic_image_load_raw_intel
: {
4088 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4089 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4090 get_nir_image_intrinsic_image(bld
, instr
);
4091 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4092 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4093 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4096 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4097 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4098 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4102 case nir_intrinsic_image_store_raw_intel
: {
4103 if (stage
== MESA_SHADER_FRAGMENT
)
4104 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4106 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4107 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4108 get_nir_image_intrinsic_image(bld
, instr
);
4109 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4110 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4111 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4112 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4114 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4115 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4119 case nir_intrinsic_group_memory_barrier
:
4120 case nir_intrinsic_memory_barrier_shared
:
4121 case nir_intrinsic_memory_barrier_atomic_counter
:
4122 case nir_intrinsic_memory_barrier_buffer
:
4123 case nir_intrinsic_memory_barrier_image
:
4124 case nir_intrinsic_memory_barrier
: {
4125 bool l3_fence
, slm_fence
;
4126 if (devinfo
->gen
>= 11) {
4127 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4128 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4129 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4130 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4132 /* Prior to gen11, we only have one kind of fence. */
4137 /* Be conservative in Gen11+ and always stall in a fence. Since there
4138 * are two different fences, and shader might want to synchronize
4141 * TODO: Improve NIR so that scope and visibility information for the
4142 * barriers is available here to make a better decision.
4144 * TODO: When emitting more than one fence, it might help emit all
4145 * the fences first and then generate the stall moves.
4147 const bool stall
= devinfo
->gen
>= 11;
4149 const fs_builder ubld
= bld
.group(8, 0);
4150 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4153 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4154 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4155 /* bti */ brw_imm_ud(0))
4156 ->size_written
= 2 * REG_SIZE
;
4160 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4161 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4162 brw_imm_ud(GEN7_BTI_SLM
))
4163 ->size_written
= 2 * REG_SIZE
;
4169 case nir_intrinsic_shader_clock
: {
4170 /* We cannot do anything if there is an event, so ignore it for now */
4171 const fs_reg shader_clock
= get_timestamp(bld
);
4172 const fs_reg srcs
[] = { component(shader_clock
, 0),
4173 component(shader_clock
, 1) };
4174 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4178 case nir_intrinsic_image_samples
:
4179 /* The driver does not support multi-sampled images. */
4180 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4183 case nir_intrinsic_load_uniform
: {
4184 /* Offsets are in bytes but they should always aligned to
4187 assert(instr
->const_index
[0] % 4 == 0 ||
4188 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4190 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4192 if (nir_src_is_const(instr
->src
[0])) {
4193 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4194 assert(load_offset
% type_sz(dest
.type
) == 0);
4195 /* For 16-bit types we add the module of the const_index[0]
4196 * offset to access to not 32-bit aligned element
4198 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4200 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4201 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4204 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4205 BRW_REGISTER_TYPE_UD
);
4207 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4208 * go past the end of the uniform. In order to keep the n'th
4209 * component from running past, we subtract off the size of all but
4210 * one component of the vector.
4212 assert(instr
->const_index
[1] >=
4213 instr
->num_components
* (int) type_sz(dest
.type
));
4214 unsigned read_size
= instr
->const_index
[1] -
4215 (instr
->num_components
- 1) * type_sz(dest
.type
);
4217 bool supports_64bit_indirects
=
4218 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4220 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4221 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4222 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4223 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4224 indirect
, brw_imm_ud(read_size
));
4227 const unsigned num_mov_indirects
=
4228 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4229 /* We read a little bit less per MOV INDIRECT, as they are now
4230 * 32-bits ones instead of 64-bit. Fix read_size then.
4232 const unsigned read_size_32bit
= read_size
-
4233 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4234 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4235 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4236 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4237 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4238 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4239 indirect
, brw_imm_ud(read_size_32bit
));
4247 case nir_intrinsic_load_ubo
: {
4249 if (nir_src_is_const(instr
->src
[0])) {
4250 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4251 nir_src_as_uint(instr
->src
[0]);
4252 surf_index
= brw_imm_ud(index
);
4254 /* The block index is not a constant. Evaluate the index expression
4255 * per-channel and add the base UBO index; we have to select a value
4256 * from any live channel.
4258 surf_index
= vgrf(glsl_type::uint_type
);
4259 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4260 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4261 surf_index
= bld
.emit_uniformize(surf_index
);
4264 if (!nir_src_is_const(instr
->src
[1])) {
4265 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4266 BRW_REGISTER_TYPE_UD
);
4268 for (int i
= 0; i
< instr
->num_components
; i
++)
4269 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4270 base_offset
, i
* type_sz(dest
.type
));
4272 /* Even if we are loading doubles, a pull constant load will load
4273 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4274 * need to load a full dvec4 we will have to emit 2 loads. This is
4275 * similar to demote_pull_constants(), except that in that case we
4276 * see individual accesses to each component of the vector and then
4277 * we let CSE deal with duplicate loads. Here we see a vector access
4278 * and we have to split it if necessary.
4280 const unsigned type_size
= type_sz(dest
.type
);
4281 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4283 /* See if we've selected this as a push constant candidate */
4284 if (nir_src_is_const(instr
->src
[0])) {
4285 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4286 const unsigned offset_256b
= load_offset
/ 32;
4289 for (int i
= 0; i
< 4; i
++) {
4290 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4291 if (range
->block
== ubo_block
&&
4292 offset_256b
>= range
->start
&&
4293 offset_256b
< range
->start
+ range
->length
) {
4295 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4296 push_reg
.offset
= load_offset
- 32 * range
->start
;
4301 if (push_reg
.file
!= BAD_FILE
) {
4302 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4303 bld
.MOV(offset(dest
, bld
, i
),
4304 byte_offset(push_reg
, i
* type_size
));
4310 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4311 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4312 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4314 for (unsigned c
= 0; c
< instr
->num_components
;) {
4315 const unsigned base
= load_offset
+ c
* type_size
;
4316 /* Number of usable components in the next block-aligned load. */
4317 const unsigned count
= MIN2(instr
->num_components
- c
,
4318 (block_sz
- base
% block_sz
) / type_size
);
4320 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4321 packed_consts
, surf_index
,
4322 brw_imm_ud(base
& ~(block_sz
- 1)));
4324 const fs_reg consts
=
4325 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4328 for (unsigned d
= 0; d
< count
; d
++)
4329 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4337 case nir_intrinsic_load_global
: {
4338 assert(devinfo
->gen
>= 8);
4340 if (nir_intrinsic_align(instr
) >= 4) {
4341 assert(nir_dest_bit_size(instr
->dest
) == 32);
4342 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4344 get_nir_src(instr
->src
[0]), /* Address */
4345 fs_reg(), /* No source data */
4346 brw_imm_ud(instr
->num_components
));
4347 inst
->size_written
= instr
->num_components
*
4348 inst
->dst
.component_size(inst
->exec_size
);
4350 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4351 assert(bit_size
<= 32);
4352 assert(nir_dest_num_components(instr
->dest
) == 1);
4353 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4354 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4356 get_nir_src(instr
->src
[0]), /* Address */
4357 fs_reg(), /* No source data */
4358 brw_imm_ud(bit_size
));
4359 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4364 case nir_intrinsic_store_global
:
4365 assert(devinfo
->gen
>= 8);
4367 if (stage
== MESA_SHADER_FRAGMENT
)
4368 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4370 if (nir_intrinsic_align(instr
) >= 4) {
4371 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4372 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4374 get_nir_src(instr
->src
[1]), /* Address */
4375 get_nir_src(instr
->src
[0]), /* Data */
4376 brw_imm_ud(instr
->num_components
));
4378 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4379 assert(bit_size
<= 32);
4380 assert(nir_src_num_components(instr
->src
[0]) == 1);
4381 brw_reg_type data_type
=
4382 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4383 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4384 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4385 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4387 get_nir_src(instr
->src
[1]), /* Address */
4389 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4393 case nir_intrinsic_global_atomic_add
:
4394 case nir_intrinsic_global_atomic_imin
:
4395 case nir_intrinsic_global_atomic_umin
:
4396 case nir_intrinsic_global_atomic_imax
:
4397 case nir_intrinsic_global_atomic_umax
:
4398 case nir_intrinsic_global_atomic_and
:
4399 case nir_intrinsic_global_atomic_or
:
4400 case nir_intrinsic_global_atomic_xor
:
4401 case nir_intrinsic_global_atomic_exchange
:
4402 case nir_intrinsic_global_atomic_comp_swap
:
4403 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4405 case nir_intrinsic_global_atomic_fmin
:
4406 case nir_intrinsic_global_atomic_fmax
:
4407 case nir_intrinsic_global_atomic_fcomp_swap
:
4408 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4411 case nir_intrinsic_load_ssbo
: {
4412 assert(devinfo
->gen
>= 7);
4414 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4415 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4416 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4417 get_nir_ssbo_intrinsic_index(bld
, instr
);
4418 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4419 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4421 /* Make dest unsigned because that's what the temporary will be */
4422 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4424 /* Read the vector */
4425 if (nir_intrinsic_align(instr
) >= 4) {
4426 assert(nir_dest_bit_size(instr
->dest
) == 32);
4427 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4429 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4430 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4431 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4433 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4434 assert(nir_dest_num_components(instr
->dest
) == 1);
4435 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4437 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4438 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4439 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4440 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4445 case nir_intrinsic_store_ssbo
: {
4446 assert(devinfo
->gen
>= 7);
4448 if (stage
== MESA_SHADER_FRAGMENT
)
4449 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4451 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4452 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4453 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4454 get_nir_ssbo_intrinsic_index(bld
, instr
);
4455 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4456 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4458 fs_reg data
= get_nir_src(instr
->src
[0]);
4459 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4461 assert(nir_intrinsic_write_mask(instr
) ==
4462 (1u << instr
->num_components
) - 1);
4463 if (nir_intrinsic_align(instr
) >= 4) {
4464 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4465 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4466 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4467 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4468 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4469 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4471 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4472 assert(nir_src_num_components(instr
->src
[0]) == 1);
4473 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4475 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4476 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4478 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4479 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4484 case nir_intrinsic_store_output
: {
4485 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4486 fs_reg src
= get_nir_src(instr
->src
[0]);
4488 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4489 unsigned num_components
= instr
->num_components
;
4490 unsigned first_component
= nir_intrinsic_component(instr
);
4492 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4493 4 * store_offset
), src
.type
);
4494 for (unsigned j
= 0; j
< num_components
; j
++) {
4495 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4496 offset(src
, bld
, j
));
4501 case nir_intrinsic_ssbo_atomic_add
:
4502 case nir_intrinsic_ssbo_atomic_imin
:
4503 case nir_intrinsic_ssbo_atomic_umin
:
4504 case nir_intrinsic_ssbo_atomic_imax
:
4505 case nir_intrinsic_ssbo_atomic_umax
:
4506 case nir_intrinsic_ssbo_atomic_and
:
4507 case nir_intrinsic_ssbo_atomic_or
:
4508 case nir_intrinsic_ssbo_atomic_xor
:
4509 case nir_intrinsic_ssbo_atomic_exchange
:
4510 case nir_intrinsic_ssbo_atomic_comp_swap
:
4511 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4513 case nir_intrinsic_ssbo_atomic_fmin
:
4514 case nir_intrinsic_ssbo_atomic_fmax
:
4515 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4516 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4519 case nir_intrinsic_get_buffer_size
: {
4520 assert(nir_src_num_components(instr
->src
[0]) == 1);
4521 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4522 nir_src_as_uint(instr
->src
[0]) : 0;
4524 /* A resinfo's sampler message is used to get the buffer size. The
4525 * SIMD8's writeback message consists of four registers and SIMD16's
4526 * writeback message consists of 8 destination registers (two per each
4527 * component). Because we are only interested on the first channel of
4528 * the first returned component, where resinfo returns the buffer size
4529 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4530 * the dispatch width.
4532 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4533 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4534 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4537 ubld
.MOV(src_payload
, brw_imm_d(0));
4539 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4540 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4541 src_payload
, brw_imm_ud(index
));
4542 inst
->header_size
= 0;
4544 inst
->size_written
= 4 * REG_SIZE
;
4546 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4548 * "Out-of-bounds checking is always performed at a DWord granularity. If
4549 * any part of the DWord is out-of-bounds then the whole DWord is
4550 * considered out-of-bounds."
4552 * This implies that types with size smaller than 4-bytes need to be
4553 * padded if they don't complete the last dword of the buffer. But as we
4554 * need to maintain the original size we need to reverse the padding
4555 * calculation to return the correct size to know the number of elements
4556 * of an unsized array. As we stored in the last two bits of the surface
4557 * size the needed padding for the buffer, we calculate here the
4558 * original buffer_size reversing the surface_size calculation:
4560 * surface_size = isl_align(buffer_size, 4) +
4561 * (isl_align(buffer_size) - buffer_size)
4563 * buffer_size = surface_size & ~3 - surface_size & 3
4566 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4567 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4568 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4570 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4571 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4572 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4574 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4578 case nir_intrinsic_load_subgroup_size
:
4579 /* This should only happen for fragment shaders because every other case
4580 * is lowered in NIR so we can optimize on it.
4582 assert(stage
== MESA_SHADER_FRAGMENT
);
4583 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4586 case nir_intrinsic_load_subgroup_invocation
:
4587 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4588 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4591 case nir_intrinsic_load_subgroup_eq_mask
:
4592 case nir_intrinsic_load_subgroup_ge_mask
:
4593 case nir_intrinsic_load_subgroup_gt_mask
:
4594 case nir_intrinsic_load_subgroup_le_mask
:
4595 case nir_intrinsic_load_subgroup_lt_mask
:
4596 unreachable("not reached");
4598 case nir_intrinsic_vote_any
: {
4599 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4601 /* The any/all predicates do not consider channel enables. To prevent
4602 * dead channels from affecting the result, we initialize the flag with
4603 * with the identity value for the logical operation.
4605 if (dispatch_width
== 32) {
4606 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4607 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4610 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4612 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4614 /* For some reason, the any/all predicates don't work properly with
4615 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4616 * doesn't read the correct subset of the flag register and you end up
4617 * getting garbage in the second half. Work around this by using a pair
4618 * of 1-wide MOVs and scattering the result.
4620 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4621 ubld
.MOV(res1
, brw_imm_d(0));
4622 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4623 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4624 BRW_PREDICATE_ALIGN1_ANY32H
,
4625 ubld
.MOV(res1
, brw_imm_d(-1)));
4627 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4630 case nir_intrinsic_vote_all
: {
4631 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4633 /* The any/all predicates do not consider channel enables. To prevent
4634 * dead channels from affecting the result, we initialize the flag with
4635 * with the identity value for the logical operation.
4637 if (dispatch_width
== 32) {
4638 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4639 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4640 brw_imm_ud(0xffffffff));
4642 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4644 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4646 /* For some reason, the any/all predicates don't work properly with
4647 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4648 * doesn't read the correct subset of the flag register and you end up
4649 * getting garbage in the second half. Work around this by using a pair
4650 * of 1-wide MOVs and scattering the result.
4652 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4653 ubld
.MOV(res1
, brw_imm_d(0));
4654 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4655 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4656 BRW_PREDICATE_ALIGN1_ALL32H
,
4657 ubld
.MOV(res1
, brw_imm_d(-1)));
4659 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4662 case nir_intrinsic_vote_feq
:
4663 case nir_intrinsic_vote_ieq
: {
4664 fs_reg value
= get_nir_src(instr
->src
[0]);
4665 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4666 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4667 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4668 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4671 fs_reg uniformized
= bld
.emit_uniformize(value
);
4672 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4674 /* The any/all predicates do not consider channel enables. To prevent
4675 * dead channels from affecting the result, we initialize the flag with
4676 * with the identity value for the logical operation.
4678 if (dispatch_width
== 32) {
4679 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4680 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4681 brw_imm_ud(0xffffffff));
4683 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4685 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4687 /* For some reason, the any/all predicates don't work properly with
4688 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4689 * doesn't read the correct subset of the flag register and you end up
4690 * getting garbage in the second half. Work around this by using a pair
4691 * of 1-wide MOVs and scattering the result.
4693 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4694 ubld
.MOV(res1
, brw_imm_d(0));
4695 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4696 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4697 BRW_PREDICATE_ALIGN1_ALL32H
,
4698 ubld
.MOV(res1
, brw_imm_d(-1)));
4700 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4704 case nir_intrinsic_ballot
: {
4705 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4706 BRW_REGISTER_TYPE_UD
);
4707 struct brw_reg flag
= brw_flag_reg(0, 0);
4708 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4709 * as f0.0. This is a problem for fragment programs as we currently use
4710 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4711 * programs yet so this isn't a problem. When we do, something will
4714 if (dispatch_width
== 32)
4715 flag
.type
= BRW_REGISTER_TYPE_UD
;
4717 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4718 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4720 if (instr
->dest
.ssa
.bit_size
> 32) {
4721 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4723 dest
.type
= BRW_REGISTER_TYPE_UD
;
4725 bld
.MOV(dest
, flag
);
4729 case nir_intrinsic_read_invocation
: {
4730 const fs_reg value
= get_nir_src(instr
->src
[0]);
4731 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4732 fs_reg tmp
= bld
.vgrf(value
.type
);
4734 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4735 bld
.emit_uniformize(invocation
));
4737 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4741 case nir_intrinsic_read_first_invocation
: {
4742 const fs_reg value
= get_nir_src(instr
->src
[0]);
4743 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4747 case nir_intrinsic_shuffle
: {
4748 const fs_reg value
= get_nir_src(instr
->src
[0]);
4749 const fs_reg index
= get_nir_src(instr
->src
[1]);
4751 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4755 case nir_intrinsic_first_invocation
: {
4756 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4757 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4758 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4759 fs_reg(component(tmp
, 0)));
4763 case nir_intrinsic_quad_broadcast
: {
4764 const fs_reg value
= get_nir_src(instr
->src
[0]);
4765 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4767 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4768 value
, brw_imm_ud(index
), brw_imm_ud(4));
4772 case nir_intrinsic_quad_swap_horizontal
: {
4773 const fs_reg value
= get_nir_src(instr
->src
[0]);
4774 const fs_reg tmp
= bld
.vgrf(value
.type
);
4775 if (devinfo
->gen
<= 7) {
4776 /* The hardware doesn't seem to support these crazy regions with
4777 * compressed instructions on gen7 and earlier so we fall back to
4778 * using quad swizzles. Fortunately, we don't support 64-bit
4779 * anything in Vulkan on gen7.
4781 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4782 const fs_builder ubld
= bld
.exec_all();
4783 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4784 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
4785 bld
.MOV(retype(dest
, value
.type
), tmp
);
4787 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4789 const fs_reg src_left
= horiz_stride(value
, 2);
4790 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4791 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4792 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4794 ubld
.MOV(tmp_left
, src_right
);
4795 ubld
.MOV(tmp_right
, src_left
);
4798 bld
.MOV(retype(dest
, value
.type
), tmp
);
4802 case nir_intrinsic_quad_swap_vertical
: {
4803 const fs_reg value
= get_nir_src(instr
->src
[0]);
4804 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4805 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4806 const fs_reg tmp
= bld
.vgrf(value
.type
);
4807 const fs_builder ubld
= bld
.exec_all();
4808 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4809 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4810 bld
.MOV(retype(dest
, value
.type
), tmp
);
4812 /* For larger data types, we have to either emit dispatch_width many
4813 * MOVs or else fall back to doing indirects.
4815 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4816 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4818 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4823 case nir_intrinsic_quad_swap_diagonal
: {
4824 const fs_reg value
= get_nir_src(instr
->src
[0]);
4825 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4826 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4827 const fs_reg tmp
= bld
.vgrf(value
.type
);
4828 const fs_builder ubld
= bld
.exec_all();
4829 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4830 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4831 bld
.MOV(retype(dest
, value
.type
), tmp
);
4833 /* For larger data types, we have to either emit dispatch_width many
4834 * MOVs or else fall back to doing indirects.
4836 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4837 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4839 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4844 case nir_intrinsic_reduce
: {
4845 fs_reg src
= get_nir_src(instr
->src
[0]);
4846 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4847 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4848 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4849 cluster_size
= dispatch_width
;
4851 /* Figure out the source type */
4852 src
.type
= brw_type_for_nir_type(devinfo
,
4853 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4854 nir_src_bit_size(instr
->src
[0])));
4856 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4857 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4858 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4860 /* Set up a register for all of our scratching around and initialize it
4861 * to reduction operation's identity value.
4863 fs_reg scan
= bld
.vgrf(src
.type
);
4864 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4866 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4868 dest
.type
= src
.type
;
4869 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4870 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4871 * the distance between clusters is at least 2 GRFs. In this case,
4872 * we don't need the weird striding of the CLUSTER_BROADCAST
4873 * instruction and can just do regular MOVs.
4875 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4876 const unsigned groups
=
4877 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4878 const unsigned group_size
= dispatch_width
/ groups
;
4879 for (unsigned i
= 0; i
< groups
; i
++) {
4880 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4881 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4882 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4883 component(scan
, comp
));
4886 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4887 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4892 case nir_intrinsic_inclusive_scan
:
4893 case nir_intrinsic_exclusive_scan
: {
4894 fs_reg src
= get_nir_src(instr
->src
[0]);
4895 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4897 /* Figure out the source type */
4898 src
.type
= brw_type_for_nir_type(devinfo
,
4899 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4900 nir_src_bit_size(instr
->src
[0])));
4902 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4903 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4904 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4906 /* Set up a register for all of our scratching around and initialize it
4907 * to reduction operation's identity value.
4909 fs_reg scan
= bld
.vgrf(src
.type
);
4910 const fs_builder allbld
= bld
.exec_all();
4911 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4913 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4914 /* Exclusive scan is a bit harder because we have to do an annoying
4915 * shift of the contents before we can begin. To make things worse,
4916 * we can't do this with a normal stride; we have to use indirects.
4918 fs_reg shifted
= bld
.vgrf(src
.type
);
4919 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4920 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4922 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4923 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4927 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4929 bld
.MOV(retype(dest
, src
.type
), scan
);
4933 case nir_intrinsic_begin_invocation_interlock
: {
4934 const fs_builder ubld
= bld
.group(8, 0);
4935 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4937 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
4938 ->size_written
= 2 * REG_SIZE
;
4942 case nir_intrinsic_end_invocation_interlock
: {
4943 /* For endInvocationInterlock(), we need to insert a memory fence which
4944 * stalls in the shader until the memory transactions prior to that
4945 * fence are complete. This ensures that the shader does not end before
4946 * any writes from its critical section have landed. Otherwise, you can
4947 * end up with a case where the next invocation on that pixel properly
4948 * stalls for previous FS invocation on its pixel to complete but
4949 * doesn't actually wait for the dataport memory transactions from that
4950 * thread to land before submitting its own.
4952 const fs_builder ubld
= bld
.group(8, 0);
4953 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4954 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4955 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
4956 ->size_written
= 2 * REG_SIZE
;
4961 unreachable("unknown intrinsic");
4966 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4967 int op
, nir_intrinsic_instr
*instr
)
4969 if (stage
== MESA_SHADER_FRAGMENT
)
4970 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4972 /* The BTI untyped atomic messages only support 32-bit atomics. If you
4973 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
4974 * appear to exist. However, if you look at Vol 2a, there are no message
4975 * descriptors provided for Qword atomic ops except for A64 messages.
4977 assert(nir_dest_bit_size(instr
->dest
) == 32);
4980 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4981 dest
= get_nir_dest(instr
->dest
);
4983 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4984 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4985 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4986 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4987 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4990 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4991 data
= get_nir_src(instr
->src
[2]);
4993 if (op
== BRW_AOP_CMPWR
) {
4994 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4995 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4996 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4999 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5001 /* Emit the actual atomic operation */
5003 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5004 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5008 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5009 int op
, nir_intrinsic_instr
*instr
)
5011 if (stage
== MESA_SHADER_FRAGMENT
)
5012 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5015 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5016 dest
= get_nir_dest(instr
->dest
);
5018 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5019 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5020 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5021 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5022 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5024 fs_reg data
= get_nir_src(instr
->src
[2]);
5025 if (op
== BRW_AOP_FCMPWR
) {
5026 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5027 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5028 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5031 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5033 /* Emit the actual atomic operation */
5035 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5036 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5040 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5041 int op
, nir_intrinsic_instr
*instr
)
5044 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5045 dest
= get_nir_dest(instr
->dest
);
5047 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5048 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5049 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5050 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5053 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5054 data
= get_nir_src(instr
->src
[1]);
5055 if (op
== BRW_AOP_CMPWR
) {
5056 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5057 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5058 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5061 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5063 /* Get the offset */
5064 if (nir_src_is_const(instr
->src
[0])) {
5065 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5066 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5068 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5069 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5070 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5071 brw_imm_ud(instr
->const_index
[0]));
5074 /* Emit the actual atomic operation operation */
5076 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5077 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5081 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5082 int op
, nir_intrinsic_instr
*instr
)
5085 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5086 dest
= get_nir_dest(instr
->dest
);
5088 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5089 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5090 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5091 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5093 fs_reg data
= get_nir_src(instr
->src
[1]);
5094 if (op
== BRW_AOP_FCMPWR
) {
5095 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5096 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5097 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5100 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5102 /* Get the offset */
5103 if (nir_src_is_const(instr
->src
[0])) {
5104 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5105 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5107 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5108 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5109 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5110 brw_imm_ud(instr
->const_index
[0]));
5113 /* Emit the actual atomic operation operation */
5115 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5116 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5120 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5121 int op
, nir_intrinsic_instr
*instr
)
5123 if (stage
== MESA_SHADER_FRAGMENT
)
5124 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5127 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5128 dest
= get_nir_dest(instr
->dest
);
5130 fs_reg addr
= get_nir_src(instr
->src
[0]);
5133 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5134 data
= get_nir_src(instr
->src
[1]);
5136 if (op
== BRW_AOP_CMPWR
) {
5137 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5138 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5139 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5143 if (nir_dest_bit_size(instr
->dest
) == 64) {
5144 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5145 dest
, addr
, data
, brw_imm_ud(op
));
5147 assert(nir_dest_bit_size(instr
->dest
) == 32);
5148 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5149 dest
, addr
, data
, brw_imm_ud(op
));
5154 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5155 int op
, nir_intrinsic_instr
*instr
)
5157 if (stage
== MESA_SHADER_FRAGMENT
)
5158 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5160 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5161 fs_reg dest
= get_nir_dest(instr
->dest
);
5163 fs_reg addr
= get_nir_src(instr
->src
[0]);
5165 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5166 fs_reg data
= get_nir_src(instr
->src
[1]);
5168 if (op
== BRW_AOP_FCMPWR
) {
5169 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5170 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5171 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5175 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5176 dest
, addr
, data
, brw_imm_ud(op
));
5180 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5182 unsigned texture
= instr
->texture_index
;
5183 unsigned sampler
= instr
->sampler_index
;
5185 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5187 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5188 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5190 int lod_components
= 0;
5192 /* The hardware requires a LOD for buffer textures */
5193 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5194 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5196 uint32_t header_bits
= 0;
5197 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5198 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5199 switch (instr
->src
[i
].src_type
) {
5200 case nir_tex_src_bias
:
5201 srcs
[TEX_LOGICAL_SRC_LOD
] =
5202 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5204 case nir_tex_src_comparator
:
5205 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5207 case nir_tex_src_coord
:
5208 switch (instr
->op
) {
5210 case nir_texop_txf_ms
:
5211 case nir_texop_txf_ms_mcs
:
5212 case nir_texop_samples_identical
:
5213 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5216 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5220 case nir_tex_src_ddx
:
5221 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5222 lod_components
= nir_tex_instr_src_size(instr
, i
);
5224 case nir_tex_src_ddy
:
5225 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5227 case nir_tex_src_lod
:
5228 switch (instr
->op
) {
5230 srcs
[TEX_LOGICAL_SRC_LOD
] =
5231 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5234 srcs
[TEX_LOGICAL_SRC_LOD
] =
5235 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5238 srcs
[TEX_LOGICAL_SRC_LOD
] =
5239 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5243 case nir_tex_src_min_lod
:
5244 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5245 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5247 case nir_tex_src_ms_index
:
5248 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5251 case nir_tex_src_offset
: {
5252 uint32_t offset_bits
= 0;
5253 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5254 header_bits
|= offset_bits
;
5256 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5257 retype(src
, BRW_REGISTER_TYPE_D
);
5262 case nir_tex_src_projector
:
5263 unreachable("should be lowered");
5265 case nir_tex_src_texture_offset
: {
5266 /* Emit code to evaluate the actual indexing expression */
5267 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5268 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5269 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5273 case nir_tex_src_sampler_offset
: {
5274 /* Emit code to evaluate the actual indexing expression */
5275 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5276 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5277 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5281 case nir_tex_src_texture_handle
:
5282 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5283 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5284 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5287 case nir_tex_src_sampler_handle
:
5288 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5289 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5290 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5293 case nir_tex_src_ms_mcs
:
5294 assert(instr
->op
== nir_texop_txf_ms
);
5295 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5298 case nir_tex_src_plane
: {
5299 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5300 const uint32_t texture_index
=
5301 instr
->texture_index
+
5302 stage_prog_data
->binding_table
.plane_start
[plane
] -
5303 stage_prog_data
->binding_table
.texture_start
;
5305 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5310 unreachable("unknown texture source");
5314 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5315 (instr
->op
== nir_texop_txf_ms
||
5316 instr
->op
== nir_texop_samples_identical
)) {
5317 if (devinfo
->gen
>= 7 &&
5318 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5319 srcs
[TEX_LOGICAL_SRC_MCS
] =
5320 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5321 instr
->coord_components
,
5322 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5323 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5325 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5329 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5330 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5333 switch (instr
->op
) {
5335 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5338 opcode
= FS_OPCODE_TXB_LOGICAL
;
5341 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5344 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5347 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5349 case nir_texop_txf_ms
:
5350 if ((key_tex
->msaa_16
& (1 << sampler
)))
5351 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5353 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5355 case nir_texop_txf_ms_mcs
:
5356 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5358 case nir_texop_query_levels
:
5360 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5363 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5366 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5367 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5369 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5371 case nir_texop_texture_samples
:
5372 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5374 case nir_texop_samples_identical
: {
5375 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5377 /* If mcs is an immediate value, it means there is no MCS. In that case
5378 * just return false.
5380 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5381 bld
.MOV(dst
, brw_imm_ud(0u));
5382 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5383 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5384 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5385 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5386 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5388 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5389 BRW_CONDITIONAL_EQ
);
5394 unreachable("unknown texture opcode");
5397 if (instr
->op
== nir_texop_tg4
) {
5398 if (instr
->component
== 1 &&
5399 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5400 /* gather4 sampler is broken for green channel on RG32F --
5401 * we must ask for blue instead.
5403 header_bits
|= 2 << 16;
5405 header_bits
|= instr
->component
<< 16;
5409 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5410 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5411 inst
->offset
= header_bits
;
5413 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5414 if (devinfo
->gen
>= 9 &&
5415 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5416 unsigned write_mask
= instr
->dest
.is_ssa
?
5417 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5418 (1 << dest_size
) - 1;
5419 assert(write_mask
!= 0); /* dead code should have been eliminated */
5420 inst
->size_written
= util_last_bit(write_mask
) *
5421 inst
->dst
.component_size(inst
->exec_size
);
5423 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5426 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5427 inst
->shadow_compare
= true;
5429 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5430 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5433 for (unsigned i
= 0; i
< dest_size
; i
++)
5434 nir_dest
[i
] = offset(dst
, bld
, i
);
5436 if (instr
->op
== nir_texop_query_levels
) {
5437 /* # levels is in .w */
5438 nir_dest
[0] = offset(dst
, bld
, 3);
5439 } else if (instr
->op
== nir_texop_txs
&&
5440 dest_size
>= 3 && devinfo
->gen
< 7) {
5441 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5442 fs_reg depth
= offset(dst
, bld
, 2);
5443 nir_dest
[2] = vgrf(glsl_type::int_type
);
5444 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5447 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5451 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5453 switch (instr
->type
) {
5454 case nir_jump_break
:
5455 bld
.emit(BRW_OPCODE_BREAK
);
5457 case nir_jump_continue
:
5458 bld
.emit(BRW_OPCODE_CONTINUE
);
5460 case nir_jump_return
:
5462 unreachable("unknown jump");
5467 * This helper takes a source register and un/shuffles it into the destination
5470 * If source type size is smaller than destination type size the operation
5471 * needed is a component shuffle. The opposite case would be an unshuffle. If
5472 * source/destination type size is equal a shuffle is done that would be
5473 * equivalent to a simple MOV.
5475 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5476 * components .xyz 16-bit vector on SIMD8 would be.
5478 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5479 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5481 * This helper will return the following 2 32-bit components with the 16-bit
5484 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5485 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5487 * For unshuffle, the example would be the opposite, a 64-bit type source
5488 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5491 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5492 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5493 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5494 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5496 * The returned result would be the following 4 32-bit components unshuffled:
5498 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5499 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5500 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5501 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5503 * - Source and destination register must not be overlapped.
5504 * - components units are measured in terms of the smaller type between
5505 * source and destination because we are un/shuffling the smaller
5506 * components from/into the bigger ones.
5507 * - first_component parameter allows skipping source components.
5510 shuffle_src_to_dst(const fs_builder
&bld
,
5513 uint32_t first_component
,
5514 uint32_t components
)
5516 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5517 assert(!regions_overlap(dst
,
5518 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5519 offset(src
, bld
, first_component
),
5520 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5521 for (unsigned i
= 0; i
< components
; i
++) {
5522 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5523 offset(src
, bld
, i
+ first_component
));
5525 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5526 /* Source is shuffled into destination */
5527 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5528 assert(!regions_overlap(dst
,
5529 type_sz(dst
.type
) * bld
.dispatch_width() *
5530 DIV_ROUND_UP(components
, size_ratio
),
5531 offset(src
, bld
, first_component
),
5532 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5534 brw_reg_type shuffle_type
=
5535 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5536 BRW_REGISTER_TYPE_D
);
5537 for (unsigned i
= 0; i
< components
; i
++) {
5538 fs_reg shuffle_component_i
=
5539 subscript(offset(dst
, bld
, i
/ size_ratio
),
5540 shuffle_type
, i
% size_ratio
);
5541 bld
.MOV(shuffle_component_i
,
5542 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5545 /* Source is unshuffled into destination */
5546 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5547 assert(!regions_overlap(dst
,
5548 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5549 offset(src
, bld
, first_component
/ size_ratio
),
5550 type_sz(src
.type
) * bld
.dispatch_width() *
5551 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5554 brw_reg_type shuffle_type
=
5555 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5556 BRW_REGISTER_TYPE_D
);
5557 for (unsigned i
= 0; i
< components
; i
++) {
5558 fs_reg shuffle_component_i
=
5559 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5560 shuffle_type
, (first_component
+ i
) % size_ratio
);
5561 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5562 shuffle_component_i
);
5568 shuffle_from_32bit_read(const fs_builder
&bld
,
5571 uint32_t first_component
,
5572 uint32_t components
)
5574 assert(type_sz(src
.type
) == 4);
5576 /* This function takes components in units of the destination type while
5577 * shuffle_src_to_dst takes components in units of the smallest type
5579 if (type_sz(dst
.type
) > 4) {
5580 assert(type_sz(dst
.type
) == 8);
5581 first_component
*= 2;
5585 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5589 setup_imm_df(const fs_builder
&bld
, double v
)
5591 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5592 assert(devinfo
->gen
>= 7);
5594 if (devinfo
->gen
>= 8)
5595 return brw_imm_df(v
);
5597 /* gen7.5 does not support DF immediates straighforward but the DIM
5598 * instruction allows to set the 64-bit immediate value.
5600 if (devinfo
->is_haswell
) {
5601 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5602 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5603 ubld
.DIM(dst
, brw_imm_df(v
));
5604 return component(dst
, 0);
5607 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5608 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5609 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5611 * Alternatively, we could also produce a normal VGRF (without stride 0)
5612 * by writing to all the channels in the VGRF, however, that would hit the
5613 * gen7 bug where we have to split writes that span more than 1 register
5614 * into instructions with a width of 4 (otherwise the write to the second
5615 * register written runs into an execmask hardware bug) which isn't very
5628 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5629 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5630 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5631 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5633 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5637 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5639 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5640 bld
.MOV(tmp
, brw_imm_w(v
));
5645 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5647 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5648 bld
.MOV(tmp
, brw_imm_uw(v
));