2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
46 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
50 fs_visitor::nir_setup_outputs()
52 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
55 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
57 /* Calculate the size of output registers in a separate pass, before
58 * allocating them. With ARB_enhanced_layouts, multiple output variables
59 * may occupy the same slot, but have different type sizes.
61 nir_foreach_variable(var
, &nir
->outputs
) {
62 const int loc
= var
->data
.driver_location
;
63 const unsigned var_vec4s
=
64 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
65 : type_size_vec4(var
->type
, true);
66 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
69 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
70 if (vec4s
[loc
] == 0) {
75 unsigned reg_size
= vec4s
[loc
];
77 /* Check if there are any ranges that start within this range and extend
78 * past it. If so, include them in this allocation.
80 for (unsigned i
= 1; i
< reg_size
; i
++)
81 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
83 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
84 for (unsigned i
= 0; i
< reg_size
; i
++)
85 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
92 fs_visitor::nir_setup_uniforms()
94 /* Only the first compile gets to set up uniforms. */
95 if (push_constant_loc
) {
96 assert(pull_constant_loc
);
100 uniforms
= nir
->num_uniforms
/ 4;
102 if (stage
== MESA_SHADER_COMPUTE
) {
103 /* Add a uniform for the thread local id. It must be the last uniform
106 assert(uniforms
== prog_data
->nr_params
);
107 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
108 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
109 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
114 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
118 nir_foreach_instr(instr
, block
) {
119 if (instr
->type
!= nir_instr_type_intrinsic
)
122 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
123 switch (intrin
->intrinsic
) {
124 case nir_intrinsic_load_vertex_id
:
125 case nir_intrinsic_load_base_vertex
:
126 unreachable("should be lowered by nir_lower_system_values().");
128 case nir_intrinsic_load_vertex_id_zero_base
:
129 case nir_intrinsic_load_is_indexed_draw
:
130 case nir_intrinsic_load_first_vertex
:
131 case nir_intrinsic_load_instance_id
:
132 case nir_intrinsic_load_base_instance
:
133 case nir_intrinsic_load_draw_id
:
134 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
136 case nir_intrinsic_load_invocation_id
:
137 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
139 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
141 if (reg
->file
== BAD_FILE
) {
142 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
143 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
144 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
145 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
150 case nir_intrinsic_load_sample_pos
:
151 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
152 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
153 if (reg
->file
== BAD_FILE
)
154 *reg
= *v
->emit_samplepos_setup();
157 case nir_intrinsic_load_sample_id
:
158 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
159 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
160 if (reg
->file
== BAD_FILE
)
161 *reg
= *v
->emit_sampleid_setup();
164 case nir_intrinsic_load_sample_mask_in
:
165 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
166 assert(v
->devinfo
->gen
>= 7);
167 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
168 if (reg
->file
== BAD_FILE
)
169 *reg
= *v
->emit_samplemaskin_setup();
172 case nir_intrinsic_load_work_group_id
:
173 assert(v
->stage
== MESA_SHADER_COMPUTE
);
174 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
175 if (reg
->file
== BAD_FILE
)
176 *reg
= *v
->emit_cs_work_group_id_setup();
179 case nir_intrinsic_load_helper_invocation
:
180 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
182 if (reg
->file
== BAD_FILE
) {
183 const fs_builder abld
=
184 v
->bld
.annotate("gl_HelperInvocation", NULL
);
186 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
187 * pixel mask is in g1.7 of the thread payload.
189 * We move the per-channel pixel enable bit to the low bit of each
190 * channel by shifting the byte containing the pixel mask by the
191 * vector immediate 0x76543210UV.
193 * The region of <1,8,0> reads only 1 byte (the pixel masks for
194 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
195 * masks for 2 and 3) in SIMD16.
197 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
199 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
200 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
201 hbld
.SHR(offset(shifted
, hbld
, i
),
202 stride(retype(brw_vec1_grf(1 + i
, 7),
203 BRW_REGISTER_TYPE_UB
),
205 brw_imm_v(0x76543210));
208 /* A set bit in the pixel mask means the channel is enabled, but
209 * that is the opposite of gl_HelperInvocation so we need to invert
212 * The negate source-modifier bit of logical instructions on Gen8+
213 * performs 1's complement negation, so we can use that instead of
216 fs_reg inverted
= negate(shifted
);
217 if (v
->devinfo
->gen
< 8) {
218 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
219 abld
.NOT(inverted
, shifted
);
222 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
223 * with 1 and negating.
225 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
226 abld
.AND(anded
, inverted
, brw_imm_uw(1));
228 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
229 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
243 fs_visitor::nir_emit_system_values()
245 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
246 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
247 nir_system_values
[i
] = fs_reg();
250 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
251 * never end up using it.
254 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
255 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
256 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
258 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
259 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
260 if (dispatch_width
> 8)
261 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
262 if (dispatch_width
> 16) {
263 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
264 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
268 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
269 nir_foreach_block(block
, impl
)
270 emit_system_values_block(block
, this);
274 * Returns a type based on a reference_type (word, float, half-float) and a
277 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
279 * @FIXME: 64-bit return types are always DF on integer types to maintain
280 * compability with uses of DF previously to the introduction of int64
284 brw_reg_type_from_bit_size(const unsigned bit_size
,
285 const brw_reg_type reference_type
)
287 switch(reference_type
) {
288 case BRW_REGISTER_TYPE_HF
:
289 case BRW_REGISTER_TYPE_F
:
290 case BRW_REGISTER_TYPE_DF
:
293 return BRW_REGISTER_TYPE_HF
;
295 return BRW_REGISTER_TYPE_F
;
297 return BRW_REGISTER_TYPE_DF
;
299 unreachable("Invalid bit size");
301 case BRW_REGISTER_TYPE_B
:
302 case BRW_REGISTER_TYPE_W
:
303 case BRW_REGISTER_TYPE_D
:
304 case BRW_REGISTER_TYPE_Q
:
307 return BRW_REGISTER_TYPE_B
;
309 return BRW_REGISTER_TYPE_W
;
311 return BRW_REGISTER_TYPE_D
;
313 return BRW_REGISTER_TYPE_Q
;
315 unreachable("Invalid bit size");
317 case BRW_REGISTER_TYPE_UB
:
318 case BRW_REGISTER_TYPE_UW
:
319 case BRW_REGISTER_TYPE_UD
:
320 case BRW_REGISTER_TYPE_UQ
:
323 return BRW_REGISTER_TYPE_UB
;
325 return BRW_REGISTER_TYPE_UW
;
327 return BRW_REGISTER_TYPE_UD
;
329 return BRW_REGISTER_TYPE_UQ
;
331 unreachable("Invalid bit size");
334 unreachable("Unknown type");
339 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
341 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
342 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
343 nir_locals
[i
] = fs_reg();
346 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
347 unsigned array_elems
=
348 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
349 unsigned size
= array_elems
* reg
->num_components
;
350 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
351 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
352 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
355 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
358 nir_emit_cf_list(&impl
->body
);
362 fs_visitor::nir_emit_cf_list(exec_list
*list
)
364 exec_list_validate(list
);
365 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
366 switch (node
->type
) {
368 nir_emit_if(nir_cf_node_as_if(node
));
371 case nir_cf_node_loop
:
372 nir_emit_loop(nir_cf_node_as_loop(node
));
375 case nir_cf_node_block
:
376 nir_emit_block(nir_cf_node_as_block(node
));
380 unreachable("Invalid CFG node block");
386 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
391 /* If the condition has the form !other_condition, use other_condition as
392 * the source, but invert the predicate on the if instruction.
394 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
395 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
396 assert(!cond
->src
[0].negate
);
397 assert(!cond
->src
[0].abs
);
400 cond_reg
= get_nir_src(cond
->src
[0].src
);
403 cond_reg
= get_nir_src(if_stmt
->condition
);
406 /* first, put the condition into f0 */
407 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
408 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
411 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
413 nir_emit_cf_list(&if_stmt
->then_list
);
415 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
416 bld
.emit(BRW_OPCODE_ELSE
);
417 nir_emit_cf_list(&if_stmt
->else_list
);
420 bld
.emit(BRW_OPCODE_ENDIF
);
422 if (devinfo
->gen
< 7)
423 limit_dispatch_width(16, "Non-uniform control flow unsupported "
428 fs_visitor::nir_emit_loop(nir_loop
*loop
)
430 bld
.emit(BRW_OPCODE_DO
);
432 nir_emit_cf_list(&loop
->body
);
434 bld
.emit(BRW_OPCODE_WHILE
);
436 if (devinfo
->gen
< 7)
437 limit_dispatch_width(16, "Non-uniform control flow unsupported "
442 fs_visitor::nir_emit_block(nir_block
*block
)
444 nir_foreach_instr(instr
, block
) {
445 nir_emit_instr(instr
);
450 fs_visitor::nir_emit_instr(nir_instr
*instr
)
452 const fs_builder abld
= bld
.annotate(NULL
, instr
);
454 switch (instr
->type
) {
455 case nir_instr_type_alu
:
456 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
459 case nir_instr_type_deref
:
460 unreachable("All derefs should've been lowered");
463 case nir_instr_type_intrinsic
:
465 case MESA_SHADER_VERTEX
:
466 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_TESS_CTRL
:
469 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_TESS_EVAL
:
472 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_GEOMETRY
:
475 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
477 case MESA_SHADER_FRAGMENT
:
478 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 case MESA_SHADER_COMPUTE
:
481 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
484 unreachable("unsupported shader stage");
488 case nir_instr_type_tex
:
489 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
492 case nir_instr_type_load_const
:
493 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
496 case nir_instr_type_ssa_undef
:
497 /* We create a new VGRF for undefs on every use (by handling
498 * them in get_nir_src()), rather than for each definition.
499 * This helps register coalescing eliminate MOVs from undef.
503 case nir_instr_type_jump
:
504 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
508 unreachable("unknown instruction type");
513 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
517 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
518 const fs_reg
&result
)
520 if (!instr
->src
[0].src
.is_ssa
||
521 !instr
->src
[0].src
.ssa
->parent_instr
)
524 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
527 nir_alu_instr
*src0
=
528 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
530 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
531 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
534 /* If either opcode has source modifiers, bail.
536 * TODO: We can potentially handle source modifiers if both of the opcodes
537 * we're combining are signed integers.
539 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
540 src0
->src
[0].abs
|| src0
->src
[0].negate
)
543 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
545 /* Element type to extract.*/
546 const brw_reg_type type
= brw_int_type(
547 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
548 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
550 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
551 op0
.type
= brw_type_for_nir_type(devinfo
,
552 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
553 nir_src_bit_size(src0
->src
[0].src
)));
554 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
556 set_saturate(instr
->dest
.saturate
,
557 bld
.MOV(result
, subscript(op0
, type
, element
)));
562 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
563 const fs_reg
&result
)
565 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
566 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
569 if (!nir_src_is_const(instr
->src
[1].src
) ||
570 !nir_src_is_const(instr
->src
[2].src
))
573 const float value1
= nir_src_as_float(instr
->src
[1].src
);
574 const float value2
= nir_src_as_float(instr
->src
[2].src
);
575 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
578 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
579 assert(value1
== -value2
);
581 fs_reg tmp
= vgrf(glsl_type::int_type
);
583 if (devinfo
->gen
>= 12) {
584 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
585 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
587 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
589 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
590 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
592 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
594 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
595 g1
, brw_imm_uw(0x3f80));
598 bld
.MOV(tmp
, negate(tmp
));
600 } else if (devinfo
->gen
>= 6) {
601 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
602 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
604 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
606 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
607 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
609 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
611 * This negation looks like it's safe in practice, because bits 0:4 will
612 * surely be TRIANGLES
615 if (value1
== -1.0f
) {
619 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
620 g0
, brw_imm_uw(0x3f80));
622 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
623 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
625 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
627 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
628 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
630 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
632 * This negation looks like it's safe in practice, because bits 0:4 will
633 * surely be TRIANGLES
636 if (value1
== -1.0f
) {
640 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
642 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
648 emit_find_msb_using_lzd(const fs_builder
&bld
,
649 const fs_reg
&result
,
657 /* LZD of an absolute value source almost always does the right
658 * thing. There are two problem values:
660 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
661 * 0. However, findMSB(int(0x80000000)) == 30.
663 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
664 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
666 * For a value of zero or negative one, -1 will be returned.
668 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
669 * findMSB(-(1<<x)) should return x-1.
671 * For all negative number cases, including 0x80000000 and
672 * 0xffffffff, the correct value is obtained from LZD if instead of
673 * negating the (already negative) value the logical-not is used. A
674 * conditonal logical-not can be achieved in two instructions.
676 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
678 bld
.ASR(temp
, src
, brw_imm_d(31));
679 bld
.XOR(temp
, temp
, src
);
682 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
683 retype(temp
, BRW_REGISTER_TYPE_UD
));
685 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
686 * from the LSB side. Subtract the result from 31 to convert the MSB
687 * count into an LSB count. If no bits are set, LZD will return 32.
688 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
690 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
691 inst
->src
[0].negate
= true;
695 brw_rnd_mode_from_nir_op (const nir_op op
) {
697 case nir_op_f2f16_rtz
:
698 return BRW_RND_MODE_RTZ
;
699 case nir_op_f2f16_rtne
:
700 return BRW_RND_MODE_RTNE
;
702 unreachable("Operation doesn't support rounding mode");
707 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
709 if (nir_has_any_rounding_mode_rtne(execution_mode
))
710 return BRW_RND_MODE_RTNE
;
711 if (nir_has_any_rounding_mode_rtz(execution_mode
))
712 return BRW_RND_MODE_RTZ
;
713 return BRW_RND_MODE_UNSPECIFIED
;
717 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
718 nir_alu_instr
*instr
,
723 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
725 result
.type
= brw_type_for_nir_type(devinfo
,
726 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
727 nir_dest_bit_size(instr
->dest
.dest
)));
729 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
730 op
[i
] = get_nir_src(instr
->src
[i
].src
);
731 op
[i
].type
= brw_type_for_nir_type(devinfo
,
732 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
733 nir_src_bit_size(instr
->src
[i
].src
)));
734 op
[i
].abs
= instr
->src
[i
].abs
;
735 op
[i
].negate
= instr
->src
[i
].negate
;
738 /* Move and vecN instrutions may still be vectored. Return the raw,
739 * vectored source and destination so that fs_visitor::nir_emit_alu can
740 * handle it. Other callers should not have to handle these kinds of
753 /* At this point, we have dealt with any instruction that operates on
754 * more than a single channel. Therefore, we can just adjust the source
755 * and destination registers for that channel and emit the instruction.
757 unsigned channel
= 0;
758 if (nir_op_infos
[instr
->op
].output_size
== 0) {
759 /* Since NIR is doing the scalarizing for us, we should only ever see
760 * vectorized operations with a single channel.
762 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
763 channel
= ffs(instr
->dest
.write_mask
) - 1;
765 result
= offset(result
, bld
, channel
);
768 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
769 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
770 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
777 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
780 for (unsigned i
= 0; i
< 2; i
++) {
781 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
783 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
784 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
785 /* The source of the inot is now the source of instr. */
786 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
788 assert(!op
[i
].negate
);
791 op
[i
] = resolve_source_modifiers(op
[i
]);
797 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
799 nir_alu_instr
*instr
)
801 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
804 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
806 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
809 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
810 * of valid size-changing combinations is a bit more complex.
812 * The source restriction is just because I was lazy about generating the
815 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
816 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
819 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
820 * this is float(1 + a).
824 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
826 /* Ignore the saturate modifier, if there is one. The result of the
827 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
829 bld
.ADD(result
, op
, brw_imm_d(1));
835 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
837 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
838 * the source of \c instr that is a \c nir_op_fsign.
841 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
842 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
846 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
847 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
849 if (instr
->op
!= nir_op_fsign
) {
850 const nir_alu_instr
*const fsign_instr
=
851 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
853 assert(!fsign_instr
->dest
.saturate
);
855 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
856 * fsign_src] has the other multiply source. This must be rearranged so
857 * that op[0] is the source of the fsign op[1] is the other multiply
863 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
865 const nir_alu_type t
=
866 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
867 nir_src_bit_size(fsign_instr
->src
[0].src
));
869 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
870 op
[0].abs
= fsign_instr
->src
[0].abs
;
871 op
[0].negate
= fsign_instr
->src
[0].negate
;
873 unsigned channel
= 0;
874 if (nir_op_infos
[instr
->op
].output_size
== 0) {
875 /* Since NIR is doing the scalarizing for us, we should only ever see
876 * vectorized operations with a single channel.
878 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
879 channel
= ffs(instr
->dest
.write_mask
) - 1;
882 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
884 assert(!instr
->dest
.saturate
);
888 /* Straightforward since the source can be assumed to be either strictly
889 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
891 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
893 if (instr
->op
== nir_op_fsign
) {
894 inst
= (op
[0].negate
)
895 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
896 : bld
.MOV(result
, brw_imm_f(1.0f
));
898 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
899 inst
= bld
.MOV(result
, op
[1]);
902 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
903 } else if (type_sz(op
[0].type
) == 2) {
904 /* AND(val, 0x8000) gives the sign bit.
906 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
908 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
909 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
911 op
[0].type
= BRW_REGISTER_TYPE_UW
;
912 result
.type
= BRW_REGISTER_TYPE_UW
;
913 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
915 if (instr
->op
== nir_op_fsign
)
916 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
918 /* Use XOR here to get the result sign correct. */
919 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
922 inst
->predicate
= BRW_PREDICATE_NORMAL
;
923 } else if (type_sz(op
[0].type
) == 4) {
924 /* AND(val, 0x80000000) gives the sign bit.
926 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
929 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
931 op
[0].type
= BRW_REGISTER_TYPE_UD
;
932 result
.type
= BRW_REGISTER_TYPE_UD
;
933 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
935 if (instr
->op
== nir_op_fsign
)
936 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
938 /* Use XOR here to get the result sign correct. */
939 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
942 inst
->predicate
= BRW_PREDICATE_NORMAL
;
944 /* For doubles we do the same but we need to consider:
946 * - 2-src instructions can't operate with 64-bit immediates
947 * - The sign is encoded in the high 32-bit of each DF
948 * - We need to produce a DF result.
951 fs_reg zero
= vgrf(glsl_type::double_type
);
952 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
953 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
955 bld
.MOV(result
, zero
);
957 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
958 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
959 brw_imm_ud(0x80000000u
));
961 if (instr
->op
== nir_op_fsign
) {
962 set_predicate(BRW_PREDICATE_NORMAL
,
963 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
965 /* This could be done better in some cases. If the scale is an
966 * immediate with the low 32-bits all 0, emitting a separate XOR and
967 * OR would allow an algebraic optimization to remove the OR. There
968 * are currently zero instances of fsign(double(x))*IMM in shader-db
969 * or any test suite, so it is hard to care at this time.
971 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
972 inst
= bld
.XOR(result_int64
, result_int64
,
973 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
979 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
981 * Checks the operands of a \c nir_op_fmul to determine whether or not
982 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
984 * \param instr The multiplication instruction
986 * \param fsign_src The source of \c instr that may or may not be a
990 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
992 assert(instr
->op
== nir_op_fmul
);
994 nir_alu_instr
*const fsign_instr
=
995 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
999 * 1. instr->src[fsign_src] must be a nir_op_fsign.
1000 * 2. The nir_op_fsign can only be used by this multiplication.
1001 * 3. The source that is the nir_op_fsign does not have source modifiers.
1002 * \c emit_fsign only examines the source modifiers of the source of the
1005 * The nir_op_fsign must also not have the saturate modifier, but steps
1006 * have already been taken (in nir_opt_algebraic) to ensure that.
1008 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
1009 is_used_once(fsign_instr
) &&
1010 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
1014 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1017 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1019 unsigned execution_mode
=
1020 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1023 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1025 switch (instr
->op
) {
1030 fs_reg temp
= result
;
1031 bool need_extra_copy
= false;
1032 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1033 if (!instr
->src
[i
].src
.is_ssa
&&
1034 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1035 need_extra_copy
= true;
1036 temp
= bld
.vgrf(result
.type
, 4);
1041 for (unsigned i
= 0; i
< 4; i
++) {
1042 if (!(instr
->dest
.write_mask
& (1 << i
)))
1045 if (instr
->op
== nir_op_mov
) {
1046 inst
= bld
.MOV(offset(temp
, bld
, i
),
1047 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1049 inst
= bld
.MOV(offset(temp
, bld
, i
),
1050 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1052 inst
->saturate
= instr
->dest
.saturate
;
1055 /* In this case the source and destination registers were the same,
1056 * so we need to insert an extra set of moves in order to deal with
1059 if (need_extra_copy
) {
1060 for (unsigned i
= 0; i
< 4; i
++) {
1061 if (!(instr
->dest
.write_mask
& (1 << i
)))
1064 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1072 if (optimize_extract_to_float(instr
, result
))
1074 inst
= bld
.MOV(result
, op
[0]);
1075 inst
->saturate
= instr
->dest
.saturate
;
1078 case nir_op_f2f16_rtne
:
1079 case nir_op_f2f16_rtz
:
1080 case nir_op_f2f16
: {
1081 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1083 if (nir_op_f2f16
== instr
->op
)
1084 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1086 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1088 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1089 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1091 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1092 * on the HW gen, it is a special hw opcode or just a MOV, and
1093 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1095 * But if we want to use that opcode, we need to provide support on
1096 * different optimizations and lowerings. As right now HF support is
1097 * only for gen8+, it will be better to use directly the MOV, and use
1098 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1100 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1101 inst
= bld
.MOV(result
, op
[0]);
1102 inst
->saturate
= instr
->dest
.saturate
;
1113 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1115 op
[0].type
= BRW_REGISTER_TYPE_D
;
1116 op
[0].negate
= !op
[0].negate
;
1139 if (result
.type
== BRW_REGISTER_TYPE_B
||
1140 result
.type
== BRW_REGISTER_TYPE_UB
||
1141 result
.type
== BRW_REGISTER_TYPE_HF
)
1142 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1144 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1145 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1146 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1147 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1149 inst
= bld
.MOV(result
, op
[0]);
1150 inst
->saturate
= instr
->dest
.saturate
;
1154 inst
= bld
.MOV(result
, op
[0]);
1155 inst
->saturate
= true;
1160 op
[0].negate
= true;
1161 inst
= bld
.MOV(result
, op
[0]);
1162 if (instr
->op
== nir_op_fneg
)
1163 inst
->saturate
= instr
->dest
.saturate
;
1168 op
[0].negate
= false;
1170 inst
= bld
.MOV(result
, op
[0]);
1171 if (instr
->op
== nir_op_fabs
)
1172 inst
->saturate
= instr
->dest
.saturate
;
1176 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1178 brw_rnd_mode_from_execution_mode(execution_mode
);
1179 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1183 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1184 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1186 inst
= bld
.MOV(result
, op
[0]);
1187 inst
->saturate
= instr
->dest
.saturate
;
1191 emit_fsign(bld
, instr
, result
, op
, 0);
1195 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1196 inst
->saturate
= instr
->dest
.saturate
;
1200 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1201 inst
->saturate
= instr
->dest
.saturate
;
1205 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1206 inst
->saturate
= instr
->dest
.saturate
;
1210 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1211 inst
->saturate
= instr
->dest
.saturate
;
1215 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1216 inst
->saturate
= instr
->dest
.saturate
;
1220 if (fs_key
->high_quality_derivatives
) {
1221 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1223 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1225 inst
->saturate
= instr
->dest
.saturate
;
1227 case nir_op_fddx_fine
:
1228 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1229 inst
->saturate
= instr
->dest
.saturate
;
1231 case nir_op_fddx_coarse
:
1232 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1233 inst
->saturate
= instr
->dest
.saturate
;
1236 if (fs_key
->high_quality_derivatives
) {
1237 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1239 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1241 inst
->saturate
= instr
->dest
.saturate
;
1243 case nir_op_fddy_fine
:
1244 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1245 inst
->saturate
= instr
->dest
.saturate
;
1247 case nir_op_fddy_coarse
:
1248 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1249 inst
->saturate
= instr
->dest
.saturate
;
1253 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1255 brw_rnd_mode_from_execution_mode(execution_mode
);
1256 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1261 inst
= bld
.ADD(result
, op
[0], op
[1]);
1262 inst
->saturate
= instr
->dest
.saturate
;
1265 case nir_op_uadd_sat
:
1266 inst
= bld
.ADD(result
, op
[0], op
[1]);
1267 inst
->saturate
= true;
1271 for (unsigned i
= 0; i
< 2; i
++) {
1272 if (can_fuse_fmul_fsign(instr
, i
)) {
1273 emit_fsign(bld
, instr
, result
, op
, i
);
1278 /* We emit the rounding mode after the previous fsign optimization since
1279 * it won't result in a MUL, but will try to negate the value by other
1282 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1284 brw_rnd_mode_from_execution_mode(execution_mode
);
1285 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1289 inst
= bld
.MUL(result
, op
[0], op
[1]);
1290 inst
->saturate
= instr
->dest
.saturate
;
1293 case nir_op_imul_2x32_64
:
1294 case nir_op_umul_2x32_64
:
1295 bld
.MUL(result
, op
[0], op
[1]);
1299 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1300 bld
.MUL(result
, op
[0], op
[1]);
1303 case nir_op_imul_high
:
1304 case nir_op_umul_high
:
1305 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1306 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1311 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1312 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1315 case nir_op_uadd_carry
:
1316 unreachable("Should have been lowered by carry_to_arith().");
1318 case nir_op_usub_borrow
:
1319 unreachable("Should have been lowered by borrow_to_arith().");
1323 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1324 * appears that our hardware just does the right thing for signed
1327 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1328 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1332 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1333 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1335 /* Math instructions don't support conditional mod */
1336 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1337 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1339 /* Now, we need to determine if signs of the sources are different.
1340 * When we XOR the sources, the top bit is 0 if they are the same and 1
1341 * if they are different. We can then use a conditional modifier to
1342 * turn that into a predicate. This leads us to an XOR.l instruction.
1344 * Technically, according to the PRM, you're not allowed to use .l on a
1345 * XOR instruction. However, emperical experiments and Curro's reading
1346 * of the simulator source both indicate that it's safe.
1348 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1349 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1350 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1351 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1353 /* If the result of the initial remainder operation is non-zero and the
1354 * two sources have different signs, add in a copy of op[1] to get the
1355 * final integer modulus value.
1357 inst
= bld
.ADD(result
, result
, op
[1]);
1358 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1365 case nir_op_fne32
: {
1366 fs_reg dest
= result
;
1368 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1370 dest
= bld
.vgrf(op
[0].type
, 1);
1372 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1374 if (bit_size
> 32) {
1375 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1376 } else if(bit_size
< 32) {
1377 /* When we convert the result to 32-bit we need to be careful and do
1378 * it as a signed conversion to get sign extension (for 32-bit true)
1380 const brw_reg_type src_type
=
1381 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1383 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1393 case nir_op_ine32
: {
1394 fs_reg dest
= result
;
1396 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1397 * type. So we convert both operands for the comparison.
1400 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1401 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1403 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1405 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1407 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1408 brw_cmod_for_nir_comparison(instr
->op
));
1410 if (bit_size
> 32) {
1411 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1412 } else if (bit_size
< 32) {
1413 /* When we convert the result to 32-bit we need to be careful and do
1414 * it as a signed conversion to get sign extension (for 32-bit true)
1416 const brw_reg_type src_type
=
1417 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1419 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1425 if (devinfo
->gen
>= 8) {
1426 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1428 if (inot_src_instr
!= NULL
&&
1429 (inot_src_instr
->op
== nir_op_ior
||
1430 inot_src_instr
->op
== nir_op_ixor
||
1431 inot_src_instr
->op
== nir_op_iand
) &&
1432 !inot_src_instr
->src
[0].abs
&&
1433 !inot_src_instr
->src
[0].negate
&&
1434 !inot_src_instr
->src
[1].abs
&&
1435 !inot_src_instr
->src
[1].negate
) {
1436 /* The sources of the source logical instruction are now the
1437 * sources of the instruction that will be generated.
1439 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1440 resolve_inot_sources(bld
, inot_src_instr
, op
);
1442 /* Smash all of the sources and destination to be signed. This
1443 * doesn't matter for the operation of the instruction, but cmod
1444 * propagation fails on unsigned sources with negation (due to
1445 * fs_inst::can_do_cmod returning false).
1448 brw_type_for_nir_type(devinfo
,
1449 (nir_alu_type
)(nir_type_int
|
1450 nir_dest_bit_size(instr
->dest
.dest
)));
1452 brw_type_for_nir_type(devinfo
,
1453 (nir_alu_type
)(nir_type_int
|
1454 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1456 brw_type_for_nir_type(devinfo
,
1457 (nir_alu_type
)(nir_type_int
|
1458 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1460 /* For XOR, only invert one of the sources. Arbitrarily choose
1463 op
[0].negate
= !op
[0].negate
;
1464 if (inot_src_instr
->op
!= nir_op_ixor
)
1465 op
[1].negate
= !op
[1].negate
;
1467 switch (inot_src_instr
->op
) {
1469 bld
.AND(result
, op
[0], op
[1]);
1473 bld
.OR(result
, op
[0], op
[1]);
1477 bld
.XOR(result
, op
[0], op
[1]);
1481 unreachable("impossible opcode");
1484 op
[0] = resolve_source_modifiers(op
[0]);
1486 bld
.NOT(result
, op
[0]);
1489 if (devinfo
->gen
>= 8) {
1490 resolve_inot_sources(bld
, instr
, op
);
1492 bld
.XOR(result
, op
[0], op
[1]);
1495 if (devinfo
->gen
>= 8) {
1496 resolve_inot_sources(bld
, instr
, op
);
1498 bld
.OR(result
, op
[0], op
[1]);
1501 if (devinfo
->gen
>= 8) {
1502 resolve_inot_sources(bld
, instr
, op
);
1504 bld
.AND(result
, op
[0], op
[1]);
1510 case nir_op_b32all_fequal2
:
1511 case nir_op_b32all_iequal2
:
1512 case nir_op_b32all_fequal3
:
1513 case nir_op_b32all_iequal3
:
1514 case nir_op_b32all_fequal4
:
1515 case nir_op_b32all_iequal4
:
1516 case nir_op_b32any_fnequal2
:
1517 case nir_op_b32any_inequal2
:
1518 case nir_op_b32any_fnequal3
:
1519 case nir_op_b32any_inequal3
:
1520 case nir_op_b32any_fnequal4
:
1521 case nir_op_b32any_inequal4
:
1522 unreachable("Lowered by nir_lower_alu_reductions");
1524 case nir_op_fnoise1_1
:
1525 case nir_op_fnoise1_2
:
1526 case nir_op_fnoise1_3
:
1527 case nir_op_fnoise1_4
:
1528 case nir_op_fnoise2_1
:
1529 case nir_op_fnoise2_2
:
1530 case nir_op_fnoise2_3
:
1531 case nir_op_fnoise2_4
:
1532 case nir_op_fnoise3_1
:
1533 case nir_op_fnoise3_2
:
1534 case nir_op_fnoise3_3
:
1535 case nir_op_fnoise3_4
:
1536 case nir_op_fnoise4_1
:
1537 case nir_op_fnoise4_2
:
1538 case nir_op_fnoise4_3
:
1539 case nir_op_fnoise4_4
:
1540 unreachable("not reached: should be handled by lower_noise");
1543 unreachable("not reached: should be handled by ldexp_to_arith()");
1546 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1547 inst
->saturate
= instr
->dest
.saturate
;
1551 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1552 inst
->saturate
= instr
->dest
.saturate
;
1556 case nir_op_f2b32
: {
1557 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1558 if (bit_size
== 64) {
1559 /* two-argument instructions can't take 64-bit immediates */
1563 if (instr
->op
== nir_op_f2b32
) {
1564 zero
= vgrf(glsl_type::double_type
);
1565 tmp
= vgrf(glsl_type::double_type
);
1566 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1568 zero
= vgrf(glsl_type::int64_t_type
);
1569 tmp
= vgrf(glsl_type::int64_t_type
);
1570 bld
.MOV(zero
, brw_imm_q(0));
1573 /* A SIMD16 execution needs to be split in two instructions, so use
1574 * a vgrf instead of the flag register as dst so instruction splitting
1577 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1578 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1581 if (bit_size
== 32) {
1582 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1584 assert(bit_size
== 16);
1585 zero
= instr
->op
== nir_op_f2b32
?
1586 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1588 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1594 inst
= bld
.RNDZ(result
, op
[0]);
1595 inst
->saturate
= instr
->dest
.saturate
;
1598 case nir_op_fceil
: {
1599 op
[0].negate
= !op
[0].negate
;
1600 fs_reg temp
= vgrf(glsl_type::float_type
);
1601 bld
.RNDD(temp
, op
[0]);
1603 inst
= bld
.MOV(result
, temp
);
1604 inst
->saturate
= instr
->dest
.saturate
;
1608 inst
= bld
.RNDD(result
, op
[0]);
1609 inst
->saturate
= instr
->dest
.saturate
;
1612 inst
= bld
.FRC(result
, op
[0]);
1613 inst
->saturate
= instr
->dest
.saturate
;
1615 case nir_op_fround_even
:
1616 inst
= bld
.RNDE(result
, op
[0]);
1617 inst
->saturate
= instr
->dest
.saturate
;
1620 case nir_op_fquantize2f16
: {
1621 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1622 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1623 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1625 /* The destination stride must be at least as big as the source stride. */
1626 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1629 /* Check for denormal */
1630 fs_reg abs_src0
= op
[0];
1631 abs_src0
.abs
= true;
1632 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1634 /* Get the appropriately signed zero */
1635 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1636 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1637 brw_imm_ud(0x80000000));
1638 /* Do the actual F32 -> F16 -> F32 conversion */
1639 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1640 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1641 /* Select that or zero based on normal status */
1642 inst
= bld
.SEL(result
, zero
, tmp32
);
1643 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1644 inst
->saturate
= instr
->dest
.saturate
;
1651 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1652 inst
->saturate
= instr
->dest
.saturate
;
1658 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1659 inst
->saturate
= instr
->dest
.saturate
;
1662 case nir_op_pack_snorm_2x16
:
1663 case nir_op_pack_snorm_4x8
:
1664 case nir_op_pack_unorm_2x16
:
1665 case nir_op_pack_unorm_4x8
:
1666 case nir_op_unpack_snorm_2x16
:
1667 case nir_op_unpack_snorm_4x8
:
1668 case nir_op_unpack_unorm_2x16
:
1669 case nir_op_unpack_unorm_4x8
:
1670 case nir_op_unpack_half_2x16
:
1671 case nir_op_pack_half_2x16
:
1672 unreachable("not reached: should be handled by lower_packing_builtins");
1674 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1675 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1677 case nir_op_unpack_half_2x16_split_x
:
1678 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1679 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1680 inst
->saturate
= instr
->dest
.saturate
;
1683 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1684 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1686 case nir_op_unpack_half_2x16_split_y
:
1687 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1688 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1689 inst
->saturate
= instr
->dest
.saturate
;
1692 case nir_op_pack_64_2x32_split
:
1693 case nir_op_pack_32_2x16_split
:
1694 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1697 case nir_op_unpack_64_2x32_split_x
:
1698 case nir_op_unpack_64_2x32_split_y
: {
1699 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1700 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1702 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1706 case nir_op_unpack_32_2x16_split_x
:
1707 case nir_op_unpack_32_2x16_split_y
: {
1708 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1709 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1711 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1716 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1717 inst
->saturate
= instr
->dest
.saturate
;
1720 case nir_op_bitfield_reverse
:
1721 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1722 bld
.BFREV(result
, op
[0]);
1725 case nir_op_bit_count
:
1726 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1727 bld
.CBIT(result
, op
[0]);
1730 case nir_op_ufind_msb
: {
1731 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1732 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1736 case nir_op_ifind_msb
: {
1737 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1739 if (devinfo
->gen
< 7) {
1740 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1742 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1744 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1745 * count from the LSB side. If FBH didn't return an error
1746 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1747 * count into an LSB count.
1749 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1751 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1752 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1753 inst
->src
[0].negate
= true;
1758 case nir_op_find_lsb
:
1759 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1761 if (devinfo
->gen
< 7) {
1762 fs_reg temp
= vgrf(glsl_type::int_type
);
1764 /* (x & -x) generates a value that consists of only the LSB of x.
1765 * For all powers of 2, findMSB(y) == findLSB(y).
1767 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1768 fs_reg negated_src
= src
;
1770 /* One must be negated, and the other must be non-negated. It
1771 * doesn't matter which is which.
1773 negated_src
.negate
= true;
1776 bld
.AND(temp
, src
, negated_src
);
1777 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1779 bld
.FBL(result
, op
[0]);
1783 case nir_op_ubitfield_extract
:
1784 case nir_op_ibitfield_extract
:
1785 unreachable("should have been lowered");
1788 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1789 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1792 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1793 bld
.BFI1(result
, op
[0], op
[1]);
1796 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1797 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1800 case nir_op_bitfield_insert
:
1801 unreachable("not reached: should have been lowered");
1804 bld
.SHL(result
, op
[0], op
[1]);
1807 bld
.ASR(result
, op
[0], op
[1]);
1810 bld
.SHR(result
, op
[0], op
[1]);
1814 bld
.ROL(result
, op
[0], op
[1]);
1817 bld
.ROR(result
, op
[0], op
[1]);
1820 case nir_op_pack_half_2x16_split
:
1821 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1825 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1827 brw_rnd_mode_from_execution_mode(execution_mode
);
1828 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1832 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1833 inst
->saturate
= instr
->dest
.saturate
;
1837 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1839 brw_rnd_mode_from_execution_mode(execution_mode
);
1840 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1844 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1845 inst
->saturate
= instr
->dest
.saturate
;
1848 case nir_op_b32csel
:
1849 if (optimize_frontfacing_ternary(instr
, result
))
1852 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1853 inst
= bld
.SEL(result
, op
[1], op
[2]);
1854 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1857 case nir_op_extract_u8
:
1858 case nir_op_extract_i8
: {
1859 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1864 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1865 * Use two instructions and a word or DWord intermediate integer type.
1867 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1868 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1870 if (instr
->op
== nir_op_extract_i8
) {
1871 /* If we need to sign extend, extract to a word first */
1872 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1873 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1874 bld
.MOV(result
, w_temp
);
1875 } else if (byte
& 1) {
1876 /* Extract the high byte from the word containing the desired byte
1880 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1883 /* Otherwise use an AND with 0xff and a word type */
1885 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1889 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1890 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1895 case nir_op_extract_u16
:
1896 case nir_op_extract_i16
: {
1897 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1898 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1899 bld
.MOV(result
, subscript(op
[0], type
, word
));
1904 unreachable("unhandled instruction");
1907 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1908 * to sign extend the low bit to 0/~0
1910 if (devinfo
->gen
<= 5 &&
1911 !result
.is_null() &&
1912 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1913 fs_reg masked
= vgrf(glsl_type::int_type
);
1914 bld
.AND(masked
, result
, brw_imm_d(1));
1915 masked
.negate
= true;
1916 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1921 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1922 nir_load_const_instr
*instr
)
1924 const brw_reg_type reg_type
=
1925 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1926 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1928 switch (instr
->def
.bit_size
) {
1930 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1931 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1935 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1936 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1940 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1941 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1945 assert(devinfo
->gen
>= 7);
1946 if (devinfo
->gen
== 7) {
1947 /* We don't get 64-bit integer types until gen8 */
1948 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1949 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1950 setup_imm_df(bld
, instr
->value
[i
].f64
));
1953 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1954 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1959 unreachable("Invalid bit size");
1962 nir_ssa_values
[instr
->def
.index
] = reg
;
1966 fs_visitor::get_nir_src(const nir_src
&src
)
1970 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1971 const brw_reg_type reg_type
=
1972 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1973 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1975 reg
= nir_ssa_values
[src
.ssa
->index
];
1978 /* We don't handle indirects on locals */
1979 assert(src
.reg
.indirect
== NULL
);
1980 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1981 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1984 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1985 /* The only 64-bit type available on gen7 is DF, so use that. */
1986 reg
.type
= BRW_REGISTER_TYPE_DF
;
1988 /* To avoid floating-point denorm flushing problems, set the type by
1989 * default to an integer type - instructions that need floating point
1990 * semantics will set this to F if they need to
1992 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1993 BRW_REGISTER_TYPE_D
);
2000 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2002 * This function should not be called on any value which may be 64 bits.
2003 * We could theoretically support 64-bit on gen8+ but we choose not to
2004 * because it wouldn't work in general (no gen7 support) and there are
2005 * enough restrictions in 64-bit immediates that you can't take the return
2006 * value and treat it the same as the result of get_nir_src().
2009 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2011 assert(nir_src_bit_size(src
) == 32);
2012 return nir_src_is_const(src
) ?
2013 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2017 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2020 const brw_reg_type reg_type
=
2021 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2022 dest
.ssa
.bit_size
== 8 ?
2023 BRW_REGISTER_TYPE_D
:
2024 BRW_REGISTER_TYPE_F
);
2025 nir_ssa_values
[dest
.ssa
.index
] =
2026 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2027 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2028 return nir_ssa_values
[dest
.ssa
.index
];
2030 /* We don't handle indirects on locals */
2031 assert(dest
.reg
.indirect
== NULL
);
2032 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2033 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2038 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2041 for (unsigned i
= 0; i
< 4; i
++) {
2042 if (!((wr_mask
>> i
) & 1))
2045 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2046 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2047 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2048 if (new_inst
->src
[j
].file
== VGRF
)
2049 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2056 emit_pixel_interpolater_send(const fs_builder
&bld
,
2061 glsl_interp_mode interpolation
)
2063 struct brw_wm_prog_data
*wm_prog_data
=
2064 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2066 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2067 /* 2 floats per slot returned */
2068 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2069 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2071 wm_prog_data
->pulls_bary
= true;
2077 * Computes 1 << x, given a D/UD register containing some value x.
2080 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2082 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2084 fs_reg result
= bld
.vgrf(x
.type
, 1);
2085 fs_reg one
= bld
.vgrf(x
.type
, 1);
2087 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2088 bld
.SHL(result
, one
, x
);
2093 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2095 assert(stage
== MESA_SHADER_GEOMETRY
);
2097 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2099 if (gs_compile
->control_data_header_size_bits
== 0)
2102 /* We can only do EndPrimitive() functionality when the control data
2103 * consists of cut bits. Fortunately, the only time it isn't is when the
2104 * output type is points, in which case EndPrimitive() is a no-op.
2106 if (gs_prog_data
->control_data_format
!=
2107 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2111 /* Cut bits use one bit per vertex. */
2112 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2114 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2115 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2117 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2118 * vertex n, 0 otherwise. So all we need to do here is mark bit
2119 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2120 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2121 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2123 * Note that if EndPrimitive() is called before emitting any vertices, this
2124 * will cause us to set bit 31 of the control_data_bits register to 1.
2125 * That's fine because:
2127 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2128 * output, so the hardware will ignore cut bit 31.
2130 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2131 * last vertex, so setting cut bit 31 has no effect (since the primitive
2132 * is automatically ended when the GS terminates).
2134 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2135 * control_data_bits register to 0 when the first vertex is emitted.
2138 const fs_builder abld
= bld
.annotate("end primitive");
2140 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2141 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2142 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2143 fs_reg mask
= intexp2(abld
, prev_count
);
2144 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2145 * attention to the lower 5 bits of its second source argument, so on this
2146 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2147 * ((vertex_count - 1) % 32).
2149 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2153 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2155 assert(stage
== MESA_SHADER_GEOMETRY
);
2156 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2158 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2160 const fs_builder abld
= bld
.annotate("emit control data bits");
2161 const fs_builder fwa_bld
= bld
.exec_all();
2163 /* We use a single UD register to accumulate control data bits (32 bits
2164 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2167 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2168 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2169 * use the Channel Mask phase to enable/disable which DWord within that
2170 * group to write. (Remember, different SIMD8 channels may have emitted
2171 * different numbers of vertices, so we may need per-slot offsets.)
2173 * Channel masking presents an annoying problem: we may have to replicate
2174 * the data up to 4 times:
2176 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2178 * To avoid penalizing shaders that emit a small number of vertices, we
2179 * can avoid these sometimes: if the size of the control data header is
2180 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2181 * land in the same 128-bit group, so we can skip per-slot offsets.
2183 * Similarly, if the control data header is <= 32 bits, there is only one
2184 * DWord, so we can skip channel masks.
2186 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2188 fs_reg channel_mask
, per_slot_offset
;
2190 if (gs_compile
->control_data_header_size_bits
> 32) {
2191 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2192 channel_mask
= vgrf(glsl_type::uint_type
);
2195 if (gs_compile
->control_data_header_size_bits
> 128) {
2196 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2197 per_slot_offset
= vgrf(glsl_type::uint_type
);
2200 /* Figure out which DWord we're trying to write to using the formula:
2202 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2204 * Since bits_per_vertex is a power of two, and is known at compile
2205 * time, this can be optimized to:
2207 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2209 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2210 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2211 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2212 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2213 unsigned log2_bits_per_vertex
=
2214 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2215 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2217 if (per_slot_offset
.file
!= BAD_FILE
) {
2218 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2219 * the appropriate OWord within the control data header.
2221 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2224 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2225 * write to the appropriate DWORD within the OWORD.
2227 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2228 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2229 channel_mask
= intexp2(fwa_bld
, channel
);
2230 /* Then the channel masks need to be in bits 23:16. */
2231 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2234 /* Store the control data bits in the message payload and send it. */
2236 if (channel_mask
.file
!= BAD_FILE
)
2237 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2238 if (per_slot_offset
.file
!= BAD_FILE
)
2241 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2242 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2244 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2245 if (per_slot_offset
.file
!= BAD_FILE
)
2246 sources
[i
++] = per_slot_offset
;
2247 if (channel_mask
.file
!= BAD_FILE
)
2248 sources
[i
++] = channel_mask
;
2250 sources
[i
++] = this->control_data_bits
;
2253 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2254 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2256 /* We need to increment Global Offset by 256-bits to make room for
2257 * Broadwell's extra "Vertex Count" payload at the beginning of the
2258 * URB entry. Since this is an OWord message, Global Offset is counted
2259 * in 128-bit units, so we must set it to 2.
2261 if (gs_prog_data
->static_vertex_count
== -1)
2266 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2269 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2271 /* Note: we are calling this *before* increasing vertex_count, so
2272 * this->vertex_count == vertex_count - 1 in the formula above.
2275 /* Stream mode uses 2 bits per vertex */
2276 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2278 /* Must be a valid stream */
2279 assert(stream_id
< MAX_VERTEX_STREAMS
);
2281 /* Control data bits are initialized to 0 so we don't have to set any
2282 * bits when sending vertices to stream 0.
2287 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2289 /* reg::sid = stream_id */
2290 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2291 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2293 /* reg:shift_count = 2 * (vertex_count - 1) */
2294 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2295 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2297 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2298 * attention to the lower 5 bits of its second source argument, so on this
2299 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2300 * stream_id << ((2 * (vertex_count - 1)) % 32).
2302 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2303 abld
.SHL(mask
, sid
, shift_count
);
2304 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2308 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2311 assert(stage
== MESA_SHADER_GEOMETRY
);
2313 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2315 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2316 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2318 /* Haswell and later hardware ignores the "Render Stream Select" bits
2319 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2320 * and instead sends all primitives down the pipeline for rasterization.
2321 * If the SOL stage is enabled, "Render Stream Select" is honored and
2322 * primitives bound to non-zero streams are discarded after stream output.
2324 * Since the only purpose of primives sent to non-zero streams is to
2325 * be recorded by transform feedback, we can simply discard all geometry
2326 * bound to these streams when transform feedback is disabled.
2328 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2331 /* If we're outputting 32 control data bits or less, then we can wait
2332 * until the shader is over to output them all. Otherwise we need to
2333 * output them as we go. Now is the time to do it, since we're about to
2334 * output the vertex_count'th vertex, so it's guaranteed that the
2335 * control data bits associated with the (vertex_count - 1)th vertex are
2338 if (gs_compile
->control_data_header_size_bits
> 32) {
2339 const fs_builder abld
=
2340 bld
.annotate("emit vertex: emit control data bits");
2342 /* Only emit control data bits if we've finished accumulating a batch
2343 * of 32 bits. This is the case when:
2345 * (vertex_count * bits_per_vertex) % 32 == 0
2347 * (in other words, when the last 5 bits of vertex_count *
2348 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2349 * integer n (which is always the case, since bits_per_vertex is
2350 * always 1 or 2), this is equivalent to requiring that the last 5-n
2351 * bits of vertex_count are 0:
2353 * vertex_count & (2^(5-n) - 1) == 0
2355 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2358 * vertex_count & (32 / bits_per_vertex - 1) == 0
2360 * TODO: If vertex_count is an immediate, we could do some of this math
2361 * at compile time...
2364 abld
.AND(bld
.null_reg_d(), vertex_count
,
2365 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2366 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2368 abld
.IF(BRW_PREDICATE_NORMAL
);
2369 /* If vertex_count is 0, then no control data bits have been
2370 * accumulated yet, so we can skip emitting them.
2372 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2373 BRW_CONDITIONAL_NEQ
);
2374 abld
.IF(BRW_PREDICATE_NORMAL
);
2375 emit_gs_control_data_bits(vertex_count
);
2376 abld
.emit(BRW_OPCODE_ENDIF
);
2378 /* Reset control_data_bits to 0 so we can start accumulating a new
2381 * Note: in the case where vertex_count == 0, this neutralizes the
2382 * effect of any call to EndPrimitive() that the shader may have
2383 * made before outputting its first vertex.
2385 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2386 inst
->force_writemask_all
= true;
2387 abld
.emit(BRW_OPCODE_ENDIF
);
2390 emit_urb_writes(vertex_count
);
2392 /* In stream mode we have to set control data bits for all vertices
2393 * unless we have disabled control data bits completely (which we do
2394 * do for GL_POINTS outputs that don't use streams).
2396 if (gs_compile
->control_data_header_size_bits
> 0 &&
2397 gs_prog_data
->control_data_format
==
2398 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2399 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2404 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2405 const nir_src
&vertex_src
,
2406 unsigned base_offset
,
2407 const nir_src
&offset_src
,
2408 unsigned num_components
,
2409 unsigned first_component
)
2411 assert(type_sz(dst
.type
) == 4);
2412 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2413 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2415 /* TODO: figure out push input layout for invocations == 1 */
2416 if (gs_prog_data
->invocations
== 1 &&
2417 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2418 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2419 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2420 nir_src_as_uint(vertex_src
) * push_reg_count
;
2421 for (unsigned i
= 0; i
< num_components
; i
++) {
2422 bld
.MOV(offset(dst
, bld
, i
),
2423 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2428 /* Resort to the pull model. Ensure the VUE handles are provided. */
2429 assert(gs_prog_data
->base
.include_vue_handles
);
2431 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2432 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2434 if (gs_prog_data
->invocations
== 1) {
2435 if (nir_src_is_const(vertex_src
)) {
2436 /* The vertex index is constant; just select the proper URB handle. */
2438 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2439 BRW_REGISTER_TYPE_UD
);
2441 /* The vertex index is non-constant. We need to use indirect
2442 * addressing to fetch the proper URB handle.
2444 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2445 * indicating that channel <n> should read the handle from
2446 * DWord <n>. We convert that to bytes by multiplying by 4.
2448 * Next, we convert the vertex index to bytes by multiplying
2449 * by 32 (shifting by 5), and add the two together. This is
2450 * the final indirect byte offset.
2452 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2453 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2454 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2455 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2457 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2458 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2459 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2460 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2461 /* Convert vertex_index to bytes (multiply by 32) */
2462 bld
.SHL(vertex_offset_bytes
,
2463 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2465 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2467 /* Use first_icp_handle as the base offset. There is one register
2468 * of URB handles per vertex, so inform the register allocator that
2469 * we might read up to nir->info.gs.vertices_in registers.
2471 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2472 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2473 fs_reg(icp_offset_bytes
),
2474 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2477 assert(gs_prog_data
->invocations
> 1);
2479 if (nir_src_is_const(vertex_src
)) {
2480 unsigned vertex
= nir_src_as_uint(vertex_src
);
2481 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2483 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2484 BRW_REGISTER_TYPE_UD
));
2486 /* The vertex index is non-constant. We need to use indirect
2487 * addressing to fetch the proper URB handle.
2490 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2492 /* Convert vertex_index to bytes (multiply by 4) */
2493 bld
.SHL(icp_offset_bytes
,
2494 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2497 /* Use first_icp_handle as the base offset. There is one DWord
2498 * of URB handles per vertex, so inform the register allocator that
2499 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2501 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2502 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2503 fs_reg(icp_offset_bytes
),
2504 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2510 fs_reg indirect_offset
= get_nir_src(offset_src
);
2512 if (nir_src_is_const(offset_src
)) {
2513 /* Constant indexing - use global offset. */
2514 if (first_component
!= 0) {
2515 unsigned read_components
= num_components
+ first_component
;
2516 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2517 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2518 inst
->size_written
= read_components
*
2519 tmp
.component_size(inst
->exec_size
);
2520 for (unsigned i
= 0; i
< num_components
; i
++) {
2521 bld
.MOV(offset(dst
, bld
, i
),
2522 offset(tmp
, bld
, i
+ first_component
));
2525 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2526 inst
->size_written
= num_components
*
2527 dst
.component_size(inst
->exec_size
);
2529 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2532 /* Indirect indexing - use per-slot offsets as well. */
2533 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2534 unsigned read_components
= num_components
+ first_component
;
2535 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2536 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2537 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2538 if (first_component
!= 0) {
2539 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2541 inst
->size_written
= read_components
*
2542 tmp
.component_size(inst
->exec_size
);
2543 for (unsigned i
= 0; i
< num_components
; i
++) {
2544 bld
.MOV(offset(dst
, bld
, i
),
2545 offset(tmp
, bld
, i
+ first_component
));
2548 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2549 inst
->size_written
= num_components
*
2550 dst
.component_size(inst
->exec_size
);
2552 inst
->offset
= base_offset
;
2558 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2560 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2562 if (nir_src_is_const(*offset_src
)) {
2563 /* The only constant offset we should find is 0. brw_nir.c's
2564 * add_const_offset_to_base() will fold other constant offsets
2565 * into instr->const_index[0].
2567 assert(nir_src_as_uint(*offset_src
) == 0);
2571 return get_nir_src(*offset_src
);
2575 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2576 nir_intrinsic_instr
*instr
)
2578 assert(stage
== MESA_SHADER_VERTEX
);
2581 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2582 dest
= get_nir_dest(instr
->dest
);
2584 switch (instr
->intrinsic
) {
2585 case nir_intrinsic_load_vertex_id
:
2586 case nir_intrinsic_load_base_vertex
:
2587 unreachable("should be lowered by nir_lower_system_values()");
2589 case nir_intrinsic_load_input
: {
2590 assert(nir_dest_bit_size(instr
->dest
) == 32);
2591 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2592 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2593 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2595 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2596 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2600 case nir_intrinsic_load_vertex_id_zero_base
:
2601 case nir_intrinsic_load_instance_id
:
2602 case nir_intrinsic_load_base_instance
:
2603 case nir_intrinsic_load_draw_id
:
2604 case nir_intrinsic_load_first_vertex
:
2605 case nir_intrinsic_load_is_indexed_draw
:
2606 unreachable("lowered by brw_nir_lower_vs_inputs");
2609 nir_emit_intrinsic(bld
, instr
);
2615 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2616 nir_intrinsic_instr
*instr
)
2618 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2619 const nir_src
&vertex_src
= instr
->src
[0];
2620 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2623 if (nir_src_is_const(vertex_src
)) {
2624 /* Emit a MOV to resolve <0,1,0> regioning. */
2625 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2626 unsigned vertex
= nir_src_as_uint(vertex_src
);
2628 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2629 BRW_REGISTER_TYPE_UD
));
2630 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2631 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2632 /* For the common case of only 1 instance, an array index of
2633 * gl_InvocationID means reading g1. Skip all the indirect work.
2635 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2637 /* The vertex index is non-constant. We need to use indirect
2638 * addressing to fetch the proper URB handle.
2640 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2642 /* Each ICP handle is a single DWord (4 bytes) */
2643 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2644 bld
.SHL(vertex_offset_bytes
,
2645 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2648 /* Start at g1. We might read up to 4 registers. */
2649 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2650 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2651 brw_imm_ud(4 * REG_SIZE
));
2658 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2659 nir_intrinsic_instr
*instr
)
2661 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2662 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2663 const nir_src
&vertex_src
= instr
->src
[0];
2665 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2667 if (nir_src_is_const(vertex_src
)) {
2668 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2669 nir_src_as_uint(vertex_src
), 0),
2670 BRW_REGISTER_TYPE_UD
));
2673 /* The vertex index is non-constant. We need to use indirect
2674 * addressing to fetch the proper URB handle.
2676 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2677 * indicating that channel <n> should read the handle from
2678 * DWord <n>. We convert that to bytes by multiplying by 4.
2680 * Next, we convert the vertex index to bytes by multiplying
2681 * by 32 (shifting by 5), and add the two together. This is
2682 * the final indirect byte offset.
2684 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2685 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2686 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2687 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2688 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2690 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2691 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2692 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2693 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2694 /* Convert vertex_index to bytes (multiply by 32) */
2695 bld
.SHL(vertex_offset_bytes
,
2696 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2698 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2700 /* Use first_icp_handle as the base offset. There is one register
2701 * of URB handles per vertex, so inform the register allocator that
2702 * we might read up to nir->info.gs.vertices_in registers.
2704 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2705 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2706 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2712 fs_visitor::get_tcs_output_urb_handle()
2714 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2716 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2717 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2719 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2720 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2725 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2726 nir_intrinsic_instr
*instr
)
2728 assert(stage
== MESA_SHADER_TESS_CTRL
);
2729 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2730 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2731 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2734 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2737 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2738 dst
= get_nir_dest(instr
->dest
);
2740 switch (instr
->intrinsic
) {
2741 case nir_intrinsic_load_primitive_id
:
2742 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2743 : brw_vec1_grf(0, 1)));
2745 case nir_intrinsic_load_invocation_id
:
2746 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2748 case nir_intrinsic_load_patch_vertices_in
:
2749 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2750 brw_imm_d(tcs_key
->input_vertices
));
2753 case nir_intrinsic_barrier
: {
2754 if (tcs_prog_data
->instances
== 1)
2757 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2758 fs_reg m0_2
= component(m0
, 2);
2760 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2762 /* Zero the message header */
2763 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2765 if (devinfo
->gen
< 11) {
2766 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2767 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2768 brw_imm_ud(INTEL_MASK(16, 13)));
2770 /* Shift it up to bits 27:24. */
2771 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2773 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2774 brw_imm_ud(INTEL_MASK(30, 24)));
2777 /* Set the Barrier Count and the enable bit */
2778 if (devinfo
->gen
< 11) {
2779 chanbld
.OR(m0_2
, m0_2
,
2780 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2782 chanbld
.OR(m0_2
, m0_2
,
2783 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2786 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2790 case nir_intrinsic_load_input
:
2791 unreachable("nir_lower_io should never give us these.");
2794 case nir_intrinsic_load_per_vertex_input
: {
2795 assert(nir_dest_bit_size(instr
->dest
) == 32);
2796 fs_reg indirect_offset
= get_indirect_offset(instr
);
2797 unsigned imm_offset
= instr
->const_index
[0];
2801 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2802 : get_tcs_single_patch_icp_handle(bld
, instr
);
2804 /* We can only read two double components with each URB read, so
2805 * we send two read messages in that case, each one loading up to
2806 * two double components.
2808 unsigned num_components
= instr
->num_components
;
2809 unsigned first_component
= nir_intrinsic_component(instr
);
2811 if (indirect_offset
.file
== BAD_FILE
) {
2812 /* Constant indexing - use global offset. */
2813 if (first_component
!= 0) {
2814 unsigned read_components
= num_components
+ first_component
;
2815 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2816 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2817 for (unsigned i
= 0; i
< num_components
; i
++) {
2818 bld
.MOV(offset(dst
, bld
, i
),
2819 offset(tmp
, bld
, i
+ first_component
));
2822 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2824 inst
->offset
= imm_offset
;
2827 /* Indirect indexing - use per-slot offsets as well. */
2828 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2829 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2830 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2831 if (first_component
!= 0) {
2832 unsigned read_components
= num_components
+ first_component
;
2833 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2834 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2836 for (unsigned i
= 0; i
< num_components
; i
++) {
2837 bld
.MOV(offset(dst
, bld
, i
),
2838 offset(tmp
, bld
, i
+ first_component
));
2841 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2844 inst
->offset
= imm_offset
;
2847 inst
->size_written
= (num_components
+ first_component
) *
2848 inst
->dst
.component_size(inst
->exec_size
);
2850 /* Copy the temporary to the destination to deal with writemasking.
2852 * Also attempt to deal with gl_PointSize being in the .w component.
2854 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2855 assert(type_sz(dst
.type
) == 4);
2856 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2857 inst
->size_written
= 4 * REG_SIZE
;
2858 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2863 case nir_intrinsic_load_output
:
2864 case nir_intrinsic_load_per_vertex_output
: {
2865 assert(nir_dest_bit_size(instr
->dest
) == 32);
2866 fs_reg indirect_offset
= get_indirect_offset(instr
);
2867 unsigned imm_offset
= instr
->const_index
[0];
2868 unsigned first_component
= nir_intrinsic_component(instr
);
2870 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2873 if (indirect_offset
.file
== BAD_FILE
) {
2874 /* This MOV replicates the output handle to all enabled channels
2875 * is SINGLE_PATCH mode.
2877 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2878 bld
.MOV(patch_handle
, output_handles
);
2881 if (first_component
!= 0) {
2882 unsigned read_components
=
2883 instr
->num_components
+ first_component
;
2884 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2885 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2887 inst
->size_written
= read_components
* REG_SIZE
;
2888 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2889 bld
.MOV(offset(dst
, bld
, i
),
2890 offset(tmp
, bld
, i
+ first_component
));
2893 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2895 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2897 inst
->offset
= imm_offset
;
2901 /* Indirect indexing - use per-slot offsets as well. */
2902 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2903 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2904 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2905 if (first_component
!= 0) {
2906 unsigned read_components
=
2907 instr
->num_components
+ first_component
;
2908 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2909 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2911 inst
->size_written
= read_components
* REG_SIZE
;
2912 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2913 bld
.MOV(offset(dst
, bld
, i
),
2914 offset(tmp
, bld
, i
+ first_component
));
2917 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2919 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2921 inst
->offset
= imm_offset
;
2927 case nir_intrinsic_store_output
:
2928 case nir_intrinsic_store_per_vertex_output
: {
2929 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2930 fs_reg value
= get_nir_src(instr
->src
[0]);
2931 fs_reg indirect_offset
= get_indirect_offset(instr
);
2932 unsigned imm_offset
= instr
->const_index
[0];
2933 unsigned mask
= instr
->const_index
[1];
2934 unsigned header_regs
= 0;
2935 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2938 srcs
[header_regs
++] = output_handles
;
2940 if (indirect_offset
.file
!= BAD_FILE
) {
2941 srcs
[header_regs
++] = indirect_offset
;
2947 unsigned num_components
= util_last_bit(mask
);
2950 /* We can only pack two 64-bit components in a single message, so send
2951 * 2 messages if we have more components
2953 unsigned first_component
= nir_intrinsic_component(instr
);
2954 mask
= mask
<< first_component
;
2956 if (mask
!= WRITEMASK_XYZW
) {
2957 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2958 opcode
= indirect_offset
.file
!= BAD_FILE
?
2959 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2960 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2962 opcode
= indirect_offset
.file
!= BAD_FILE
?
2963 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2964 SHADER_OPCODE_URB_WRITE_SIMD8
;
2967 for (unsigned i
= 0; i
< num_components
; i
++) {
2968 if (!(mask
& (1 << (i
+ first_component
))))
2971 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2974 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2976 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2977 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2979 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2980 inst
->offset
= imm_offset
;
2986 nir_emit_intrinsic(bld
, instr
);
2992 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2993 nir_intrinsic_instr
*instr
)
2995 assert(stage
== MESA_SHADER_TESS_EVAL
);
2996 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2999 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3000 dest
= get_nir_dest(instr
->dest
);
3002 switch (instr
->intrinsic
) {
3003 case nir_intrinsic_load_primitive_id
:
3004 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3006 case nir_intrinsic_load_tess_coord
:
3007 /* gl_TessCoord is part of the payload in g1-3 */
3008 for (unsigned i
= 0; i
< 3; i
++) {
3009 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3013 case nir_intrinsic_load_input
:
3014 case nir_intrinsic_load_per_vertex_input
: {
3015 assert(nir_dest_bit_size(instr
->dest
) == 32);
3016 fs_reg indirect_offset
= get_indirect_offset(instr
);
3017 unsigned imm_offset
= instr
->const_index
[0];
3018 unsigned first_component
= nir_intrinsic_component(instr
);
3021 if (indirect_offset
.file
== BAD_FILE
) {
3022 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3023 * which is 16 registers (since each holds 2 vec4 slots).
3025 const unsigned max_push_slots
= 32;
3026 if (imm_offset
< max_push_slots
) {
3027 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3028 for (int i
= 0; i
< instr
->num_components
; i
++) {
3029 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3030 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3033 tes_prog_data
->base
.urb_read_length
=
3034 MAX2(tes_prog_data
->base
.urb_read_length
,
3035 (imm_offset
/ 2) + 1);
3037 /* Replicate the patch handle to all enabled channels */
3038 const fs_reg srcs
[] = {
3039 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3041 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3042 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3044 if (first_component
!= 0) {
3045 unsigned read_components
=
3046 instr
->num_components
+ first_component
;
3047 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3048 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3050 inst
->size_written
= read_components
* REG_SIZE
;
3051 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3052 bld
.MOV(offset(dest
, bld
, i
),
3053 offset(tmp
, bld
, i
+ first_component
));
3056 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3058 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3061 inst
->offset
= imm_offset
;
3064 /* Indirect indexing - use per-slot offsets as well. */
3066 /* We can only read two double components with each URB read, so
3067 * we send two read messages in that case, each one loading up to
3068 * two double components.
3070 unsigned num_components
= instr
->num_components
;
3071 const fs_reg srcs
[] = {
3072 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3075 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3076 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3078 if (first_component
!= 0) {
3079 unsigned read_components
=
3080 num_components
+ first_component
;
3081 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3082 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3084 for (unsigned i
= 0; i
< num_components
; i
++) {
3085 bld
.MOV(offset(dest
, bld
, i
),
3086 offset(tmp
, bld
, i
+ first_component
));
3089 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3093 inst
->offset
= imm_offset
;
3094 inst
->size_written
= (num_components
+ first_component
) *
3095 inst
->dst
.component_size(inst
->exec_size
);
3100 nir_emit_intrinsic(bld
, instr
);
3106 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3107 nir_intrinsic_instr
*instr
)
3109 assert(stage
== MESA_SHADER_GEOMETRY
);
3110 fs_reg indirect_offset
;
3113 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3114 dest
= get_nir_dest(instr
->dest
);
3116 switch (instr
->intrinsic
) {
3117 case nir_intrinsic_load_primitive_id
:
3118 assert(stage
== MESA_SHADER_GEOMETRY
);
3119 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3120 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3121 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3124 case nir_intrinsic_load_input
:
3125 unreachable("load_input intrinsics are invalid for the GS stage");
3127 case nir_intrinsic_load_per_vertex_input
:
3128 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3129 instr
->src
[1], instr
->num_components
,
3130 nir_intrinsic_component(instr
));
3133 case nir_intrinsic_emit_vertex_with_counter
:
3134 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3137 case nir_intrinsic_end_primitive_with_counter
:
3138 emit_gs_end_primitive(instr
->src
[0]);
3141 case nir_intrinsic_set_vertex_count
:
3142 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3145 case nir_intrinsic_load_invocation_id
: {
3146 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3147 assert(val
.file
!= BAD_FILE
);
3148 dest
.type
= val
.type
;
3154 nir_emit_intrinsic(bld
, instr
);
3160 * Fetch the current render target layer index.
3163 fetch_render_target_array_index(const fs_builder
&bld
)
3165 if (bld
.shader
->devinfo
->gen
>= 6) {
3166 /* The render target array index is provided in the thread payload as
3167 * bits 26:16 of r0.0.
3169 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3170 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3174 /* Pre-SNB we only ever render into the first layer of the framebuffer
3175 * since layered rendering is not implemented.
3177 return brw_imm_ud(0);
3182 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3183 * framebuffer at the current fragment coordinates and sample index.
3186 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3189 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3191 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3192 const brw_wm_prog_key
*wm_key
=
3193 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3194 assert(!wm_key
->coherent_fb_fetch
);
3195 const struct brw_wm_prog_data
*wm_prog_data
=
3196 brw_wm_prog_data(stage_prog_data
);
3198 /* Calculate the surface index relative to the start of the texture binding
3199 * table block, since that's what the texturing messages expect.
3201 const unsigned surface
= target
+
3202 wm_prog_data
->binding_table
.render_target_read_start
-
3203 wm_prog_data
->base
.binding_table
.texture_start
;
3205 /* Calculate the fragment coordinates. */
3206 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3207 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3208 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3209 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3211 /* Calculate the sample index and MCS payload when multisampling. Luckily
3212 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3213 * shouldn't be necessary to recompile based on whether the framebuffer is
3216 if (wm_key
->multisample_fbo
&&
3217 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3218 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3220 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3221 const fs_reg mcs
= wm_key
->multisample_fbo
?
3222 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3224 /* Use either a normal or a CMS texel fetch message depending on whether
3225 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3226 * message just in case the framebuffer uses 16x multisampling, it should
3227 * be equivalent to the normal CMS fetch for lower multisampling modes.
3229 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3230 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3231 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3233 /* Emit the instruction. */
3234 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3235 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3236 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3237 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3238 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3239 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3240 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3241 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3242 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3244 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3245 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3251 * Actual coherent framebuffer read implemented using the native render target
3252 * read message. Requires SKL+.
3255 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3257 assert(bld
.shader
->devinfo
->gen
>= 9);
3258 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3259 inst
->target
= target
;
3260 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3266 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3268 if (n
&& regs
[0].file
!= BAD_FILE
) {
3272 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3274 for (unsigned i
= 0; i
< n
; i
++)
3282 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3284 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3285 const brw_wm_prog_key
*const key
=
3286 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3287 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3288 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3290 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3291 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3293 else if (l
== FRAG_RESULT_COLOR
)
3294 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3295 MAX2(key
->nr_color_regions
, 1));
3297 else if (l
== FRAG_RESULT_DEPTH
)
3298 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3300 else if (l
== FRAG_RESULT_STENCIL
)
3301 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3303 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3304 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3306 else if (l
>= FRAG_RESULT_DATA0
&&
3307 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3308 return alloc_temporary(v
->bld
, 4,
3309 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3312 unreachable("Invalid location");
3315 /* Annoyingly, we get the barycentrics into the shader in a layout that's
3316 * optimized for PLN but it doesn't work nearly as well as one would like for
3317 * manual interpolation.
3320 shuffle_from_pln_layout(const fs_builder
&bld
, fs_reg dest
, fs_reg pln_data
)
3322 dest
.type
= BRW_REGISTER_TYPE_F
;
3323 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3324 const fs_reg dest_u
= offset(dest
, bld
, 0);
3325 const fs_reg dest_v
= offset(dest
, bld
, 1);
3327 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3328 const fs_builder gbld
= bld
.group(8, g
);
3329 gbld
.MOV(horiz_offset(dest_u
, g
* 8),
3330 byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
));
3331 gbld
.MOV(horiz_offset(dest_v
, g
* 8),
3332 byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
));
3337 shuffle_to_pln_layout(const fs_builder
&bld
, fs_reg pln_data
, fs_reg src
)
3339 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3340 src
.type
= BRW_REGISTER_TYPE_F
;
3341 const fs_reg src_u
= offset(src
, bld
, 0);
3342 const fs_reg src_v
= offset(src
, bld
, 1);
3344 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3345 const fs_builder gbld
= bld
.group(8, g
);
3346 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
),
3347 horiz_offset(src_u
, g
* 8));
3348 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
),
3349 horiz_offset(src_v
, g
* 8));
3354 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3355 nir_intrinsic_instr
*instr
)
3357 assert(stage
== MESA_SHADER_FRAGMENT
);
3360 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3361 dest
= get_nir_dest(instr
->dest
);
3363 switch (instr
->intrinsic
) {
3364 case nir_intrinsic_load_front_face
:
3365 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3366 *emit_frontfacing_interpolation());
3369 case nir_intrinsic_load_sample_pos
: {
3370 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3371 assert(sample_pos
.file
!= BAD_FILE
);
3372 dest
.type
= sample_pos
.type
;
3373 bld
.MOV(dest
, sample_pos
);
3374 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3378 case nir_intrinsic_load_layer_id
:
3379 dest
.type
= BRW_REGISTER_TYPE_UD
;
3380 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3383 case nir_intrinsic_is_helper_invocation
: {
3384 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3385 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3386 * consideration demoted invocations. That information is stored in
3389 dest
.type
= BRW_REGISTER_TYPE_UD
;
3391 bld
.MOV(dest
, brw_imm_ud(0));
3393 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3394 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3395 mov
->predicate_inverse
= true;
3396 mov
->flag_subreg
= 1;
3400 case nir_intrinsic_load_helper_invocation
:
3401 case nir_intrinsic_load_sample_mask_in
:
3402 case nir_intrinsic_load_sample_id
: {
3403 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3404 fs_reg val
= nir_system_values
[sv
];
3405 assert(val
.file
!= BAD_FILE
);
3406 dest
.type
= val
.type
;
3411 case nir_intrinsic_store_output
: {
3412 const fs_reg src
= get_nir_src(instr
->src
[0]);
3413 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3414 const unsigned location
= nir_intrinsic_base(instr
) +
3415 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3416 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3419 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3420 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3421 offset(src
, bld
, j
));
3426 case nir_intrinsic_load_output
: {
3427 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3428 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3429 assert(l
>= FRAG_RESULT_DATA0
);
3430 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3431 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3432 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3434 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3435 emit_coherent_fb_read(bld
, tmp
, target
);
3437 emit_non_coherent_fb_read(bld
, tmp
, target
);
3439 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3440 bld
.MOV(offset(dest
, bld
, j
),
3441 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3447 case nir_intrinsic_demote
:
3448 case nir_intrinsic_discard
:
3449 case nir_intrinsic_demote_if
:
3450 case nir_intrinsic_discard_if
: {
3451 /* We track our discarded pixels in f0.1. By predicating on it, we can
3452 * update just the flag bits that aren't yet discarded. If there's no
3453 * condition, we emit a CMP of g0 != g0, so all currently executing
3454 * channels will get turned off.
3456 fs_inst
*cmp
= NULL
;
3457 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3458 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3459 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3462 alu
->op
!= nir_op_bcsel
&&
3463 alu
->op
!= nir_op_inot
) {
3464 /* Re-emit the instruction that generated the Boolean value, but
3465 * do not store it. Since this instruction will be conditional,
3466 * other instructions that want to use the real Boolean value may
3467 * get garbage. This was a problem for piglit's fs-discard-exit-2
3470 * Ideally we'd detect that the instruction cannot have a
3471 * conditional modifier before emitting the instructions. Alas,
3472 * that is nigh impossible. Instead, we're going to assume the
3473 * instruction (or last instruction) generated can have a
3474 * conditional modifier. If it cannot, fallback to the old-style
3475 * compare, and hope dead code elimination will clean up the
3476 * extra instructions generated.
3478 nir_emit_alu(bld
, alu
, false);
3480 cmp
= (fs_inst
*) instructions
.get_tail();
3481 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3482 if (cmp
->can_do_cmod())
3483 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3487 /* The old sequence that would have been generated is,
3488 * basically, bool_result == false. This is equivalent to
3489 * !bool_result, so negate the old modifier.
3491 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3496 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3497 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3500 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3501 BRW_REGISTER_TYPE_UW
));
3502 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3505 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3506 cmp
->flag_subreg
= 1;
3508 if (devinfo
->gen
>= 6) {
3509 /* Due to the way we implement discard, the jump will only happen
3510 * when the whole quad is discarded. So we can do this even for
3511 * demote as it won't break its uniformity promises.
3513 emit_discard_jump();
3516 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.");
3520 case nir_intrinsic_load_input
: {
3521 /* load_input is only used for flat inputs */
3522 assert(nir_dest_bit_size(instr
->dest
) == 32);
3523 unsigned base
= nir_intrinsic_base(instr
);
3524 unsigned comp
= nir_intrinsic_component(instr
);
3525 unsigned num_components
= instr
->num_components
;
3527 /* Special case fields in the VUE header */
3528 if (base
== VARYING_SLOT_LAYER
)
3530 else if (base
== VARYING_SLOT_VIEWPORT
)
3533 for (unsigned int i
= 0; i
< num_components
; i
++) {
3534 bld
.MOV(offset(dest
, bld
, i
),
3535 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3540 case nir_intrinsic_load_fs_input_interp_deltas
: {
3541 assert(stage
== MESA_SHADER_FRAGMENT
);
3542 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3543 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3544 nir_intrinsic_component(instr
));
3545 dest
.type
= BRW_REGISTER_TYPE_F
;
3546 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3547 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3548 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3552 case nir_intrinsic_load_barycentric_pixel
:
3553 case nir_intrinsic_load_barycentric_centroid
:
3554 case nir_intrinsic_load_barycentric_sample
: {
3555 /* Use the delta_xy values computed from the payload */
3556 const glsl_interp_mode interp_mode
=
3557 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3558 enum brw_barycentric_mode bary
=
3559 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3561 shuffle_from_pln_layout(bld
, dest
, this->delta_xy
[bary
]);
3565 case nir_intrinsic_load_barycentric_at_sample
: {
3566 const glsl_interp_mode interpolation
=
3567 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3569 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3570 if (nir_src_is_const(instr
->src
[0])) {
3571 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3573 emit_pixel_interpolater_send(bld
,
3574 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3577 brw_imm_ud(msg_data
),
3580 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3581 BRW_REGISTER_TYPE_UD
);
3583 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3584 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3585 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3586 bld
.exec_all().group(1, 0)
3587 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3588 emit_pixel_interpolater_send(bld
,
3589 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3595 /* Make a loop that sends a message to the pixel interpolater
3596 * for the sample number in each live channel. If there are
3597 * multiple channels with the same sample number then these
3598 * will be handled simultaneously with a single interation of
3601 bld
.emit(BRW_OPCODE_DO
);
3603 /* Get the next live sample number into sample_id_reg */
3604 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3606 /* Set the flag register so that we can perform the send
3607 * message on all channels that have the same sample number
3609 bld
.CMP(bld
.null_reg_ud(),
3610 sample_src
, sample_id
,
3611 BRW_CONDITIONAL_EQ
);
3612 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3613 bld
.exec_all().group(1, 0)
3614 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3616 emit_pixel_interpolater_send(bld
,
3617 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3620 component(msg_data
, 0),
3622 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3624 /* Continue the loop if there are any live channels left */
3625 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3627 bld
.emit(BRW_OPCODE_WHILE
));
3630 shuffle_from_pln_layout(bld
, dest
, tmp
);
3634 case nir_intrinsic_load_barycentric_at_offset
: {
3635 const glsl_interp_mode interpolation
=
3636 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3638 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3640 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3642 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3643 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3644 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3646 emit_pixel_interpolater_send(bld
,
3647 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3650 brw_imm_ud(off_x
| (off_y
<< 4)),
3653 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3654 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3655 BRW_REGISTER_TYPE_F
);
3656 for (int i
= 0; i
< 2; i
++) {
3657 fs_reg temp
= vgrf(glsl_type::float_type
);
3658 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3659 fs_reg itemp
= vgrf(glsl_type::int_type
);
3661 bld
.MOV(itemp
, temp
);
3663 /* Clamp the upper end of the range to +7/16.
3664 * ARB_gpu_shader5 requires that we support a maximum offset
3665 * of +0.5, which isn't representable in a S0.4 value -- if
3666 * we didn't clamp it, we'd end up with -8/16, which is the
3667 * opposite of what the shader author wanted.
3669 * This is legal due to ARB_gpu_shader5's quantization
3672 * "Not all values of <offset> may be supported; x and y
3673 * offsets may be rounded to fixed-point values with the
3674 * number of fraction bits given by the
3675 * implementation-dependent constant
3676 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3678 set_condmod(BRW_CONDITIONAL_L
,
3679 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3682 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3683 emit_pixel_interpolater_send(bld
,
3690 shuffle_from_pln_layout(bld
, dest
, tmp
);
3694 case nir_intrinsic_load_frag_coord
:
3695 emit_fragcoord_interpolation(dest
);
3698 case nir_intrinsic_load_interpolated_input
: {
3699 assert(instr
->src
[0].ssa
&&
3700 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3701 nir_intrinsic_instr
*bary_intrinsic
=
3702 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3703 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3704 enum glsl_interp_mode interp_mode
=
3705 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3708 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3709 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3710 /* Use the result of the PI message. Because the load_barycentric
3711 * intrinsics return a regular vec2 and we need it in PLN layout, we
3712 * have to do a translation. Fortunately, copy-prop cleans this up
3715 dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3716 shuffle_to_pln_layout(bld
, dst_xy
, get_nir_src(instr
->src
[0]));
3718 /* Use the delta_xy values computed from the payload */
3719 enum brw_barycentric_mode bary
=
3720 brw_barycentric_mode(interp_mode
, bary_intrin
);
3722 dst_xy
= this->delta_xy
[bary
];
3725 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3727 component(interp_reg(nir_intrinsic_base(instr
),
3728 nir_intrinsic_component(instr
) + i
), 0);
3729 interp
.type
= BRW_REGISTER_TYPE_F
;
3730 dest
.type
= BRW_REGISTER_TYPE_F
;
3732 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3733 fs_reg tmp
= vgrf(glsl_type::float_type
);
3734 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3735 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3737 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3744 nir_emit_intrinsic(bld
, instr
);
3750 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3751 nir_intrinsic_instr
*instr
)
3753 assert(stage
== MESA_SHADER_COMPUTE
);
3754 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3757 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3758 dest
= get_nir_dest(instr
->dest
);
3760 switch (instr
->intrinsic
) {
3761 case nir_intrinsic_barrier
:
3763 cs_prog_data
->uses_barrier
= true;
3766 case nir_intrinsic_load_subgroup_id
:
3767 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3770 case nir_intrinsic_load_local_invocation_id
:
3771 case nir_intrinsic_load_work_group_id
: {
3772 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3773 fs_reg val
= nir_system_values
[sv
];
3774 assert(val
.file
!= BAD_FILE
);
3775 dest
.type
= val
.type
;
3776 for (unsigned i
= 0; i
< 3; i
++)
3777 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3781 case nir_intrinsic_load_num_work_groups
: {
3782 const unsigned surface
=
3783 cs_prog_data
->binding_table
.work_groups_start
;
3785 cs_prog_data
->uses_num_work_groups
= true;
3787 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3788 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3789 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3790 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3792 /* Read the 3 GLuint components of gl_NumWorkGroups */
3793 for (unsigned i
= 0; i
< 3; i
++) {
3794 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3795 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3796 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3801 case nir_intrinsic_shared_atomic_add
:
3802 case nir_intrinsic_shared_atomic_imin
:
3803 case nir_intrinsic_shared_atomic_umin
:
3804 case nir_intrinsic_shared_atomic_imax
:
3805 case nir_intrinsic_shared_atomic_umax
:
3806 case nir_intrinsic_shared_atomic_and
:
3807 case nir_intrinsic_shared_atomic_or
:
3808 case nir_intrinsic_shared_atomic_xor
:
3809 case nir_intrinsic_shared_atomic_exchange
:
3810 case nir_intrinsic_shared_atomic_comp_swap
:
3811 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3813 case nir_intrinsic_shared_atomic_fmin
:
3814 case nir_intrinsic_shared_atomic_fmax
:
3815 case nir_intrinsic_shared_atomic_fcomp_swap
:
3816 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3819 case nir_intrinsic_load_shared
: {
3820 assert(devinfo
->gen
>= 7);
3821 assert(stage
== MESA_SHADER_COMPUTE
);
3823 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3824 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3825 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3826 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3827 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3829 /* Make dest unsigned because that's what the temporary will be */
3830 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3832 /* Read the vector */
3833 if (nir_intrinsic_align(instr
) >= 4) {
3834 assert(nir_dest_bit_size(instr
->dest
) == 32);
3835 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3837 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3838 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3839 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3841 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3842 assert(nir_dest_num_components(instr
->dest
) == 1);
3843 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3845 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3846 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3847 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3848 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3853 case nir_intrinsic_store_shared
: {
3854 assert(devinfo
->gen
>= 7);
3855 assert(stage
== MESA_SHADER_COMPUTE
);
3857 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3858 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3859 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3860 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3861 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3863 fs_reg data
= get_nir_src(instr
->src
[0]);
3864 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3866 assert(nir_intrinsic_write_mask(instr
) ==
3867 (1u << instr
->num_components
) - 1);
3868 if (nir_intrinsic_align(instr
) >= 4) {
3869 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3870 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3871 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3872 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3873 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3874 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3876 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3877 assert(nir_src_num_components(instr
->src
[0]) == 1);
3878 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3880 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3881 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3883 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3884 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3890 nir_emit_intrinsic(bld
, instr
);
3896 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3897 nir_op op
, brw_reg_type type
)
3899 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3900 switch (type_sz(type
)) {
3902 if (type
== BRW_REGISTER_TYPE_UB
) {
3903 return brw_imm_uw(value
.u8
);
3905 assert(type
== BRW_REGISTER_TYPE_B
);
3906 return brw_imm_w(value
.i8
);
3909 return retype(brw_imm_uw(value
.u16
), type
);
3911 return retype(brw_imm_ud(value
.u32
), type
);
3913 if (type
== BRW_REGISTER_TYPE_DF
)
3914 return setup_imm_df(bld
, value
.f64
);
3916 return retype(brw_imm_u64(value
.u64
), type
);
3918 unreachable("Invalid type size");
3923 brw_op_for_nir_reduction_op(nir_op op
)
3926 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3927 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3928 case nir_op_imul
: return BRW_OPCODE_MUL
;
3929 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3930 case nir_op_imin
: return BRW_OPCODE_SEL
;
3931 case nir_op_umin
: return BRW_OPCODE_SEL
;
3932 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3933 case nir_op_imax
: return BRW_OPCODE_SEL
;
3934 case nir_op_umax
: return BRW_OPCODE_SEL
;
3935 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3936 case nir_op_iand
: return BRW_OPCODE_AND
;
3937 case nir_op_ior
: return BRW_OPCODE_OR
;
3938 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3940 unreachable("Invalid reduction operation");
3944 static brw_conditional_mod
3945 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3948 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3949 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3950 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3951 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3952 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3953 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3954 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3955 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3956 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3957 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3958 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3959 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3960 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3962 unreachable("Invalid reduction operation");
3967 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3968 nir_intrinsic_instr
*instr
)
3970 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3972 if (stage_prog_data
->binding_table
.image_start
> 0) {
3973 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3974 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3976 bld
.ADD(image
, image
,
3977 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3981 return bld
.emit_uniformize(image
);
3985 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3986 nir_intrinsic_instr
*instr
)
3988 /* SSBO stores are weird in that their index is in src[1] */
3989 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3992 if (nir_src_is_const(instr
->src
[src
])) {
3993 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3994 nir_src_as_uint(instr
->src
[src
]);
3995 surf_index
= brw_imm_ud(index
);
3997 surf_index
= vgrf(glsl_type::uint_type
);
3998 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3999 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4002 return bld
.emit_uniformize(surf_index
);
4006 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
4008 switch (nir_intrinsic_image_dim(instr
)) {
4009 case GLSL_SAMPLER_DIM_1D
:
4010 return 1 + nir_intrinsic_image_array(instr
);
4011 case GLSL_SAMPLER_DIM_2D
:
4012 case GLSL_SAMPLER_DIM_RECT
:
4013 return 2 + nir_intrinsic_image_array(instr
);
4014 case GLSL_SAMPLER_DIM_3D
:
4015 case GLSL_SAMPLER_DIM_CUBE
:
4017 case GLSL_SAMPLER_DIM_BUF
:
4019 case GLSL_SAMPLER_DIM_MS
:
4020 return 2 + nir_intrinsic_image_array(instr
);
4022 unreachable("Invalid image dimension");
4027 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4030 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4031 dest
= get_nir_dest(instr
->dest
);
4033 switch (instr
->intrinsic
) {
4034 case nir_intrinsic_image_load
:
4035 case nir_intrinsic_image_store
:
4036 case nir_intrinsic_image_atomic_add
:
4037 case nir_intrinsic_image_atomic_imin
:
4038 case nir_intrinsic_image_atomic_umin
:
4039 case nir_intrinsic_image_atomic_imax
:
4040 case nir_intrinsic_image_atomic_umax
:
4041 case nir_intrinsic_image_atomic_and
:
4042 case nir_intrinsic_image_atomic_or
:
4043 case nir_intrinsic_image_atomic_xor
:
4044 case nir_intrinsic_image_atomic_exchange
:
4045 case nir_intrinsic_image_atomic_comp_swap
:
4046 case nir_intrinsic_bindless_image_load
:
4047 case nir_intrinsic_bindless_image_store
:
4048 case nir_intrinsic_bindless_image_atomic_add
:
4049 case nir_intrinsic_bindless_image_atomic_imin
:
4050 case nir_intrinsic_bindless_image_atomic_umin
:
4051 case nir_intrinsic_bindless_image_atomic_imax
:
4052 case nir_intrinsic_bindless_image_atomic_umax
:
4053 case nir_intrinsic_bindless_image_atomic_and
:
4054 case nir_intrinsic_bindless_image_atomic_or
:
4055 case nir_intrinsic_bindless_image_atomic_xor
:
4056 case nir_intrinsic_bindless_image_atomic_exchange
:
4057 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4058 if (stage
== MESA_SHADER_FRAGMENT
&&
4059 instr
->intrinsic
!= nir_intrinsic_image_load
)
4060 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4062 /* Get some metadata from the image intrinsic. */
4063 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4065 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4067 switch (instr
->intrinsic
) {
4068 case nir_intrinsic_image_load
:
4069 case nir_intrinsic_image_store
:
4070 case nir_intrinsic_image_atomic_add
:
4071 case nir_intrinsic_image_atomic_imin
:
4072 case nir_intrinsic_image_atomic_umin
:
4073 case nir_intrinsic_image_atomic_imax
:
4074 case nir_intrinsic_image_atomic_umax
:
4075 case nir_intrinsic_image_atomic_and
:
4076 case nir_intrinsic_image_atomic_or
:
4077 case nir_intrinsic_image_atomic_xor
:
4078 case nir_intrinsic_image_atomic_exchange
:
4079 case nir_intrinsic_image_atomic_comp_swap
:
4080 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4081 get_nir_image_intrinsic_image(bld
, instr
);
4086 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4087 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4091 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4092 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4093 brw_imm_ud(image_intrinsic_coord_components(instr
));
4095 /* Emit an image load, store or atomic op. */
4096 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4097 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4098 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4100 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4101 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4102 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4103 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4104 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4105 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4106 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4107 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4108 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4110 unsigned num_srcs
= info
->num_srcs
;
4111 int op
= brw_aop_for_nir_intrinsic(instr
);
4112 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4113 assert(num_srcs
== 4);
4117 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4121 data
= get_nir_src(instr
->src
[3]);
4122 if (num_srcs
>= 5) {
4123 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4124 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4125 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4128 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4130 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4131 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4136 case nir_intrinsic_image_size
:
4137 case nir_intrinsic_bindless_image_size
: {
4138 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4139 * into will handle the binding table index for us in the geneerator.
4140 * Incidentally, this means that we can handle bindless with exactly the
4143 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4144 BRW_REGISTER_TYPE_UD
);
4145 image
= bld
.emit_uniformize(image
);
4147 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4148 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4149 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4151 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4152 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4153 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4154 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4156 /* Since the image size is always uniform, we can just emit a SIMD8
4157 * query instruction and splat the result out.
4159 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4161 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4162 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4163 tmp
, srcs
, ARRAY_SIZE(srcs
));
4164 inst
->size_written
= 4 * REG_SIZE
;
4166 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4167 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4168 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4169 offset(retype(dest
, tmp
.type
), bld
, c
),
4170 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4172 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4173 component(offset(tmp
, ubld
, c
), 0));
4179 case nir_intrinsic_image_load_raw_intel
: {
4180 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4181 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4182 get_nir_image_intrinsic_image(bld
, instr
);
4183 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4184 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4185 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4188 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4189 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4190 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4194 case nir_intrinsic_image_store_raw_intel
: {
4195 if (stage
== MESA_SHADER_FRAGMENT
)
4196 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4198 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4199 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4200 get_nir_image_intrinsic_image(bld
, instr
);
4201 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4202 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4203 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4204 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4206 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4207 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4211 case nir_intrinsic_scoped_memory_barrier
:
4212 case nir_intrinsic_group_memory_barrier
:
4213 case nir_intrinsic_memory_barrier_shared
:
4214 case nir_intrinsic_memory_barrier_atomic_counter
:
4215 case nir_intrinsic_memory_barrier_buffer
:
4216 case nir_intrinsic_memory_barrier_image
:
4217 case nir_intrinsic_memory_barrier
: {
4218 bool l3_fence
, slm_fence
;
4219 if (instr
->intrinsic
== nir_intrinsic_scoped_memory_barrier
) {
4220 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4221 l3_fence
= modes
& (nir_var_shader_out
|
4223 nir_var_mem_global
);
4224 /* Prior to gen11, we only have one kind of fence. */
4225 slm_fence
= devinfo
->gen
>= 11 && (modes
& nir_var_mem_shared
);
4226 l3_fence
|= devinfo
->gen
< 11 && (modes
& nir_var_mem_shared
);
4228 if (devinfo
->gen
>= 11) {
4229 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4230 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4231 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4232 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4234 /* Prior to gen11, we only have one kind of fence. */
4240 /* Be conservative in Gen11+ and always stall in a fence. Since there
4241 * are two different fences, and shader might want to synchronize
4244 * TODO: Improve NIR so that scope and visibility information for the
4245 * barriers is available here to make a better decision.
4247 * TODO: When emitting more than one fence, it might help emit all
4248 * the fences first and then generate the stall moves.
4250 const bool stall
= devinfo
->gen
>= 11;
4252 const fs_builder ubld
= bld
.group(8, 0);
4253 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4256 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4257 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4258 /* bti */ brw_imm_ud(0))
4259 ->size_written
= 2 * REG_SIZE
;
4263 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4264 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4265 brw_imm_ud(GEN7_BTI_SLM
))
4266 ->size_written
= 2 * REG_SIZE
;
4272 case nir_intrinsic_shader_clock
: {
4273 /* We cannot do anything if there is an event, so ignore it for now */
4274 const fs_reg shader_clock
= get_timestamp(bld
);
4275 const fs_reg srcs
[] = { component(shader_clock
, 0),
4276 component(shader_clock
, 1) };
4277 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4281 case nir_intrinsic_image_samples
:
4282 /* The driver does not support multi-sampled images. */
4283 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4286 case nir_intrinsic_load_uniform
: {
4287 /* Offsets are in bytes but they should always aligned to
4290 assert(instr
->const_index
[0] % 4 == 0 ||
4291 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4293 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4295 if (nir_src_is_const(instr
->src
[0])) {
4296 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4297 assert(load_offset
% type_sz(dest
.type
) == 0);
4298 /* For 16-bit types we add the module of the const_index[0]
4299 * offset to access to not 32-bit aligned element
4301 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4303 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4304 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4307 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4308 BRW_REGISTER_TYPE_UD
);
4310 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4311 * go past the end of the uniform. In order to keep the n'th
4312 * component from running past, we subtract off the size of all but
4313 * one component of the vector.
4315 assert(instr
->const_index
[1] >=
4316 instr
->num_components
* (int) type_sz(dest
.type
));
4317 unsigned read_size
= instr
->const_index
[1] -
4318 (instr
->num_components
- 1) * type_sz(dest
.type
);
4320 bool supports_64bit_indirects
=
4321 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4323 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4324 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4325 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4326 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4327 indirect
, brw_imm_ud(read_size
));
4330 const unsigned num_mov_indirects
=
4331 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4332 /* We read a little bit less per MOV INDIRECT, as they are now
4333 * 32-bits ones instead of 64-bit. Fix read_size then.
4335 const unsigned read_size_32bit
= read_size
-
4336 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4337 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4338 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4339 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4340 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4341 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4342 indirect
, brw_imm_ud(read_size_32bit
));
4350 case nir_intrinsic_load_ubo
: {
4352 if (nir_src_is_const(instr
->src
[0])) {
4353 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4354 nir_src_as_uint(instr
->src
[0]);
4355 surf_index
= brw_imm_ud(index
);
4357 /* The block index is not a constant. Evaluate the index expression
4358 * per-channel and add the base UBO index; we have to select a value
4359 * from any live channel.
4361 surf_index
= vgrf(glsl_type::uint_type
);
4362 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4363 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4364 surf_index
= bld
.emit_uniformize(surf_index
);
4367 if (!nir_src_is_const(instr
->src
[1])) {
4368 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4369 BRW_REGISTER_TYPE_UD
);
4371 for (int i
= 0; i
< instr
->num_components
; i
++)
4372 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4373 base_offset
, i
* type_sz(dest
.type
));
4375 prog_data
->has_ubo_pull
= true;
4377 /* Even if we are loading doubles, a pull constant load will load
4378 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4379 * need to load a full dvec4 we will have to emit 2 loads. This is
4380 * similar to demote_pull_constants(), except that in that case we
4381 * see individual accesses to each component of the vector and then
4382 * we let CSE deal with duplicate loads. Here we see a vector access
4383 * and we have to split it if necessary.
4385 const unsigned type_size
= type_sz(dest
.type
);
4386 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4388 /* See if we've selected this as a push constant candidate */
4389 if (nir_src_is_const(instr
->src
[0])) {
4390 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4391 const unsigned offset_256b
= load_offset
/ 32;
4394 for (int i
= 0; i
< 4; i
++) {
4395 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4396 if (range
->block
== ubo_block
&&
4397 offset_256b
>= range
->start
&&
4398 offset_256b
< range
->start
+ range
->length
) {
4400 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4401 push_reg
.offset
= load_offset
- 32 * range
->start
;
4406 if (push_reg
.file
!= BAD_FILE
) {
4407 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4408 bld
.MOV(offset(dest
, bld
, i
),
4409 byte_offset(push_reg
, i
* type_size
));
4415 prog_data
->has_ubo_pull
= true;
4417 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4418 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4419 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4421 for (unsigned c
= 0; c
< instr
->num_components
;) {
4422 const unsigned base
= load_offset
+ c
* type_size
;
4423 /* Number of usable components in the next block-aligned load. */
4424 const unsigned count
= MIN2(instr
->num_components
- c
,
4425 (block_sz
- base
% block_sz
) / type_size
);
4427 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4428 packed_consts
, surf_index
,
4429 brw_imm_ud(base
& ~(block_sz
- 1)));
4431 const fs_reg consts
=
4432 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4435 for (unsigned d
= 0; d
< count
; d
++)
4436 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4444 case nir_intrinsic_load_global
: {
4445 assert(devinfo
->gen
>= 8);
4447 if (nir_intrinsic_align(instr
) >= 4) {
4448 assert(nir_dest_bit_size(instr
->dest
) == 32);
4449 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4451 get_nir_src(instr
->src
[0]), /* Address */
4452 fs_reg(), /* No source data */
4453 brw_imm_ud(instr
->num_components
));
4454 inst
->size_written
= instr
->num_components
*
4455 inst
->dst
.component_size(inst
->exec_size
);
4457 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4458 assert(bit_size
<= 32);
4459 assert(nir_dest_num_components(instr
->dest
) == 1);
4460 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4461 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4463 get_nir_src(instr
->src
[0]), /* Address */
4464 fs_reg(), /* No source data */
4465 brw_imm_ud(bit_size
));
4466 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4471 case nir_intrinsic_store_global
:
4472 assert(devinfo
->gen
>= 8);
4474 if (stage
== MESA_SHADER_FRAGMENT
)
4475 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4477 if (nir_intrinsic_align(instr
) >= 4) {
4478 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4479 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4481 get_nir_src(instr
->src
[1]), /* Address */
4482 get_nir_src(instr
->src
[0]), /* Data */
4483 brw_imm_ud(instr
->num_components
));
4485 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4486 assert(bit_size
<= 32);
4487 assert(nir_src_num_components(instr
->src
[0]) == 1);
4488 brw_reg_type data_type
=
4489 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4490 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4491 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4492 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4494 get_nir_src(instr
->src
[1]), /* Address */
4496 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4500 case nir_intrinsic_global_atomic_add
:
4501 case nir_intrinsic_global_atomic_imin
:
4502 case nir_intrinsic_global_atomic_umin
:
4503 case nir_intrinsic_global_atomic_imax
:
4504 case nir_intrinsic_global_atomic_umax
:
4505 case nir_intrinsic_global_atomic_and
:
4506 case nir_intrinsic_global_atomic_or
:
4507 case nir_intrinsic_global_atomic_xor
:
4508 case nir_intrinsic_global_atomic_exchange
:
4509 case nir_intrinsic_global_atomic_comp_swap
:
4510 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4512 case nir_intrinsic_global_atomic_fmin
:
4513 case nir_intrinsic_global_atomic_fmax
:
4514 case nir_intrinsic_global_atomic_fcomp_swap
:
4515 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4518 case nir_intrinsic_load_ssbo
: {
4519 assert(devinfo
->gen
>= 7);
4521 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4522 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4523 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4524 get_nir_ssbo_intrinsic_index(bld
, instr
);
4525 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4526 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4528 /* Make dest unsigned because that's what the temporary will be */
4529 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4531 /* Read the vector */
4532 if (nir_intrinsic_align(instr
) >= 4) {
4533 assert(nir_dest_bit_size(instr
->dest
) == 32);
4534 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4536 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4537 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4538 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4540 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4541 assert(nir_dest_num_components(instr
->dest
) == 1);
4542 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4544 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4545 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4546 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4547 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4552 case nir_intrinsic_store_ssbo
: {
4553 assert(devinfo
->gen
>= 7);
4555 if (stage
== MESA_SHADER_FRAGMENT
)
4556 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4558 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4559 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4560 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4561 get_nir_ssbo_intrinsic_index(bld
, instr
);
4562 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4563 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4565 fs_reg data
= get_nir_src(instr
->src
[0]);
4566 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4568 assert(nir_intrinsic_write_mask(instr
) ==
4569 (1u << instr
->num_components
) - 1);
4570 if (nir_intrinsic_align(instr
) >= 4) {
4571 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4572 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4573 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4574 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4575 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4576 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4578 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4579 assert(nir_src_num_components(instr
->src
[0]) == 1);
4580 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4582 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4583 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4585 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4586 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4591 case nir_intrinsic_store_output
: {
4592 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4593 fs_reg src
= get_nir_src(instr
->src
[0]);
4595 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4596 unsigned num_components
= instr
->num_components
;
4597 unsigned first_component
= nir_intrinsic_component(instr
);
4599 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4600 4 * store_offset
), src
.type
);
4601 for (unsigned j
= 0; j
< num_components
; j
++) {
4602 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4603 offset(src
, bld
, j
));
4608 case nir_intrinsic_ssbo_atomic_add
:
4609 case nir_intrinsic_ssbo_atomic_imin
:
4610 case nir_intrinsic_ssbo_atomic_umin
:
4611 case nir_intrinsic_ssbo_atomic_imax
:
4612 case nir_intrinsic_ssbo_atomic_umax
:
4613 case nir_intrinsic_ssbo_atomic_and
:
4614 case nir_intrinsic_ssbo_atomic_or
:
4615 case nir_intrinsic_ssbo_atomic_xor
:
4616 case nir_intrinsic_ssbo_atomic_exchange
:
4617 case nir_intrinsic_ssbo_atomic_comp_swap
:
4618 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4620 case nir_intrinsic_ssbo_atomic_fmin
:
4621 case nir_intrinsic_ssbo_atomic_fmax
:
4622 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4623 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4626 case nir_intrinsic_get_buffer_size
: {
4627 assert(nir_src_num_components(instr
->src
[0]) == 1);
4628 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4629 nir_src_as_uint(instr
->src
[0]) : 0;
4631 /* A resinfo's sampler message is used to get the buffer size. The
4632 * SIMD8's writeback message consists of four registers and SIMD16's
4633 * writeback message consists of 8 destination registers (two per each
4634 * component). Because we are only interested on the first channel of
4635 * the first returned component, where resinfo returns the buffer size
4636 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4637 * the dispatch width.
4639 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4640 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4641 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4644 ubld
.MOV(src_payload
, brw_imm_d(0));
4646 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4647 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4648 src_payload
, brw_imm_ud(index
));
4649 inst
->header_size
= 0;
4651 inst
->size_written
= 4 * REG_SIZE
;
4653 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4655 * "Out-of-bounds checking is always performed at a DWord granularity. If
4656 * any part of the DWord is out-of-bounds then the whole DWord is
4657 * considered out-of-bounds."
4659 * This implies that types with size smaller than 4-bytes need to be
4660 * padded if they don't complete the last dword of the buffer. But as we
4661 * need to maintain the original size we need to reverse the padding
4662 * calculation to return the correct size to know the number of elements
4663 * of an unsized array. As we stored in the last two bits of the surface
4664 * size the needed padding for the buffer, we calculate here the
4665 * original buffer_size reversing the surface_size calculation:
4667 * surface_size = isl_align(buffer_size, 4) +
4668 * (isl_align(buffer_size) - buffer_size)
4670 * buffer_size = surface_size & ~3 - surface_size & 3
4673 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4674 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4675 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4677 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4678 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4679 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4681 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4685 case nir_intrinsic_load_subgroup_size
:
4686 /* This should only happen for fragment shaders because every other case
4687 * is lowered in NIR so we can optimize on it.
4689 assert(stage
== MESA_SHADER_FRAGMENT
);
4690 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4693 case nir_intrinsic_load_subgroup_invocation
:
4694 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4695 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4698 case nir_intrinsic_load_subgroup_eq_mask
:
4699 case nir_intrinsic_load_subgroup_ge_mask
:
4700 case nir_intrinsic_load_subgroup_gt_mask
:
4701 case nir_intrinsic_load_subgroup_le_mask
:
4702 case nir_intrinsic_load_subgroup_lt_mask
:
4703 unreachable("not reached");
4705 case nir_intrinsic_vote_any
: {
4706 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4708 /* The any/all predicates do not consider channel enables. To prevent
4709 * dead channels from affecting the result, we initialize the flag with
4710 * with the identity value for the logical operation.
4712 if (dispatch_width
== 32) {
4713 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4714 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4717 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4719 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4721 /* For some reason, the any/all predicates don't work properly with
4722 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4723 * doesn't read the correct subset of the flag register and you end up
4724 * getting garbage in the second half. Work around this by using a pair
4725 * of 1-wide MOVs and scattering the result.
4727 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4728 ubld
.MOV(res1
, brw_imm_d(0));
4729 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4730 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4731 BRW_PREDICATE_ALIGN1_ANY32H
,
4732 ubld
.MOV(res1
, brw_imm_d(-1)));
4734 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4737 case nir_intrinsic_vote_all
: {
4738 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4740 /* The any/all predicates do not consider channel enables. To prevent
4741 * dead channels from affecting the result, we initialize the flag with
4742 * with the identity value for the logical operation.
4744 if (dispatch_width
== 32) {
4745 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4746 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4747 brw_imm_ud(0xffffffff));
4749 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4751 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4753 /* For some reason, the any/all predicates don't work properly with
4754 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4755 * doesn't read the correct subset of the flag register and you end up
4756 * getting garbage in the second half. Work around this by using a pair
4757 * of 1-wide MOVs and scattering the result.
4759 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4760 ubld
.MOV(res1
, brw_imm_d(0));
4761 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4762 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4763 BRW_PREDICATE_ALIGN1_ALL32H
,
4764 ubld
.MOV(res1
, brw_imm_d(-1)));
4766 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4769 case nir_intrinsic_vote_feq
:
4770 case nir_intrinsic_vote_ieq
: {
4771 fs_reg value
= get_nir_src(instr
->src
[0]);
4772 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4773 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4774 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4775 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4778 fs_reg uniformized
= bld
.emit_uniformize(value
);
4779 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4781 /* The any/all predicates do not consider channel enables. To prevent
4782 * dead channels from affecting the result, we initialize the flag with
4783 * with the identity value for the logical operation.
4785 if (dispatch_width
== 32) {
4786 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4787 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4788 brw_imm_ud(0xffffffff));
4790 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4792 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4794 /* For some reason, the any/all predicates don't work properly with
4795 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4796 * doesn't read the correct subset of the flag register and you end up
4797 * getting garbage in the second half. Work around this by using a pair
4798 * of 1-wide MOVs and scattering the result.
4800 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4801 ubld
.MOV(res1
, brw_imm_d(0));
4802 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4803 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4804 BRW_PREDICATE_ALIGN1_ALL32H
,
4805 ubld
.MOV(res1
, brw_imm_d(-1)));
4807 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4811 case nir_intrinsic_ballot
: {
4812 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4813 BRW_REGISTER_TYPE_UD
);
4814 struct brw_reg flag
= brw_flag_reg(0, 0);
4815 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4816 * as f0.0. This is a problem for fragment programs as we currently use
4817 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4818 * programs yet so this isn't a problem. When we do, something will
4821 if (dispatch_width
== 32)
4822 flag
.type
= BRW_REGISTER_TYPE_UD
;
4824 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4825 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4827 if (instr
->dest
.ssa
.bit_size
> 32) {
4828 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4830 dest
.type
= BRW_REGISTER_TYPE_UD
;
4832 bld
.MOV(dest
, flag
);
4836 case nir_intrinsic_read_invocation
: {
4837 const fs_reg value
= get_nir_src(instr
->src
[0]);
4838 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4839 fs_reg tmp
= bld
.vgrf(value
.type
);
4841 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4842 bld
.emit_uniformize(invocation
));
4844 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4848 case nir_intrinsic_read_first_invocation
: {
4849 const fs_reg value
= get_nir_src(instr
->src
[0]);
4850 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4854 case nir_intrinsic_shuffle
: {
4855 const fs_reg value
= get_nir_src(instr
->src
[0]);
4856 const fs_reg index
= get_nir_src(instr
->src
[1]);
4858 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4862 case nir_intrinsic_first_invocation
: {
4863 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4864 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4865 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4866 fs_reg(component(tmp
, 0)));
4870 case nir_intrinsic_quad_broadcast
: {
4871 const fs_reg value
= get_nir_src(instr
->src
[0]);
4872 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4874 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4875 value
, brw_imm_ud(index
), brw_imm_ud(4));
4879 case nir_intrinsic_quad_swap_horizontal
: {
4880 const fs_reg value
= get_nir_src(instr
->src
[0]);
4881 const fs_reg tmp
= bld
.vgrf(value
.type
);
4882 if (devinfo
->gen
<= 7) {
4883 /* The hardware doesn't seem to support these crazy regions with
4884 * compressed instructions on gen7 and earlier so we fall back to
4885 * using quad swizzles. Fortunately, we don't support 64-bit
4886 * anything in Vulkan on gen7.
4888 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4889 const fs_builder ubld
= bld
.exec_all();
4890 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4891 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
4892 bld
.MOV(retype(dest
, value
.type
), tmp
);
4894 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4896 const fs_reg src_left
= horiz_stride(value
, 2);
4897 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4898 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4899 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4901 ubld
.MOV(tmp_left
, src_right
);
4902 ubld
.MOV(tmp_right
, src_left
);
4905 bld
.MOV(retype(dest
, value
.type
), tmp
);
4909 case nir_intrinsic_quad_swap_vertical
: {
4910 const fs_reg value
= get_nir_src(instr
->src
[0]);
4911 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4912 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4913 const fs_reg tmp
= bld
.vgrf(value
.type
);
4914 const fs_builder ubld
= bld
.exec_all();
4915 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4916 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4917 bld
.MOV(retype(dest
, value
.type
), tmp
);
4919 /* For larger data types, we have to either emit dispatch_width many
4920 * MOVs or else fall back to doing indirects.
4922 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4923 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4925 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4930 case nir_intrinsic_quad_swap_diagonal
: {
4931 const fs_reg value
= get_nir_src(instr
->src
[0]);
4932 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4933 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4934 const fs_reg tmp
= bld
.vgrf(value
.type
);
4935 const fs_builder ubld
= bld
.exec_all();
4936 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4937 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4938 bld
.MOV(retype(dest
, value
.type
), tmp
);
4940 /* For larger data types, we have to either emit dispatch_width many
4941 * MOVs or else fall back to doing indirects.
4943 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4944 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4946 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4951 case nir_intrinsic_reduce
: {
4952 fs_reg src
= get_nir_src(instr
->src
[0]);
4953 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4954 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4955 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4956 cluster_size
= dispatch_width
;
4958 /* Figure out the source type */
4959 src
.type
= brw_type_for_nir_type(devinfo
,
4960 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4961 nir_src_bit_size(instr
->src
[0])));
4963 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4964 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4965 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4967 /* There are a couple of register region issues that make things
4968 * complicated for 8-bit types:
4970 * 1. Only raw moves are allowed to write to a packed 8-bit
4972 * 2. If we use a strided destination, the efficient way to do scan
4973 * operations ends up using strides that are too big to encode in
4976 * To get around these issues, we just do all 8-bit scan operations in
4977 * 16 bits. It's actually fewer instructions than what we'd have to do
4978 * if we were trying to do it in native 8-bit types and the results are
4979 * the same once we truncate to 8 bits at the end.
4981 brw_reg_type scan_type
= src
.type
;
4982 if (type_sz(scan_type
) == 1)
4983 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
4985 /* Set up a register for all of our scratching around and initialize it
4986 * to reduction operation's identity value.
4988 fs_reg scan
= bld
.vgrf(scan_type
);
4989 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4991 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4993 dest
.type
= src
.type
;
4994 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4995 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4996 * the distance between clusters is at least 2 GRFs. In this case,
4997 * we don't need the weird striding of the CLUSTER_BROADCAST
4998 * instruction and can just do regular MOVs.
5000 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5001 const unsigned groups
=
5002 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5003 const unsigned group_size
= dispatch_width
/ groups
;
5004 for (unsigned i
= 0; i
< groups
; i
++) {
5005 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5006 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5007 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5008 component(scan
, comp
));
5011 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5012 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5017 case nir_intrinsic_inclusive_scan
:
5018 case nir_intrinsic_exclusive_scan
: {
5019 fs_reg src
= get_nir_src(instr
->src
[0]);
5020 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5022 /* Figure out the source type */
5023 src
.type
= brw_type_for_nir_type(devinfo
,
5024 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5025 nir_src_bit_size(instr
->src
[0])));
5027 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5028 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5029 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5031 /* There are a couple of register region issues that make things
5032 * complicated for 8-bit types:
5034 * 1. Only raw moves are allowed to write to a packed 8-bit
5036 * 2. If we use a strided destination, the efficient way to do scan
5037 * operations ends up using strides that are too big to encode in
5040 * To get around these issues, we just do all 8-bit scan operations in
5041 * 16 bits. It's actually fewer instructions than what we'd have to do
5042 * if we were trying to do it in native 8-bit types and the results are
5043 * the same once we truncate to 8 bits at the end.
5045 brw_reg_type scan_type
= src
.type
;
5046 if (type_sz(scan_type
) == 1)
5047 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5049 /* Set up a register for all of our scratching around and initialize it
5050 * to reduction operation's identity value.
5052 fs_reg scan
= bld
.vgrf(scan_type
);
5053 const fs_builder allbld
= bld
.exec_all();
5054 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5056 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5057 /* Exclusive scan is a bit harder because we have to do an annoying
5058 * shift of the contents before we can begin. To make things worse,
5059 * we can't do this with a normal stride; we have to use indirects.
5061 fs_reg shifted
= bld
.vgrf(scan_type
);
5062 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5063 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5065 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5066 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5070 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5072 bld
.MOV(retype(dest
, src
.type
), scan
);
5076 case nir_intrinsic_begin_invocation_interlock
: {
5077 const fs_builder ubld
= bld
.group(8, 0);
5078 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5080 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5081 ->size_written
= 2 * REG_SIZE
;
5085 case nir_intrinsic_end_invocation_interlock
: {
5086 /* For endInvocationInterlock(), we need to insert a memory fence which
5087 * stalls in the shader until the memory transactions prior to that
5088 * fence are complete. This ensures that the shader does not end before
5089 * any writes from its critical section have landed. Otherwise, you can
5090 * end up with a case where the next invocation on that pixel properly
5091 * stalls for previous FS invocation on its pixel to complete but
5092 * doesn't actually wait for the dataport memory transactions from that
5093 * thread to land before submitting its own.
5095 const fs_builder ubld
= bld
.group(8, 0);
5096 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5097 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5098 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5099 ->size_written
= 2 * REG_SIZE
;
5104 unreachable("unknown intrinsic");
5109 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5110 int op
, nir_intrinsic_instr
*instr
)
5112 if (stage
== MESA_SHADER_FRAGMENT
)
5113 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5115 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5116 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5117 * appear to exist. However, if you look at Vol 2a, there are no message
5118 * descriptors provided for Qword atomic ops except for A64 messages.
5120 assert(nir_dest_bit_size(instr
->dest
) == 32);
5123 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5124 dest
= get_nir_dest(instr
->dest
);
5126 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5127 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5128 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5129 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5130 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5133 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5134 data
= get_nir_src(instr
->src
[2]);
5136 if (op
== BRW_AOP_CMPWR
) {
5137 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5138 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5139 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5142 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5144 /* Emit the actual atomic operation */
5146 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5147 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5151 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5152 int op
, nir_intrinsic_instr
*instr
)
5154 if (stage
== MESA_SHADER_FRAGMENT
)
5155 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5158 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5159 dest
= get_nir_dest(instr
->dest
);
5161 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5162 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5163 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5164 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5165 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5167 fs_reg data
= get_nir_src(instr
->src
[2]);
5168 if (op
== BRW_AOP_FCMPWR
) {
5169 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5170 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5171 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5174 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5176 /* Emit the actual atomic operation */
5178 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5179 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5183 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5184 int op
, nir_intrinsic_instr
*instr
)
5187 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5188 dest
= get_nir_dest(instr
->dest
);
5190 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5191 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5192 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5193 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5196 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5197 data
= get_nir_src(instr
->src
[1]);
5198 if (op
== BRW_AOP_CMPWR
) {
5199 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5200 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5201 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5204 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5206 /* Get the offset */
5207 if (nir_src_is_const(instr
->src
[0])) {
5208 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5209 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5211 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5212 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5213 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5214 brw_imm_ud(instr
->const_index
[0]));
5217 /* Emit the actual atomic operation operation */
5219 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5220 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5224 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5225 int op
, nir_intrinsic_instr
*instr
)
5228 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5229 dest
= get_nir_dest(instr
->dest
);
5231 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5232 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5233 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5234 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5236 fs_reg data
= get_nir_src(instr
->src
[1]);
5237 if (op
== BRW_AOP_FCMPWR
) {
5238 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5239 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5240 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5243 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5245 /* Get the offset */
5246 if (nir_src_is_const(instr
->src
[0])) {
5247 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5248 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5250 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5251 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5252 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5253 brw_imm_ud(instr
->const_index
[0]));
5256 /* Emit the actual atomic operation operation */
5258 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5259 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5263 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5264 int op
, nir_intrinsic_instr
*instr
)
5266 if (stage
== MESA_SHADER_FRAGMENT
)
5267 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5270 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5271 dest
= get_nir_dest(instr
->dest
);
5273 fs_reg addr
= get_nir_src(instr
->src
[0]);
5276 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5277 data
= get_nir_src(instr
->src
[1]);
5279 if (op
== BRW_AOP_CMPWR
) {
5280 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5281 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5282 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5286 if (nir_dest_bit_size(instr
->dest
) == 64) {
5287 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5288 dest
, addr
, data
, brw_imm_ud(op
));
5290 assert(nir_dest_bit_size(instr
->dest
) == 32);
5291 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5292 dest
, addr
, data
, brw_imm_ud(op
));
5297 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5298 int op
, nir_intrinsic_instr
*instr
)
5300 if (stage
== MESA_SHADER_FRAGMENT
)
5301 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5303 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5304 fs_reg dest
= get_nir_dest(instr
->dest
);
5306 fs_reg addr
= get_nir_src(instr
->src
[0]);
5308 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5309 fs_reg data
= get_nir_src(instr
->src
[1]);
5311 if (op
== BRW_AOP_FCMPWR
) {
5312 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5313 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5314 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5318 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5319 dest
, addr
, data
, brw_imm_ud(op
));
5323 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5325 unsigned texture
= instr
->texture_index
;
5326 unsigned sampler
= instr
->sampler_index
;
5328 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5330 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5331 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5333 int lod_components
= 0;
5335 /* The hardware requires a LOD for buffer textures */
5336 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5337 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5339 uint32_t header_bits
= 0;
5340 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5341 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5342 switch (instr
->src
[i
].src_type
) {
5343 case nir_tex_src_bias
:
5344 srcs
[TEX_LOGICAL_SRC_LOD
] =
5345 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5347 case nir_tex_src_comparator
:
5348 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5350 case nir_tex_src_coord
:
5351 switch (instr
->op
) {
5353 case nir_texop_txf_ms
:
5354 case nir_texop_txf_ms_mcs
:
5355 case nir_texop_samples_identical
:
5356 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5359 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5363 case nir_tex_src_ddx
:
5364 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5365 lod_components
= nir_tex_instr_src_size(instr
, i
);
5367 case nir_tex_src_ddy
:
5368 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5370 case nir_tex_src_lod
:
5371 switch (instr
->op
) {
5373 srcs
[TEX_LOGICAL_SRC_LOD
] =
5374 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5377 srcs
[TEX_LOGICAL_SRC_LOD
] =
5378 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5381 srcs
[TEX_LOGICAL_SRC_LOD
] =
5382 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5386 case nir_tex_src_min_lod
:
5387 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5388 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5390 case nir_tex_src_ms_index
:
5391 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5394 case nir_tex_src_offset
: {
5395 uint32_t offset_bits
= 0;
5396 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5397 header_bits
|= offset_bits
;
5399 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5400 retype(src
, BRW_REGISTER_TYPE_D
);
5405 case nir_tex_src_projector
:
5406 unreachable("should be lowered");
5408 case nir_tex_src_texture_offset
: {
5409 /* Emit code to evaluate the actual indexing expression */
5410 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5411 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5412 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5416 case nir_tex_src_sampler_offset
: {
5417 /* Emit code to evaluate the actual indexing expression */
5418 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5419 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5420 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5424 case nir_tex_src_texture_handle
:
5425 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5426 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5427 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5430 case nir_tex_src_sampler_handle
:
5431 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5432 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5433 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5436 case nir_tex_src_ms_mcs
:
5437 assert(instr
->op
== nir_texop_txf_ms
);
5438 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5441 case nir_tex_src_plane
: {
5442 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5443 const uint32_t texture_index
=
5444 instr
->texture_index
+
5445 stage_prog_data
->binding_table
.plane_start
[plane
] -
5446 stage_prog_data
->binding_table
.texture_start
;
5448 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5453 unreachable("unknown texture source");
5457 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5458 (instr
->op
== nir_texop_txf_ms
||
5459 instr
->op
== nir_texop_samples_identical
)) {
5460 if (devinfo
->gen
>= 7 &&
5461 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5462 srcs
[TEX_LOGICAL_SRC_MCS
] =
5463 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5464 instr
->coord_components
,
5465 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5466 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5468 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5472 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5473 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5476 switch (instr
->op
) {
5478 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5481 opcode
= FS_OPCODE_TXB_LOGICAL
;
5484 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5487 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5490 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5492 case nir_texop_txf_ms
:
5493 if ((key_tex
->msaa_16
& (1 << sampler
)))
5494 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5496 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5498 case nir_texop_txf_ms_mcs
:
5499 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5501 case nir_texop_query_levels
:
5503 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5506 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5509 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5510 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5512 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5514 case nir_texop_texture_samples
:
5515 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5517 case nir_texop_samples_identical
: {
5518 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5520 /* If mcs is an immediate value, it means there is no MCS. In that case
5521 * just return false.
5523 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5524 bld
.MOV(dst
, brw_imm_ud(0u));
5525 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5526 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5527 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5528 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5529 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5531 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5532 BRW_CONDITIONAL_EQ
);
5537 unreachable("unknown texture opcode");
5540 if (instr
->op
== nir_texop_tg4
) {
5541 if (instr
->component
== 1 &&
5542 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5543 /* gather4 sampler is broken for green channel on RG32F --
5544 * we must ask for blue instead.
5546 header_bits
|= 2 << 16;
5548 header_bits
|= instr
->component
<< 16;
5552 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5553 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5554 inst
->offset
= header_bits
;
5556 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5557 if (devinfo
->gen
>= 9 &&
5558 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5559 unsigned write_mask
= instr
->dest
.is_ssa
?
5560 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5561 (1 << dest_size
) - 1;
5562 assert(write_mask
!= 0); /* dead code should have been eliminated */
5563 inst
->size_written
= util_last_bit(write_mask
) *
5564 inst
->dst
.component_size(inst
->exec_size
);
5566 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5569 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5570 inst
->shadow_compare
= true;
5572 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5573 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5576 for (unsigned i
= 0; i
< dest_size
; i
++)
5577 nir_dest
[i
] = offset(dst
, bld
, i
);
5579 if (instr
->op
== nir_texop_query_levels
) {
5580 /* # levels is in .w */
5581 nir_dest
[0] = offset(dst
, bld
, 3);
5582 } else if (instr
->op
== nir_texop_txs
&&
5583 dest_size
>= 3 && devinfo
->gen
< 7) {
5584 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5585 fs_reg depth
= offset(dst
, bld
, 2);
5586 nir_dest
[2] = vgrf(glsl_type::int_type
);
5587 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5590 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5594 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5596 switch (instr
->type
) {
5597 case nir_jump_break
:
5598 bld
.emit(BRW_OPCODE_BREAK
);
5600 case nir_jump_continue
:
5601 bld
.emit(BRW_OPCODE_CONTINUE
);
5603 case nir_jump_return
:
5605 unreachable("unknown jump");
5610 * This helper takes a source register and un/shuffles it into the destination
5613 * If source type size is smaller than destination type size the operation
5614 * needed is a component shuffle. The opposite case would be an unshuffle. If
5615 * source/destination type size is equal a shuffle is done that would be
5616 * equivalent to a simple MOV.
5618 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5619 * components .xyz 16-bit vector on SIMD8 would be.
5621 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5622 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5624 * This helper will return the following 2 32-bit components with the 16-bit
5627 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5628 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5630 * For unshuffle, the example would be the opposite, a 64-bit type source
5631 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5634 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5635 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5636 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5637 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5639 * The returned result would be the following 4 32-bit components unshuffled:
5641 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5642 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5643 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5644 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5646 * - Source and destination register must not be overlapped.
5647 * - components units are measured in terms of the smaller type between
5648 * source and destination because we are un/shuffling the smaller
5649 * components from/into the bigger ones.
5650 * - first_component parameter allows skipping source components.
5653 shuffle_src_to_dst(const fs_builder
&bld
,
5656 uint32_t first_component
,
5657 uint32_t components
)
5659 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5660 assert(!regions_overlap(dst
,
5661 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5662 offset(src
, bld
, first_component
),
5663 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5664 for (unsigned i
= 0; i
< components
; i
++) {
5665 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5666 offset(src
, bld
, i
+ first_component
));
5668 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5669 /* Source is shuffled into destination */
5670 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5671 assert(!regions_overlap(dst
,
5672 type_sz(dst
.type
) * bld
.dispatch_width() *
5673 DIV_ROUND_UP(components
, size_ratio
),
5674 offset(src
, bld
, first_component
),
5675 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5677 brw_reg_type shuffle_type
=
5678 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5679 BRW_REGISTER_TYPE_D
);
5680 for (unsigned i
= 0; i
< components
; i
++) {
5681 fs_reg shuffle_component_i
=
5682 subscript(offset(dst
, bld
, i
/ size_ratio
),
5683 shuffle_type
, i
% size_ratio
);
5684 bld
.MOV(shuffle_component_i
,
5685 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5688 /* Source is unshuffled into destination */
5689 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5690 assert(!regions_overlap(dst
,
5691 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5692 offset(src
, bld
, first_component
/ size_ratio
),
5693 type_sz(src
.type
) * bld
.dispatch_width() *
5694 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5697 brw_reg_type shuffle_type
=
5698 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5699 BRW_REGISTER_TYPE_D
);
5700 for (unsigned i
= 0; i
< components
; i
++) {
5701 fs_reg shuffle_component_i
=
5702 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5703 shuffle_type
, (first_component
+ i
) % size_ratio
);
5704 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5705 shuffle_component_i
);
5711 shuffle_from_32bit_read(const fs_builder
&bld
,
5714 uint32_t first_component
,
5715 uint32_t components
)
5717 assert(type_sz(src
.type
) == 4);
5719 /* This function takes components in units of the destination type while
5720 * shuffle_src_to_dst takes components in units of the smallest type
5722 if (type_sz(dst
.type
) > 4) {
5723 assert(type_sz(dst
.type
) == 8);
5724 first_component
*= 2;
5728 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5732 setup_imm_df(const fs_builder
&bld
, double v
)
5734 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5735 assert(devinfo
->gen
>= 7);
5737 if (devinfo
->gen
>= 8)
5738 return brw_imm_df(v
);
5740 /* gen7.5 does not support DF immediates straighforward but the DIM
5741 * instruction allows to set the 64-bit immediate value.
5743 if (devinfo
->is_haswell
) {
5744 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5745 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5746 ubld
.DIM(dst
, brw_imm_df(v
));
5747 return component(dst
, 0);
5750 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5751 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5752 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5754 * Alternatively, we could also produce a normal VGRF (without stride 0)
5755 * by writing to all the channels in the VGRF, however, that would hit the
5756 * gen7 bug where we have to split writes that span more than 1 register
5757 * into instructions with a width of 4 (otherwise the write to the second
5758 * register written runs into an execmask hardware bug) which isn't very
5771 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5772 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5773 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5774 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5776 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5780 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5782 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5783 bld
.MOV(tmp
, brw_imm_w(v
));
5788 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5790 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5791 bld
.MOV(tmp
, brw_imm_uw(v
));