037fe780d37b3e536b0b3038108f75b8a7949078
[mesa.git] / src / intel / compiler / brw_nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_nir.h"
25 #include "brw_shader.h"
26 #include "dev/gen_debug.h"
27 #include "compiler/glsl_types.h"
28 #include "compiler/nir/nir_builder.h"
29 #include "util/u_math.h"
30
31 static bool
32 remap_tess_levels(nir_builder *b, nir_intrinsic_instr *intr,
33 GLenum primitive_mode)
34 {
35 const int location = nir_intrinsic_base(intr);
36 const unsigned component = nir_intrinsic_component(intr);
37 bool out_of_bounds;
38
39 if (location == VARYING_SLOT_TESS_LEVEL_INNER) {
40 switch (primitive_mode) {
41 case GL_QUADS:
42 /* gl_TessLevelInner[0..1] lives at DWords 3-2 (reversed). */
43 nir_intrinsic_set_base(intr, 0);
44 nir_intrinsic_set_component(intr, 3 - component);
45 out_of_bounds = false;
46 break;
47 case GL_TRIANGLES:
48 /* gl_TessLevelInner[0] lives at DWord 4. */
49 nir_intrinsic_set_base(intr, 1);
50 out_of_bounds = component > 0;
51 break;
52 case GL_ISOLINES:
53 out_of_bounds = true;
54 break;
55 default:
56 unreachable("Bogus tessellation domain");
57 }
58 } else if (location == VARYING_SLOT_TESS_LEVEL_OUTER) {
59 if (primitive_mode == GL_ISOLINES) {
60 /* gl_TessLevelOuter[0..1] lives at DWords 6-7 (in order). */
61 nir_intrinsic_set_base(intr, 1);
62 nir_intrinsic_set_component(intr, 2 + nir_intrinsic_component(intr));
63 out_of_bounds = component > 1;
64 } else {
65 /* Triangles use DWords 7-5 (reversed); Quads use 7-4 (reversed) */
66 nir_intrinsic_set_base(intr, 1);
67 nir_intrinsic_set_component(intr, 3 - nir_intrinsic_component(intr));
68 out_of_bounds = component == 3 && primitive_mode == GL_TRIANGLES;
69 }
70 } else {
71 return false;
72 }
73
74 if (out_of_bounds) {
75 if (nir_intrinsic_infos[intr->intrinsic].has_dest) {
76 b->cursor = nir_before_instr(&intr->instr);
77 nir_ssa_def *undef = nir_ssa_undef(b, 1, 32);
78 nir_ssa_def_rewrite_uses(&intr->dest.ssa, nir_src_for_ssa(undef));
79 }
80 nir_instr_remove(&intr->instr);
81 }
82
83 return true;
84 }
85
86 static bool
87 is_input(nir_intrinsic_instr *intrin)
88 {
89 return intrin->intrinsic == nir_intrinsic_load_input ||
90 intrin->intrinsic == nir_intrinsic_load_per_vertex_input ||
91 intrin->intrinsic == nir_intrinsic_load_interpolated_input;
92 }
93
94 static bool
95 is_output(nir_intrinsic_instr *intrin)
96 {
97 return intrin->intrinsic == nir_intrinsic_load_output ||
98 intrin->intrinsic == nir_intrinsic_load_per_vertex_output ||
99 intrin->intrinsic == nir_intrinsic_store_output ||
100 intrin->intrinsic == nir_intrinsic_store_per_vertex_output;
101 }
102
103
104 static bool
105 remap_patch_urb_offsets(nir_block *block, nir_builder *b,
106 const struct brw_vue_map *vue_map,
107 GLenum tes_primitive_mode)
108 {
109 const bool is_passthrough_tcs = b->shader->info.name &&
110 strcmp(b->shader->info.name, "passthrough") == 0;
111
112 nir_foreach_instr_safe(instr, block) {
113 if (instr->type != nir_instr_type_intrinsic)
114 continue;
115
116 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
117
118 gl_shader_stage stage = b->shader->info.stage;
119
120 if ((stage == MESA_SHADER_TESS_CTRL && is_output(intrin)) ||
121 (stage == MESA_SHADER_TESS_EVAL && is_input(intrin))) {
122
123 if (!is_passthrough_tcs &&
124 remap_tess_levels(b, intrin, tes_primitive_mode))
125 continue;
126
127 int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
128 assert(vue_slot != -1);
129 intrin->const_index[0] = vue_slot;
130
131 nir_src *vertex = nir_get_io_vertex_index_src(intrin);
132 if (vertex) {
133 if (nir_src_is_const(*vertex)) {
134 intrin->const_index[0] += nir_src_as_uint(*vertex) *
135 vue_map->num_per_vertex_slots;
136 } else {
137 b->cursor = nir_before_instr(&intrin->instr);
138
139 /* Multiply by the number of per-vertex slots. */
140 nir_ssa_def *vertex_offset =
141 nir_imul(b,
142 nir_ssa_for_src(b, *vertex, 1),
143 nir_imm_int(b,
144 vue_map->num_per_vertex_slots));
145
146 /* Add it to the existing offset */
147 nir_src *offset = nir_get_io_offset_src(intrin);
148 nir_ssa_def *total_offset =
149 nir_iadd(b, vertex_offset,
150 nir_ssa_for_src(b, *offset, 1));
151
152 nir_instr_rewrite_src(&intrin->instr, offset,
153 nir_src_for_ssa(total_offset));
154 }
155 }
156 }
157 }
158 return true;
159 }
160
161 void
162 brw_nir_lower_vs_inputs(nir_shader *nir,
163 const uint8_t *vs_attrib_wa_flags)
164 {
165 /* Start with the location of the variable's base. */
166 nir_foreach_shader_in_variable(var, nir)
167 var->data.driver_location = var->data.location;
168
169 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
170 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
171 * whether it is a double-precision type or not.
172 */
173 nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
174 nir_lower_io_lower_64bit_to_32);
175
176 /* This pass needs actual constants */
177 nir_opt_constant_folding(nir);
178
179 nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
180
181 brw_nir_apply_attribute_workarounds(nir, vs_attrib_wa_flags);
182
183 /* The last step is to remap VERT_ATTRIB_* to actual registers */
184
185 /* Whether or not we have any system generated values. gl_DrawID is not
186 * included here as it lives in its own vec4.
187 */
188 const bool has_sgvs =
189 nir->info.system_values_read &
190 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX) |
191 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE) |
192 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) |
193 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID));
194
195 const unsigned num_inputs = util_bitcount64(nir->info.inputs_read);
196
197 nir_foreach_function(function, nir) {
198 if (!function->impl)
199 continue;
200
201 nir_builder b;
202 nir_builder_init(&b, function->impl);
203
204 nir_foreach_block(block, function->impl) {
205 nir_foreach_instr_safe(instr, block) {
206 if (instr->type != nir_instr_type_intrinsic)
207 continue;
208
209 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
210
211 switch (intrin->intrinsic) {
212 case nir_intrinsic_load_first_vertex:
213 case nir_intrinsic_load_base_instance:
214 case nir_intrinsic_load_vertex_id_zero_base:
215 case nir_intrinsic_load_instance_id:
216 case nir_intrinsic_load_is_indexed_draw:
217 case nir_intrinsic_load_draw_id: {
218 b.cursor = nir_after_instr(&intrin->instr);
219
220 /* gl_VertexID and friends are stored by the VF as the last
221 * vertex element. We convert them to load_input intrinsics at
222 * the right location.
223 */
224 nir_intrinsic_instr *load =
225 nir_intrinsic_instr_create(nir, nir_intrinsic_load_input);
226 load->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
227
228 nir_intrinsic_set_base(load, num_inputs);
229 switch (intrin->intrinsic) {
230 case nir_intrinsic_load_first_vertex:
231 nir_intrinsic_set_component(load, 0);
232 break;
233 case nir_intrinsic_load_base_instance:
234 nir_intrinsic_set_component(load, 1);
235 break;
236 case nir_intrinsic_load_vertex_id_zero_base:
237 nir_intrinsic_set_component(load, 2);
238 break;
239 case nir_intrinsic_load_instance_id:
240 nir_intrinsic_set_component(load, 3);
241 break;
242 case nir_intrinsic_load_draw_id:
243 case nir_intrinsic_load_is_indexed_draw:
244 /* gl_DrawID and IsIndexedDraw are stored right after
245 * gl_VertexID and friends if any of them exist.
246 */
247 nir_intrinsic_set_base(load, num_inputs + has_sgvs);
248 if (intrin->intrinsic == nir_intrinsic_load_draw_id)
249 nir_intrinsic_set_component(load, 0);
250 else
251 nir_intrinsic_set_component(load, 1);
252 break;
253 default:
254 unreachable("Invalid system value intrinsic");
255 }
256
257 load->num_components = 1;
258 nir_ssa_dest_init(&load->instr, &load->dest, 1, 32, NULL);
259 nir_builder_instr_insert(&b, &load->instr);
260
261 nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
262 nir_src_for_ssa(&load->dest.ssa));
263 nir_instr_remove(&intrin->instr);
264 break;
265 }
266
267 case nir_intrinsic_load_input: {
268 /* Attributes come in a contiguous block, ordered by their
269 * gl_vert_attrib value. That means we can compute the slot
270 * number for an attribute by masking out the enabled attributes
271 * before it and counting the bits.
272 */
273 int attr = nir_intrinsic_base(intrin);
274 int slot = util_bitcount64(nir->info.inputs_read &
275 BITFIELD64_MASK(attr));
276 nir_intrinsic_set_base(intrin, slot);
277 break;
278 }
279
280 default:
281 break; /* Nothing to do */
282 }
283 }
284 }
285 }
286 }
287
288 void
289 brw_nir_lower_vue_inputs(nir_shader *nir,
290 const struct brw_vue_map *vue_map)
291 {
292 nir_foreach_shader_in_variable(var, nir)
293 var->data.driver_location = var->data.location;
294
295 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
296 nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
297 nir_lower_io_lower_64bit_to_32);
298
299 /* This pass needs actual constants */
300 nir_opt_constant_folding(nir);
301
302 nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
303
304 nir_foreach_function(function, nir) {
305 if (!function->impl)
306 continue;
307
308 nir_foreach_block(block, function->impl) {
309 nir_foreach_instr(instr, block) {
310 if (instr->type != nir_instr_type_intrinsic)
311 continue;
312
313 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
314
315 if (intrin->intrinsic == nir_intrinsic_load_input ||
316 intrin->intrinsic == nir_intrinsic_load_per_vertex_input) {
317 /* Offset 0 is the VUE header, which contains
318 * VARYING_SLOT_LAYER [.y], VARYING_SLOT_VIEWPORT [.z], and
319 * VARYING_SLOT_PSIZ [.w].
320 */
321 int varying = nir_intrinsic_base(intrin);
322 int vue_slot;
323 switch (varying) {
324 case VARYING_SLOT_PSIZ:
325 nir_intrinsic_set_base(intrin, 0);
326 nir_intrinsic_set_component(intrin, 3);
327 break;
328
329 default:
330 vue_slot = vue_map->varying_to_slot[varying];
331 assert(vue_slot != -1);
332 nir_intrinsic_set_base(intrin, vue_slot);
333 break;
334 }
335 }
336 }
337 }
338 }
339 }
340
341 void
342 brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue_map)
343 {
344 nir_foreach_shader_in_variable(var, nir)
345 var->data.driver_location = var->data.location;
346
347 nir_lower_io(nir, nir_var_shader_in, type_size_vec4,
348 nir_lower_io_lower_64bit_to_32);
349
350 /* This pass needs actual constants */
351 nir_opt_constant_folding(nir);
352
353 nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
354
355 nir_foreach_function(function, nir) {
356 if (function->impl) {
357 nir_builder b;
358 nir_builder_init(&b, function->impl);
359 nir_foreach_block(block, function->impl) {
360 remap_patch_urb_offsets(block, &b, vue_map,
361 nir->info.tess.primitive_mode);
362 }
363 }
364 }
365 }
366
367 void
368 brw_nir_lower_fs_inputs(nir_shader *nir,
369 const struct gen_device_info *devinfo,
370 const struct brw_wm_prog_key *key)
371 {
372 nir_foreach_shader_in_variable(var, nir) {
373 var->data.driver_location = var->data.location;
374
375 /* Apply default interpolation mode.
376 *
377 * Everything defaults to smooth except for the legacy GL color
378 * built-in variables, which might be flat depending on API state.
379 */
380 if (var->data.interpolation == INTERP_MODE_NONE) {
381 const bool flat = key->flat_shade &&
382 (var->data.location == VARYING_SLOT_COL0 ||
383 var->data.location == VARYING_SLOT_COL1);
384
385 var->data.interpolation = flat ? INTERP_MODE_FLAT
386 : INTERP_MODE_SMOOTH;
387 }
388
389 /* On Ironlake and below, there is only one interpolation mode.
390 * Centroid interpolation doesn't mean anything on this hardware --
391 * there is no multisampling.
392 */
393 if (devinfo->gen < 6) {
394 var->data.centroid = false;
395 var->data.sample = false;
396 }
397 }
398
399 nir_lower_io_options lower_io_options = nir_lower_io_lower_64bit_to_32;
400 if (key->persample_interp)
401 lower_io_options |= nir_lower_io_force_sample_interpolation;
402
403 nir_lower_io(nir, nir_var_shader_in, type_size_vec4, lower_io_options);
404 if (devinfo->gen >= 11)
405 nir_lower_interpolation(nir, ~0);
406
407 /* This pass needs actual constants */
408 nir_opt_constant_folding(nir);
409
410 nir_io_add_const_offset_to_base(nir, nir_var_shader_in);
411 }
412
413 void
414 brw_nir_lower_vue_outputs(nir_shader *nir)
415 {
416 nir_foreach_shader_out_variable(var, nir) {
417 var->data.driver_location = var->data.location;
418 }
419
420 nir_lower_io(nir, nir_var_shader_out, type_size_vec4,
421 nir_lower_io_lower_64bit_to_32);
422 }
423
424 void
425 brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue_map,
426 GLenum tes_primitive_mode)
427 {
428 nir_foreach_shader_out_variable(var, nir) {
429 var->data.driver_location = var->data.location;
430 }
431
432 nir_lower_io(nir, nir_var_shader_out, type_size_vec4,
433 nir_lower_io_lower_64bit_to_32);
434
435 /* This pass needs actual constants */
436 nir_opt_constant_folding(nir);
437
438 nir_io_add_const_offset_to_base(nir, nir_var_shader_out);
439
440 nir_foreach_function(function, nir) {
441 if (function->impl) {
442 nir_builder b;
443 nir_builder_init(&b, function->impl);
444 nir_foreach_block(block, function->impl) {
445 remap_patch_urb_offsets(block, &b, vue_map, tes_primitive_mode);
446 }
447 }
448 }
449 }
450
451 void
452 brw_nir_lower_fs_outputs(nir_shader *nir)
453 {
454 nir_foreach_shader_out_variable(var, nir) {
455 var->data.driver_location =
456 SET_FIELD(var->data.index, BRW_NIR_FRAG_OUTPUT_INDEX) |
457 SET_FIELD(var->data.location, BRW_NIR_FRAG_OUTPUT_LOCATION);
458 }
459
460 nir_lower_io(nir, nir_var_shader_out, type_size_dvec4, 0);
461 }
462
463 #define OPT(pass, ...) ({ \
464 bool this_progress = false; \
465 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
466 if (this_progress) \
467 progress = true; \
468 this_progress; \
469 })
470
471 static nir_variable_mode
472 brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
473 gl_shader_stage stage)
474 {
475 const bool is_scalar = compiler->scalar_stage[stage];
476 nir_variable_mode indirect_mask = 0;
477
478 switch (stage) {
479 case MESA_SHADER_VERTEX:
480 case MESA_SHADER_FRAGMENT:
481 indirect_mask |= nir_var_shader_in;
482 break;
483
484 case MESA_SHADER_GEOMETRY:
485 if (!is_scalar)
486 indirect_mask |= nir_var_shader_in;
487 break;
488
489 default:
490 /* Everything else can handle indirect inputs */
491 break;
492 }
493
494 if (is_scalar && stage != MESA_SHADER_TESS_CTRL)
495 indirect_mask |= nir_var_shader_out;
496
497 if (is_scalar)
498 indirect_mask |= nir_var_function_temp;
499
500 return indirect_mask;
501 }
502
503 void
504 brw_nir_optimize(nir_shader *nir, const struct brw_compiler *compiler,
505 bool is_scalar, bool allow_copies)
506 {
507 nir_variable_mode indirect_mask =
508 brw_nir_no_indirect_mask(compiler, nir->info.stage);
509
510 bool progress;
511 unsigned lower_flrp =
512 (nir->options->lower_flrp16 ? 16 : 0) |
513 (nir->options->lower_flrp32 ? 32 : 0) |
514 (nir->options->lower_flrp64 ? 64 : 0);
515
516 do {
517 progress = false;
518 OPT(nir_split_array_vars, nir_var_function_temp);
519 OPT(nir_shrink_vec_array_vars, nir_var_function_temp);
520 OPT(nir_opt_deref);
521 OPT(nir_lower_vars_to_ssa);
522 if (allow_copies) {
523 /* Only run this pass in the first call to brw_nir_optimize. Later
524 * calls assume that we've lowered away any copy_deref instructions
525 * and we don't want to introduce any more.
526 */
527 OPT(nir_opt_find_array_copies);
528 }
529 OPT(nir_opt_copy_prop_vars);
530 OPT(nir_opt_dead_write_vars);
531 OPT(nir_opt_combine_stores, nir_var_all);
532
533 if (is_scalar) {
534 OPT(nir_lower_alu_to_scalar, NULL, NULL);
535 } else {
536 OPT(nir_opt_shrink_vectors);
537 }
538
539 OPT(nir_copy_prop);
540
541 if (is_scalar) {
542 OPT(nir_lower_phis_to_scalar);
543 }
544
545 OPT(nir_copy_prop);
546 OPT(nir_opt_dce);
547 OPT(nir_opt_cse);
548 OPT(nir_opt_combine_stores, nir_var_all);
549
550 /* Passing 0 to the peephole select pass causes it to convert
551 * if-statements that contain only move instructions in the branches
552 * regardless of the count.
553 *
554 * Passing 1 to the peephole select pass causes it to convert
555 * if-statements that contain at most a single ALU instruction (total)
556 * in both branches. Before Gen6, some math instructions were
557 * prohibitively expensive and the results of compare operations need an
558 * extra resolve step. For these reasons, this pass is more harmful
559 * than good on those platforms.
560 *
561 * For indirect loads of uniforms (push constants), we assume that array
562 * indices will nearly always be in bounds and the cost of the load is
563 * low. Therefore there shouldn't be a performance benefit to avoid it.
564 * However, in vec4 tessellation shaders, these loads operate by
565 * actually pulling from memory.
566 */
567 const bool is_vec4_tessellation = !is_scalar &&
568 (nir->info.stage == MESA_SHADER_TESS_CTRL ||
569 nir->info.stage == MESA_SHADER_TESS_EVAL);
570 OPT(nir_opt_peephole_select, 0, !is_vec4_tessellation, false);
571 OPT(nir_opt_peephole_select, 8, !is_vec4_tessellation,
572 compiler->devinfo->gen >= 6);
573
574 OPT(nir_opt_intrinsics);
575 OPT(nir_opt_idiv_const, 32);
576 OPT(nir_opt_algebraic);
577 OPT(nir_opt_constant_folding);
578
579 if (lower_flrp != 0) {
580 if (OPT(nir_lower_flrp,
581 lower_flrp,
582 false /* always_precise */,
583 compiler->devinfo->gen >= 6)) {
584 OPT(nir_opt_constant_folding);
585 }
586
587 /* Nothing should rematerialize any flrps, so we only need to do this
588 * lowering once.
589 */
590 lower_flrp = 0;
591 }
592
593 OPT(nir_opt_dead_cf);
594 if (OPT(nir_opt_trivial_continues)) {
595 /* If nir_opt_trivial_continues makes progress, then we need to clean
596 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
597 * to make progress.
598 */
599 OPT(nir_copy_prop);
600 OPT(nir_opt_dce);
601 }
602 OPT(nir_opt_if, false);
603 OPT(nir_opt_conditional_discard);
604 if (nir->options->max_unroll_iterations != 0) {
605 OPT(nir_opt_loop_unroll, indirect_mask);
606 }
607 OPT(nir_opt_remove_phis);
608 OPT(nir_opt_undef);
609 OPT(nir_lower_pack);
610 } while (progress);
611
612 /* Workaround Gfxbench unused local sampler variable which will trigger an
613 * assert in the opt_large_constants pass.
614 */
615 OPT(nir_remove_dead_variables, nir_var_function_temp, NULL);
616 }
617
618 static unsigned
619 lower_bit_size_callback(const nir_alu_instr *alu, UNUSED void *data)
620 {
621 assert(alu->dest.dest.is_ssa);
622 if (alu->dest.dest.ssa.bit_size >= 32)
623 return 0;
624
625 const struct brw_compiler *compiler = (const struct brw_compiler *) data;
626
627 switch (alu->op) {
628 case nir_op_idiv:
629 case nir_op_imod:
630 case nir_op_irem:
631 case nir_op_udiv:
632 case nir_op_umod:
633 case nir_op_fceil:
634 case nir_op_ffloor:
635 case nir_op_ffract:
636 case nir_op_fround_even:
637 case nir_op_ftrunc:
638 return 32;
639 case nir_op_frcp:
640 case nir_op_frsq:
641 case nir_op_fsqrt:
642 case nir_op_fpow:
643 case nir_op_fexp2:
644 case nir_op_flog2:
645 case nir_op_fsin:
646 case nir_op_fcos:
647 return compiler->devinfo->gen < 9 ? 32 : 0;
648 default:
649 return 0;
650 }
651 }
652
653 /* Does some simple lowering and runs the standard suite of optimizations
654 *
655 * This is intended to be called more-or-less directly after you get the
656 * shader out of GLSL or some other source. While it is geared towards i965,
657 * it is not at all generator-specific except for the is_scalar flag. Even
658 * there, it is safe to call with is_scalar = false for a shader that is
659 * intended for the FS backend as long as nir_optimize is called again with
660 * is_scalar = true to scalarize everything prior to code gen.
661 */
662 void
663 brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
664 const nir_shader *softfp64)
665 {
666 const struct gen_device_info *devinfo = compiler->devinfo;
667 UNUSED bool progress; /* Written by OPT */
668
669 const bool is_scalar = compiler->scalar_stage[nir->info.stage];
670
671 if (is_scalar) {
672 OPT(nir_lower_alu_to_scalar, NULL, NULL);
673 }
674
675 if (nir->info.stage == MESA_SHADER_GEOMETRY)
676 OPT(nir_lower_gs_intrinsics, false);
677
678 /* See also brw_nir_trig_workarounds.py */
679 if (compiler->precise_trig &&
680 !(devinfo->gen >= 10 || devinfo->is_kabylake))
681 OPT(brw_nir_apply_trig_workarounds);
682
683 if (devinfo->gen >= 12)
684 OPT(brw_nir_clamp_image_1d_2d_array_sizes);
685
686 static const nir_lower_tex_options tex_options = {
687 .lower_txp = ~0,
688 .lower_txf_offset = true,
689 .lower_rect_offset = true,
690 .lower_tex_without_implicit_lod = true,
691 .lower_txd_cube_map = true,
692 .lower_txb_shadow_clamp = true,
693 .lower_txd_shadow_clamp = true,
694 .lower_txd_offset_clamp = true,
695 .lower_tg4_offsets = true,
696 };
697
698 OPT(nir_lower_tex, &tex_options);
699 OPT(nir_normalize_cubemap_coords);
700
701 OPT(nir_lower_global_vars_to_local);
702
703 OPT(nir_split_var_copies);
704 OPT(nir_split_struct_vars, nir_var_function_temp);
705
706 brw_nir_optimize(nir, compiler, is_scalar, true);
707
708 OPT(nir_lower_doubles, softfp64, nir->options->lower_doubles_options);
709 OPT(nir_lower_int64);
710
711 OPT(nir_lower_bit_size, lower_bit_size_callback, (void *)compiler);
712
713 if (is_scalar) {
714 OPT(nir_lower_load_const_to_scalar);
715 }
716
717 /* Lower a bunch of stuff */
718 OPT(nir_lower_var_copies);
719
720 /* This needs to be run after the first optimization pass but before we
721 * lower indirect derefs away
722 */
723 if (compiler->supports_shader_constants) {
724 OPT(nir_opt_large_constants, NULL, 32);
725 }
726
727 OPT(nir_lower_system_values);
728 OPT(nir_lower_compute_system_values, NULL);
729
730 const nir_lower_subgroups_options subgroups_options = {
731 .ballot_bit_size = 32,
732 .lower_to_scalar = true,
733 .lower_vote_trivial = !is_scalar,
734 .lower_shuffle = true,
735 .lower_quad_broadcast_dynamic = true,
736 };
737 OPT(nir_lower_subgroups, &subgroups_options);
738
739 OPT(nir_lower_clip_cull_distance_arrays);
740
741 if ((devinfo->gen >= 8 || devinfo->is_haswell) && is_scalar) {
742 /* TODO: Yes, we could in theory do this on gen6 and earlier. However,
743 * that would require plumbing through support for these indirect
744 * scratch read/write messages with message registers and that's just a
745 * pain. Also, the primary benefit of this is for compute shaders which
746 * won't run on gen6 and earlier anyway.
747 *
748 * On gen7 and earlier the scratch space size is limited to 12kB.
749 * By enabling this optimization we may easily exceed this limit without
750 * having any fallback.
751 *
752 * The threshold of 128B was chosen semi-arbitrarily. The idea is that
753 * 128B per channel on a SIMD8 program is 32 registers or 25% of the
754 * register file. Any array that large is likely to cause pressure
755 * issues. Also, this value is sufficiently high that the benchmarks
756 * known to suffer from large temporary array issues are helped but
757 * nothing else in shader-db is hurt except for maybe that one kerbal
758 * space program shader.
759 */
760 OPT(nir_lower_vars_to_scratch, nir_var_function_temp, 128,
761 glsl_get_natural_size_align_bytes);
762 }
763
764 nir_variable_mode indirect_mask =
765 brw_nir_no_indirect_mask(compiler, nir->info.stage);
766 OPT(nir_lower_indirect_derefs, indirect_mask, UINT32_MAX);
767
768 /* Lower array derefs of vectors for SSBO and UBO loads. For both UBOs and
769 * SSBOs, our back-end is capable of loading an entire vec4 at a time and
770 * we would like to take advantage of that whenever possible regardless of
771 * whether or not the app gives us full loads. This should allow the
772 * optimizer to combine UBO and SSBO load operations and save us some send
773 * messages.
774 */
775 OPT(nir_lower_array_deref_of_vec,
776 nir_var_mem_ubo | nir_var_mem_ssbo,
777 nir_lower_direct_array_deref_of_vec_load);
778
779 /* Get rid of split copies */
780 brw_nir_optimize(nir, compiler, is_scalar, false);
781 }
782
783 void
784 brw_nir_link_shaders(const struct brw_compiler *compiler,
785 nir_shader *producer, nir_shader *consumer)
786 {
787 nir_lower_io_arrays_to_elements(producer, consumer);
788 nir_validate_shader(producer, "after nir_lower_io_arrays_to_elements");
789 nir_validate_shader(consumer, "after nir_lower_io_arrays_to_elements");
790
791 const bool p_is_scalar = compiler->scalar_stage[producer->info.stage];
792 const bool c_is_scalar = compiler->scalar_stage[consumer->info.stage];
793
794 if (p_is_scalar && c_is_scalar) {
795 NIR_PASS_V(producer, nir_lower_io_to_scalar_early, nir_var_shader_out);
796 NIR_PASS_V(consumer, nir_lower_io_to_scalar_early, nir_var_shader_in);
797 brw_nir_optimize(producer, compiler, p_is_scalar, false);
798 brw_nir_optimize(consumer, compiler, c_is_scalar, false);
799 }
800
801 if (nir_link_opt_varyings(producer, consumer))
802 brw_nir_optimize(consumer, compiler, c_is_scalar, false);
803
804 NIR_PASS_V(producer, nir_remove_dead_variables, nir_var_shader_out, NULL);
805 NIR_PASS_V(consumer, nir_remove_dead_variables, nir_var_shader_in, NULL);
806
807 if (nir_remove_unused_varyings(producer, consumer)) {
808 NIR_PASS_V(producer, nir_lower_global_vars_to_local);
809 NIR_PASS_V(consumer, nir_lower_global_vars_to_local);
810
811 /* The backend might not be able to handle indirects on
812 * temporaries so we need to lower indirects on any of the
813 * varyings we have demoted here.
814 */
815 NIR_PASS_V(producer, nir_lower_indirect_derefs,
816 brw_nir_no_indirect_mask(compiler, producer->info.stage),
817 UINT32_MAX);
818 NIR_PASS_V(consumer, nir_lower_indirect_derefs,
819 brw_nir_no_indirect_mask(compiler, consumer->info.stage),
820 UINT32_MAX);
821
822 brw_nir_optimize(producer, compiler, p_is_scalar, false);
823 brw_nir_optimize(consumer, compiler, c_is_scalar, false);
824 }
825
826 NIR_PASS_V(producer, nir_lower_io_to_vector, nir_var_shader_out);
827 NIR_PASS_V(producer, nir_opt_combine_stores, nir_var_shader_out);
828 NIR_PASS_V(consumer, nir_lower_io_to_vector, nir_var_shader_in);
829
830 if (producer->info.stage != MESA_SHADER_TESS_CTRL) {
831 /* Calling lower_io_to_vector creates output variable writes with
832 * write-masks. On non-TCS outputs, the back-end can't handle it and we
833 * need to call nir_lower_io_to_temporaries to get rid of them. This,
834 * in turn, creates temporary variables and extra copy_deref intrinsics
835 * that we need to clean up.
836 */
837 NIR_PASS_V(producer, nir_lower_io_to_temporaries,
838 nir_shader_get_entrypoint(producer), true, false);
839 NIR_PASS_V(producer, nir_lower_global_vars_to_local);
840 NIR_PASS_V(producer, nir_split_var_copies);
841 NIR_PASS_V(producer, nir_lower_var_copies);
842 }
843 }
844
845 static bool
846 brw_nir_should_vectorize_mem(unsigned align, unsigned bit_size,
847 unsigned num_components, unsigned high_offset,
848 nir_intrinsic_instr *low,
849 nir_intrinsic_instr *high)
850 {
851 /* Don't combine things to generate 64-bit loads/stores. We have to split
852 * those back into 32-bit ones anyway and UBO loads aren't split in NIR so
853 * we don't want to make a mess for the back-end.
854 */
855 if (bit_size > 32)
856 return false;
857
858 /* We can handle at most a vec4 right now. Anything bigger would get
859 * immediately split by brw_nir_lower_mem_access_bit_sizes anyway.
860 */
861 if (num_components > 4)
862 return false;
863
864 if (align < bit_size / 8)
865 return false;
866
867 return true;
868 }
869
870 static
871 bool combine_all_barriers(nir_intrinsic_instr *a,
872 nir_intrinsic_instr *b,
873 void *data)
874 {
875 /* Translation to backend IR will get rid of modes we don't care about, so
876 * no harm in always combining them.
877 *
878 * TODO: While HW has only ACQUIRE|RELEASE fences, we could improve the
879 * scheduling so that it can take advantage of the different semantics.
880 */
881 nir_intrinsic_set_memory_modes(a, nir_intrinsic_memory_modes(a) |
882 nir_intrinsic_memory_modes(b));
883 nir_intrinsic_set_memory_semantics(a, nir_intrinsic_memory_semantics(a) |
884 nir_intrinsic_memory_semantics(b));
885 nir_intrinsic_set_memory_scope(a, MAX2(nir_intrinsic_memory_scope(a),
886 nir_intrinsic_memory_scope(b)));
887 return true;
888 }
889
890 static void
891 brw_vectorize_lower_mem_access(nir_shader *nir,
892 const struct brw_compiler *compiler,
893 bool is_scalar)
894 {
895 const struct gen_device_info *devinfo = compiler->devinfo;
896 bool progress = false;
897
898 if (is_scalar) {
899 OPT(nir_opt_load_store_vectorize,
900 nir_var_mem_ubo | nir_var_mem_ssbo |
901 nir_var_mem_global | nir_var_mem_shared,
902 brw_nir_should_vectorize_mem,
903 (nir_variable_mode)0);
904 }
905
906 OPT(brw_nir_lower_mem_access_bit_sizes, devinfo);
907
908 while (progress) {
909 progress = false;
910
911 OPT(nir_lower_pack);
912 OPT(nir_copy_prop);
913 OPT(nir_opt_dce);
914 OPT(nir_opt_cse);
915 OPT(nir_opt_algebraic);
916 OPT(nir_opt_constant_folding);
917 }
918 }
919
920 /* Prepare the given shader for codegen
921 *
922 * This function is intended to be called right before going into the actual
923 * backend and is highly backend-specific. Also, once this function has been
924 * called on a shader, it will no longer be in SSA form so most optimizations
925 * will not work.
926 */
927 void
928 brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
929 bool is_scalar)
930 {
931 const struct gen_device_info *devinfo = compiler->devinfo;
932 bool debug_enabled =
933 (INTEL_DEBUG & intel_debug_flag_for_shader_stage(nir->info.stage));
934
935 UNUSED bool progress; /* Written by OPT */
936
937 OPT(brw_nir_lower_scoped_barriers);
938 OPT(nir_opt_combine_memory_barriers, combine_all_barriers, NULL);
939
940 do {
941 progress = false;
942 OPT(nir_opt_algebraic_before_ffma);
943 } while (progress);
944
945 brw_nir_optimize(nir, compiler, is_scalar, false);
946
947 brw_vectorize_lower_mem_access(nir, compiler, is_scalar);
948
949 if (OPT(nir_lower_int64))
950 brw_nir_optimize(nir, compiler, is_scalar, false);
951
952 if (devinfo->gen >= 6) {
953 /* Try and fuse multiply-adds */
954 OPT(brw_nir_opt_peephole_ffma);
955 }
956
957 if (OPT(nir_opt_comparison_pre)) {
958 OPT(nir_copy_prop);
959 OPT(nir_opt_dce);
960 OPT(nir_opt_cse);
961
962 /* Do the select peepehole again. nir_opt_comparison_pre (combined with
963 * the other optimization passes) will have removed at least one
964 * instruction from one of the branches of the if-statement, so now it
965 * might be under the threshold of conversion to bcsel.
966 *
967 * See brw_nir_optimize for the explanation of is_vec4_tessellation.
968 */
969 const bool is_vec4_tessellation = !is_scalar &&
970 (nir->info.stage == MESA_SHADER_TESS_CTRL ||
971 nir->info.stage == MESA_SHADER_TESS_EVAL);
972 OPT(nir_opt_peephole_select, 0, is_vec4_tessellation, false);
973 OPT(nir_opt_peephole_select, 1, is_vec4_tessellation,
974 compiler->devinfo->gen >= 6);
975 }
976
977 do {
978 progress = false;
979 if (OPT(nir_opt_algebraic_late)) {
980 /* At this late stage, anything that makes more constants will wreak
981 * havok on the vec4 backend. The handling of constants in the vec4
982 * backend is not good.
983 */
984 if (is_scalar)
985 OPT(nir_opt_constant_folding);
986
987 OPT(nir_copy_prop);
988 OPT(nir_opt_dce);
989 OPT(nir_opt_cse);
990 }
991 } while (progress);
992
993
994 OPT(brw_nir_lower_conversions);
995
996 if (is_scalar)
997 OPT(nir_lower_alu_to_scalar, NULL, NULL);
998
999 while (OPT(nir_opt_algebraic_distribute_src_mods)) {
1000 OPT(nir_copy_prop);
1001 OPT(nir_opt_dce);
1002 OPT(nir_opt_cse);
1003 }
1004
1005 OPT(nir_copy_prop);
1006 OPT(nir_opt_dce);
1007 OPT(nir_opt_move, nir_move_comparisons);
1008
1009 OPT(nir_lower_bool_to_int32);
1010 OPT(nir_copy_prop);
1011 OPT(nir_opt_dce);
1012
1013 OPT(nir_lower_locals_to_regs);
1014
1015 if (unlikely(debug_enabled)) {
1016 /* Re-index SSA defs so we print more sensible numbers. */
1017 nir_foreach_function(function, nir) {
1018 if (function->impl)
1019 nir_index_ssa_defs(function->impl);
1020 }
1021
1022 fprintf(stderr, "NIR (SSA form) for %s shader:\n",
1023 _mesa_shader_stage_to_string(nir->info.stage));
1024 nir_print_shader(nir, stderr);
1025 }
1026
1027 OPT(nir_convert_from_ssa, true);
1028
1029 if (!is_scalar) {
1030 OPT(nir_move_vec_src_uses_to_dest);
1031 OPT(nir_lower_vec_to_movs);
1032 }
1033
1034 OPT(nir_opt_dce);
1035
1036 if (OPT(nir_opt_rematerialize_compares))
1037 OPT(nir_opt_dce);
1038
1039 /* This is the last pass we run before we start emitting stuff. It
1040 * determines when we need to insert boolean resolves on Gen <= 5. We
1041 * run it last because it stashes data in instr->pass_flags and we don't
1042 * want that to be squashed by other NIR passes.
1043 */
1044 if (devinfo->gen <= 5)
1045 brw_nir_analyze_boolean_resolves(nir);
1046
1047 nir_sweep(nir);
1048
1049 if (unlikely(debug_enabled)) {
1050 fprintf(stderr, "NIR (final form) for %s shader:\n",
1051 _mesa_shader_stage_to_string(nir->info.stage));
1052 nir_print_shader(nir, stderr);
1053 }
1054 }
1055
1056 static bool
1057 brw_nir_apply_sampler_key(nir_shader *nir,
1058 const struct brw_compiler *compiler,
1059 const struct brw_sampler_prog_key_data *key_tex)
1060 {
1061 const struct gen_device_info *devinfo = compiler->devinfo;
1062 nir_lower_tex_options tex_options = {
1063 .lower_txd_clamp_bindless_sampler = true,
1064 .lower_txd_clamp_if_sampler_index_not_lt_16 = true,
1065 };
1066
1067 /* Iron Lake and prior require lowering of all rectangle textures */
1068 if (devinfo->gen < 6)
1069 tex_options.lower_rect = true;
1070
1071 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
1072 if (devinfo->gen < 8) {
1073 tex_options.saturate_s = key_tex->gl_clamp_mask[0];
1074 tex_options.saturate_t = key_tex->gl_clamp_mask[1];
1075 tex_options.saturate_r = key_tex->gl_clamp_mask[2];
1076 }
1077
1078 /* Prior to Haswell, we have to fake texture swizzle */
1079 for (unsigned s = 0; s < MAX_SAMPLERS; s++) {
1080 if (key_tex->swizzles[s] == SWIZZLE_NOOP)
1081 continue;
1082
1083 tex_options.swizzle_result |= BITFIELD_BIT(s);
1084 for (unsigned c = 0; c < 4; c++)
1085 tex_options.swizzles[s][c] = GET_SWZ(key_tex->swizzles[s], c);
1086 }
1087
1088 /* Prior to Haswell, we have to lower gradients on shadow samplers */
1089 tex_options.lower_txd_shadow = devinfo->gen < 8 && !devinfo->is_haswell;
1090
1091 tex_options.lower_y_uv_external = key_tex->y_uv_image_mask;
1092 tex_options.lower_y_u_v_external = key_tex->y_u_v_image_mask;
1093 tex_options.lower_yx_xuxv_external = key_tex->yx_xuxv_image_mask;
1094 tex_options.lower_xy_uxvx_external = key_tex->xy_uxvx_image_mask;
1095 tex_options.lower_ayuv_external = key_tex->ayuv_image_mask;
1096 tex_options.lower_xyuv_external = key_tex->xyuv_image_mask;
1097 tex_options.bt709_external = key_tex->bt709_mask;
1098 tex_options.bt2020_external = key_tex->bt2020_mask;
1099
1100 /* Setup array of scaling factors for each texture. */
1101 memcpy(&tex_options.scale_factors, &key_tex->scale_factors,
1102 sizeof(tex_options.scale_factors));
1103
1104 return nir_lower_tex(nir, &tex_options);
1105 }
1106
1107 static unsigned
1108 get_subgroup_size(gl_shader_stage stage,
1109 const struct brw_base_prog_key *key,
1110 unsigned max_subgroup_size)
1111 {
1112 switch (key->subgroup_size_type) {
1113 case BRW_SUBGROUP_SIZE_API_CONSTANT:
1114 /* We have to use the global constant size. */
1115 return BRW_SUBGROUP_SIZE;
1116
1117 case BRW_SUBGROUP_SIZE_UNIFORM:
1118 /* It has to be uniform across all invocations but can vary per stage
1119 * if we want. This gives us a bit more freedom.
1120 *
1121 * For compute, brw_nir_apply_key is called per-dispatch-width so this
1122 * is the actual subgroup size and not a maximum. However, we only
1123 * invoke one size of any given compute shader so it's still guaranteed
1124 * to be uniform across invocations.
1125 */
1126 return max_subgroup_size;
1127
1128 case BRW_SUBGROUP_SIZE_VARYING:
1129 /* The subgroup size is allowed to be fully varying. For geometry
1130 * stages, we know it's always 8 which is max_subgroup_size so we can
1131 * return that. For compute, brw_nir_apply_key is called once per
1132 * dispatch-width so max_subgroup_size is the real subgroup size.
1133 *
1134 * For fragment, we return 0 and let it fall through to the back-end
1135 * compiler. This means we can't optimize based on subgroup size but
1136 * that's a risk the client took when it asked for a varying subgroup
1137 * size.
1138 */
1139 return stage == MESA_SHADER_FRAGMENT ? 0 : max_subgroup_size;
1140
1141 case BRW_SUBGROUP_SIZE_REQUIRE_8:
1142 case BRW_SUBGROUP_SIZE_REQUIRE_16:
1143 case BRW_SUBGROUP_SIZE_REQUIRE_32:
1144 assert(stage == MESA_SHADER_COMPUTE);
1145 /* These enum values are expressly chosen to be equal to the subgroup
1146 * size that they require.
1147 */
1148 return key->subgroup_size_type;
1149 }
1150
1151 unreachable("Invalid subgroup size type");
1152 }
1153
1154 void
1155 brw_nir_apply_key(nir_shader *nir,
1156 const struct brw_compiler *compiler,
1157 const struct brw_base_prog_key *key,
1158 unsigned max_subgroup_size,
1159 bool is_scalar)
1160 {
1161 bool progress = false;
1162
1163 OPT(brw_nir_apply_sampler_key, compiler, &key->tex);
1164
1165 const nir_lower_subgroups_options subgroups_options = {
1166 .subgroup_size = get_subgroup_size(nir->info.stage, key,
1167 max_subgroup_size),
1168 .ballot_bit_size = 32,
1169 .lower_subgroup_masks = true,
1170 };
1171 OPT(nir_lower_subgroups, &subgroups_options);
1172
1173 if (progress)
1174 brw_nir_optimize(nir, compiler, is_scalar, false);
1175 }
1176
1177 enum brw_conditional_mod
1178 brw_cmod_for_nir_comparison(nir_op op)
1179 {
1180 switch (op) {
1181 case nir_op_flt:
1182 case nir_op_flt32:
1183 case nir_op_ilt:
1184 case nir_op_ilt32:
1185 case nir_op_ult:
1186 case nir_op_ult32:
1187 return BRW_CONDITIONAL_L;
1188
1189 case nir_op_fge:
1190 case nir_op_fge32:
1191 case nir_op_ige:
1192 case nir_op_ige32:
1193 case nir_op_uge:
1194 case nir_op_uge32:
1195 return BRW_CONDITIONAL_GE;
1196
1197 case nir_op_feq:
1198 case nir_op_feq32:
1199 case nir_op_ieq:
1200 case nir_op_ieq32:
1201 case nir_op_b32all_fequal2:
1202 case nir_op_b32all_iequal2:
1203 case nir_op_b32all_fequal3:
1204 case nir_op_b32all_iequal3:
1205 case nir_op_b32all_fequal4:
1206 case nir_op_b32all_iequal4:
1207 return BRW_CONDITIONAL_Z;
1208
1209 case nir_op_fneu:
1210 case nir_op_fneu32:
1211 case nir_op_ine:
1212 case nir_op_ine32:
1213 case nir_op_b32any_fnequal2:
1214 case nir_op_b32any_inequal2:
1215 case nir_op_b32any_fnequal3:
1216 case nir_op_b32any_inequal3:
1217 case nir_op_b32any_fnequal4:
1218 case nir_op_b32any_inequal4:
1219 return BRW_CONDITIONAL_NZ;
1220
1221 default:
1222 unreachable("Unsupported NIR comparison op");
1223 }
1224 }
1225
1226 uint32_t
1227 brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic)
1228 {
1229 switch (atomic->intrinsic) {
1230 #define AOP_CASE(atom) \
1231 case nir_intrinsic_image_atomic_##atom: \
1232 case nir_intrinsic_bindless_image_atomic_##atom: \
1233 case nir_intrinsic_ssbo_atomic_##atom: \
1234 case nir_intrinsic_shared_atomic_##atom: \
1235 case nir_intrinsic_global_atomic_##atom
1236
1237 AOP_CASE(add): {
1238 unsigned src_idx;
1239 switch (atomic->intrinsic) {
1240 case nir_intrinsic_image_atomic_add:
1241 case nir_intrinsic_bindless_image_atomic_add:
1242 src_idx = 3;
1243 break;
1244 case nir_intrinsic_ssbo_atomic_add:
1245 src_idx = 2;
1246 break;
1247 case nir_intrinsic_shared_atomic_add:
1248 case nir_intrinsic_global_atomic_add:
1249 src_idx = 1;
1250 break;
1251 default:
1252 unreachable("Invalid add atomic opcode");
1253 }
1254
1255 if (nir_src_is_const(atomic->src[src_idx])) {
1256 int64_t add_val = nir_src_as_int(atomic->src[src_idx]);
1257 if (add_val == 1)
1258 return BRW_AOP_INC;
1259 else if (add_val == -1)
1260 return BRW_AOP_DEC;
1261 }
1262 return BRW_AOP_ADD;
1263 }
1264
1265 AOP_CASE(imin): return BRW_AOP_IMIN;
1266 AOP_CASE(umin): return BRW_AOP_UMIN;
1267 AOP_CASE(imax): return BRW_AOP_IMAX;
1268 AOP_CASE(umax): return BRW_AOP_UMAX;
1269 AOP_CASE(and): return BRW_AOP_AND;
1270 AOP_CASE(or): return BRW_AOP_OR;
1271 AOP_CASE(xor): return BRW_AOP_XOR;
1272 AOP_CASE(exchange): return BRW_AOP_MOV;
1273 AOP_CASE(comp_swap): return BRW_AOP_CMPWR;
1274
1275 #undef AOP_CASE
1276 #define AOP_CASE(atom) \
1277 case nir_intrinsic_ssbo_atomic_##atom: \
1278 case nir_intrinsic_shared_atomic_##atom: \
1279 case nir_intrinsic_global_atomic_##atom
1280
1281 AOP_CASE(fmin): return BRW_AOP_FMIN;
1282 AOP_CASE(fmax): return BRW_AOP_FMAX;
1283 AOP_CASE(fcomp_swap): return BRW_AOP_FCMPWR;
1284
1285 #undef AOP_CASE
1286
1287 default:
1288 unreachable("Unsupported NIR atomic intrinsic");
1289 }
1290 }
1291
1292 enum brw_reg_type
1293 brw_type_for_nir_type(const struct gen_device_info *devinfo, nir_alu_type type)
1294 {
1295 switch (type) {
1296 case nir_type_uint:
1297 case nir_type_uint32:
1298 return BRW_REGISTER_TYPE_UD;
1299 case nir_type_bool:
1300 case nir_type_int:
1301 case nir_type_bool32:
1302 case nir_type_int32:
1303 return BRW_REGISTER_TYPE_D;
1304 case nir_type_float:
1305 case nir_type_float32:
1306 return BRW_REGISTER_TYPE_F;
1307 case nir_type_float16:
1308 return BRW_REGISTER_TYPE_HF;
1309 case nir_type_float64:
1310 return BRW_REGISTER_TYPE_DF;
1311 case nir_type_int64:
1312 return devinfo->gen < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_Q;
1313 case nir_type_uint64:
1314 return devinfo->gen < 8 ? BRW_REGISTER_TYPE_DF : BRW_REGISTER_TYPE_UQ;
1315 case nir_type_int16:
1316 return BRW_REGISTER_TYPE_W;
1317 case nir_type_uint16:
1318 return BRW_REGISTER_TYPE_UW;
1319 case nir_type_int8:
1320 return BRW_REGISTER_TYPE_B;
1321 case nir_type_uint8:
1322 return BRW_REGISTER_TYPE_UB;
1323 default:
1324 unreachable("unknown type");
1325 }
1326
1327 return BRW_REGISTER_TYPE_F;
1328 }
1329
1330 /* Returns the glsl_base_type corresponding to a nir_alu_type.
1331 * This is used by both brw_vec4_nir and brw_fs_nir.
1332 */
1333 enum glsl_base_type
1334 brw_glsl_base_type_for_nir_type(nir_alu_type type)
1335 {
1336 switch (type) {
1337 case nir_type_float:
1338 case nir_type_float32:
1339 return GLSL_TYPE_FLOAT;
1340
1341 case nir_type_float16:
1342 return GLSL_TYPE_FLOAT16;
1343
1344 case nir_type_float64:
1345 return GLSL_TYPE_DOUBLE;
1346
1347 case nir_type_int:
1348 case nir_type_int32:
1349 return GLSL_TYPE_INT;
1350
1351 case nir_type_uint:
1352 case nir_type_uint32:
1353 return GLSL_TYPE_UINT;
1354
1355 case nir_type_int16:
1356 return GLSL_TYPE_INT16;
1357
1358 case nir_type_uint16:
1359 return GLSL_TYPE_UINT16;
1360
1361 default:
1362 unreachable("bad type");
1363 }
1364 }
1365
1366 nir_shader *
1367 brw_nir_create_passthrough_tcs(void *mem_ctx, const struct brw_compiler *compiler,
1368 const nir_shader_compiler_options *options,
1369 const struct brw_tcs_prog_key *key)
1370 {
1371 nir_builder b;
1372 nir_builder_init_simple_shader(&b, mem_ctx, MESA_SHADER_TESS_CTRL,
1373 options);
1374 nir_shader *nir = b.shader;
1375 nir_variable *var;
1376 nir_intrinsic_instr *load;
1377 nir_intrinsic_instr *store;
1378 nir_ssa_def *zero = nir_imm_int(&b, 0);
1379 nir_ssa_def *invoc_id = nir_load_invocation_id(&b);
1380
1381 nir->info.inputs_read = key->outputs_written &
1382 ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER);
1383 nir->info.outputs_written = key->outputs_written;
1384 nir->info.tess.tcs_vertices_out = key->input_vertices;
1385 nir->info.name = ralloc_strdup(nir, "passthrough");
1386 nir->num_uniforms = 8 * sizeof(uint32_t);
1387
1388 var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0");
1389 var->data.location = 0;
1390 var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1");
1391 var->data.location = 1;
1392
1393 /* Write the patch URB header. */
1394 for (int i = 0; i <= 1; i++) {
1395 load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform);
1396 load->num_components = 4;
1397 load->src[0] = nir_src_for_ssa(zero);
1398 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1399 nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t));
1400 nir_builder_instr_insert(&b, &load->instr);
1401
1402 store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output);
1403 store->num_components = 4;
1404 store->src[0] = nir_src_for_ssa(&load->dest.ssa);
1405 store->src[1] = nir_src_for_ssa(zero);
1406 nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i);
1407 nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
1408 nir_builder_instr_insert(&b, &store->instr);
1409 }
1410
1411 /* Copy inputs to outputs. */
1412 uint64_t varyings = nir->info.inputs_read;
1413
1414 while (varyings != 0) {
1415 const int varying = ffsll(varyings) - 1;
1416
1417 load = nir_intrinsic_instr_create(nir,
1418 nir_intrinsic_load_per_vertex_input);
1419 load->num_components = 4;
1420 load->src[0] = nir_src_for_ssa(invoc_id);
1421 load->src[1] = nir_src_for_ssa(zero);
1422 nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
1423 nir_intrinsic_set_base(load, varying);
1424 nir_builder_instr_insert(&b, &load->instr);
1425
1426 store = nir_intrinsic_instr_create(nir,
1427 nir_intrinsic_store_per_vertex_output);
1428 store->num_components = 4;
1429 store->src[0] = nir_src_for_ssa(&load->dest.ssa);
1430 store->src[1] = nir_src_for_ssa(invoc_id);
1431 store->src[2] = nir_src_for_ssa(zero);
1432 nir_intrinsic_set_base(store, varying);
1433 nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
1434 nir_builder_instr_insert(&b, &store->instr);
1435
1436 varyings &= ~BITFIELD64_BIT(varying);
1437 }
1438
1439 nir_validate_shader(nir, "in brw_nir_create_passthrough_tcs");
1440
1441 brw_preprocess_nir(compiler, nir, NULL);
1442
1443 return nir;
1444 }