2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "dev/gen_debug.h"
27 #include "compiler/glsl_types.h"
28 #include "compiler/nir/nir_builder.h"
29 #include "util/u_math.h"
32 remap_tess_levels(nir_builder
*b
, nir_intrinsic_instr
*intr
,
33 GLenum primitive_mode
)
35 const int location
= nir_intrinsic_base(intr
);
36 const unsigned component
= nir_intrinsic_component(intr
);
39 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
) {
40 switch (primitive_mode
) {
42 /* gl_TessLevelInner[0..1] lives at DWords 3-2 (reversed). */
43 nir_intrinsic_set_base(intr
, 0);
44 nir_intrinsic_set_component(intr
, 3 - component
);
45 out_of_bounds
= false;
48 /* gl_TessLevelInner[0] lives at DWord 4. */
49 nir_intrinsic_set_base(intr
, 1);
50 out_of_bounds
= component
> 0;
56 unreachable("Bogus tessellation domain");
58 } else if (location
== VARYING_SLOT_TESS_LEVEL_OUTER
) {
59 if (primitive_mode
== GL_ISOLINES
) {
60 /* gl_TessLevelOuter[0..1] lives at DWords 6-7 (in order). */
61 nir_intrinsic_set_base(intr
, 1);
62 nir_intrinsic_set_component(intr
, 2 + nir_intrinsic_component(intr
));
63 out_of_bounds
= component
> 1;
65 /* Triangles use DWords 7-5 (reversed); Quads use 7-4 (reversed) */
66 nir_intrinsic_set_base(intr
, 1);
67 nir_intrinsic_set_component(intr
, 3 - nir_intrinsic_component(intr
));
68 out_of_bounds
= component
== 3 && primitive_mode
== GL_TRIANGLES
;
75 if (nir_intrinsic_infos
[intr
->intrinsic
].has_dest
) {
76 b
->cursor
= nir_before_instr(&intr
->instr
);
77 nir_ssa_def
*undef
= nir_ssa_undef(b
, 1, 32);
78 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(undef
));
80 nir_instr_remove(&intr
->instr
);
87 is_input(nir_intrinsic_instr
*intrin
)
89 return intrin
->intrinsic
== nir_intrinsic_load_input
||
90 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
91 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
;
95 is_output(nir_intrinsic_instr
*intrin
)
97 return intrin
->intrinsic
== nir_intrinsic_load_output
||
98 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
99 intrin
->intrinsic
== nir_intrinsic_store_output
||
100 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
105 remap_patch_urb_offsets(nir_block
*block
, nir_builder
*b
,
106 const struct brw_vue_map
*vue_map
,
107 GLenum tes_primitive_mode
)
109 const bool is_passthrough_tcs
= b
->shader
->info
.name
&&
110 strcmp(b
->shader
->info
.name
, "passthrough") == 0;
112 nir_foreach_instr_safe(instr
, block
) {
113 if (instr
->type
!= nir_instr_type_intrinsic
)
116 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
118 gl_shader_stage stage
= b
->shader
->info
.stage
;
120 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
121 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
123 if (!is_passthrough_tcs
&&
124 remap_tess_levels(b
, intrin
, tes_primitive_mode
))
127 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
128 assert(vue_slot
!= -1);
129 intrin
->const_index
[0] = vue_slot
;
131 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
133 if (nir_src_is_const(*vertex
)) {
134 intrin
->const_index
[0] += nir_src_as_uint(*vertex
) *
135 vue_map
->num_per_vertex_slots
;
137 b
->cursor
= nir_before_instr(&intrin
->instr
);
139 /* Multiply by the number of per-vertex slots. */
140 nir_ssa_def
*vertex_offset
=
142 nir_ssa_for_src(b
, *vertex
, 1),
144 vue_map
->num_per_vertex_slots
));
146 /* Add it to the existing offset */
147 nir_src
*offset
= nir_get_io_offset_src(intrin
);
148 nir_ssa_def
*total_offset
=
149 nir_iadd(b
, vertex_offset
,
150 nir_ssa_for_src(b
, *offset
, 1));
152 nir_instr_rewrite_src(&intrin
->instr
, offset
,
153 nir_src_for_ssa(total_offset
));
162 brw_nir_lower_vs_inputs(nir_shader
*nir
,
163 const uint8_t *vs_attrib_wa_flags
)
165 /* Start with the location of the variable's base. */
166 nir_foreach_shader_in_variable(var
, nir
)
167 var
->data
.driver_location
= var
->data
.location
;
169 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
170 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
171 * whether it is a double-precision type or not.
173 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
,
174 nir_lower_io_lower_64bit_to_32
);
176 /* This pass needs actual constants */
177 nir_opt_constant_folding(nir
);
179 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
181 brw_nir_apply_attribute_workarounds(nir
, vs_attrib_wa_flags
);
183 /* The last step is to remap VERT_ATTRIB_* to actual registers */
185 /* Whether or not we have any system generated values. gl_DrawID is not
186 * included here as it lives in its own vec4.
188 const bool has_sgvs
=
189 nir
->info
.system_values_read
&
190 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
) |
191 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
192 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
193 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
));
195 const unsigned num_inputs
= util_bitcount64(nir
->info
.inputs_read
);
197 nir_foreach_function(function
, nir
) {
202 nir_builder_init(&b
, function
->impl
);
204 nir_foreach_block(block
, function
->impl
) {
205 nir_foreach_instr_safe(instr
, block
) {
206 if (instr
->type
!= nir_instr_type_intrinsic
)
209 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
211 switch (intrin
->intrinsic
) {
212 case nir_intrinsic_load_first_vertex
:
213 case nir_intrinsic_load_base_instance
:
214 case nir_intrinsic_load_vertex_id_zero_base
:
215 case nir_intrinsic_load_instance_id
:
216 case nir_intrinsic_load_is_indexed_draw
:
217 case nir_intrinsic_load_draw_id
: {
218 b
.cursor
= nir_after_instr(&intrin
->instr
);
220 /* gl_VertexID and friends are stored by the VF as the last
221 * vertex element. We convert them to load_input intrinsics at
222 * the right location.
224 nir_intrinsic_instr
*load
=
225 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_input
);
226 load
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
228 nir_intrinsic_set_base(load
, num_inputs
);
229 switch (intrin
->intrinsic
) {
230 case nir_intrinsic_load_first_vertex
:
231 nir_intrinsic_set_component(load
, 0);
233 case nir_intrinsic_load_base_instance
:
234 nir_intrinsic_set_component(load
, 1);
236 case nir_intrinsic_load_vertex_id_zero_base
:
237 nir_intrinsic_set_component(load
, 2);
239 case nir_intrinsic_load_instance_id
:
240 nir_intrinsic_set_component(load
, 3);
242 case nir_intrinsic_load_draw_id
:
243 case nir_intrinsic_load_is_indexed_draw
:
244 /* gl_DrawID and IsIndexedDraw are stored right after
245 * gl_VertexID and friends if any of them exist.
247 nir_intrinsic_set_base(load
, num_inputs
+ has_sgvs
);
248 if (intrin
->intrinsic
== nir_intrinsic_load_draw_id
)
249 nir_intrinsic_set_component(load
, 0);
251 nir_intrinsic_set_component(load
, 1);
254 unreachable("Invalid system value intrinsic");
257 load
->num_components
= 1;
258 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
259 nir_builder_instr_insert(&b
, &load
->instr
);
261 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
262 nir_src_for_ssa(&load
->dest
.ssa
));
263 nir_instr_remove(&intrin
->instr
);
267 case nir_intrinsic_load_input
: {
268 /* Attributes come in a contiguous block, ordered by their
269 * gl_vert_attrib value. That means we can compute the slot
270 * number for an attribute by masking out the enabled attributes
271 * before it and counting the bits.
273 int attr
= nir_intrinsic_base(intrin
);
274 int slot
= util_bitcount64(nir
->info
.inputs_read
&
275 BITFIELD64_MASK(attr
));
276 nir_intrinsic_set_base(intrin
, slot
);
281 break; /* Nothing to do */
289 brw_nir_lower_vue_inputs(nir_shader
*nir
,
290 const struct brw_vue_map
*vue_map
)
292 nir_foreach_shader_in_variable(var
, nir
)
293 var
->data
.driver_location
= var
->data
.location
;
295 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
296 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
,
297 nir_lower_io_lower_64bit_to_32
);
299 /* This pass needs actual constants */
300 nir_opt_constant_folding(nir
);
302 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
304 nir_foreach_function(function
, nir
) {
308 nir_foreach_block(block
, function
->impl
) {
309 nir_foreach_instr(instr
, block
) {
310 if (instr
->type
!= nir_instr_type_intrinsic
)
313 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
315 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
316 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
317 /* Offset 0 is the VUE header, which contains
318 * VARYING_SLOT_LAYER [.y], VARYING_SLOT_VIEWPORT [.z], and
319 * VARYING_SLOT_PSIZ [.w].
321 int varying
= nir_intrinsic_base(intrin
);
324 case VARYING_SLOT_PSIZ
:
325 nir_intrinsic_set_base(intrin
, 0);
326 nir_intrinsic_set_component(intrin
, 3);
330 vue_slot
= vue_map
->varying_to_slot
[varying
];
331 assert(vue_slot
!= -1);
332 nir_intrinsic_set_base(intrin
, vue_slot
);
342 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
344 nir_foreach_shader_in_variable(var
, nir
)
345 var
->data
.driver_location
= var
->data
.location
;
347 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
,
348 nir_lower_io_lower_64bit_to_32
);
350 /* This pass needs actual constants */
351 nir_opt_constant_folding(nir
);
353 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
355 nir_foreach_function(function
, nir
) {
356 if (function
->impl
) {
358 nir_builder_init(&b
, function
->impl
);
359 nir_foreach_block(block
, function
->impl
) {
360 remap_patch_urb_offsets(block
, &b
, vue_map
,
361 nir
->info
.tess
.primitive_mode
);
368 brw_nir_lower_fs_inputs(nir_shader
*nir
,
369 const struct gen_device_info
*devinfo
,
370 const struct brw_wm_prog_key
*key
)
372 nir_foreach_shader_in_variable(var
, nir
) {
373 var
->data
.driver_location
= var
->data
.location
;
375 /* Apply default interpolation mode.
377 * Everything defaults to smooth except for the legacy GL color
378 * built-in variables, which might be flat depending on API state.
380 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
381 const bool flat
= key
->flat_shade
&&
382 (var
->data
.location
== VARYING_SLOT_COL0
||
383 var
->data
.location
== VARYING_SLOT_COL1
);
385 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
386 : INTERP_MODE_SMOOTH
;
389 /* On Ironlake and below, there is only one interpolation mode.
390 * Centroid interpolation doesn't mean anything on this hardware --
391 * there is no multisampling.
393 if (devinfo
->gen
< 6) {
394 var
->data
.centroid
= false;
395 var
->data
.sample
= false;
399 nir_lower_io_options lower_io_options
= nir_lower_io_lower_64bit_to_32
;
400 if (key
->persample_interp
)
401 lower_io_options
|= nir_lower_io_force_sample_interpolation
;
403 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, lower_io_options
);
404 if (devinfo
->gen
>= 11)
405 nir_lower_interpolation(nir
, ~0);
407 /* This pass needs actual constants */
408 nir_opt_constant_folding(nir
);
410 nir_io_add_const_offset_to_base(nir
, nir_var_shader_in
);
414 brw_nir_lower_vue_outputs(nir_shader
*nir
)
416 nir_foreach_shader_out_variable(var
, nir
) {
417 var
->data
.driver_location
= var
->data
.location
;
420 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
,
421 nir_lower_io_lower_64bit_to_32
);
425 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
,
426 GLenum tes_primitive_mode
)
428 nir_foreach_shader_out_variable(var
, nir
) {
429 var
->data
.driver_location
= var
->data
.location
;
432 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
,
433 nir_lower_io_lower_64bit_to_32
);
435 /* This pass needs actual constants */
436 nir_opt_constant_folding(nir
);
438 nir_io_add_const_offset_to_base(nir
, nir_var_shader_out
);
440 nir_foreach_function(function
, nir
) {
441 if (function
->impl
) {
443 nir_builder_init(&b
, function
->impl
);
444 nir_foreach_block(block
, function
->impl
) {
445 remap_patch_urb_offsets(block
, &b
, vue_map
, tes_primitive_mode
);
452 brw_nir_lower_fs_outputs(nir_shader
*nir
)
454 nir_foreach_shader_out_variable(var
, nir
) {
455 var
->data
.driver_location
=
456 SET_FIELD(var
->data
.index
, BRW_NIR_FRAG_OUTPUT_INDEX
) |
457 SET_FIELD(var
->data
.location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
460 nir_lower_io(nir
, nir_var_shader_out
, type_size_dvec4
, 0);
463 #define OPT(pass, ...) ({ \
464 bool this_progress = false; \
465 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
471 static nir_variable_mode
472 brw_nir_no_indirect_mask(const struct brw_compiler
*compiler
,
473 gl_shader_stage stage
)
475 nir_variable_mode indirect_mask
= 0;
477 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
478 indirect_mask
|= nir_var_shader_in
;
479 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectOutput
)
480 indirect_mask
|= nir_var_shader_out
;
481 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
482 indirect_mask
|= nir_var_function_temp
;
484 return indirect_mask
;
488 brw_nir_optimize(nir_shader
*nir
, const struct brw_compiler
*compiler
,
489 bool is_scalar
, bool allow_copies
)
491 nir_variable_mode indirect_mask
=
492 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
495 unsigned lower_flrp
=
496 (nir
->options
->lower_flrp16
? 16 : 0) |
497 (nir
->options
->lower_flrp32
? 32 : 0) |
498 (nir
->options
->lower_flrp64
? 64 : 0);
502 OPT(nir_split_array_vars
, nir_var_function_temp
);
503 OPT(nir_shrink_vec_array_vars
, nir_var_function_temp
);
505 OPT(nir_lower_vars_to_ssa
);
507 /* Only run this pass in the first call to brw_nir_optimize. Later
508 * calls assume that we've lowered away any copy_deref instructions
509 * and we don't want to introduce any more.
511 OPT(nir_opt_find_array_copies
);
513 OPT(nir_opt_copy_prop_vars
);
514 OPT(nir_opt_dead_write_vars
);
515 OPT(nir_opt_combine_stores
, nir_var_all
);
518 OPT(nir_lower_alu_to_scalar
, NULL
, NULL
);
520 OPT(nir_opt_shrink_vectors
);
526 OPT(nir_lower_phis_to_scalar
);
532 OPT(nir_opt_combine_stores
, nir_var_all
);
534 /* Passing 0 to the peephole select pass causes it to convert
535 * if-statements that contain only move instructions in the branches
536 * regardless of the count.
538 * Passing 1 to the peephole select pass causes it to convert
539 * if-statements that contain at most a single ALU instruction (total)
540 * in both branches. Before Gen6, some math instructions were
541 * prohibitively expensive and the results of compare operations need an
542 * extra resolve step. For these reasons, this pass is more harmful
543 * than good on those platforms.
545 * For indirect loads of uniforms (push constants), we assume that array
546 * indices will nearly always be in bounds and the cost of the load is
547 * low. Therefore there shouldn't be a performance benefit to avoid it.
548 * However, in vec4 tessellation shaders, these loads operate by
549 * actually pulling from memory.
551 const bool is_vec4_tessellation
= !is_scalar
&&
552 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
553 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
554 OPT(nir_opt_peephole_select
, 0, !is_vec4_tessellation
, false);
555 OPT(nir_opt_peephole_select
, 8, !is_vec4_tessellation
,
556 compiler
->devinfo
->gen
>= 6);
558 OPT(nir_opt_intrinsics
);
559 OPT(nir_opt_idiv_const
, 32);
560 OPT(nir_opt_algebraic
);
561 OPT(nir_opt_constant_folding
);
563 if (lower_flrp
!= 0) {
564 if (OPT(nir_lower_flrp
,
566 false /* always_precise */,
567 compiler
->devinfo
->gen
>= 6)) {
568 OPT(nir_opt_constant_folding
);
571 /* Nothing should rematerialize any flrps, so we only need to do this
577 OPT(nir_opt_dead_cf
);
578 if (OPT(nir_opt_trivial_continues
)) {
579 /* If nir_opt_trivial_continues makes progress, then we need to clean
580 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
586 OPT(nir_opt_if
, false);
587 OPT(nir_opt_conditional_discard
);
588 if (nir
->options
->max_unroll_iterations
!= 0) {
589 OPT(nir_opt_loop_unroll
, indirect_mask
);
591 OPT(nir_opt_remove_phis
);
596 /* Workaround Gfxbench unused local sampler variable which will trigger an
597 * assert in the opt_large_constants pass.
599 OPT(nir_remove_dead_variables
, nir_var_function_temp
, NULL
);
603 lower_bit_size_callback(const nir_alu_instr
*alu
, UNUSED
void *data
)
605 assert(alu
->dest
.dest
.is_ssa
);
606 if (alu
->dest
.dest
.ssa
.bit_size
>= 32)
609 const struct brw_compiler
*compiler
= (const struct brw_compiler
*) data
;
620 case nir_op_fround_even
:
631 return compiler
->devinfo
->gen
< 9 ? 32 : 0;
637 /* Does some simple lowering and runs the standard suite of optimizations
639 * This is intended to be called more-or-less directly after you get the
640 * shader out of GLSL or some other source. While it is geared towards i965,
641 * it is not at all generator-specific except for the is_scalar flag. Even
642 * there, it is safe to call with is_scalar = false for a shader that is
643 * intended for the FS backend as long as nir_optimize is called again with
644 * is_scalar = true to scalarize everything prior to code gen.
647 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
,
648 const nir_shader
*softfp64
)
650 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
651 UNUSED
bool progress
; /* Written by OPT */
653 const bool is_scalar
= compiler
->scalar_stage
[nir
->info
.stage
];
656 OPT(nir_lower_alu_to_scalar
, NULL
, NULL
);
659 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
660 OPT(nir_lower_gs_intrinsics
, false);
662 /* See also brw_nir_trig_workarounds.py */
663 if (compiler
->precise_trig
&&
664 !(devinfo
->gen
>= 10 || devinfo
->is_kabylake
))
665 OPT(brw_nir_apply_trig_workarounds
);
667 if (devinfo
->gen
>= 12)
668 OPT(brw_nir_clamp_image_1d_2d_array_sizes
);
670 static const nir_lower_tex_options tex_options
= {
672 .lower_txf_offset
= true,
673 .lower_rect_offset
= true,
674 .lower_tex_without_implicit_lod
= true,
675 .lower_txd_cube_map
= true,
676 .lower_txb_shadow_clamp
= true,
677 .lower_txd_shadow_clamp
= true,
678 .lower_txd_offset_clamp
= true,
679 .lower_tg4_offsets
= true,
682 OPT(nir_lower_tex
, &tex_options
);
683 OPT(nir_normalize_cubemap_coords
);
685 OPT(nir_lower_global_vars_to_local
);
687 OPT(nir_split_var_copies
);
688 OPT(nir_split_struct_vars
, nir_var_function_temp
);
690 brw_nir_optimize(nir
, compiler
, is_scalar
, true);
692 OPT(nir_lower_doubles
, softfp64
, nir
->options
->lower_doubles_options
);
693 OPT(nir_lower_int64
);
695 OPT(nir_lower_bit_size
, lower_bit_size_callback
, (void *)compiler
);
698 OPT(nir_lower_load_const_to_scalar
);
701 /* Lower a bunch of stuff */
702 OPT(nir_lower_var_copies
);
704 /* This needs to be run after the first optimization pass but before we
705 * lower indirect derefs away
707 if (compiler
->supports_shader_constants
) {
708 OPT(nir_opt_large_constants
, NULL
, 32);
711 OPT(nir_lower_system_values
);
713 const nir_lower_subgroups_options subgroups_options
= {
714 .ballot_bit_size
= 32,
715 .lower_to_scalar
= true,
716 .lower_vote_trivial
= !is_scalar
,
717 .lower_shuffle
= true,
718 .lower_quad_broadcast_dynamic
= true,
720 OPT(nir_lower_subgroups
, &subgroups_options
);
722 OPT(nir_lower_clip_cull_distance_arrays
);
724 if ((devinfo
->gen
>= 8 || devinfo
->is_haswell
) && is_scalar
) {
725 /* TODO: Yes, we could in theory do this on gen6 and earlier. However,
726 * that would require plumbing through support for these indirect
727 * scratch read/write messages with message registers and that's just a
728 * pain. Also, the primary benefit of this is for compute shaders which
729 * won't run on gen6 and earlier anyway.
731 * On gen7 and earlier the scratch space size is limited to 12kB.
732 * By enabling this optimization we may easily exceed this limit without
733 * having any fallback.
735 * The threshold of 128B was chosen semi-arbitrarily. The idea is that
736 * 128B per channel on a SIMD8 program is 32 registers or 25% of the
737 * register file. Any array that large is likely to cause pressure
738 * issues. Also, this value is sufficiently high that the benchmarks
739 * known to suffer from large temporary array issues are helped but
740 * nothing else in shader-db is hurt except for maybe that one kerbal
741 * space program shader.
743 OPT(nir_lower_vars_to_scratch
, nir_var_function_temp
, 128,
744 glsl_get_natural_size_align_bytes
);
747 nir_variable_mode indirect_mask
=
748 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
749 OPT(nir_lower_indirect_derefs
, indirect_mask
);
751 /* Lower array derefs of vectors for SSBO and UBO loads. For both UBOs and
752 * SSBOs, our back-end is capable of loading an entire vec4 at a time and
753 * we would like to take advantage of that whenever possible regardless of
754 * whether or not the app gives us full loads. This should allow the
755 * optimizer to combine UBO and SSBO load operations and save us some send
758 OPT(nir_lower_array_deref_of_vec
,
759 nir_var_mem_ubo
| nir_var_mem_ssbo
,
760 nir_lower_direct_array_deref_of_vec_load
);
762 /* Get rid of split copies */
763 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
767 brw_nir_link_shaders(const struct brw_compiler
*compiler
,
768 nir_shader
*producer
, nir_shader
*consumer
)
770 nir_lower_io_arrays_to_elements(producer
, consumer
);
771 nir_validate_shader(producer
, "after nir_lower_io_arrays_to_elements");
772 nir_validate_shader(consumer
, "after nir_lower_io_arrays_to_elements");
774 const bool p_is_scalar
= compiler
->scalar_stage
[producer
->info
.stage
];
775 const bool c_is_scalar
= compiler
->scalar_stage
[consumer
->info
.stage
];
777 if (p_is_scalar
&& c_is_scalar
) {
778 NIR_PASS_V(producer
, nir_lower_io_to_scalar_early
, nir_var_shader_out
);
779 NIR_PASS_V(consumer
, nir_lower_io_to_scalar_early
, nir_var_shader_in
);
780 brw_nir_optimize(producer
, compiler
, p_is_scalar
, false);
781 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
784 if (nir_link_opt_varyings(producer
, consumer
))
785 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
787 NIR_PASS_V(producer
, nir_remove_dead_variables
, nir_var_shader_out
, NULL
);
788 NIR_PASS_V(consumer
, nir_remove_dead_variables
, nir_var_shader_in
, NULL
);
790 if (nir_remove_unused_varyings(producer
, consumer
)) {
791 NIR_PASS_V(producer
, nir_lower_global_vars_to_local
);
792 NIR_PASS_V(consumer
, nir_lower_global_vars_to_local
);
794 /* The backend might not be able to handle indirects on
795 * temporaries so we need to lower indirects on any of the
796 * varyings we have demoted here.
798 NIR_PASS_V(producer
, nir_lower_indirect_derefs
,
799 brw_nir_no_indirect_mask(compiler
, producer
->info
.stage
));
800 NIR_PASS_V(consumer
, nir_lower_indirect_derefs
,
801 brw_nir_no_indirect_mask(compiler
, consumer
->info
.stage
));
803 brw_nir_optimize(producer
, compiler
, p_is_scalar
, false);
804 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
807 NIR_PASS_V(producer
, nir_lower_io_to_vector
, nir_var_shader_out
);
808 NIR_PASS_V(producer
, nir_opt_combine_stores
, nir_var_shader_out
);
809 NIR_PASS_V(consumer
, nir_lower_io_to_vector
, nir_var_shader_in
);
811 if (producer
->info
.stage
!= MESA_SHADER_TESS_CTRL
) {
812 /* Calling lower_io_to_vector creates output variable writes with
813 * write-masks. On non-TCS outputs, the back-end can't handle it and we
814 * need to call nir_lower_io_to_temporaries to get rid of them. This,
815 * in turn, creates temporary variables and extra copy_deref intrinsics
816 * that we need to clean up.
818 NIR_PASS_V(producer
, nir_lower_io_to_temporaries
,
819 nir_shader_get_entrypoint(producer
), true, false);
820 NIR_PASS_V(producer
, nir_lower_global_vars_to_local
);
821 NIR_PASS_V(producer
, nir_split_var_copies
);
822 NIR_PASS_V(producer
, nir_lower_var_copies
);
827 brw_nir_should_vectorize_mem(unsigned align
, unsigned bit_size
,
828 unsigned num_components
, unsigned high_offset
,
829 nir_intrinsic_instr
*low
,
830 nir_intrinsic_instr
*high
)
832 /* Don't combine things to generate 64-bit loads/stores. We have to split
833 * those back into 32-bit ones anyway and UBO loads aren't split in NIR so
834 * we don't want to make a mess for the back-end.
839 /* We can handle at most a vec4 right now. Anything bigger would get
840 * immediately split by brw_nir_lower_mem_access_bit_sizes anyway.
842 if (num_components
> 4)
845 if (align
< bit_size
/ 8)
852 bool combine_all_barriers(nir_intrinsic_instr
*a
,
853 nir_intrinsic_instr
*b
,
856 /* Translation to backend IR will get rid of modes we don't care about, so
857 * no harm in always combining them.
859 * TODO: While HW has only ACQUIRE|RELEASE fences, we could improve the
860 * scheduling so that it can take advantage of the different semantics.
862 nir_intrinsic_set_memory_modes(a
, nir_intrinsic_memory_modes(a
) |
863 nir_intrinsic_memory_modes(b
));
864 nir_intrinsic_set_memory_semantics(a
, nir_intrinsic_memory_semantics(a
) |
865 nir_intrinsic_memory_semantics(b
));
866 nir_intrinsic_set_memory_scope(a
, MAX2(nir_intrinsic_memory_scope(a
),
867 nir_intrinsic_memory_scope(b
)));
872 brw_vectorize_lower_mem_access(nir_shader
*nir
,
873 const struct brw_compiler
*compiler
,
876 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
877 bool progress
= false;
880 OPT(nir_opt_load_store_vectorize
,
881 nir_var_mem_ubo
| nir_var_mem_ssbo
|
882 nir_var_mem_global
| nir_var_mem_shared
,
883 brw_nir_should_vectorize_mem
,
884 (nir_variable_mode
)0);
887 OPT(brw_nir_lower_mem_access_bit_sizes
, devinfo
);
896 OPT(nir_opt_algebraic
);
897 OPT(nir_opt_constant_folding
);
901 /* Prepare the given shader for codegen
903 * This function is intended to be called right before going into the actual
904 * backend and is highly backend-specific. Also, once this function has been
905 * called on a shader, it will no longer be in SSA form so most optimizations
909 brw_postprocess_nir(nir_shader
*nir
, const struct brw_compiler
*compiler
,
912 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
914 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->info
.stage
));
916 UNUSED
bool progress
; /* Written by OPT */
918 OPT(brw_nir_lower_scoped_barriers
);
919 OPT(nir_opt_combine_memory_barriers
, combine_all_barriers
, NULL
);
923 OPT(nir_opt_algebraic_before_ffma
);
926 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
928 brw_vectorize_lower_mem_access(nir
, compiler
, is_scalar
);
930 if (OPT(nir_lower_int64
))
931 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
933 if (devinfo
->gen
>= 6) {
934 /* Try and fuse multiply-adds */
935 OPT(brw_nir_opt_peephole_ffma
);
938 if (OPT(nir_opt_comparison_pre
)) {
943 /* Do the select peepehole again. nir_opt_comparison_pre (combined with
944 * the other optimization passes) will have removed at least one
945 * instruction from one of the branches of the if-statement, so now it
946 * might be under the threshold of conversion to bcsel.
948 * See brw_nir_optimize for the explanation of is_vec4_tessellation.
950 const bool is_vec4_tessellation
= !is_scalar
&&
951 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
952 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
953 OPT(nir_opt_peephole_select
, 0, is_vec4_tessellation
, false);
954 OPT(nir_opt_peephole_select
, 1, is_vec4_tessellation
,
955 compiler
->devinfo
->gen
>= 6);
960 if (OPT(nir_opt_algebraic_late
)) {
961 /* At this late stage, anything that makes more constants will wreak
962 * havok on the vec4 backend. The handling of constants in the vec4
963 * backend is not good.
966 OPT(nir_opt_constant_folding
);
975 OPT(brw_nir_lower_conversions
);
978 OPT(nir_lower_alu_to_scalar
, NULL
, NULL
);
980 while (OPT(nir_opt_algebraic_distribute_src_mods
)) {
988 OPT(nir_opt_move
, nir_move_comparisons
);
990 OPT(nir_lower_bool_to_int32
);
994 OPT(nir_lower_locals_to_regs
);
996 if (unlikely(debug_enabled
)) {
997 /* Re-index SSA defs so we print more sensible numbers. */
998 nir_foreach_function(function
, nir
) {
1000 nir_index_ssa_defs(function
->impl
);
1003 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
1004 _mesa_shader_stage_to_string(nir
->info
.stage
));
1005 nir_print_shader(nir
, stderr
);
1008 OPT(nir_convert_from_ssa
, true);
1011 OPT(nir_move_vec_src_uses_to_dest
);
1012 OPT(nir_lower_vec_to_movs
);
1017 if (OPT(nir_opt_rematerialize_compares
))
1020 /* This is the last pass we run before we start emitting stuff. It
1021 * determines when we need to insert boolean resolves on Gen <= 5. We
1022 * run it last because it stashes data in instr->pass_flags and we don't
1023 * want that to be squashed by other NIR passes.
1025 if (devinfo
->gen
<= 5)
1026 brw_nir_analyze_boolean_resolves(nir
);
1030 if (unlikely(debug_enabled
)) {
1031 fprintf(stderr
, "NIR (final form) for %s shader:\n",
1032 _mesa_shader_stage_to_string(nir
->info
.stage
));
1033 nir_print_shader(nir
, stderr
);
1038 brw_nir_apply_sampler_key(nir_shader
*nir
,
1039 const struct brw_compiler
*compiler
,
1040 const struct brw_sampler_prog_key_data
*key_tex
)
1042 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
1043 nir_lower_tex_options tex_options
= {
1044 .lower_txd_clamp_bindless_sampler
= true,
1045 .lower_txd_clamp_if_sampler_index_not_lt_16
= true,
1048 /* Iron Lake and prior require lowering of all rectangle textures */
1049 if (devinfo
->gen
< 6)
1050 tex_options
.lower_rect
= true;
1052 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
1053 if (devinfo
->gen
< 8) {
1054 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
1055 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
1056 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
1059 /* Prior to Haswell, we have to fake texture swizzle */
1060 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
1061 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
1064 tex_options
.swizzle_result
|= BITFIELD_BIT(s
);
1065 for (unsigned c
= 0; c
< 4; c
++)
1066 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
1069 /* Prior to Haswell, we have to lower gradients on shadow samplers */
1070 tex_options
.lower_txd_shadow
= devinfo
->gen
< 8 && !devinfo
->is_haswell
;
1072 tex_options
.lower_y_uv_external
= key_tex
->y_uv_image_mask
;
1073 tex_options
.lower_y_u_v_external
= key_tex
->y_u_v_image_mask
;
1074 tex_options
.lower_yx_xuxv_external
= key_tex
->yx_xuxv_image_mask
;
1075 tex_options
.lower_xy_uxvx_external
= key_tex
->xy_uxvx_image_mask
;
1076 tex_options
.lower_ayuv_external
= key_tex
->ayuv_image_mask
;
1077 tex_options
.lower_xyuv_external
= key_tex
->xyuv_image_mask
;
1078 tex_options
.bt709_external
= key_tex
->bt709_mask
;
1079 tex_options
.bt2020_external
= key_tex
->bt2020_mask
;
1081 /* Setup array of scaling factors for each texture. */
1082 memcpy(&tex_options
.scale_factors
, &key_tex
->scale_factors
,
1083 sizeof(tex_options
.scale_factors
));
1085 return nir_lower_tex(nir
, &tex_options
);
1089 get_subgroup_size(gl_shader_stage stage
,
1090 const struct brw_base_prog_key
*key
,
1091 unsigned max_subgroup_size
)
1093 switch (key
->subgroup_size_type
) {
1094 case BRW_SUBGROUP_SIZE_API_CONSTANT
:
1095 /* We have to use the global constant size. */
1096 return BRW_SUBGROUP_SIZE
;
1098 case BRW_SUBGROUP_SIZE_UNIFORM
:
1099 /* It has to be uniform across all invocations but can vary per stage
1100 * if we want. This gives us a bit more freedom.
1102 * For compute, brw_nir_apply_key is called per-dispatch-width so this
1103 * is the actual subgroup size and not a maximum. However, we only
1104 * invoke one size of any given compute shader so it's still guaranteed
1105 * to be uniform across invocations.
1107 return max_subgroup_size
;
1109 case BRW_SUBGROUP_SIZE_VARYING
:
1110 /* The subgroup size is allowed to be fully varying. For geometry
1111 * stages, we know it's always 8 which is max_subgroup_size so we can
1112 * return that. For compute, brw_nir_apply_key is called once per
1113 * dispatch-width so max_subgroup_size is the real subgroup size.
1115 * For fragment, we return 0 and let it fall through to the back-end
1116 * compiler. This means we can't optimize based on subgroup size but
1117 * that's a risk the client took when it asked for a varying subgroup
1120 return stage
== MESA_SHADER_FRAGMENT
? 0 : max_subgroup_size
;
1122 case BRW_SUBGROUP_SIZE_REQUIRE_8
:
1123 case BRW_SUBGROUP_SIZE_REQUIRE_16
:
1124 case BRW_SUBGROUP_SIZE_REQUIRE_32
:
1125 assert(stage
== MESA_SHADER_COMPUTE
);
1126 /* These enum values are expressly chosen to be equal to the subgroup
1127 * size that they require.
1129 return key
->subgroup_size_type
;
1132 unreachable("Invalid subgroup size type");
1136 brw_nir_apply_key(nir_shader
*nir
,
1137 const struct brw_compiler
*compiler
,
1138 const struct brw_base_prog_key
*key
,
1139 unsigned max_subgroup_size
,
1142 bool progress
= false;
1144 OPT(brw_nir_apply_sampler_key
, compiler
, &key
->tex
);
1146 const nir_lower_subgroups_options subgroups_options
= {
1147 .subgroup_size
= get_subgroup_size(nir
->info
.stage
, key
,
1149 .ballot_bit_size
= 32,
1150 .lower_subgroup_masks
= true,
1152 OPT(nir_lower_subgroups
, &subgroups_options
);
1155 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
1158 enum brw_conditional_mod
1159 brw_cmod_for_nir_comparison(nir_op op
)
1168 return BRW_CONDITIONAL_L
;
1176 return BRW_CONDITIONAL_GE
;
1182 case nir_op_b32all_fequal2
:
1183 case nir_op_b32all_iequal2
:
1184 case nir_op_b32all_fequal3
:
1185 case nir_op_b32all_iequal3
:
1186 case nir_op_b32all_fequal4
:
1187 case nir_op_b32all_iequal4
:
1188 return BRW_CONDITIONAL_Z
;
1194 case nir_op_b32any_fnequal2
:
1195 case nir_op_b32any_inequal2
:
1196 case nir_op_b32any_fnequal3
:
1197 case nir_op_b32any_inequal3
:
1198 case nir_op_b32any_fnequal4
:
1199 case nir_op_b32any_inequal4
:
1200 return BRW_CONDITIONAL_NZ
;
1203 unreachable("Unsupported NIR comparison op");
1208 brw_aop_for_nir_intrinsic(const nir_intrinsic_instr
*atomic
)
1210 switch (atomic
->intrinsic
) {
1211 #define AOP_CASE(atom) \
1212 case nir_intrinsic_image_atomic_##atom: \
1213 case nir_intrinsic_bindless_image_atomic_##atom: \
1214 case nir_intrinsic_ssbo_atomic_##atom: \
1215 case nir_intrinsic_shared_atomic_##atom: \
1216 case nir_intrinsic_global_atomic_##atom
1220 switch (atomic
->intrinsic
) {
1221 case nir_intrinsic_image_atomic_add
:
1222 case nir_intrinsic_bindless_image_atomic_add
:
1225 case nir_intrinsic_ssbo_atomic_add
:
1228 case nir_intrinsic_shared_atomic_add
:
1229 case nir_intrinsic_global_atomic_add
:
1233 unreachable("Invalid add atomic opcode");
1236 if (nir_src_is_const(atomic
->src
[src_idx
])) {
1237 int64_t add_val
= nir_src_as_int(atomic
->src
[src_idx
]);
1240 else if (add_val
== -1)
1246 AOP_CASE(imin
): return BRW_AOP_IMIN
;
1247 AOP_CASE(umin
): return BRW_AOP_UMIN
;
1248 AOP_CASE(imax
): return BRW_AOP_IMAX
;
1249 AOP_CASE(umax
): return BRW_AOP_UMAX
;
1250 AOP_CASE(and): return BRW_AOP_AND
;
1251 AOP_CASE(or): return BRW_AOP_OR
;
1252 AOP_CASE(xor): return BRW_AOP_XOR
;
1253 AOP_CASE(exchange
): return BRW_AOP_MOV
;
1254 AOP_CASE(comp_swap
): return BRW_AOP_CMPWR
;
1257 #define AOP_CASE(atom) \
1258 case nir_intrinsic_ssbo_atomic_##atom: \
1259 case nir_intrinsic_shared_atomic_##atom: \
1260 case nir_intrinsic_global_atomic_##atom
1262 AOP_CASE(fmin
): return BRW_AOP_FMIN
;
1263 AOP_CASE(fmax
): return BRW_AOP_FMAX
;
1264 AOP_CASE(fcomp_swap
): return BRW_AOP_FCMPWR
;
1269 unreachable("Unsupported NIR atomic intrinsic");
1274 brw_type_for_nir_type(const struct gen_device_info
*devinfo
, nir_alu_type type
)
1278 case nir_type_uint32
:
1279 return BRW_REGISTER_TYPE_UD
;
1282 case nir_type_bool32
:
1283 case nir_type_int32
:
1284 return BRW_REGISTER_TYPE_D
;
1285 case nir_type_float
:
1286 case nir_type_float32
:
1287 return BRW_REGISTER_TYPE_F
;
1288 case nir_type_float16
:
1289 return BRW_REGISTER_TYPE_HF
;
1290 case nir_type_float64
:
1291 return BRW_REGISTER_TYPE_DF
;
1292 case nir_type_int64
:
1293 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_Q
;
1294 case nir_type_uint64
:
1295 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_UQ
;
1296 case nir_type_int16
:
1297 return BRW_REGISTER_TYPE_W
;
1298 case nir_type_uint16
:
1299 return BRW_REGISTER_TYPE_UW
;
1301 return BRW_REGISTER_TYPE_B
;
1302 case nir_type_uint8
:
1303 return BRW_REGISTER_TYPE_UB
;
1305 unreachable("unknown type");
1308 return BRW_REGISTER_TYPE_F
;
1311 /* Returns the glsl_base_type corresponding to a nir_alu_type.
1312 * This is used by both brw_vec4_nir and brw_fs_nir.
1315 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
1318 case nir_type_float
:
1319 case nir_type_float32
:
1320 return GLSL_TYPE_FLOAT
;
1322 case nir_type_float16
:
1323 return GLSL_TYPE_FLOAT16
;
1325 case nir_type_float64
:
1326 return GLSL_TYPE_DOUBLE
;
1329 case nir_type_int32
:
1330 return GLSL_TYPE_INT
;
1333 case nir_type_uint32
:
1334 return GLSL_TYPE_UINT
;
1336 case nir_type_int16
:
1337 return GLSL_TYPE_INT16
;
1339 case nir_type_uint16
:
1340 return GLSL_TYPE_UINT16
;
1343 unreachable("bad type");
1348 brw_nir_create_passthrough_tcs(void *mem_ctx
, const struct brw_compiler
*compiler
,
1349 const nir_shader_compiler_options
*options
,
1350 const struct brw_tcs_prog_key
*key
)
1353 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_TESS_CTRL
,
1355 nir_shader
*nir
= b
.shader
;
1357 nir_intrinsic_instr
*load
;
1358 nir_intrinsic_instr
*store
;
1359 nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
1360 nir_ssa_def
*invoc_id
= nir_load_invocation_id(&b
);
1362 nir
->info
.inputs_read
= key
->outputs_written
&
1363 ~(VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
);
1364 nir
->info
.outputs_written
= key
->outputs_written
;
1365 nir
->info
.tess
.tcs_vertices_out
= key
->input_vertices
;
1366 nir
->info
.name
= ralloc_strdup(nir
, "passthrough");
1367 nir
->num_uniforms
= 8 * sizeof(uint32_t);
1369 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_0");
1370 var
->data
.location
= 0;
1371 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_1");
1372 var
->data
.location
= 1;
1374 /* Write the patch URB header. */
1375 for (int i
= 0; i
<= 1; i
++) {
1376 load
= nir_intrinsic_instr_create(nir
, nir_intrinsic_load_uniform
);
1377 load
->num_components
= 4;
1378 load
->src
[0] = nir_src_for_ssa(zero
);
1379 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1380 nir_intrinsic_set_base(load
, i
* 4 * sizeof(uint32_t));
1381 nir_builder_instr_insert(&b
, &load
->instr
);
1383 store
= nir_intrinsic_instr_create(nir
, nir_intrinsic_store_output
);
1384 store
->num_components
= 4;
1385 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1386 store
->src
[1] = nir_src_for_ssa(zero
);
1387 nir_intrinsic_set_base(store
, VARYING_SLOT_TESS_LEVEL_INNER
- i
);
1388 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1389 nir_builder_instr_insert(&b
, &store
->instr
);
1392 /* Copy inputs to outputs. */
1393 uint64_t varyings
= nir
->info
.inputs_read
;
1395 while (varyings
!= 0) {
1396 const int varying
= ffsll(varyings
) - 1;
1398 load
= nir_intrinsic_instr_create(nir
,
1399 nir_intrinsic_load_per_vertex_input
);
1400 load
->num_components
= 4;
1401 load
->src
[0] = nir_src_for_ssa(invoc_id
);
1402 load
->src
[1] = nir_src_for_ssa(zero
);
1403 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1404 nir_intrinsic_set_base(load
, varying
);
1405 nir_builder_instr_insert(&b
, &load
->instr
);
1407 store
= nir_intrinsic_instr_create(nir
,
1408 nir_intrinsic_store_per_vertex_output
);
1409 store
->num_components
= 4;
1410 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1411 store
->src
[1] = nir_src_for_ssa(invoc_id
);
1412 store
->src
[2] = nir_src_for_ssa(zero
);
1413 nir_intrinsic_set_base(store
, varying
);
1414 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1415 nir_builder_instr_insert(&b
, &store
->instr
);
1417 varyings
&= ~BITFIELD64_BIT(varying
);
1420 nir_validate_shader(nir
, "in brw_nir_create_passthrough_tcs");
1422 brw_preprocess_nir(compiler
, nir
, NULL
);