2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_shader.h"
26 #include "dev/gen_debug.h"
27 #include "compiler/glsl_types.h"
28 #include "compiler/nir/nir_builder.h"
29 #include "util/u_math.h"
32 is_input(nir_intrinsic_instr
*intrin
)
34 return intrin
->intrinsic
== nir_intrinsic_load_input
||
35 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
||
36 intrin
->intrinsic
== nir_intrinsic_load_interpolated_input
||
37 intrin
->intrinsic
== nir_intrinsic_load_fs_input_interp_deltas
;
41 is_output(nir_intrinsic_instr
*intrin
)
43 return intrin
->intrinsic
== nir_intrinsic_load_output
||
44 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_output
||
45 intrin
->intrinsic
== nir_intrinsic_store_output
||
46 intrin
->intrinsic
== nir_intrinsic_store_per_vertex_output
;
50 * In many cases, we just add the base and offset together, so there's no
51 * reason to keep them separate. Sometimes, combining them is essential:
52 * if a shader only accesses part of a compound variable (such as a matrix
53 * or array), the variable's base may not actually exist in the VUE map.
55 * This pass adds constant offsets to instr->const_index[0], and resets
56 * the offset source to 0. Non-constant offsets remain unchanged - since
57 * we don't know what part of a compound variable is accessed, we allocate
58 * storage for the entire thing.
62 add_const_offset_to_base_block(nir_block
*block
, nir_builder
*b
,
63 nir_variable_mode mode
)
65 nir_foreach_instr_safe(instr
, block
) {
66 if (instr
->type
!= nir_instr_type_intrinsic
)
69 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
71 if ((mode
== nir_var_shader_in
&& is_input(intrin
)) ||
72 (mode
== nir_var_shader_out
&& is_output(intrin
))) {
73 nir_src
*offset
= nir_get_io_offset_src(intrin
);
75 if (nir_src_is_const(*offset
)) {
76 intrin
->const_index
[0] += nir_src_as_uint(*offset
);
77 b
->cursor
= nir_before_instr(&intrin
->instr
);
78 nir_instr_rewrite_src(&intrin
->instr
, offset
,
79 nir_src_for_ssa(nir_imm_int(b
, 0)));
87 add_const_offset_to_base(nir_shader
*nir
, nir_variable_mode mode
)
89 nir_foreach_function(f
, nir
) {
92 nir_builder_init(&b
, f
->impl
);
93 nir_foreach_block(block
, f
->impl
) {
94 add_const_offset_to_base_block(block
, &b
, mode
);
101 remap_tess_levels(nir_builder
*b
, nir_intrinsic_instr
*intr
,
102 GLenum primitive_mode
)
104 const int location
= nir_intrinsic_base(intr
);
105 const unsigned component
= nir_intrinsic_component(intr
);
108 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
) {
109 switch (primitive_mode
) {
111 /* gl_TessLevelInner[0..1] lives at DWords 3-2 (reversed). */
112 nir_intrinsic_set_base(intr
, 0);
113 nir_intrinsic_set_component(intr
, 3 - component
);
114 out_of_bounds
= false;
117 /* gl_TessLevelInner[0] lives at DWord 4. */
118 nir_intrinsic_set_base(intr
, 1);
119 out_of_bounds
= component
> 0;
122 out_of_bounds
= true;
125 unreachable("Bogus tessellation domain");
127 } else if (location
== VARYING_SLOT_TESS_LEVEL_OUTER
) {
128 if (primitive_mode
== GL_ISOLINES
) {
129 /* gl_TessLevelOuter[0..1] lives at DWords 6-7 (in order). */
130 nir_intrinsic_set_base(intr
, 1);
131 nir_intrinsic_set_component(intr
, 2 + nir_intrinsic_component(intr
));
132 out_of_bounds
= component
> 1;
134 /* Triangles use DWords 7-5 (reversed); Quads use 7-4 (reversed) */
135 nir_intrinsic_set_base(intr
, 1);
136 nir_intrinsic_set_component(intr
, 3 - nir_intrinsic_component(intr
));
137 out_of_bounds
= component
== 3 && primitive_mode
== GL_TRIANGLES
;
144 if (nir_intrinsic_infos
[intr
->intrinsic
].has_dest
) {
145 b
->cursor
= nir_before_instr(&intr
->instr
);
146 nir_ssa_def
*undef
= nir_ssa_undef(b
, 1, 32);
147 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(undef
));
149 nir_instr_remove(&intr
->instr
);
156 remap_patch_urb_offsets(nir_block
*block
, nir_builder
*b
,
157 const struct brw_vue_map
*vue_map
,
158 GLenum tes_primitive_mode
)
160 const bool is_passthrough_tcs
= b
->shader
->info
.name
&&
161 strcmp(b
->shader
->info
.name
, "passthrough") == 0;
163 nir_foreach_instr_safe(instr
, block
) {
164 if (instr
->type
!= nir_instr_type_intrinsic
)
167 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
169 gl_shader_stage stage
= b
->shader
->info
.stage
;
171 if ((stage
== MESA_SHADER_TESS_CTRL
&& is_output(intrin
)) ||
172 (stage
== MESA_SHADER_TESS_EVAL
&& is_input(intrin
))) {
174 if (!is_passthrough_tcs
&&
175 remap_tess_levels(b
, intrin
, tes_primitive_mode
))
178 int vue_slot
= vue_map
->varying_to_slot
[intrin
->const_index
[0]];
179 assert(vue_slot
!= -1);
180 intrin
->const_index
[0] = vue_slot
;
182 nir_src
*vertex
= nir_get_io_vertex_index_src(intrin
);
184 if (nir_src_is_const(*vertex
)) {
185 intrin
->const_index
[0] += nir_src_as_uint(*vertex
) *
186 vue_map
->num_per_vertex_slots
;
188 b
->cursor
= nir_before_instr(&intrin
->instr
);
190 /* Multiply by the number of per-vertex slots. */
191 nir_ssa_def
*vertex_offset
=
193 nir_ssa_for_src(b
, *vertex
, 1),
195 vue_map
->num_per_vertex_slots
));
197 /* Add it to the existing offset */
198 nir_src
*offset
= nir_get_io_offset_src(intrin
);
199 nir_ssa_def
*total_offset
=
200 nir_iadd(b
, vertex_offset
,
201 nir_ssa_for_src(b
, *offset
, 1));
203 nir_instr_rewrite_src(&intrin
->instr
, offset
,
204 nir_src_for_ssa(total_offset
));
213 brw_nir_lower_vs_inputs(nir_shader
*nir
,
214 const uint8_t *vs_attrib_wa_flags
)
216 /* Start with the location of the variable's base. */
217 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
218 var
->data
.driver_location
= var
->data
.location
;
221 /* Now use nir_lower_io to walk dereference chains. Attribute arrays are
222 * loaded as one vec4 or dvec4 per element (or matrix column), depending on
223 * whether it is a double-precision type or not.
225 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
227 /* This pass needs actual constants */
228 nir_opt_constant_folding(nir
);
230 add_const_offset_to_base(nir
, nir_var_shader_in
);
232 brw_nir_apply_attribute_workarounds(nir
, vs_attrib_wa_flags
);
234 /* The last step is to remap VERT_ATTRIB_* to actual registers */
236 /* Whether or not we have any system generated values. gl_DrawID is not
237 * included here as it lives in its own vec4.
239 const bool has_sgvs
=
240 nir
->info
.system_values_read
&
241 (BITFIELD64_BIT(SYSTEM_VALUE_FIRST_VERTEX
) |
242 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
243 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
244 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
));
246 const unsigned num_inputs
= util_bitcount64(nir
->info
.inputs_read
);
248 nir_foreach_function(function
, nir
) {
253 nir_builder_init(&b
, function
->impl
);
255 nir_foreach_block(block
, function
->impl
) {
256 nir_foreach_instr_safe(instr
, block
) {
257 if (instr
->type
!= nir_instr_type_intrinsic
)
260 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
262 switch (intrin
->intrinsic
) {
263 case nir_intrinsic_load_first_vertex
:
264 case nir_intrinsic_load_base_instance
:
265 case nir_intrinsic_load_vertex_id_zero_base
:
266 case nir_intrinsic_load_instance_id
:
267 case nir_intrinsic_load_is_indexed_draw
:
268 case nir_intrinsic_load_draw_id
: {
269 b
.cursor
= nir_after_instr(&intrin
->instr
);
271 /* gl_VertexID and friends are stored by the VF as the last
272 * vertex element. We convert them to load_input intrinsics at
273 * the right location.
275 nir_intrinsic_instr
*load
=
276 nir_intrinsic_instr_create(nir
, nir_intrinsic_load_input
);
277 load
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
279 nir_intrinsic_set_base(load
, num_inputs
);
280 switch (intrin
->intrinsic
) {
281 case nir_intrinsic_load_first_vertex
:
282 nir_intrinsic_set_component(load
, 0);
284 case nir_intrinsic_load_base_instance
:
285 nir_intrinsic_set_component(load
, 1);
287 case nir_intrinsic_load_vertex_id_zero_base
:
288 nir_intrinsic_set_component(load
, 2);
290 case nir_intrinsic_load_instance_id
:
291 nir_intrinsic_set_component(load
, 3);
293 case nir_intrinsic_load_draw_id
:
294 case nir_intrinsic_load_is_indexed_draw
:
295 /* gl_DrawID and IsIndexedDraw are stored right after
296 * gl_VertexID and friends if any of them exist.
298 nir_intrinsic_set_base(load
, num_inputs
+ has_sgvs
);
299 if (intrin
->intrinsic
== nir_intrinsic_load_draw_id
)
300 nir_intrinsic_set_component(load
, 0);
302 nir_intrinsic_set_component(load
, 1);
305 unreachable("Invalid system value intrinsic");
308 load
->num_components
= 1;
309 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 1, 32, NULL
);
310 nir_builder_instr_insert(&b
, &load
->instr
);
312 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
313 nir_src_for_ssa(&load
->dest
.ssa
));
314 nir_instr_remove(&intrin
->instr
);
318 case nir_intrinsic_load_input
: {
319 /* Attributes come in a contiguous block, ordered by their
320 * gl_vert_attrib value. That means we can compute the slot
321 * number for an attribute by masking out the enabled attributes
322 * before it and counting the bits.
324 int attr
= nir_intrinsic_base(intrin
);
325 int slot
= util_bitcount64(nir
->info
.inputs_read
&
326 BITFIELD64_MASK(attr
));
327 nir_intrinsic_set_base(intrin
, slot
);
332 break; /* Nothing to do */
340 brw_nir_lower_vue_inputs(nir_shader
*nir
,
341 const struct brw_vue_map
*vue_map
)
343 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
344 var
->data
.driver_location
= var
->data
.location
;
347 /* Inputs are stored in vec4 slots, so use type_size_vec4(). */
348 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
350 /* This pass needs actual constants */
351 nir_opt_constant_folding(nir
);
353 add_const_offset_to_base(nir
, nir_var_shader_in
);
355 nir_foreach_function(function
, nir
) {
359 nir_foreach_block(block
, function
->impl
) {
360 nir_foreach_instr(instr
, block
) {
361 if (instr
->type
!= nir_instr_type_intrinsic
)
364 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
366 if (intrin
->intrinsic
== nir_intrinsic_load_input
||
367 intrin
->intrinsic
== nir_intrinsic_load_per_vertex_input
) {
368 /* Offset 0 is the VUE header, which contains
369 * VARYING_SLOT_LAYER [.y], VARYING_SLOT_VIEWPORT [.z], and
370 * VARYING_SLOT_PSIZ [.w].
372 int varying
= nir_intrinsic_base(intrin
);
375 case VARYING_SLOT_PSIZ
:
376 nir_intrinsic_set_base(intrin
, 0);
377 nir_intrinsic_set_component(intrin
, 3);
381 vue_slot
= vue_map
->varying_to_slot
[varying
];
382 assert(vue_slot
!= -1);
383 nir_intrinsic_set_base(intrin
, vue_slot
);
393 brw_nir_lower_tes_inputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
)
395 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
396 var
->data
.driver_location
= var
->data
.location
;
399 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, 0);
401 /* This pass needs actual constants */
402 nir_opt_constant_folding(nir
);
404 add_const_offset_to_base(nir
, nir_var_shader_in
);
406 nir_foreach_function(function
, nir
) {
407 if (function
->impl
) {
409 nir_builder_init(&b
, function
->impl
);
410 nir_foreach_block(block
, function
->impl
) {
411 remap_patch_urb_offsets(block
, &b
, vue_map
,
412 nir
->info
.tess
.primitive_mode
);
419 brw_nir_lower_fs_inputs(nir_shader
*nir
,
420 const struct gen_device_info
*devinfo
,
421 const struct brw_wm_prog_key
*key
)
423 foreach_list_typed(nir_variable
, var
, node
, &nir
->inputs
) {
424 var
->data
.driver_location
= var
->data
.location
;
426 /* Apply default interpolation mode.
428 * Everything defaults to smooth except for the legacy GL color
429 * built-in variables, which might be flat depending on API state.
431 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
432 const bool flat
= key
->flat_shade
&&
433 (var
->data
.location
== VARYING_SLOT_COL0
||
434 var
->data
.location
== VARYING_SLOT_COL1
);
436 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
437 : INTERP_MODE_SMOOTH
;
440 /* On Ironlake and below, there is only one interpolation mode.
441 * Centroid interpolation doesn't mean anything on this hardware --
442 * there is no multisampling.
444 if (devinfo
->gen
< 6) {
445 var
->data
.centroid
= false;
446 var
->data
.sample
= false;
450 nir_lower_io_options lower_io_options
= 0;
451 if (key
->persample_interp
)
452 lower_io_options
|= nir_lower_io_force_sample_interpolation
;
454 nir_lower_io(nir
, nir_var_shader_in
, type_size_vec4
, lower_io_options
);
455 if (devinfo
->gen
>= 11)
456 nir_lower_interpolation(nir
, ~0);
458 /* This pass needs actual constants */
459 nir_opt_constant_folding(nir
);
461 add_const_offset_to_base(nir
, nir_var_shader_in
);
465 brw_nir_lower_vue_outputs(nir_shader
*nir
)
467 nir_foreach_variable(var
, &nir
->outputs
) {
468 var
->data
.driver_location
= var
->data
.location
;
471 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
475 brw_nir_lower_tcs_outputs(nir_shader
*nir
, const struct brw_vue_map
*vue_map
,
476 GLenum tes_primitive_mode
)
478 nir_foreach_variable(var
, &nir
->outputs
) {
479 var
->data
.driver_location
= var
->data
.location
;
482 nir_lower_io(nir
, nir_var_shader_out
, type_size_vec4
, 0);
484 /* This pass needs actual constants */
485 nir_opt_constant_folding(nir
);
487 add_const_offset_to_base(nir
, nir_var_shader_out
);
489 nir_foreach_function(function
, nir
) {
490 if (function
->impl
) {
492 nir_builder_init(&b
, function
->impl
);
493 nir_foreach_block(block
, function
->impl
) {
494 remap_patch_urb_offsets(block
, &b
, vue_map
, tes_primitive_mode
);
501 brw_nir_lower_fs_outputs(nir_shader
*nir
)
503 nir_foreach_variable(var
, &nir
->outputs
) {
504 var
->data
.driver_location
=
505 SET_FIELD(var
->data
.index
, BRW_NIR_FRAG_OUTPUT_INDEX
) |
506 SET_FIELD(var
->data
.location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
509 nir_lower_io(nir
, nir_var_shader_out
, type_size_dvec4
, 0);
512 #define OPT(pass, ...) ({ \
513 bool this_progress = false; \
514 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
520 static nir_variable_mode
521 brw_nir_no_indirect_mask(const struct brw_compiler
*compiler
,
522 gl_shader_stage stage
)
524 nir_variable_mode indirect_mask
= 0;
526 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectInput
)
527 indirect_mask
|= nir_var_shader_in
;
528 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectOutput
)
529 indirect_mask
|= nir_var_shader_out
;
530 if (compiler
->glsl_compiler_options
[stage
].EmitNoIndirectTemp
)
531 indirect_mask
|= nir_var_function_temp
;
533 return indirect_mask
;
537 brw_nir_optimize(nir_shader
*nir
, const struct brw_compiler
*compiler
,
538 bool is_scalar
, bool allow_copies
)
540 nir_variable_mode indirect_mask
=
541 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
544 unsigned lower_flrp
=
545 (nir
->options
->lower_flrp16
? 16 : 0) |
546 (nir
->options
->lower_flrp32
? 32 : 0) |
547 (nir
->options
->lower_flrp64
? 64 : 0);
551 OPT(nir_split_array_vars
, nir_var_function_temp
);
552 OPT(nir_shrink_vec_array_vars
, nir_var_function_temp
);
554 OPT(nir_lower_vars_to_ssa
);
556 /* Only run this pass in the first call to brw_nir_optimize. Later
557 * calls assume that we've lowered away any copy_deref instructions
558 * and we don't want to introduce any more.
560 OPT(nir_opt_find_array_copies
);
562 OPT(nir_opt_copy_prop_vars
);
563 OPT(nir_opt_dead_write_vars
);
564 OPT(nir_opt_combine_stores
, nir_var_all
);
567 OPT(nir_lower_alu_to_scalar
, NULL
);
573 OPT(nir_lower_phis_to_scalar
);
579 OPT(nir_opt_combine_stores
, nir_var_all
);
581 /* Passing 0 to the peephole select pass causes it to convert
582 * if-statements that contain only move instructions in the branches
583 * regardless of the count.
585 * Passing 1 to the peephole select pass causes it to convert
586 * if-statements that contain at most a single ALU instruction (total)
587 * in both branches. Before Gen6, some math instructions were
588 * prohibitively expensive and the results of compare operations need an
589 * extra resolve step. For these reasons, this pass is more harmful
590 * than good on those platforms.
592 * For indirect loads of uniforms (push constants), we assume that array
593 * indices will nearly always be in bounds and the cost of the load is
594 * low. Therefore there shouldn't be a performance benefit to avoid it.
595 * However, in vec4 tessellation shaders, these loads operate by
596 * actually pulling from memory.
598 const bool is_vec4_tessellation
= !is_scalar
&&
599 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
600 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
601 OPT(nir_opt_peephole_select
, 0, !is_vec4_tessellation
, false);
602 OPT(nir_opt_peephole_select
, 1, !is_vec4_tessellation
,
603 compiler
->devinfo
->gen
>= 6);
605 OPT(nir_opt_intrinsics
);
606 OPT(nir_opt_idiv_const
, 32);
607 OPT(nir_opt_algebraic
);
608 OPT(nir_opt_constant_folding
);
610 if (lower_flrp
!= 0) {
611 /* To match the old behavior, set always_precise only for scalar
614 if (OPT(nir_lower_flrp
,
616 false /* always_precise */,
617 compiler
->devinfo
->gen
>= 6)) {
618 OPT(nir_opt_constant_folding
);
621 /* Nothing should rematerialize any flrps, so we only need to do this
627 OPT(nir_opt_dead_cf
);
628 if (OPT(nir_opt_trivial_continues
)) {
629 /* If nir_opt_trivial_continues makes progress, then we need to clean
630 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
636 OPT(nir_opt_if
, false);
637 if (nir
->options
->max_unroll_iterations
!= 0) {
638 OPT(nir_opt_loop_unroll
, indirect_mask
);
640 OPT(nir_opt_remove_phis
);
645 /* Workaround Gfxbench unused local sampler variable which will trigger an
646 * assert in the opt_large_constants pass.
648 OPT(nir_remove_dead_variables
, nir_var_function_temp
);
652 lower_bit_size_callback(const nir_alu_instr
*alu
, UNUSED
void *data
)
654 assert(alu
->dest
.dest
.is_ssa
);
655 if (alu
->dest
.dest
.ssa
.bit_size
>= 32)
658 const struct brw_compiler
*compiler
= (const struct brw_compiler
*) data
;
669 case nir_op_fround_even
:
680 return compiler
->devinfo
->gen
< 9 ? 32 : 0;
686 /* Does some simple lowering and runs the standard suite of optimizations
688 * This is intended to be called more-or-less directly after you get the
689 * shader out of GLSL or some other source. While it is geared towards i965,
690 * it is not at all generator-specific except for the is_scalar flag. Even
691 * there, it is safe to call with is_scalar = false for a shader that is
692 * intended for the FS backend as long as nir_optimize is called again with
693 * is_scalar = true to scalarize everything prior to code gen.
696 brw_preprocess_nir(const struct brw_compiler
*compiler
, nir_shader
*nir
,
697 const nir_shader
*softfp64
)
699 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
700 UNUSED
bool progress
; /* Written by OPT */
702 const bool is_scalar
= compiler
->scalar_stage
[nir
->info
.stage
];
705 OPT(nir_lower_alu_to_scalar
, NULL
);
708 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
709 OPT(nir_lower_gs_intrinsics
);
711 /* See also brw_nir_trig_workarounds.py */
712 if (compiler
->precise_trig
&&
713 !(devinfo
->gen
>= 10 || devinfo
->is_kabylake
))
714 OPT(brw_nir_apply_trig_workarounds
);
716 static const nir_lower_tex_options tex_options
= {
718 .lower_txf_offset
= true,
719 .lower_rect_offset
= true,
720 .lower_tex_without_implicit_lod
= true,
721 .lower_txd_cube_map
= true,
722 .lower_txb_shadow_clamp
= true,
723 .lower_txd_shadow_clamp
= true,
724 .lower_txd_offset_clamp
= true,
725 .lower_tg4_offsets
= true,
728 OPT(nir_lower_tex
, &tex_options
);
729 OPT(nir_normalize_cubemap_coords
);
731 OPT(nir_lower_global_vars_to_local
);
733 OPT(nir_split_var_copies
);
734 OPT(nir_split_struct_vars
, nir_var_function_temp
);
736 brw_nir_optimize(nir
, compiler
, is_scalar
, true);
738 bool lowered_64bit_ops
= false;
742 OPT(nir_lower_int64
, nir
->options
->lower_int64_options
);
743 OPT(nir_lower_doubles
, softfp64
, nir
->options
->lower_doubles_options
);
745 /* Necessary to lower add -> sub and div -> mul/rcp */
746 OPT(nir_opt_algebraic
);
748 lowered_64bit_ops
|= progress
;
751 /* This needs to be run after the first optimization pass but before we
752 * lower indirect derefs away
754 if (compiler
->supports_shader_constants
) {
755 OPT(nir_opt_large_constants
, NULL
, 32);
758 OPT(nir_lower_bit_size
, lower_bit_size_callback
, (void *)compiler
);
761 OPT(nir_lower_load_const_to_scalar
);
764 /* Lower a bunch of stuff */
765 OPT(nir_lower_var_copies
);
767 OPT(nir_lower_system_values
);
769 const nir_lower_subgroups_options subgroups_options
= {
770 .subgroup_size
= BRW_SUBGROUP_SIZE
,
771 .ballot_bit_size
= 32,
772 .lower_to_scalar
= true,
773 .lower_subgroup_masks
= true,
774 .lower_vote_trivial
= !is_scalar
,
775 .lower_shuffle
= true,
777 OPT(nir_lower_subgroups
, &subgroups_options
);
779 OPT(nir_lower_clip_cull_distance_arrays
);
781 nir_variable_mode indirect_mask
=
782 brw_nir_no_indirect_mask(compiler
, nir
->info
.stage
);
783 OPT(nir_lower_indirect_derefs
, indirect_mask
);
785 /* Lower array derefs of vectors for SSBO and UBO loads. For both UBOs and
786 * SSBOs, our back-end is capable of loading an entire vec4 at a time and
787 * we would like to take advantage of that whenever possible regardless of
788 * whether or not the app gives us full loads. This should allow the
789 * optimizer to combine UBO and SSBO load operations and save us some send
792 OPT(nir_lower_array_deref_of_vec
,
793 nir_var_mem_ubo
| nir_var_mem_ssbo
,
794 nir_lower_direct_array_deref_of_vec_load
);
796 /* Get rid of split copies */
797 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
801 brw_nir_link_shaders(const struct brw_compiler
*compiler
,
802 nir_shader
*producer
, nir_shader
*consumer
)
804 nir_lower_io_arrays_to_elements(producer
, consumer
);
805 nir_validate_shader(producer
, "after nir_lower_io_arrays_to_elements");
806 nir_validate_shader(consumer
, "after nir_lower_io_arrays_to_elements");
808 const bool p_is_scalar
= compiler
->scalar_stage
[producer
->info
.stage
];
809 const bool c_is_scalar
= compiler
->scalar_stage
[consumer
->info
.stage
];
811 if (p_is_scalar
&& c_is_scalar
) {
812 NIR_PASS_V(producer
, nir_lower_io_to_scalar_early
, nir_var_shader_out
);
813 NIR_PASS_V(consumer
, nir_lower_io_to_scalar_early
, nir_var_shader_in
);
814 brw_nir_optimize(producer
, compiler
, p_is_scalar
, false);
815 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
818 if (nir_link_opt_varyings(producer
, consumer
))
819 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
821 NIR_PASS_V(producer
, nir_remove_dead_variables
, nir_var_shader_out
);
822 NIR_PASS_V(consumer
, nir_remove_dead_variables
, nir_var_shader_in
);
824 if (nir_remove_unused_varyings(producer
, consumer
)) {
825 NIR_PASS_V(producer
, nir_lower_global_vars_to_local
);
826 NIR_PASS_V(consumer
, nir_lower_global_vars_to_local
);
828 /* The backend might not be able to handle indirects on
829 * temporaries so we need to lower indirects on any of the
830 * varyings we have demoted here.
832 NIR_PASS_V(producer
, nir_lower_indirect_derefs
,
833 brw_nir_no_indirect_mask(compiler
, producer
->info
.stage
));
834 NIR_PASS_V(consumer
, nir_lower_indirect_derefs
,
835 brw_nir_no_indirect_mask(compiler
, consumer
->info
.stage
));
837 brw_nir_optimize(producer
, compiler
, p_is_scalar
, false);
838 brw_nir_optimize(consumer
, compiler
, c_is_scalar
, false);
841 NIR_PASS_V(producer
, nir_lower_io_to_vector
, nir_var_shader_out
);
842 NIR_PASS_V(producer
, nir_opt_combine_stores
, nir_var_shader_out
);
843 NIR_PASS_V(consumer
, nir_lower_io_to_vector
, nir_var_shader_in
);
845 if (producer
->info
.stage
!= MESA_SHADER_TESS_CTRL
) {
846 /* Calling lower_io_to_vector creates output variable writes with
847 * write-masks. On non-TCS outputs, the back-end can't handle it and we
848 * need to call nir_lower_io_to_temporaries to get rid of them. This,
849 * in turn, creates temporary variables and extra copy_deref intrinsics
850 * that we need to clean up.
852 NIR_PASS_V(producer
, nir_lower_io_to_temporaries
,
853 nir_shader_get_entrypoint(producer
), true, false);
854 NIR_PASS_V(producer
, nir_lower_global_vars_to_local
);
855 NIR_PASS_V(producer
, nir_split_var_copies
);
856 NIR_PASS_V(producer
, nir_lower_var_copies
);
860 /* Prepare the given shader for codegen
862 * This function is intended to be called right before going into the actual
863 * backend and is highly backend-specific. Also, once this function has been
864 * called on a shader, it will no longer be in SSA form so most optimizations
868 brw_postprocess_nir(nir_shader
*nir
, const struct brw_compiler
*compiler
,
871 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
873 (INTEL_DEBUG
& intel_debug_flag_for_shader_stage(nir
->info
.stage
));
875 UNUSED
bool progress
; /* Written by OPT */
877 OPT(brw_nir_lower_mem_access_bit_sizes
);
878 OPT(nir_lower_int64
, nir
->options
->lower_int64_options
);
882 OPT(nir_opt_algebraic_before_ffma
);
885 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
887 if (devinfo
->gen
>= 6) {
888 /* Try and fuse multiply-adds */
889 OPT(brw_nir_opt_peephole_ffma
);
892 if (OPT(nir_opt_comparison_pre
)) {
897 /* Do the select peepehole again. nir_opt_comparison_pre (combined with
898 * the other optimization passes) will have removed at least one
899 * instruction from one of the branches of the if-statement, so now it
900 * might be under the threshold of conversion to bcsel.
902 * See brw_nir_optimize for the explanation of is_vec4_tessellation.
904 const bool is_vec4_tessellation
= !is_scalar
&&
905 (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
906 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
);
907 OPT(nir_opt_peephole_select
, 0, is_vec4_tessellation
, false);
908 OPT(nir_opt_peephole_select
, 1, is_vec4_tessellation
,
909 compiler
->devinfo
->gen
>= 6);
914 if (OPT(nir_opt_algebraic_late
)) {
915 /* At this late stage, anything that makes more constants will wreak
916 * havok on the vec4 backend. The handling of constants in the vec4
917 * backend is not good.
920 OPT(nir_opt_constant_folding
);
929 OPT(brw_nir_lower_conversions
);
932 OPT(nir_lower_alu_to_scalar
, NULL
);
933 OPT(nir_lower_to_source_mods
, nir_lower_all_source_mods
);
936 OPT(nir_opt_move_comparisons
);
938 OPT(nir_lower_bool_to_int32
);
940 OPT(nir_lower_locals_to_regs
);
942 if (unlikely(debug_enabled
)) {
943 /* Re-index SSA defs so we print more sensible numbers. */
944 nir_foreach_function(function
, nir
) {
946 nir_index_ssa_defs(function
->impl
);
949 fprintf(stderr
, "NIR (SSA form) for %s shader:\n",
950 _mesa_shader_stage_to_string(nir
->info
.stage
));
951 nir_print_shader(nir
, stderr
);
954 OPT(nir_convert_from_ssa
, true);
957 OPT(nir_move_vec_src_uses_to_dest
);
958 OPT(nir_lower_vec_to_movs
);
963 if (OPT(nir_opt_rematerialize_compares
))
966 /* This is the last pass we run before we start emitting stuff. It
967 * determines when we need to insert boolean resolves on Gen <= 5. We
968 * run it last because it stashes data in instr->pass_flags and we don't
969 * want that to be squashed by other NIR passes.
971 if (devinfo
->gen
<= 5)
972 brw_nir_analyze_boolean_resolves(nir
);
976 if (unlikely(debug_enabled
)) {
977 fprintf(stderr
, "NIR (final form) for %s shader:\n",
978 _mesa_shader_stage_to_string(nir
->info
.stage
));
979 nir_print_shader(nir
, stderr
);
984 brw_nir_apply_sampler_key(nir_shader
*nir
,
985 const struct brw_compiler
*compiler
,
986 const struct brw_sampler_prog_key_data
*key_tex
,
989 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
990 nir_lower_tex_options tex_options
= {
991 .lower_txd_clamp_bindless_sampler
= true,
992 .lower_txd_clamp_if_sampler_index_not_lt_16
= true,
995 /* Iron Lake and prior require lowering of all rectangle textures */
996 if (devinfo
->gen
< 6)
997 tex_options
.lower_rect
= true;
999 /* Prior to Broadwell, our hardware can't actually do GL_CLAMP */
1000 if (devinfo
->gen
< 8) {
1001 tex_options
.saturate_s
= key_tex
->gl_clamp_mask
[0];
1002 tex_options
.saturate_t
= key_tex
->gl_clamp_mask
[1];
1003 tex_options
.saturate_r
= key_tex
->gl_clamp_mask
[2];
1006 /* Prior to Haswell, we have to fake texture swizzle */
1007 for (unsigned s
= 0; s
< MAX_SAMPLERS
; s
++) {
1008 if (key_tex
->swizzles
[s
] == SWIZZLE_NOOP
)
1011 tex_options
.swizzle_result
|= (1 << s
);
1012 for (unsigned c
= 0; c
< 4; c
++)
1013 tex_options
.swizzles
[s
][c
] = GET_SWZ(key_tex
->swizzles
[s
], c
);
1016 /* Prior to Haswell, we have to lower gradients on shadow samplers */
1017 tex_options
.lower_txd_shadow
= devinfo
->gen
< 8 && !devinfo
->is_haswell
;
1019 tex_options
.lower_y_uv_external
= key_tex
->y_uv_image_mask
;
1020 tex_options
.lower_y_u_v_external
= key_tex
->y_u_v_image_mask
;
1021 tex_options
.lower_yx_xuxv_external
= key_tex
->yx_xuxv_image_mask
;
1022 tex_options
.lower_xy_uxvx_external
= key_tex
->xy_uxvx_image_mask
;
1023 tex_options
.lower_ayuv_external
= key_tex
->ayuv_image_mask
;
1024 tex_options
.lower_xyuv_external
= key_tex
->xyuv_image_mask
;
1026 /* Setup array of scaling factors for each texture. */
1027 memcpy(&tex_options
.scale_factors
, &key_tex
->scale_factors
,
1028 sizeof(tex_options
.scale_factors
));
1030 if (nir_lower_tex(nir
, &tex_options
)) {
1031 nir_validate_shader(nir
, "after nir_lower_tex");
1032 brw_nir_optimize(nir
, compiler
, is_scalar
, false);
1037 brw_type_for_nir_type(const struct gen_device_info
*devinfo
, nir_alu_type type
)
1041 case nir_type_uint32
:
1042 return BRW_REGISTER_TYPE_UD
;
1045 case nir_type_bool32
:
1046 case nir_type_int32
:
1047 return BRW_REGISTER_TYPE_D
;
1048 case nir_type_float
:
1049 case nir_type_float32
:
1050 return BRW_REGISTER_TYPE_F
;
1051 case nir_type_float16
:
1052 return BRW_REGISTER_TYPE_HF
;
1053 case nir_type_float64
:
1054 return BRW_REGISTER_TYPE_DF
;
1055 case nir_type_int64
:
1056 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_Q
;
1057 case nir_type_uint64
:
1058 return devinfo
->gen
< 8 ? BRW_REGISTER_TYPE_DF
: BRW_REGISTER_TYPE_UQ
;
1059 case nir_type_int16
:
1060 return BRW_REGISTER_TYPE_W
;
1061 case nir_type_uint16
:
1062 return BRW_REGISTER_TYPE_UW
;
1064 return BRW_REGISTER_TYPE_B
;
1065 case nir_type_uint8
:
1066 return BRW_REGISTER_TYPE_UB
;
1068 unreachable("unknown type");
1071 return BRW_REGISTER_TYPE_F
;
1074 /* Returns the glsl_base_type corresponding to a nir_alu_type.
1075 * This is used by both brw_vec4_nir and brw_fs_nir.
1078 brw_glsl_base_type_for_nir_type(nir_alu_type type
)
1081 case nir_type_float
:
1082 case nir_type_float32
:
1083 return GLSL_TYPE_FLOAT
;
1085 case nir_type_float16
:
1086 return GLSL_TYPE_FLOAT16
;
1088 case nir_type_float64
:
1089 return GLSL_TYPE_DOUBLE
;
1092 case nir_type_int32
:
1093 return GLSL_TYPE_INT
;
1096 case nir_type_uint32
:
1097 return GLSL_TYPE_UINT
;
1099 case nir_type_int16
:
1100 return GLSL_TYPE_INT16
;
1102 case nir_type_uint16
:
1103 return GLSL_TYPE_UINT16
;
1106 unreachable("bad type");
1111 brw_nir_create_passthrough_tcs(void *mem_ctx
, const struct brw_compiler
*compiler
,
1112 const nir_shader_compiler_options
*options
,
1113 const struct brw_tcs_prog_key
*key
)
1116 nir_builder_init_simple_shader(&b
, mem_ctx
, MESA_SHADER_TESS_CTRL
,
1118 nir_shader
*nir
= b
.shader
;
1120 nir_intrinsic_instr
*load
;
1121 nir_intrinsic_instr
*store
;
1122 nir_ssa_def
*zero
= nir_imm_int(&b
, 0);
1123 nir_ssa_def
*invoc_id
= nir_load_invocation_id(&b
);
1125 nir
->info
.inputs_read
= key
->outputs_written
&
1126 ~(VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
);
1127 nir
->info
.outputs_written
= key
->outputs_written
;
1128 nir
->info
.tess
.tcs_vertices_out
= key
->input_vertices
;
1129 nir
->info
.name
= ralloc_strdup(nir
, "passthrough");
1130 nir
->num_uniforms
= 8 * sizeof(uint32_t);
1132 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_0");
1133 var
->data
.location
= 0;
1134 var
= nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "hdr_1");
1135 var
->data
.location
= 1;
1137 /* Write the patch URB header. */
1138 for (int i
= 0; i
<= 1; i
++) {
1139 load
= nir_intrinsic_instr_create(nir
, nir_intrinsic_load_uniform
);
1140 load
->num_components
= 4;
1141 load
->src
[0] = nir_src_for_ssa(zero
);
1142 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1143 nir_intrinsic_set_base(load
, i
* 4 * sizeof(uint32_t));
1144 nir_builder_instr_insert(&b
, &load
->instr
);
1146 store
= nir_intrinsic_instr_create(nir
, nir_intrinsic_store_output
);
1147 store
->num_components
= 4;
1148 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1149 store
->src
[1] = nir_src_for_ssa(zero
);
1150 nir_intrinsic_set_base(store
, VARYING_SLOT_TESS_LEVEL_INNER
- i
);
1151 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1152 nir_builder_instr_insert(&b
, &store
->instr
);
1155 /* Copy inputs to outputs. */
1156 uint64_t varyings
= nir
->info
.inputs_read
;
1158 while (varyings
!= 0) {
1159 const int varying
= ffsll(varyings
) - 1;
1161 load
= nir_intrinsic_instr_create(nir
,
1162 nir_intrinsic_load_per_vertex_input
);
1163 load
->num_components
= 4;
1164 load
->src
[0] = nir_src_for_ssa(invoc_id
);
1165 load
->src
[1] = nir_src_for_ssa(zero
);
1166 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
1167 nir_intrinsic_set_base(load
, varying
);
1168 nir_builder_instr_insert(&b
, &load
->instr
);
1170 store
= nir_intrinsic_instr_create(nir
,
1171 nir_intrinsic_store_per_vertex_output
);
1172 store
->num_components
= 4;
1173 store
->src
[0] = nir_src_for_ssa(&load
->dest
.ssa
);
1174 store
->src
[1] = nir_src_for_ssa(invoc_id
);
1175 store
->src
[2] = nir_src_for_ssa(zero
);
1176 nir_intrinsic_set_base(store
, varying
);
1177 nir_intrinsic_set_write_mask(store
, WRITEMASK_XYZW
);
1178 nir_builder_instr_insert(&b
, &store
->instr
);
1180 varyings
&= ~BITFIELD64_BIT(varying
);
1183 nir_validate_shader(nir
, "in brw_nir_create_passthrough_tcs");
1185 brw_preprocess_nir(compiler
, nir
, NULL
);