src/intel/compiler/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_cfg.h"
  25 #include "brw_eu.h"
  26 #include "brw_fs.h"
  27 #include "brw_nir.h"
  28 #include "brw_vec4_tes.h"
  29 #include "dev/gen_debug.h"
  30 #include "main/uniforms.h"
  31 #include "util/macros.h"
  32
  33 enum brw_reg_type
  34 brw_type_for_base_type(const struct glsl_type *type)
  35 {
  36    switch (type->base_type) {
  37    case GLSL_TYPE_FLOAT16:
  38       return BRW_REGISTER_TYPE_HF;
  39    case GLSL_TYPE_FLOAT:
  40       return BRW_REGISTER_TYPE_F;
  41    case GLSL_TYPE_INT:
  42    case GLSL_TYPE_BOOL:
  43    case GLSL_TYPE_SUBROUTINE:
  44       return BRW_REGISTER_TYPE_D;
  45    case GLSL_TYPE_INT16:
  46       return BRW_REGISTER_TYPE_W;
  47    case GLSL_TYPE_INT8:
  48       return BRW_REGISTER_TYPE_B;
  49    case GLSL_TYPE_UINT:
  50       return BRW_REGISTER_TYPE_UD;
  51    case GLSL_TYPE_UINT16:
  52       return BRW_REGISTER_TYPE_UW;
  53    case GLSL_TYPE_UINT8:
  54       return BRW_REGISTER_TYPE_UB;
  55    case GLSL_TYPE_ARRAY:
  56       return brw_type_for_base_type(type->fields.array);
  57    case GLSL_TYPE_STRUCT:
  58    case GLSL_TYPE_INTERFACE:
  59    case GLSL_TYPE_SAMPLER:
  60    case GLSL_TYPE_ATOMIC_UINT:
  61       /* These should be overridden with the type of the member when
  62        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  63        * way to trip up if we don't.
  64        */
  65       return BRW_REGISTER_TYPE_UD;
  66    case GLSL_TYPE_IMAGE:
  67       return BRW_REGISTER_TYPE_UD;
  68    case GLSL_TYPE_DOUBLE:
  69       return BRW_REGISTER_TYPE_DF;
  70    case GLSL_TYPE_UINT64:
  71       return BRW_REGISTER_TYPE_UQ;
  72    case GLSL_TYPE_INT64:
  73       return BRW_REGISTER_TYPE_Q;
  74    case GLSL_TYPE_VOID:
  75    case GLSL_TYPE_ERROR:
  76    case GLSL_TYPE_FUNCTION:
  77       unreachable("not reached");
  78    }
  79
  80    return BRW_REGISTER_TYPE_F;
  81 }
  82
  83 enum brw_conditional_mod
  84 brw_conditional_for_comparison(unsigned int op)
  85 {
  86    switch (op) {
  87    case ir_binop_less:
  88       return BRW_CONDITIONAL_L;
  89    case ir_binop_gequal:
  90       return BRW_CONDITIONAL_GE;
  91    case ir_binop_equal:
  92    case ir_binop_all_equal: /* same as equal for scalars */
  93       return BRW_CONDITIONAL_Z;
  94    case ir_binop_nequal:
  95    case ir_binop_any_nequal: /* same as nequal for scalars */
  96       return BRW_CONDITIONAL_NZ;
  97    default:
  98       unreachable("not reached: bad operation for comparison");
  99    }
 100 }
 101
 102 uint32_t
 103 brw_math_function(enum opcode op)
 104 {
 105    switch (op) {
 106    case SHADER_OPCODE_RCP:
 107       return BRW_MATH_FUNCTION_INV;
 108    case SHADER_OPCODE_RSQ:
 109       return BRW_MATH_FUNCTION_RSQ;
 110    case SHADER_OPCODE_SQRT:
 111       return BRW_MATH_FUNCTION_SQRT;
 112    case SHADER_OPCODE_EXP2:
 113       return BRW_MATH_FUNCTION_EXP;
 114    case SHADER_OPCODE_LOG2:
 115       return BRW_MATH_FUNCTION_LOG;
 116    case SHADER_OPCODE_POW:
 117       return BRW_MATH_FUNCTION_POW;
 118    case SHADER_OPCODE_SIN:
 119       return BRW_MATH_FUNCTION_SIN;
 120    case SHADER_OPCODE_COS:
 121       return BRW_MATH_FUNCTION_COS;
 122    case SHADER_OPCODE_INT_QUOTIENT:
 123       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 124    case SHADER_OPCODE_INT_REMAINDER:
 125       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 126    default:
 127       unreachable("not reached: unknown math function");
 128    }
 129 }
 130
 131 bool
 132 brw_texture_offset(const nir_tex_instr *tex, unsigned src,
 133                    uint32_t *offset_bits_out)
 134 {
 135    if (!nir_src_is_const(tex->src[src].src))
 136       return false;
 137
 138    const unsigned num_components = nir_tex_instr_src_size(tex, src);
 139
 140    /* Combine all three offsets into a single unsigned dword:
 141     *
 142     *    bits 11:8 - U Offset (X component)
 143     *    bits  7:4 - V Offset (Y component)
 144     *    bits  3:0 - R Offset (Z component)
 145     */
 146    uint32_t offset_bits = 0;
 147    for (unsigned i = 0; i < num_components; i++) {
 148       int offset = nir_src_comp_as_int(tex->src[src].src, i);
 149
 150       /* offset out of bounds; caller will handle it. */
 151       if (offset > 7 || offset < -8)
 152          return false;
 153
 154       const unsigned shift = 4 * (2 - i);
 155       offset_bits |= (offset << shift) & (0xF << shift);
 156    }
 157
 158    *offset_bits_out = offset_bits;
 159
 160    return true;
 161 }
 162
 163 const char *
 164 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 165 {
 166    switch (op) {
 167    case 0 ... NUM_BRW_OPCODES - 1:
 168       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 169        * start of a loop in the IR.
 170        */
 171       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 172          return "do";
 173
 174       /* The following conversion opcodes doesn't exist on Gen8+, but we use
 175        * then to mark that we want to do the conversion.
 176        */
 177       if (devinfo->gen > 7 && op == BRW_OPCODE_F32TO16)
 178          return "f32to16";
 179
 180       if (devinfo->gen > 7 && op == BRW_OPCODE_F16TO32)
 181          return "f16to32";
 182
 183       assert(brw_opcode_desc(devinfo, op)->name);
 184       return brw_opcode_desc(devinfo, op)->name;
 185    case FS_OPCODE_FB_WRITE:
 186       return "fb_write";
 187    case FS_OPCODE_FB_WRITE_LOGICAL:
 188       return "fb_write_logical";
 189    case FS_OPCODE_REP_FB_WRITE:
 190       return "rep_fb_write";
 191    case FS_OPCODE_FB_READ:
 192       return "fb_read";
 193    case FS_OPCODE_FB_READ_LOGICAL:
 194       return "fb_read_logical";
 195
 196    case SHADER_OPCODE_RCP:
 197       return "rcp";
 198    case SHADER_OPCODE_RSQ:
 199       return "rsq";
 200    case SHADER_OPCODE_SQRT:
 201       return "sqrt";
 202    case SHADER_OPCODE_EXP2:
 203       return "exp2";
 204    case SHADER_OPCODE_LOG2:
 205       return "log2";
 206    case SHADER_OPCODE_POW:
 207       return "pow";
 208    case SHADER_OPCODE_INT_QUOTIENT:
 209       return "int_quot";
 210    case SHADER_OPCODE_INT_REMAINDER:
 211       return "int_rem";
 212    case SHADER_OPCODE_SIN:
 213       return "sin";
 214    case SHADER_OPCODE_COS:
 215       return "cos";
 216
 217    case SHADER_OPCODE_SEND:
 218       return "send";
 219
 220    case SHADER_OPCODE_UNDEF:
 221       return "undef";
 222
 223    case SHADER_OPCODE_TEX:
 224       return "tex";
 225    case SHADER_OPCODE_TEX_LOGICAL:
 226       return "tex_logical";
 227    case SHADER_OPCODE_TXD:
 228       return "txd";
 229    case SHADER_OPCODE_TXD_LOGICAL:
 230       return "txd_logical";
 231    case SHADER_OPCODE_TXF:
 232       return "txf";
 233    case SHADER_OPCODE_TXF_LOGICAL:
 234       return "txf_logical";
 235    case SHADER_OPCODE_TXF_LZ:
 236       return "txf_lz";
 237    case SHADER_OPCODE_TXL:
 238       return "txl";
 239    case SHADER_OPCODE_TXL_LOGICAL:
 240       return "txl_logical";
 241    case SHADER_OPCODE_TXL_LZ:
 242       return "txl_lz";
 243    case SHADER_OPCODE_TXS:
 244       return "txs";
 245    case SHADER_OPCODE_TXS_LOGICAL:
 246       return "txs_logical";
 247    case FS_OPCODE_TXB:
 248       return "txb";
 249    case FS_OPCODE_TXB_LOGICAL:
 250       return "txb_logical";
 251    case SHADER_OPCODE_TXF_CMS:
 252       return "txf_cms";
 253    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 254       return "txf_cms_logical";
 255    case SHADER_OPCODE_TXF_CMS_W:
 256       return "txf_cms_w";
 257    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 258       return "txf_cms_w_logical";
 259    case SHADER_OPCODE_TXF_UMS:
 260       return "txf_ums";
 261    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 262       return "txf_ums_logical";
 263    case SHADER_OPCODE_TXF_MCS:
 264       return "txf_mcs";
 265    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 266       return "txf_mcs_logical";
 267    case SHADER_OPCODE_LOD:
 268       return "lod";
 269    case SHADER_OPCODE_LOD_LOGICAL:
 270       return "lod_logical";
 271    case SHADER_OPCODE_TG4:
 272       return "tg4";
 273    case SHADER_OPCODE_TG4_LOGICAL:
 274       return "tg4_logical";
 275    case SHADER_OPCODE_TG4_OFFSET:
 276       return "tg4_offset";
 277    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 278       return "tg4_offset_logical";
 279    case SHADER_OPCODE_SAMPLEINFO:
 280       return "sampleinfo";
 281    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 282       return "sampleinfo_logical";
 283
 284    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
 285       return "image_size_logical";
 286
 287    case SHADER_OPCODE_SHADER_TIME_ADD:
 288       return "shader_time_add";
 289
 290    case VEC4_OPCODE_UNTYPED_ATOMIC:
 291       return "untyped_atomic";
 292    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 293       return "untyped_atomic_logical";
 294    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 295       return "untyped_atomic_float_logical";
 296    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
 297       return "untyped_surface_read";
 298    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 299       return "untyped_surface_read_logical";
 300    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
 301       return "untyped_surface_write";
 302    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 303       return "untyped_surface_write_logical";
 304    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
 305       return "a64_untyped_read_logical";
 306    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
 307       return "a64_untyped_write_logical";
 308    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
 309       return "a64_byte_scattered_read_logical";
 310    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
 311       return "a64_byte_scattered_write_logical";
 312    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
 313       return "a64_untyped_atomic_logical";
 314    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
 315       return "a64_untyped_atomic_int64_logical";
 316    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
 317       return "a64_untyped_atomic_float_logical";
 318    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 319       return "typed_atomic_logical";
 320    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 321       return "typed_surface_read_logical";
 322    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 323       return "typed_surface_write_logical";
 324    case SHADER_OPCODE_MEMORY_FENCE:
 325       return "memory_fence";
 326    case FS_OPCODE_SCHEDULING_FENCE:
 327       return "scheduling_fence";
 328    case SHADER_OPCODE_INTERLOCK:
 329       /* For an interlock we actually issue a memory fence via sendc. */
 330       return "interlock";
 331
 332    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
 333       return "byte_scattered_read_logical";
 334    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
 335       return "byte_scattered_write_logical";
 336    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
 337       return "dword_scattered_read_logical";
 338    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
 339       return "dword_scattered_write_logical";
 340
 341    case SHADER_OPCODE_LOAD_PAYLOAD:
 342       return "load_payload";
 343    case FS_OPCODE_PACK:
 344       return "pack";
 345
 346    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 347       return "gen4_scratch_read";
 348    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 349       return "gen4_scratch_write";
 350    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 351       return "gen7_scratch_read";
 352    case SHADER_OPCODE_URB_WRITE_SIMD8:
 353       return "gen8_urb_write_simd8";
 354    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 355       return "gen8_urb_write_simd8_per_slot";
 356    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 357       return "gen8_urb_write_simd8_masked";
 358    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 359       return "gen8_urb_write_simd8_masked_per_slot";
 360    case SHADER_OPCODE_URB_READ_SIMD8:
 361       return "urb_read_simd8";
 362    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 363       return "urb_read_simd8_per_slot";
 364
 365    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 366       return "find_live_channel";
 367    case FS_OPCODE_LOAD_LIVE_CHANNELS:
 368       return "load_live_channels";
 369
 370    case SHADER_OPCODE_BROADCAST:
 371       return "broadcast";
 372    case SHADER_OPCODE_SHUFFLE:
 373       return "shuffle";
 374    case SHADER_OPCODE_SEL_EXEC:
 375       return "sel_exec";
 376    case SHADER_OPCODE_QUAD_SWIZZLE:
 377       return "quad_swizzle";
 378    case SHADER_OPCODE_CLUSTER_BROADCAST:
 379       return "cluster_broadcast";
 380
 381    case SHADER_OPCODE_GET_BUFFER_SIZE:
 382       return "get_buffer_size";
 383
 384    case VEC4_OPCODE_MOV_BYTES:
 385       return "mov_bytes";
 386    case VEC4_OPCODE_PACK_BYTES:
 387       return "pack_bytes";
 388    case VEC4_OPCODE_UNPACK_UNIFORM:
 389       return "unpack_uniform";
 390    case VEC4_OPCODE_DOUBLE_TO_F32:
 391       return "double_to_f32";
 392    case VEC4_OPCODE_DOUBLE_TO_D32:
 393       return "double_to_d32";
 394    case VEC4_OPCODE_DOUBLE_TO_U32:
 395       return "double_to_u32";
 396    case VEC4_OPCODE_TO_DOUBLE:
 397       return "single_to_double";
 398    case VEC4_OPCODE_PICK_LOW_32BIT:
 399       return "pick_low_32bit";
 400    case VEC4_OPCODE_PICK_HIGH_32BIT:
 401       return "pick_high_32bit";
 402    case VEC4_OPCODE_SET_LOW_32BIT:
 403       return "set_low_32bit";
 404    case VEC4_OPCODE_SET_HIGH_32BIT:
 405       return "set_high_32bit";
 406
 407    case FS_OPCODE_DDX_COARSE:
 408       return "ddx_coarse";
 409    case FS_OPCODE_DDX_FINE:
 410       return "ddx_fine";
 411    case FS_OPCODE_DDY_COARSE:
 412       return "ddy_coarse";
 413    case FS_OPCODE_DDY_FINE:
 414       return "ddy_fine";
 415
 416    case FS_OPCODE_LINTERP:
 417       return "linterp";
 418
 419    case FS_OPCODE_PIXEL_X:
 420       return "pixel_x";
 421    case FS_OPCODE_PIXEL_Y:
 422       return "pixel_y";
 423
 424    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 425       return "uniform_pull_const";
 426    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 427       return "uniform_pull_const_gen7";
 428    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 429       return "varying_pull_const_gen4";
 430    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 431       return "varying_pull_const_logical";
 432
 433    case FS_OPCODE_DISCARD_JUMP:
 434       return "discard_jump";
 435
 436    case FS_OPCODE_SET_SAMPLE_ID:
 437       return "set_sample_id";
 438
 439    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 440       return "pack_half_2x16_split";
 441
 442    case FS_OPCODE_PLACEHOLDER_HALT:
 443       return "placeholder_halt";
 444
 445    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 446       return "interp_sample";
 447    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 448       return "interp_shared_offset";
 449    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 450       return "interp_per_slot_offset";
 451
 452    case VS_OPCODE_URB_WRITE:
 453       return "vs_urb_write";
 454    case VS_OPCODE_PULL_CONSTANT_LOAD:
 455       return "pull_constant_load";
 456    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 457       return "pull_constant_load_gen7";
 458
 459    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 460       return "set_simd4x2_header_gen9";
 461
 462    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 463       return "unpack_flags_simd4x2";
 464
 465    case GS_OPCODE_URB_WRITE:
 466       return "gs_urb_write";
 467    case GS_OPCODE_URB_WRITE_ALLOCATE:
 468       return "gs_urb_write_allocate";
 469    case GS_OPCODE_THREAD_END:
 470       return "gs_thread_end";
 471    case GS_OPCODE_SET_WRITE_OFFSET:
 472       return "set_write_offset";
 473    case GS_OPCODE_SET_VERTEX_COUNT:
 474       return "set_vertex_count";
 475    case GS_OPCODE_SET_DWORD_2:
 476       return "set_dword_2";
 477    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 478       return "prepare_channel_masks";
 479    case GS_OPCODE_SET_CHANNEL_MASKS:
 480       return "set_channel_masks";
 481    case GS_OPCODE_GET_INSTANCE_ID:
 482       return "get_instance_id";
 483    case GS_OPCODE_FF_SYNC:
 484       return "ff_sync";
 485    case GS_OPCODE_SET_PRIMITIVE_ID:
 486       return "set_primitive_id";
 487    case GS_OPCODE_SVB_WRITE:
 488       return "gs_svb_write";
 489    case GS_OPCODE_SVB_SET_DST_INDEX:
 490       return "gs_svb_set_dst_index";
 491    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 492       return "gs_ff_sync_set_primitives";
 493    case CS_OPCODE_CS_TERMINATE:
 494       return "cs_terminate";
 495    case SHADER_OPCODE_BARRIER:
 496       return "barrier";
 497    case SHADER_OPCODE_MULH:
 498       return "mulh";
 499    case SHADER_OPCODE_ISUB_SAT:
 500       return "isub_sat";
 501    case SHADER_OPCODE_USUB_SAT:
 502       return "usub_sat";
 503    case SHADER_OPCODE_MOV_INDIRECT:
 504       return "mov_indirect";
 505    case SHADER_OPCODE_MOV_RELOC_IMM:
 506       return "mov_reloc_imm";
 507
 508    case VEC4_OPCODE_URB_READ:
 509       return "urb_read";
 510    case TCS_OPCODE_GET_INSTANCE_ID:
 511       return "tcs_get_instance_id";
 512    case TCS_OPCODE_URB_WRITE:
 513       return "tcs_urb_write";
 514    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 515       return "tcs_set_input_urb_offsets";
 516    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 517       return "tcs_set_output_urb_offsets";
 518    case TCS_OPCODE_GET_PRIMITIVE_ID:
 519       return "tcs_get_primitive_id";
 520    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 521       return "tcs_create_barrier_header";
 522    case TCS_OPCODE_SRC0_010_IS_ZERO:
 523       return "tcs_src0<0,1,0>_is_zero";
 524    case TCS_OPCODE_RELEASE_INPUT:
 525       return "tcs_release_input";
 526    case TCS_OPCODE_THREAD_END:
 527       return "tcs_thread_end";
 528    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 529       return "tes_create_input_read_header";
 530    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 531       return "tes_add_indirect_urb_offset";
 532    case TES_OPCODE_GET_PRIMITIVE_ID:
 533       return "tes_get_primitive_id";
 534
 535    case SHADER_OPCODE_RND_MODE:
 536       return "rnd_mode";
 537    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
 538       return "float_control_mode";
 539    }
 540
 541    unreachable("not reached");
 542 }
 543
 544 bool
 545 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 546 {
 547    union {
 548       unsigned ud;
 549       int d;
 550       float f;
 551       double df;
 552    } imm, sat_imm = { 0 };
 553
 554    const unsigned size = type_sz(type);
 555
 556    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 557     * irrelevant, so just check the size of the type and copy from/to an
 558     * appropriately sized field.
 559     */
 560    if (size < 8)
 561       imm.ud = reg->ud;
 562    else
 563       imm.df = reg->df;
 564
 565    switch (type) {
 566    case BRW_REGISTER_TYPE_UD:
 567    case BRW_REGISTER_TYPE_D:
 568    case BRW_REGISTER_TYPE_UW:
 569    case BRW_REGISTER_TYPE_W:
 570    case BRW_REGISTER_TYPE_UQ:
 571    case BRW_REGISTER_TYPE_Q:
 572       /* Nothing to do. */
 573       return false;
 574    case BRW_REGISTER_TYPE_F:
 575       sat_imm.f = SATURATE(imm.f);
 576       break;
 577    case BRW_REGISTER_TYPE_DF:
 578       sat_imm.df = SATURATE(imm.df);
 579       break;
 580    case BRW_REGISTER_TYPE_UB:
 581    case BRW_REGISTER_TYPE_B:
 582       unreachable("no UB/B immediates");
 583    case BRW_REGISTER_TYPE_V:
 584    case BRW_REGISTER_TYPE_UV:
 585    case BRW_REGISTER_TYPE_VF:
 586       unreachable("unimplemented: saturate vector immediate");
 587    case BRW_REGISTER_TYPE_HF:
 588       unreachable("unimplemented: saturate HF immediate");
 589    case BRW_REGISTER_TYPE_NF:
 590       unreachable("no NF immediates");
 591    }
 592
 593    if (size < 8) {
 594       if (imm.ud != sat_imm.ud) {
 595          reg->ud = sat_imm.ud;
 596          return true;
 597       }
 598    } else {
 599       if (imm.df != sat_imm.df) {
 600          reg->df = sat_imm.df;
 601          return true;
 602       }
 603    }
 604    return false;
 605 }
 606
 607 bool
 608 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 609 {
 610    switch (type) {
 611    case BRW_REGISTER_TYPE_D:
 612    case BRW_REGISTER_TYPE_UD:
 613       reg->d = -reg->d;
 614       return true;
 615    case BRW_REGISTER_TYPE_W:
 616    case BRW_REGISTER_TYPE_UW: {
 617       uint16_t value = -(int16_t)reg->ud;
 618       reg->ud = value | (uint32_t)value << 16;
 619       return true;
 620    }
 621    case BRW_REGISTER_TYPE_F:
 622       reg->f = -reg->f;
 623       return true;
 624    case BRW_REGISTER_TYPE_VF:
 625       reg->ud ^= 0x80808080;
 626       return true;
 627    case BRW_REGISTER_TYPE_DF:
 628       reg->df = -reg->df;
 629       return true;
 630    case BRW_REGISTER_TYPE_UQ:
 631    case BRW_REGISTER_TYPE_Q:
 632       reg->d64 = -reg->d64;
 633       return true;
 634    case BRW_REGISTER_TYPE_UB:
 635    case BRW_REGISTER_TYPE_B:
 636       unreachable("no UB/B immediates");
 637    case BRW_REGISTER_TYPE_UV:
 638    case BRW_REGISTER_TYPE_V:
 639       assert(!"unimplemented: negate UV/V immediate");
 640    case BRW_REGISTER_TYPE_HF:
 641       reg->ud ^= 0x80008000;
 642       return true;
 643    case BRW_REGISTER_TYPE_NF:
 644       unreachable("no NF immediates");
 645    }
 646
 647    return false;
 648 }
 649
 650 bool
 651 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 652 {
 653    switch (type) {
 654    case BRW_REGISTER_TYPE_D:
 655       reg->d = abs(reg->d);
 656       return true;
 657    case BRW_REGISTER_TYPE_W: {
 658       uint16_t value = abs((int16_t)reg->ud);
 659       reg->ud = value | (uint32_t)value << 16;
 660       return true;
 661    }
 662    case BRW_REGISTER_TYPE_F:
 663       reg->f = fabsf(reg->f);
 664       return true;
 665    case BRW_REGISTER_TYPE_DF:
 666       reg->df = fabs(reg->df);
 667       return true;
 668    case BRW_REGISTER_TYPE_VF:
 669       reg->ud &= ~0x80808080;
 670       return true;
 671    case BRW_REGISTER_TYPE_Q:
 672       reg->d64 = imaxabs(reg->d64);
 673       return true;
 674    case BRW_REGISTER_TYPE_UB:
 675    case BRW_REGISTER_TYPE_B:
 676       unreachable("no UB/B immediates");
 677    case BRW_REGISTER_TYPE_UQ:
 678    case BRW_REGISTER_TYPE_UD:
 679    case BRW_REGISTER_TYPE_UW:
 680    case BRW_REGISTER_TYPE_UV:
 681       /* Presumably the absolute value modifier on an unsigned source is a
 682        * nop, but it would be nice to confirm.
 683        */
 684       assert(!"unimplemented: abs unsigned immediate");
 685    case BRW_REGISTER_TYPE_V:
 686       assert(!"unimplemented: abs V immediate");
 687    case BRW_REGISTER_TYPE_HF:
 688       reg->ud &= ~0x80008000;
 689       return true;
 690    case BRW_REGISTER_TYPE_NF:
 691       unreachable("no NF immediates");
 692    }
 693
 694    return false;
 695 }
 696
 697 backend_shader::backend_shader(const struct brw_compiler *compiler,
 698                                void *log_data,
 699                                void *mem_ctx,
 700                                const nir_shader *shader,
 701                                struct brw_stage_prog_data *stage_prog_data)
 702    : compiler(compiler),
 703      log_data(log_data),
 704      devinfo(compiler->devinfo),
 705      nir(shader),
 706      stage_prog_data(stage_prog_data),
 707      mem_ctx(mem_ctx),
 708      cfg(NULL), idom_analysis(this),
 709      stage(shader->info.stage)
 710 {
 711    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 712    stage_name = _mesa_shader_stage_to_string(stage);
 713    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 714 }
 715
 716 backend_shader::~backend_shader()
 717 {
 718 }
 719
 720 bool
 721 backend_reg::equals(const backend_reg &r) const
 722 {
 723    return brw_regs_equal(this, &r) && offset == r.offset;
 724 }
 725
 726 bool
 727 backend_reg::negative_equals(const backend_reg &r) const
 728 {
 729    return brw_regs_negative_equal(this, &r) && offset == r.offset;
 730 }
 731
 732 bool
 733 backend_reg::is_zero() const
 734 {
 735    if (file != IMM)
 736       return false;
 737
 738    assert(type_sz(type) > 1);
 739
 740    switch (type) {
 741    case BRW_REGISTER_TYPE_HF:
 742       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 743       return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
 744    case BRW_REGISTER_TYPE_F:
 745       return f == 0;
 746    case BRW_REGISTER_TYPE_DF:
 747       return df == 0;
 748    case BRW_REGISTER_TYPE_W:
 749    case BRW_REGISTER_TYPE_UW:
 750       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 751       return (d & 0xffff) == 0;
 752    case BRW_REGISTER_TYPE_D:
 753    case BRW_REGISTER_TYPE_UD:
 754       return d == 0;
 755    case BRW_REGISTER_TYPE_UQ:
 756    case BRW_REGISTER_TYPE_Q:
 757       return u64 == 0;
 758    default:
 759       return false;
 760    }
 761 }
 762
 763 bool
 764 backend_reg::is_one() const
 765 {
 766    if (file != IMM)
 767       return false;
 768
 769    assert(type_sz(type) > 1);
 770
 771    switch (type) {
 772    case BRW_REGISTER_TYPE_HF:
 773       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 774       return (d & 0xffff) == 0x3c00;
 775    case BRW_REGISTER_TYPE_F:
 776       return f == 1.0f;
 777    case BRW_REGISTER_TYPE_DF:
 778       return df == 1.0;
 779    case BRW_REGISTER_TYPE_W:
 780    case BRW_REGISTER_TYPE_UW:
 781       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 782       return (d & 0xffff) == 1;
 783    case BRW_REGISTER_TYPE_D:
 784    case BRW_REGISTER_TYPE_UD:
 785       return d == 1;
 786    case BRW_REGISTER_TYPE_UQ:
 787    case BRW_REGISTER_TYPE_Q:
 788       return u64 == 1;
 789    default:
 790       return false;
 791    }
 792 }
 793
 794 bool
 795 backend_reg::is_negative_one() const
 796 {
 797    if (file != IMM)
 798       return false;
 799
 800    assert(type_sz(type) > 1);
 801
 802    switch (type) {
 803    case BRW_REGISTER_TYPE_HF:
 804       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 805       return (d & 0xffff) == 0xbc00;
 806    case BRW_REGISTER_TYPE_F:
 807       return f == -1.0;
 808    case BRW_REGISTER_TYPE_DF:
 809       return df == -1.0;
 810    case BRW_REGISTER_TYPE_W:
 811       assert((d & 0xffff) == ((d >> 16) & 0xffff));
 812       return (d & 0xffff) == 0xffff;
 813    case BRW_REGISTER_TYPE_D:
 814       return d == -1;
 815    case BRW_REGISTER_TYPE_Q:
 816       return d64 == -1;
 817    default:
 818       return false;
 819    }
 820 }
 821
 822 bool
 823 backend_reg::is_null() const
 824 {
 825    return file == ARF && nr == BRW_ARF_NULL;
 826 }
 827
 828
 829 bool
 830 backend_reg::is_accumulator() const
 831 {
 832    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 833 }
 834
 835 bool
 836 backend_instruction::is_commutative() const
 837 {
 838    switch (opcode) {
 839    case BRW_OPCODE_AND:
 840    case BRW_OPCODE_OR:
 841    case BRW_OPCODE_XOR:
 842    case BRW_OPCODE_ADD:
 843    case BRW_OPCODE_MUL:
 844    case SHADER_OPCODE_MULH:
 845       return true;
 846    case BRW_OPCODE_SEL:
 847       /* MIN and MAX are commutative. */
 848       if (conditional_mod == BRW_CONDITIONAL_GE ||
 849           conditional_mod == BRW_CONDITIONAL_L) {
 850          return true;
 851       }
 852       /* fallthrough */
 853    default:
 854       return false;
 855    }
 856 }
 857
 858 bool
 859 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 860 {
 861    return ::is_3src(devinfo, opcode);
 862 }
 863
 864 bool
 865 backend_instruction::is_tex() const
 866 {
 867    return (opcode == SHADER_OPCODE_TEX ||
 868            opcode == FS_OPCODE_TXB ||
 869            opcode == SHADER_OPCODE_TXD ||
 870            opcode == SHADER_OPCODE_TXF ||
 871            opcode == SHADER_OPCODE_TXF_LZ ||
 872            opcode == SHADER_OPCODE_TXF_CMS ||
 873            opcode == SHADER_OPCODE_TXF_CMS_W ||
 874            opcode == SHADER_OPCODE_TXF_UMS ||
 875            opcode == SHADER_OPCODE_TXF_MCS ||
 876            opcode == SHADER_OPCODE_TXL ||
 877            opcode == SHADER_OPCODE_TXL_LZ ||
 878            opcode == SHADER_OPCODE_TXS ||
 879            opcode == SHADER_OPCODE_LOD ||
 880            opcode == SHADER_OPCODE_TG4 ||
 881            opcode == SHADER_OPCODE_TG4_OFFSET ||
 882            opcode == SHADER_OPCODE_SAMPLEINFO);
 883 }
 884
 885 bool
 886 backend_instruction::is_math() const
 887 {
 888    return (opcode == SHADER_OPCODE_RCP ||
 889            opcode == SHADER_OPCODE_RSQ ||
 890            opcode == SHADER_OPCODE_SQRT ||
 891            opcode == SHADER_OPCODE_EXP2 ||
 892            opcode == SHADER_OPCODE_LOG2 ||
 893            opcode == SHADER_OPCODE_SIN ||
 894            opcode == SHADER_OPCODE_COS ||
 895            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 896            opcode == SHADER_OPCODE_INT_REMAINDER ||
 897            opcode == SHADER_OPCODE_POW);
 898 }
 899
 900 bool
 901 backend_instruction::is_control_flow() const
 902 {
 903    switch (opcode) {
 904    case BRW_OPCODE_DO:
 905    case BRW_OPCODE_WHILE:
 906    case BRW_OPCODE_IF:
 907    case BRW_OPCODE_ELSE:
 908    case BRW_OPCODE_ENDIF:
 909    case BRW_OPCODE_BREAK:
 910    case BRW_OPCODE_CONTINUE:
 911       return true;
 912    default:
 913       return false;
 914    }
 915 }
 916
 917 bool
 918 backend_instruction::can_do_source_mods() const
 919 {
 920    switch (opcode) {
 921    case BRW_OPCODE_ADDC:
 922    case BRW_OPCODE_BFE:
 923    case BRW_OPCODE_BFI1:
 924    case BRW_OPCODE_BFI2:
 925    case BRW_OPCODE_BFREV:
 926    case BRW_OPCODE_CBIT:
 927    case BRW_OPCODE_FBH:
 928    case BRW_OPCODE_FBL:
 929    case BRW_OPCODE_SUBB:
 930    case SHADER_OPCODE_BROADCAST:
 931    case SHADER_OPCODE_CLUSTER_BROADCAST:
 932    case SHADER_OPCODE_MOV_INDIRECT:
 933       return false;
 934    default:
 935       return true;
 936    }
 937 }
 938
 939 bool
 940 backend_instruction::can_do_saturate() const
 941 {
 942    switch (opcode) {
 943    case BRW_OPCODE_ADD:
 944    case BRW_OPCODE_ASR:
 945    case BRW_OPCODE_AVG:
 946    case BRW_OPCODE_CSEL:
 947    case BRW_OPCODE_DP2:
 948    case BRW_OPCODE_DP3:
 949    case BRW_OPCODE_DP4:
 950    case BRW_OPCODE_DPH:
 951    case BRW_OPCODE_F16TO32:
 952    case BRW_OPCODE_F32TO16:
 953    case BRW_OPCODE_LINE:
 954    case BRW_OPCODE_LRP:
 955    case BRW_OPCODE_MAC:
 956    case BRW_OPCODE_MAD:
 957    case BRW_OPCODE_MATH:
 958    case BRW_OPCODE_MOV:
 959    case BRW_OPCODE_MUL:
 960    case SHADER_OPCODE_MULH:
 961    case BRW_OPCODE_PLN:
 962    case BRW_OPCODE_RNDD:
 963    case BRW_OPCODE_RNDE:
 964    case BRW_OPCODE_RNDU:
 965    case BRW_OPCODE_RNDZ:
 966    case BRW_OPCODE_SEL:
 967    case BRW_OPCODE_SHL:
 968    case BRW_OPCODE_SHR:
 969    case FS_OPCODE_LINTERP:
 970    case SHADER_OPCODE_COS:
 971    case SHADER_OPCODE_EXP2:
 972    case SHADER_OPCODE_LOG2:
 973    case SHADER_OPCODE_POW:
 974    case SHADER_OPCODE_RCP:
 975    case SHADER_OPCODE_RSQ:
 976    case SHADER_OPCODE_SIN:
 977    case SHADER_OPCODE_SQRT:
 978       return true;
 979    default:
 980       return false;
 981    }
 982 }
 983
 984 bool
 985 backend_instruction::can_do_cmod() const
 986 {
 987    switch (opcode) {
 988    case BRW_OPCODE_ADD:
 989    case BRW_OPCODE_ADDC:
 990    case BRW_OPCODE_AND:
 991    case BRW_OPCODE_ASR:
 992    case BRW_OPCODE_AVG:
 993    case BRW_OPCODE_CMP:
 994    case BRW_OPCODE_CMPN:
 995    case BRW_OPCODE_DP2:
 996    case BRW_OPCODE_DP3:
 997    case BRW_OPCODE_DP4:
 998    case BRW_OPCODE_DPH:
 999    case BRW_OPCODE_F16TO32:
1000    case BRW_OPCODE_F32TO16:
1001    case BRW_OPCODE_FRC:
1002    case BRW_OPCODE_LINE:
1003    case BRW_OPCODE_LRP:
1004    case BRW_OPCODE_LZD:
1005    case BRW_OPCODE_MAC:
1006    case BRW_OPCODE_MACH:
1007    case BRW_OPCODE_MAD:
1008    case BRW_OPCODE_MOV:
1009    case BRW_OPCODE_MUL:
1010    case BRW_OPCODE_NOT:
1011    case BRW_OPCODE_OR:
1012    case BRW_OPCODE_PLN:
1013    case BRW_OPCODE_RNDD:
1014    case BRW_OPCODE_RNDE:
1015    case BRW_OPCODE_RNDU:
1016    case BRW_OPCODE_RNDZ:
1017    case BRW_OPCODE_SAD2:
1018    case BRW_OPCODE_SADA2:
1019    case BRW_OPCODE_SHL:
1020    case BRW_OPCODE_SHR:
1021    case BRW_OPCODE_SUBB:
1022    case BRW_OPCODE_XOR:
1023    case FS_OPCODE_LINTERP:
1024       return true;
1025    default:
1026       return false;
1027    }
1028 }
1029
1030 bool
1031 backend_instruction::reads_accumulator_implicitly() const
1032 {
1033    switch (opcode) {
1034    case BRW_OPCODE_MAC:
1035    case BRW_OPCODE_MACH:
1036    case BRW_OPCODE_SADA2:
1037       return true;
1038    default:
1039       return false;
1040    }
1041 }
1042
1043 bool
1044 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
1045 {
1046    return writes_accumulator ||
1047           (devinfo->gen < 6 &&
1048            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1049             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
1050           (opcode == FS_OPCODE_LINTERP &&
1051            (!devinfo->has_pln || devinfo->gen <= 6));
1052 }
1053
1054 bool
1055 backend_instruction::has_side_effects() const
1056 {
1057    switch (opcode) {
1058    case SHADER_OPCODE_SEND:
1059       return send_has_side_effects;
1060
1061    case BRW_OPCODE_SYNC:
1062    case VEC4_OPCODE_UNTYPED_ATOMIC:
1063    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1064    case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1065    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1066    case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1067    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1068    case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1069    case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1070    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1071    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL:
1072    case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL:
1073    case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1074    case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
1075    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1076    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1077    case SHADER_OPCODE_MEMORY_FENCE:
1078    case SHADER_OPCODE_INTERLOCK:
1079    case SHADER_OPCODE_URB_WRITE_SIMD8:
1080    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
1081    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
1082    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
1083    case FS_OPCODE_FB_WRITE:
1084    case FS_OPCODE_FB_WRITE_LOGICAL:
1085    case FS_OPCODE_REP_FB_WRITE:
1086    case SHADER_OPCODE_BARRIER:
1087    case TCS_OPCODE_URB_WRITE:
1088    case TCS_OPCODE_RELEASE_INPUT:
1089    case SHADER_OPCODE_RND_MODE:
1090    case SHADER_OPCODE_FLOAT_CONTROL_MODE:
1091    case FS_OPCODE_SCHEDULING_FENCE:
1092       return true;
1093    default:
1094       return eot;
1095    }
1096 }
1097
1098 bool
1099 backend_instruction::is_volatile() const
1100 {
1101    switch (opcode) {
1102    case SHADER_OPCODE_SEND:
1103       return send_is_volatile;
1104
1105    case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1106    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1107    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1108    case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1109    case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
1110    case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1111    case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1112    case SHADER_OPCODE_URB_READ_SIMD8:
1113    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1114    case VEC4_OPCODE_URB_READ:
1115       return true;
1116    default:
1117       return false;
1118    }
1119 }
1120
1121 #ifndef NDEBUG
1122 static bool
1123 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1124 {
1125    bool found = false;
1126    foreach_inst_in_block (backend_instruction, i, block) {
1127       if (inst == i) {
1128          found = true;
1129       }
1130    }
1131    return found;
1132 }
1133 #endif
1134
1135 static void
1136 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1137 {
1138    for (bblock_t *block_iter = start_block->next();
1139         block_iter;
1140         block_iter = block_iter->next()) {
1141       block_iter->start_ip += ip_adjustment;
1142       block_iter->end_ip += ip_adjustment;
1143    }
1144 }
1145
1146 void
1147 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1148 {
1149    assert(this != inst);
1150
1151    if (!this->is_head_sentinel())
1152       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1153
1154    block->end_ip++;
1155
1156    adjust_later_block_ips(block, 1);
1157
1158    exec_node::insert_after(inst);
1159 }
1160
1161 void
1162 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1163 {
1164    assert(this != inst);
1165
1166    if (!this->is_tail_sentinel())
1167       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1168
1169    block->end_ip++;
1170
1171    adjust_later_block_ips(block, 1);
1172
1173    exec_node::insert_before(inst);
1174 }
1175
1176 void
1177 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1178 {
1179    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1180
1181    unsigned num_inst = list->length();
1182
1183    block->end_ip += num_inst;
1184
1185    adjust_later_block_ips(block, num_inst);
1186
1187    exec_node::insert_before(list);
1188 }
1189
1190 void
1191 backend_instruction::remove(bblock_t *block)
1192 {
1193    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1194
1195    adjust_later_block_ips(block, -1);
1196
1197    if (block->start_ip == block->end_ip) {
1198       block->cfg->remove_block(block);
1199    } else {
1200       block->end_ip--;
1201    }
1202
1203    exec_node::remove();
1204 }
1205
1206 void
1207 backend_shader::dump_instructions() const
1208 {
1209    dump_instructions(NULL);
1210 }
1211
1212 void
1213 backend_shader::dump_instructions(const char *name) const
1214 {
1215    FILE *file = stderr;
1216    if (name && geteuid() != 0) {
1217       file = fopen(name, "w");
1218       if (!file)
1219          file = stderr;
1220    }
1221
1222    if (cfg) {
1223       int ip = 0;
1224       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1225          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1226             fprintf(file, "%4d: ", ip++);
1227          dump_instruction(inst, file);
1228       }
1229    } else {
1230       int ip = 0;
1231       foreach_in_list(backend_instruction, inst, &instructions) {
1232          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1233             fprintf(file, "%4d: ", ip++);
1234          dump_instruction(inst, file);
1235       }
1236    }
1237
1238    if (file != stderr) {
1239       fclose(file);
1240    }
1241 }
1242
1243 void
1244 backend_shader::calculate_cfg()
1245 {
1246    if (this->cfg)
1247       return;
1248    cfg = new(mem_ctx) cfg_t(this, &this->instructions);
1249 }
1250
1251 void
1252 backend_shader::invalidate_analysis(brw::analysis_dependency_class c)
1253 {
1254    idom_analysis.invalidate(c);
1255 }
1256
1257 extern "C" const unsigned *
1258 brw_compile_tes(const struct brw_compiler *compiler,
1259                 void *log_data,
1260                 void *mem_ctx,
1261                 const struct brw_tes_prog_key *key,
1262                 const struct brw_vue_map *input_vue_map,
1263                 struct brw_tes_prog_data *prog_data,
1264                 nir_shader *nir,
1265                 int shader_time_index,
1266                 struct brw_compile_stats *stats,
1267                 char **error_str)
1268 {
1269    const struct gen_device_info *devinfo = compiler->devinfo;
1270    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1271    const unsigned *assembly;
1272
1273    nir->info.inputs_read = key->inputs_read;
1274    nir->info.patch_inputs_read = key->patch_inputs_read;
1275
1276    brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar);
1277    brw_nir_lower_tes_inputs(nir, input_vue_map);
1278    brw_nir_lower_vue_outputs(nir);
1279    brw_postprocess_nir(nir, compiler, is_scalar);
1280
1281    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1282                        nir->info.outputs_written,
1283                        nir->info.separate_shader, 1);
1284
1285    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1286
1287    assert(output_size_bytes >= 1);
1288    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1289       if (error_str)
1290          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1291       return NULL;
1292    }
1293
1294    prog_data->base.clip_distance_mask =
1295       ((1 << nir->info.clip_distance_array_size) - 1);
1296    prog_data->base.cull_distance_mask =
1297       ((1 << nir->info.cull_distance_array_size) - 1) <<
1298       nir->info.clip_distance_array_size;
1299
1300    /* URB entry sizes are stored as a multiple of 64 bytes. */
1301    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1302
1303    /* On Cannonlake software shall not program an allocation size that
1304     * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
1305     */
1306    if (devinfo->gen == 10 &&
1307        prog_data->base.urb_entry_size % 3 == 0)
1308       prog_data->base.urb_entry_size++;
1309
1310    prog_data->base.urb_read_length = 0;
1311
1312    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1313    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1314                  TESS_SPACING_FRACTIONAL_ODD - 1);
1315    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1316                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1317
1318    prog_data->partitioning =
1319       (enum brw_tess_partitioning) (nir->info.tess.spacing - 1);
1320
1321    switch (nir->info.tess.primitive_mode) {
1322    case GL_QUADS:
1323       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1324       break;
1325    case GL_TRIANGLES:
1326       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1327       break;
1328    case GL_ISOLINES:
1329       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1330       break;
1331    default:
1332       unreachable("invalid domain shader primitive mode");
1333    }
1334
1335    if (nir->info.tess.point_mode) {
1336       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1337    } else if (nir->info.tess.primitive_mode == GL_ISOLINES) {
1338       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1339    } else {
1340       /* Hardware winding order is backwards from OpenGL */
1341       prog_data->output_topology =
1342          nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1343                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1344    }
1345
1346    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1347       fprintf(stderr, "TES Input ");
1348       brw_print_vue_map(stderr, input_vue_map);
1349       fprintf(stderr, "TES Output ");
1350       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1351    }
1352
1353    if (is_scalar) {
1354       fs_visitor v(compiler, log_data, mem_ctx, &key->base,
1355                    &prog_data->base.base, nir, 8,
1356                    shader_time_index, input_vue_map);
1357       if (!v.run_tes()) {
1358          if (error_str)
1359             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1360          return NULL;
1361       }
1362
1363       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1364       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1365
1366       fs_generator g(compiler, log_data, mem_ctx,
1367                      &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
1368       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1369          g.enable_debug(ralloc_asprintf(mem_ctx,
1370                                         "%s tessellation evaluation shader %s",
1371                                         nir->info.label ? nir->info.label
1372                                                         : "unnamed",
1373                                         nir->info.name));
1374       }
1375
1376       g.generate_code(v.cfg, 8, v.shader_stats,
1377                       v.performance_analysis.require(), stats);
1378
1379       g.add_const_data(nir->constant_data, nir->constant_data_size);
1380
1381       assembly = g.get_assembly();
1382    } else {
1383       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1384                               nir, mem_ctx, shader_time_index);
1385       if (!v.run()) {
1386          if (error_str)
1387             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1388          return NULL;
1389       }
1390
1391       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1392          v.dump_instructions();
1393
1394       assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1395                                             &prog_data->base, v.cfg,
1396                                             v.performance_analysis.require(),
1397                                             stats);
1398    }
1399
1400    return assembly;
1401 }