src/intel/compiler/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27 #include "brw_reg.h"
  28 #include "brw_compiler.h"
  29 #include "brw_eu_defines.h"
  30 #include "brw_inst.h"
  31 #include "compiler/nir/nir.h"
  32
  33 #ifdef __cplusplus
  34 #include "brw_ir_allocator.h"
  35 #endif
  36
  37 #define MAX_SAMPLER_MESSAGE_SIZE 11
  38 #define MAX_VGRF_SIZE 16
  39
  40 #ifdef __cplusplus
  41 struct backend_reg : private brw_reg
  42 {
  43    backend_reg() {}
  44    backend_reg(const struct brw_reg &reg) : brw_reg(reg) {}
  45
  46    const brw_reg &as_brw_reg() const
  47    {
  48       assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
  49       assert(offset == 0);
  50       return static_cast<const brw_reg &>(*this);
  51    }
  52
  53    brw_reg &as_brw_reg()
  54    {
  55       assert(file == ARF || file == FIXED_GRF || file == MRF || file == IMM);
  56       assert(offset == 0);
  57       return static_cast<brw_reg &>(*this);
  58    }
  59
  60    bool equals(const backend_reg &r) const;
  61
  62    bool is_zero() const;
  63    bool is_one() const;
  64    bool is_negative_one() const;
  65    bool is_null() const;
  66    bool is_accumulator() const;
  67
  68    /** Offset from the start of the (virtual) register in bytes. */
  69    uint16_t offset;
  70
  71    using brw_reg::type;
  72    using brw_reg::file;
  73    using brw_reg::negate;
  74    using brw_reg::abs;
  75    using brw_reg::address_mode;
  76    using brw_reg::subnr;
  77    using brw_reg::nr;
  78
  79    using brw_reg::swizzle;
  80    using brw_reg::writemask;
  81    using brw_reg::indirect_offset;
  82    using brw_reg::vstride;
  83    using brw_reg::width;
  84    using brw_reg::hstride;
  85
  86    using brw_reg::df;
  87    using brw_reg::f;
  88    using brw_reg::d;
  89    using brw_reg::ud;
  90 };
  91 #endif
  92
  93 struct cfg_t;
  94 struct bblock_t;
  95
  96 #ifdef __cplusplus
  97 struct backend_instruction : public exec_node {
  98    bool is_3src(const struct gen_device_info *devinfo) const;
  99    bool is_tex() const;
 100    bool is_math() const;
 101    bool is_control_flow() const;
 102    bool is_commutative() const;
 103    bool can_do_source_mods() const;
 104    bool can_do_saturate() const;
 105    bool can_do_cmod() const;
 106    bool reads_accumulator_implicitly() const;
 107    bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const;
 108
 109    void remove(bblock_t *block);
 110    void insert_after(bblock_t *block, backend_instruction *inst);
 111    void insert_before(bblock_t *block, backend_instruction *inst);
 112    void insert_before(bblock_t *block, exec_list *list);
 113
 114    /**
 115     * True if the instruction has side effects other than writing to
 116     * its destination registers.  You are expected not to reorder or
 117     * optimize these out unless you know what you are doing.
 118     */
 119    bool has_side_effects() const;
 120
 121    /**
 122     * True if the instruction might be affected by side effects of other
 123     * instructions.
 124     */
 125    bool is_volatile() const;
 126 #else
 127 struct backend_instruction {
 128    struct exec_node link;
 129 #endif
 130    /** @{
 131     * Annotation for the generated IR.  One of the two can be set.
 132     */
 133    const void *ir;
 134    const char *annotation;
 135    /** @} */
 136
 137    /**
 138     * Execution size of the instruction.  This is used by the generator to
 139     * generate the correct binary for the given instruction.  Current valid
 140     * values are 1, 4, 8, 16, 32.
 141     */
 142    uint8_t exec_size;
 143
 144    /**
 145     * Channel group from the hardware execution and predication mask that
 146     * should be applied to the instruction.  The subset of channel enable
 147     * signals (calculated from the EU control flow and predication state)
 148     * given by [group, group + exec_size) will be used to mask GRF writes and
 149     * any other side effects of the instruction.
 150     */
 151    uint8_t group;
 152
 153    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 154    uint8_t mlen; /**< SEND message length */
 155    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 156    uint8_t target; /**< MRT target. */
 157    unsigned size_written; /**< Data written to the destination register in bytes. */
 158
 159    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 160    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 161    enum brw_predicate predicate;
 162    bool predicate_inverse:1;
 163    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 164    bool force_writemask_all:1;
 165    bool no_dd_clear:1;
 166    bool no_dd_check:1;
 167    bool saturate:1;
 168    bool shadow_compare:1;
 169
 170    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 171     * mod and predication.
 172     */
 173    unsigned flag_subreg:1;
 174
 175    /** The number of hardware registers used for a message header. */
 176    uint8_t header_size;
 177 };
 178
 179 #ifdef __cplusplus
 180
 181 enum instruction_scheduler_mode {
 182    SCHEDULE_PRE,
 183    SCHEDULE_PRE_NON_LIFO,
 184    SCHEDULE_PRE_LIFO,
 185    SCHEDULE_POST,
 186 };
 187
 188 struct backend_shader {
 189 protected:
 190
 191    backend_shader(const struct brw_compiler *compiler,
 192                   void *log_data,
 193                   void *mem_ctx,
 194                   const nir_shader *shader,
 195                   struct brw_stage_prog_data *stage_prog_data);
 196
 197 public:
 198
 199    const struct brw_compiler *compiler;
 200    void *log_data; /* Passed to compiler->*_log functions */
 201
 202    const struct gen_device_info * const devinfo;
 203    const nir_shader *nir;
 204    struct brw_stage_prog_data * const stage_prog_data;
 205
 206    /** ralloc context for temporary data used during compile */
 207    void *mem_ctx;
 208
 209    /**
 210     * List of either fs_inst or vec4_instruction (inheriting from
 211     * backend_instruction)
 212     */
 213    exec_list instructions;
 214
 215    cfg_t *cfg;
 216
 217    gl_shader_stage stage;
 218    bool debug_enabled;
 219    const char *stage_name;
 220    const char *stage_abbrev;
 221
 222    brw::simple_allocator alloc;
 223
 224    virtual void dump_instruction(backend_instruction *inst) = 0;
 225    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 226    virtual void dump_instructions();
 227    virtual void dump_instructions(const char *name);
 228
 229    void calculate_cfg();
 230
 231    virtual void invalidate_live_intervals() = 0;
 232 };
 233
 234 bool brw_texture_offset(int *offsets,
 235                         unsigned num_components,
 236                         uint32_t *offset_bits);
 237
 238 void brw_setup_image_uniform_values(gl_shader_stage stage,
 239                                     struct brw_stage_prog_data *stage_prog_data,
 240                                     unsigned param_start_index,
 241                                     const gl_uniform_storage *storage);
 242
 243 #else
 244 struct backend_shader;
 245 #endif /* __cplusplus */
 246
 247 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 248 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 249 uint32_t brw_math_function(enum opcode op);
 250 const char *brw_instruction_name(const struct gen_device_info *devinfo,
 251                                  enum opcode op);
 252 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 253 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 254 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 255
 256 bool opt_predicated_break(struct backend_shader *s);
 257
 258 #ifdef __cplusplus
 259 extern "C" {
 260 #endif
 261
 262 /* brw_fs_reg_allocate.cpp */
 263 void brw_fs_alloc_reg_sets(struct brw_compiler *compiler);
 264
 265 /* brw_vec4_reg_allocate.cpp */
 266 void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
 267
 268 /* brw_disasm.c */
 269 extern const char *const conditional_modifier[16];
 270 extern const char *const pred_ctrl_align16[16];
 271
 272 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
 273 static inline int
 274 brw_get_scratch_size(int size)
 275 {
 276    return MAX2(1024, util_next_power_of_two(size));
 277 }
 278
 279 /**
 280  * Scratch data used when compiling a GLSL geometry shader.
 281  */
 282 struct brw_gs_compile
 283 {
 284    struct brw_gs_prog_key key;
 285    struct brw_vue_map input_vue_map;
 286
 287    unsigned control_data_bits_per_vertex;
 288    unsigned control_data_header_size_bits;
 289 };
 290
 291 unsigned get_atomic_counter_op(nir_intrinsic_op op);
 292
 293 #ifdef __cplusplus
 294 }
 295 #endif