1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "common/gen_debug.h"
31 generate_math1_gen4(struct brw_codegen
*p
,
32 vec4_instruction
*inst
,
38 brw_math_function(inst
->opcode
),
41 BRW_MATH_PRECISION_FULL
);
45 check_gen6_math_src_arg(struct brw_reg src
)
47 /* Source swizzles are ignored. */
50 assert(src
.swizzle
== BRW_SWIZZLE_XYZW
);
54 generate_math_gen6(struct brw_codegen
*p
,
55 vec4_instruction
*inst
,
60 /* Can't do writemask because math can't be align16. */
61 assert(dst
.writemask
== WRITEMASK_XYZW
);
62 /* Source swizzles are ignored. */
63 check_gen6_math_src_arg(src0
);
64 if (src1
.file
== BRW_GENERAL_REGISTER_FILE
)
65 check_gen6_math_src_arg(src1
);
67 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
68 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src0
, src1
);
69 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
73 generate_math2_gen4(struct brw_codegen
*p
,
74 vec4_instruction
*inst
,
79 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
82 * "Operand0[7]. For the INT DIV functions, this operand is the
85 * "Operand1[7]. For the INT DIV functions, this operand is the
88 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
89 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
90 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
92 brw_push_insn_state(p
);
93 brw_set_default_saturate(p
, false);
94 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
95 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
96 brw_pop_insn_state(p
);
100 brw_math_function(inst
->opcode
),
103 BRW_MATH_PRECISION_FULL
);
107 generate_tex(struct brw_codegen
*p
,
108 struct brw_vue_prog_data
*prog_data
,
109 gl_shader_stage stage
,
110 vec4_instruction
*inst
,
113 struct brw_reg surface_index
,
114 struct brw_reg sampler_index
)
116 const struct gen_device_info
*devinfo
= p
->devinfo
;
119 if (devinfo
->gen
>= 5) {
120 switch (inst
->opcode
) {
121 case SHADER_OPCODE_TEX
:
122 case SHADER_OPCODE_TXL
:
123 if (inst
->shadow_compare
) {
124 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
126 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
129 case SHADER_OPCODE_TXD
:
130 if (inst
->shadow_compare
) {
131 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
132 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
133 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
135 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
138 case SHADER_OPCODE_TXF
:
139 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
141 case SHADER_OPCODE_TXF_CMS_W
:
142 assert(devinfo
->gen
>= 9);
143 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
145 case SHADER_OPCODE_TXF_CMS
:
146 if (devinfo
->gen
>= 7)
147 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
149 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
151 case SHADER_OPCODE_TXF_MCS
:
152 assert(devinfo
->gen
>= 7);
153 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
155 case SHADER_OPCODE_TXS
:
156 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
158 case SHADER_OPCODE_TG4
:
159 if (inst
->shadow_compare
) {
160 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
162 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
165 case SHADER_OPCODE_TG4_OFFSET
:
166 if (inst
->shadow_compare
) {
167 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
169 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
172 case SHADER_OPCODE_SAMPLEINFO
:
173 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
176 unreachable("should not get here: invalid vec4 texture opcode");
179 switch (inst
->opcode
) {
180 case SHADER_OPCODE_TEX
:
181 case SHADER_OPCODE_TXL
:
182 if (inst
->shadow_compare
) {
183 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
184 assert(inst
->mlen
== 3);
186 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
187 assert(inst
->mlen
== 2);
190 case SHADER_OPCODE_TXD
:
191 /* There is no sample_d_c message; comparisons are done manually. */
192 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
193 assert(inst
->mlen
== 4);
195 case SHADER_OPCODE_TXF
:
196 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
197 assert(inst
->mlen
== 2);
199 case SHADER_OPCODE_TXS
:
200 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
201 assert(inst
->mlen
== 2);
204 unreachable("should not get here: invalid vec4 texture opcode");
208 assert(msg_type
!= -1);
210 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
212 /* Load the message header if present. If there's a texture offset, we need
213 * to set it up explicitly and load the offset bitfield. Otherwise, we can
214 * use an implied move from g0 to the first message register.
216 if (inst
->header_size
!= 0) {
217 if (devinfo
->gen
< 6 && !inst
->offset
) {
218 /* Set up an implied move from g0 to the MRF. */
219 src
= brw_vec8_grf(0, 0);
221 struct brw_reg header
=
222 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
225 /* Explicitly set up the message header by copying g0 to the MRF. */
226 brw_push_insn_state(p
);
227 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
228 brw_MOV(p
, header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
230 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
233 /* Set the texel offset bits in DWord 2. */
236 if (devinfo
->gen
>= 9)
237 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
238 * based on bit 22 in the header.
240 dw2
|= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
;
242 /* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
243 * so header0.2 is 0 when g0 is copied. The HS and GS stages do
244 * not, so we must set to to 0 to avoid setting undesirable bits
245 * in the message header.
248 stage
== MESA_SHADER_TESS_CTRL
||
249 stage
== MESA_SHADER_GEOMETRY
) {
250 brw_MOV(p
, get_element_ud(header
, 2), brw_imm_ud(dw2
));
253 brw_adjust_sampler_state_pointer(p
, header
, sampler_index
);
254 brw_pop_insn_state(p
);
258 uint32_t return_format
;
261 case BRW_REGISTER_TYPE_D
:
262 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
264 case BRW_REGISTER_TYPE_UD
:
265 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
268 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
272 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
273 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
274 ? prog_data
->base
.binding_table
.gather_texture_start
275 : prog_data
->base
.binding_table
.texture_start
;
277 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
278 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
279 uint32_t surface
= surface_index
.ud
;
280 uint32_t sampler
= sampler_index
.ud
;
286 surface
+ base_binding_table_index
,
289 1, /* response length */
291 inst
->header_size
!= 0,
292 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
295 brw_mark_surface_used(&prog_data
->base
, sampler
+ base_binding_table_index
);
297 /* Non-constant sampler index. */
299 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
300 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
301 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
303 brw_push_insn_state(p
);
304 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
305 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
307 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
308 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
310 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
311 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
313 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
314 brw_OR(p
, addr
, addr
, surface_reg
);
317 if (base_binding_table_index
)
318 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
319 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
321 brw_pop_insn_state(p
);
323 if (inst
->base_mrf
!= -1)
324 gen6_resolve_implied_move(p
, &src
, inst
->base_mrf
);
326 /* dst = send(offset, a0.0 | <descriptor>) */
327 brw_inst
*insn
= brw_send_indirect_message(
328 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
, 0);
329 brw_set_sampler_message(p
, insn
,
334 inst
->mlen
/* mlen */,
335 inst
->header_size
!= 0 /* header */,
336 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
339 /* visitor knows more than we do about the surface limit required,
340 * so has already done marking.
346 generate_vs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
349 brw_null_reg(), /* dest */
350 inst
->base_mrf
, /* starting mrf reg nr */
351 brw_vec8_grf(0, 0), /* src */
352 inst
->urb_write_flags
,
354 0, /* response len */
355 inst
->offset
, /* urb destination offset */
356 BRW_URB_SWIZZLE_INTERLEAVE
);
360 generate_gs_urb_write(struct brw_codegen
*p
, vec4_instruction
*inst
)
362 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
364 brw_null_reg(), /* dest */
365 inst
->base_mrf
, /* starting mrf reg nr */
367 inst
->urb_write_flags
,
369 0, /* response len */
370 inst
->offset
, /* urb destination offset */
371 BRW_URB_SWIZZLE_INTERLEAVE
);
375 generate_gs_urb_write_allocate(struct brw_codegen
*p
, vec4_instruction
*inst
)
377 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
379 /* We pass the temporary passed in src0 as the writeback register */
381 inst
->src
[0].as_brw_reg(), /* dest */
382 inst
->base_mrf
, /* starting mrf reg nr */
384 BRW_URB_WRITE_ALLOCATE_COMPLETE
,
386 1, /* response len */
387 inst
->offset
, /* urb destination offset */
388 BRW_URB_SWIZZLE_INTERLEAVE
);
390 /* Now put allocated urb handle in dst.0 */
391 brw_push_insn_state(p
);
392 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
393 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
394 brw_MOV(p
, get_element_ud(inst
->dst
.as_brw_reg(), 0),
395 get_element_ud(inst
->src
[0].as_brw_reg(), 0));
396 brw_pop_insn_state(p
);
400 generate_gs_thread_end(struct brw_codegen
*p
, vec4_instruction
*inst
)
402 struct brw_reg src
= brw_message_reg(inst
->base_mrf
);
404 brw_null_reg(), /* dest */
405 inst
->base_mrf
, /* starting mrf reg nr */
407 BRW_URB_WRITE_EOT
| inst
->urb_write_flags
,
409 0, /* response len */
410 0, /* urb destination offset */
411 BRW_URB_SWIZZLE_INTERLEAVE
);
415 generate_gs_set_write_offset(struct brw_codegen
*p
,
420 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
423 * Slot 0 Offset. This field, after adding to the Global Offset field
424 * in the message descriptor, specifies the offset (in 256-bit units)
425 * from the start of the URB entry, as referenced by URB Handle 0, at
426 * which the data will be accessed.
428 * Similar text describes DWORD M0.4, which is slot 1 offset.
430 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
431 * of the register for geometry shader invocations 0 and 1) by the
432 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
434 * We can do this with the following EU instruction:
436 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
438 brw_push_insn_state(p
);
439 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
440 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
441 assert(p
->devinfo
->gen
>= 7 &&
442 src1
.file
== BRW_IMMEDIATE_VALUE
&&
443 src1
.type
== BRW_REGISTER_TYPE_UD
&&
444 src1
.ud
<= USHRT_MAX
);
445 if (src0
.file
== BRW_IMMEDIATE_VALUE
) {
446 brw_MOV(p
, suboffset(stride(dst
, 2, 2, 1), 3),
447 brw_imm_ud(src0
.ud
* src1
.ud
));
449 brw_MUL(p
, suboffset(stride(dst
, 2, 2, 1), 3), stride(src0
, 8, 2, 4),
450 retype(src1
, BRW_REGISTER_TYPE_UW
));
452 brw_pop_insn_state(p
);
456 generate_gs_set_vertex_count(struct brw_codegen
*p
,
460 brw_push_insn_state(p
);
461 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
463 if (p
->devinfo
->gen
>= 8) {
464 /* Move the vertex count into the second MRF for the EOT write. */
465 brw_MOV(p
, retype(brw_message_reg(dst
.nr
+ 1), BRW_REGISTER_TYPE_UD
),
468 /* If we think of the src and dst registers as composed of 8 DWORDs each,
469 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
470 * them to WORDs, and then pack them into DWORD 2 of dst.
472 * It's easier to get the EU to do this if we think of the src and dst
473 * registers as composed of 16 WORDS each; then, we want to pick up the
474 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
477 * We can do that by the following EU instruction:
479 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
481 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
483 suboffset(stride(retype(dst
, BRW_REGISTER_TYPE_UW
), 2, 2, 1), 4),
484 stride(retype(src
, BRW_REGISTER_TYPE_UW
), 8, 1, 0));
486 brw_pop_insn_state(p
);
490 generate_gs_svb_write(struct brw_codegen
*p
,
491 struct brw_vue_prog_data
*prog_data
,
492 vec4_instruction
*inst
,
497 int binding
= inst
->sol_binding
;
498 bool final_write
= inst
->sol_final_write
;
500 brw_push_insn_state(p
);
501 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
502 /* Copy Vertex data into M0.x */
503 brw_MOV(p
, stride(dst
, 4, 4, 1),
504 stride(retype(src0
, BRW_REGISTER_TYPE_UD
), 4, 4, 1));
505 brw_pop_insn_state(p
);
507 brw_push_insn_state(p
);
510 final_write
? src1
: brw_null_reg(), /* dest == src1 */
512 dst
, /* src0 == previous dst */
513 BRW_GEN6_SOL_BINDING_START
+ binding
, /* binding_table_index */
514 final_write
); /* send_commit_msg */
516 /* Finally, wait for the write commit to occur so that we can proceed to
517 * other things safely.
519 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
521 * The write commit does not modify the destination register, but
522 * merely clears the dependency associated with the destination
523 * register. Thus, a simple “mov” instruction using the register as a
524 * source is sufficient to wait for the write commit to occur.
527 brw_MOV(p
, src1
, src1
);
529 brw_pop_insn_state(p
);
533 generate_gs_svb_set_destination_index(struct brw_codegen
*p
,
534 vec4_instruction
*inst
,
538 int vertex
= inst
->sol_vertex
;
539 brw_push_insn_state(p
);
540 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
541 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
542 brw_MOV(p
, get_element_ud(dst
, 5), get_element_ud(src
, vertex
));
543 brw_pop_insn_state(p
);
547 generate_gs_set_dword_2(struct brw_codegen
*p
,
551 brw_push_insn_state(p
);
552 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
553 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
554 brw_MOV(p
, suboffset(vec1(dst
), 2), suboffset(vec1(src
), 0));
555 brw_pop_insn_state(p
);
559 generate_gs_prepare_channel_masks(struct brw_codegen
*p
,
562 /* We want to left shift just DWORD 4 (the x component belonging to the
563 * second geometry shader invocation) by 4 bits. So generate the
566 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
568 dst
= suboffset(vec1(dst
), 4);
569 brw_push_insn_state(p
);
570 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
571 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
572 brw_SHL(p
, dst
, dst
, brw_imm_ud(4));
573 brw_pop_insn_state(p
);
577 generate_gs_set_channel_masks(struct brw_codegen
*p
,
581 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
584 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
586 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
587 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
588 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
589 * channel enable to determine the final channel enable. For the
590 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
591 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
592 * in the writeback message. For the URB_WRITE_OWORD &
593 * URB_WRITE_HWORD messages, when final channel enable is 1 it
594 * indicates that Vertex 1 DATA [3] will be written to the surface.
596 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
597 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
599 * 14 Vertex 1 DATA [2] Channel Mask
600 * 13 Vertex 1 DATA [1] Channel Mask
601 * 12 Vertex 1 DATA [0] Channel Mask
602 * 11 Vertex 0 DATA [3] Channel Mask
603 * 10 Vertex 0 DATA [2] Channel Mask
604 * 9 Vertex 0 DATA [1] Channel Mask
605 * 8 Vertex 0 DATA [0] Channel Mask
607 * (This is from a section of the PRM that is agnostic to the particular
608 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
609 * geometry shader invocations 0 and 1, respectively). Since we have the
610 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
611 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
612 * DWORD 4, we just need to OR them together and store the result in bits
615 * It's easier to get the EU to do this if we think of the src and dst
616 * registers as composed of 32 bytes each; then, we want to pick up the
617 * contents of bytes 0 and 16 from src, OR them together, and store them in
620 * We can do that by the following EU instruction:
622 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
624 * Note: this relies on the source register having zeros in (a) bits 7:4 of
625 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
626 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
627 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
628 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
629 * contain valid channel mask values (which are in the range 0x0-0xf).
631 dst
= retype(dst
, BRW_REGISTER_TYPE_UB
);
632 src
= retype(src
, BRW_REGISTER_TYPE_UB
);
633 brw_push_insn_state(p
);
634 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
635 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
636 brw_OR(p
, suboffset(vec1(dst
), 21), vec1(src
), suboffset(vec1(src
), 16));
637 brw_pop_insn_state(p
);
641 generate_gs_get_instance_id(struct brw_codegen
*p
,
644 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
645 * and store into dst.0 & dst.4. So generate the instruction:
647 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
649 brw_push_insn_state(p
);
650 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
651 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
652 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
653 brw_SHR(p
, dst
, stride(r0
, 1, 4, 0),
654 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
));
655 brw_pop_insn_state(p
);
659 generate_gs_ff_sync_set_primitives(struct brw_codegen
*p
,
665 brw_push_insn_state(p
);
666 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
667 /* Save src0 data in 16:31 bits of dst.0 */
668 brw_AND(p
, suboffset(vec1(dst
), 0), suboffset(vec1(src0
), 0),
669 brw_imm_ud(0xffffu
));
670 brw_SHL(p
, suboffset(vec1(dst
), 0), suboffset(vec1(dst
), 0), brw_imm_ud(16));
671 /* Save src1 data in 0:15 bits of dst.0 */
672 brw_AND(p
, suboffset(vec1(src2
), 0), suboffset(vec1(src1
), 0),
673 brw_imm_ud(0xffffu
));
674 brw_OR(p
, suboffset(vec1(dst
), 0),
675 suboffset(vec1(dst
), 0),
676 suboffset(vec1(src2
), 0));
677 brw_pop_insn_state(p
);
681 generate_gs_ff_sync(struct brw_codegen
*p
,
682 vec4_instruction
*inst
,
687 /* This opcode uses an implied MRF register for:
688 * - the header of the ff_sync message. And as such it is expected to be
689 * initialized to r0 before calling here.
690 * - the destination where we will write the allocated URB handle.
692 struct brw_reg header
=
693 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
);
695 /* Overwrite dword 0 of the header (SO vertices to write) and
696 * dword 1 (number of primitives written).
698 brw_push_insn_state(p
);
699 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
700 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
701 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(src1
, 0));
702 brw_MOV(p
, get_element_ud(header
, 1), get_element_ud(src0
, 0));
703 brw_pop_insn_state(p
);
705 /* Allocate URB handle in dst */
711 1, /* response length */
714 /* Now put allocated urb handle in header.0 */
715 brw_push_insn_state(p
);
716 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
717 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
718 brw_MOV(p
, get_element_ud(header
, 0), get_element_ud(dst
, 0));
720 /* src1 is not an immediate when we use transform feedback */
721 if (src1
.file
!= BRW_IMMEDIATE_VALUE
) {
722 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
723 brw_MOV(p
, brw_vec4_grf(src1
.nr
, 0), brw_vec4_grf(dst
.nr
, 1));
726 brw_pop_insn_state(p
);
730 generate_gs_set_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
732 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
733 struct brw_reg src
= brw_vec8_grf(0, 0);
734 brw_push_insn_state(p
);
735 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
736 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
737 brw_MOV(p
, get_element_ud(dst
, 0), get_element_ud(src
, 1));
738 brw_pop_insn_state(p
);
742 generate_tcs_get_instance_id(struct brw_codegen
*p
, struct brw_reg dst
)
744 const struct gen_device_info
*devinfo
= p
->devinfo
;
745 const bool ivb
= devinfo
->is_ivybridge
|| devinfo
->is_baytrail
;
747 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
749 * Since we operate in SIMD4x2 mode, we need run half as many threads
750 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
751 * shift right by one less to accomplish the multiplication by two.
753 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
754 struct brw_reg
r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
756 brw_push_insn_state(p
);
757 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
759 const int mask
= ivb
? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
760 const int shift
= ivb
? 16 : 17;
762 brw_AND(p
, get_element_ud(dst
, 0), get_element_ud(r0
, 2), brw_imm_ud(mask
));
763 brw_SHR(p
, get_element_ud(dst
, 0), get_element_ud(dst
, 0),
764 brw_imm_ud(shift
- 1));
765 brw_ADD(p
, get_element_ud(dst
, 4), get_element_ud(dst
, 0), brw_imm_ud(1));
767 brw_pop_insn_state(p
);
771 generate_tcs_urb_write(struct brw_codegen
*p
,
772 vec4_instruction
*inst
,
773 struct brw_reg urb_header
)
775 const struct gen_device_info
*devinfo
= p
->devinfo
;
777 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
778 brw_set_dest(p
, send
, brw_null_reg());
779 brw_set_src0(p
, send
, urb_header
);
780 brw_set_desc(p
, send
, brw_message_desc(devinfo
, inst
->mlen
, 0, true));
782 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_URB
);
783 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_WRITE_OWORD
);
784 brw_inst_set_urb_global_offset(devinfo
, send
, inst
->offset
);
785 if (inst
->urb_write_flags
& BRW_URB_WRITE_EOT
) {
786 brw_inst_set_eot(devinfo
, send
, 1);
788 brw_inst_set_urb_per_slot_offset(devinfo
, send
, 1);
789 brw_inst_set_urb_swizzle_control(devinfo
, send
, BRW_URB_SWIZZLE_INTERLEAVE
);
792 /* what happens to swizzles? */
797 generate_tcs_input_urb_offsets(struct brw_codegen
*p
,
799 struct brw_reg vertex
,
800 struct brw_reg offset
)
802 /* Generates an URB read/write message header for HS/DS operation.
803 * Inputs are a vertex index, and a byte offset from the beginning of
806 /* If `vertex` is not an immediate, we clobber a0.0 */
808 assert(vertex
.file
== BRW_IMMEDIATE_VALUE
|| vertex
.file
== BRW_GENERAL_REGISTER_FILE
);
809 assert(vertex
.type
== BRW_REGISTER_TYPE_UD
|| vertex
.type
== BRW_REGISTER_TYPE_D
);
811 assert(dst
.file
== BRW_GENERAL_REGISTER_FILE
);
813 brw_push_insn_state(p
);
814 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
815 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
816 brw_MOV(p
, dst
, brw_imm_ud(0));
818 /* m0.5 bits 8-15 are channel enables */
819 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud(0xff00));
821 /* m0.0-0.1: URB handles */
822 if (vertex
.file
== BRW_IMMEDIATE_VALUE
) {
823 uint32_t vertex_index
= vertex
.ud
;
824 struct brw_reg index_reg
= brw_vec1_grf(
825 1 + (vertex_index
>> 3), vertex_index
& 7);
827 brw_MOV(p
, vec2(get_element_ud(dst
, 0)),
828 retype(index_reg
, BRW_REGISTER_TYPE_UD
));
830 /* Use indirect addressing. ICP Handles are DWords (single channels
831 * of a register) and start at g1.0.
833 * In order to start our region at g1.0, we add 8 to the vertex index,
834 * effectively skipping over the 8 channels in g0.0. This gives us a
835 * DWord offset to the ICP Handle.
837 * Indirect addressing works in terms of bytes, so we then multiply
838 * the DWord offset by 4 (by shifting left by 2).
840 struct brw_reg addr
= brw_address_reg(0);
842 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
843 brw_ADD(p
, addr
, retype(get_element_ud(vertex
, 0), BRW_REGISTER_TYPE_UW
),
845 brw_SHL(p
, addr
, addr
, brw_imm_uw(2));
846 brw_MOV(p
, get_element_ud(dst
, 0), deref_1ud(brw_indirect(0, 0), 0));
848 /* top half: m0.1 = g[1.0 + vertex.4]UD */
849 brw_ADD(p
, addr
, retype(get_element_ud(vertex
, 4), BRW_REGISTER_TYPE_UW
),
851 brw_SHL(p
, addr
, addr
, brw_imm_uw(2));
852 brw_MOV(p
, get_element_ud(dst
, 1), deref_1ud(brw_indirect(0, 0), 0));
855 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
856 if (offset
.file
!= ARF
)
857 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
859 brw_pop_insn_state(p
);
864 generate_tcs_output_urb_offsets(struct brw_codegen
*p
,
866 struct brw_reg write_mask
,
867 struct brw_reg offset
)
869 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
870 assert(dst
.file
== BRW_GENERAL_REGISTER_FILE
|| dst
.file
== BRW_MESSAGE_REGISTER_FILE
);
872 assert(write_mask
.file
== BRW_IMMEDIATE_VALUE
);
873 assert(write_mask
.type
== BRW_REGISTER_TYPE_UD
);
875 brw_push_insn_state(p
);
877 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
878 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
879 brw_MOV(p
, dst
, brw_imm_ud(0));
881 unsigned mask
= write_mask
.ud
;
883 /* m0.5 bits 15:12 and 11:8 are channel enables */
884 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud((mask
<< 8) | (mask
<< 12)));
886 /* HS patch URB handle is delivered in r0.0 */
887 struct brw_reg urb_handle
= brw_vec1_grf(0, 0);
889 /* m0.0-0.1: URB handles */
890 brw_MOV(p
, vec2(get_element_ud(dst
, 0)),
891 retype(urb_handle
, BRW_REGISTER_TYPE_UD
));
893 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
894 if (offset
.file
!= ARF
)
895 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
897 brw_pop_insn_state(p
);
901 generate_tes_create_input_read_header(struct brw_codegen
*p
,
904 brw_push_insn_state(p
);
905 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
906 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
908 /* Initialize the register to 0 */
909 brw_MOV(p
, dst
, brw_imm_ud(0));
911 /* Enable all the channels in m0.5 bits 15:8 */
912 brw_MOV(p
, get_element_ud(dst
, 5), brw_imm_ud(0xff00));
914 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
915 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
917 brw_AND(p
, vec2(get_element_ud(dst
, 0)),
918 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD
),
920 brw_pop_insn_state(p
);
924 generate_tes_add_indirect_urb_offset(struct brw_codegen
*p
,
926 struct brw_reg header
,
927 struct brw_reg offset
)
929 brw_push_insn_state(p
);
930 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
931 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
933 brw_MOV(p
, dst
, header
);
934 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
935 brw_MOV(p
, vec2(get_element_ud(dst
, 3)), stride(offset
, 4, 1, 0));
937 brw_pop_insn_state(p
);
941 generate_vec4_urb_read(struct brw_codegen
*p
,
942 vec4_instruction
*inst
,
944 struct brw_reg header
)
946 const struct gen_device_info
*devinfo
= p
->devinfo
;
948 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
949 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
951 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
952 brw_set_dest(p
, send
, dst
);
953 brw_set_src0(p
, send
, header
);
955 brw_set_desc(p
, send
, brw_message_desc(devinfo
, 1, 1, true));
957 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_URB
);
958 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_READ_OWORD
);
959 brw_inst_set_urb_swizzle_control(devinfo
, send
, BRW_URB_SWIZZLE_INTERLEAVE
);
960 brw_inst_set_urb_per_slot_offset(devinfo
, send
, 1);
962 brw_inst_set_urb_global_offset(devinfo
, send
, inst
->offset
);
966 generate_tcs_release_input(struct brw_codegen
*p
,
967 struct brw_reg header
,
968 struct brw_reg vertex
,
969 struct brw_reg is_unpaired
)
971 const struct gen_device_info
*devinfo
= p
->devinfo
;
973 assert(vertex
.file
== BRW_IMMEDIATE_VALUE
);
974 assert(vertex
.type
== BRW_REGISTER_TYPE_UD
);
976 /* m0.0-0.1: URB handles */
977 struct brw_reg urb_handles
=
978 retype(brw_vec2_grf(1 + (vertex
.ud
>> 3), vertex
.ud
& 7),
979 BRW_REGISTER_TYPE_UD
);
981 brw_push_insn_state(p
);
982 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
983 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
984 brw_MOV(p
, header
, brw_imm_ud(0));
985 brw_MOV(p
, vec2(get_element_ud(header
, 0)), urb_handles
);
986 brw_pop_insn_state(p
);
988 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
989 brw_set_dest(p
, send
, brw_null_reg());
990 brw_set_src0(p
, send
, header
);
991 brw_set_desc(p
, send
, brw_message_desc(devinfo
, 1, 0, true));
993 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_URB
);
994 brw_inst_set_urb_opcode(devinfo
, send
, BRW_URB_OPCODE_READ_OWORD
);
995 brw_inst_set_urb_complete(devinfo
, send
, 1);
996 brw_inst_set_urb_swizzle_control(devinfo
, send
, is_unpaired
.ud
?
997 BRW_URB_SWIZZLE_NONE
:
998 BRW_URB_SWIZZLE_INTERLEAVE
);
1002 generate_tcs_thread_end(struct brw_codegen
*p
, vec4_instruction
*inst
)
1004 struct brw_reg header
= brw_message_reg(inst
->base_mrf
);
1006 brw_push_insn_state(p
);
1007 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1008 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1009 brw_MOV(p
, header
, brw_imm_ud(0));
1010 brw_MOV(p
, get_element_ud(header
, 5), brw_imm_ud(WRITEMASK_X
<< 8));
1011 brw_MOV(p
, get_element_ud(header
, 0),
1012 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1013 brw_MOV(p
, brw_message_reg(inst
->base_mrf
+ 1), brw_imm_ud(0u));
1014 brw_pop_insn_state(p
);
1017 brw_null_reg(), /* dest */
1018 inst
->base_mrf
, /* starting mrf reg nr */
1020 BRW_URB_WRITE_EOT
| BRW_URB_WRITE_OWORD
|
1021 BRW_URB_WRITE_USE_CHANNEL_MASKS
,
1023 0, /* response len */
1024 0, /* urb destination offset */
1029 generate_tes_get_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
1031 brw_push_insn_state(p
);
1032 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1033 brw_MOV(p
, dst
, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D
));
1034 brw_pop_insn_state(p
);
1038 generate_tcs_get_primitive_id(struct brw_codegen
*p
, struct brw_reg dst
)
1040 brw_push_insn_state(p
);
1041 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1042 brw_MOV(p
, dst
, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
1043 brw_pop_insn_state(p
);
1047 generate_tcs_create_barrier_header(struct brw_codegen
*p
,
1048 struct brw_vue_prog_data
*prog_data
,
1051 const struct gen_device_info
*devinfo
= p
->devinfo
;
1052 const bool ivb
= devinfo
->is_ivybridge
|| devinfo
->is_baytrail
;
1053 struct brw_reg m0_2
= get_element_ud(dst
, 2);
1054 unsigned instances
= ((struct brw_tcs_prog_data
*) prog_data
)->instances
;
1056 brw_push_insn_state(p
);
1057 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1058 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1060 /* Zero the message header */
1061 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
1063 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1065 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
1066 brw_imm_ud(ivb
? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1068 /* Shift it up to bits 27:24. */
1069 brw_SHL(p
, m0_2
, get_element_ud(dst
, 2), brw_imm_ud(ivb
? 12 : 11));
1071 /* Set the Barrier Count and the enable bit */
1072 brw_OR(p
, m0_2
, m0_2
, brw_imm_ud(instances
<< 9 | (1 << 15)));
1074 brw_pop_insn_state(p
);
1078 generate_oword_dual_block_offsets(struct brw_codegen
*p
,
1080 struct brw_reg index
)
1082 int second_vertex_offset
;
1084 if (p
->devinfo
->gen
>= 6)
1085 second_vertex_offset
= 1;
1087 second_vertex_offset
= 16;
1089 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
1091 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1092 * M1.4 are used, and the rest are ignored.
1094 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
1095 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
1096 struct brw_reg index_0
= suboffset(vec1(index
), 0);
1097 struct brw_reg index_4
= suboffset(vec1(index
), 4);
1099 brw_push_insn_state(p
);
1100 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1101 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1103 brw_MOV(p
, m1_0
, index_0
);
1105 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1106 index_4
.ud
+= second_vertex_offset
;
1107 brw_MOV(p
, m1_4
, index_4
);
1109 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
1112 brw_pop_insn_state(p
);
1116 generate_unpack_flags(struct brw_codegen
*p
,
1119 brw_push_insn_state(p
);
1120 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1121 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1123 struct brw_reg flags
= brw_flag_reg(0, 0);
1124 struct brw_reg dst_0
= suboffset(vec1(dst
), 0);
1125 struct brw_reg dst_4
= suboffset(vec1(dst
), 4);
1127 brw_AND(p
, dst_0
, flags
, brw_imm_ud(0x0f));
1128 brw_AND(p
, dst_4
, flags
, brw_imm_ud(0xf0));
1129 brw_SHR(p
, dst_4
, dst_4
, brw_imm_ud(4));
1131 brw_pop_insn_state(p
);
1135 generate_scratch_read(struct brw_codegen
*p
,
1136 vec4_instruction
*inst
,
1138 struct brw_reg index
)
1140 const struct gen_device_info
*devinfo
= p
->devinfo
;
1141 struct brw_reg header
= brw_vec8_grf(0, 0);
1143 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1145 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
1150 if (devinfo
->gen
>= 6)
1151 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1152 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
1153 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1155 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1157 const unsigned target_cache
=
1158 devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
1159 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
1160 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
1162 /* Each of the 8 channel enables is considered for whether each
1165 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1166 brw_set_dest(p
, send
, dst
);
1167 brw_set_src0(p
, send
, header
);
1168 if (devinfo
->gen
< 6)
1169 brw_inst_set_cond_modifier(devinfo
, send
, inst
->base_mrf
);
1170 brw_set_dp_read_message(p
, send
,
1171 brw_scratch_surface_idx(p
),
1172 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1173 msg_type
, target_cache
,
1175 true, /* header_present */
1180 generate_scratch_write(struct brw_codegen
*p
,
1181 vec4_instruction
*inst
,
1184 struct brw_reg index
)
1186 const struct gen_device_info
*devinfo
= p
->devinfo
;
1187 const unsigned target_cache
=
1188 (devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
1189 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
1190 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
);
1191 struct brw_reg header
= brw_vec8_grf(0, 0);
1194 /* If the instruction is predicated, we'll predicate the send, not
1197 brw_set_default_predicate_control(p
, false);
1199 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1201 generate_oword_dual_block_offsets(p
, brw_message_reg(inst
->base_mrf
+ 1),
1205 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
1206 retype(src
, BRW_REGISTER_TYPE_D
));
1210 if (devinfo
->gen
>= 7)
1211 msg_type
= GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE
;
1212 else if (devinfo
->gen
== 6)
1213 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
1215 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
1217 brw_set_default_predicate_control(p
, inst
->predicate
);
1219 /* Pre-gen6, we have to specify write commits to ensure ordering
1220 * between reads and writes within a thread. Afterwards, that's
1221 * guaranteed and write commits only matter for inter-thread
1224 if (devinfo
->gen
>= 6) {
1225 write_commit
= false;
1227 /* The visitor set up our destination register to be g0. This
1228 * means that when the next read comes along, we will end up
1229 * reading from g0 and causing a block on the write commit. For
1230 * write-after-read, we are relying on the value of the previous
1231 * read being used (and thus blocking on completion) before our
1232 * write is executed. This means we have to be careful in
1233 * instruction scheduling to not violate this assumption.
1235 write_commit
= true;
1238 /* Each of the 8 channel enables is considered for whether each
1241 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1242 brw_set_dest(p
, send
, dst
);
1243 brw_set_src0(p
, send
, header
);
1244 if (devinfo
->gen
< 6)
1245 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
1246 brw_set_dp_write_message(p
, send
,
1247 brw_scratch_surface_idx(p
),
1248 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1252 true, /* header present */
1253 false, /* not a render target write */
1254 write_commit
, /* rlen */
1260 generate_pull_constant_load(struct brw_codegen
*p
,
1261 struct brw_vue_prog_data
*prog_data
,
1262 vec4_instruction
*inst
,
1264 struct brw_reg index
,
1265 struct brw_reg offset
)
1267 const struct gen_device_info
*devinfo
= p
->devinfo
;
1268 const unsigned target_cache
=
1269 (devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE
:
1270 BRW_DATAPORT_READ_TARGET_DATA_CACHE
);
1271 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1272 index
.type
== BRW_REGISTER_TYPE_UD
);
1273 uint32_t surf_index
= index
.ud
;
1275 struct brw_reg header
= brw_vec8_grf(0, 0);
1277 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1279 if (devinfo
->gen
>= 6) {
1280 if (offset
.file
== BRW_IMMEDIATE_VALUE
) {
1281 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1282 BRW_REGISTER_TYPE_D
),
1283 brw_imm_d(offset
.ud
>> 4));
1285 brw_SHR(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1286 BRW_REGISTER_TYPE_D
),
1287 offset
, brw_imm_d(4));
1290 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1),
1291 BRW_REGISTER_TYPE_D
),
1297 if (devinfo
->gen
>= 6)
1298 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1299 else if (devinfo
->gen
== 5 || devinfo
->is_g4x
)
1300 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1302 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1304 /* Each of the 8 channel enables is considered for whether each
1307 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1308 brw_set_dest(p
, send
, dst
);
1309 brw_set_src0(p
, send
, header
);
1310 if (devinfo
->gen
< 6)
1311 brw_inst_set_cond_modifier(p
->devinfo
, send
, inst
->base_mrf
);
1312 brw_set_dp_read_message(p
, send
,
1314 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1318 true, /* header_present */
1323 generate_get_buffer_size(struct brw_codegen
*p
,
1324 struct brw_vue_prog_data
*prog_data
,
1325 vec4_instruction
*inst
,
1328 struct brw_reg surf_index
)
1330 assert(p
->devinfo
->gen
>= 7);
1331 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
&&
1332 surf_index
.file
== BRW_IMMEDIATE_VALUE
);
1340 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
1341 1, /* response length */
1343 inst
->header_size
> 0,
1344 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1345 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
1347 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
1351 generate_pull_constant_load_gen7(struct brw_codegen
*p
,
1352 struct brw_vue_prog_data
*prog_data
,
1353 vec4_instruction
*inst
,
1355 struct brw_reg surf_index
,
1356 struct brw_reg offset
)
1358 assert(surf_index
.type
== BRW_REGISTER_TYPE_UD
);
1360 if (surf_index
.file
== BRW_IMMEDIATE_VALUE
) {
1362 brw_inst
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1363 brw_set_dest(p
, insn
, dst
);
1364 brw_set_src0(p
, insn
, offset
);
1365 brw_set_sampler_message(p
, insn
,
1367 0, /* LD message ignores sampler unit */
1368 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1371 inst
->header_size
!= 0,
1372 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1375 brw_mark_surface_used(&prog_data
->base
, surf_index
.ud
);
1379 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1381 brw_push_insn_state(p
);
1382 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1383 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1385 /* a0.0 = surf_index & 0xff */
1386 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1387 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1388 brw_set_dest(p
, insn_and
, addr
);
1389 brw_set_src0(p
, insn_and
, vec1(retype(surf_index
, BRW_REGISTER_TYPE_UD
)));
1390 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1392 brw_pop_insn_state(p
);
1394 /* dst = send(offset, a0.0 | <descriptor>) */
1395 brw_inst
*insn
= brw_send_indirect_message(
1396 p
, BRW_SFID_SAMPLER
, dst
, offset
, addr
, 0);
1397 brw_set_sampler_message(p
, insn
,
1400 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1403 inst
->header_size
!= 0,
1404 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1410 generate_set_simd4x2_header_gen9(struct brw_codegen
*p
,
1414 brw_push_insn_state(p
);
1415 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1417 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1418 brw_MOV(p
, vec8(dst
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1420 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1421 brw_MOV(p
, get_element_ud(dst
, 2),
1422 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1424 brw_pop_insn_state(p
);
1428 generate_mov_indirect(struct brw_codegen
*p
,
1430 struct brw_reg dst
, struct brw_reg reg
,
1431 struct brw_reg indirect
)
1433 assert(indirect
.type
== BRW_REGISTER_TYPE_UD
);
1434 assert(p
->devinfo
->gen
>= 6);
1436 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
* (REG_SIZE
/ 2);
1438 /* This instruction acts in align1 mode */
1439 assert(dst
.writemask
== WRITEMASK_XYZW
);
1441 if (indirect
.file
== BRW_IMMEDIATE_VALUE
) {
1442 imm_byte_offset
+= indirect
.ud
;
1444 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
1445 reg
.subnr
= (imm_byte_offset
/ (REG_SIZE
/ 2)) % 2;
1446 unsigned shift
= (imm_byte_offset
/ 4) % 4;
1447 reg
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
1449 brw_MOV(p
, dst
, reg
);
1451 brw_push_insn_state(p
);
1452 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1453 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1455 struct brw_reg addr
= vec8(brw_address_reg(0));
1457 /* We need to move the indirect value into the address register. In
1458 * order to make things make some sense, we want to respect at least the
1459 * X component of the swizzle. In order to do that, we need to convert
1460 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1462 assert(brw_is_single_value_swizzle(indirect
.swizzle
));
1463 indirect
.subnr
= (indirect
.subnr
* 4 + BRW_GET_SWZ(indirect
.swizzle
, 0));
1465 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1466 * the indirect and splat it out to all four channels of the given half
1469 indirect
.subnr
*= 2;
1470 indirect
= stride(retype(indirect
, BRW_REGISTER_TYPE_UW
), 8, 4, 0);
1471 brw_ADD(p
, addr
, indirect
, brw_imm_uw(imm_byte_offset
));
1473 /* Now we need to incorporate the swizzle from the source register */
1474 if (reg
.swizzle
!= BRW_SWIZZLE_XXXX
) {
1475 uint32_t uv_swiz
= BRW_GET_SWZ(reg
.swizzle
, 0) << 2 |
1476 BRW_GET_SWZ(reg
.swizzle
, 1) << 6 |
1477 BRW_GET_SWZ(reg
.swizzle
, 2) << 10 |
1478 BRW_GET_SWZ(reg
.swizzle
, 3) << 14;
1479 uv_swiz
|= uv_swiz
<< 16;
1481 brw_ADD(p
, addr
, addr
, brw_imm_uv(uv_swiz
));
1484 brw_MOV(p
, dst
, retype(brw_VxH_indirect(0, 0), reg
.type
));
1486 brw_pop_insn_state(p
);
1491 generate_code(struct brw_codegen
*p
,
1492 const struct brw_compiler
*compiler
,
1494 const nir_shader
*nir
,
1495 struct brw_vue_prog_data
*prog_data
,
1496 const struct cfg_t
*cfg
)
1498 const struct gen_device_info
*devinfo
= p
->devinfo
;
1499 const char *stage_abbrev
= _mesa_shader_stage_to_abbrev(nir
->info
.stage
);
1500 bool debug_flag
= INTEL_DEBUG
&
1501 intel_debug_flag_for_shader_stage(nir
->info
.stage
);
1502 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1503 int spill_count
= 0, fill_count
= 0;
1506 foreach_block_and_inst (block
, vec4_instruction
, inst
, cfg
) {
1507 struct brw_reg src
[3], dst
;
1509 if (unlikely(debug_flag
))
1510 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1512 for (unsigned int i
= 0; i
< 3; i
++) {
1513 src
[i
] = inst
->src
[i
].as_brw_reg();
1515 dst
= inst
->dst
.as_brw_reg();
1517 brw_set_default_predicate_control(p
, inst
->predicate
);
1518 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1519 brw_set_default_flag_reg(p
, inst
->flag_subreg
/ 2, inst
->flag_subreg
% 2);
1520 brw_set_default_saturate(p
, inst
->saturate
);
1521 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1522 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1524 assert(inst
->group
% inst
->exec_size
== 0);
1525 assert(inst
->group
% 4 == 0);
1527 /* There are some instructions where the destination is 64-bit
1528 * but we retype it to a smaller type. In that case, we cannot
1529 * double the exec_size.
1531 const bool is_df
= (get_exec_type_size(inst
) == 8 ||
1532 inst
->dst
.type
== BRW_REGISTER_TYPE_DF
) &&
1533 inst
->opcode
!= VEC4_OPCODE_PICK_LOW_32BIT
&&
1534 inst
->opcode
!= VEC4_OPCODE_PICK_HIGH_32BIT
&&
1535 inst
->opcode
!= VEC4_OPCODE_SET_LOW_32BIT
&&
1536 inst
->opcode
!= VEC4_OPCODE_SET_HIGH_32BIT
;
1538 unsigned exec_size
= inst
->exec_size
;
1539 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&& is_df
)
1542 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1544 if (!inst
->force_writemask_all
)
1545 brw_set_default_group(p
, inst
->group
);
1547 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1548 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1550 unsigned pre_emit_nr_insn
= p
->nr_insn
;
1552 switch (inst
->opcode
) {
1553 case VEC4_OPCODE_UNPACK_UNIFORM
:
1554 case BRW_OPCODE_MOV
:
1555 brw_MOV(p
, dst
, src
[0]);
1557 case BRW_OPCODE_ADD
:
1558 brw_ADD(p
, dst
, src
[0], src
[1]);
1560 case BRW_OPCODE_MUL
:
1561 brw_MUL(p
, dst
, src
[0], src
[1]);
1563 case BRW_OPCODE_MACH
:
1564 brw_MACH(p
, dst
, src
[0], src
[1]);
1567 case BRW_OPCODE_MAD
:
1568 assert(devinfo
->gen
>= 6);
1569 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1572 case BRW_OPCODE_FRC
:
1573 brw_FRC(p
, dst
, src
[0]);
1575 case BRW_OPCODE_RNDD
:
1576 brw_RNDD(p
, dst
, src
[0]);
1578 case BRW_OPCODE_RNDE
:
1579 brw_RNDE(p
, dst
, src
[0]);
1581 case BRW_OPCODE_RNDZ
:
1582 brw_RNDZ(p
, dst
, src
[0]);
1585 case BRW_OPCODE_AND
:
1586 brw_AND(p
, dst
, src
[0], src
[1]);
1589 brw_OR(p
, dst
, src
[0], src
[1]);
1591 case BRW_OPCODE_XOR
:
1592 brw_XOR(p
, dst
, src
[0], src
[1]);
1594 case BRW_OPCODE_NOT
:
1595 brw_NOT(p
, dst
, src
[0]);
1597 case BRW_OPCODE_ASR
:
1598 brw_ASR(p
, dst
, src
[0], src
[1]);
1600 case BRW_OPCODE_SHR
:
1601 brw_SHR(p
, dst
, src
[0], src
[1]);
1603 case BRW_OPCODE_SHL
:
1604 brw_SHL(p
, dst
, src
[0], src
[1]);
1607 case BRW_OPCODE_CMP
:
1608 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1610 case BRW_OPCODE_SEL
:
1611 brw_SEL(p
, dst
, src
[0], src
[1]);
1614 case BRW_OPCODE_DPH
:
1615 brw_DPH(p
, dst
, src
[0], src
[1]);
1618 case BRW_OPCODE_DP4
:
1619 brw_DP4(p
, dst
, src
[0], src
[1]);
1622 case BRW_OPCODE_DP3
:
1623 brw_DP3(p
, dst
, src
[0], src
[1]);
1626 case BRW_OPCODE_DP2
:
1627 brw_DP2(p
, dst
, src
[0], src
[1]);
1630 case BRW_OPCODE_F32TO16
:
1631 assert(devinfo
->gen
>= 7);
1632 brw_F32TO16(p
, dst
, src
[0]);
1635 case BRW_OPCODE_F16TO32
:
1636 assert(devinfo
->gen
>= 7);
1637 brw_F16TO32(p
, dst
, src
[0]);
1640 case BRW_OPCODE_LRP
:
1641 assert(devinfo
->gen
>= 6);
1642 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1645 case BRW_OPCODE_BFREV
:
1646 assert(devinfo
->gen
>= 7);
1647 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1648 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1650 case BRW_OPCODE_FBH
:
1651 assert(devinfo
->gen
>= 7);
1652 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1654 case BRW_OPCODE_FBL
:
1655 assert(devinfo
->gen
>= 7);
1656 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1657 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1659 case BRW_OPCODE_LZD
:
1660 brw_LZD(p
, dst
, src
[0]);
1662 case BRW_OPCODE_CBIT
:
1663 assert(devinfo
->gen
>= 7);
1664 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1665 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1667 case BRW_OPCODE_ADDC
:
1668 assert(devinfo
->gen
>= 7);
1669 brw_ADDC(p
, dst
, src
[0], src
[1]);
1671 case BRW_OPCODE_SUBB
:
1672 assert(devinfo
->gen
>= 7);
1673 brw_SUBB(p
, dst
, src
[0], src
[1]);
1675 case BRW_OPCODE_MAC
:
1676 brw_MAC(p
, dst
, src
[0], src
[1]);
1679 case BRW_OPCODE_BFE
:
1680 assert(devinfo
->gen
>= 7);
1681 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1684 case BRW_OPCODE_BFI1
:
1685 assert(devinfo
->gen
>= 7);
1686 brw_BFI1(p
, dst
, src
[0], src
[1]);
1688 case BRW_OPCODE_BFI2
:
1689 assert(devinfo
->gen
>= 7);
1690 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1694 if (!inst
->src
[0].is_null()) {
1695 /* The instruction has an embedded compare (only allowed on gen6) */
1696 assert(devinfo
->gen
== 6);
1697 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1699 brw_inst
*if_inst
= brw_IF(p
, BRW_EXECUTE_8
);
1700 brw_inst_set_pred_control(p
->devinfo
, if_inst
, inst
->predicate
);
1704 case BRW_OPCODE_ELSE
:
1707 case BRW_OPCODE_ENDIF
:
1712 brw_DO(p
, BRW_EXECUTE_8
);
1715 case BRW_OPCODE_BREAK
:
1717 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1719 case BRW_OPCODE_CONTINUE
:
1721 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
1724 case BRW_OPCODE_WHILE
:
1729 case SHADER_OPCODE_RCP
:
1730 case SHADER_OPCODE_RSQ
:
1731 case SHADER_OPCODE_SQRT
:
1732 case SHADER_OPCODE_EXP2
:
1733 case SHADER_OPCODE_LOG2
:
1734 case SHADER_OPCODE_SIN
:
1735 case SHADER_OPCODE_COS
:
1736 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1737 if (devinfo
->gen
>= 7) {
1738 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
1740 } else if (devinfo
->gen
== 6) {
1741 generate_math_gen6(p
, inst
, dst
, src
[0], brw_null_reg());
1743 generate_math1_gen4(p
, inst
, dst
, src
[0]);
1747 case SHADER_OPCODE_POW
:
1748 case SHADER_OPCODE_INT_QUOTIENT
:
1749 case SHADER_OPCODE_INT_REMAINDER
:
1750 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1751 if (devinfo
->gen
>= 7) {
1752 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1753 } else if (devinfo
->gen
== 6) {
1754 generate_math_gen6(p
, inst
, dst
, src
[0], src
[1]);
1756 generate_math2_gen4(p
, inst
, dst
, src
[0], src
[1]);
1760 case SHADER_OPCODE_TEX
:
1761 case SHADER_OPCODE_TXD
:
1762 case SHADER_OPCODE_TXF
:
1763 case SHADER_OPCODE_TXF_CMS
:
1764 case SHADER_OPCODE_TXF_CMS_W
:
1765 case SHADER_OPCODE_TXF_MCS
:
1766 case SHADER_OPCODE_TXL
:
1767 case SHADER_OPCODE_TXS
:
1768 case SHADER_OPCODE_TG4
:
1769 case SHADER_OPCODE_TG4_OFFSET
:
1770 case SHADER_OPCODE_SAMPLEINFO
:
1771 generate_tex(p
, prog_data
, nir
->info
.stage
,
1772 inst
, dst
, src
[0], src
[1], src
[2]);
1775 case SHADER_OPCODE_GET_BUFFER_SIZE
:
1776 generate_get_buffer_size(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1779 case VS_OPCODE_URB_WRITE
:
1780 generate_vs_urb_write(p
, inst
);
1783 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1784 generate_scratch_read(p
, inst
, dst
, src
[0]);
1788 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1789 generate_scratch_write(p
, inst
, dst
, src
[0], src
[1]);
1793 case VS_OPCODE_PULL_CONSTANT_LOAD
:
1794 generate_pull_constant_load(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1797 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
1798 generate_pull_constant_load_gen7(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1801 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
1802 generate_set_simd4x2_header_gen9(p
, inst
, dst
);
1805 case GS_OPCODE_URB_WRITE
:
1806 generate_gs_urb_write(p
, inst
);
1809 case GS_OPCODE_URB_WRITE_ALLOCATE
:
1810 generate_gs_urb_write_allocate(p
, inst
);
1813 case GS_OPCODE_SVB_WRITE
:
1814 generate_gs_svb_write(p
, prog_data
, inst
, dst
, src
[0], src
[1]);
1817 case GS_OPCODE_SVB_SET_DST_INDEX
:
1818 generate_gs_svb_set_destination_index(p
, inst
, dst
, src
[0]);
1821 case GS_OPCODE_THREAD_END
:
1822 generate_gs_thread_end(p
, inst
);
1825 case GS_OPCODE_SET_WRITE_OFFSET
:
1826 generate_gs_set_write_offset(p
, dst
, src
[0], src
[1]);
1829 case GS_OPCODE_SET_VERTEX_COUNT
:
1830 generate_gs_set_vertex_count(p
, dst
, src
[0]);
1833 case GS_OPCODE_FF_SYNC
:
1834 generate_gs_ff_sync(p
, inst
, dst
, src
[0], src
[1]);
1837 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES
:
1838 generate_gs_ff_sync_set_primitives(p
, dst
, src
[0], src
[1], src
[2]);
1841 case GS_OPCODE_SET_PRIMITIVE_ID
:
1842 generate_gs_set_primitive_id(p
, dst
);
1845 case GS_OPCODE_SET_DWORD_2
:
1846 generate_gs_set_dword_2(p
, dst
, src
[0]);
1849 case GS_OPCODE_PREPARE_CHANNEL_MASKS
:
1850 generate_gs_prepare_channel_masks(p
, dst
);
1853 case GS_OPCODE_SET_CHANNEL_MASKS
:
1854 generate_gs_set_channel_masks(p
, dst
, src
[0]);
1857 case GS_OPCODE_GET_INSTANCE_ID
:
1858 generate_gs_get_instance_id(p
, dst
);
1861 case SHADER_OPCODE_SHADER_TIME_ADD
:
1862 brw_shader_time_add(p
, src
[0],
1863 prog_data
->base
.binding_table
.shader_time_start
);
1864 brw_mark_surface_used(&prog_data
->base
,
1865 prog_data
->base
.binding_table
.shader_time_start
);
1868 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1869 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1870 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1871 !inst
->dst
.is_null(), inst
->header_size
);
1874 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1875 assert(!inst
->header_size
);
1876 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1877 brw_untyped_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1881 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1882 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1883 brw_untyped_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1884 src
[2].ud
, inst
->header_size
);
1887 case SHADER_OPCODE_TYPED_ATOMIC
:
1888 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1889 brw_typed_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
, inst
->mlen
,
1890 !inst
->dst
.is_null(), inst
->header_size
);
1893 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1894 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1895 brw_typed_surface_read(p
, dst
, src
[0], src
[1], inst
->mlen
,
1896 src
[2].ud
, inst
->header_size
);
1899 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1900 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
1901 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
,
1902 src
[2].ud
, inst
->header_size
);
1905 case SHADER_OPCODE_MEMORY_FENCE
:
1906 brw_memory_fence(p
, dst
, BRW_OPCODE_SEND
);
1909 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
1910 const struct brw_reg mask
=
1911 brw_stage_has_packed_dispatch(devinfo
, nir
->info
.stage
,
1912 &prog_data
->base
) ? brw_imm_ud(~0u) :
1914 brw_find_live_channel(p
, dst
, mask
);
1918 case SHADER_OPCODE_BROADCAST
:
1919 assert(inst
->force_writemask_all
);
1920 brw_broadcast(p
, dst
, src
[0], src
[1]);
1923 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2
:
1924 generate_unpack_flags(p
, dst
);
1927 case VEC4_OPCODE_MOV_BYTES
: {
1928 /* Moves the low byte from each channel, using an Align1 access mode
1929 * and a <4,1,0> source region.
1931 assert(src
[0].type
== BRW_REGISTER_TYPE_UB
||
1932 src
[0].type
== BRW_REGISTER_TYPE_B
);
1934 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1935 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
1936 src
[0].width
= BRW_WIDTH_1
;
1937 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
1938 brw_MOV(p
, dst
, src
[0]);
1939 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1943 case VEC4_OPCODE_DOUBLE_TO_F32
:
1944 case VEC4_OPCODE_DOUBLE_TO_D32
:
1945 case VEC4_OPCODE_DOUBLE_TO_U32
: {
1946 assert(type_sz(src
[0].type
) == 8);
1947 assert(type_sz(dst
.type
) == 8);
1949 brw_reg_type dst_type
;
1951 switch (inst
->opcode
) {
1952 case VEC4_OPCODE_DOUBLE_TO_F32
:
1953 dst_type
= BRW_REGISTER_TYPE_F
;
1955 case VEC4_OPCODE_DOUBLE_TO_D32
:
1956 dst_type
= BRW_REGISTER_TYPE_D
;
1958 case VEC4_OPCODE_DOUBLE_TO_U32
:
1959 dst_type
= BRW_REGISTER_TYPE_UD
;
1962 unreachable("Not supported conversion");
1964 dst
= retype(dst
, dst_type
);
1966 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1968 /* When converting from DF->F, we set destination's stride as 2 as an
1969 * aligment requirement. But in IVB/BYT, each DF implicitly writes
1970 * two floats, being the first one the converted value. So we don't
1971 * need to explicitly set stride 2, but 1.
1973 struct brw_reg spread_dst
;
1974 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
)
1975 spread_dst
= stride(dst
, 8, 4, 1);
1977 spread_dst
= stride(dst
, 8, 4, 2);
1979 brw_MOV(p
, spread_dst
, src
[0]);
1981 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1985 case VEC4_OPCODE_TO_DOUBLE
: {
1986 assert(type_sz(src
[0].type
) == 4);
1987 assert(type_sz(dst
.type
) == 8);
1989 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1991 brw_MOV(p
, dst
, src
[0]);
1993 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1997 case VEC4_OPCODE_PICK_LOW_32BIT
:
1998 case VEC4_OPCODE_PICK_HIGH_32BIT
: {
1999 /* Stores the low/high 32-bit of each 64-bit element in src[0] into
2000 * dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
2002 assert(type_sz(src
[0].type
) == 8);
2003 assert(type_sz(dst
.type
) == 4);
2005 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2007 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
2008 dst
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
2010 src
[0] = retype(src
[0], BRW_REGISTER_TYPE_UD
);
2011 if (inst
->opcode
== VEC4_OPCODE_PICK_HIGH_32BIT
)
2012 src
[0] = suboffset(src
[0], 1);
2013 src
[0] = spread(src
[0], 2);
2014 brw_MOV(p
, dst
, src
[0]);
2016 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2020 case VEC4_OPCODE_SET_LOW_32BIT
:
2021 case VEC4_OPCODE_SET_HIGH_32BIT
: {
2022 /* Reads consecutive 32-bit elements from src[0] and writes
2023 * them to the low/high 32-bit of each 64-bit element in dst.
2025 assert(type_sz(src
[0].type
) == 4);
2026 assert(type_sz(dst
.type
) == 8);
2028 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2030 dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
2031 if (inst
->opcode
== VEC4_OPCODE_SET_HIGH_32BIT
)
2032 dst
= suboffset(dst
, 1);
2033 dst
.hstride
= BRW_HORIZONTAL_STRIDE_2
;
2035 src
[0] = retype(src
[0], BRW_REGISTER_TYPE_UD
);
2036 brw_MOV(p
, dst
, src
[0]);
2038 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2042 case VEC4_OPCODE_PACK_BYTES
: {
2045 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
2047 * but destinations' only regioning is horizontal stride, so instead we
2048 * have to use two instructions:
2050 * mov(4) dst<1>:UB src<4,1,0>:UB
2051 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
2053 * where they pack the four bytes from the low and high four DW.
2055 assert(_mesa_is_pow_two(dst
.writemask
) &&
2056 dst
.writemask
!= 0);
2057 unsigned offset
= __builtin_ctz(dst
.writemask
);
2059 dst
.type
= BRW_REGISTER_TYPE_UB
;
2061 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2063 src
[0].type
= BRW_REGISTER_TYPE_UB
;
2064 src
[0].vstride
= BRW_VERTICAL_STRIDE_4
;
2065 src
[0].width
= BRW_WIDTH_1
;
2066 src
[0].hstride
= BRW_HORIZONTAL_STRIDE_0
;
2067 dst
.subnr
= offset
* 4;
2068 struct brw_inst
*insn
= brw_MOV(p
, dst
, src
[0]);
2069 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
2070 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, true);
2071 brw_inst_set_no_dd_check(p
->devinfo
, insn
, inst
->no_dd_check
);
2074 dst
.subnr
= 16 + offset
* 4;
2075 insn
= brw_MOV(p
, dst
, src
[0]);
2076 brw_inst_set_exec_size(p
->devinfo
, insn
, BRW_EXECUTE_4
);
2077 brw_inst_set_no_dd_clear(p
->devinfo
, insn
, inst
->no_dd_clear
);
2078 brw_inst_set_no_dd_check(p
->devinfo
, insn
, true);
2080 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2084 case TCS_OPCODE_URB_WRITE
:
2085 generate_tcs_urb_write(p
, inst
, src
[0]);
2088 case VEC4_OPCODE_URB_READ
:
2089 generate_vec4_urb_read(p
, inst
, dst
, src
[0]);
2092 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
2093 generate_tcs_input_urb_offsets(p
, dst
, src
[0], src
[1]);
2096 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
2097 generate_tcs_output_urb_offsets(p
, dst
, src
[0], src
[1]);
2100 case TCS_OPCODE_GET_INSTANCE_ID
:
2101 generate_tcs_get_instance_id(p
, dst
);
2104 case TCS_OPCODE_GET_PRIMITIVE_ID
:
2105 generate_tcs_get_primitive_id(p
, dst
);
2108 case TCS_OPCODE_CREATE_BARRIER_HEADER
:
2109 generate_tcs_create_barrier_header(p
, prog_data
, dst
);
2112 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
2113 generate_tes_create_input_read_header(p
, dst
);
2116 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
2117 generate_tes_add_indirect_urb_offset(p
, dst
, src
[0], src
[1]);
2120 case TES_OPCODE_GET_PRIMITIVE_ID
:
2121 generate_tes_get_primitive_id(p
, dst
);
2124 case TCS_OPCODE_SRC0_010_IS_ZERO
:
2125 /* If src_reg had stride like fs_reg, we wouldn't need this. */
2126 brw_MOV(p
, brw_null_reg(), stride(src
[0], 0, 1, 0));
2129 case TCS_OPCODE_RELEASE_INPUT
:
2130 generate_tcs_release_input(p
, dst
, src
[0], src
[1]);
2133 case TCS_OPCODE_THREAD_END
:
2134 generate_tcs_thread_end(p
, inst
);
2137 case SHADER_OPCODE_BARRIER
:
2138 brw_barrier(p
, src
[0]);
2142 case SHADER_OPCODE_MOV_INDIRECT
:
2143 generate_mov_indirect(p
, inst
, dst
, src
[0], src
[1]);
2146 case BRW_OPCODE_DIM
:
2147 assert(devinfo
->is_haswell
);
2148 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2149 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2150 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2154 unreachable("Unsupported opcode");
2157 if (inst
->opcode
== VEC4_OPCODE_PACK_BYTES
) {
2158 /* Handled dependency hints in the generator. */
2160 assert(!inst
->conditional_mod
);
2161 } else if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2162 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
2163 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2164 "emitting more than 1 instruction");
2166 brw_inst
*last
= &p
->store
[pre_emit_nr_insn
];
2168 if (inst
->conditional_mod
)
2169 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2170 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2171 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2175 brw_set_uip_jip(p
, 0);
2177 /* end of program sentinel */
2178 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2183 if (unlikely(debug_flag
))
2185 brw_validate_instructions(devinfo
, p
->store
,
2186 0, p
->next_insn_offset
,
2189 int before_size
= p
->next_insn_offset
;
2190 brw_compact_instructions(p
, 0, disasm_info
);
2191 int after_size
= p
->next_insn_offset
;
2193 if (unlikely(debug_flag
)) {
2194 fprintf(stderr
, "Native code for %s %s shader %s:\n",
2195 nir
->info
.label
? nir
->info
.label
: "unnamed",
2196 _mesa_shader_stage_to_string(nir
->info
.stage
), nir
->info
.name
);
2198 fprintf(stderr
, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2199 "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
2200 stage_abbrev
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2201 spill_count
, fill_count
, before_size
, after_size
,
2202 100.0f
* (before_size
- after_size
) / before_size
);
2204 dump_assembly(p
->store
, disasm_info
);
2206 ralloc_free(disasm_info
);
2209 compiler
->shader_debug_log(log_data
,
2210 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2211 "%d:%d spills:fills, compacted %d to %d bytes.",
2212 stage_abbrev
, before_size
/ 16,
2213 loop_count
, cfg
->cycle_count
, spill_count
,
2214 fill_count
, before_size
, after_size
);
2218 extern "C" const unsigned *
2219 brw_vec4_generate_assembly(const struct brw_compiler
*compiler
,
2222 const nir_shader
*nir
,
2223 struct brw_vue_prog_data
*prog_data
,
2224 const struct cfg_t
*cfg
)
2226 struct brw_codegen
*p
= rzalloc(mem_ctx
, struct brw_codegen
);
2227 brw_init_codegen(compiler
->devinfo
, p
, mem_ctx
);
2228 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2230 generate_code(p
, compiler
, log_data
, nir
, prog_data
, cfg
);
2232 return brw_get_program(p
, &prog_data
->base
.program_size
);