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intel/eu: Fix up various type conversions in brw_eu.c that are illegal C++.
[mesa.git] / src / intel / compiler / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "dev/gen_debug.h"
27 #include "util/mesa-sha1.h"
28
29 using namespace brw;
30
31 static void
32 generate_math1_gen4(struct brw_codegen *p,
33 vec4_instruction *inst,
34 struct brw_reg dst,
35 struct brw_reg src)
36 {
37 gen4_math(p,
38 dst,
39 brw_math_function(inst->opcode),
40 inst->base_mrf,
41 src,
42 BRW_MATH_PRECISION_FULL);
43 }
44
45 static void
46 check_gen6_math_src_arg(struct brw_reg src)
47 {
48 /* Source swizzles are ignored. */
49 assert(!src.abs);
50 assert(!src.negate);
51 assert(src.swizzle == BRW_SWIZZLE_XYZW);
52 }
53
54 static void
55 generate_math_gen6(struct brw_codegen *p,
56 vec4_instruction *inst,
57 struct brw_reg dst,
58 struct brw_reg src0,
59 struct brw_reg src1)
60 {
61 /* Can't do writemask because math can't be align16. */
62 assert(dst.writemask == WRITEMASK_XYZW);
63 /* Source swizzles are ignored. */
64 check_gen6_math_src_arg(src0);
65 if (src1.file == BRW_GENERAL_REGISTER_FILE)
66 check_gen6_math_src_arg(src1);
67
68 brw_set_default_access_mode(p, BRW_ALIGN_1);
69 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
70 brw_set_default_access_mode(p, BRW_ALIGN_16);
71 }
72
73 static void
74 generate_math2_gen4(struct brw_codegen *p,
75 vec4_instruction *inst,
76 struct brw_reg dst,
77 struct brw_reg src0,
78 struct brw_reg src1)
79 {
80 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
81 * "Message Payload":
82 *
83 * "Operand0[7]. For the INT DIV functions, this operand is the
84 * denominator."
85 * ...
86 * "Operand1[7]. For the INT DIV functions, this operand is the
87 * numerator."
88 */
89 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
90 struct brw_reg &op0 = is_int_div ? src1 : src0;
91 struct brw_reg &op1 = is_int_div ? src0 : src1;
92
93 brw_push_insn_state(p);
94 brw_set_default_saturate(p, false);
95 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
96 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
97 brw_pop_insn_state(p);
98
99 gen4_math(p,
100 dst,
101 brw_math_function(inst->opcode),
102 inst->base_mrf,
103 op0,
104 BRW_MATH_PRECISION_FULL);
105 }
106
107 static void
108 generate_tex(struct brw_codegen *p,
109 struct brw_vue_prog_data *prog_data,
110 gl_shader_stage stage,
111 vec4_instruction *inst,
112 struct brw_reg dst,
113 struct brw_reg src,
114 struct brw_reg surface_index,
115 struct brw_reg sampler_index)
116 {
117 const struct gen_device_info *devinfo = p->devinfo;
118 int msg_type = -1;
119
120 if (devinfo->gen >= 5) {
121 switch (inst->opcode) {
122 case SHADER_OPCODE_TEX:
123 case SHADER_OPCODE_TXL:
124 if (inst->shadow_compare) {
125 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
126 } else {
127 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
128 }
129 break;
130 case SHADER_OPCODE_TXD:
131 if (inst->shadow_compare) {
132 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
133 assert(devinfo->gen >= 8 || devinfo->is_haswell);
134 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
135 } else {
136 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
137 }
138 break;
139 case SHADER_OPCODE_TXF:
140 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
141 break;
142 case SHADER_OPCODE_TXF_CMS_W:
143 assert(devinfo->gen >= 9);
144 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
145 break;
146 case SHADER_OPCODE_TXF_CMS:
147 if (devinfo->gen >= 7)
148 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
149 else
150 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
151 break;
152 case SHADER_OPCODE_TXF_MCS:
153 assert(devinfo->gen >= 7);
154 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
155 break;
156 case SHADER_OPCODE_TXS:
157 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
158 break;
159 case SHADER_OPCODE_TG4:
160 if (inst->shadow_compare) {
161 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
162 } else {
163 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
164 }
165 break;
166 case SHADER_OPCODE_TG4_OFFSET:
167 if (inst->shadow_compare) {
168 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
169 } else {
170 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
171 }
172 break;
173 case SHADER_OPCODE_SAMPLEINFO:
174 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
175 break;
176 default:
177 unreachable("should not get here: invalid vec4 texture opcode");
178 }
179 } else {
180 switch (inst->opcode) {
181 case SHADER_OPCODE_TEX:
182 case SHADER_OPCODE_TXL:
183 if (inst->shadow_compare) {
184 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
185 assert(inst->mlen == 3);
186 } else {
187 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
188 assert(inst->mlen == 2);
189 }
190 break;
191 case SHADER_OPCODE_TXD:
192 /* There is no sample_d_c message; comparisons are done manually. */
193 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
194 assert(inst->mlen == 4);
195 break;
196 case SHADER_OPCODE_TXF:
197 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
198 assert(inst->mlen == 2);
199 break;
200 case SHADER_OPCODE_TXS:
201 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
202 assert(inst->mlen == 2);
203 break;
204 default:
205 unreachable("should not get here: invalid vec4 texture opcode");
206 }
207 }
208
209 assert(msg_type != -1);
210
211 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
212
213 /* Load the message header if present. If there's a texture offset, we need
214 * to set it up explicitly and load the offset bitfield. Otherwise, we can
215 * use an implied move from g0 to the first message register.
216 */
217 if (inst->header_size != 0) {
218 if (devinfo->gen < 6 && !inst->offset) {
219 /* Set up an implied move from g0 to the MRF. */
220 src = brw_vec8_grf(0, 0);
221 } else {
222 struct brw_reg header =
223 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
224 uint32_t dw2 = 0;
225
226 /* Explicitly set up the message header by copying g0 to the MRF. */
227 brw_push_insn_state(p);
228 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
229 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
230
231 brw_set_default_access_mode(p, BRW_ALIGN_1);
232
233 if (inst->offset)
234 /* Set the texel offset bits in DWord 2. */
235 dw2 = inst->offset;
236
237 if (devinfo->gen >= 9)
238 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
239 * based on bit 22 in the header.
240 */
241 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
242
243 /* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
244 * so header0.2 is 0 when g0 is copied. The HS and GS stages do
245 * not, so we must set to to 0 to avoid setting undesirable bits
246 * in the message header.
247 */
248 if (dw2 ||
249 stage == MESA_SHADER_TESS_CTRL ||
250 stage == MESA_SHADER_GEOMETRY) {
251 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
252 }
253
254 brw_adjust_sampler_state_pointer(p, header, sampler_index);
255 brw_pop_insn_state(p);
256 }
257 }
258
259 uint32_t return_format;
260
261 switch (dst.type) {
262 case BRW_REGISTER_TYPE_D:
263 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
264 break;
265 case BRW_REGISTER_TYPE_UD:
266 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
267 break;
268 default:
269 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
270 break;
271 }
272
273 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
274 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
275 ? prog_data->base.binding_table.gather_texture_start
276 : prog_data->base.binding_table.texture_start;
277
278 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
279 sampler_index.file == BRW_IMMEDIATE_VALUE) {
280 uint32_t surface = surface_index.ud;
281 uint32_t sampler = sampler_index.ud;
282
283 brw_SAMPLE(p,
284 dst,
285 inst->base_mrf,
286 src,
287 surface + base_binding_table_index,
288 sampler % 16,
289 msg_type,
290 1, /* response length */
291 inst->mlen,
292 inst->header_size != 0,
293 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
294 return_format);
295 } else {
296 /* Non-constant sampler index. */
297
298 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
299 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
300 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
301
302 brw_push_insn_state(p);
303 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
304 brw_set_default_access_mode(p, BRW_ALIGN_1);
305
306 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
307 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
308 } else {
309 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
310 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
311 } else {
312 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
313 brw_OR(p, addr, addr, surface_reg);
314 }
315 }
316 if (base_binding_table_index)
317 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
318 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
319
320 brw_pop_insn_state(p);
321
322 if (inst->base_mrf != -1)
323 gen6_resolve_implied_move(p, &src, inst->base_mrf);
324
325 /* dst = send(offset, a0.0 | <descriptor>) */
326 brw_send_indirect_message(
327 p, BRW_SFID_SAMPLER, dst, src, addr,
328 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
329 brw_sampler_desc(devinfo,
330 0 /* surface */,
331 0 /* sampler */,
332 msg_type,
333 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
334 return_format),
335 false /* EOT */);
336
337 /* visitor knows more than we do about the surface limit required,
338 * so has already done marking.
339 */
340 }
341 }
342
343 static void
344 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
345 {
346 brw_urb_WRITE(p,
347 brw_null_reg(), /* dest */
348 inst->base_mrf, /* starting mrf reg nr */
349 brw_vec8_grf(0, 0), /* src */
350 inst->urb_write_flags,
351 inst->mlen,
352 0, /* response len */
353 inst->offset, /* urb destination offset */
354 BRW_URB_SWIZZLE_INTERLEAVE);
355 }
356
357 static void
358 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
359 {
360 struct brw_reg src = brw_message_reg(inst->base_mrf);
361 brw_urb_WRITE(p,
362 brw_null_reg(), /* dest */
363 inst->base_mrf, /* starting mrf reg nr */
364 src,
365 inst->urb_write_flags,
366 inst->mlen,
367 0, /* response len */
368 inst->offset, /* urb destination offset */
369 BRW_URB_SWIZZLE_INTERLEAVE);
370 }
371
372 static void
373 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
374 {
375 struct brw_reg src = brw_message_reg(inst->base_mrf);
376
377 /* We pass the temporary passed in src0 as the writeback register */
378 brw_urb_WRITE(p,
379 inst->src[0].as_brw_reg(), /* dest */
380 inst->base_mrf, /* starting mrf reg nr */
381 src,
382 BRW_URB_WRITE_ALLOCATE_COMPLETE,
383 inst->mlen,
384 1, /* response len */
385 inst->offset, /* urb destination offset */
386 BRW_URB_SWIZZLE_INTERLEAVE);
387
388 /* Now put allocated urb handle in dst.0 */
389 brw_push_insn_state(p);
390 brw_set_default_access_mode(p, BRW_ALIGN_1);
391 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
392 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
393 get_element_ud(inst->src[0].as_brw_reg(), 0));
394 brw_pop_insn_state(p);
395 }
396
397 static void
398 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
399 {
400 struct brw_reg src = brw_message_reg(inst->base_mrf);
401 brw_urb_WRITE(p,
402 brw_null_reg(), /* dest */
403 inst->base_mrf, /* starting mrf reg nr */
404 src,
405 BRW_URB_WRITE_EOT | inst->urb_write_flags,
406 inst->mlen,
407 0, /* response len */
408 0, /* urb destination offset */
409 BRW_URB_SWIZZLE_INTERLEAVE);
410 }
411
412 static void
413 generate_gs_set_write_offset(struct brw_codegen *p,
414 struct brw_reg dst,
415 struct brw_reg src0,
416 struct brw_reg src1)
417 {
418 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
419 * Header: M0.3):
420 *
421 * Slot 0 Offset. This field, after adding to the Global Offset field
422 * in the message descriptor, specifies the offset (in 256-bit units)
423 * from the start of the URB entry, as referenced by URB Handle 0, at
424 * which the data will be accessed.
425 *
426 * Similar text describes DWORD M0.4, which is slot 1 offset.
427 *
428 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
429 * of the register for geometry shader invocations 0 and 1) by the
430 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
431 *
432 * We can do this with the following EU instruction:
433 *
434 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
435 */
436 brw_push_insn_state(p);
437 brw_set_default_access_mode(p, BRW_ALIGN_1);
438 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
439 assert(p->devinfo->gen >= 7 &&
440 src1.file == BRW_IMMEDIATE_VALUE &&
441 src1.type == BRW_REGISTER_TYPE_UD &&
442 src1.ud <= USHRT_MAX);
443 if (src0.file == BRW_IMMEDIATE_VALUE) {
444 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
445 brw_imm_ud(src0.ud * src1.ud));
446 } else {
447 if (src1.file == BRW_IMMEDIATE_VALUE) {
448 src1 = brw_imm_uw(src1.ud);
449 }
450 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
451 retype(src1, BRW_REGISTER_TYPE_UW));
452 }
453 brw_pop_insn_state(p);
454 }
455
456 static void
457 generate_gs_set_vertex_count(struct brw_codegen *p,
458 struct brw_reg dst,
459 struct brw_reg src)
460 {
461 brw_push_insn_state(p);
462 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
463
464 if (p->devinfo->gen >= 8) {
465 /* Move the vertex count into the second MRF for the EOT write. */
466 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
467 src);
468 } else {
469 /* If we think of the src and dst registers as composed of 8 DWORDs each,
470 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
471 * them to WORDs, and then pack them into DWORD 2 of dst.
472 *
473 * It's easier to get the EU to do this if we think of the src and dst
474 * registers as composed of 16 WORDS each; then, we want to pick up the
475 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
476 * of dst.
477 *
478 * We can do that by the following EU instruction:
479 *
480 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
481 */
482 brw_set_default_access_mode(p, BRW_ALIGN_1);
483 brw_MOV(p,
484 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
485 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
486 }
487 brw_pop_insn_state(p);
488 }
489
490 static void
491 generate_gs_svb_write(struct brw_codegen *p,
492 struct brw_vue_prog_data *prog_data,
493 vec4_instruction *inst,
494 struct brw_reg dst,
495 struct brw_reg src0,
496 struct brw_reg src1)
497 {
498 int binding = inst->sol_binding;
499 bool final_write = inst->sol_final_write;
500
501 brw_push_insn_state(p);
502 brw_set_default_exec_size(p, BRW_EXECUTE_4);
503 /* Copy Vertex data into M0.x */
504 brw_MOV(p, stride(dst, 4, 4, 1),
505 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
506 brw_pop_insn_state(p);
507
508 brw_push_insn_state(p);
509 /* Send SVB Write */
510 brw_svb_write(p,
511 final_write ? src1 : brw_null_reg(), /* dest == src1 */
512 1, /* msg_reg_nr */
513 dst, /* src0 == previous dst */
514 BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */
515 final_write); /* send_commit_msg */
516
517 /* Finally, wait for the write commit to occur so that we can proceed to
518 * other things safely.
519 *
520 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
521 *
522 * The write commit does not modify the destination register, but
523 * merely clears the dependency associated with the destination
524 * register. Thus, a simple “mov” instruction using the register as a
525 * source is sufficient to wait for the write commit to occur.
526 */
527 if (final_write) {
528 brw_MOV(p, src1, src1);
529 }
530 brw_pop_insn_state(p);
531 }
532
533 static void
534 generate_gs_svb_set_destination_index(struct brw_codegen *p,
535 vec4_instruction *inst,
536 struct brw_reg dst,
537 struct brw_reg src)
538 {
539 int vertex = inst->sol_vertex;
540 brw_push_insn_state(p);
541 brw_set_default_access_mode(p, BRW_ALIGN_1);
542 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
543 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
544 brw_pop_insn_state(p);
545 }
546
547 static void
548 generate_gs_set_dword_2(struct brw_codegen *p,
549 struct brw_reg dst,
550 struct brw_reg src)
551 {
552 brw_push_insn_state(p);
553 brw_set_default_access_mode(p, BRW_ALIGN_1);
554 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
555 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
556 brw_pop_insn_state(p);
557 }
558
559 static void
560 generate_gs_prepare_channel_masks(struct brw_codegen *p,
561 struct brw_reg dst)
562 {
563 /* We want to left shift just DWORD 4 (the x component belonging to the
564 * second geometry shader invocation) by 4 bits. So generate the
565 * instruction:
566 *
567 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
568 */
569 dst = suboffset(vec1(dst), 4);
570 brw_push_insn_state(p);
571 brw_set_default_access_mode(p, BRW_ALIGN_1);
572 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
573 brw_SHL(p, dst, dst, brw_imm_ud(4));
574 brw_pop_insn_state(p);
575 }
576
577 static void
578 generate_gs_set_channel_masks(struct brw_codegen *p,
579 struct brw_reg dst,
580 struct brw_reg src)
581 {
582 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
583 * Header: M0.5):
584 *
585 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
586 *
587 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
588 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
589 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
590 * channel enable to determine the final channel enable. For the
591 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
592 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
593 * in the writeback message. For the URB_WRITE_OWORD &
594 * URB_WRITE_HWORD messages, when final channel enable is 1 it
595 * indicates that Vertex 1 DATA [3] will be written to the surface.
596 *
597 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
598 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
599 *
600 * 14 Vertex 1 DATA [2] Channel Mask
601 * 13 Vertex 1 DATA [1] Channel Mask
602 * 12 Vertex 1 DATA [0] Channel Mask
603 * 11 Vertex 0 DATA [3] Channel Mask
604 * 10 Vertex 0 DATA [2] Channel Mask
605 * 9 Vertex 0 DATA [1] Channel Mask
606 * 8 Vertex 0 DATA [0] Channel Mask
607 *
608 * (This is from a section of the PRM that is agnostic to the particular
609 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
610 * geometry shader invocations 0 and 1, respectively). Since we have the
611 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
612 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
613 * DWORD 4, we just need to OR them together and store the result in bits
614 * 15:8 of DWORD 5.
615 *
616 * It's easier to get the EU to do this if we think of the src and dst
617 * registers as composed of 32 bytes each; then, we want to pick up the
618 * contents of bytes 0 and 16 from src, OR them together, and store them in
619 * byte 21.
620 *
621 * We can do that by the following EU instruction:
622 *
623 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
624 *
625 * Note: this relies on the source register having zeros in (a) bits 7:4 of
626 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
627 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
628 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
629 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
630 * contain valid channel mask values (which are in the range 0x0-0xf).
631 */
632 dst = retype(dst, BRW_REGISTER_TYPE_UB);
633 src = retype(src, BRW_REGISTER_TYPE_UB);
634 brw_push_insn_state(p);
635 brw_set_default_access_mode(p, BRW_ALIGN_1);
636 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
637 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
638 brw_pop_insn_state(p);
639 }
640
641 static void
642 generate_gs_get_instance_id(struct brw_codegen *p,
643 struct brw_reg dst)
644 {
645 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
646 * and store into dst.0 & dst.4. So generate the instruction:
647 *
648 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
649 */
650 brw_push_insn_state(p);
651 brw_set_default_access_mode(p, BRW_ALIGN_1);
652 dst = retype(dst, BRW_REGISTER_TYPE_UD);
653 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
654 brw_SHR(p, dst, stride(r0, 1, 4, 0),
655 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
656 brw_pop_insn_state(p);
657 }
658
659 static void
660 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
661 struct brw_reg dst,
662 struct brw_reg src0,
663 struct brw_reg src1,
664 struct brw_reg src2)
665 {
666 brw_push_insn_state(p);
667 brw_set_default_access_mode(p, BRW_ALIGN_1);
668 /* Save src0 data in 16:31 bits of dst.0 */
669 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
670 brw_imm_ud(0xffffu));
671 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
672 /* Save src1 data in 0:15 bits of dst.0 */
673 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
674 brw_imm_ud(0xffffu));
675 brw_OR(p, suboffset(vec1(dst), 0),
676 suboffset(vec1(dst), 0),
677 suboffset(vec1(src2), 0));
678 brw_pop_insn_state(p);
679 }
680
681 static void
682 generate_gs_ff_sync(struct brw_codegen *p,
683 vec4_instruction *inst,
684 struct brw_reg dst,
685 struct brw_reg src0,
686 struct brw_reg src1)
687 {
688 /* This opcode uses an implied MRF register for:
689 * - the header of the ff_sync message. And as such it is expected to be
690 * initialized to r0 before calling here.
691 * - the destination where we will write the allocated URB handle.
692 */
693 struct brw_reg header =
694 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
695
696 /* Overwrite dword 0 of the header (SO vertices to write) and
697 * dword 1 (number of primitives written).
698 */
699 brw_push_insn_state(p);
700 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
701 brw_set_default_access_mode(p, BRW_ALIGN_1);
702 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
703 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
704 brw_pop_insn_state(p);
705
706 /* Allocate URB handle in dst */
707 brw_ff_sync(p,
708 dst,
709 0,
710 header,
711 1, /* allocate */
712 1, /* response length */
713 0 /* eot */);
714
715 /* Now put allocated urb handle in header.0 */
716 brw_push_insn_state(p);
717 brw_set_default_access_mode(p, BRW_ALIGN_1);
718 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
719 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
720
721 /* src1 is not an immediate when we use transform feedback */
722 if (src1.file != BRW_IMMEDIATE_VALUE) {
723 brw_set_default_exec_size(p, BRW_EXECUTE_4);
724 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
725 }
726
727 brw_pop_insn_state(p);
728 }
729
730 static void
731 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
732 {
733 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
734 struct brw_reg src = brw_vec8_grf(0, 0);
735 brw_push_insn_state(p);
736 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
737 brw_set_default_access_mode(p, BRW_ALIGN_1);
738 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
739 brw_pop_insn_state(p);
740 }
741
742 static void
743 generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
744 {
745 const struct gen_device_info *devinfo = p->devinfo;
746 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
747
748 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
749 *
750 * Since we operate in SIMD4x2 mode, we need run half as many threads
751 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
752 * shift right by one less to accomplish the multiplication by two.
753 */
754 dst = retype(dst, BRW_REGISTER_TYPE_UD);
755 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
756
757 brw_push_insn_state(p);
758 brw_set_default_access_mode(p, BRW_ALIGN_1);
759
760 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
761 const int shift = ivb ? 16 : 17;
762
763 brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
764 brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
765 brw_imm_ud(shift - 1));
766 brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
767
768 brw_pop_insn_state(p);
769 }
770
771 static void
772 generate_tcs_urb_write(struct brw_codegen *p,
773 vec4_instruction *inst,
774 struct brw_reg urb_header)
775 {
776 const struct gen_device_info *devinfo = p->devinfo;
777
778 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
779 brw_set_dest(p, send, brw_null_reg());
780 brw_set_src0(p, send, urb_header);
781 brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
782
783 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
784 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
785 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
786 if (inst->urb_write_flags & BRW_URB_WRITE_EOT) {
787 brw_inst_set_eot(devinfo, send, 1);
788 } else {
789 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
790 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
791 }
792
793 /* what happens to swizzles? */
794 }
795
796
797 static void
798 generate_tcs_input_urb_offsets(struct brw_codegen *p,
799 struct brw_reg dst,
800 struct brw_reg vertex,
801 struct brw_reg offset)
802 {
803 /* Generates an URB read/write message header for HS/DS operation.
804 * Inputs are a vertex index, and a byte offset from the beginning of
805 * the vertex. */
806
807 /* If `vertex` is not an immediate, we clobber a0.0 */
808
809 assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
810 assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
811
812 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
813
814 brw_push_insn_state(p);
815 brw_set_default_access_mode(p, BRW_ALIGN_1);
816 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
817 brw_MOV(p, dst, brw_imm_ud(0));
818
819 /* m0.5 bits 8-15 are channel enables */
820 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
821
822 /* m0.0-0.1: URB handles */
823 if (vertex.file == BRW_IMMEDIATE_VALUE) {
824 uint32_t vertex_index = vertex.ud;
825 struct brw_reg index_reg = brw_vec1_grf(
826 1 + (vertex_index >> 3), vertex_index & 7);
827
828 brw_MOV(p, vec2(get_element_ud(dst, 0)),
829 retype(index_reg, BRW_REGISTER_TYPE_UD));
830 } else {
831 /* Use indirect addressing. ICP Handles are DWords (single channels
832 * of a register) and start at g1.0.
833 *
834 * In order to start our region at g1.0, we add 8 to the vertex index,
835 * effectively skipping over the 8 channels in g0.0. This gives us a
836 * DWord offset to the ICP Handle.
837 *
838 * Indirect addressing works in terms of bytes, so we then multiply
839 * the DWord offset by 4 (by shifting left by 2).
840 */
841 struct brw_reg addr = brw_address_reg(0);
842
843 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
844 brw_ADD(p, addr, retype(get_element_ud(vertex, 0), BRW_REGISTER_TYPE_UW),
845 brw_imm_uw(0x8));
846 brw_SHL(p, addr, addr, brw_imm_uw(2));
847 brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
848
849 /* top half: m0.1 = g[1.0 + vertex.4]UD */
850 brw_ADD(p, addr, retype(get_element_ud(vertex, 4), BRW_REGISTER_TYPE_UW),
851 brw_imm_uw(0x8));
852 brw_SHL(p, addr, addr, brw_imm_uw(2));
853 brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
854 }
855
856 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
857 if (offset.file != ARF)
858 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
859
860 brw_pop_insn_state(p);
861 }
862
863
864 static void
865 generate_tcs_output_urb_offsets(struct brw_codegen *p,
866 struct brw_reg dst,
867 struct brw_reg write_mask,
868 struct brw_reg offset)
869 {
870 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
871 assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
872
873 assert(write_mask.file == BRW_IMMEDIATE_VALUE);
874 assert(write_mask.type == BRW_REGISTER_TYPE_UD);
875
876 brw_push_insn_state(p);
877
878 brw_set_default_access_mode(p, BRW_ALIGN_1);
879 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
880 brw_MOV(p, dst, brw_imm_ud(0));
881
882 unsigned mask = write_mask.ud;
883
884 /* m0.5 bits 15:12 and 11:8 are channel enables */
885 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
886
887 /* HS patch URB handle is delivered in r0.0 */
888 struct brw_reg urb_handle = brw_vec1_grf(0, 0);
889
890 /* m0.0-0.1: URB handles */
891 brw_MOV(p, vec2(get_element_ud(dst, 0)),
892 retype(urb_handle, BRW_REGISTER_TYPE_UD));
893
894 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
895 if (offset.file != ARF)
896 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
897
898 brw_pop_insn_state(p);
899 }
900
901 static void
902 generate_tes_create_input_read_header(struct brw_codegen *p,
903 struct brw_reg dst)
904 {
905 brw_push_insn_state(p);
906 brw_set_default_access_mode(p, BRW_ALIGN_1);
907 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
908
909 /* Initialize the register to 0 */
910 brw_MOV(p, dst, brw_imm_ud(0));
911
912 /* Enable all the channels in m0.5 bits 15:8 */
913 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
914
915 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
916 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
917 */
918 brw_AND(p, vec2(get_element_ud(dst, 0)),
919 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
920 brw_imm_ud(0x1fff));
921 brw_pop_insn_state(p);
922 }
923
924 static void
925 generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
926 struct brw_reg dst,
927 struct brw_reg header,
928 struct brw_reg offset)
929 {
930 brw_push_insn_state(p);
931 brw_set_default_access_mode(p, BRW_ALIGN_1);
932 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
933
934 brw_MOV(p, dst, header);
935
936 /* Uniforms will have a stride <0;4,1>, and we need to convert to <0;1,0>.
937 * Other values get <4;1,0>.
938 */
939 struct brw_reg restrided_offset;
940 if (offset.vstride == BRW_VERTICAL_STRIDE_0 &&
941 offset.width == BRW_WIDTH_4 &&
942 offset.hstride == BRW_HORIZONTAL_STRIDE_1) {
943 restrided_offset = stride(offset, 0, 1, 0);
944 } else {
945 restrided_offset = stride(offset, 4, 1, 0);
946 }
947
948 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
949 brw_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset);
950
951 brw_pop_insn_state(p);
952 }
953
954 static void
955 generate_vec4_urb_read(struct brw_codegen *p,
956 vec4_instruction *inst,
957 struct brw_reg dst,
958 struct brw_reg header)
959 {
960 const struct gen_device_info *devinfo = p->devinfo;
961
962 assert(header.file == BRW_GENERAL_REGISTER_FILE);
963 assert(header.type == BRW_REGISTER_TYPE_UD);
964
965 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
966 brw_set_dest(p, send, dst);
967 brw_set_src0(p, send, header);
968
969 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 1, true));
970
971 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
972 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
973 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
974 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
975
976 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
977 }
978
979 static void
980 generate_tcs_release_input(struct brw_codegen *p,
981 struct brw_reg header,
982 struct brw_reg vertex,
983 struct brw_reg is_unpaired)
984 {
985 const struct gen_device_info *devinfo = p->devinfo;
986
987 assert(vertex.file == BRW_IMMEDIATE_VALUE);
988 assert(vertex.type == BRW_REGISTER_TYPE_UD);
989
990 /* m0.0-0.1: URB handles */
991 struct brw_reg urb_handles =
992 retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7),
993 BRW_REGISTER_TYPE_UD);
994
995 brw_push_insn_state(p);
996 brw_set_default_access_mode(p, BRW_ALIGN_1);
997 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
998 brw_MOV(p, header, brw_imm_ud(0));
999 brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles);
1000 brw_pop_insn_state(p);
1001
1002 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1003 brw_set_dest(p, send, brw_null_reg());
1004 brw_set_src0(p, send, header);
1005 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 0, true));
1006
1007 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
1008 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
1009 brw_inst_set_urb_complete(devinfo, send, 1);
1010 brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ?
1011 BRW_URB_SWIZZLE_NONE :
1012 BRW_URB_SWIZZLE_INTERLEAVE);
1013 }
1014
1015 static void
1016 generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
1017 {
1018 struct brw_reg header = brw_message_reg(inst->base_mrf);
1019
1020 brw_push_insn_state(p);
1021 brw_set_default_access_mode(p, BRW_ALIGN_1);
1022 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1023 brw_MOV(p, header, brw_imm_ud(0));
1024 brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
1025 brw_MOV(p, get_element_ud(header, 0),
1026 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
1027 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
1028 brw_pop_insn_state(p);
1029
1030 brw_urb_WRITE(p,
1031 brw_null_reg(), /* dest */
1032 inst->base_mrf, /* starting mrf reg nr */
1033 header,
1034 BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
1035 BRW_URB_WRITE_USE_CHANNEL_MASKS,
1036 inst->mlen,
1037 0, /* response len */
1038 0, /* urb destination offset */
1039 0);
1040 }
1041
1042 static void
1043 generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1044 {
1045 brw_push_insn_state(p);
1046 brw_set_default_access_mode(p, BRW_ALIGN_1);
1047 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
1048 brw_pop_insn_state(p);
1049 }
1050
1051 static void
1052 generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1053 {
1054 brw_push_insn_state(p);
1055 brw_set_default_access_mode(p, BRW_ALIGN_1);
1056 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
1057 brw_pop_insn_state(p);
1058 }
1059
1060 static void
1061 generate_tcs_create_barrier_header(struct brw_codegen *p,
1062 struct brw_vue_prog_data *prog_data,
1063 struct brw_reg dst)
1064 {
1065 const struct gen_device_info *devinfo = p->devinfo;
1066 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
1067 struct brw_reg m0_2 = get_element_ud(dst, 2);
1068 unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
1069
1070 brw_push_insn_state(p);
1071 brw_set_default_access_mode(p, BRW_ALIGN_1);
1072 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1073
1074 /* Zero the message header */
1075 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
1076
1077 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1078 brw_AND(p, m0_2,
1079 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
1080 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1081
1082 /* Shift it up to bits 27:24. */
1083 brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11));
1084
1085 /* Set the Barrier Count and the enable bit */
1086 brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
1087
1088 brw_pop_insn_state(p);
1089 }
1090
1091 static void
1092 generate_oword_dual_block_offsets(struct brw_codegen *p,
1093 struct brw_reg m1,
1094 struct brw_reg index)
1095 {
1096 int second_vertex_offset;
1097
1098 if (p->devinfo->gen >= 6)
1099 second_vertex_offset = 1;
1100 else
1101 second_vertex_offset = 16;
1102
1103 m1 = retype(m1, BRW_REGISTER_TYPE_D);
1104
1105 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1106 * M1.4 are used, and the rest are ignored.
1107 */
1108 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
1109 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
1110 struct brw_reg index_0 = suboffset(vec1(index), 0);
1111 struct brw_reg index_4 = suboffset(vec1(index), 4);
1112
1113 brw_push_insn_state(p);
1114 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1115 brw_set_default_access_mode(p, BRW_ALIGN_1);
1116
1117 brw_MOV(p, m1_0, index_0);
1118
1119 if (index.file == BRW_IMMEDIATE_VALUE) {
1120 index_4.ud += second_vertex_offset;
1121 brw_MOV(p, m1_4, index_4);
1122 } else {
1123 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
1124 }
1125
1126 brw_pop_insn_state(p);
1127 }
1128
1129 static void
1130 generate_unpack_flags(struct brw_codegen *p,
1131 struct brw_reg dst)
1132 {
1133 brw_push_insn_state(p);
1134 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1135 brw_set_default_access_mode(p, BRW_ALIGN_1);
1136
1137 struct brw_reg flags = brw_flag_reg(0, 0);
1138 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
1139 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
1140
1141 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
1142 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
1143 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
1144
1145 brw_pop_insn_state(p);
1146 }
1147
1148 static void
1149 generate_scratch_read(struct brw_codegen *p,
1150 vec4_instruction *inst,
1151 struct brw_reg dst,
1152 struct brw_reg index)
1153 {
1154 const struct gen_device_info *devinfo = p->devinfo;
1155 struct brw_reg header = brw_vec8_grf(0, 0);
1156
1157 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1158
1159 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1160 index);
1161
1162 uint32_t msg_type;
1163
1164 if (devinfo->gen >= 6)
1165 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1166 else if (devinfo->gen == 5 || devinfo->is_g4x)
1167 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1168 else
1169 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1170
1171 const unsigned target_cache =
1172 devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1173 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1174 BRW_SFID_DATAPORT_READ;
1175
1176 /* Each of the 8 channel enables is considered for whether each
1177 * dword is written.
1178 */
1179 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1180 brw_inst_set_sfid(devinfo, send, target_cache);
1181 brw_set_dest(p, send, dst);
1182 brw_set_src0(p, send, header);
1183 if (devinfo->gen < 6)
1184 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
1185 brw_set_desc(p, send,
1186 brw_message_desc(devinfo, 2, 1, true) |
1187 brw_dp_read_desc(devinfo,
1188 brw_scratch_surface_idx(p),
1189 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1190 msg_type, BRW_DATAPORT_READ_TARGET_RENDER_CACHE));
1191 }
1192
1193 static void
1194 generate_scratch_write(struct brw_codegen *p,
1195 vec4_instruction *inst,
1196 struct brw_reg dst,
1197 struct brw_reg src,
1198 struct brw_reg index)
1199 {
1200 const struct gen_device_info *devinfo = p->devinfo;
1201 const unsigned target_cache =
1202 (devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1203 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1204 BRW_SFID_DATAPORT_WRITE);
1205 struct brw_reg header = brw_vec8_grf(0, 0);
1206 bool write_commit;
1207
1208 /* If the instruction is predicated, we'll predicate the send, not
1209 * the header setup.
1210 */
1211 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1212
1213 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1214
1215 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1216 index);
1217
1218 brw_MOV(p,
1219 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
1220 retype(src, BRW_REGISTER_TYPE_D));
1221
1222 uint32_t msg_type;
1223
1224 if (devinfo->gen >= 7)
1225 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
1226 else if (devinfo->gen == 6)
1227 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1228 else
1229 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1230
1231 brw_set_default_predicate_control(p, inst->predicate);
1232
1233 /* Pre-gen6, we have to specify write commits to ensure ordering
1234 * between reads and writes within a thread. Afterwards, that's
1235 * guaranteed and write commits only matter for inter-thread
1236 * synchronization.
1237 */
1238 if (devinfo->gen >= 6) {
1239 write_commit = false;
1240 } else {
1241 /* The visitor set up our destination register to be g0. This
1242 * means that when the next read comes along, we will end up
1243 * reading from g0 and causing a block on the write commit. For
1244 * write-after-read, we are relying on the value of the previous
1245 * read being used (and thus blocking on completion) before our
1246 * write is executed. This means we have to be careful in
1247 * instruction scheduling to not violate this assumption.
1248 */
1249 write_commit = true;
1250 }
1251
1252 /* Each of the 8 channel enables is considered for whether each
1253 * dword is written.
1254 */
1255 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1256 brw_inst_set_sfid(p->devinfo, send, target_cache);
1257 brw_set_dest(p, send, dst);
1258 brw_set_src0(p, send, header);
1259 if (devinfo->gen < 6)
1260 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1261 brw_set_desc(p, send,
1262 brw_message_desc(devinfo, 3, write_commit, true) |
1263 brw_dp_write_desc(devinfo,
1264 brw_scratch_surface_idx(p),
1265 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1266 msg_type,
1267 false, /* not a render target write */
1268 write_commit));
1269 }
1270
1271 static void
1272 generate_pull_constant_load(struct brw_codegen *p,
1273 struct brw_vue_prog_data *prog_data,
1274 vec4_instruction *inst,
1275 struct brw_reg dst,
1276 struct brw_reg index,
1277 struct brw_reg offset)
1278 {
1279 const struct gen_device_info *devinfo = p->devinfo;
1280 const unsigned target_cache =
1281 (devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE :
1282 BRW_SFID_DATAPORT_READ);
1283 assert(index.file == BRW_IMMEDIATE_VALUE &&
1284 index.type == BRW_REGISTER_TYPE_UD);
1285 uint32_t surf_index = index.ud;
1286
1287 struct brw_reg header = brw_vec8_grf(0, 0);
1288
1289 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1290
1291 if (devinfo->gen >= 6) {
1292 if (offset.file == BRW_IMMEDIATE_VALUE) {
1293 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1294 BRW_REGISTER_TYPE_D),
1295 brw_imm_d(offset.ud >> 4));
1296 } else {
1297 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
1298 BRW_REGISTER_TYPE_D),
1299 offset, brw_imm_d(4));
1300 }
1301 } else {
1302 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1303 BRW_REGISTER_TYPE_D),
1304 offset);
1305 }
1306
1307 uint32_t msg_type;
1308
1309 if (devinfo->gen >= 6)
1310 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1311 else if (devinfo->gen == 5 || devinfo->is_g4x)
1312 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1313 else
1314 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1315
1316 /* Each of the 8 channel enables is considered for whether each
1317 * dword is written.
1318 */
1319 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1320 brw_inst_set_sfid(devinfo, send, target_cache);
1321 brw_set_dest(p, send, dst);
1322 brw_set_src0(p, send, header);
1323 if (devinfo->gen < 6)
1324 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1325 brw_set_desc(p, send,
1326 brw_message_desc(devinfo, 2, 1, true) |
1327 brw_dp_read_desc(devinfo, surf_index,
1328 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1329 msg_type,
1330 BRW_DATAPORT_READ_TARGET_DATA_CACHE));
1331 }
1332
1333 static void
1334 generate_get_buffer_size(struct brw_codegen *p,
1335 struct brw_vue_prog_data *prog_data,
1336 vec4_instruction *inst,
1337 struct brw_reg dst,
1338 struct brw_reg src,
1339 struct brw_reg surf_index)
1340 {
1341 assert(p->devinfo->gen >= 7);
1342 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
1343 surf_index.file == BRW_IMMEDIATE_VALUE);
1344
1345 brw_SAMPLE(p,
1346 dst,
1347 inst->base_mrf,
1348 src,
1349 surf_index.ud,
1350 0,
1351 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1352 1, /* response length */
1353 inst->mlen,
1354 inst->header_size > 0,
1355 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1356 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1357 }
1358
1359 static void
1360 generate_pull_constant_load_gen7(struct brw_codegen *p,
1361 struct brw_vue_prog_data *prog_data,
1362 vec4_instruction *inst,
1363 struct brw_reg dst,
1364 struct brw_reg surf_index,
1365 struct brw_reg offset)
1366 {
1367 const struct gen_device_info *devinfo = p->devinfo;
1368 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1369
1370 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1371
1372 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1373 brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
1374 brw_set_dest(p, insn, dst);
1375 brw_set_src0(p, insn, offset);
1376 brw_set_desc(p, insn,
1377 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1378 brw_sampler_desc(devinfo, surf_index.ud,
1379 0, /* LD message ignores sampler unit */
1380 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1381 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0));
1382 } else {
1383
1384 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1385
1386 brw_push_insn_state(p);
1387 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1388 brw_set_default_access_mode(p, BRW_ALIGN_1);
1389
1390 /* a0.0 = surf_index & 0xff */
1391 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1392 brw_inst_set_exec_size(devinfo, insn_and, BRW_EXECUTE_1);
1393 brw_set_dest(p, insn_and, addr);
1394 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1395 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1396
1397 brw_pop_insn_state(p);
1398
1399 /* dst = send(offset, a0.0 | <descriptor>) */
1400 brw_send_indirect_message(
1401 p, BRW_SFID_SAMPLER, dst, offset, addr,
1402 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1403 brw_sampler_desc(devinfo,
1404 0 /* surface */,
1405 0 /* sampler */,
1406 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1407 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1408 0),
1409 false /* EOT */);
1410 }
1411 }
1412
1413 static void
1414 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1415 vec4_instruction *,
1416 struct brw_reg dst)
1417 {
1418 brw_push_insn_state(p);
1419 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1420
1421 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1422 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1423
1424 brw_set_default_access_mode(p, BRW_ALIGN_1);
1425 brw_MOV(p, get_element_ud(dst, 2),
1426 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1427
1428 brw_pop_insn_state(p);
1429 }
1430
1431 static void
1432 generate_mov_indirect(struct brw_codegen *p,
1433 vec4_instruction *,
1434 struct brw_reg dst, struct brw_reg reg,
1435 struct brw_reg indirect)
1436 {
1437 assert(indirect.type == BRW_REGISTER_TYPE_UD);
1438 assert(p->devinfo->gen >= 6);
1439
1440 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1441
1442 /* This instruction acts in align1 mode */
1443 assert(dst.writemask == WRITEMASK_XYZW);
1444
1445 if (indirect.file == BRW_IMMEDIATE_VALUE) {
1446 imm_byte_offset += indirect.ud;
1447
1448 reg.nr = imm_byte_offset / REG_SIZE;
1449 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
1450 unsigned shift = (imm_byte_offset / 4) % 4;
1451 reg.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift);
1452
1453 brw_MOV(p, dst, reg);
1454 } else {
1455 brw_push_insn_state(p);
1456 brw_set_default_access_mode(p, BRW_ALIGN_1);
1457 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1458
1459 struct brw_reg addr = vec8(brw_address_reg(0));
1460
1461 /* We need to move the indirect value into the address register. In
1462 * order to make things make some sense, we want to respect at least the
1463 * X component of the swizzle. In order to do that, we need to convert
1464 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1465 */
1466 assert(brw_is_single_value_swizzle(indirect.swizzle));
1467 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
1468
1469 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1470 * the indirect and splat it out to all four channels of the given half
1471 * of a0.
1472 */
1473 indirect.subnr *= 2;
1474 indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0);
1475 brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset));
1476
1477 /* Now we need to incorporate the swizzle from the source register */
1478 if (reg.swizzle != BRW_SWIZZLE_XXXX) {
1479 uint32_t uv_swiz = BRW_GET_SWZ(reg.swizzle, 0) << 2 |
1480 BRW_GET_SWZ(reg.swizzle, 1) << 6 |
1481 BRW_GET_SWZ(reg.swizzle, 2) << 10 |
1482 BRW_GET_SWZ(reg.swizzle, 3) << 14;
1483 uv_swiz |= uv_swiz << 16;
1484
1485 brw_ADD(p, addr, addr, brw_imm_uv(uv_swiz));
1486 }
1487
1488 brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), reg.type));
1489
1490 brw_pop_insn_state(p);
1491 }
1492 }
1493
1494 static void
1495 generate_code(struct brw_codegen *p,
1496 const struct brw_compiler *compiler,
1497 void *log_data,
1498 const nir_shader *nir,
1499 struct brw_vue_prog_data *prog_data,
1500 const struct cfg_t *cfg,
1501 struct brw_compile_stats *stats)
1502 {
1503 const struct gen_device_info *devinfo = p->devinfo;
1504 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
1505 bool debug_flag = INTEL_DEBUG &
1506 intel_debug_flag_for_shader_stage(nir->info.stage);
1507 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1508 int spill_count = 0, fill_count = 0;
1509 int loop_count = 0;
1510
1511 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1512 struct brw_reg src[3], dst;
1513
1514 if (unlikely(debug_flag))
1515 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1516
1517 for (unsigned int i = 0; i < 3; i++) {
1518 src[i] = inst->src[i].as_brw_reg();
1519 }
1520 dst = inst->dst.as_brw_reg();
1521
1522 brw_set_default_predicate_control(p, inst->predicate);
1523 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1524 brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
1525 brw_set_default_saturate(p, inst->saturate);
1526 brw_set_default_mask_control(p, inst->force_writemask_all);
1527 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1528
1529 assert(inst->group % inst->exec_size == 0);
1530 assert(inst->group % 4 == 0);
1531
1532 /* There are some instructions where the destination is 64-bit
1533 * but we retype it to a smaller type. In that case, we cannot
1534 * double the exec_size.
1535 */
1536 const bool is_df = (get_exec_type_size(inst) == 8 ||
1537 inst->dst.type == BRW_REGISTER_TYPE_DF) &&
1538 inst->opcode != VEC4_OPCODE_PICK_LOW_32BIT &&
1539 inst->opcode != VEC4_OPCODE_PICK_HIGH_32BIT &&
1540 inst->opcode != VEC4_OPCODE_SET_LOW_32BIT &&
1541 inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
1542
1543 unsigned exec_size = inst->exec_size;
1544 if (devinfo->gen == 7 && !devinfo->is_haswell && is_df)
1545 exec_size *= 2;
1546
1547 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1548
1549 if (!inst->force_writemask_all)
1550 brw_set_default_group(p, inst->group);
1551
1552 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1553 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1554
1555 unsigned pre_emit_nr_insn = p->nr_insn;
1556
1557 switch (inst->opcode) {
1558 case VEC4_OPCODE_UNPACK_UNIFORM:
1559 case BRW_OPCODE_MOV:
1560 brw_MOV(p, dst, src[0]);
1561 break;
1562 case BRW_OPCODE_ADD:
1563 brw_ADD(p, dst, src[0], src[1]);
1564 break;
1565 case BRW_OPCODE_MUL:
1566 brw_MUL(p, dst, src[0], src[1]);
1567 break;
1568 case BRW_OPCODE_MACH:
1569 brw_MACH(p, dst, src[0], src[1]);
1570 break;
1571
1572 case BRW_OPCODE_MAD:
1573 assert(devinfo->gen >= 6);
1574 brw_MAD(p, dst, src[0], src[1], src[2]);
1575 break;
1576
1577 case BRW_OPCODE_FRC:
1578 brw_FRC(p, dst, src[0]);
1579 break;
1580 case BRW_OPCODE_RNDD:
1581 brw_RNDD(p, dst, src[0]);
1582 break;
1583 case BRW_OPCODE_RNDE:
1584 brw_RNDE(p, dst, src[0]);
1585 break;
1586 case BRW_OPCODE_RNDZ:
1587 brw_RNDZ(p, dst, src[0]);
1588 break;
1589
1590 case BRW_OPCODE_AND:
1591 brw_AND(p, dst, src[0], src[1]);
1592 break;
1593 case BRW_OPCODE_OR:
1594 brw_OR(p, dst, src[0], src[1]);
1595 break;
1596 case BRW_OPCODE_XOR:
1597 brw_XOR(p, dst, src[0], src[1]);
1598 break;
1599 case BRW_OPCODE_NOT:
1600 brw_NOT(p, dst, src[0]);
1601 break;
1602 case BRW_OPCODE_ASR:
1603 brw_ASR(p, dst, src[0], src[1]);
1604 break;
1605 case BRW_OPCODE_SHR:
1606 brw_SHR(p, dst, src[0], src[1]);
1607 break;
1608 case BRW_OPCODE_SHL:
1609 brw_SHL(p, dst, src[0], src[1]);
1610 break;
1611
1612 case BRW_OPCODE_CMP:
1613 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1614 break;
1615 case BRW_OPCODE_SEL:
1616 brw_SEL(p, dst, src[0], src[1]);
1617 break;
1618
1619 case BRW_OPCODE_DPH:
1620 brw_DPH(p, dst, src[0], src[1]);
1621 break;
1622
1623 case BRW_OPCODE_DP4:
1624 brw_DP4(p, dst, src[0], src[1]);
1625 break;
1626
1627 case BRW_OPCODE_DP3:
1628 brw_DP3(p, dst, src[0], src[1]);
1629 break;
1630
1631 case BRW_OPCODE_DP2:
1632 brw_DP2(p, dst, src[0], src[1]);
1633 break;
1634
1635 case BRW_OPCODE_F32TO16:
1636 assert(devinfo->gen >= 7);
1637 brw_F32TO16(p, dst, src[0]);
1638 break;
1639
1640 case BRW_OPCODE_F16TO32:
1641 assert(devinfo->gen >= 7);
1642 brw_F16TO32(p, dst, src[0]);
1643 break;
1644
1645 case BRW_OPCODE_LRP:
1646 assert(devinfo->gen >= 6);
1647 brw_LRP(p, dst, src[0], src[1], src[2]);
1648 break;
1649
1650 case BRW_OPCODE_BFREV:
1651 assert(devinfo->gen >= 7);
1652 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1653 retype(src[0], BRW_REGISTER_TYPE_UD));
1654 break;
1655 case BRW_OPCODE_FBH:
1656 assert(devinfo->gen >= 7);
1657 brw_FBH(p, retype(dst, src[0].type), src[0]);
1658 break;
1659 case BRW_OPCODE_FBL:
1660 assert(devinfo->gen >= 7);
1661 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
1662 retype(src[0], BRW_REGISTER_TYPE_UD));
1663 break;
1664 case BRW_OPCODE_LZD:
1665 brw_LZD(p, dst, src[0]);
1666 break;
1667 case BRW_OPCODE_CBIT:
1668 assert(devinfo->gen >= 7);
1669 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
1670 retype(src[0], BRW_REGISTER_TYPE_UD));
1671 break;
1672 case BRW_OPCODE_ADDC:
1673 assert(devinfo->gen >= 7);
1674 brw_ADDC(p, dst, src[0], src[1]);
1675 break;
1676 case BRW_OPCODE_SUBB:
1677 assert(devinfo->gen >= 7);
1678 brw_SUBB(p, dst, src[0], src[1]);
1679 break;
1680 case BRW_OPCODE_MAC:
1681 brw_MAC(p, dst, src[0], src[1]);
1682 break;
1683
1684 case BRW_OPCODE_BFE:
1685 assert(devinfo->gen >= 7);
1686 brw_BFE(p, dst, src[0], src[1], src[2]);
1687 break;
1688
1689 case BRW_OPCODE_BFI1:
1690 assert(devinfo->gen >= 7);
1691 brw_BFI1(p, dst, src[0], src[1]);
1692 break;
1693 case BRW_OPCODE_BFI2:
1694 assert(devinfo->gen >= 7);
1695 brw_BFI2(p, dst, src[0], src[1], src[2]);
1696 break;
1697
1698 case BRW_OPCODE_IF:
1699 if (!inst->src[0].is_null()) {
1700 /* The instruction has an embedded compare (only allowed on gen6) */
1701 assert(devinfo->gen == 6);
1702 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1703 } else {
1704 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1705 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1706 }
1707 break;
1708
1709 case BRW_OPCODE_ELSE:
1710 brw_ELSE(p);
1711 break;
1712 case BRW_OPCODE_ENDIF:
1713 brw_ENDIF(p);
1714 break;
1715
1716 case BRW_OPCODE_DO:
1717 brw_DO(p, BRW_EXECUTE_8);
1718 break;
1719
1720 case BRW_OPCODE_BREAK:
1721 brw_BREAK(p);
1722 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1723 break;
1724 case BRW_OPCODE_CONTINUE:
1725 brw_CONT(p);
1726 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1727 break;
1728
1729 case BRW_OPCODE_WHILE:
1730 brw_WHILE(p);
1731 loop_count++;
1732 break;
1733
1734 case SHADER_OPCODE_RCP:
1735 case SHADER_OPCODE_RSQ:
1736 case SHADER_OPCODE_SQRT:
1737 case SHADER_OPCODE_EXP2:
1738 case SHADER_OPCODE_LOG2:
1739 case SHADER_OPCODE_SIN:
1740 case SHADER_OPCODE_COS:
1741 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1742 if (devinfo->gen >= 7) {
1743 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1744 brw_null_reg());
1745 } else if (devinfo->gen == 6) {
1746 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1747 } else {
1748 generate_math1_gen4(p, inst, dst, src[0]);
1749 }
1750 break;
1751
1752 case SHADER_OPCODE_POW:
1753 case SHADER_OPCODE_INT_QUOTIENT:
1754 case SHADER_OPCODE_INT_REMAINDER:
1755 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1756 if (devinfo->gen >= 7) {
1757 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1758 } else if (devinfo->gen == 6) {
1759 generate_math_gen6(p, inst, dst, src[0], src[1]);
1760 } else {
1761 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1762 }
1763 break;
1764
1765 case SHADER_OPCODE_TEX:
1766 case SHADER_OPCODE_TXD:
1767 case SHADER_OPCODE_TXF:
1768 case SHADER_OPCODE_TXF_CMS:
1769 case SHADER_OPCODE_TXF_CMS_W:
1770 case SHADER_OPCODE_TXF_MCS:
1771 case SHADER_OPCODE_TXL:
1772 case SHADER_OPCODE_TXS:
1773 case SHADER_OPCODE_TG4:
1774 case SHADER_OPCODE_TG4_OFFSET:
1775 case SHADER_OPCODE_SAMPLEINFO:
1776 generate_tex(p, prog_data, nir->info.stage,
1777 inst, dst, src[0], src[1], src[2]);
1778 break;
1779
1780 case SHADER_OPCODE_GET_BUFFER_SIZE:
1781 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1782 break;
1783
1784 case VS_OPCODE_URB_WRITE:
1785 generate_vs_urb_write(p, inst);
1786 break;
1787
1788 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1789 generate_scratch_read(p, inst, dst, src[0]);
1790 fill_count++;
1791 break;
1792
1793 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1794 generate_scratch_write(p, inst, dst, src[0], src[1]);
1795 spill_count++;
1796 break;
1797
1798 case VS_OPCODE_PULL_CONSTANT_LOAD:
1799 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1800 break;
1801
1802 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1803 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1804 break;
1805
1806 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1807 generate_set_simd4x2_header_gen9(p, inst, dst);
1808 break;
1809
1810 case GS_OPCODE_URB_WRITE:
1811 generate_gs_urb_write(p, inst);
1812 break;
1813
1814 case GS_OPCODE_URB_WRITE_ALLOCATE:
1815 generate_gs_urb_write_allocate(p, inst);
1816 break;
1817
1818 case GS_OPCODE_SVB_WRITE:
1819 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1820 break;
1821
1822 case GS_OPCODE_SVB_SET_DST_INDEX:
1823 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1824 break;
1825
1826 case GS_OPCODE_THREAD_END:
1827 generate_gs_thread_end(p, inst);
1828 break;
1829
1830 case GS_OPCODE_SET_WRITE_OFFSET:
1831 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1832 break;
1833
1834 case GS_OPCODE_SET_VERTEX_COUNT:
1835 generate_gs_set_vertex_count(p, dst, src[0]);
1836 break;
1837
1838 case GS_OPCODE_FF_SYNC:
1839 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1840 break;
1841
1842 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1843 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1844 break;
1845
1846 case GS_OPCODE_SET_PRIMITIVE_ID:
1847 generate_gs_set_primitive_id(p, dst);
1848 break;
1849
1850 case GS_OPCODE_SET_DWORD_2:
1851 generate_gs_set_dword_2(p, dst, src[0]);
1852 break;
1853
1854 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1855 generate_gs_prepare_channel_masks(p, dst);
1856 break;
1857
1858 case GS_OPCODE_SET_CHANNEL_MASKS:
1859 generate_gs_set_channel_masks(p, dst, src[0]);
1860 break;
1861
1862 case GS_OPCODE_GET_INSTANCE_ID:
1863 generate_gs_get_instance_id(p, dst);
1864 break;
1865
1866 case SHADER_OPCODE_SHADER_TIME_ADD:
1867 brw_shader_time_add(p, src[0],
1868 prog_data->base.binding_table.shader_time_start);
1869 break;
1870
1871 case VEC4_OPCODE_UNTYPED_ATOMIC:
1872 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1873 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1874 !inst->dst.is_null(), inst->header_size);
1875 break;
1876
1877 case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1878 assert(!inst->header_size);
1879 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1880 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1881 src[2].ud);
1882 break;
1883
1884 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1885 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1886 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1887 src[2].ud, inst->header_size);
1888 break;
1889
1890 case SHADER_OPCODE_MEMORY_FENCE:
1891 brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND, false, /* bti */ 0);
1892 break;
1893
1894 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
1895 const struct brw_reg mask =
1896 brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
1897 &prog_data->base) ? brw_imm_ud(~0u) :
1898 brw_dmask_reg();
1899 brw_find_live_channel(p, dst, mask);
1900 break;
1901 }
1902
1903 case SHADER_OPCODE_BROADCAST:
1904 assert(inst->force_writemask_all);
1905 brw_broadcast(p, dst, src[0], src[1]);
1906 break;
1907
1908 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1909 generate_unpack_flags(p, dst);
1910 break;
1911
1912 case VEC4_OPCODE_MOV_BYTES: {
1913 /* Moves the low byte from each channel, using an Align1 access mode
1914 * and a <4,1,0> source region.
1915 */
1916 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1917 src[0].type == BRW_REGISTER_TYPE_B);
1918
1919 brw_set_default_access_mode(p, BRW_ALIGN_1);
1920 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1921 src[0].width = BRW_WIDTH_1;
1922 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1923 brw_MOV(p, dst, src[0]);
1924 brw_set_default_access_mode(p, BRW_ALIGN_16);
1925 break;
1926 }
1927
1928 case VEC4_OPCODE_DOUBLE_TO_F32:
1929 case VEC4_OPCODE_DOUBLE_TO_D32:
1930 case VEC4_OPCODE_DOUBLE_TO_U32: {
1931 assert(type_sz(src[0].type) == 8);
1932 assert(type_sz(dst.type) == 8);
1933
1934 brw_reg_type dst_type;
1935
1936 switch (inst->opcode) {
1937 case VEC4_OPCODE_DOUBLE_TO_F32:
1938 dst_type = BRW_REGISTER_TYPE_F;
1939 break;
1940 case VEC4_OPCODE_DOUBLE_TO_D32:
1941 dst_type = BRW_REGISTER_TYPE_D;
1942 break;
1943 case VEC4_OPCODE_DOUBLE_TO_U32:
1944 dst_type = BRW_REGISTER_TYPE_UD;
1945 break;
1946 default:
1947 unreachable("Not supported conversion");
1948 }
1949 dst = retype(dst, dst_type);
1950
1951 brw_set_default_access_mode(p, BRW_ALIGN_1);
1952
1953 /* When converting from DF->F, we set destination's stride as 2 as an
1954 * aligment requirement. But in IVB/BYT, each DF implicitly writes
1955 * two floats, being the first one the converted value. So we don't
1956 * need to explicitly set stride 2, but 1.
1957 */
1958 struct brw_reg spread_dst;
1959 if (devinfo->gen == 7 && !devinfo->is_haswell)
1960 spread_dst = stride(dst, 8, 4, 1);
1961 else
1962 spread_dst = stride(dst, 8, 4, 2);
1963
1964 brw_MOV(p, spread_dst, src[0]);
1965
1966 brw_set_default_access_mode(p, BRW_ALIGN_16);
1967 break;
1968 }
1969
1970 case VEC4_OPCODE_TO_DOUBLE: {
1971 assert(type_sz(src[0].type) == 4);
1972 assert(type_sz(dst.type) == 8);
1973
1974 brw_set_default_access_mode(p, BRW_ALIGN_1);
1975
1976 brw_MOV(p, dst, src[0]);
1977
1978 brw_set_default_access_mode(p, BRW_ALIGN_16);
1979 break;
1980 }
1981
1982 case VEC4_OPCODE_PICK_LOW_32BIT:
1983 case VEC4_OPCODE_PICK_HIGH_32BIT: {
1984 /* Stores the low/high 32-bit of each 64-bit element in src[0] into
1985 * dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
1986 */
1987 assert(type_sz(src[0].type) == 8);
1988 assert(type_sz(dst.type) == 4);
1989
1990 brw_set_default_access_mode(p, BRW_ALIGN_1);
1991
1992 dst = retype(dst, BRW_REGISTER_TYPE_UD);
1993 dst.hstride = BRW_HORIZONTAL_STRIDE_1;
1994
1995 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
1996 if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)
1997 src[0] = suboffset(src[0], 1);
1998 src[0] = spread(src[0], 2);
1999 brw_MOV(p, dst, src[0]);
2000
2001 brw_set_default_access_mode(p, BRW_ALIGN_16);
2002 break;
2003 }
2004
2005 case VEC4_OPCODE_SET_LOW_32BIT:
2006 case VEC4_OPCODE_SET_HIGH_32BIT: {
2007 /* Reads consecutive 32-bit elements from src[0] and writes
2008 * them to the low/high 32-bit of each 64-bit element in dst.
2009 */
2010 assert(type_sz(src[0].type) == 4);
2011 assert(type_sz(dst.type) == 8);
2012
2013 brw_set_default_access_mode(p, BRW_ALIGN_1);
2014
2015 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2016 if (inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT)
2017 dst = suboffset(dst, 1);
2018 dst.hstride = BRW_HORIZONTAL_STRIDE_2;
2019
2020 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2021 brw_MOV(p, dst, src[0]);
2022
2023 brw_set_default_access_mode(p, BRW_ALIGN_16);
2024 break;
2025 }
2026
2027 case VEC4_OPCODE_PACK_BYTES: {
2028 /* Is effectively:
2029 *
2030 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
2031 *
2032 * but destinations' only regioning is horizontal stride, so instead we
2033 * have to use two instructions:
2034 *
2035 * mov(4) dst<1>:UB src<4,1,0>:UB
2036 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
2037 *
2038 * where they pack the four bytes from the low and high four DW.
2039 */
2040 assert(_mesa_is_pow_two(dst.writemask) &&
2041 dst.writemask != 0);
2042 unsigned offset = __builtin_ctz(dst.writemask);
2043
2044 dst.type = BRW_REGISTER_TYPE_UB;
2045
2046 brw_set_default_access_mode(p, BRW_ALIGN_1);
2047
2048 src[0].type = BRW_REGISTER_TYPE_UB;
2049 src[0].vstride = BRW_VERTICAL_STRIDE_4;
2050 src[0].width = BRW_WIDTH_1;
2051 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
2052 dst.subnr = offset * 4;
2053 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
2054 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2055 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
2056 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
2057
2058 src[0].subnr = 16;
2059 dst.subnr = 16 + offset * 4;
2060 insn = brw_MOV(p, dst, src[0]);
2061 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2062 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
2063 brw_inst_set_no_dd_check(p->devinfo, insn, true);
2064
2065 brw_set_default_access_mode(p, BRW_ALIGN_16);
2066 break;
2067 }
2068
2069 case TCS_OPCODE_URB_WRITE:
2070 generate_tcs_urb_write(p, inst, src[0]);
2071 break;
2072
2073 case VEC4_OPCODE_URB_READ:
2074 generate_vec4_urb_read(p, inst, dst, src[0]);
2075 break;
2076
2077 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
2078 generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
2079 break;
2080
2081 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
2082 generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
2083 break;
2084
2085 case TCS_OPCODE_GET_INSTANCE_ID:
2086 generate_tcs_get_instance_id(p, dst);
2087 break;
2088
2089 case TCS_OPCODE_GET_PRIMITIVE_ID:
2090 generate_tcs_get_primitive_id(p, dst);
2091 break;
2092
2093 case TCS_OPCODE_CREATE_BARRIER_HEADER:
2094 generate_tcs_create_barrier_header(p, prog_data, dst);
2095 break;
2096
2097 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
2098 generate_tes_create_input_read_header(p, dst);
2099 break;
2100
2101 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
2102 generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
2103 break;
2104
2105 case TES_OPCODE_GET_PRIMITIVE_ID:
2106 generate_tes_get_primitive_id(p, dst);
2107 break;
2108
2109 case TCS_OPCODE_SRC0_010_IS_ZERO:
2110 /* If src_reg had stride like fs_reg, we wouldn't need this. */
2111 brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
2112 break;
2113
2114 case TCS_OPCODE_RELEASE_INPUT:
2115 generate_tcs_release_input(p, dst, src[0], src[1]);
2116 break;
2117
2118 case TCS_OPCODE_THREAD_END:
2119 generate_tcs_thread_end(p, inst);
2120 break;
2121
2122 case SHADER_OPCODE_BARRIER:
2123 brw_barrier(p, src[0]);
2124 brw_WAIT(p);
2125 break;
2126
2127 case SHADER_OPCODE_MOV_INDIRECT:
2128 generate_mov_indirect(p, inst, dst, src[0], src[1]);
2129 break;
2130
2131 case BRW_OPCODE_DIM:
2132 assert(devinfo->is_haswell);
2133 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2134 assert(dst.type == BRW_REGISTER_TYPE_DF);
2135 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2136 break;
2137
2138 default:
2139 unreachable("Unsupported opcode");
2140 }
2141
2142 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
2143 /* Handled dependency hints in the generator. */
2144
2145 assert(!inst->conditional_mod);
2146 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2147 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
2148 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2149 "emitting more than 1 instruction");
2150
2151 brw_inst *last = &p->store[pre_emit_nr_insn];
2152
2153 if (inst->conditional_mod)
2154 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2155 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2156 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2157 }
2158 }
2159
2160 brw_set_uip_jip(p, 0);
2161
2162 /* end of program sentinel */
2163 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2164
2165 #ifndef NDEBUG
2166 bool validated =
2167 #else
2168 if (unlikely(debug_flag))
2169 #endif
2170 brw_validate_instructions(devinfo, p->store,
2171 0, p->next_insn_offset,
2172 disasm_info);
2173
2174 int before_size = p->next_insn_offset;
2175 brw_compact_instructions(p, 0, disasm_info);
2176 int after_size = p->next_insn_offset;
2177
2178 if (unlikely(debug_flag)) {
2179 unsigned char sha1[21];
2180 char sha1buf[41];
2181
2182 _mesa_sha1_compute(p->store, p->next_insn_offset, sha1);
2183 _mesa_sha1_format(sha1buf, sha1);
2184
2185 fprintf(stderr, "Native code for %s %s shader %s (sha1 %s):\n",
2186 nir->info.label ? nir->info.label : "unnamed",
2187 _mesa_shader_stage_to_string(nir->info.stage), nir->info.name,
2188 sha1buf);
2189
2190 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2191 "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
2192 stage_abbrev, before_size / 16, loop_count, cfg->cycle_count,
2193 spill_count, fill_count, before_size, after_size,
2194 100.0f * (before_size - after_size) / before_size);
2195
2196 /* overriding the shader makes disasm_info invalid */
2197 if (!brw_try_override_assembly(p, 0, sha1buf)) {
2198 dump_assembly(p->store, disasm_info);
2199 } else {
2200 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
2201 }
2202 }
2203 ralloc_free(disasm_info);
2204 assert(validated);
2205
2206 compiler->shader_debug_log(log_data,
2207 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2208 "%d:%d spills:fills, compacted %d to %d bytes.",
2209 stage_abbrev, before_size / 16,
2210 loop_count, cfg->cycle_count, spill_count,
2211 fill_count, before_size, after_size);
2212 if (stats) {
2213 stats->dispatch_width = 0;
2214 stats->instructions = before_size / 16;
2215 stats->loops = loop_count;
2216 stats->cycles = cfg->cycle_count;
2217 stats->spills = spill_count;
2218 stats->fills = fill_count;
2219 }
2220 }
2221
2222 extern "C" const unsigned *
2223 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
2224 void *log_data,
2225 void *mem_ctx,
2226 const nir_shader *nir,
2227 struct brw_vue_prog_data *prog_data,
2228 const struct cfg_t *cfg,
2229 struct brw_compile_stats *stats)
2230 {
2231 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
2232 brw_init_codegen(compiler->devinfo, p, mem_ctx);
2233 brw_set_default_access_mode(p, BRW_ALIGN_16);
2234
2235 generate_code(p, compiler, log_data, nir, prog_data, cfg, stats);
2236
2237 return brw_get_program(p, &prog_data->base.program_size);
2238 }