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i965/vec4: Correctly handle uniform sources in generate_tes_add_indirect_urb_offset
[mesa.git] / src / intel / compiler / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "common/gen_debug.h"
27
28 using namespace brw;
29
30 static void
31 generate_math1_gen4(struct brw_codegen *p,
32 vec4_instruction *inst,
33 struct brw_reg dst,
34 struct brw_reg src)
35 {
36 gen4_math(p,
37 dst,
38 brw_math_function(inst->opcode),
39 inst->base_mrf,
40 src,
41 BRW_MATH_PRECISION_FULL);
42 }
43
44 static void
45 check_gen6_math_src_arg(struct brw_reg src)
46 {
47 /* Source swizzles are ignored. */
48 assert(!src.abs);
49 assert(!src.negate);
50 assert(src.swizzle == BRW_SWIZZLE_XYZW);
51 }
52
53 static void
54 generate_math_gen6(struct brw_codegen *p,
55 vec4_instruction *inst,
56 struct brw_reg dst,
57 struct brw_reg src0,
58 struct brw_reg src1)
59 {
60 /* Can't do writemask because math can't be align16. */
61 assert(dst.writemask == WRITEMASK_XYZW);
62 /* Source swizzles are ignored. */
63 check_gen6_math_src_arg(src0);
64 if (src1.file == BRW_GENERAL_REGISTER_FILE)
65 check_gen6_math_src_arg(src1);
66
67 brw_set_default_access_mode(p, BRW_ALIGN_1);
68 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
69 brw_set_default_access_mode(p, BRW_ALIGN_16);
70 }
71
72 static void
73 generate_math2_gen4(struct brw_codegen *p,
74 vec4_instruction *inst,
75 struct brw_reg dst,
76 struct brw_reg src0,
77 struct brw_reg src1)
78 {
79 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
80 * "Message Payload":
81 *
82 * "Operand0[7]. For the INT DIV functions, this operand is the
83 * denominator."
84 * ...
85 * "Operand1[7]. For the INT DIV functions, this operand is the
86 * numerator."
87 */
88 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
89 struct brw_reg &op0 = is_int_div ? src1 : src0;
90 struct brw_reg &op1 = is_int_div ? src0 : src1;
91
92 brw_push_insn_state(p);
93 brw_set_default_saturate(p, false);
94 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
95 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
96 brw_pop_insn_state(p);
97
98 gen4_math(p,
99 dst,
100 brw_math_function(inst->opcode),
101 inst->base_mrf,
102 op0,
103 BRW_MATH_PRECISION_FULL);
104 }
105
106 static void
107 generate_tex(struct brw_codegen *p,
108 struct brw_vue_prog_data *prog_data,
109 gl_shader_stage stage,
110 vec4_instruction *inst,
111 struct brw_reg dst,
112 struct brw_reg src,
113 struct brw_reg surface_index,
114 struct brw_reg sampler_index)
115 {
116 const struct gen_device_info *devinfo = p->devinfo;
117 int msg_type = -1;
118
119 if (devinfo->gen >= 5) {
120 switch (inst->opcode) {
121 case SHADER_OPCODE_TEX:
122 case SHADER_OPCODE_TXL:
123 if (inst->shadow_compare) {
124 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
125 } else {
126 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
127 }
128 break;
129 case SHADER_OPCODE_TXD:
130 if (inst->shadow_compare) {
131 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
132 assert(devinfo->gen >= 8 || devinfo->is_haswell);
133 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
134 } else {
135 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
136 }
137 break;
138 case SHADER_OPCODE_TXF:
139 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
140 break;
141 case SHADER_OPCODE_TXF_CMS_W:
142 assert(devinfo->gen >= 9);
143 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
144 break;
145 case SHADER_OPCODE_TXF_CMS:
146 if (devinfo->gen >= 7)
147 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
148 else
149 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
150 break;
151 case SHADER_OPCODE_TXF_MCS:
152 assert(devinfo->gen >= 7);
153 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
154 break;
155 case SHADER_OPCODE_TXS:
156 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
157 break;
158 case SHADER_OPCODE_TG4:
159 if (inst->shadow_compare) {
160 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
161 } else {
162 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
163 }
164 break;
165 case SHADER_OPCODE_TG4_OFFSET:
166 if (inst->shadow_compare) {
167 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
168 } else {
169 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
170 }
171 break;
172 case SHADER_OPCODE_SAMPLEINFO:
173 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
174 break;
175 default:
176 unreachable("should not get here: invalid vec4 texture opcode");
177 }
178 } else {
179 switch (inst->opcode) {
180 case SHADER_OPCODE_TEX:
181 case SHADER_OPCODE_TXL:
182 if (inst->shadow_compare) {
183 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
184 assert(inst->mlen == 3);
185 } else {
186 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
187 assert(inst->mlen == 2);
188 }
189 break;
190 case SHADER_OPCODE_TXD:
191 /* There is no sample_d_c message; comparisons are done manually. */
192 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
193 assert(inst->mlen == 4);
194 break;
195 case SHADER_OPCODE_TXF:
196 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
197 assert(inst->mlen == 2);
198 break;
199 case SHADER_OPCODE_TXS:
200 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
201 assert(inst->mlen == 2);
202 break;
203 default:
204 unreachable("should not get here: invalid vec4 texture opcode");
205 }
206 }
207
208 assert(msg_type != -1);
209
210 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
211
212 /* Load the message header if present. If there's a texture offset, we need
213 * to set it up explicitly and load the offset bitfield. Otherwise, we can
214 * use an implied move from g0 to the first message register.
215 */
216 if (inst->header_size != 0) {
217 if (devinfo->gen < 6 && !inst->offset) {
218 /* Set up an implied move from g0 to the MRF. */
219 src = brw_vec8_grf(0, 0);
220 } else {
221 struct brw_reg header =
222 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
223 uint32_t dw2 = 0;
224
225 /* Explicitly set up the message header by copying g0 to the MRF. */
226 brw_push_insn_state(p);
227 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
228 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
229
230 brw_set_default_access_mode(p, BRW_ALIGN_1);
231
232 if (inst->offset)
233 /* Set the texel offset bits in DWord 2. */
234 dw2 = inst->offset;
235
236 if (devinfo->gen >= 9)
237 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
238 * based on bit 22 in the header.
239 */
240 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
241
242 /* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
243 * so header0.2 is 0 when g0 is copied. The HS and GS stages do
244 * not, so we must set to to 0 to avoid setting undesirable bits
245 * in the message header.
246 */
247 if (dw2 ||
248 stage == MESA_SHADER_TESS_CTRL ||
249 stage == MESA_SHADER_GEOMETRY) {
250 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
251 }
252
253 brw_adjust_sampler_state_pointer(p, header, sampler_index);
254 brw_pop_insn_state(p);
255 }
256 }
257
258 uint32_t return_format;
259
260 switch (dst.type) {
261 case BRW_REGISTER_TYPE_D:
262 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
263 break;
264 case BRW_REGISTER_TYPE_UD:
265 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
266 break;
267 default:
268 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
269 break;
270 }
271
272 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
273 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
274 ? prog_data->base.binding_table.gather_texture_start
275 : prog_data->base.binding_table.texture_start;
276
277 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
278 sampler_index.file == BRW_IMMEDIATE_VALUE) {
279 uint32_t surface = surface_index.ud;
280 uint32_t sampler = sampler_index.ud;
281
282 brw_SAMPLE(p,
283 dst,
284 inst->base_mrf,
285 src,
286 surface + base_binding_table_index,
287 sampler % 16,
288 msg_type,
289 1, /* response length */
290 inst->mlen,
291 inst->header_size != 0,
292 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
293 return_format);
294
295 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
296 } else {
297 /* Non-constant sampler index. */
298
299 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
300 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
301 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
302
303 brw_push_insn_state(p);
304 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
305 brw_set_default_access_mode(p, BRW_ALIGN_1);
306
307 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
308 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
309 } else {
310 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
311 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
312 } else {
313 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
314 brw_OR(p, addr, addr, surface_reg);
315 }
316 }
317 if (base_binding_table_index)
318 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
319 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
320
321 brw_pop_insn_state(p);
322
323 if (inst->base_mrf != -1)
324 gen6_resolve_implied_move(p, &src, inst->base_mrf);
325
326 /* dst = send(offset, a0.0 | <descriptor>) */
327 brw_send_indirect_message(
328 p, BRW_SFID_SAMPLER, dst, src, addr,
329 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
330 brw_sampler_desc(devinfo,
331 0 /* surface */,
332 0 /* sampler */,
333 msg_type,
334 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
335 return_format));
336
337 /* visitor knows more than we do about the surface limit required,
338 * so has already done marking.
339 */
340 }
341 }
342
343 static void
344 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
345 {
346 brw_urb_WRITE(p,
347 brw_null_reg(), /* dest */
348 inst->base_mrf, /* starting mrf reg nr */
349 brw_vec8_grf(0, 0), /* src */
350 inst->urb_write_flags,
351 inst->mlen,
352 0, /* response len */
353 inst->offset, /* urb destination offset */
354 BRW_URB_SWIZZLE_INTERLEAVE);
355 }
356
357 static void
358 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
359 {
360 struct brw_reg src = brw_message_reg(inst->base_mrf);
361 brw_urb_WRITE(p,
362 brw_null_reg(), /* dest */
363 inst->base_mrf, /* starting mrf reg nr */
364 src,
365 inst->urb_write_flags,
366 inst->mlen,
367 0, /* response len */
368 inst->offset, /* urb destination offset */
369 BRW_URB_SWIZZLE_INTERLEAVE);
370 }
371
372 static void
373 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
374 {
375 struct brw_reg src = brw_message_reg(inst->base_mrf);
376
377 /* We pass the temporary passed in src0 as the writeback register */
378 brw_urb_WRITE(p,
379 inst->src[0].as_brw_reg(), /* dest */
380 inst->base_mrf, /* starting mrf reg nr */
381 src,
382 BRW_URB_WRITE_ALLOCATE_COMPLETE,
383 inst->mlen,
384 1, /* response len */
385 inst->offset, /* urb destination offset */
386 BRW_URB_SWIZZLE_INTERLEAVE);
387
388 /* Now put allocated urb handle in dst.0 */
389 brw_push_insn_state(p);
390 brw_set_default_access_mode(p, BRW_ALIGN_1);
391 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
392 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
393 get_element_ud(inst->src[0].as_brw_reg(), 0));
394 brw_pop_insn_state(p);
395 }
396
397 static void
398 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
399 {
400 struct brw_reg src = brw_message_reg(inst->base_mrf);
401 brw_urb_WRITE(p,
402 brw_null_reg(), /* dest */
403 inst->base_mrf, /* starting mrf reg nr */
404 src,
405 BRW_URB_WRITE_EOT | inst->urb_write_flags,
406 inst->mlen,
407 0, /* response len */
408 0, /* urb destination offset */
409 BRW_URB_SWIZZLE_INTERLEAVE);
410 }
411
412 static void
413 generate_gs_set_write_offset(struct brw_codegen *p,
414 struct brw_reg dst,
415 struct brw_reg src0,
416 struct brw_reg src1)
417 {
418 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
419 * Header: M0.3):
420 *
421 * Slot 0 Offset. This field, after adding to the Global Offset field
422 * in the message descriptor, specifies the offset (in 256-bit units)
423 * from the start of the URB entry, as referenced by URB Handle 0, at
424 * which the data will be accessed.
425 *
426 * Similar text describes DWORD M0.4, which is slot 1 offset.
427 *
428 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
429 * of the register for geometry shader invocations 0 and 1) by the
430 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
431 *
432 * We can do this with the following EU instruction:
433 *
434 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
435 */
436 brw_push_insn_state(p);
437 brw_set_default_access_mode(p, BRW_ALIGN_1);
438 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
439 assert(p->devinfo->gen >= 7 &&
440 src1.file == BRW_IMMEDIATE_VALUE &&
441 src1.type == BRW_REGISTER_TYPE_UD &&
442 src1.ud <= USHRT_MAX);
443 if (src0.file == BRW_IMMEDIATE_VALUE) {
444 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
445 brw_imm_ud(src0.ud * src1.ud));
446 } else {
447 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
448 retype(src1, BRW_REGISTER_TYPE_UW));
449 }
450 brw_pop_insn_state(p);
451 }
452
453 static void
454 generate_gs_set_vertex_count(struct brw_codegen *p,
455 struct brw_reg dst,
456 struct brw_reg src)
457 {
458 brw_push_insn_state(p);
459 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
460
461 if (p->devinfo->gen >= 8) {
462 /* Move the vertex count into the second MRF for the EOT write. */
463 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
464 src);
465 } else {
466 /* If we think of the src and dst registers as composed of 8 DWORDs each,
467 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
468 * them to WORDs, and then pack them into DWORD 2 of dst.
469 *
470 * It's easier to get the EU to do this if we think of the src and dst
471 * registers as composed of 16 WORDS each; then, we want to pick up the
472 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
473 * of dst.
474 *
475 * We can do that by the following EU instruction:
476 *
477 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
478 */
479 brw_set_default_access_mode(p, BRW_ALIGN_1);
480 brw_MOV(p,
481 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
482 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
483 }
484 brw_pop_insn_state(p);
485 }
486
487 static void
488 generate_gs_svb_write(struct brw_codegen *p,
489 struct brw_vue_prog_data *prog_data,
490 vec4_instruction *inst,
491 struct brw_reg dst,
492 struct brw_reg src0,
493 struct brw_reg src1)
494 {
495 int binding = inst->sol_binding;
496 bool final_write = inst->sol_final_write;
497
498 brw_push_insn_state(p);
499 brw_set_default_exec_size(p, BRW_EXECUTE_4);
500 /* Copy Vertex data into M0.x */
501 brw_MOV(p, stride(dst, 4, 4, 1),
502 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
503 brw_pop_insn_state(p);
504
505 brw_push_insn_state(p);
506 /* Send SVB Write */
507 brw_svb_write(p,
508 final_write ? src1 : brw_null_reg(), /* dest == src1 */
509 1, /* msg_reg_nr */
510 dst, /* src0 == previous dst */
511 BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */
512 final_write); /* send_commit_msg */
513
514 /* Finally, wait for the write commit to occur so that we can proceed to
515 * other things safely.
516 *
517 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
518 *
519 * The write commit does not modify the destination register, but
520 * merely clears the dependency associated with the destination
521 * register. Thus, a simple “mov” instruction using the register as a
522 * source is sufficient to wait for the write commit to occur.
523 */
524 if (final_write) {
525 brw_MOV(p, src1, src1);
526 }
527 brw_pop_insn_state(p);
528 }
529
530 static void
531 generate_gs_svb_set_destination_index(struct brw_codegen *p,
532 vec4_instruction *inst,
533 struct brw_reg dst,
534 struct brw_reg src)
535 {
536 int vertex = inst->sol_vertex;
537 brw_push_insn_state(p);
538 brw_set_default_access_mode(p, BRW_ALIGN_1);
539 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
540 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
541 brw_pop_insn_state(p);
542 }
543
544 static void
545 generate_gs_set_dword_2(struct brw_codegen *p,
546 struct brw_reg dst,
547 struct brw_reg src)
548 {
549 brw_push_insn_state(p);
550 brw_set_default_access_mode(p, BRW_ALIGN_1);
551 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
552 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
553 brw_pop_insn_state(p);
554 }
555
556 static void
557 generate_gs_prepare_channel_masks(struct brw_codegen *p,
558 struct brw_reg dst)
559 {
560 /* We want to left shift just DWORD 4 (the x component belonging to the
561 * second geometry shader invocation) by 4 bits. So generate the
562 * instruction:
563 *
564 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
565 */
566 dst = suboffset(vec1(dst), 4);
567 brw_push_insn_state(p);
568 brw_set_default_access_mode(p, BRW_ALIGN_1);
569 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
570 brw_SHL(p, dst, dst, brw_imm_ud(4));
571 brw_pop_insn_state(p);
572 }
573
574 static void
575 generate_gs_set_channel_masks(struct brw_codegen *p,
576 struct brw_reg dst,
577 struct brw_reg src)
578 {
579 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
580 * Header: M0.5):
581 *
582 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
583 *
584 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
585 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
586 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
587 * channel enable to determine the final channel enable. For the
588 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
589 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
590 * in the writeback message. For the URB_WRITE_OWORD &
591 * URB_WRITE_HWORD messages, when final channel enable is 1 it
592 * indicates that Vertex 1 DATA [3] will be written to the surface.
593 *
594 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
595 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
596 *
597 * 14 Vertex 1 DATA [2] Channel Mask
598 * 13 Vertex 1 DATA [1] Channel Mask
599 * 12 Vertex 1 DATA [0] Channel Mask
600 * 11 Vertex 0 DATA [3] Channel Mask
601 * 10 Vertex 0 DATA [2] Channel Mask
602 * 9 Vertex 0 DATA [1] Channel Mask
603 * 8 Vertex 0 DATA [0] Channel Mask
604 *
605 * (This is from a section of the PRM that is agnostic to the particular
606 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
607 * geometry shader invocations 0 and 1, respectively). Since we have the
608 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
609 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
610 * DWORD 4, we just need to OR them together and store the result in bits
611 * 15:8 of DWORD 5.
612 *
613 * It's easier to get the EU to do this if we think of the src and dst
614 * registers as composed of 32 bytes each; then, we want to pick up the
615 * contents of bytes 0 and 16 from src, OR them together, and store them in
616 * byte 21.
617 *
618 * We can do that by the following EU instruction:
619 *
620 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
621 *
622 * Note: this relies on the source register having zeros in (a) bits 7:4 of
623 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
624 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
625 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
626 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
627 * contain valid channel mask values (which are in the range 0x0-0xf).
628 */
629 dst = retype(dst, BRW_REGISTER_TYPE_UB);
630 src = retype(src, BRW_REGISTER_TYPE_UB);
631 brw_push_insn_state(p);
632 brw_set_default_access_mode(p, BRW_ALIGN_1);
633 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
634 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
635 brw_pop_insn_state(p);
636 }
637
638 static void
639 generate_gs_get_instance_id(struct brw_codegen *p,
640 struct brw_reg dst)
641 {
642 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
643 * and store into dst.0 & dst.4. So generate the instruction:
644 *
645 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
646 */
647 brw_push_insn_state(p);
648 brw_set_default_access_mode(p, BRW_ALIGN_1);
649 dst = retype(dst, BRW_REGISTER_TYPE_UD);
650 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
651 brw_SHR(p, dst, stride(r0, 1, 4, 0),
652 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
653 brw_pop_insn_state(p);
654 }
655
656 static void
657 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
658 struct brw_reg dst,
659 struct brw_reg src0,
660 struct brw_reg src1,
661 struct brw_reg src2)
662 {
663 brw_push_insn_state(p);
664 brw_set_default_access_mode(p, BRW_ALIGN_1);
665 /* Save src0 data in 16:31 bits of dst.0 */
666 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
667 brw_imm_ud(0xffffu));
668 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
669 /* Save src1 data in 0:15 bits of dst.0 */
670 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
671 brw_imm_ud(0xffffu));
672 brw_OR(p, suboffset(vec1(dst), 0),
673 suboffset(vec1(dst), 0),
674 suboffset(vec1(src2), 0));
675 brw_pop_insn_state(p);
676 }
677
678 static void
679 generate_gs_ff_sync(struct brw_codegen *p,
680 vec4_instruction *inst,
681 struct brw_reg dst,
682 struct brw_reg src0,
683 struct brw_reg src1)
684 {
685 /* This opcode uses an implied MRF register for:
686 * - the header of the ff_sync message. And as such it is expected to be
687 * initialized to r0 before calling here.
688 * - the destination where we will write the allocated URB handle.
689 */
690 struct brw_reg header =
691 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
692
693 /* Overwrite dword 0 of the header (SO vertices to write) and
694 * dword 1 (number of primitives written).
695 */
696 brw_push_insn_state(p);
697 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
698 brw_set_default_access_mode(p, BRW_ALIGN_1);
699 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
700 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
701 brw_pop_insn_state(p);
702
703 /* Allocate URB handle in dst */
704 brw_ff_sync(p,
705 dst,
706 0,
707 header,
708 1, /* allocate */
709 1, /* response length */
710 0 /* eot */);
711
712 /* Now put allocated urb handle in header.0 */
713 brw_push_insn_state(p);
714 brw_set_default_access_mode(p, BRW_ALIGN_1);
715 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
716 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
717
718 /* src1 is not an immediate when we use transform feedback */
719 if (src1.file != BRW_IMMEDIATE_VALUE) {
720 brw_set_default_exec_size(p, BRW_EXECUTE_4);
721 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
722 }
723
724 brw_pop_insn_state(p);
725 }
726
727 static void
728 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
729 {
730 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
731 struct brw_reg src = brw_vec8_grf(0, 0);
732 brw_push_insn_state(p);
733 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
734 brw_set_default_access_mode(p, BRW_ALIGN_1);
735 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
736 brw_pop_insn_state(p);
737 }
738
739 static void
740 generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
741 {
742 const struct gen_device_info *devinfo = p->devinfo;
743 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
744
745 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
746 *
747 * Since we operate in SIMD4x2 mode, we need run half as many threads
748 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
749 * shift right by one less to accomplish the multiplication by two.
750 */
751 dst = retype(dst, BRW_REGISTER_TYPE_UD);
752 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
753
754 brw_push_insn_state(p);
755 brw_set_default_access_mode(p, BRW_ALIGN_1);
756
757 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
758 const int shift = ivb ? 16 : 17;
759
760 brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
761 brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
762 brw_imm_ud(shift - 1));
763 brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
764
765 brw_pop_insn_state(p);
766 }
767
768 static void
769 generate_tcs_urb_write(struct brw_codegen *p,
770 vec4_instruction *inst,
771 struct brw_reg urb_header)
772 {
773 const struct gen_device_info *devinfo = p->devinfo;
774
775 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
776 brw_set_dest(p, send, brw_null_reg());
777 brw_set_src0(p, send, urb_header);
778 brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
779
780 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
781 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
782 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
783 if (inst->urb_write_flags & BRW_URB_WRITE_EOT) {
784 brw_inst_set_eot(devinfo, send, 1);
785 } else {
786 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
787 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
788 }
789
790 /* what happens to swizzles? */
791 }
792
793
794 static void
795 generate_tcs_input_urb_offsets(struct brw_codegen *p,
796 struct brw_reg dst,
797 struct brw_reg vertex,
798 struct brw_reg offset)
799 {
800 /* Generates an URB read/write message header for HS/DS operation.
801 * Inputs are a vertex index, and a byte offset from the beginning of
802 * the vertex. */
803
804 /* If `vertex` is not an immediate, we clobber a0.0 */
805
806 assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
807 assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
808
809 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
810
811 brw_push_insn_state(p);
812 brw_set_default_access_mode(p, BRW_ALIGN_1);
813 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
814 brw_MOV(p, dst, brw_imm_ud(0));
815
816 /* m0.5 bits 8-15 are channel enables */
817 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
818
819 /* m0.0-0.1: URB handles */
820 if (vertex.file == BRW_IMMEDIATE_VALUE) {
821 uint32_t vertex_index = vertex.ud;
822 struct brw_reg index_reg = brw_vec1_grf(
823 1 + (vertex_index >> 3), vertex_index & 7);
824
825 brw_MOV(p, vec2(get_element_ud(dst, 0)),
826 retype(index_reg, BRW_REGISTER_TYPE_UD));
827 } else {
828 /* Use indirect addressing. ICP Handles are DWords (single channels
829 * of a register) and start at g1.0.
830 *
831 * In order to start our region at g1.0, we add 8 to the vertex index,
832 * effectively skipping over the 8 channels in g0.0. This gives us a
833 * DWord offset to the ICP Handle.
834 *
835 * Indirect addressing works in terms of bytes, so we then multiply
836 * the DWord offset by 4 (by shifting left by 2).
837 */
838 struct brw_reg addr = brw_address_reg(0);
839
840 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
841 brw_ADD(p, addr, retype(get_element_ud(vertex, 0), BRW_REGISTER_TYPE_UW),
842 brw_imm_uw(0x8));
843 brw_SHL(p, addr, addr, brw_imm_uw(2));
844 brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
845
846 /* top half: m0.1 = g[1.0 + vertex.4]UD */
847 brw_ADD(p, addr, retype(get_element_ud(vertex, 4), BRW_REGISTER_TYPE_UW),
848 brw_imm_uw(0x8));
849 brw_SHL(p, addr, addr, brw_imm_uw(2));
850 brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
851 }
852
853 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
854 if (offset.file != ARF)
855 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
856
857 brw_pop_insn_state(p);
858 }
859
860
861 static void
862 generate_tcs_output_urb_offsets(struct brw_codegen *p,
863 struct brw_reg dst,
864 struct brw_reg write_mask,
865 struct brw_reg offset)
866 {
867 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
868 assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
869
870 assert(write_mask.file == BRW_IMMEDIATE_VALUE);
871 assert(write_mask.type == BRW_REGISTER_TYPE_UD);
872
873 brw_push_insn_state(p);
874
875 brw_set_default_access_mode(p, BRW_ALIGN_1);
876 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
877 brw_MOV(p, dst, brw_imm_ud(0));
878
879 unsigned mask = write_mask.ud;
880
881 /* m0.5 bits 15:12 and 11:8 are channel enables */
882 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
883
884 /* HS patch URB handle is delivered in r0.0 */
885 struct brw_reg urb_handle = brw_vec1_grf(0, 0);
886
887 /* m0.0-0.1: URB handles */
888 brw_MOV(p, vec2(get_element_ud(dst, 0)),
889 retype(urb_handle, BRW_REGISTER_TYPE_UD));
890
891 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
892 if (offset.file != ARF)
893 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
894
895 brw_pop_insn_state(p);
896 }
897
898 static void
899 generate_tes_create_input_read_header(struct brw_codegen *p,
900 struct brw_reg dst)
901 {
902 brw_push_insn_state(p);
903 brw_set_default_access_mode(p, BRW_ALIGN_1);
904 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
905
906 /* Initialize the register to 0 */
907 brw_MOV(p, dst, brw_imm_ud(0));
908
909 /* Enable all the channels in m0.5 bits 15:8 */
910 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
911
912 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
913 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
914 */
915 brw_AND(p, vec2(get_element_ud(dst, 0)),
916 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
917 brw_imm_ud(0x1fff));
918 brw_pop_insn_state(p);
919 }
920
921 static void
922 generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
923 struct brw_reg dst,
924 struct brw_reg header,
925 struct brw_reg offset)
926 {
927 brw_push_insn_state(p);
928 brw_set_default_access_mode(p, BRW_ALIGN_1);
929 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
930
931 brw_MOV(p, dst, header);
932
933 /* Uniforms will have a stride <0;4,1>, and we need to convert to <0;1,0>.
934 * Other values get <4;1,0>.
935 */
936 struct brw_reg restrided_offset;
937 if (offset.vstride == BRW_VERTICAL_STRIDE_0 &&
938 offset.width == BRW_WIDTH_4 &&
939 offset.hstride == BRW_HORIZONTAL_STRIDE_1) {
940 restrided_offset = stride(offset, 0, 1, 0);
941 } else {
942 restrided_offset = stride(offset, 4, 1, 0);
943 }
944
945 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
946 brw_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset);
947
948 brw_pop_insn_state(p);
949 }
950
951 static void
952 generate_vec4_urb_read(struct brw_codegen *p,
953 vec4_instruction *inst,
954 struct brw_reg dst,
955 struct brw_reg header)
956 {
957 const struct gen_device_info *devinfo = p->devinfo;
958
959 assert(header.file == BRW_GENERAL_REGISTER_FILE);
960 assert(header.type == BRW_REGISTER_TYPE_UD);
961
962 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
963 brw_set_dest(p, send, dst);
964 brw_set_src0(p, send, header);
965
966 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 1, true));
967
968 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
969 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
970 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
971 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
972
973 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
974 }
975
976 static void
977 generate_tcs_release_input(struct brw_codegen *p,
978 struct brw_reg header,
979 struct brw_reg vertex,
980 struct brw_reg is_unpaired)
981 {
982 const struct gen_device_info *devinfo = p->devinfo;
983
984 assert(vertex.file == BRW_IMMEDIATE_VALUE);
985 assert(vertex.type == BRW_REGISTER_TYPE_UD);
986
987 /* m0.0-0.1: URB handles */
988 struct brw_reg urb_handles =
989 retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7),
990 BRW_REGISTER_TYPE_UD);
991
992 brw_push_insn_state(p);
993 brw_set_default_access_mode(p, BRW_ALIGN_1);
994 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
995 brw_MOV(p, header, brw_imm_ud(0));
996 brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles);
997 brw_pop_insn_state(p);
998
999 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1000 brw_set_dest(p, send, brw_null_reg());
1001 brw_set_src0(p, send, header);
1002 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 0, true));
1003
1004 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
1005 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
1006 brw_inst_set_urb_complete(devinfo, send, 1);
1007 brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ?
1008 BRW_URB_SWIZZLE_NONE :
1009 BRW_URB_SWIZZLE_INTERLEAVE);
1010 }
1011
1012 static void
1013 generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
1014 {
1015 struct brw_reg header = brw_message_reg(inst->base_mrf);
1016
1017 brw_push_insn_state(p);
1018 brw_set_default_access_mode(p, BRW_ALIGN_1);
1019 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1020 brw_MOV(p, header, brw_imm_ud(0));
1021 brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
1022 brw_MOV(p, get_element_ud(header, 0),
1023 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
1024 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
1025 brw_pop_insn_state(p);
1026
1027 brw_urb_WRITE(p,
1028 brw_null_reg(), /* dest */
1029 inst->base_mrf, /* starting mrf reg nr */
1030 header,
1031 BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
1032 BRW_URB_WRITE_USE_CHANNEL_MASKS,
1033 inst->mlen,
1034 0, /* response len */
1035 0, /* urb destination offset */
1036 0);
1037 }
1038
1039 static void
1040 generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1041 {
1042 brw_push_insn_state(p);
1043 brw_set_default_access_mode(p, BRW_ALIGN_1);
1044 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
1045 brw_pop_insn_state(p);
1046 }
1047
1048 static void
1049 generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1050 {
1051 brw_push_insn_state(p);
1052 brw_set_default_access_mode(p, BRW_ALIGN_1);
1053 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
1054 brw_pop_insn_state(p);
1055 }
1056
1057 static void
1058 generate_tcs_create_barrier_header(struct brw_codegen *p,
1059 struct brw_vue_prog_data *prog_data,
1060 struct brw_reg dst)
1061 {
1062 const struct gen_device_info *devinfo = p->devinfo;
1063 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
1064 struct brw_reg m0_2 = get_element_ud(dst, 2);
1065 unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
1066
1067 brw_push_insn_state(p);
1068 brw_set_default_access_mode(p, BRW_ALIGN_1);
1069 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1070
1071 /* Zero the message header */
1072 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
1073
1074 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1075 brw_AND(p, m0_2,
1076 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
1077 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1078
1079 /* Shift it up to bits 27:24. */
1080 brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11));
1081
1082 /* Set the Barrier Count and the enable bit */
1083 brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
1084
1085 brw_pop_insn_state(p);
1086 }
1087
1088 static void
1089 generate_oword_dual_block_offsets(struct brw_codegen *p,
1090 struct brw_reg m1,
1091 struct brw_reg index)
1092 {
1093 int second_vertex_offset;
1094
1095 if (p->devinfo->gen >= 6)
1096 second_vertex_offset = 1;
1097 else
1098 second_vertex_offset = 16;
1099
1100 m1 = retype(m1, BRW_REGISTER_TYPE_D);
1101
1102 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1103 * M1.4 are used, and the rest are ignored.
1104 */
1105 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
1106 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
1107 struct brw_reg index_0 = suboffset(vec1(index), 0);
1108 struct brw_reg index_4 = suboffset(vec1(index), 4);
1109
1110 brw_push_insn_state(p);
1111 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1112 brw_set_default_access_mode(p, BRW_ALIGN_1);
1113
1114 brw_MOV(p, m1_0, index_0);
1115
1116 if (index.file == BRW_IMMEDIATE_VALUE) {
1117 index_4.ud += second_vertex_offset;
1118 brw_MOV(p, m1_4, index_4);
1119 } else {
1120 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
1121 }
1122
1123 brw_pop_insn_state(p);
1124 }
1125
1126 static void
1127 generate_unpack_flags(struct brw_codegen *p,
1128 struct brw_reg dst)
1129 {
1130 brw_push_insn_state(p);
1131 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1132 brw_set_default_access_mode(p, BRW_ALIGN_1);
1133
1134 struct brw_reg flags = brw_flag_reg(0, 0);
1135 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
1136 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
1137
1138 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
1139 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
1140 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
1141
1142 brw_pop_insn_state(p);
1143 }
1144
1145 static void
1146 generate_scratch_read(struct brw_codegen *p,
1147 vec4_instruction *inst,
1148 struct brw_reg dst,
1149 struct brw_reg index)
1150 {
1151 const struct gen_device_info *devinfo = p->devinfo;
1152 struct brw_reg header = brw_vec8_grf(0, 0);
1153
1154 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1155
1156 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1157 index);
1158
1159 uint32_t msg_type;
1160
1161 if (devinfo->gen >= 6)
1162 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1163 else if (devinfo->gen == 5 || devinfo->is_g4x)
1164 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1165 else
1166 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1167
1168 const unsigned target_cache =
1169 devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1170 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1171 BRW_SFID_DATAPORT_READ;
1172
1173 /* Each of the 8 channel enables is considered for whether each
1174 * dword is written.
1175 */
1176 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1177 brw_inst_set_sfid(devinfo, send, target_cache);
1178 brw_set_dest(p, send, dst);
1179 brw_set_src0(p, send, header);
1180 if (devinfo->gen < 6)
1181 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
1182 brw_set_desc(p, send,
1183 brw_message_desc(devinfo, 2, 1, true) |
1184 brw_dp_read_desc(devinfo,
1185 brw_scratch_surface_idx(p),
1186 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1187 msg_type, BRW_DATAPORT_READ_TARGET_RENDER_CACHE));
1188 }
1189
1190 static void
1191 generate_scratch_write(struct brw_codegen *p,
1192 vec4_instruction *inst,
1193 struct brw_reg dst,
1194 struct brw_reg src,
1195 struct brw_reg index)
1196 {
1197 const struct gen_device_info *devinfo = p->devinfo;
1198 const unsigned target_cache =
1199 (devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1200 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1201 BRW_SFID_DATAPORT_WRITE);
1202 struct brw_reg header = brw_vec8_grf(0, 0);
1203 bool write_commit;
1204
1205 /* If the instruction is predicated, we'll predicate the send, not
1206 * the header setup.
1207 */
1208 brw_set_default_predicate_control(p, false);
1209
1210 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1211
1212 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1213 index);
1214
1215 brw_MOV(p,
1216 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
1217 retype(src, BRW_REGISTER_TYPE_D));
1218
1219 uint32_t msg_type;
1220
1221 if (devinfo->gen >= 7)
1222 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
1223 else if (devinfo->gen == 6)
1224 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1225 else
1226 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1227
1228 brw_set_default_predicate_control(p, inst->predicate);
1229
1230 /* Pre-gen6, we have to specify write commits to ensure ordering
1231 * between reads and writes within a thread. Afterwards, that's
1232 * guaranteed and write commits only matter for inter-thread
1233 * synchronization.
1234 */
1235 if (devinfo->gen >= 6) {
1236 write_commit = false;
1237 } else {
1238 /* The visitor set up our destination register to be g0. This
1239 * means that when the next read comes along, we will end up
1240 * reading from g0 and causing a block on the write commit. For
1241 * write-after-read, we are relying on the value of the previous
1242 * read being used (and thus blocking on completion) before our
1243 * write is executed. This means we have to be careful in
1244 * instruction scheduling to not violate this assumption.
1245 */
1246 write_commit = true;
1247 }
1248
1249 /* Each of the 8 channel enables is considered for whether each
1250 * dword is written.
1251 */
1252 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1253 brw_inst_set_sfid(p->devinfo, send, target_cache);
1254 brw_set_dest(p, send, dst);
1255 brw_set_src0(p, send, header);
1256 if (devinfo->gen < 6)
1257 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1258 brw_set_desc(p, send,
1259 brw_message_desc(devinfo, 3, write_commit, true) |
1260 brw_dp_write_desc(devinfo,
1261 brw_scratch_surface_idx(p),
1262 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1263 msg_type,
1264 false, /* not a render target write */
1265 write_commit));
1266 }
1267
1268 static void
1269 generate_pull_constant_load(struct brw_codegen *p,
1270 struct brw_vue_prog_data *prog_data,
1271 vec4_instruction *inst,
1272 struct brw_reg dst,
1273 struct brw_reg index,
1274 struct brw_reg offset)
1275 {
1276 const struct gen_device_info *devinfo = p->devinfo;
1277 const unsigned target_cache =
1278 (devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE :
1279 BRW_SFID_DATAPORT_READ);
1280 assert(index.file == BRW_IMMEDIATE_VALUE &&
1281 index.type == BRW_REGISTER_TYPE_UD);
1282 uint32_t surf_index = index.ud;
1283
1284 struct brw_reg header = brw_vec8_grf(0, 0);
1285
1286 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1287
1288 if (devinfo->gen >= 6) {
1289 if (offset.file == BRW_IMMEDIATE_VALUE) {
1290 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1291 BRW_REGISTER_TYPE_D),
1292 brw_imm_d(offset.ud >> 4));
1293 } else {
1294 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
1295 BRW_REGISTER_TYPE_D),
1296 offset, brw_imm_d(4));
1297 }
1298 } else {
1299 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1300 BRW_REGISTER_TYPE_D),
1301 offset);
1302 }
1303
1304 uint32_t msg_type;
1305
1306 if (devinfo->gen >= 6)
1307 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1308 else if (devinfo->gen == 5 || devinfo->is_g4x)
1309 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1310 else
1311 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1312
1313 /* Each of the 8 channel enables is considered for whether each
1314 * dword is written.
1315 */
1316 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1317 brw_inst_set_sfid(devinfo, send, target_cache);
1318 brw_set_dest(p, send, dst);
1319 brw_set_src0(p, send, header);
1320 if (devinfo->gen < 6)
1321 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1322 brw_set_desc(p, send,
1323 brw_message_desc(devinfo, 2, 1, true) |
1324 brw_dp_read_desc(devinfo, surf_index,
1325 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1326 msg_type,
1327 BRW_DATAPORT_READ_TARGET_DATA_CACHE));
1328 }
1329
1330 static void
1331 generate_get_buffer_size(struct brw_codegen *p,
1332 struct brw_vue_prog_data *prog_data,
1333 vec4_instruction *inst,
1334 struct brw_reg dst,
1335 struct brw_reg src,
1336 struct brw_reg surf_index)
1337 {
1338 assert(p->devinfo->gen >= 7);
1339 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
1340 surf_index.file == BRW_IMMEDIATE_VALUE);
1341
1342 brw_SAMPLE(p,
1343 dst,
1344 inst->base_mrf,
1345 src,
1346 surf_index.ud,
1347 0,
1348 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1349 1, /* response length */
1350 inst->mlen,
1351 inst->header_size > 0,
1352 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1353 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1354
1355 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1356 }
1357
1358 static void
1359 generate_pull_constant_load_gen7(struct brw_codegen *p,
1360 struct brw_vue_prog_data *prog_data,
1361 vec4_instruction *inst,
1362 struct brw_reg dst,
1363 struct brw_reg surf_index,
1364 struct brw_reg offset)
1365 {
1366 const struct gen_device_info *devinfo = p->devinfo;
1367 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1368
1369 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1370
1371 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1372 brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
1373 brw_set_dest(p, insn, dst);
1374 brw_set_src0(p, insn, offset);
1375 brw_set_desc(p, insn,
1376 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1377 brw_sampler_desc(devinfo, surf_index.ud,
1378 0, /* LD message ignores sampler unit */
1379 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1380 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0));
1381
1382 brw_mark_surface_used(&prog_data->base, surf_index.ud);
1383
1384 } else {
1385
1386 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1387
1388 brw_push_insn_state(p);
1389 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1390 brw_set_default_access_mode(p, BRW_ALIGN_1);
1391
1392 /* a0.0 = surf_index & 0xff */
1393 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1394 brw_inst_set_exec_size(devinfo, insn_and, BRW_EXECUTE_1);
1395 brw_set_dest(p, insn_and, addr);
1396 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1397 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1398
1399 brw_pop_insn_state(p);
1400
1401 /* dst = send(offset, a0.0 | <descriptor>) */
1402 brw_send_indirect_message(
1403 p, BRW_SFID_SAMPLER, dst, offset, addr,
1404 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1405 brw_sampler_desc(devinfo,
1406 0 /* surface */,
1407 0 /* sampler */,
1408 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1409 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1410 0));
1411 }
1412 }
1413
1414 static void
1415 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1416 vec4_instruction *,
1417 struct brw_reg dst)
1418 {
1419 brw_push_insn_state(p);
1420 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1421
1422 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1423 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1424
1425 brw_set_default_access_mode(p, BRW_ALIGN_1);
1426 brw_MOV(p, get_element_ud(dst, 2),
1427 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1428
1429 brw_pop_insn_state(p);
1430 }
1431
1432 static void
1433 generate_mov_indirect(struct brw_codegen *p,
1434 vec4_instruction *,
1435 struct brw_reg dst, struct brw_reg reg,
1436 struct brw_reg indirect)
1437 {
1438 assert(indirect.type == BRW_REGISTER_TYPE_UD);
1439 assert(p->devinfo->gen >= 6);
1440
1441 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1442
1443 /* This instruction acts in align1 mode */
1444 assert(dst.writemask == WRITEMASK_XYZW);
1445
1446 if (indirect.file == BRW_IMMEDIATE_VALUE) {
1447 imm_byte_offset += indirect.ud;
1448
1449 reg.nr = imm_byte_offset / REG_SIZE;
1450 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
1451 unsigned shift = (imm_byte_offset / 4) % 4;
1452 reg.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift);
1453
1454 brw_MOV(p, dst, reg);
1455 } else {
1456 brw_push_insn_state(p);
1457 brw_set_default_access_mode(p, BRW_ALIGN_1);
1458 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1459
1460 struct brw_reg addr = vec8(brw_address_reg(0));
1461
1462 /* We need to move the indirect value into the address register. In
1463 * order to make things make some sense, we want to respect at least the
1464 * X component of the swizzle. In order to do that, we need to convert
1465 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1466 */
1467 assert(brw_is_single_value_swizzle(indirect.swizzle));
1468 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
1469
1470 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1471 * the indirect and splat it out to all four channels of the given half
1472 * of a0.
1473 */
1474 indirect.subnr *= 2;
1475 indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0);
1476 brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset));
1477
1478 /* Now we need to incorporate the swizzle from the source register */
1479 if (reg.swizzle != BRW_SWIZZLE_XXXX) {
1480 uint32_t uv_swiz = BRW_GET_SWZ(reg.swizzle, 0) << 2 |
1481 BRW_GET_SWZ(reg.swizzle, 1) << 6 |
1482 BRW_GET_SWZ(reg.swizzle, 2) << 10 |
1483 BRW_GET_SWZ(reg.swizzle, 3) << 14;
1484 uv_swiz |= uv_swiz << 16;
1485
1486 brw_ADD(p, addr, addr, brw_imm_uv(uv_swiz));
1487 }
1488
1489 brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), reg.type));
1490
1491 brw_pop_insn_state(p);
1492 }
1493 }
1494
1495 static void
1496 generate_code(struct brw_codegen *p,
1497 const struct brw_compiler *compiler,
1498 void *log_data,
1499 const nir_shader *nir,
1500 struct brw_vue_prog_data *prog_data,
1501 const struct cfg_t *cfg)
1502 {
1503 const struct gen_device_info *devinfo = p->devinfo;
1504 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
1505 bool debug_flag = INTEL_DEBUG &
1506 intel_debug_flag_for_shader_stage(nir->info.stage);
1507 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1508 int spill_count = 0, fill_count = 0;
1509 int loop_count = 0;
1510
1511 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1512 struct brw_reg src[3], dst;
1513
1514 if (unlikely(debug_flag))
1515 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1516
1517 for (unsigned int i = 0; i < 3; i++) {
1518 src[i] = inst->src[i].as_brw_reg();
1519 }
1520 dst = inst->dst.as_brw_reg();
1521
1522 brw_set_default_predicate_control(p, inst->predicate);
1523 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1524 brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
1525 brw_set_default_saturate(p, inst->saturate);
1526 brw_set_default_mask_control(p, inst->force_writemask_all);
1527 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1528
1529 assert(inst->group % inst->exec_size == 0);
1530 assert(inst->group % 4 == 0);
1531
1532 /* There are some instructions where the destination is 64-bit
1533 * but we retype it to a smaller type. In that case, we cannot
1534 * double the exec_size.
1535 */
1536 const bool is_df = (get_exec_type_size(inst) == 8 ||
1537 inst->dst.type == BRW_REGISTER_TYPE_DF) &&
1538 inst->opcode != VEC4_OPCODE_PICK_LOW_32BIT &&
1539 inst->opcode != VEC4_OPCODE_PICK_HIGH_32BIT &&
1540 inst->opcode != VEC4_OPCODE_SET_LOW_32BIT &&
1541 inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
1542
1543 unsigned exec_size = inst->exec_size;
1544 if (devinfo->gen == 7 && !devinfo->is_haswell && is_df)
1545 exec_size *= 2;
1546
1547 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1548
1549 if (!inst->force_writemask_all)
1550 brw_set_default_group(p, inst->group);
1551
1552 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1553 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1554
1555 unsigned pre_emit_nr_insn = p->nr_insn;
1556
1557 switch (inst->opcode) {
1558 case VEC4_OPCODE_UNPACK_UNIFORM:
1559 case BRW_OPCODE_MOV:
1560 brw_MOV(p, dst, src[0]);
1561 break;
1562 case BRW_OPCODE_ADD:
1563 brw_ADD(p, dst, src[0], src[1]);
1564 break;
1565 case BRW_OPCODE_MUL:
1566 brw_MUL(p, dst, src[0], src[1]);
1567 break;
1568 case BRW_OPCODE_MACH:
1569 brw_MACH(p, dst, src[0], src[1]);
1570 break;
1571
1572 case BRW_OPCODE_MAD:
1573 assert(devinfo->gen >= 6);
1574 brw_MAD(p, dst, src[0], src[1], src[2]);
1575 break;
1576
1577 case BRW_OPCODE_FRC:
1578 brw_FRC(p, dst, src[0]);
1579 break;
1580 case BRW_OPCODE_RNDD:
1581 brw_RNDD(p, dst, src[0]);
1582 break;
1583 case BRW_OPCODE_RNDE:
1584 brw_RNDE(p, dst, src[0]);
1585 break;
1586 case BRW_OPCODE_RNDZ:
1587 brw_RNDZ(p, dst, src[0]);
1588 break;
1589
1590 case BRW_OPCODE_AND:
1591 brw_AND(p, dst, src[0], src[1]);
1592 break;
1593 case BRW_OPCODE_OR:
1594 brw_OR(p, dst, src[0], src[1]);
1595 break;
1596 case BRW_OPCODE_XOR:
1597 brw_XOR(p, dst, src[0], src[1]);
1598 break;
1599 case BRW_OPCODE_NOT:
1600 brw_NOT(p, dst, src[0]);
1601 break;
1602 case BRW_OPCODE_ASR:
1603 brw_ASR(p, dst, src[0], src[1]);
1604 break;
1605 case BRW_OPCODE_SHR:
1606 brw_SHR(p, dst, src[0], src[1]);
1607 break;
1608 case BRW_OPCODE_SHL:
1609 brw_SHL(p, dst, src[0], src[1]);
1610 break;
1611
1612 case BRW_OPCODE_CMP:
1613 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1614 break;
1615 case BRW_OPCODE_SEL:
1616 brw_SEL(p, dst, src[0], src[1]);
1617 break;
1618
1619 case BRW_OPCODE_DPH:
1620 brw_DPH(p, dst, src[0], src[1]);
1621 break;
1622
1623 case BRW_OPCODE_DP4:
1624 brw_DP4(p, dst, src[0], src[1]);
1625 break;
1626
1627 case BRW_OPCODE_DP3:
1628 brw_DP3(p, dst, src[0], src[1]);
1629 break;
1630
1631 case BRW_OPCODE_DP2:
1632 brw_DP2(p, dst, src[0], src[1]);
1633 break;
1634
1635 case BRW_OPCODE_F32TO16:
1636 assert(devinfo->gen >= 7);
1637 brw_F32TO16(p, dst, src[0]);
1638 break;
1639
1640 case BRW_OPCODE_F16TO32:
1641 assert(devinfo->gen >= 7);
1642 brw_F16TO32(p, dst, src[0]);
1643 break;
1644
1645 case BRW_OPCODE_LRP:
1646 assert(devinfo->gen >= 6);
1647 brw_LRP(p, dst, src[0], src[1], src[2]);
1648 break;
1649
1650 case BRW_OPCODE_BFREV:
1651 assert(devinfo->gen >= 7);
1652 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1653 retype(src[0], BRW_REGISTER_TYPE_UD));
1654 break;
1655 case BRW_OPCODE_FBH:
1656 assert(devinfo->gen >= 7);
1657 brw_FBH(p, retype(dst, src[0].type), src[0]);
1658 break;
1659 case BRW_OPCODE_FBL:
1660 assert(devinfo->gen >= 7);
1661 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
1662 retype(src[0], BRW_REGISTER_TYPE_UD));
1663 break;
1664 case BRW_OPCODE_LZD:
1665 brw_LZD(p, dst, src[0]);
1666 break;
1667 case BRW_OPCODE_CBIT:
1668 assert(devinfo->gen >= 7);
1669 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
1670 retype(src[0], BRW_REGISTER_TYPE_UD));
1671 break;
1672 case BRW_OPCODE_ADDC:
1673 assert(devinfo->gen >= 7);
1674 brw_ADDC(p, dst, src[0], src[1]);
1675 break;
1676 case BRW_OPCODE_SUBB:
1677 assert(devinfo->gen >= 7);
1678 brw_SUBB(p, dst, src[0], src[1]);
1679 break;
1680 case BRW_OPCODE_MAC:
1681 brw_MAC(p, dst, src[0], src[1]);
1682 break;
1683
1684 case BRW_OPCODE_BFE:
1685 assert(devinfo->gen >= 7);
1686 brw_BFE(p, dst, src[0], src[1], src[2]);
1687 break;
1688
1689 case BRW_OPCODE_BFI1:
1690 assert(devinfo->gen >= 7);
1691 brw_BFI1(p, dst, src[0], src[1]);
1692 break;
1693 case BRW_OPCODE_BFI2:
1694 assert(devinfo->gen >= 7);
1695 brw_BFI2(p, dst, src[0], src[1], src[2]);
1696 break;
1697
1698 case BRW_OPCODE_IF:
1699 if (!inst->src[0].is_null()) {
1700 /* The instruction has an embedded compare (only allowed on gen6) */
1701 assert(devinfo->gen == 6);
1702 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1703 } else {
1704 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1705 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1706 }
1707 break;
1708
1709 case BRW_OPCODE_ELSE:
1710 brw_ELSE(p);
1711 break;
1712 case BRW_OPCODE_ENDIF:
1713 brw_ENDIF(p);
1714 break;
1715
1716 case BRW_OPCODE_DO:
1717 brw_DO(p, BRW_EXECUTE_8);
1718 break;
1719
1720 case BRW_OPCODE_BREAK:
1721 brw_BREAK(p);
1722 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1723 break;
1724 case BRW_OPCODE_CONTINUE:
1725 brw_CONT(p);
1726 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1727 break;
1728
1729 case BRW_OPCODE_WHILE:
1730 brw_WHILE(p);
1731 loop_count++;
1732 break;
1733
1734 case SHADER_OPCODE_RCP:
1735 case SHADER_OPCODE_RSQ:
1736 case SHADER_OPCODE_SQRT:
1737 case SHADER_OPCODE_EXP2:
1738 case SHADER_OPCODE_LOG2:
1739 case SHADER_OPCODE_SIN:
1740 case SHADER_OPCODE_COS:
1741 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1742 if (devinfo->gen >= 7) {
1743 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1744 brw_null_reg());
1745 } else if (devinfo->gen == 6) {
1746 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1747 } else {
1748 generate_math1_gen4(p, inst, dst, src[0]);
1749 }
1750 break;
1751
1752 case SHADER_OPCODE_POW:
1753 case SHADER_OPCODE_INT_QUOTIENT:
1754 case SHADER_OPCODE_INT_REMAINDER:
1755 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1756 if (devinfo->gen >= 7) {
1757 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1758 } else if (devinfo->gen == 6) {
1759 generate_math_gen6(p, inst, dst, src[0], src[1]);
1760 } else {
1761 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1762 }
1763 break;
1764
1765 case SHADER_OPCODE_TEX:
1766 case SHADER_OPCODE_TXD:
1767 case SHADER_OPCODE_TXF:
1768 case SHADER_OPCODE_TXF_CMS:
1769 case SHADER_OPCODE_TXF_CMS_W:
1770 case SHADER_OPCODE_TXF_MCS:
1771 case SHADER_OPCODE_TXL:
1772 case SHADER_OPCODE_TXS:
1773 case SHADER_OPCODE_TG4:
1774 case SHADER_OPCODE_TG4_OFFSET:
1775 case SHADER_OPCODE_SAMPLEINFO:
1776 generate_tex(p, prog_data, nir->info.stage,
1777 inst, dst, src[0], src[1], src[2]);
1778 break;
1779
1780 case SHADER_OPCODE_GET_BUFFER_SIZE:
1781 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1782 break;
1783
1784 case VS_OPCODE_URB_WRITE:
1785 generate_vs_urb_write(p, inst);
1786 break;
1787
1788 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1789 generate_scratch_read(p, inst, dst, src[0]);
1790 fill_count++;
1791 break;
1792
1793 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1794 generate_scratch_write(p, inst, dst, src[0], src[1]);
1795 spill_count++;
1796 break;
1797
1798 case VS_OPCODE_PULL_CONSTANT_LOAD:
1799 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1800 break;
1801
1802 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1803 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1804 break;
1805
1806 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1807 generate_set_simd4x2_header_gen9(p, inst, dst);
1808 break;
1809
1810 case GS_OPCODE_URB_WRITE:
1811 generate_gs_urb_write(p, inst);
1812 break;
1813
1814 case GS_OPCODE_URB_WRITE_ALLOCATE:
1815 generate_gs_urb_write_allocate(p, inst);
1816 break;
1817
1818 case GS_OPCODE_SVB_WRITE:
1819 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1820 break;
1821
1822 case GS_OPCODE_SVB_SET_DST_INDEX:
1823 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1824 break;
1825
1826 case GS_OPCODE_THREAD_END:
1827 generate_gs_thread_end(p, inst);
1828 break;
1829
1830 case GS_OPCODE_SET_WRITE_OFFSET:
1831 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1832 break;
1833
1834 case GS_OPCODE_SET_VERTEX_COUNT:
1835 generate_gs_set_vertex_count(p, dst, src[0]);
1836 break;
1837
1838 case GS_OPCODE_FF_SYNC:
1839 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1840 break;
1841
1842 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1843 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1844 break;
1845
1846 case GS_OPCODE_SET_PRIMITIVE_ID:
1847 generate_gs_set_primitive_id(p, dst);
1848 break;
1849
1850 case GS_OPCODE_SET_DWORD_2:
1851 generate_gs_set_dword_2(p, dst, src[0]);
1852 break;
1853
1854 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1855 generate_gs_prepare_channel_masks(p, dst);
1856 break;
1857
1858 case GS_OPCODE_SET_CHANNEL_MASKS:
1859 generate_gs_set_channel_masks(p, dst, src[0]);
1860 break;
1861
1862 case GS_OPCODE_GET_INSTANCE_ID:
1863 generate_gs_get_instance_id(p, dst);
1864 break;
1865
1866 case SHADER_OPCODE_SHADER_TIME_ADD:
1867 brw_shader_time_add(p, src[0],
1868 prog_data->base.binding_table.shader_time_start);
1869 brw_mark_surface_used(&prog_data->base,
1870 prog_data->base.binding_table.shader_time_start);
1871 break;
1872
1873 case SHADER_OPCODE_UNTYPED_ATOMIC:
1874 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1875 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1876 !inst->dst.is_null(), inst->header_size);
1877 break;
1878
1879 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1880 assert(!inst->header_size);
1881 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1882 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1883 src[2].ud);
1884 break;
1885
1886 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1887 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1888 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1889 src[2].ud, inst->header_size);
1890 break;
1891
1892 case SHADER_OPCODE_TYPED_ATOMIC:
1893 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1894 brw_typed_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1895 !inst->dst.is_null(), inst->header_size);
1896 break;
1897
1898 case SHADER_OPCODE_TYPED_SURFACE_READ:
1899 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1900 brw_typed_surface_read(p, dst, src[0], src[1], inst->mlen,
1901 src[2].ud, inst->header_size);
1902 break;
1903
1904 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1905 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1906 brw_typed_surface_write(p, src[0], src[1], inst->mlen,
1907 src[2].ud, inst->header_size);
1908 break;
1909
1910 case SHADER_OPCODE_MEMORY_FENCE:
1911 brw_memory_fence(p, dst, BRW_OPCODE_SEND);
1912 break;
1913
1914 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
1915 const struct brw_reg mask =
1916 brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
1917 &prog_data->base) ? brw_imm_ud(~0u) :
1918 brw_dmask_reg();
1919 brw_find_live_channel(p, dst, mask);
1920 break;
1921 }
1922
1923 case SHADER_OPCODE_BROADCAST:
1924 assert(inst->force_writemask_all);
1925 brw_broadcast(p, dst, src[0], src[1]);
1926 break;
1927
1928 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1929 generate_unpack_flags(p, dst);
1930 break;
1931
1932 case VEC4_OPCODE_MOV_BYTES: {
1933 /* Moves the low byte from each channel, using an Align1 access mode
1934 * and a <4,1,0> source region.
1935 */
1936 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1937 src[0].type == BRW_REGISTER_TYPE_B);
1938
1939 brw_set_default_access_mode(p, BRW_ALIGN_1);
1940 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1941 src[0].width = BRW_WIDTH_1;
1942 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1943 brw_MOV(p, dst, src[0]);
1944 brw_set_default_access_mode(p, BRW_ALIGN_16);
1945 break;
1946 }
1947
1948 case VEC4_OPCODE_DOUBLE_TO_F32:
1949 case VEC4_OPCODE_DOUBLE_TO_D32:
1950 case VEC4_OPCODE_DOUBLE_TO_U32: {
1951 assert(type_sz(src[0].type) == 8);
1952 assert(type_sz(dst.type) == 8);
1953
1954 brw_reg_type dst_type;
1955
1956 switch (inst->opcode) {
1957 case VEC4_OPCODE_DOUBLE_TO_F32:
1958 dst_type = BRW_REGISTER_TYPE_F;
1959 break;
1960 case VEC4_OPCODE_DOUBLE_TO_D32:
1961 dst_type = BRW_REGISTER_TYPE_D;
1962 break;
1963 case VEC4_OPCODE_DOUBLE_TO_U32:
1964 dst_type = BRW_REGISTER_TYPE_UD;
1965 break;
1966 default:
1967 unreachable("Not supported conversion");
1968 }
1969 dst = retype(dst, dst_type);
1970
1971 brw_set_default_access_mode(p, BRW_ALIGN_1);
1972
1973 /* When converting from DF->F, we set destination's stride as 2 as an
1974 * aligment requirement. But in IVB/BYT, each DF implicitly writes
1975 * two floats, being the first one the converted value. So we don't
1976 * need to explicitly set stride 2, but 1.
1977 */
1978 struct brw_reg spread_dst;
1979 if (devinfo->gen == 7 && !devinfo->is_haswell)
1980 spread_dst = stride(dst, 8, 4, 1);
1981 else
1982 spread_dst = stride(dst, 8, 4, 2);
1983
1984 brw_MOV(p, spread_dst, src[0]);
1985
1986 brw_set_default_access_mode(p, BRW_ALIGN_16);
1987 break;
1988 }
1989
1990 case VEC4_OPCODE_TO_DOUBLE: {
1991 assert(type_sz(src[0].type) == 4);
1992 assert(type_sz(dst.type) == 8);
1993
1994 brw_set_default_access_mode(p, BRW_ALIGN_1);
1995
1996 brw_MOV(p, dst, src[0]);
1997
1998 brw_set_default_access_mode(p, BRW_ALIGN_16);
1999 break;
2000 }
2001
2002 case VEC4_OPCODE_PICK_LOW_32BIT:
2003 case VEC4_OPCODE_PICK_HIGH_32BIT: {
2004 /* Stores the low/high 32-bit of each 64-bit element in src[0] into
2005 * dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
2006 */
2007 assert(type_sz(src[0].type) == 8);
2008 assert(type_sz(dst.type) == 4);
2009
2010 brw_set_default_access_mode(p, BRW_ALIGN_1);
2011
2012 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2013 dst.hstride = BRW_HORIZONTAL_STRIDE_1;
2014
2015 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2016 if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)
2017 src[0] = suboffset(src[0], 1);
2018 src[0] = spread(src[0], 2);
2019 brw_MOV(p, dst, src[0]);
2020
2021 brw_set_default_access_mode(p, BRW_ALIGN_16);
2022 break;
2023 }
2024
2025 case VEC4_OPCODE_SET_LOW_32BIT:
2026 case VEC4_OPCODE_SET_HIGH_32BIT: {
2027 /* Reads consecutive 32-bit elements from src[0] and writes
2028 * them to the low/high 32-bit of each 64-bit element in dst.
2029 */
2030 assert(type_sz(src[0].type) == 4);
2031 assert(type_sz(dst.type) == 8);
2032
2033 brw_set_default_access_mode(p, BRW_ALIGN_1);
2034
2035 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2036 if (inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT)
2037 dst = suboffset(dst, 1);
2038 dst.hstride = BRW_HORIZONTAL_STRIDE_2;
2039
2040 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2041 brw_MOV(p, dst, src[0]);
2042
2043 brw_set_default_access_mode(p, BRW_ALIGN_16);
2044 break;
2045 }
2046
2047 case VEC4_OPCODE_PACK_BYTES: {
2048 /* Is effectively:
2049 *
2050 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
2051 *
2052 * but destinations' only regioning is horizontal stride, so instead we
2053 * have to use two instructions:
2054 *
2055 * mov(4) dst<1>:UB src<4,1,0>:UB
2056 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
2057 *
2058 * where they pack the four bytes from the low and high four DW.
2059 */
2060 assert(_mesa_is_pow_two(dst.writemask) &&
2061 dst.writemask != 0);
2062 unsigned offset = __builtin_ctz(dst.writemask);
2063
2064 dst.type = BRW_REGISTER_TYPE_UB;
2065
2066 brw_set_default_access_mode(p, BRW_ALIGN_1);
2067
2068 src[0].type = BRW_REGISTER_TYPE_UB;
2069 src[0].vstride = BRW_VERTICAL_STRIDE_4;
2070 src[0].width = BRW_WIDTH_1;
2071 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
2072 dst.subnr = offset * 4;
2073 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
2074 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2075 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
2076 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
2077
2078 src[0].subnr = 16;
2079 dst.subnr = 16 + offset * 4;
2080 insn = brw_MOV(p, dst, src[0]);
2081 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2082 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
2083 brw_inst_set_no_dd_check(p->devinfo, insn, true);
2084
2085 brw_set_default_access_mode(p, BRW_ALIGN_16);
2086 break;
2087 }
2088
2089 case TCS_OPCODE_URB_WRITE:
2090 generate_tcs_urb_write(p, inst, src[0]);
2091 break;
2092
2093 case VEC4_OPCODE_URB_READ:
2094 generate_vec4_urb_read(p, inst, dst, src[0]);
2095 break;
2096
2097 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
2098 generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
2099 break;
2100
2101 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
2102 generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
2103 break;
2104
2105 case TCS_OPCODE_GET_INSTANCE_ID:
2106 generate_tcs_get_instance_id(p, dst);
2107 break;
2108
2109 case TCS_OPCODE_GET_PRIMITIVE_ID:
2110 generate_tcs_get_primitive_id(p, dst);
2111 break;
2112
2113 case TCS_OPCODE_CREATE_BARRIER_HEADER:
2114 generate_tcs_create_barrier_header(p, prog_data, dst);
2115 break;
2116
2117 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
2118 generate_tes_create_input_read_header(p, dst);
2119 break;
2120
2121 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
2122 generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
2123 break;
2124
2125 case TES_OPCODE_GET_PRIMITIVE_ID:
2126 generate_tes_get_primitive_id(p, dst);
2127 break;
2128
2129 case TCS_OPCODE_SRC0_010_IS_ZERO:
2130 /* If src_reg had stride like fs_reg, we wouldn't need this. */
2131 brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
2132 break;
2133
2134 case TCS_OPCODE_RELEASE_INPUT:
2135 generate_tcs_release_input(p, dst, src[0], src[1]);
2136 break;
2137
2138 case TCS_OPCODE_THREAD_END:
2139 generate_tcs_thread_end(p, inst);
2140 break;
2141
2142 case SHADER_OPCODE_BARRIER:
2143 brw_barrier(p, src[0]);
2144 brw_WAIT(p);
2145 break;
2146
2147 case SHADER_OPCODE_MOV_INDIRECT:
2148 generate_mov_indirect(p, inst, dst, src[0], src[1]);
2149 break;
2150
2151 case BRW_OPCODE_DIM:
2152 assert(devinfo->is_haswell);
2153 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2154 assert(dst.type == BRW_REGISTER_TYPE_DF);
2155 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2156 break;
2157
2158 default:
2159 unreachable("Unsupported opcode");
2160 }
2161
2162 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
2163 /* Handled dependency hints in the generator. */
2164
2165 assert(!inst->conditional_mod);
2166 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2167 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
2168 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2169 "emitting more than 1 instruction");
2170
2171 brw_inst *last = &p->store[pre_emit_nr_insn];
2172
2173 if (inst->conditional_mod)
2174 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2175 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2176 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2177 }
2178 }
2179
2180 brw_set_uip_jip(p, 0);
2181
2182 /* end of program sentinel */
2183 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2184
2185 #ifndef NDEBUG
2186 bool validated =
2187 #else
2188 if (unlikely(debug_flag))
2189 #endif
2190 brw_validate_instructions(devinfo, p->store,
2191 0, p->next_insn_offset,
2192 disasm_info);
2193
2194 int before_size = p->next_insn_offset;
2195 brw_compact_instructions(p, 0, disasm_info);
2196 int after_size = p->next_insn_offset;
2197
2198 if (unlikely(debug_flag)) {
2199 fprintf(stderr, "Native code for %s %s shader %s:\n",
2200 nir->info.label ? nir->info.label : "unnamed",
2201 _mesa_shader_stage_to_string(nir->info.stage), nir->info.name);
2202
2203 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2204 "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
2205 stage_abbrev, before_size / 16, loop_count, cfg->cycle_count,
2206 spill_count, fill_count, before_size, after_size,
2207 100.0f * (before_size - after_size) / before_size);
2208
2209 dump_assembly(p->store, disasm_info);
2210 }
2211 ralloc_free(disasm_info);
2212 assert(validated);
2213
2214 compiler->shader_debug_log(log_data,
2215 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2216 "%d:%d spills:fills, compacted %d to %d bytes.",
2217 stage_abbrev, before_size / 16,
2218 loop_count, cfg->cycle_count, spill_count,
2219 fill_count, before_size, after_size);
2220
2221 }
2222
2223 extern "C" const unsigned *
2224 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
2225 void *log_data,
2226 void *mem_ctx,
2227 const nir_shader *nir,
2228 struct brw_vue_prog_data *prog_data,
2229 const struct cfg_t *cfg)
2230 {
2231 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
2232 brw_init_codegen(compiler->devinfo, p, mem_ctx);
2233 brw_set_default_access_mode(p, BRW_ALIGN_16);
2234
2235 generate_code(p, compiler, log_data, nir, prog_data, cfg);
2236
2237 return brw_get_program(p, &prog_data->base.program_size);
2238 }