projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
intel/fs: Add support for SLM fence in Gen11
[mesa.git] / src / intel / compiler / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25 #include "brw_eu.h"
26 #include "dev/gen_debug.h"
27
28 using namespace brw;
29
30 static void
31 generate_math1_gen4(struct brw_codegen *p,
32 vec4_instruction *inst,
33 struct brw_reg dst,
34 struct brw_reg src)
35 {
36 gen4_math(p,
37 dst,
38 brw_math_function(inst->opcode),
39 inst->base_mrf,
40 src,
41 BRW_MATH_PRECISION_FULL);
42 }
43
44 static void
45 check_gen6_math_src_arg(struct brw_reg src)
46 {
47 /* Source swizzles are ignored. */
48 assert(!src.abs);
49 assert(!src.negate);
50 assert(src.swizzle == BRW_SWIZZLE_XYZW);
51 }
52
53 static void
54 generate_math_gen6(struct brw_codegen *p,
55 vec4_instruction *inst,
56 struct brw_reg dst,
57 struct brw_reg src0,
58 struct brw_reg src1)
59 {
60 /* Can't do writemask because math can't be align16. */
61 assert(dst.writemask == WRITEMASK_XYZW);
62 /* Source swizzles are ignored. */
63 check_gen6_math_src_arg(src0);
64 if (src1.file == BRW_GENERAL_REGISTER_FILE)
65 check_gen6_math_src_arg(src1);
66
67 brw_set_default_access_mode(p, BRW_ALIGN_1);
68 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
69 brw_set_default_access_mode(p, BRW_ALIGN_16);
70 }
71
72 static void
73 generate_math2_gen4(struct brw_codegen *p,
74 vec4_instruction *inst,
75 struct brw_reg dst,
76 struct brw_reg src0,
77 struct brw_reg src1)
78 {
79 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
80 * "Message Payload":
81 *
82 * "Operand0[7]. For the INT DIV functions, this operand is the
83 * denominator."
84 * ...
85 * "Operand1[7]. For the INT DIV functions, this operand is the
86 * numerator."
87 */
88 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
89 struct brw_reg &op0 = is_int_div ? src1 : src0;
90 struct brw_reg &op1 = is_int_div ? src0 : src1;
91
92 brw_push_insn_state(p);
93 brw_set_default_saturate(p, false);
94 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
95 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
96 brw_pop_insn_state(p);
97
98 gen4_math(p,
99 dst,
100 brw_math_function(inst->opcode),
101 inst->base_mrf,
102 op0,
103 BRW_MATH_PRECISION_FULL);
104 }
105
106 static void
107 generate_tex(struct brw_codegen *p,
108 struct brw_vue_prog_data *prog_data,
109 gl_shader_stage stage,
110 vec4_instruction *inst,
111 struct brw_reg dst,
112 struct brw_reg src,
113 struct brw_reg surface_index,
114 struct brw_reg sampler_index)
115 {
116 const struct gen_device_info *devinfo = p->devinfo;
117 int msg_type = -1;
118
119 if (devinfo->gen >= 5) {
120 switch (inst->opcode) {
121 case SHADER_OPCODE_TEX:
122 case SHADER_OPCODE_TXL:
123 if (inst->shadow_compare) {
124 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
125 } else {
126 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
127 }
128 break;
129 case SHADER_OPCODE_TXD:
130 if (inst->shadow_compare) {
131 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
132 assert(devinfo->gen >= 8 || devinfo->is_haswell);
133 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
134 } else {
135 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
136 }
137 break;
138 case SHADER_OPCODE_TXF:
139 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
140 break;
141 case SHADER_OPCODE_TXF_CMS_W:
142 assert(devinfo->gen >= 9);
143 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
144 break;
145 case SHADER_OPCODE_TXF_CMS:
146 if (devinfo->gen >= 7)
147 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
148 else
149 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
150 break;
151 case SHADER_OPCODE_TXF_MCS:
152 assert(devinfo->gen >= 7);
153 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
154 break;
155 case SHADER_OPCODE_TXS:
156 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
157 break;
158 case SHADER_OPCODE_TG4:
159 if (inst->shadow_compare) {
160 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
161 } else {
162 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
163 }
164 break;
165 case SHADER_OPCODE_TG4_OFFSET:
166 if (inst->shadow_compare) {
167 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
168 } else {
169 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
170 }
171 break;
172 case SHADER_OPCODE_SAMPLEINFO:
173 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
174 break;
175 default:
176 unreachable("should not get here: invalid vec4 texture opcode");
177 }
178 } else {
179 switch (inst->opcode) {
180 case SHADER_OPCODE_TEX:
181 case SHADER_OPCODE_TXL:
182 if (inst->shadow_compare) {
183 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
184 assert(inst->mlen == 3);
185 } else {
186 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
187 assert(inst->mlen == 2);
188 }
189 break;
190 case SHADER_OPCODE_TXD:
191 /* There is no sample_d_c message; comparisons are done manually. */
192 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
193 assert(inst->mlen == 4);
194 break;
195 case SHADER_OPCODE_TXF:
196 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
197 assert(inst->mlen == 2);
198 break;
199 case SHADER_OPCODE_TXS:
200 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
201 assert(inst->mlen == 2);
202 break;
203 default:
204 unreachable("should not get here: invalid vec4 texture opcode");
205 }
206 }
207
208 assert(msg_type != -1);
209
210 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
211
212 /* Load the message header if present. If there's a texture offset, we need
213 * to set it up explicitly and load the offset bitfield. Otherwise, we can
214 * use an implied move from g0 to the first message register.
215 */
216 if (inst->header_size != 0) {
217 if (devinfo->gen < 6 && !inst->offset) {
218 /* Set up an implied move from g0 to the MRF. */
219 src = brw_vec8_grf(0, 0);
220 } else {
221 struct brw_reg header =
222 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
223 uint32_t dw2 = 0;
224
225 /* Explicitly set up the message header by copying g0 to the MRF. */
226 brw_push_insn_state(p);
227 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
228 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
229
230 brw_set_default_access_mode(p, BRW_ALIGN_1);
231
232 if (inst->offset)
233 /* Set the texel offset bits in DWord 2. */
234 dw2 = inst->offset;
235
236 if (devinfo->gen >= 9)
237 /* SKL+ overloads BRW_SAMPLER_SIMD_MODE_SIMD4X2 to also do SIMD8D,
238 * based on bit 22 in the header.
239 */
240 dw2 |= GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2;
241
242 /* The VS, DS, and FS stages have the g0.2 payload delivered as 0,
243 * so header0.2 is 0 when g0 is copied. The HS and GS stages do
244 * not, so we must set to to 0 to avoid setting undesirable bits
245 * in the message header.
246 */
247 if (dw2 ||
248 stage == MESA_SHADER_TESS_CTRL ||
249 stage == MESA_SHADER_GEOMETRY) {
250 brw_MOV(p, get_element_ud(header, 2), brw_imm_ud(dw2));
251 }
252
253 brw_adjust_sampler_state_pointer(p, header, sampler_index);
254 brw_pop_insn_state(p);
255 }
256 }
257
258 uint32_t return_format;
259
260 switch (dst.type) {
261 case BRW_REGISTER_TYPE_D:
262 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
263 break;
264 case BRW_REGISTER_TYPE_UD:
265 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
266 break;
267 default:
268 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
269 break;
270 }
271
272 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
273 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
274 ? prog_data->base.binding_table.gather_texture_start
275 : prog_data->base.binding_table.texture_start;
276
277 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
278 sampler_index.file == BRW_IMMEDIATE_VALUE) {
279 uint32_t surface = surface_index.ud;
280 uint32_t sampler = sampler_index.ud;
281
282 brw_SAMPLE(p,
283 dst,
284 inst->base_mrf,
285 src,
286 surface + base_binding_table_index,
287 sampler % 16,
288 msg_type,
289 1, /* response length */
290 inst->mlen,
291 inst->header_size != 0,
292 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
293 return_format);
294 } else {
295 /* Non-constant sampler index. */
296
297 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
298 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
299 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
300
301 brw_push_insn_state(p);
302 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
303 brw_set_default_access_mode(p, BRW_ALIGN_1);
304
305 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
306 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
307 } else {
308 if (sampler_reg.file == BRW_IMMEDIATE_VALUE) {
309 brw_OR(p, addr, surface_reg, brw_imm_ud(sampler_reg.ud << 8));
310 } else {
311 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
312 brw_OR(p, addr, addr, surface_reg);
313 }
314 }
315 if (base_binding_table_index)
316 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
317 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
318
319 brw_pop_insn_state(p);
320
321 if (inst->base_mrf != -1)
322 gen6_resolve_implied_move(p, &src, inst->base_mrf);
323
324 /* dst = send(offset, a0.0 | <descriptor>) */
325 brw_send_indirect_message(
326 p, BRW_SFID_SAMPLER, dst, src, addr,
327 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
328 brw_sampler_desc(devinfo,
329 0 /* surface */,
330 0 /* sampler */,
331 msg_type,
332 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
333 return_format),
334 false /* EOT */);
335
336 /* visitor knows more than we do about the surface limit required,
337 * so has already done marking.
338 */
339 }
340 }
341
342 static void
343 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
344 {
345 brw_urb_WRITE(p,
346 brw_null_reg(), /* dest */
347 inst->base_mrf, /* starting mrf reg nr */
348 brw_vec8_grf(0, 0), /* src */
349 inst->urb_write_flags,
350 inst->mlen,
351 0, /* response len */
352 inst->offset, /* urb destination offset */
353 BRW_URB_SWIZZLE_INTERLEAVE);
354 }
355
356 static void
357 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst)
358 {
359 struct brw_reg src = brw_message_reg(inst->base_mrf);
360 brw_urb_WRITE(p,
361 brw_null_reg(), /* dest */
362 inst->base_mrf, /* starting mrf reg nr */
363 src,
364 inst->urb_write_flags,
365 inst->mlen,
366 0, /* response len */
367 inst->offset, /* urb destination offset */
368 BRW_URB_SWIZZLE_INTERLEAVE);
369 }
370
371 static void
372 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst)
373 {
374 struct brw_reg src = brw_message_reg(inst->base_mrf);
375
376 /* We pass the temporary passed in src0 as the writeback register */
377 brw_urb_WRITE(p,
378 inst->src[0].as_brw_reg(), /* dest */
379 inst->base_mrf, /* starting mrf reg nr */
380 src,
381 BRW_URB_WRITE_ALLOCATE_COMPLETE,
382 inst->mlen,
383 1, /* response len */
384 inst->offset, /* urb destination offset */
385 BRW_URB_SWIZZLE_INTERLEAVE);
386
387 /* Now put allocated urb handle in dst.0 */
388 brw_push_insn_state(p);
389 brw_set_default_access_mode(p, BRW_ALIGN_1);
390 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
391 brw_MOV(p, get_element_ud(inst->dst.as_brw_reg(), 0),
392 get_element_ud(inst->src[0].as_brw_reg(), 0));
393 brw_pop_insn_state(p);
394 }
395
396 static void
397 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
398 {
399 struct brw_reg src = brw_message_reg(inst->base_mrf);
400 brw_urb_WRITE(p,
401 brw_null_reg(), /* dest */
402 inst->base_mrf, /* starting mrf reg nr */
403 src,
404 BRW_URB_WRITE_EOT | inst->urb_write_flags,
405 inst->mlen,
406 0, /* response len */
407 0, /* urb destination offset */
408 BRW_URB_SWIZZLE_INTERLEAVE);
409 }
410
411 static void
412 generate_gs_set_write_offset(struct brw_codegen *p,
413 struct brw_reg dst,
414 struct brw_reg src0,
415 struct brw_reg src1)
416 {
417 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
418 * Header: M0.3):
419 *
420 * Slot 0 Offset. This field, after adding to the Global Offset field
421 * in the message descriptor, specifies the offset (in 256-bit units)
422 * from the start of the URB entry, as referenced by URB Handle 0, at
423 * which the data will be accessed.
424 *
425 * Similar text describes DWORD M0.4, which is slot 1 offset.
426 *
427 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
428 * of the register for geometry shader invocations 0 and 1) by the
429 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
430 *
431 * We can do this with the following EU instruction:
432 *
433 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
434 */
435 brw_push_insn_state(p);
436 brw_set_default_access_mode(p, BRW_ALIGN_1);
437 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
438 assert(p->devinfo->gen >= 7 &&
439 src1.file == BRW_IMMEDIATE_VALUE &&
440 src1.type == BRW_REGISTER_TYPE_UD &&
441 src1.ud <= USHRT_MAX);
442 if (src0.file == BRW_IMMEDIATE_VALUE) {
443 brw_MOV(p, suboffset(stride(dst, 2, 2, 1), 3),
444 brw_imm_ud(src0.ud * src1.ud));
445 } else {
446 if (src1.file == BRW_IMMEDIATE_VALUE) {
447 src1 = brw_imm_uw(src1.ud);
448 }
449 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
450 retype(src1, BRW_REGISTER_TYPE_UW));
451 }
452 brw_pop_insn_state(p);
453 }
454
455 static void
456 generate_gs_set_vertex_count(struct brw_codegen *p,
457 struct brw_reg dst,
458 struct brw_reg src)
459 {
460 brw_push_insn_state(p);
461 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
462
463 if (p->devinfo->gen >= 8) {
464 /* Move the vertex count into the second MRF for the EOT write. */
465 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
466 src);
467 } else {
468 /* If we think of the src and dst registers as composed of 8 DWORDs each,
469 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
470 * them to WORDs, and then pack them into DWORD 2 of dst.
471 *
472 * It's easier to get the EU to do this if we think of the src and dst
473 * registers as composed of 16 WORDS each; then, we want to pick up the
474 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
475 * of dst.
476 *
477 * We can do that by the following EU instruction:
478 *
479 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
480 */
481 brw_set_default_access_mode(p, BRW_ALIGN_1);
482 brw_MOV(p,
483 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
484 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
485 }
486 brw_pop_insn_state(p);
487 }
488
489 static void
490 generate_gs_svb_write(struct brw_codegen *p,
491 struct brw_vue_prog_data *prog_data,
492 vec4_instruction *inst,
493 struct brw_reg dst,
494 struct brw_reg src0,
495 struct brw_reg src1)
496 {
497 int binding = inst->sol_binding;
498 bool final_write = inst->sol_final_write;
499
500 brw_push_insn_state(p);
501 brw_set_default_exec_size(p, BRW_EXECUTE_4);
502 /* Copy Vertex data into M0.x */
503 brw_MOV(p, stride(dst, 4, 4, 1),
504 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
505 brw_pop_insn_state(p);
506
507 brw_push_insn_state(p);
508 /* Send SVB Write */
509 brw_svb_write(p,
510 final_write ? src1 : brw_null_reg(), /* dest == src1 */
511 1, /* msg_reg_nr */
512 dst, /* src0 == previous dst */
513 BRW_GEN6_SOL_BINDING_START + binding, /* binding_table_index */
514 final_write); /* send_commit_msg */
515
516 /* Finally, wait for the write commit to occur so that we can proceed to
517 * other things safely.
518 *
519 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
520 *
521 * The write commit does not modify the destination register, but
522 * merely clears the dependency associated with the destination
523 * register. Thus, a simple “mov” instruction using the register as a
524 * source is sufficient to wait for the write commit to occur.
525 */
526 if (final_write) {
527 brw_MOV(p, src1, src1);
528 }
529 brw_pop_insn_state(p);
530 }
531
532 static void
533 generate_gs_svb_set_destination_index(struct brw_codegen *p,
534 vec4_instruction *inst,
535 struct brw_reg dst,
536 struct brw_reg src)
537 {
538 int vertex = inst->sol_vertex;
539 brw_push_insn_state(p);
540 brw_set_default_access_mode(p, BRW_ALIGN_1);
541 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
542 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
543 brw_pop_insn_state(p);
544 }
545
546 static void
547 generate_gs_set_dword_2(struct brw_codegen *p,
548 struct brw_reg dst,
549 struct brw_reg src)
550 {
551 brw_push_insn_state(p);
552 brw_set_default_access_mode(p, BRW_ALIGN_1);
553 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
554 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
555 brw_pop_insn_state(p);
556 }
557
558 static void
559 generate_gs_prepare_channel_masks(struct brw_codegen *p,
560 struct brw_reg dst)
561 {
562 /* We want to left shift just DWORD 4 (the x component belonging to the
563 * second geometry shader invocation) by 4 bits. So generate the
564 * instruction:
565 *
566 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
567 */
568 dst = suboffset(vec1(dst), 4);
569 brw_push_insn_state(p);
570 brw_set_default_access_mode(p, BRW_ALIGN_1);
571 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
572 brw_SHL(p, dst, dst, brw_imm_ud(4));
573 brw_pop_insn_state(p);
574 }
575
576 static void
577 generate_gs_set_channel_masks(struct brw_codegen *p,
578 struct brw_reg dst,
579 struct brw_reg src)
580 {
581 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
582 * Header: M0.5):
583 *
584 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
585 *
586 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
587 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
588 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
589 * channel enable to determine the final channel enable. For the
590 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
591 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
592 * in the writeback message. For the URB_WRITE_OWORD &
593 * URB_WRITE_HWORD messages, when final channel enable is 1 it
594 * indicates that Vertex 1 DATA [3] will be written to the surface.
595 *
596 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
597 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
598 *
599 * 14 Vertex 1 DATA [2] Channel Mask
600 * 13 Vertex 1 DATA [1] Channel Mask
601 * 12 Vertex 1 DATA [0] Channel Mask
602 * 11 Vertex 0 DATA [3] Channel Mask
603 * 10 Vertex 0 DATA [2] Channel Mask
604 * 9 Vertex 0 DATA [1] Channel Mask
605 * 8 Vertex 0 DATA [0] Channel Mask
606 *
607 * (This is from a section of the PRM that is agnostic to the particular
608 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
609 * geometry shader invocations 0 and 1, respectively). Since we have the
610 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
611 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
612 * DWORD 4, we just need to OR them together and store the result in bits
613 * 15:8 of DWORD 5.
614 *
615 * It's easier to get the EU to do this if we think of the src and dst
616 * registers as composed of 32 bytes each; then, we want to pick up the
617 * contents of bytes 0 and 16 from src, OR them together, and store them in
618 * byte 21.
619 *
620 * We can do that by the following EU instruction:
621 *
622 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
623 *
624 * Note: this relies on the source register having zeros in (a) bits 7:4 of
625 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
626 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
627 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
628 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
629 * contain valid channel mask values (which are in the range 0x0-0xf).
630 */
631 dst = retype(dst, BRW_REGISTER_TYPE_UB);
632 src = retype(src, BRW_REGISTER_TYPE_UB);
633 brw_push_insn_state(p);
634 brw_set_default_access_mode(p, BRW_ALIGN_1);
635 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
636 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
637 brw_pop_insn_state(p);
638 }
639
640 static void
641 generate_gs_get_instance_id(struct brw_codegen *p,
642 struct brw_reg dst)
643 {
644 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
645 * and store into dst.0 & dst.4. So generate the instruction:
646 *
647 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
648 */
649 brw_push_insn_state(p);
650 brw_set_default_access_mode(p, BRW_ALIGN_1);
651 dst = retype(dst, BRW_REGISTER_TYPE_UD);
652 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
653 brw_SHR(p, dst, stride(r0, 1, 4, 0),
654 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
655 brw_pop_insn_state(p);
656 }
657
658 static void
659 generate_gs_ff_sync_set_primitives(struct brw_codegen *p,
660 struct brw_reg dst,
661 struct brw_reg src0,
662 struct brw_reg src1,
663 struct brw_reg src2)
664 {
665 brw_push_insn_state(p);
666 brw_set_default_access_mode(p, BRW_ALIGN_1);
667 /* Save src0 data in 16:31 bits of dst.0 */
668 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
669 brw_imm_ud(0xffffu));
670 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
671 /* Save src1 data in 0:15 bits of dst.0 */
672 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
673 brw_imm_ud(0xffffu));
674 brw_OR(p, suboffset(vec1(dst), 0),
675 suboffset(vec1(dst), 0),
676 suboffset(vec1(src2), 0));
677 brw_pop_insn_state(p);
678 }
679
680 static void
681 generate_gs_ff_sync(struct brw_codegen *p,
682 vec4_instruction *inst,
683 struct brw_reg dst,
684 struct brw_reg src0,
685 struct brw_reg src1)
686 {
687 /* This opcode uses an implied MRF register for:
688 * - the header of the ff_sync message. And as such it is expected to be
689 * initialized to r0 before calling here.
690 * - the destination where we will write the allocated URB handle.
691 */
692 struct brw_reg header =
693 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
694
695 /* Overwrite dword 0 of the header (SO vertices to write) and
696 * dword 1 (number of primitives written).
697 */
698 brw_push_insn_state(p);
699 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
700 brw_set_default_access_mode(p, BRW_ALIGN_1);
701 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
702 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
703 brw_pop_insn_state(p);
704
705 /* Allocate URB handle in dst */
706 brw_ff_sync(p,
707 dst,
708 0,
709 header,
710 1, /* allocate */
711 1, /* response length */
712 0 /* eot */);
713
714 /* Now put allocated urb handle in header.0 */
715 brw_push_insn_state(p);
716 brw_set_default_access_mode(p, BRW_ALIGN_1);
717 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
718 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
719
720 /* src1 is not an immediate when we use transform feedback */
721 if (src1.file != BRW_IMMEDIATE_VALUE) {
722 brw_set_default_exec_size(p, BRW_EXECUTE_4);
723 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
724 }
725
726 brw_pop_insn_state(p);
727 }
728
729 static void
730 generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
731 {
732 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
733 struct brw_reg src = brw_vec8_grf(0, 0);
734 brw_push_insn_state(p);
735 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
736 brw_set_default_access_mode(p, BRW_ALIGN_1);
737 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
738 brw_pop_insn_state(p);
739 }
740
741 static void
742 generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
743 {
744 const struct gen_device_info *devinfo = p->devinfo;
745 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
746
747 /* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
748 *
749 * Since we operate in SIMD4x2 mode, we need run half as many threads
750 * as necessary. So we assign (2i + 1, 2i) as the thread counts. We
751 * shift right by one less to accomplish the multiplication by two.
752 */
753 dst = retype(dst, BRW_REGISTER_TYPE_UD);
754 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
755
756 brw_push_insn_state(p);
757 brw_set_default_access_mode(p, BRW_ALIGN_1);
758
759 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
760 const int shift = ivb ? 16 : 17;
761
762 brw_AND(p, get_element_ud(dst, 0), get_element_ud(r0, 2), brw_imm_ud(mask));
763 brw_SHR(p, get_element_ud(dst, 0), get_element_ud(dst, 0),
764 brw_imm_ud(shift - 1));
765 brw_ADD(p, get_element_ud(dst, 4), get_element_ud(dst, 0), brw_imm_ud(1));
766
767 brw_pop_insn_state(p);
768 }
769
770 static void
771 generate_tcs_urb_write(struct brw_codegen *p,
772 vec4_instruction *inst,
773 struct brw_reg urb_header)
774 {
775 const struct gen_device_info *devinfo = p->devinfo;
776
777 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
778 brw_set_dest(p, send, brw_null_reg());
779 brw_set_src0(p, send, urb_header);
780 brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
781
782 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
783 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
784 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
785 if (inst->urb_write_flags & BRW_URB_WRITE_EOT) {
786 brw_inst_set_eot(devinfo, send, 1);
787 } else {
788 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
789 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
790 }
791
792 /* what happens to swizzles? */
793 }
794
795
796 static void
797 generate_tcs_input_urb_offsets(struct brw_codegen *p,
798 struct brw_reg dst,
799 struct brw_reg vertex,
800 struct brw_reg offset)
801 {
802 /* Generates an URB read/write message header for HS/DS operation.
803 * Inputs are a vertex index, and a byte offset from the beginning of
804 * the vertex. */
805
806 /* If `vertex` is not an immediate, we clobber a0.0 */
807
808 assert(vertex.file == BRW_IMMEDIATE_VALUE || vertex.file == BRW_GENERAL_REGISTER_FILE);
809 assert(vertex.type == BRW_REGISTER_TYPE_UD || vertex.type == BRW_REGISTER_TYPE_D);
810
811 assert(dst.file == BRW_GENERAL_REGISTER_FILE);
812
813 brw_push_insn_state(p);
814 brw_set_default_access_mode(p, BRW_ALIGN_1);
815 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
816 brw_MOV(p, dst, brw_imm_ud(0));
817
818 /* m0.5 bits 8-15 are channel enables */
819 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
820
821 /* m0.0-0.1: URB handles */
822 if (vertex.file == BRW_IMMEDIATE_VALUE) {
823 uint32_t vertex_index = vertex.ud;
824 struct brw_reg index_reg = brw_vec1_grf(
825 1 + (vertex_index >> 3), vertex_index & 7);
826
827 brw_MOV(p, vec2(get_element_ud(dst, 0)),
828 retype(index_reg, BRW_REGISTER_TYPE_UD));
829 } else {
830 /* Use indirect addressing. ICP Handles are DWords (single channels
831 * of a register) and start at g1.0.
832 *
833 * In order to start our region at g1.0, we add 8 to the vertex index,
834 * effectively skipping over the 8 channels in g0.0. This gives us a
835 * DWord offset to the ICP Handle.
836 *
837 * Indirect addressing works in terms of bytes, so we then multiply
838 * the DWord offset by 4 (by shifting left by 2).
839 */
840 struct brw_reg addr = brw_address_reg(0);
841
842 /* bottom half: m0.0 = g[1.0 + vertex.0]UD */
843 brw_ADD(p, addr, retype(get_element_ud(vertex, 0), BRW_REGISTER_TYPE_UW),
844 brw_imm_uw(0x8));
845 brw_SHL(p, addr, addr, brw_imm_uw(2));
846 brw_MOV(p, get_element_ud(dst, 0), deref_1ud(brw_indirect(0, 0), 0));
847
848 /* top half: m0.1 = g[1.0 + vertex.4]UD */
849 brw_ADD(p, addr, retype(get_element_ud(vertex, 4), BRW_REGISTER_TYPE_UW),
850 brw_imm_uw(0x8));
851 brw_SHL(p, addr, addr, brw_imm_uw(2));
852 brw_MOV(p, get_element_ud(dst, 1), deref_1ud(brw_indirect(0, 0), 0));
853 }
854
855 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
856 if (offset.file != ARF)
857 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
858
859 brw_pop_insn_state(p);
860 }
861
862
863 static void
864 generate_tcs_output_urb_offsets(struct brw_codegen *p,
865 struct brw_reg dst,
866 struct brw_reg write_mask,
867 struct brw_reg offset)
868 {
869 /* Generates an URB read/write message header for HS/DS operation, for the patch URB entry. */
870 assert(dst.file == BRW_GENERAL_REGISTER_FILE || dst.file == BRW_MESSAGE_REGISTER_FILE);
871
872 assert(write_mask.file == BRW_IMMEDIATE_VALUE);
873 assert(write_mask.type == BRW_REGISTER_TYPE_UD);
874
875 brw_push_insn_state(p);
876
877 brw_set_default_access_mode(p, BRW_ALIGN_1);
878 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
879 brw_MOV(p, dst, brw_imm_ud(0));
880
881 unsigned mask = write_mask.ud;
882
883 /* m0.5 bits 15:12 and 11:8 are channel enables */
884 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud((mask << 8) | (mask << 12)));
885
886 /* HS patch URB handle is delivered in r0.0 */
887 struct brw_reg urb_handle = brw_vec1_grf(0, 0);
888
889 /* m0.0-0.1: URB handles */
890 brw_MOV(p, vec2(get_element_ud(dst, 0)),
891 retype(urb_handle, BRW_REGISTER_TYPE_UD));
892
893 /* m0.3-0.4: 128bit-granular offsets into the URB from the handles */
894 if (offset.file != ARF)
895 brw_MOV(p, vec2(get_element_ud(dst, 3)), stride(offset, 4, 1, 0));
896
897 brw_pop_insn_state(p);
898 }
899
900 static void
901 generate_tes_create_input_read_header(struct brw_codegen *p,
902 struct brw_reg dst)
903 {
904 brw_push_insn_state(p);
905 brw_set_default_access_mode(p, BRW_ALIGN_1);
906 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
907
908 /* Initialize the register to 0 */
909 brw_MOV(p, dst, brw_imm_ud(0));
910
911 /* Enable all the channels in m0.5 bits 15:8 */
912 brw_MOV(p, get_element_ud(dst, 5), brw_imm_ud(0xff00));
913
914 /* Copy g1.3 (the patch URB handle) to m0.0 and m0.1. For safety,
915 * mask out irrelevant "Reserved" bits, as they're not marked MBZ.
916 */
917 brw_AND(p, vec2(get_element_ud(dst, 0)),
918 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD),
919 brw_imm_ud(0x1fff));
920 brw_pop_insn_state(p);
921 }
922
923 static void
924 generate_tes_add_indirect_urb_offset(struct brw_codegen *p,
925 struct brw_reg dst,
926 struct brw_reg header,
927 struct brw_reg offset)
928 {
929 brw_push_insn_state(p);
930 brw_set_default_access_mode(p, BRW_ALIGN_1);
931 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
932
933 brw_MOV(p, dst, header);
934
935 /* Uniforms will have a stride <0;4,1>, and we need to convert to <0;1,0>.
936 * Other values get <4;1,0>.
937 */
938 struct brw_reg restrided_offset;
939 if (offset.vstride == BRW_VERTICAL_STRIDE_0 &&
940 offset.width == BRW_WIDTH_4 &&
941 offset.hstride == BRW_HORIZONTAL_STRIDE_1) {
942 restrided_offset = stride(offset, 0, 1, 0);
943 } else {
944 restrided_offset = stride(offset, 4, 1, 0);
945 }
946
947 /* m0.3-0.4: 128-bit-granular offsets into the URB from the handles */
948 brw_MOV(p, vec2(get_element_ud(dst, 3)), restrided_offset);
949
950 brw_pop_insn_state(p);
951 }
952
953 static void
954 generate_vec4_urb_read(struct brw_codegen *p,
955 vec4_instruction *inst,
956 struct brw_reg dst,
957 struct brw_reg header)
958 {
959 const struct gen_device_info *devinfo = p->devinfo;
960
961 assert(header.file == BRW_GENERAL_REGISTER_FILE);
962 assert(header.type == BRW_REGISTER_TYPE_UD);
963
964 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
965 brw_set_dest(p, send, dst);
966 brw_set_src0(p, send, header);
967
968 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 1, true));
969
970 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
971 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
972 brw_inst_set_urb_swizzle_control(devinfo, send, BRW_URB_SWIZZLE_INTERLEAVE);
973 brw_inst_set_urb_per_slot_offset(devinfo, send, 1);
974
975 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
976 }
977
978 static void
979 generate_tcs_release_input(struct brw_codegen *p,
980 struct brw_reg header,
981 struct brw_reg vertex,
982 struct brw_reg is_unpaired)
983 {
984 const struct gen_device_info *devinfo = p->devinfo;
985
986 assert(vertex.file == BRW_IMMEDIATE_VALUE);
987 assert(vertex.type == BRW_REGISTER_TYPE_UD);
988
989 /* m0.0-0.1: URB handles */
990 struct brw_reg urb_handles =
991 retype(brw_vec2_grf(1 + (vertex.ud >> 3), vertex.ud & 7),
992 BRW_REGISTER_TYPE_UD);
993
994 brw_push_insn_state(p);
995 brw_set_default_access_mode(p, BRW_ALIGN_1);
996 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
997 brw_MOV(p, header, brw_imm_ud(0));
998 brw_MOV(p, vec2(get_element_ud(header, 0)), urb_handles);
999 brw_pop_insn_state(p);
1000
1001 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1002 brw_set_dest(p, send, brw_null_reg());
1003 brw_set_src0(p, send, header);
1004 brw_set_desc(p, send, brw_message_desc(devinfo, 1, 0, true));
1005
1006 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
1007 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_READ_OWORD);
1008 brw_inst_set_urb_complete(devinfo, send, 1);
1009 brw_inst_set_urb_swizzle_control(devinfo, send, is_unpaired.ud ?
1010 BRW_URB_SWIZZLE_NONE :
1011 BRW_URB_SWIZZLE_INTERLEAVE);
1012 }
1013
1014 static void
1015 generate_tcs_thread_end(struct brw_codegen *p, vec4_instruction *inst)
1016 {
1017 struct brw_reg header = brw_message_reg(inst->base_mrf);
1018
1019 brw_push_insn_state(p);
1020 brw_set_default_access_mode(p, BRW_ALIGN_1);
1021 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1022 brw_MOV(p, header, brw_imm_ud(0));
1023 brw_MOV(p, get_element_ud(header, 5), brw_imm_ud(WRITEMASK_X << 8));
1024 brw_MOV(p, get_element_ud(header, 0),
1025 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
1026 brw_MOV(p, brw_message_reg(inst->base_mrf + 1), brw_imm_ud(0u));
1027 brw_pop_insn_state(p);
1028
1029 brw_urb_WRITE(p,
1030 brw_null_reg(), /* dest */
1031 inst->base_mrf, /* starting mrf reg nr */
1032 header,
1033 BRW_URB_WRITE_EOT | BRW_URB_WRITE_OWORD |
1034 BRW_URB_WRITE_USE_CHANNEL_MASKS,
1035 inst->mlen,
1036 0, /* response len */
1037 0, /* urb destination offset */
1038 0);
1039 }
1040
1041 static void
1042 generate_tes_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1043 {
1044 brw_push_insn_state(p);
1045 brw_set_default_access_mode(p, BRW_ALIGN_1);
1046 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D));
1047 brw_pop_insn_state(p);
1048 }
1049
1050 static void
1051 generate_tcs_get_primitive_id(struct brw_codegen *p, struct brw_reg dst)
1052 {
1053 brw_push_insn_state(p);
1054 brw_set_default_access_mode(p, BRW_ALIGN_1);
1055 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD));
1056 brw_pop_insn_state(p);
1057 }
1058
1059 static void
1060 generate_tcs_create_barrier_header(struct brw_codegen *p,
1061 struct brw_vue_prog_data *prog_data,
1062 struct brw_reg dst)
1063 {
1064 const struct gen_device_info *devinfo = p->devinfo;
1065 const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
1066 struct brw_reg m0_2 = get_element_ud(dst, 2);
1067 unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
1068
1069 brw_push_insn_state(p);
1070 brw_set_default_access_mode(p, BRW_ALIGN_1);
1071 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1072
1073 /* Zero the message header */
1074 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
1075
1076 /* Copy "Barrier ID" from r0.2, bits 16:13 (Gen7.5+) or 15:12 (Gen7) */
1077 brw_AND(p, m0_2,
1078 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
1079 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
1080
1081 /* Shift it up to bits 27:24. */
1082 brw_SHL(p, m0_2, get_element_ud(dst, 2), brw_imm_ud(ivb ? 12 : 11));
1083
1084 /* Set the Barrier Count and the enable bit */
1085 brw_OR(p, m0_2, m0_2, brw_imm_ud(instances << 9 | (1 << 15)));
1086
1087 brw_pop_insn_state(p);
1088 }
1089
1090 static void
1091 generate_oword_dual_block_offsets(struct brw_codegen *p,
1092 struct brw_reg m1,
1093 struct brw_reg index)
1094 {
1095 int second_vertex_offset;
1096
1097 if (p->devinfo->gen >= 6)
1098 second_vertex_offset = 1;
1099 else
1100 second_vertex_offset = 16;
1101
1102 m1 = retype(m1, BRW_REGISTER_TYPE_D);
1103
1104 /* Set up M1 (message payload). Only the block offsets in M1.0 and
1105 * M1.4 are used, and the rest are ignored.
1106 */
1107 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
1108 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
1109 struct brw_reg index_0 = suboffset(vec1(index), 0);
1110 struct brw_reg index_4 = suboffset(vec1(index), 4);
1111
1112 brw_push_insn_state(p);
1113 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1114 brw_set_default_access_mode(p, BRW_ALIGN_1);
1115
1116 brw_MOV(p, m1_0, index_0);
1117
1118 if (index.file == BRW_IMMEDIATE_VALUE) {
1119 index_4.ud += second_vertex_offset;
1120 brw_MOV(p, m1_4, index_4);
1121 } else {
1122 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
1123 }
1124
1125 brw_pop_insn_state(p);
1126 }
1127
1128 static void
1129 generate_unpack_flags(struct brw_codegen *p,
1130 struct brw_reg dst)
1131 {
1132 brw_push_insn_state(p);
1133 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1134 brw_set_default_access_mode(p, BRW_ALIGN_1);
1135
1136 struct brw_reg flags = brw_flag_reg(0, 0);
1137 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
1138 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
1139
1140 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
1141 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
1142 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
1143
1144 brw_pop_insn_state(p);
1145 }
1146
1147 static void
1148 generate_scratch_read(struct brw_codegen *p,
1149 vec4_instruction *inst,
1150 struct brw_reg dst,
1151 struct brw_reg index)
1152 {
1153 const struct gen_device_info *devinfo = p->devinfo;
1154 struct brw_reg header = brw_vec8_grf(0, 0);
1155
1156 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1157
1158 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1159 index);
1160
1161 uint32_t msg_type;
1162
1163 if (devinfo->gen >= 6)
1164 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1165 else if (devinfo->gen == 5 || devinfo->is_g4x)
1166 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1167 else
1168 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1169
1170 const unsigned target_cache =
1171 devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1172 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1173 BRW_SFID_DATAPORT_READ;
1174
1175 /* Each of the 8 channel enables is considered for whether each
1176 * dword is written.
1177 */
1178 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1179 brw_inst_set_sfid(devinfo, send, target_cache);
1180 brw_set_dest(p, send, dst);
1181 brw_set_src0(p, send, header);
1182 if (devinfo->gen < 6)
1183 brw_inst_set_cond_modifier(devinfo, send, inst->base_mrf);
1184 brw_set_desc(p, send,
1185 brw_message_desc(devinfo, 2, 1, true) |
1186 brw_dp_read_desc(devinfo,
1187 brw_scratch_surface_idx(p),
1188 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1189 msg_type, BRW_DATAPORT_READ_TARGET_RENDER_CACHE));
1190 }
1191
1192 static void
1193 generate_scratch_write(struct brw_codegen *p,
1194 vec4_instruction *inst,
1195 struct brw_reg dst,
1196 struct brw_reg src,
1197 struct brw_reg index)
1198 {
1199 const struct gen_device_info *devinfo = p->devinfo;
1200 const unsigned target_cache =
1201 (devinfo->gen >= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE :
1202 devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE :
1203 BRW_SFID_DATAPORT_WRITE);
1204 struct brw_reg header = brw_vec8_grf(0, 0);
1205 bool write_commit;
1206
1207 /* If the instruction is predicated, we'll predicate the send, not
1208 * the header setup.
1209 */
1210 brw_set_default_predicate_control(p, false);
1211
1212 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1213
1214 generate_oword_dual_block_offsets(p, brw_message_reg(inst->base_mrf + 1),
1215 index);
1216
1217 brw_MOV(p,
1218 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
1219 retype(src, BRW_REGISTER_TYPE_D));
1220
1221 uint32_t msg_type;
1222
1223 if (devinfo->gen >= 7)
1224 msg_type = GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE;
1225 else if (devinfo->gen == 6)
1226 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1227 else
1228 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
1229
1230 brw_set_default_predicate_control(p, inst->predicate);
1231
1232 /* Pre-gen6, we have to specify write commits to ensure ordering
1233 * between reads and writes within a thread. Afterwards, that's
1234 * guaranteed and write commits only matter for inter-thread
1235 * synchronization.
1236 */
1237 if (devinfo->gen >= 6) {
1238 write_commit = false;
1239 } else {
1240 /* The visitor set up our destination register to be g0. This
1241 * means that when the next read comes along, we will end up
1242 * reading from g0 and causing a block on the write commit. For
1243 * write-after-read, we are relying on the value of the previous
1244 * read being used (and thus blocking on completion) before our
1245 * write is executed. This means we have to be careful in
1246 * instruction scheduling to not violate this assumption.
1247 */
1248 write_commit = true;
1249 }
1250
1251 /* Each of the 8 channel enables is considered for whether each
1252 * dword is written.
1253 */
1254 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1255 brw_inst_set_sfid(p->devinfo, send, target_cache);
1256 brw_set_dest(p, send, dst);
1257 brw_set_src0(p, send, header);
1258 if (devinfo->gen < 6)
1259 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1260 brw_set_desc(p, send,
1261 brw_message_desc(devinfo, 3, write_commit, true) |
1262 brw_dp_write_desc(devinfo,
1263 brw_scratch_surface_idx(p),
1264 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1265 msg_type,
1266 false, /* not a render target write */
1267 write_commit));
1268 }
1269
1270 static void
1271 generate_pull_constant_load(struct brw_codegen *p,
1272 struct brw_vue_prog_data *prog_data,
1273 vec4_instruction *inst,
1274 struct brw_reg dst,
1275 struct brw_reg index,
1276 struct brw_reg offset)
1277 {
1278 const struct gen_device_info *devinfo = p->devinfo;
1279 const unsigned target_cache =
1280 (devinfo->gen >= 6 ? GEN6_SFID_DATAPORT_SAMPLER_CACHE :
1281 BRW_SFID_DATAPORT_READ);
1282 assert(index.file == BRW_IMMEDIATE_VALUE &&
1283 index.type == BRW_REGISTER_TYPE_UD);
1284 uint32_t surf_index = index.ud;
1285
1286 struct brw_reg header = brw_vec8_grf(0, 0);
1287
1288 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1289
1290 if (devinfo->gen >= 6) {
1291 if (offset.file == BRW_IMMEDIATE_VALUE) {
1292 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1293 BRW_REGISTER_TYPE_D),
1294 brw_imm_d(offset.ud >> 4));
1295 } else {
1296 brw_SHR(p, retype(brw_message_reg(inst->base_mrf + 1),
1297 BRW_REGISTER_TYPE_D),
1298 offset, brw_imm_d(4));
1299 }
1300 } else {
1301 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1),
1302 BRW_REGISTER_TYPE_D),
1303 offset);
1304 }
1305
1306 uint32_t msg_type;
1307
1308 if (devinfo->gen >= 6)
1309 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1310 else if (devinfo->gen == 5 || devinfo->is_g4x)
1311 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1312 else
1313 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1314
1315 /* Each of the 8 channel enables is considered for whether each
1316 * dword is written.
1317 */
1318 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1319 brw_inst_set_sfid(devinfo, send, target_cache);
1320 brw_set_dest(p, send, dst);
1321 brw_set_src0(p, send, header);
1322 if (devinfo->gen < 6)
1323 brw_inst_set_cond_modifier(p->devinfo, send, inst->base_mrf);
1324 brw_set_desc(p, send,
1325 brw_message_desc(devinfo, 2, 1, true) |
1326 brw_dp_read_desc(devinfo, surf_index,
1327 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1328 msg_type,
1329 BRW_DATAPORT_READ_TARGET_DATA_CACHE));
1330 }
1331
1332 static void
1333 generate_get_buffer_size(struct brw_codegen *p,
1334 struct brw_vue_prog_data *prog_data,
1335 vec4_instruction *inst,
1336 struct brw_reg dst,
1337 struct brw_reg src,
1338 struct brw_reg surf_index)
1339 {
1340 assert(p->devinfo->gen >= 7);
1341 assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
1342 surf_index.file == BRW_IMMEDIATE_VALUE);
1343
1344 brw_SAMPLE(p,
1345 dst,
1346 inst->base_mrf,
1347 src,
1348 surf_index.ud,
1349 0,
1350 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
1351 1, /* response length */
1352 inst->mlen,
1353 inst->header_size > 0,
1354 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1355 BRW_SAMPLER_RETURN_FORMAT_SINT32);
1356 }
1357
1358 static void
1359 generate_pull_constant_load_gen7(struct brw_codegen *p,
1360 struct brw_vue_prog_data *prog_data,
1361 vec4_instruction *inst,
1362 struct brw_reg dst,
1363 struct brw_reg surf_index,
1364 struct brw_reg offset)
1365 {
1366 const struct gen_device_info *devinfo = p->devinfo;
1367 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1368
1369 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1370
1371 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1372 brw_inst_set_sfid(devinfo, insn, BRW_SFID_SAMPLER);
1373 brw_set_dest(p, insn, dst);
1374 brw_set_src0(p, insn, offset);
1375 brw_set_desc(p, insn,
1376 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1377 brw_sampler_desc(devinfo, surf_index.ud,
1378 0, /* LD message ignores sampler unit */
1379 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1380 BRW_SAMPLER_SIMD_MODE_SIMD4X2, 0));
1381 } else {
1382
1383 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1384
1385 brw_push_insn_state(p);
1386 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1387 brw_set_default_access_mode(p, BRW_ALIGN_1);
1388
1389 /* a0.0 = surf_index & 0xff */
1390 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1391 brw_inst_set_exec_size(devinfo, insn_and, BRW_EXECUTE_1);
1392 brw_set_dest(p, insn_and, addr);
1393 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1394 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1395
1396 brw_pop_insn_state(p);
1397
1398 /* dst = send(offset, a0.0 | <descriptor>) */
1399 brw_send_indirect_message(
1400 p, BRW_SFID_SAMPLER, dst, offset, addr,
1401 brw_message_desc(devinfo, inst->mlen, 1, inst->header_size) |
1402 brw_sampler_desc(devinfo,
1403 0 /* surface */,
1404 0 /* sampler */,
1405 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1406 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1407 0),
1408 false /* EOT */);
1409 }
1410 }
1411
1412 static void
1413 generate_set_simd4x2_header_gen9(struct brw_codegen *p,
1414 vec4_instruction *,
1415 struct brw_reg dst)
1416 {
1417 brw_push_insn_state(p);
1418 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1419
1420 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1421 brw_MOV(p, vec8(dst), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1422
1423 brw_set_default_access_mode(p, BRW_ALIGN_1);
1424 brw_MOV(p, get_element_ud(dst, 2),
1425 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1426
1427 brw_pop_insn_state(p);
1428 }
1429
1430 static void
1431 generate_mov_indirect(struct brw_codegen *p,
1432 vec4_instruction *,
1433 struct brw_reg dst, struct brw_reg reg,
1434 struct brw_reg indirect)
1435 {
1436 assert(indirect.type == BRW_REGISTER_TYPE_UD);
1437 assert(p->devinfo->gen >= 6);
1438
1439 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1440
1441 /* This instruction acts in align1 mode */
1442 assert(dst.writemask == WRITEMASK_XYZW);
1443
1444 if (indirect.file == BRW_IMMEDIATE_VALUE) {
1445 imm_byte_offset += indirect.ud;
1446
1447 reg.nr = imm_byte_offset / REG_SIZE;
1448 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
1449 unsigned shift = (imm_byte_offset / 4) % 4;
1450 reg.swizzle += BRW_SWIZZLE4(shift, shift, shift, shift);
1451
1452 brw_MOV(p, dst, reg);
1453 } else {
1454 brw_push_insn_state(p);
1455 brw_set_default_access_mode(p, BRW_ALIGN_1);
1456 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1457
1458 struct brw_reg addr = vec8(brw_address_reg(0));
1459
1460 /* We need to move the indirect value into the address register. In
1461 * order to make things make some sense, we want to respect at least the
1462 * X component of the swizzle. In order to do that, we need to convert
1463 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1464 */
1465 assert(brw_is_single_value_swizzle(indirect.swizzle));
1466 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
1467
1468 /* We then use a region of <8,4,0>:uw to pick off the first 2 bytes of
1469 * the indirect and splat it out to all four channels of the given half
1470 * of a0.
1471 */
1472 indirect.subnr *= 2;
1473 indirect = stride(retype(indirect, BRW_REGISTER_TYPE_UW), 8, 4, 0);
1474 brw_ADD(p, addr, indirect, brw_imm_uw(imm_byte_offset));
1475
1476 /* Now we need to incorporate the swizzle from the source register */
1477 if (reg.swizzle != BRW_SWIZZLE_XXXX) {
1478 uint32_t uv_swiz = BRW_GET_SWZ(reg.swizzle, 0) << 2 |
1479 BRW_GET_SWZ(reg.swizzle, 1) << 6 |
1480 BRW_GET_SWZ(reg.swizzle, 2) << 10 |
1481 BRW_GET_SWZ(reg.swizzle, 3) << 14;
1482 uv_swiz |= uv_swiz << 16;
1483
1484 brw_ADD(p, addr, addr, brw_imm_uv(uv_swiz));
1485 }
1486
1487 brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), reg.type));
1488
1489 brw_pop_insn_state(p);
1490 }
1491 }
1492
1493 static void
1494 generate_code(struct brw_codegen *p,
1495 const struct brw_compiler *compiler,
1496 void *log_data,
1497 const nir_shader *nir,
1498 struct brw_vue_prog_data *prog_data,
1499 const struct cfg_t *cfg)
1500 {
1501 const struct gen_device_info *devinfo = p->devinfo;
1502 const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
1503 bool debug_flag = INTEL_DEBUG &
1504 intel_debug_flag_for_shader_stage(nir->info.stage);
1505 struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
1506 int spill_count = 0, fill_count = 0;
1507 int loop_count = 0;
1508
1509 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1510 struct brw_reg src[3], dst;
1511
1512 if (unlikely(debug_flag))
1513 disasm_annotate(disasm_info, inst, p->next_insn_offset);
1514
1515 for (unsigned int i = 0; i < 3; i++) {
1516 src[i] = inst->src[i].as_brw_reg();
1517 }
1518 dst = inst->dst.as_brw_reg();
1519
1520 brw_set_default_predicate_control(p, inst->predicate);
1521 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1522 brw_set_default_flag_reg(p, inst->flag_subreg / 2, inst->flag_subreg % 2);
1523 brw_set_default_saturate(p, inst->saturate);
1524 brw_set_default_mask_control(p, inst->force_writemask_all);
1525 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1526
1527 assert(inst->group % inst->exec_size == 0);
1528 assert(inst->group % 4 == 0);
1529
1530 /* There are some instructions where the destination is 64-bit
1531 * but we retype it to a smaller type. In that case, we cannot
1532 * double the exec_size.
1533 */
1534 const bool is_df = (get_exec_type_size(inst) == 8 ||
1535 inst->dst.type == BRW_REGISTER_TYPE_DF) &&
1536 inst->opcode != VEC4_OPCODE_PICK_LOW_32BIT &&
1537 inst->opcode != VEC4_OPCODE_PICK_HIGH_32BIT &&
1538 inst->opcode != VEC4_OPCODE_SET_LOW_32BIT &&
1539 inst->opcode != VEC4_OPCODE_SET_HIGH_32BIT;
1540
1541 unsigned exec_size = inst->exec_size;
1542 if (devinfo->gen == 7 && !devinfo->is_haswell && is_df)
1543 exec_size *= 2;
1544
1545 brw_set_default_exec_size(p, cvt(exec_size) - 1);
1546
1547 if (!inst->force_writemask_all)
1548 brw_set_default_group(p, inst->group);
1549
1550 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1551 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1552
1553 unsigned pre_emit_nr_insn = p->nr_insn;
1554
1555 switch (inst->opcode) {
1556 case VEC4_OPCODE_UNPACK_UNIFORM:
1557 case BRW_OPCODE_MOV:
1558 brw_MOV(p, dst, src[0]);
1559 break;
1560 case BRW_OPCODE_ADD:
1561 brw_ADD(p, dst, src[0], src[1]);
1562 break;
1563 case BRW_OPCODE_MUL:
1564 brw_MUL(p, dst, src[0], src[1]);
1565 break;
1566 case BRW_OPCODE_MACH:
1567 brw_MACH(p, dst, src[0], src[1]);
1568 break;
1569
1570 case BRW_OPCODE_MAD:
1571 assert(devinfo->gen >= 6);
1572 brw_MAD(p, dst, src[0], src[1], src[2]);
1573 break;
1574
1575 case BRW_OPCODE_FRC:
1576 brw_FRC(p, dst, src[0]);
1577 break;
1578 case BRW_OPCODE_RNDD:
1579 brw_RNDD(p, dst, src[0]);
1580 break;
1581 case BRW_OPCODE_RNDE:
1582 brw_RNDE(p, dst, src[0]);
1583 break;
1584 case BRW_OPCODE_RNDZ:
1585 brw_RNDZ(p, dst, src[0]);
1586 break;
1587
1588 case BRW_OPCODE_AND:
1589 brw_AND(p, dst, src[0], src[1]);
1590 break;
1591 case BRW_OPCODE_OR:
1592 brw_OR(p, dst, src[0], src[1]);
1593 break;
1594 case BRW_OPCODE_XOR:
1595 brw_XOR(p, dst, src[0], src[1]);
1596 break;
1597 case BRW_OPCODE_NOT:
1598 brw_NOT(p, dst, src[0]);
1599 break;
1600 case BRW_OPCODE_ASR:
1601 brw_ASR(p, dst, src[0], src[1]);
1602 break;
1603 case BRW_OPCODE_SHR:
1604 brw_SHR(p, dst, src[0], src[1]);
1605 break;
1606 case BRW_OPCODE_SHL:
1607 brw_SHL(p, dst, src[0], src[1]);
1608 break;
1609
1610 case BRW_OPCODE_CMP:
1611 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1612 break;
1613 case BRW_OPCODE_SEL:
1614 brw_SEL(p, dst, src[0], src[1]);
1615 break;
1616
1617 case BRW_OPCODE_DPH:
1618 brw_DPH(p, dst, src[0], src[1]);
1619 break;
1620
1621 case BRW_OPCODE_DP4:
1622 brw_DP4(p, dst, src[0], src[1]);
1623 break;
1624
1625 case BRW_OPCODE_DP3:
1626 brw_DP3(p, dst, src[0], src[1]);
1627 break;
1628
1629 case BRW_OPCODE_DP2:
1630 brw_DP2(p, dst, src[0], src[1]);
1631 break;
1632
1633 case BRW_OPCODE_F32TO16:
1634 assert(devinfo->gen >= 7);
1635 brw_F32TO16(p, dst, src[0]);
1636 break;
1637
1638 case BRW_OPCODE_F16TO32:
1639 assert(devinfo->gen >= 7);
1640 brw_F16TO32(p, dst, src[0]);
1641 break;
1642
1643 case BRW_OPCODE_LRP:
1644 assert(devinfo->gen >= 6);
1645 brw_LRP(p, dst, src[0], src[1], src[2]);
1646 break;
1647
1648 case BRW_OPCODE_BFREV:
1649 assert(devinfo->gen >= 7);
1650 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1651 retype(src[0], BRW_REGISTER_TYPE_UD));
1652 break;
1653 case BRW_OPCODE_FBH:
1654 assert(devinfo->gen >= 7);
1655 brw_FBH(p, retype(dst, src[0].type), src[0]);
1656 break;
1657 case BRW_OPCODE_FBL:
1658 assert(devinfo->gen >= 7);
1659 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD),
1660 retype(src[0], BRW_REGISTER_TYPE_UD));
1661 break;
1662 case BRW_OPCODE_LZD:
1663 brw_LZD(p, dst, src[0]);
1664 break;
1665 case BRW_OPCODE_CBIT:
1666 assert(devinfo->gen >= 7);
1667 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD),
1668 retype(src[0], BRW_REGISTER_TYPE_UD));
1669 break;
1670 case BRW_OPCODE_ADDC:
1671 assert(devinfo->gen >= 7);
1672 brw_ADDC(p, dst, src[0], src[1]);
1673 break;
1674 case BRW_OPCODE_SUBB:
1675 assert(devinfo->gen >= 7);
1676 brw_SUBB(p, dst, src[0], src[1]);
1677 break;
1678 case BRW_OPCODE_MAC:
1679 brw_MAC(p, dst, src[0], src[1]);
1680 break;
1681
1682 case BRW_OPCODE_BFE:
1683 assert(devinfo->gen >= 7);
1684 brw_BFE(p, dst, src[0], src[1], src[2]);
1685 break;
1686
1687 case BRW_OPCODE_BFI1:
1688 assert(devinfo->gen >= 7);
1689 brw_BFI1(p, dst, src[0], src[1]);
1690 break;
1691 case BRW_OPCODE_BFI2:
1692 assert(devinfo->gen >= 7);
1693 brw_BFI2(p, dst, src[0], src[1], src[2]);
1694 break;
1695
1696 case BRW_OPCODE_IF:
1697 if (!inst->src[0].is_null()) {
1698 /* The instruction has an embedded compare (only allowed on gen6) */
1699 assert(devinfo->gen == 6);
1700 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1701 } else {
1702 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1703 brw_inst_set_pred_control(p->devinfo, if_inst, inst->predicate);
1704 }
1705 break;
1706
1707 case BRW_OPCODE_ELSE:
1708 brw_ELSE(p);
1709 break;
1710 case BRW_OPCODE_ENDIF:
1711 brw_ENDIF(p);
1712 break;
1713
1714 case BRW_OPCODE_DO:
1715 brw_DO(p, BRW_EXECUTE_8);
1716 break;
1717
1718 case BRW_OPCODE_BREAK:
1719 brw_BREAK(p);
1720 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1721 break;
1722 case BRW_OPCODE_CONTINUE:
1723 brw_CONT(p);
1724 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1725 break;
1726
1727 case BRW_OPCODE_WHILE:
1728 brw_WHILE(p);
1729 loop_count++;
1730 break;
1731
1732 case SHADER_OPCODE_RCP:
1733 case SHADER_OPCODE_RSQ:
1734 case SHADER_OPCODE_SQRT:
1735 case SHADER_OPCODE_EXP2:
1736 case SHADER_OPCODE_LOG2:
1737 case SHADER_OPCODE_SIN:
1738 case SHADER_OPCODE_COS:
1739 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1740 if (devinfo->gen >= 7) {
1741 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1742 brw_null_reg());
1743 } else if (devinfo->gen == 6) {
1744 generate_math_gen6(p, inst, dst, src[0], brw_null_reg());
1745 } else {
1746 generate_math1_gen4(p, inst, dst, src[0]);
1747 }
1748 break;
1749
1750 case SHADER_OPCODE_POW:
1751 case SHADER_OPCODE_INT_QUOTIENT:
1752 case SHADER_OPCODE_INT_REMAINDER:
1753 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1754 if (devinfo->gen >= 7) {
1755 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1756 } else if (devinfo->gen == 6) {
1757 generate_math_gen6(p, inst, dst, src[0], src[1]);
1758 } else {
1759 generate_math2_gen4(p, inst, dst, src[0], src[1]);
1760 }
1761 break;
1762
1763 case SHADER_OPCODE_TEX:
1764 case SHADER_OPCODE_TXD:
1765 case SHADER_OPCODE_TXF:
1766 case SHADER_OPCODE_TXF_CMS:
1767 case SHADER_OPCODE_TXF_CMS_W:
1768 case SHADER_OPCODE_TXF_MCS:
1769 case SHADER_OPCODE_TXL:
1770 case SHADER_OPCODE_TXS:
1771 case SHADER_OPCODE_TG4:
1772 case SHADER_OPCODE_TG4_OFFSET:
1773 case SHADER_OPCODE_SAMPLEINFO:
1774 generate_tex(p, prog_data, nir->info.stage,
1775 inst, dst, src[0], src[1], src[2]);
1776 break;
1777
1778 case SHADER_OPCODE_GET_BUFFER_SIZE:
1779 generate_get_buffer_size(p, prog_data, inst, dst, src[0], src[1]);
1780 break;
1781
1782 case VS_OPCODE_URB_WRITE:
1783 generate_vs_urb_write(p, inst);
1784 break;
1785
1786 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1787 generate_scratch_read(p, inst, dst, src[0]);
1788 fill_count++;
1789 break;
1790
1791 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1792 generate_scratch_write(p, inst, dst, src[0], src[1]);
1793 spill_count++;
1794 break;
1795
1796 case VS_OPCODE_PULL_CONSTANT_LOAD:
1797 generate_pull_constant_load(p, prog_data, inst, dst, src[0], src[1]);
1798 break;
1799
1800 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1801 generate_pull_constant_load_gen7(p, prog_data, inst, dst, src[0], src[1]);
1802 break;
1803
1804 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
1805 generate_set_simd4x2_header_gen9(p, inst, dst);
1806 break;
1807
1808 case GS_OPCODE_URB_WRITE:
1809 generate_gs_urb_write(p, inst);
1810 break;
1811
1812 case GS_OPCODE_URB_WRITE_ALLOCATE:
1813 generate_gs_urb_write_allocate(p, inst);
1814 break;
1815
1816 case GS_OPCODE_SVB_WRITE:
1817 generate_gs_svb_write(p, prog_data, inst, dst, src[0], src[1]);
1818 break;
1819
1820 case GS_OPCODE_SVB_SET_DST_INDEX:
1821 generate_gs_svb_set_destination_index(p, inst, dst, src[0]);
1822 break;
1823
1824 case GS_OPCODE_THREAD_END:
1825 generate_gs_thread_end(p, inst);
1826 break;
1827
1828 case GS_OPCODE_SET_WRITE_OFFSET:
1829 generate_gs_set_write_offset(p, dst, src[0], src[1]);
1830 break;
1831
1832 case GS_OPCODE_SET_VERTEX_COUNT:
1833 generate_gs_set_vertex_count(p, dst, src[0]);
1834 break;
1835
1836 case GS_OPCODE_FF_SYNC:
1837 generate_gs_ff_sync(p, inst, dst, src[0], src[1]);
1838 break;
1839
1840 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1841 generate_gs_ff_sync_set_primitives(p, dst, src[0], src[1], src[2]);
1842 break;
1843
1844 case GS_OPCODE_SET_PRIMITIVE_ID:
1845 generate_gs_set_primitive_id(p, dst);
1846 break;
1847
1848 case GS_OPCODE_SET_DWORD_2:
1849 generate_gs_set_dword_2(p, dst, src[0]);
1850 break;
1851
1852 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1853 generate_gs_prepare_channel_masks(p, dst);
1854 break;
1855
1856 case GS_OPCODE_SET_CHANNEL_MASKS:
1857 generate_gs_set_channel_masks(p, dst, src[0]);
1858 break;
1859
1860 case GS_OPCODE_GET_INSTANCE_ID:
1861 generate_gs_get_instance_id(p, dst);
1862 break;
1863
1864 case SHADER_OPCODE_SHADER_TIME_ADD:
1865 brw_shader_time_add(p, src[0],
1866 prog_data->base.binding_table.shader_time_start);
1867 break;
1868
1869 case VEC4_OPCODE_UNTYPED_ATOMIC:
1870 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1871 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud, inst->mlen,
1872 !inst->dst.is_null(), inst->header_size);
1873 break;
1874
1875 case VEC4_OPCODE_UNTYPED_SURFACE_READ:
1876 assert(!inst->header_size);
1877 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1878 brw_untyped_surface_read(p, dst, src[0], src[1], inst->mlen,
1879 src[2].ud);
1880 break;
1881
1882 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1883 assert(src[2].file == BRW_IMMEDIATE_VALUE);
1884 brw_untyped_surface_write(p, src[0], src[1], inst->mlen,
1885 src[2].ud, inst->header_size);
1886 break;
1887
1888 case SHADER_OPCODE_MEMORY_FENCE:
1889 brw_memory_fence(p, dst, src[0], BRW_OPCODE_SEND, false, /* bti */ 0);
1890 break;
1891
1892 case SHADER_OPCODE_FIND_LIVE_CHANNEL: {
1893 const struct brw_reg mask =
1894 brw_stage_has_packed_dispatch(devinfo, nir->info.stage,
1895 &prog_data->base) ? brw_imm_ud(~0u) :
1896 brw_dmask_reg();
1897 brw_find_live_channel(p, dst, mask);
1898 break;
1899 }
1900
1901 case SHADER_OPCODE_BROADCAST:
1902 assert(inst->force_writemask_all);
1903 brw_broadcast(p, dst, src[0], src[1]);
1904 break;
1905
1906 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1907 generate_unpack_flags(p, dst);
1908 break;
1909
1910 case VEC4_OPCODE_MOV_BYTES: {
1911 /* Moves the low byte from each channel, using an Align1 access mode
1912 * and a <4,1,0> source region.
1913 */
1914 assert(src[0].type == BRW_REGISTER_TYPE_UB ||
1915 src[0].type == BRW_REGISTER_TYPE_B);
1916
1917 brw_set_default_access_mode(p, BRW_ALIGN_1);
1918 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1919 src[0].width = BRW_WIDTH_1;
1920 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1921 brw_MOV(p, dst, src[0]);
1922 brw_set_default_access_mode(p, BRW_ALIGN_16);
1923 break;
1924 }
1925
1926 case VEC4_OPCODE_DOUBLE_TO_F32:
1927 case VEC4_OPCODE_DOUBLE_TO_D32:
1928 case VEC4_OPCODE_DOUBLE_TO_U32: {
1929 assert(type_sz(src[0].type) == 8);
1930 assert(type_sz(dst.type) == 8);
1931
1932 brw_reg_type dst_type;
1933
1934 switch (inst->opcode) {
1935 case VEC4_OPCODE_DOUBLE_TO_F32:
1936 dst_type = BRW_REGISTER_TYPE_F;
1937 break;
1938 case VEC4_OPCODE_DOUBLE_TO_D32:
1939 dst_type = BRW_REGISTER_TYPE_D;
1940 break;
1941 case VEC4_OPCODE_DOUBLE_TO_U32:
1942 dst_type = BRW_REGISTER_TYPE_UD;
1943 break;
1944 default:
1945 unreachable("Not supported conversion");
1946 }
1947 dst = retype(dst, dst_type);
1948
1949 brw_set_default_access_mode(p, BRW_ALIGN_1);
1950
1951 /* When converting from DF->F, we set destination's stride as 2 as an
1952 * aligment requirement. But in IVB/BYT, each DF implicitly writes
1953 * two floats, being the first one the converted value. So we don't
1954 * need to explicitly set stride 2, but 1.
1955 */
1956 struct brw_reg spread_dst;
1957 if (devinfo->gen == 7 && !devinfo->is_haswell)
1958 spread_dst = stride(dst, 8, 4, 1);
1959 else
1960 spread_dst = stride(dst, 8, 4, 2);
1961
1962 brw_MOV(p, spread_dst, src[0]);
1963
1964 brw_set_default_access_mode(p, BRW_ALIGN_16);
1965 break;
1966 }
1967
1968 case VEC4_OPCODE_TO_DOUBLE: {
1969 assert(type_sz(src[0].type) == 4);
1970 assert(type_sz(dst.type) == 8);
1971
1972 brw_set_default_access_mode(p, BRW_ALIGN_1);
1973
1974 brw_MOV(p, dst, src[0]);
1975
1976 brw_set_default_access_mode(p, BRW_ALIGN_16);
1977 break;
1978 }
1979
1980 case VEC4_OPCODE_PICK_LOW_32BIT:
1981 case VEC4_OPCODE_PICK_HIGH_32BIT: {
1982 /* Stores the low/high 32-bit of each 64-bit element in src[0] into
1983 * dst using ALIGN1 mode and a <8,4,2>:UD region on the source.
1984 */
1985 assert(type_sz(src[0].type) == 8);
1986 assert(type_sz(dst.type) == 4);
1987
1988 brw_set_default_access_mode(p, BRW_ALIGN_1);
1989
1990 dst = retype(dst, BRW_REGISTER_TYPE_UD);
1991 dst.hstride = BRW_HORIZONTAL_STRIDE_1;
1992
1993 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
1994 if (inst->opcode == VEC4_OPCODE_PICK_HIGH_32BIT)
1995 src[0] = suboffset(src[0], 1);
1996 src[0] = spread(src[0], 2);
1997 brw_MOV(p, dst, src[0]);
1998
1999 brw_set_default_access_mode(p, BRW_ALIGN_16);
2000 break;
2001 }
2002
2003 case VEC4_OPCODE_SET_LOW_32BIT:
2004 case VEC4_OPCODE_SET_HIGH_32BIT: {
2005 /* Reads consecutive 32-bit elements from src[0] and writes
2006 * them to the low/high 32-bit of each 64-bit element in dst.
2007 */
2008 assert(type_sz(src[0].type) == 4);
2009 assert(type_sz(dst.type) == 8);
2010
2011 brw_set_default_access_mode(p, BRW_ALIGN_1);
2012
2013 dst = retype(dst, BRW_REGISTER_TYPE_UD);
2014 if (inst->opcode == VEC4_OPCODE_SET_HIGH_32BIT)
2015 dst = suboffset(dst, 1);
2016 dst.hstride = BRW_HORIZONTAL_STRIDE_2;
2017
2018 src[0] = retype(src[0], BRW_REGISTER_TYPE_UD);
2019 brw_MOV(p, dst, src[0]);
2020
2021 brw_set_default_access_mode(p, BRW_ALIGN_16);
2022 break;
2023 }
2024
2025 case VEC4_OPCODE_PACK_BYTES: {
2026 /* Is effectively:
2027 *
2028 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
2029 *
2030 * but destinations' only regioning is horizontal stride, so instead we
2031 * have to use two instructions:
2032 *
2033 * mov(4) dst<1>:UB src<4,1,0>:UB
2034 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
2035 *
2036 * where they pack the four bytes from the low and high four DW.
2037 */
2038 assert(_mesa_is_pow_two(dst.writemask) &&
2039 dst.writemask != 0);
2040 unsigned offset = __builtin_ctz(dst.writemask);
2041
2042 dst.type = BRW_REGISTER_TYPE_UB;
2043
2044 brw_set_default_access_mode(p, BRW_ALIGN_1);
2045
2046 src[0].type = BRW_REGISTER_TYPE_UB;
2047 src[0].vstride = BRW_VERTICAL_STRIDE_4;
2048 src[0].width = BRW_WIDTH_1;
2049 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
2050 dst.subnr = offset * 4;
2051 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
2052 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2053 brw_inst_set_no_dd_clear(p->devinfo, insn, true);
2054 brw_inst_set_no_dd_check(p->devinfo, insn, inst->no_dd_check);
2055
2056 src[0].subnr = 16;
2057 dst.subnr = 16 + offset * 4;
2058 insn = brw_MOV(p, dst, src[0]);
2059 brw_inst_set_exec_size(p->devinfo, insn, BRW_EXECUTE_4);
2060 brw_inst_set_no_dd_clear(p->devinfo, insn, inst->no_dd_clear);
2061 brw_inst_set_no_dd_check(p->devinfo, insn, true);
2062
2063 brw_set_default_access_mode(p, BRW_ALIGN_16);
2064 break;
2065 }
2066
2067 case TCS_OPCODE_URB_WRITE:
2068 generate_tcs_urb_write(p, inst, src[0]);
2069 break;
2070
2071 case VEC4_OPCODE_URB_READ:
2072 generate_vec4_urb_read(p, inst, dst, src[0]);
2073 break;
2074
2075 case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
2076 generate_tcs_input_urb_offsets(p, dst, src[0], src[1]);
2077 break;
2078
2079 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
2080 generate_tcs_output_urb_offsets(p, dst, src[0], src[1]);
2081 break;
2082
2083 case TCS_OPCODE_GET_INSTANCE_ID:
2084 generate_tcs_get_instance_id(p, dst);
2085 break;
2086
2087 case TCS_OPCODE_GET_PRIMITIVE_ID:
2088 generate_tcs_get_primitive_id(p, dst);
2089 break;
2090
2091 case TCS_OPCODE_CREATE_BARRIER_HEADER:
2092 generate_tcs_create_barrier_header(p, prog_data, dst);
2093 break;
2094
2095 case TES_OPCODE_CREATE_INPUT_READ_HEADER:
2096 generate_tes_create_input_read_header(p, dst);
2097 break;
2098
2099 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
2100 generate_tes_add_indirect_urb_offset(p, dst, src[0], src[1]);
2101 break;
2102
2103 case TES_OPCODE_GET_PRIMITIVE_ID:
2104 generate_tes_get_primitive_id(p, dst);
2105 break;
2106
2107 case TCS_OPCODE_SRC0_010_IS_ZERO:
2108 /* If src_reg had stride like fs_reg, we wouldn't need this. */
2109 brw_MOV(p, brw_null_reg(), stride(src[0], 0, 1, 0));
2110 break;
2111
2112 case TCS_OPCODE_RELEASE_INPUT:
2113 generate_tcs_release_input(p, dst, src[0], src[1]);
2114 break;
2115
2116 case TCS_OPCODE_THREAD_END:
2117 generate_tcs_thread_end(p, inst);
2118 break;
2119
2120 case SHADER_OPCODE_BARRIER:
2121 brw_barrier(p, src[0]);
2122 brw_WAIT(p);
2123 break;
2124
2125 case SHADER_OPCODE_MOV_INDIRECT:
2126 generate_mov_indirect(p, inst, dst, src[0], src[1]);
2127 break;
2128
2129 case BRW_OPCODE_DIM:
2130 assert(devinfo->is_haswell);
2131 assert(src[0].type == BRW_REGISTER_TYPE_DF);
2132 assert(dst.type == BRW_REGISTER_TYPE_DF);
2133 brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
2134 break;
2135
2136 default:
2137 unreachable("Unsupported opcode");
2138 }
2139
2140 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
2141 /* Handled dependency hints in the generator. */
2142
2143 assert(!inst->conditional_mod);
2144 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2145 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
2146 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2147 "emitting more than 1 instruction");
2148
2149 brw_inst *last = &p->store[pre_emit_nr_insn];
2150
2151 if (inst->conditional_mod)
2152 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2153 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2154 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2155 }
2156 }
2157
2158 brw_set_uip_jip(p, 0);
2159
2160 /* end of program sentinel */
2161 disasm_new_inst_group(disasm_info, p->next_insn_offset);
2162
2163 #ifndef NDEBUG
2164 bool validated =
2165 #else
2166 if (unlikely(debug_flag))
2167 #endif
2168 brw_validate_instructions(devinfo, p->store,
2169 0, p->next_insn_offset,
2170 disasm_info);
2171
2172 int before_size = p->next_insn_offset;
2173 brw_compact_instructions(p, 0, disasm_info);
2174 int after_size = p->next_insn_offset;
2175
2176 if (unlikely(debug_flag)) {
2177 fprintf(stderr, "Native code for %s %s shader %s:\n",
2178 nir->info.label ? nir->info.label : "unnamed",
2179 _mesa_shader_stage_to_string(nir->info.stage), nir->info.name);
2180
2181 fprintf(stderr, "%s vec4 shader: %d instructions. %d loops. %u cycles. %d:%d "
2182 "spills:fills. Compacted %d to %d bytes (%.0f%%)\n",
2183 stage_abbrev, before_size / 16, loop_count, cfg->cycle_count,
2184 spill_count, fill_count, before_size, after_size,
2185 100.0f * (before_size - after_size) / before_size);
2186
2187 dump_assembly(p->store, disasm_info);
2188 }
2189 ralloc_free(disasm_info);
2190 assert(validated);
2191
2192 compiler->shader_debug_log(log_data,
2193 "%s vec4 shader: %d inst, %d loops, %u cycles, "
2194 "%d:%d spills:fills, compacted %d to %d bytes.",
2195 stage_abbrev, before_size / 16,
2196 loop_count, cfg->cycle_count, spill_count,
2197 fill_count, before_size, after_size);
2198
2199 }
2200
2201 extern "C" const unsigned *
2202 brw_vec4_generate_assembly(const struct brw_compiler *compiler,
2203 void *log_data,
2204 void *mem_ctx,
2205 const nir_shader *nir,
2206 struct brw_vue_prog_data *prog_data,
2207 const struct cfg_t *cfg)
2208 {
2209 struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
2210 brw_init_codegen(compiler->devinfo, p, mem_ctx);
2211 brw_set_default_access_mode(p, BRW_ALIGN_16);
2212
2213 generate_code(p, compiler, log_data, nir, prog_data, cfg);
2214
2215 return brw_get_program(p, &prog_data->base.program_size);
2216 }