2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 /* get the main function and emit it */
41 nir_foreach_function(function
, nir
) {
42 assert(strcmp(function
->name
, "main") == 0);
43 assert(function
->impl
);
44 nir_emit_impl(function
->impl
);
49 vec4_visitor::nir_setup_uniforms()
51 uniforms
= nir
->num_uniforms
/ 16;
55 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
57 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
58 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
59 nir_locals
[i
] = dst_reg();
62 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
63 unsigned array_elems
=
64 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
65 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
66 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
68 if (reg
->bit_size
== 64)
69 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
72 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
74 nir_emit_cf_list(&impl
->body
);
78 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
80 exec_list_validate(list
);
81 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
84 nir_emit_if(nir_cf_node_as_if(node
));
87 case nir_cf_node_loop
:
88 nir_emit_loop(nir_cf_node_as_loop(node
));
91 case nir_cf_node_block
:
92 nir_emit_block(nir_cf_node_as_block(node
));
96 unreachable("Invalid CFG node block");
102 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
104 /* First, put the condition in f0 */
105 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
106 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
107 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
109 /* We can just predicate based on the X channel, as the condition only
110 * goes on its own line */
111 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
113 nir_emit_cf_list(&if_stmt
->then_list
);
115 /* note: if the else is empty, dead CF elimination will remove it */
116 emit(BRW_OPCODE_ELSE
);
118 nir_emit_cf_list(&if_stmt
->else_list
);
120 emit(BRW_OPCODE_ENDIF
);
124 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
128 nir_emit_cf_list(&loop
->body
);
130 emit(BRW_OPCODE_WHILE
);
134 vec4_visitor::nir_emit_block(nir_block
*block
)
136 nir_foreach_instr(instr
, block
) {
137 nir_emit_instr(instr
);
142 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
146 switch (instr
->type
) {
147 case nir_instr_type_load_const
:
148 nir_emit_load_const(nir_instr_as_load_const(instr
));
151 case nir_instr_type_intrinsic
:
152 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
155 case nir_instr_type_alu
:
156 nir_emit_alu(nir_instr_as_alu(instr
));
159 case nir_instr_type_jump
:
160 nir_emit_jump(nir_instr_as_jump(instr
));
163 case nir_instr_type_tex
:
164 nir_emit_texture(nir_instr_as_tex(instr
));
167 case nir_instr_type_ssa_undef
:
168 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
172 unreachable("VS instruction not yet implemented by NIR->vec4");
177 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
178 unsigned base_offset
, nir_src
*indirect
)
182 reg
= v
->nir_locals
[nir_reg
->index
];
183 if (nir_reg
->bit_size
== 64)
184 reg
.type
= BRW_REGISTER_TYPE_DF
;
185 reg
= offset(reg
, 8, base_offset
);
188 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
196 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
200 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
201 if (dest
.ssa
.bit_size
== 64)
202 dst
.type
= BRW_REGISTER_TYPE_DF
;
203 nir_ssa_values
[dest
.ssa
.index
] = dst
;
206 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
212 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
214 return retype(get_nir_dest(dest
), type
);
218 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
220 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
224 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
225 unsigned num_components
)
230 assert(src
.ssa
!= NULL
);
231 reg
= nir_ssa_values
[src
.ssa
->index
];
234 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
238 reg
= retype(reg
, type
);
240 src_reg reg_as_src
= src_reg(reg
);
241 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
246 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
247 unsigned num_components
)
249 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
254 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
256 /* if type is not specified, default to signed int */
257 return get_nir_src(src
, nir_type_int32
, num_components
);
261 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
263 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
264 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
267 /* The only constant offset we should find is 0. brw_nir.c's
268 * add_const_offset_to_base() will fold other constant offsets
269 * into instr->const_index[0].
271 assert(const_value
->u32
[0] == 0);
275 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
279 setup_imm_df(const vec4_builder
&bld
, double v
)
281 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
282 assert(devinfo
->gen
>= 7);
284 if (devinfo
->gen
>= 8)
285 return brw_imm_df(v
);
287 /* gen7.5 does not support DF immediates straighforward but the DIM
288 * instruction allows to set the 64-bit immediate value.
290 if (devinfo
->is_haswell
) {
291 const vec4_builder ubld
= bld
.exec_all();
292 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
293 ubld
.DIM(dst
, brw_imm_df(v
));
294 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
297 /* gen7 does not support DF immediates */
308 /* Write the low 32-bit of the constant to the X:UD channel and the
309 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
310 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
311 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
312 * XXXX so any access to the VGRF only reads the constant data in these
315 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
316 for (unsigned n
= 0; n
< 2; n
++) {
317 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
318 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
319 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
322 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
326 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
330 if (instr
->def
.bit_size
== 64) {
331 reg
= dst_reg(VGRF
, alloc
.allocate(2));
332 reg
.type
= BRW_REGISTER_TYPE_DF
;
334 reg
= dst_reg(VGRF
, alloc
.allocate(1));
335 reg
.type
= BRW_REGISTER_TYPE_D
;
338 const vec4_builder ibld
= vec4_builder(this).at_end();
339 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
341 /* @FIXME: consider emitting vector operations to save some MOVs in
342 * cases where the components are representable in 8 bits.
343 * For now, we emit a MOV for each distinct value.
345 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
346 unsigned writemask
= 1 << i
;
348 if ((remaining
& writemask
) == 0)
351 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
352 if ((instr
->def
.bit_size
== 32 &&
353 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
354 (instr
->def
.bit_size
== 64 &&
355 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
360 reg
.writemask
= writemask
;
361 if (instr
->def
.bit_size
== 64) {
362 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
364 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
367 remaining
&= ~writemask
;
370 /* Set final writemask */
371 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
373 nir_ssa_values
[instr
->def
.index
] = reg
;
377 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
382 switch (instr
->intrinsic
) {
384 case nir_intrinsic_load_input
: {
385 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
387 /* We set EmitNoIndirectInput for VS */
388 assert(const_offset
);
390 dest
= get_nir_dest(instr
->dest
);
391 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
393 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
394 glsl_type::uvec4_type
);
395 src
= retype(src
, dest
.type
);
397 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
399 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
400 src
.swizzle
= BRW_SWIZZLE_XYZW
;
401 shuffle_64bit_data(tmp
, src
, false);
402 emit(MOV(dest
, src_reg(tmp
)));
404 /* Swizzle source based on component layout qualifier */
405 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
406 emit(MOV(dest
, src
));
411 case nir_intrinsic_store_output
: {
412 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
413 assert(const_offset
);
415 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
417 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
420 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
421 instr
->num_components
);
422 data
= src_reg(this, glsl_type::dvec4_type
);
423 shuffle_64bit_data(dst_reg(data
), src
, true);
424 src
= retype(data
, BRW_REGISTER_TYPE_F
);
426 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
427 instr
->num_components
);
430 unsigned c
= nir_intrinsic_component(instr
);
431 output_reg
[varying
][c
] = dst_reg(src
);
432 output_num_components
[varying
][c
] = instr
->num_components
;
434 unsigned num_components
= instr
->num_components
;
438 output_reg
[varying
][c
] = dst_reg(src
);
439 output_num_components
[varying
][c
] = MIN2(4, num_components
);
441 if (is_64bit
&& num_components
> 4) {
442 assert(num_components
<= 8);
443 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
444 output_num_components
[varying
+ 1][c
] = num_components
- 4;
449 case nir_intrinsic_get_buffer_size
: {
450 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
451 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
453 const unsigned index
=
454 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
455 dst_reg result_dst
= get_nir_dest(instr
->dest
);
456 vec4_instruction
*inst
= new(mem_ctx
)
457 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE
, result_dst
);
460 inst
->mlen
= 1; /* always at least one */
461 inst
->src
[1] = brw_imm_ud(index
);
463 /* MRF for the first parameter */
464 src_reg lod
= brw_imm_d(0);
465 int param_base
= inst
->base_mrf
;
466 int writemask
= WRITEMASK_X
;
467 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
471 brw_mark_surface_used(&prog_data
->base
, index
);
475 case nir_intrinsic_store_ssbo
: {
476 assert(devinfo
->gen
>= 7);
480 nir_const_value
*const_uniform_block
=
481 nir_src_as_const_value(instr
->src
[1]);
482 if (const_uniform_block
) {
483 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
484 const_uniform_block
->u32
[0];
485 surf_index
= brw_imm_ud(index
);
486 brw_mark_surface_used(&prog_data
->base
, index
);
488 surf_index
= src_reg(this, glsl_type::uint_type
);
489 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
490 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
491 surf_index
= emit_uniformize(surf_index
);
493 brw_mark_surface_used(&prog_data
->base
,
494 prog_data
->base
.binding_table
.ssbo_start
+
495 nir
->info
.num_ssbos
- 1);
500 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
502 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
504 offset_reg
= get_nir_src(instr
->src
[2], 1);
508 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
511 unsigned write_mask
= instr
->const_index
[0];
513 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
514 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
515 * typed and untyped messages and across hardware platforms, the
516 * current implementation of the untyped messages will transparently convert
517 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
518 * and enabling only channel X on the SEND instruction.
520 * The above, works well for full vector writes, but not for partial writes
521 * where we want to write some channels and not others, like when we have
522 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
523 * quite restrictive with regards to the channel enables we can configure in
524 * the message descriptor (not all combinations are allowed) we cannot simply
525 * implement these scenarios with a single message while keeping the
526 * aforementioned symmetry in the implementation. For now we de decided that
527 * it is better to keep the symmetry to reduce complexity, so in situations
528 * such as the one described we end up emitting two untyped write messages
529 * (one for xy and another for w).
531 * The code below packs consecutive channels into a single write message,
532 * detects gaps in the vector write and if needed, sends a second message
533 * with the remaining channels. If in the future we decide that we want to
534 * emit a single message at the expense of losing the symmetry in the
535 * implementation we can:
537 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
538 * message payload. In this mode we can write up to 8 offsets and dwords
539 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
540 * and select which of the 8 channels carry data to write by setting the
541 * appropriate writemask in the dst register of the SEND instruction.
542 * It would require to write a new generator opcode specifically for
543 * IvyBridge since we would need to prepare a SIMD8 payload that could
544 * use any channel, not just X.
546 * 2) For Haswell+: Simply send a single write message but set the writemask
547 * on the dst of the SEND instruction to select the channels we want to
548 * write. It would require to modify the current messages to receive
549 * and honor the writemask provided.
551 const vec4_builder bld
= vec4_builder(this).at_end()
552 .annotate(current_annotation
, base_ir
);
554 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
555 if (type_slots
== 2) {
556 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
557 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
558 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
561 uint8_t swizzle
[4] = { 0, 0, 0, 0};
562 int num_channels
= 0;
563 unsigned skipped_channels
= 0;
564 int num_components
= instr
->num_components
;
565 for (int i
= 0; i
< num_components
; i
++) {
566 /* Read components Z/W of a dvec from the appropriate place. We will
567 * also have to adjust the swizzle (we do that with the '% 4' below)
569 if (i
== 2 && type_slots
== 2)
570 val_reg
= byte_offset(val_reg
, REG_SIZE
);
572 /* Check if this channel needs to be written. If so, record the
573 * channel we need to take the data from in the swizzle array
575 int component_mask
= 1 << i
;
576 int write_test
= write_mask
& component_mask
;
578 /* If we are writing doubles we have to write 2 channels worth of
579 * of data (64 bits) for each double component.
581 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
583 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
586 /* If we don't have to write this channel it means we have a gap in the
587 * vector, so write the channels we accumulated until now, if any. Do
588 * the same if this was the last component in the vector, if we have
589 * enough channels for a full vec4 write or if we have processed
590 * components XY of a dvec (since components ZW are not in the same
593 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
594 (i
== 1 && type_slots
== 2)) {
595 if (num_channels
> 0) {
596 /* We have channels to write, so update the offset we need to
597 * write at to skip the channels we skipped, if any.
599 if (skipped_channels
> 0) {
600 if (offset_reg
.file
== IMM
) {
601 offset_reg
.ud
+= 4 * skipped_channels
;
603 emit(ADD(dst_reg(offset_reg
), offset_reg
,
604 brw_imm_ud(4 * skipped_channels
)));
608 /* Swizzle the data register so we take the data from the channels
609 * we need to write and send the write message. This will write
610 * num_channels consecutive dwords starting at offset.
613 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
614 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
615 1 /* dims */, num_channels
/* size */,
618 /* If we have to do a second write we will have to update the
619 * offset so that we jump over the channels we have just written
622 skipped_channels
= num_channels
;
624 /* Restart the count for the next write message */
628 /* If we didn't write the channel, increase skipped count */
630 skipped_channels
+= type_slots
;
637 case nir_intrinsic_load_ssbo
: {
638 assert(devinfo
->gen
>= 7);
640 nir_const_value
*const_uniform_block
=
641 nir_src_as_const_value(instr
->src
[0]);
644 if (const_uniform_block
) {
645 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
646 const_uniform_block
->u32
[0];
647 surf_index
= brw_imm_ud(index
);
649 brw_mark_surface_used(&prog_data
->base
, index
);
651 surf_index
= src_reg(this, glsl_type::uint_type
);
652 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
653 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
654 surf_index
= emit_uniformize(surf_index
);
656 /* Assume this may touch any UBO. It would be nice to provide
657 * a tighter bound, but the array information is already lowered away.
659 brw_mark_surface_used(&prog_data
->base
,
660 prog_data
->base
.binding_table
.ssbo_start
+
661 nir
->info
.num_ssbos
- 1);
665 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
667 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
669 offset_reg
= get_nir_src(instr
->src
[1], 1);
672 /* Read the vector */
673 const vec4_builder bld
= vec4_builder(this).at_end()
674 .annotate(current_annotation
, base_ir
);
677 dst_reg dest
= get_nir_dest(instr
->dest
);
678 if (type_sz(dest
.type
) < 8) {
679 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
680 1 /* dims */, 4 /* size*/,
683 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
686 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
687 1 /* dims */, 4 /* size*/,
689 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
691 if (offset_reg
.file
== IMM
)
694 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
696 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
697 1 /* dims */, 4 /* size*/,
699 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
702 read_result
= src_reg(this, glsl_type::dvec4_type
);
703 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
706 read_result
.type
= dest
.type
;
707 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
708 emit(MOV(dest
, read_result
));
712 case nir_intrinsic_ssbo_atomic_add
: {
713 int op
= BRW_AOP_ADD
;
714 const nir_const_value
*const val
= nir_src_as_const_value(instr
->src
[2]);
717 if (val
->i32
[0] == 1)
719 else if (val
->i32
[0] == -1)
723 nir_emit_ssbo_atomic(op
, instr
);
726 case nir_intrinsic_ssbo_atomic_imin
:
727 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
729 case nir_intrinsic_ssbo_atomic_umin
:
730 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
732 case nir_intrinsic_ssbo_atomic_imax
:
733 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
735 case nir_intrinsic_ssbo_atomic_umax
:
736 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
738 case nir_intrinsic_ssbo_atomic_and
:
739 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
741 case nir_intrinsic_ssbo_atomic_or
:
742 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
744 case nir_intrinsic_ssbo_atomic_xor
:
745 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
747 case nir_intrinsic_ssbo_atomic_exchange
:
748 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
750 case nir_intrinsic_ssbo_atomic_comp_swap
:
751 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
754 case nir_intrinsic_load_vertex_id
:
755 unreachable("should be lowered by lower_vertex_id()");
757 case nir_intrinsic_load_vertex_id_zero_base
:
758 case nir_intrinsic_load_base_vertex
:
759 case nir_intrinsic_load_instance_id
:
760 case nir_intrinsic_load_base_instance
:
761 case nir_intrinsic_load_draw_id
:
762 case nir_intrinsic_load_invocation_id
:
763 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
765 case nir_intrinsic_load_uniform
: {
766 /* Offsets are in bytes but they should always be multiples of 4 */
767 assert(nir_intrinsic_base(instr
) % 4 == 0);
769 dest
= get_nir_dest(instr
->dest
);
771 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
772 src
.type
= dest
.type
;
774 /* Uniforms don't actually have to be vec4 aligned. In the case that
775 * it isn't, we have to use a swizzle to shift things around. They
776 * do still have the std140 alignment requirement that vec2's have to
777 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
779 * The swizzle also works in the indirect case as the generator adds
780 * the swizzle to the offset for us.
782 const int type_size
= type_sz(src
.type
);
783 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
784 assert(shift
+ instr
->num_components
<= 4);
786 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
788 /* Offsets are in bytes but they should always be multiples of 4 */
789 assert(const_offset
->u32
[0] % 4 == 0);
791 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
792 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
793 unsigned offset
= const_offset
->u32
[0] + shift
* type_size
;
794 src
.offset
= ROUND_DOWN_TO(offset
, 16);
795 shift
= (offset
% 16) / type_size
;
796 assert(shift
+ instr
->num_components
<= 4);
797 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
799 emit(MOV(dest
, src
));
801 /* Uniform arrays are vec4 aligned, because of std140 alignment
806 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
808 /* MOV_INDIRECT is going to stomp the whole thing anyway */
809 dest
.writemask
= WRITEMASK_XYZW
;
811 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
812 indirect
, brw_imm_ud(instr
->const_index
[1]));
817 case nir_intrinsic_load_ubo
: {
818 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
821 dest
= get_nir_dest(instr
->dest
);
823 if (const_block_index
) {
824 /* The block index is a constant, so just emit the binding table entry
827 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
828 const_block_index
->u32
[0];
829 surf_index
= brw_imm_ud(index
);
830 brw_mark_surface_used(&prog_data
->base
, index
);
832 /* The block index is not a constant. Evaluate the index expression
833 * per-channel and add the base UBO index; we have to select a value
834 * from any live channel.
836 surf_index
= src_reg(this, glsl_type::uint_type
);
837 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
838 instr
->num_components
),
839 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
840 surf_index
= emit_uniformize(surf_index
);
842 /* Assume this may touch any UBO. It would be nice to provide
843 * a tighter bound, but the array information is already lowered away.
845 brw_mark_surface_used(&prog_data
->base
,
846 prog_data
->base
.binding_table
.ubo_start
+
847 nir
->info
.num_ubos
- 1);
851 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
853 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
855 offset_reg
= src_reg(this, glsl_type::uint_type
);
856 emit(MOV(dst_reg(offset_reg
),
857 get_nir_src(instr
->src
[1], nir_type_uint32
, 1)));
860 src_reg packed_consts
;
861 if (nir_dest_bit_size(instr
->dest
) == 32) {
862 packed_consts
= src_reg(this, glsl_type::vec4_type
);
863 emit_pull_constant_load_reg(dst_reg(packed_consts
),
866 NULL
, NULL
/* before_block/inst */);
868 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
869 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
871 emit_pull_constant_load_reg(dst_reg(temp_float
),
872 surf_index
, offset_reg
, NULL
, NULL
);
873 if (offset_reg
.file
== IMM
)
876 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
877 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
878 surf_index
, offset_reg
, NULL
, NULL
);
880 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
881 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
884 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
886 unsigned type_size
= type_sz(dest
.type
);
887 packed_consts
.swizzle
+=
888 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
889 const_offset
->u32
[0] % 16 / type_size
,
890 const_offset
->u32
[0] % 16 / type_size
,
891 const_offset
->u32
[0] % 16 / type_size
);
894 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
899 case nir_intrinsic_memory_barrier
: {
900 const vec4_builder bld
=
901 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
902 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
903 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
904 ->size_written
= 2 * REG_SIZE
;
908 case nir_intrinsic_shader_clock
: {
909 /* We cannot do anything if there is an event, so ignore it for now */
910 const src_reg shader_clock
= get_timestamp();
911 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
913 dest
= get_nir_dest(instr
->dest
, type
);
914 emit(MOV(dest
, shader_clock
));
919 unreachable("Unknown intrinsic");
924 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
927 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
928 dest
= get_nir_dest(instr
->dest
);
931 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
933 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
934 const_surface
->u32
[0];
935 surface
= brw_imm_ud(surf_index
);
936 brw_mark_surface_used(&prog_data
->base
, surf_index
);
938 surface
= src_reg(this, glsl_type::uint_type
);
939 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
940 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
942 /* Assume this may touch any UBO. This is the same we do for other
943 * UBO/SSBO accesses with non-constant surface.
945 brw_mark_surface_used(&prog_data
->base
,
946 prog_data
->base
.binding_table
.ssbo_start
+
947 nir
->info
.num_ssbos
- 1);
950 src_reg offset
= get_nir_src(instr
->src
[1], 1);
952 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
953 data1
= get_nir_src(instr
->src
[2], 1);
955 if (op
== BRW_AOP_CMPWR
)
956 data2
= get_nir_src(instr
->src
[3], 1);
958 /* Emit the actual atomic operation operation */
959 const vec4_builder bld
=
960 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
962 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
964 1 /* dims */, 1 /* rsize */,
967 dest
.type
= atomic_result
.type
;
968 bld
.MOV(dest
, atomic_result
);
972 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
974 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
977 static enum brw_conditional_mod
978 brw_conditional_for_nir_comparison(nir_op op
)
984 return BRW_CONDITIONAL_L
;
989 return BRW_CONDITIONAL_GE
;
993 case nir_op_ball_fequal2
:
994 case nir_op_ball_iequal2
:
995 case nir_op_ball_fequal3
:
996 case nir_op_ball_iequal3
:
997 case nir_op_ball_fequal4
:
998 case nir_op_ball_iequal4
:
999 return BRW_CONDITIONAL_Z
;
1003 case nir_op_bany_fnequal2
:
1004 case nir_op_bany_inequal2
:
1005 case nir_op_bany_fnequal3
:
1006 case nir_op_bany_inequal3
:
1007 case nir_op_bany_fnequal4
:
1008 case nir_op_bany_inequal4
:
1009 return BRW_CONDITIONAL_NZ
;
1012 unreachable("not reached: bad operation for comparison");
1017 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1018 enum brw_predicate
*predicate
)
1020 if (!instr
->src
[0].src
.is_ssa
||
1021 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1024 nir_alu_instr
*cmp_instr
=
1025 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1027 switch (cmp_instr
->op
) {
1028 case nir_op_bany_fnequal2
:
1029 case nir_op_bany_inequal2
:
1030 case nir_op_bany_fnequal3
:
1031 case nir_op_bany_inequal3
:
1032 case nir_op_bany_fnequal4
:
1033 case nir_op_bany_inequal4
:
1034 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1036 case nir_op_ball_fequal2
:
1037 case nir_op_ball_iequal2
:
1038 case nir_op_ball_fequal3
:
1039 case nir_op_ball_iequal3
:
1040 case nir_op_ball_fequal4
:
1041 case nir_op_ball_iequal4
:
1042 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1048 unsigned size_swizzle
=
1049 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1052 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1053 for (unsigned i
= 0; i
< 2; i
++) {
1054 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1055 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1056 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1057 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1058 unsigned base_swizzle
=
1059 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1060 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1061 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1062 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1065 emit(CMP(dst_null_d(), op
[0], op
[1],
1066 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1072 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1077 vec4_instruction
*inst
;
1081 /* LZD of an absolute value source almost always does the right
1082 * thing. There are two problem values:
1084 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1085 * 0. However, findMSB(int(0x80000000)) == 30.
1087 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1088 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1090 * For a value of zero or negative one, -1 will be returned.
1092 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1093 * findMSB(-(1<<x)) should return x-1.
1095 * For all negative number cases, including 0x80000000 and
1096 * 0xffffffff, the correct value is obtained from LZD if instead of
1097 * negating the (already negative) value the logical-not is used. A
1098 * conditonal logical-not can be achieved in two instructions.
1100 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1102 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1103 bld
.XOR(dst_reg(temp
), temp
, src
);
1106 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1107 retype(temp
, BRW_REGISTER_TYPE_UD
));
1109 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1110 * from the LSB side. Subtract the result from 31 to convert the MSB count
1111 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1112 * which is exactly what findMSB() is supposed to return.
1114 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1116 inst
->src
[0].negate
= true;
1120 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1123 /* BDW PRM vol 15 - workarounds:
1124 * DF->f format conversion for Align16 has wrong emask calculation when
1125 * source is immediate.
1127 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1128 src
.file
== BRW_IMMEDIATE_VALUE
) {
1129 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1130 inst
->saturate
= saturate
;
1136 case BRW_REGISTER_TYPE_D
:
1137 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1139 case BRW_REGISTER_TYPE_UD
:
1140 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1142 case BRW_REGISTER_TYPE_F
:
1143 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1146 unreachable("Unknown conversion");
1149 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1150 emit(MOV(temp
, src
));
1151 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1152 emit(op
, temp2
, src_reg(temp
));
1154 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1155 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1156 inst
->saturate
= saturate
;
1160 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1163 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1164 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1165 emit(MOV(dst_reg(tmp_src
), src
));
1166 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1167 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1168 inst
->saturate
= saturate
;
1172 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1174 vec4_instruction
*inst
;
1176 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1177 nir_dest_bit_size(instr
->dest
.dest
));
1178 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1179 dst
.writemask
= instr
->dest
.write_mask
;
1182 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1183 nir_alu_type src_type
= (nir_alu_type
)
1184 (nir_op_infos
[instr
->op
].input_types
[i
] |
1185 nir_src_bit_size(instr
->src
[i
].src
));
1186 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1187 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1188 op
[i
].abs
= instr
->src
[i
].abs
;
1189 op
[i
].negate
= instr
->src
[i
].negate
;
1192 switch (instr
->op
) {
1195 inst
= emit(MOV(dst
, op
[0]));
1196 inst
->saturate
= instr
->dest
.saturate
;
1202 unreachable("not reached: should be handled by lower_vec_to_movs()");
1206 inst
= emit(MOV(dst
, op
[0]));
1207 inst
->saturate
= instr
->dest
.saturate
;
1213 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1214 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1216 inst
= emit(MOV(dst
, op
[0]));
1222 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1226 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1229 inst
= emit(ADD(dst
, op
[0], op
[1]));
1230 inst
->saturate
= instr
->dest
.saturate
;
1234 inst
= emit(MUL(dst
, op
[0], op
[1]));
1235 inst
->saturate
= instr
->dest
.saturate
;
1239 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1240 if (devinfo
->gen
< 8) {
1241 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1242 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1244 /* For integer multiplication, the MUL uses the low 16 bits of one of
1245 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1246 * accumulates in the contribution of the upper 16 bits of that
1247 * operand. If we can determine that one of the args is in the low
1248 * 16 bits, though, we can just emit a single MUL.
1250 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1251 if (devinfo
->gen
< 7)
1252 emit(MUL(dst
, op
[0], op
[1]));
1254 emit(MUL(dst
, op
[1], op
[0]));
1255 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1256 if (devinfo
->gen
< 7)
1257 emit(MUL(dst
, op
[1], op
[0]));
1259 emit(MUL(dst
, op
[0], op
[1]));
1261 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1263 emit(MUL(acc
, op
[0], op
[1]));
1264 emit(MACH(dst_null_d(), op
[0], op
[1]));
1265 emit(MOV(dst
, src_reg(acc
)));
1268 emit(MUL(dst
, op
[0], op
[1]));
1273 case nir_op_imul_high
:
1274 case nir_op_umul_high
: {
1275 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1276 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1278 if (devinfo
->gen
>= 8)
1279 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1281 emit(MUL(acc
, op
[0], op
[1]));
1283 emit(MACH(dst
, op
[0], op
[1]));
1288 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1289 inst
->saturate
= instr
->dest
.saturate
;
1293 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1294 inst
->saturate
= instr
->dest
.saturate
;
1298 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1299 inst
->saturate
= instr
->dest
.saturate
;
1303 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1304 inst
->saturate
= instr
->dest
.saturate
;
1308 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1309 inst
->saturate
= instr
->dest
.saturate
;
1314 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1315 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1320 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1321 * appears that our hardware just does the right thing for signed
1324 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1325 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1329 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1330 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1332 /* Math instructions don't support conditional mod */
1333 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1334 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1336 /* Now, we need to determine if signs of the sources are different.
1337 * When we XOR the sources, the top bit is 0 if they are the same and 1
1338 * if they are different. We can then use a conditional modifier to
1339 * turn that into a predicate. This leads us to an XOR.l instruction.
1341 * Technically, according to the PRM, you're not allowed to use .l on a
1342 * XOR instruction. However, emperical experiments and Curro's reading
1343 * of the simulator source both indicate that it's safe.
1345 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1346 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1347 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1348 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1350 /* If the result of the initial remainder operation is non-zero and the
1351 * two sources have different signs, add in a copy of op[1] to get the
1352 * final integer modulus value.
1354 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1355 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1360 unreachable("not reached: should be handled by ldexp_to_arith()");
1363 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1364 inst
->saturate
= instr
->dest
.saturate
;
1368 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1369 inst
->saturate
= instr
->dest
.saturate
;
1373 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1374 inst
->saturate
= instr
->dest
.saturate
;
1377 case nir_op_uadd_carry
: {
1378 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1379 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1381 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1382 emit(MOV(dst
, src_reg(acc
)));
1386 case nir_op_usub_borrow
: {
1387 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1388 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1390 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1391 emit(MOV(dst
, src_reg(acc
)));
1396 inst
= emit(RNDZ(dst
, op
[0]));
1397 inst
->saturate
= instr
->dest
.saturate
;
1400 case nir_op_fceil
: {
1401 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1403 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1404 instr
->src
[0].src
.ssa
->num_components
:
1405 instr
->src
[0].src
.reg
.reg
->num_components
);
1407 op
[0].negate
= !op
[0].negate
;
1408 emit(RNDD(dst_reg(tmp
), op
[0]));
1410 inst
= emit(MOV(dst
, tmp
));
1411 inst
->saturate
= instr
->dest
.saturate
;
1416 inst
= emit(RNDD(dst
, op
[0]));
1417 inst
->saturate
= instr
->dest
.saturate
;
1421 inst
= emit(FRC(dst
, op
[0]));
1422 inst
->saturate
= instr
->dest
.saturate
;
1425 case nir_op_fround_even
:
1426 inst
= emit(RNDE(dst
, op
[0]));
1427 inst
->saturate
= instr
->dest
.saturate
;
1430 case nir_op_fquantize2f16
: {
1431 /* See also vec4_visitor::emit_pack_half_2x16() */
1432 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1433 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1434 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1436 /* Check for denormal */
1437 src_reg abs_src0
= op
[0];
1438 abs_src0
.abs
= true;
1439 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1440 BRW_CONDITIONAL_L
));
1441 /* Get the appropriately signed zero */
1442 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1443 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1444 brw_imm_ud(0x80000000)));
1445 /* Do the actual F32 -> F16 -> F32 conversion */
1446 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1447 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1448 /* Select that or zero based on normal status */
1449 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1450 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1451 inst
->saturate
= instr
->dest
.saturate
;
1457 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1460 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1461 inst
->saturate
= instr
->dest
.saturate
;
1466 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1469 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1470 inst
->saturate
= instr
->dest
.saturate
;
1474 case nir_op_fddx_coarse
:
1475 case nir_op_fddx_fine
:
1477 case nir_op_fddy_coarse
:
1478 case nir_op_fddy_fine
:
1479 unreachable("derivatives are not valid in vertex shaders");
1487 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1493 enum brw_conditional_mod conditional_mod
=
1494 brw_conditional_for_nir_comparison(instr
->op
);
1496 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1497 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1499 /* Produce a 32-bit boolean result from the DF comparison by selecting
1500 * only the low 32-bit in each DF produced. Do this in a temporary
1501 * so we can then move from there to the result using align16 again
1502 * to honor the original writemask.
1504 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1505 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1506 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1507 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1508 emit(MOV(dst
, src_reg(result
)));
1513 case nir_op_ball_iequal2
:
1514 case nir_op_ball_iequal3
:
1515 case nir_op_ball_iequal4
:
1516 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1518 case nir_op_ball_fequal2
:
1519 case nir_op_ball_fequal3
:
1520 case nir_op_ball_fequal4
: {
1522 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1524 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1525 brw_conditional_for_nir_comparison(instr
->op
)));
1526 emit(MOV(dst
, brw_imm_d(0)));
1527 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1528 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1532 case nir_op_bany_inequal2
:
1533 case nir_op_bany_inequal3
:
1534 case nir_op_bany_inequal4
:
1535 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1537 case nir_op_bany_fnequal2
:
1538 case nir_op_bany_fnequal3
:
1539 case nir_op_bany_fnequal4
: {
1541 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1543 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1544 brw_conditional_for_nir_comparison(instr
->op
)));
1546 emit(MOV(dst
, brw_imm_d(0)));
1547 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1548 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1553 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1554 if (devinfo
->gen
>= 8) {
1555 op
[0] = resolve_source_modifiers(op
[0]);
1557 emit(NOT(dst
, op
[0]));
1561 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1562 if (devinfo
->gen
>= 8) {
1563 op
[0] = resolve_source_modifiers(op
[0]);
1564 op
[1] = resolve_source_modifiers(op
[1]);
1566 emit(XOR(dst
, op
[0], op
[1]));
1570 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1571 if (devinfo
->gen
>= 8) {
1572 op
[0] = resolve_source_modifiers(op
[0]);
1573 op
[1] = resolve_source_modifiers(op
[1]);
1575 emit(OR(dst
, op
[0], op
[1]));
1579 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1580 if (devinfo
->gen
>= 8) {
1581 op
[0] = resolve_source_modifiers(op
[0]);
1582 op
[1] = resolve_source_modifiers(op
[1]);
1584 emit(AND(dst
, op
[0], op
[1]));
1589 if (nir_dest_bit_size(instr
->dest
.dest
) > 32) {
1590 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
1591 emit_conversion_to_double(dst
, negate(op
[0]), false);
1593 emit(MOV(dst
, negate(op
[0])));
1598 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1599 /* We use a MOV with conditional_mod to check if the provided value is
1600 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1601 * source modifier on the source operand to trigger this, as source
1602 * modifiers don't affect the result of the testing against 0.0.
1604 src_reg value
= op
[0];
1606 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1607 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1609 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1610 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1611 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1612 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1614 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1619 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1622 case nir_op_fnoise1_1
:
1623 case nir_op_fnoise1_2
:
1624 case nir_op_fnoise1_3
:
1625 case nir_op_fnoise1_4
:
1626 case nir_op_fnoise2_1
:
1627 case nir_op_fnoise2_2
:
1628 case nir_op_fnoise2_3
:
1629 case nir_op_fnoise2_4
:
1630 case nir_op_fnoise3_1
:
1631 case nir_op_fnoise3_2
:
1632 case nir_op_fnoise3_3
:
1633 case nir_op_fnoise3_4
:
1634 case nir_op_fnoise4_1
:
1635 case nir_op_fnoise4_2
:
1636 case nir_op_fnoise4_3
:
1637 case nir_op_fnoise4_4
:
1638 unreachable("not reached: should be handled by lower_noise");
1640 case nir_op_unpack_half_2x16_split_x
:
1641 case nir_op_unpack_half_2x16_split_y
:
1642 case nir_op_pack_half_2x16_split
:
1643 unreachable("not reached: should not occur in vertex shader");
1645 case nir_op_unpack_snorm_2x16
:
1646 case nir_op_unpack_unorm_2x16
:
1647 case nir_op_pack_snorm_2x16
:
1648 case nir_op_pack_unorm_2x16
:
1649 unreachable("not reached: should be handled by lower_packing_builtins");
1651 case nir_op_pack_uvec4_to_uint
:
1652 unreachable("not reached");
1654 case nir_op_pack_uvec2_to_uint
: {
1655 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1656 tmp1
.writemask
= WRITEMASK_X
;
1657 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1658 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1660 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1661 tmp2
.writemask
= WRITEMASK_X
;
1662 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1663 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1665 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1669 case nir_op_pack_64_2x32_split
: {
1670 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1671 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1672 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1673 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1674 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1675 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1676 emit(MOV(dst
, src_reg(result
)));
1680 case nir_op_unpack_64_2x32_split_x
:
1681 case nir_op_unpack_64_2x32_split_y
: {
1682 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1683 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1684 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1685 emit(MOV(tmp
, op
[0]));
1686 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1687 emit(oper
, tmp2
, src_reg(tmp
));
1688 emit(MOV(dst
, src_reg(tmp2
)));
1692 case nir_op_unpack_half_2x16
:
1693 /* As NIR does not guarantee that we have a correct swizzle outside the
1694 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1695 * uses the source operand in an operation with WRITEMASK_Y while our
1696 * source operand has only size 1, it accessed incorrect data producing
1697 * regressions in Piglit. We repeat the swizzle of the first component on the
1698 * rest of components to avoid regressions. In the vec4_visitor IR code path
1699 * this is not needed because the operand has already the correct swizzle.
1701 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1702 emit_unpack_half_2x16(dst
, op
[0]);
1705 case nir_op_pack_half_2x16
:
1706 emit_pack_half_2x16(dst
, op
[0]);
1709 case nir_op_unpack_unorm_4x8
:
1710 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1711 emit_unpack_unorm_4x8(dst
, op
[0]);
1714 case nir_op_pack_unorm_4x8
:
1715 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1716 emit_pack_unorm_4x8(dst
, op
[0]);
1719 case nir_op_unpack_snorm_4x8
:
1720 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1721 emit_unpack_snorm_4x8(dst
, op
[0]);
1724 case nir_op_pack_snorm_4x8
:
1725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1726 emit_pack_snorm_4x8(dst
, op
[0]);
1729 case nir_op_bitfield_reverse
:
1730 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1731 emit(BFREV(dst
, op
[0]));
1734 case nir_op_bit_count
:
1735 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1736 emit(CBIT(dst
, op
[0]));
1739 case nir_op_ufind_msb
:
1740 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1741 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1744 case nir_op_ifind_msb
: {
1745 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1746 vec4_builder bld
= vec4_builder(this).at_end();
1749 if (devinfo
->gen
< 7) {
1750 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1752 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1754 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1755 * count from the LSB side. If FBH didn't return an error
1756 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1757 * count into an LSB count.
1759 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1761 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1762 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1763 inst
->src
[0].negate
= true;
1768 case nir_op_find_lsb
: {
1769 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1770 vec4_builder bld
= vec4_builder(this).at_end();
1772 if (devinfo
->gen
< 7) {
1773 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1775 /* (x & -x) generates a value that consists of only the LSB of x.
1776 * For all powers of 2, findMSB(y) == findLSB(y).
1778 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1779 src_reg negated_src
= src
;
1781 /* One must be negated, and the other must be non-negated. It
1782 * doesn't matter which is which.
1784 negated_src
.negate
= true;
1787 bld
.AND(temp
, src
, negated_src
);
1788 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1790 bld
.FBL(dst
, op
[0]);
1795 case nir_op_ubitfield_extract
:
1796 case nir_op_ibitfield_extract
:
1797 unreachable("should have been lowered");
1800 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1801 op
[0] = fix_3src_operand(op
[0]);
1802 op
[1] = fix_3src_operand(op
[1]);
1803 op
[2] = fix_3src_operand(op
[2]);
1805 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1809 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1810 emit(BFI1(dst
, op
[0], op
[1]));
1814 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1815 op
[0] = fix_3src_operand(op
[0]);
1816 op
[1] = fix_3src_operand(op
[1]);
1817 op
[2] = fix_3src_operand(op
[2]);
1819 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1822 case nir_op_bitfield_insert
:
1823 unreachable("not reached: should have been lowered");
1826 assert(!instr
->dest
.saturate
);
1828 /* Straightforward since the source can be assumed to be either
1829 * strictly >= 0 or strictly <= 0 depending on the setting of the
1832 inst
= emit(MOV(dst
, op
[0]));
1833 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1835 inst
= (op
[0].negate
)
1836 ? emit(MOV(dst
, brw_imm_f(-1.0f
)))
1837 : emit(MOV(dst
, brw_imm_f(1.0f
)));
1838 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1839 } else if (type_sz(op
[0].type
) < 8) {
1840 /* AND(val, 0x80000000) gives the sign bit.
1842 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1845 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1847 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1848 dst
.type
= BRW_REGISTER_TYPE_UD
;
1849 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1851 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1852 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1853 dst
.type
= BRW_REGISTER_TYPE_F
;
1855 /* For doubles we do the same but we need to consider:
1857 * - We use a MOV with conditional_mod instead of a CMP so that we can
1858 * skip loading a 0.0 immediate. We use a source modifier on the
1859 * source of the MOV so that we flush denormalized values to 0.
1860 * Since we want to compare against 0, this won't alter the result.
1861 * - We need to extract the high 32-bit of each DF where the sign
1863 * - We need to produce a DF result.
1866 /* Check for zero */
1867 src_reg value
= op
[0];
1869 inst
= emit(MOV(dst_null_df(), value
));
1870 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1872 /* AND each high 32-bit channel with 0x80000000u */
1873 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1874 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1875 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1877 /* Add 1.0 to each channel, predicated to skip the cases where the
1878 * channel's value was 0
1880 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1881 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1883 /* Now convert the result from float to double */
1884 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1885 BRW_REGISTER_TYPE_F
),
1891 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1892 * -> non-negative val generates 0x00000000.
1893 * Predicated OR sets 1 if val is positive.
1895 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1896 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1897 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1898 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1899 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1903 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1904 emit(SHL(dst
, op
[0], op
[1]));
1908 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1909 emit(ASR(dst
, op
[0], op
[1]));
1913 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1914 emit(SHR(dst
, op
[0], op
[1]));
1918 if (type_sz(dst
.type
) == 8) {
1919 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1920 emit(MUL(mul_dst
, op
[1], op
[0]));
1921 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1922 inst
->saturate
= instr
->dest
.saturate
;
1924 op
[0] = fix_3src_operand(op
[0]);
1925 op
[1] = fix_3src_operand(op
[1]);
1926 op
[2] = fix_3src_operand(op
[2]);
1928 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1929 inst
->saturate
= instr
->dest
.saturate
;
1934 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1935 inst
->saturate
= instr
->dest
.saturate
;
1939 enum brw_predicate predicate
;
1940 if (!optimize_predicate(instr
, &predicate
)) {
1941 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1942 switch (dst
.writemask
) {
1944 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1947 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1950 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1953 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1956 predicate
= BRW_PREDICATE_NORMAL
;
1960 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1961 inst
->predicate
= predicate
;
1964 case nir_op_fdot_replicated2
:
1965 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1966 inst
->saturate
= instr
->dest
.saturate
;
1969 case nir_op_fdot_replicated3
:
1970 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1971 inst
->saturate
= instr
->dest
.saturate
;
1974 case nir_op_fdot_replicated4
:
1975 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1976 inst
->saturate
= instr
->dest
.saturate
;
1979 case nir_op_fdph_replicated
:
1980 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1981 inst
->saturate
= instr
->dest
.saturate
;
1986 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1991 unreachable("not reached: should be lowered by lower_source mods");
1994 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1997 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
2001 unreachable("not reached: should be handled by ir_sub_to_add_neg");
2004 unreachable("Unimplemented ALU operation");
2007 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2008 * to sign extend the low bit to 0/~0
2010 if (devinfo
->gen
<= 5 &&
2011 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2012 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2013 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2014 masked
.writemask
= dst
.writemask
;
2015 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2016 src_reg masked_neg
= src_reg(masked
);
2017 masked_neg
.negate
= true;
2018 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2023 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2025 switch (instr
->type
) {
2026 case nir_jump_break
:
2027 emit(BRW_OPCODE_BREAK
);
2030 case nir_jump_continue
:
2031 emit(BRW_OPCODE_CONTINUE
);
2034 case nir_jump_return
:
2037 unreachable("unknown jump");
2041 static enum ir_texture_opcode
2042 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2044 enum ir_texture_opcode op
;
2047 case nir_texop_lod
: op
= ir_lod
; break;
2048 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2049 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2050 case nir_texop_tex
: op
= ir_tex
; break;
2051 case nir_texop_tg4
: op
= ir_tg4
; break;
2052 case nir_texop_txb
: op
= ir_txb
; break;
2053 case nir_texop_txd
: op
= ir_txd
; break;
2054 case nir_texop_txf
: op
= ir_txf
; break;
2055 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2056 case nir_texop_txl
: op
= ir_txl
; break;
2057 case nir_texop_txs
: op
= ir_txs
; break;
2058 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2060 unreachable("unknown texture opcode");
2066 static const glsl_type
*
2067 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2068 unsigned components
)
2070 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2075 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2077 unsigned texture
= instr
->texture_index
;
2078 unsigned sampler
= instr
->sampler_index
;
2079 src_reg texture_reg
= brw_imm_ud(texture
);
2080 src_reg sampler_reg
= brw_imm_ud(sampler
);
2082 const glsl_type
*coord_type
= NULL
;
2083 src_reg shadow_comparator
;
2084 src_reg offset_value
;
2086 src_reg sample_index
;
2089 const glsl_type
*dest_type
=
2090 glsl_type_for_nir_alu_type(instr
->dest_type
,
2091 nir_tex_instr_dest_size(instr
));
2092 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2094 /* The hardware requires a LOD for buffer textures */
2095 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2098 /* Load the texture operation sources */
2099 uint32_t constant_offset
= 0;
2100 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2101 switch (instr
->src
[i
].src_type
) {
2102 case nir_tex_src_comparator
:
2103 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2104 BRW_REGISTER_TYPE_F
, 1);
2107 case nir_tex_src_coord
: {
2108 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2110 switch (instr
->op
) {
2112 case nir_texop_txf_ms
:
2113 case nir_texop_samples_identical
:
2114 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2116 coord_type
= glsl_type::ivec(src_size
);
2120 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2122 coord_type
= glsl_type::vec(src_size
);
2128 case nir_tex_src_ddx
:
2129 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2130 nir_tex_instr_src_size(instr
, i
));
2133 case nir_tex_src_ddy
:
2134 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2135 nir_tex_instr_src_size(instr
, i
));
2138 case nir_tex_src_lod
:
2139 switch (instr
->op
) {
2142 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2146 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2151 case nir_tex_src_ms_index
: {
2152 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2156 case nir_tex_src_offset
: {
2157 nir_const_value
*const_offset
=
2158 nir_src_as_const_value(instr
->src
[i
].src
);
2159 if (!const_offset
||
2160 !brw_texture_offset(const_offset
->i32
,
2161 nir_tex_instr_src_size(instr
, i
),
2162 &constant_offset
)) {
2164 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2169 case nir_tex_src_texture_offset
: {
2170 /* The highest texture which may be used by this operation is
2171 * the last element of the array. Mark it here, because the generator
2172 * doesn't have enough information to determine the bound.
2174 uint32_t array_size
= instr
->texture_array_size
;
2175 uint32_t max_used
= texture
+ array_size
- 1;
2176 if (instr
->op
== nir_texop_tg4
) {
2177 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2179 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2182 brw_mark_surface_used(&prog_data
->base
, max_used
);
2184 /* Emit code to evaluate the actual indexing expression */
2185 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2186 src_reg
temp(this, glsl_type::uint_type
);
2187 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2188 texture_reg
= emit_uniformize(temp
);
2192 case nir_tex_src_sampler_offset
: {
2193 /* Emit code to evaluate the actual indexing expression */
2194 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2195 src_reg
temp(this, glsl_type::uint_type
);
2196 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2197 sampler_reg
= emit_uniformize(temp
);
2201 case nir_tex_src_projector
:
2202 unreachable("Should be lowered by do_lower_texture_projection");
2204 case nir_tex_src_bias
:
2205 unreachable("LOD bias is not valid for vertex shaders.\n");
2208 unreachable("unknown texture source");
2212 if (instr
->op
== nir_texop_txf_ms
||
2213 instr
->op
== nir_texop_samples_identical
) {
2214 assert(coord_type
!= NULL
);
2215 if (devinfo
->gen
>= 7 &&
2216 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2217 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2219 mcs
= brw_imm_ud(0u);
2223 /* Stuff the channel select bits in the top of the texture offset */
2224 if (instr
->op
== nir_texop_tg4
) {
2225 if (instr
->component
== 1 &&
2226 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2227 /* gather4 sampler is broken for green channel on RG32F --
2228 * we must ask for blue instead.
2230 constant_offset
|= 2 << 16;
2232 constant_offset
|= instr
->component
<< 16;
2236 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2238 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2240 lod
, lod2
, sample_index
,
2241 constant_offset
, offset_value
, mcs
,
2242 texture
, texture_reg
, sampler_reg
);
2246 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2248 nir_ssa_values
[instr
->def
.index
] =
2249 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2252 /* SIMD4x2 64bit data is stored in register space like this:
2254 * r0.0:DF x0 y0 z0 w0
2255 * r1.0:DF x1 y1 z1 w1
2257 * When we need to write data such as this to memory using 32-bit write
2258 * messages we need to shuffle it in this fashion:
2260 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2261 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2263 * We need to do the inverse operation when we read using 32-bit messages,
2264 * which we can do by applying the same exact shuffling on the 64-bit data
2265 * read, only that because the data for each vertex is positioned differently
2266 * we need to apply different channel enables.
2268 * This function takes 64bit data and shuffles it as explained above.
2270 * The @for_write parameter is used to specify if the shuffling is being done
2271 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2272 * write message (for_write = true), or instead we are doing the inverse
2273 * operation and we have just read 64-bit data using a 32-bit messages that we
2274 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2276 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2277 * otherwise the instructions are emitted normally at the end. The function
2278 * returns the last instruction inserted.
2280 * Notice that @src and @dst cannot be the same register.
2283 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2284 bblock_t
*block
, vec4_instruction
*ref
)
2286 assert(type_sz(src
.type
) == 8);
2287 assert(type_sz(dst
.type
) == 8);
2288 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2289 assert(!ref
== !block
);
2291 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2292 vec4_builder(this).at(block
, ref
->next
);
2294 /* Resolve swizzle in src */
2295 vec4_instruction
*inst
;
2296 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2297 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2298 inst
= bld
.MOV(data
, src
);
2299 src
= src_reg(data
);
2302 /* dst+0.XY = src+0.XY */
2303 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2305 /* dst+0.ZW = src+1.XY */
2306 inst
= bld
.group(4, for_write
? 1 : 0)
2307 .MOV(writemask(dst
, WRITEMASK_ZW
),
2308 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2310 /* dst+1.XY = src+0.ZW */
2311 inst
= bld
.group(4, for_write
? 0 : 1)
2312 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2313 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2315 /* dst+1.ZW = src+1.ZW */
2316 inst
= bld
.group(4, 1)
2317 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2318 byte_offset(src
, REG_SIZE
));