2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
44 vec4_visitor::nir_setup_uniforms()
46 uniforms
= nir
->num_uniforms
/ 16;
50 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
52 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
53 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
54 nir_locals
[i
] = dst_reg();
57 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
58 unsigned array_elems
=
59 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
60 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
61 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
63 if (reg
->bit_size
== 64)
64 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
67 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
69 nir_emit_cf_list(&impl
->body
);
73 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
75 exec_list_validate(list
);
76 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
79 nir_emit_if(nir_cf_node_as_if(node
));
82 case nir_cf_node_loop
:
83 nir_emit_loop(nir_cf_node_as_loop(node
));
86 case nir_cf_node_block
:
87 nir_emit_block(nir_cf_node_as_block(node
));
91 unreachable("Invalid CFG node block");
97 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
99 /* First, put the condition in f0 */
100 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
101 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
102 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
104 /* We can just predicate based on the X channel, as the condition only
105 * goes on its own line */
106 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
108 nir_emit_cf_list(&if_stmt
->then_list
);
110 /* note: if the else is empty, dead CF elimination will remove it */
111 emit(BRW_OPCODE_ELSE
);
113 nir_emit_cf_list(&if_stmt
->else_list
);
115 emit(BRW_OPCODE_ENDIF
);
119 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
123 nir_emit_cf_list(&loop
->body
);
125 emit(BRW_OPCODE_WHILE
);
129 vec4_visitor::nir_emit_block(nir_block
*block
)
131 nir_foreach_instr(instr
, block
) {
132 nir_emit_instr(instr
);
137 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
141 switch (instr
->type
) {
142 case nir_instr_type_load_const
:
143 nir_emit_load_const(nir_instr_as_load_const(instr
));
146 case nir_instr_type_intrinsic
:
147 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
150 case nir_instr_type_alu
:
151 nir_emit_alu(nir_instr_as_alu(instr
));
154 case nir_instr_type_jump
:
155 nir_emit_jump(nir_instr_as_jump(instr
));
158 case nir_instr_type_tex
:
159 nir_emit_texture(nir_instr_as_tex(instr
));
162 case nir_instr_type_ssa_undef
:
163 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
167 unreachable("VS instruction not yet implemented by NIR->vec4");
172 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
173 unsigned base_offset
, nir_src
*indirect
)
177 reg
= v
->nir_locals
[nir_reg
->index
];
178 if (nir_reg
->bit_size
== 64)
179 reg
.type
= BRW_REGISTER_TYPE_DF
;
180 reg
= offset(reg
, 8, base_offset
);
183 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
191 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
195 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
196 if (dest
.ssa
.bit_size
== 64)
197 dst
.type
= BRW_REGISTER_TYPE_DF
;
198 nir_ssa_values
[dest
.ssa
.index
] = dst
;
201 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
207 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
209 return retype(get_nir_dest(dest
), type
);
213 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
215 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
219 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
220 unsigned num_components
)
225 assert(src
.ssa
!= NULL
);
226 reg
= nir_ssa_values
[src
.ssa
->index
];
229 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
233 reg
= retype(reg
, type
);
235 src_reg reg_as_src
= src_reg(reg
);
236 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
241 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
242 unsigned num_components
)
244 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
249 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
251 /* if type is not specified, default to signed int */
252 return get_nir_src(src
, nir_type_int32
, num_components
);
256 vec4_visitor::get_nir_src_imm(const nir_src
&src
)
258 assert(nir_src_num_components(src
) == 1);
259 assert(nir_src_bit_size(src
) == 32);
260 nir_const_value
*const_val
= nir_src_as_const_value(src
);
261 return const_val
? src_reg(brw_imm_d(const_val
->i32
[0])) :
266 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
268 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
269 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
272 /* The only constant offset we should find is 0. brw_nir.c's
273 * add_const_offset_to_base() will fold other constant offsets
274 * into instr->const_index[0].
276 assert(const_value
->u32
[0] == 0);
280 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
284 setup_imm_df(const vec4_builder
&bld
, double v
)
286 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
287 assert(devinfo
->gen
>= 7);
289 if (devinfo
->gen
>= 8)
290 return brw_imm_df(v
);
292 /* gen7.5 does not support DF immediates straighforward but the DIM
293 * instruction allows to set the 64-bit immediate value.
295 if (devinfo
->is_haswell
) {
296 const vec4_builder ubld
= bld
.exec_all();
297 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
298 ubld
.DIM(dst
, brw_imm_df(v
));
299 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
302 /* gen7 does not support DF immediates */
313 /* Write the low 32-bit of the constant to the X:UD channel and the
314 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
315 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
316 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
317 * XXXX so any access to the VGRF only reads the constant data in these
320 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
321 for (unsigned n
= 0; n
< 2; n
++) {
322 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
323 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
324 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
327 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
331 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
335 if (instr
->def
.bit_size
== 64) {
336 reg
= dst_reg(VGRF
, alloc
.allocate(2));
337 reg
.type
= BRW_REGISTER_TYPE_DF
;
339 reg
= dst_reg(VGRF
, alloc
.allocate(1));
340 reg
.type
= BRW_REGISTER_TYPE_D
;
343 const vec4_builder ibld
= vec4_builder(this).at_end();
344 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
346 /* @FIXME: consider emitting vector operations to save some MOVs in
347 * cases where the components are representable in 8 bits.
348 * For now, we emit a MOV for each distinct value.
350 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
351 unsigned writemask
= 1 << i
;
353 if ((remaining
& writemask
) == 0)
356 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
357 if ((instr
->def
.bit_size
== 32 &&
358 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
359 (instr
->def
.bit_size
== 64 &&
360 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
365 reg
.writemask
= writemask
;
366 if (instr
->def
.bit_size
== 64) {
367 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
369 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
372 remaining
&= ~writemask
;
375 /* Set final writemask */
376 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
378 nir_ssa_values
[instr
->def
.index
] = reg
;
382 vec4_visitor::get_nir_ssbo_intrinsic_index(nir_intrinsic_instr
*instr
)
384 /* SSBO stores are weird in that their index is in src[1] */
385 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
388 nir_const_value
*const_uniform_block
=
389 nir_src_as_const_value(instr
->src
[src
]);
390 if (const_uniform_block
) {
391 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
392 const_uniform_block
->u32
[0];
393 surf_index
= brw_imm_ud(index
);
394 brw_mark_surface_used(&prog_data
->base
, index
);
396 surf_index
= src_reg(this, glsl_type::uint_type
);
397 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[src
], 1),
398 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
399 surf_index
= emit_uniformize(surf_index
);
401 brw_mark_surface_used(&prog_data
->base
,
402 prog_data
->base
.binding_table
.ssbo_start
+
403 nir
->info
.num_ssbos
- 1);
410 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
415 switch (instr
->intrinsic
) {
417 case nir_intrinsic_load_input
: {
418 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
420 /* We set EmitNoIndirectInput for VS */
421 assert(const_offset
);
423 dest
= get_nir_dest(instr
->dest
);
424 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
426 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
427 glsl_type::uvec4_type
);
428 src
= retype(src
, dest
.type
);
430 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
432 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
433 src
.swizzle
= BRW_SWIZZLE_XYZW
;
434 shuffle_64bit_data(tmp
, src
, false);
435 emit(MOV(dest
, src_reg(tmp
)));
437 /* Swizzle source based on component layout qualifier */
438 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
439 emit(MOV(dest
, src
));
444 case nir_intrinsic_store_output
: {
445 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
446 assert(const_offset
);
448 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
450 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
453 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
454 instr
->num_components
);
455 data
= src_reg(this, glsl_type::dvec4_type
);
456 shuffle_64bit_data(dst_reg(data
), src
, true);
457 src
= retype(data
, BRW_REGISTER_TYPE_F
);
459 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
460 instr
->num_components
);
463 unsigned c
= nir_intrinsic_component(instr
);
464 output_reg
[varying
][c
] = dst_reg(src
);
465 output_num_components
[varying
][c
] = instr
->num_components
;
467 unsigned num_components
= instr
->num_components
;
471 output_reg
[varying
][c
] = dst_reg(src
);
472 output_num_components
[varying
][c
] = MIN2(4, num_components
);
474 if (is_64bit
&& num_components
> 4) {
475 assert(num_components
<= 8);
476 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
477 output_num_components
[varying
+ 1][c
] = num_components
- 4;
482 case nir_intrinsic_get_buffer_size
: {
483 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
484 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
486 const unsigned index
=
487 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
488 dst_reg result_dst
= get_nir_dest(instr
->dest
);
489 vec4_instruction
*inst
= new(mem_ctx
)
490 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE
, result_dst
);
493 inst
->mlen
= 1; /* always at least one */
494 inst
->src
[1] = brw_imm_ud(index
);
496 /* MRF for the first parameter */
497 src_reg lod
= brw_imm_d(0);
498 int param_base
= inst
->base_mrf
;
499 int writemask
= WRITEMASK_X
;
500 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
504 brw_mark_surface_used(&prog_data
->base
, index
);
508 case nir_intrinsic_store_ssbo
: {
509 assert(devinfo
->gen
>= 7);
511 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
512 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[2]),
513 BRW_REGISTER_TYPE_UD
);
516 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
519 unsigned write_mask
= instr
->const_index
[0];
521 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
522 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
523 * typed and untyped messages and across hardware platforms, the
524 * current implementation of the untyped messages will transparently convert
525 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
526 * and enabling only channel X on the SEND instruction.
528 * The above, works well for full vector writes, but not for partial writes
529 * where we want to write some channels and not others, like when we have
530 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
531 * quite restrictive with regards to the channel enables we can configure in
532 * the message descriptor (not all combinations are allowed) we cannot simply
533 * implement these scenarios with a single message while keeping the
534 * aforementioned symmetry in the implementation. For now we de decided that
535 * it is better to keep the symmetry to reduce complexity, so in situations
536 * such as the one described we end up emitting two untyped write messages
537 * (one for xy and another for w).
539 * The code below packs consecutive channels into a single write message,
540 * detects gaps in the vector write and if needed, sends a second message
541 * with the remaining channels. If in the future we decide that we want to
542 * emit a single message at the expense of losing the symmetry in the
543 * implementation we can:
545 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
546 * message payload. In this mode we can write up to 8 offsets and dwords
547 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
548 * and select which of the 8 channels carry data to write by setting the
549 * appropriate writemask in the dst register of the SEND instruction.
550 * It would require to write a new generator opcode specifically for
551 * IvyBridge since we would need to prepare a SIMD8 payload that could
552 * use any channel, not just X.
554 * 2) For Haswell+: Simply send a single write message but set the writemask
555 * on the dst of the SEND instruction to select the channels we want to
556 * write. It would require to modify the current messages to receive
557 * and honor the writemask provided.
559 const vec4_builder bld
= vec4_builder(this).at_end()
560 .annotate(current_annotation
, base_ir
);
562 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
563 if (type_slots
== 2) {
564 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
565 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
566 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
569 uint8_t swizzle
[4] = { 0, 0, 0, 0};
570 int num_channels
= 0;
571 unsigned skipped_channels
= 0;
572 int num_components
= instr
->num_components
;
573 for (int i
= 0; i
< num_components
; i
++) {
574 /* Read components Z/W of a dvec from the appropriate place. We will
575 * also have to adjust the swizzle (we do that with the '% 4' below)
577 if (i
== 2 && type_slots
== 2)
578 val_reg
= byte_offset(val_reg
, REG_SIZE
);
580 /* Check if this channel needs to be written. If so, record the
581 * channel we need to take the data from in the swizzle array
583 int component_mask
= 1 << i
;
584 int write_test
= write_mask
& component_mask
;
586 /* If we are writing doubles we have to write 2 channels worth of
587 * of data (64 bits) for each double component.
589 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
591 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
594 /* If we don't have to write this channel it means we have a gap in the
595 * vector, so write the channels we accumulated until now, if any. Do
596 * the same if this was the last component in the vector, if we have
597 * enough channels for a full vec4 write or if we have processed
598 * components XY of a dvec (since components ZW are not in the same
601 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
602 (i
== 1 && type_slots
== 2)) {
603 if (num_channels
> 0) {
604 /* We have channels to write, so update the offset we need to
605 * write at to skip the channels we skipped, if any.
607 if (skipped_channels
> 0) {
608 if (offset_reg
.file
== IMM
) {
609 offset_reg
.ud
+= 4 * skipped_channels
;
611 emit(ADD(dst_reg(offset_reg
), offset_reg
,
612 brw_imm_ud(4 * skipped_channels
)));
616 /* Swizzle the data register so we take the data from the channels
617 * we need to write and send the write message. This will write
618 * num_channels consecutive dwords starting at offset.
621 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
622 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
623 1 /* dims */, num_channels
/* size */,
626 /* If we have to do a second write we will have to update the
627 * offset so that we jump over the channels we have just written
630 skipped_channels
= num_channels
;
632 /* Restart the count for the next write message */
636 /* If we didn't write the channel, increase skipped count */
638 skipped_channels
+= type_slots
;
645 case nir_intrinsic_load_ssbo
: {
646 assert(devinfo
->gen
>= 7);
648 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
649 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[1]),
650 BRW_REGISTER_TYPE_UD
);
652 /* Read the vector */
653 const vec4_builder bld
= vec4_builder(this).at_end()
654 .annotate(current_annotation
, base_ir
);
657 dst_reg dest
= get_nir_dest(instr
->dest
);
658 if (type_sz(dest
.type
) < 8) {
659 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
660 1 /* dims */, 4 /* size*/,
663 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
666 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
667 1 /* dims */, 4 /* size*/,
669 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
671 if (offset_reg
.file
== IMM
)
674 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
676 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
677 1 /* dims */, 4 /* size*/,
679 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
682 read_result
= src_reg(this, glsl_type::dvec4_type
);
683 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
686 read_result
.type
= dest
.type
;
687 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
688 emit(MOV(dest
, read_result
));
692 case nir_intrinsic_ssbo_atomic_add
: {
693 int op
= BRW_AOP_ADD
;
694 const nir_const_value
*const val
= nir_src_as_const_value(instr
->src
[2]);
697 if (val
->i32
[0] == 1)
699 else if (val
->i32
[0] == -1)
703 nir_emit_ssbo_atomic(op
, instr
);
706 case nir_intrinsic_ssbo_atomic_imin
:
707 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
709 case nir_intrinsic_ssbo_atomic_umin
:
710 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
712 case nir_intrinsic_ssbo_atomic_imax
:
713 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
715 case nir_intrinsic_ssbo_atomic_umax
:
716 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
718 case nir_intrinsic_ssbo_atomic_and
:
719 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
721 case nir_intrinsic_ssbo_atomic_or
:
722 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
724 case nir_intrinsic_ssbo_atomic_xor
:
725 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
727 case nir_intrinsic_ssbo_atomic_exchange
:
728 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
730 case nir_intrinsic_ssbo_atomic_comp_swap
:
731 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
734 case nir_intrinsic_load_vertex_id
:
735 unreachable("should be lowered by lower_vertex_id()");
737 case nir_intrinsic_load_vertex_id_zero_base
:
738 case nir_intrinsic_load_base_vertex
:
739 case nir_intrinsic_load_instance_id
:
740 case nir_intrinsic_load_base_instance
:
741 case nir_intrinsic_load_draw_id
:
742 case nir_intrinsic_load_invocation_id
:
743 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
745 case nir_intrinsic_load_uniform
: {
746 /* Offsets are in bytes but they should always be multiples of 4 */
747 assert(nir_intrinsic_base(instr
) % 4 == 0);
749 dest
= get_nir_dest(instr
->dest
);
751 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
752 src
.type
= dest
.type
;
754 /* Uniforms don't actually have to be vec4 aligned. In the case that
755 * it isn't, we have to use a swizzle to shift things around. They
756 * do still have the std140 alignment requirement that vec2's have to
757 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
759 * The swizzle also works in the indirect case as the generator adds
760 * the swizzle to the offset for us.
762 const int type_size
= type_sz(src
.type
);
763 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
764 assert(shift
+ instr
->num_components
<= 4);
766 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
768 /* Offsets are in bytes but they should always be multiples of 4 */
769 assert(const_offset
->u32
[0] % 4 == 0);
771 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
772 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
773 unsigned offset
= const_offset
->u32
[0] + shift
* type_size
;
774 src
.offset
= ROUND_DOWN_TO(offset
, 16);
775 shift
= (offset
% 16) / type_size
;
776 assert(shift
+ instr
->num_components
<= 4);
777 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
779 emit(MOV(dest
, src
));
781 /* Uniform arrays are vec4 aligned, because of std140 alignment
786 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
788 /* MOV_INDIRECT is going to stomp the whole thing anyway */
789 dest
.writemask
= WRITEMASK_XYZW
;
791 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
792 indirect
, brw_imm_ud(instr
->const_index
[1]));
797 case nir_intrinsic_load_ubo
: {
798 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
801 dest
= get_nir_dest(instr
->dest
);
803 if (const_block_index
) {
804 /* The block index is a constant, so just emit the binding table entry
807 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
808 const_block_index
->u32
[0];
809 surf_index
= brw_imm_ud(index
);
810 brw_mark_surface_used(&prog_data
->base
, index
);
812 /* The block index is not a constant. Evaluate the index expression
813 * per-channel and add the base UBO index; we have to select a value
814 * from any live channel.
816 surf_index
= src_reg(this, glsl_type::uint_type
);
817 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
818 instr
->num_components
),
819 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
820 surf_index
= emit_uniformize(surf_index
);
822 /* Assume this may touch any UBO. It would be nice to provide
823 * a tighter bound, but the array information is already lowered away.
825 brw_mark_surface_used(&prog_data
->base
,
826 prog_data
->base
.binding_table
.ubo_start
+
827 nir
->info
.num_ubos
- 1);
831 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
833 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
835 offset_reg
= src_reg(this, glsl_type::uint_type
);
836 emit(MOV(dst_reg(offset_reg
),
837 get_nir_src(instr
->src
[1], nir_type_uint32
, 1)));
840 src_reg packed_consts
;
841 if (nir_dest_bit_size(instr
->dest
) == 32) {
842 packed_consts
= src_reg(this, glsl_type::vec4_type
);
843 emit_pull_constant_load_reg(dst_reg(packed_consts
),
846 NULL
, NULL
/* before_block/inst */);
848 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
849 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
851 emit_pull_constant_load_reg(dst_reg(temp_float
),
852 surf_index
, offset_reg
, NULL
, NULL
);
853 if (offset_reg
.file
== IMM
)
856 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
857 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
858 surf_index
, offset_reg
, NULL
, NULL
);
860 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
861 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
864 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
866 unsigned type_size
= type_sz(dest
.type
);
867 packed_consts
.swizzle
+=
868 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
869 const_offset
->u32
[0] % 16 / type_size
,
870 const_offset
->u32
[0] % 16 / type_size
,
871 const_offset
->u32
[0] % 16 / type_size
);
874 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
879 case nir_intrinsic_memory_barrier
: {
880 const vec4_builder bld
=
881 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
882 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
883 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
884 ->size_written
= 2 * REG_SIZE
;
888 case nir_intrinsic_shader_clock
: {
889 /* We cannot do anything if there is an event, so ignore it for now */
890 const src_reg shader_clock
= get_timestamp();
891 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
893 dest
= get_nir_dest(instr
->dest
, type
);
894 emit(MOV(dest
, shader_clock
));
899 unreachable("Unknown intrinsic");
904 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
907 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
908 dest
= get_nir_dest(instr
->dest
);
910 src_reg surface
= get_nir_ssbo_intrinsic_index(instr
);
911 src_reg offset
= get_nir_src(instr
->src
[1], 1);
913 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
914 data1
= get_nir_src(instr
->src
[2], 1);
916 if (op
== BRW_AOP_CMPWR
)
917 data2
= get_nir_src(instr
->src
[3], 1);
919 /* Emit the actual atomic operation operation */
920 const vec4_builder bld
=
921 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
923 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
925 1 /* dims */, 1 /* rsize */,
928 dest
.type
= atomic_result
.type
;
929 bld
.MOV(dest
, atomic_result
);
933 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
935 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
938 static enum brw_conditional_mod
939 brw_conditional_for_nir_comparison(nir_op op
)
945 return BRW_CONDITIONAL_L
;
950 return BRW_CONDITIONAL_GE
;
954 case nir_op_ball_fequal2
:
955 case nir_op_ball_iequal2
:
956 case nir_op_ball_fequal3
:
957 case nir_op_ball_iequal3
:
958 case nir_op_ball_fequal4
:
959 case nir_op_ball_iequal4
:
960 return BRW_CONDITIONAL_Z
;
964 case nir_op_bany_fnequal2
:
965 case nir_op_bany_inequal2
:
966 case nir_op_bany_fnequal3
:
967 case nir_op_bany_inequal3
:
968 case nir_op_bany_fnequal4
:
969 case nir_op_bany_inequal4
:
970 return BRW_CONDITIONAL_NZ
;
973 unreachable("not reached: bad operation for comparison");
978 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
979 enum brw_predicate
*predicate
)
981 if (!instr
->src
[0].src
.is_ssa
||
982 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
985 nir_alu_instr
*cmp_instr
=
986 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
988 switch (cmp_instr
->op
) {
989 case nir_op_bany_fnequal2
:
990 case nir_op_bany_inequal2
:
991 case nir_op_bany_fnequal3
:
992 case nir_op_bany_inequal3
:
993 case nir_op_bany_fnequal4
:
994 case nir_op_bany_inequal4
:
995 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
997 case nir_op_ball_fequal2
:
998 case nir_op_ball_iequal2
:
999 case nir_op_ball_fequal3
:
1000 case nir_op_ball_iequal3
:
1001 case nir_op_ball_fequal4
:
1002 case nir_op_ball_iequal4
:
1003 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1009 unsigned size_swizzle
=
1010 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1013 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1014 for (unsigned i
= 0; i
< 2; i
++) {
1015 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1016 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1017 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1018 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1019 unsigned base_swizzle
=
1020 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1021 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1022 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1023 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1026 emit(CMP(dst_null_d(), op
[0], op
[1],
1027 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1033 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1038 vec4_instruction
*inst
;
1042 /* LZD of an absolute value source almost always does the right
1043 * thing. There are two problem values:
1045 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1046 * 0. However, findMSB(int(0x80000000)) == 30.
1048 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1049 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1051 * For a value of zero or negative one, -1 will be returned.
1053 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1054 * findMSB(-(1<<x)) should return x-1.
1056 * For all negative number cases, including 0x80000000 and
1057 * 0xffffffff, the correct value is obtained from LZD if instead of
1058 * negating the (already negative) value the logical-not is used. A
1059 * conditonal logical-not can be achieved in two instructions.
1061 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1063 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1064 bld
.XOR(dst_reg(temp
), temp
, src
);
1067 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1068 retype(temp
, BRW_REGISTER_TYPE_UD
));
1070 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1071 * from the LSB side. Subtract the result from 31 to convert the MSB count
1072 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1073 * which is exactly what findMSB() is supposed to return.
1075 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1077 inst
->src
[0].negate
= true;
1081 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1084 /* BDW PRM vol 15 - workarounds:
1085 * DF->f format conversion for Align16 has wrong emask calculation when
1086 * source is immediate.
1088 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1089 src
.file
== BRW_IMMEDIATE_VALUE
) {
1090 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1091 inst
->saturate
= saturate
;
1097 case BRW_REGISTER_TYPE_D
:
1098 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1100 case BRW_REGISTER_TYPE_UD
:
1101 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1103 case BRW_REGISTER_TYPE_F
:
1104 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1107 unreachable("Unknown conversion");
1110 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1111 emit(MOV(temp
, src
));
1112 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1113 emit(op
, temp2
, src_reg(temp
));
1115 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1116 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1117 inst
->saturate
= saturate
;
1121 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1124 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1125 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1126 emit(MOV(dst_reg(tmp_src
), src
));
1127 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1128 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1129 inst
->saturate
= saturate
;
1133 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1135 vec4_instruction
*inst
;
1137 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1138 nir_dest_bit_size(instr
->dest
.dest
));
1139 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1140 dst
.writemask
= instr
->dest
.write_mask
;
1143 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1144 nir_alu_type src_type
= (nir_alu_type
)
1145 (nir_op_infos
[instr
->op
].input_types
[i
] |
1146 nir_src_bit_size(instr
->src
[i
].src
));
1147 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1148 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1149 op
[i
].abs
= instr
->src
[i
].abs
;
1150 op
[i
].negate
= instr
->src
[i
].negate
;
1153 switch (instr
->op
) {
1156 inst
= emit(MOV(dst
, op
[0]));
1157 inst
->saturate
= instr
->dest
.saturate
;
1163 unreachable("not reached: should be handled by lower_vec_to_movs()");
1167 inst
= emit(MOV(dst
, op
[0]));
1168 inst
->saturate
= instr
->dest
.saturate
;
1174 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1175 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1177 inst
= emit(MOV(dst
, op
[0]));
1183 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1187 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1190 inst
= emit(ADD(dst
, op
[0], op
[1]));
1191 inst
->saturate
= instr
->dest
.saturate
;
1195 inst
= emit(MUL(dst
, op
[0], op
[1]));
1196 inst
->saturate
= instr
->dest
.saturate
;
1200 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1201 if (devinfo
->gen
< 8) {
1202 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1203 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1205 /* For integer multiplication, the MUL uses the low 16 bits of one of
1206 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1207 * accumulates in the contribution of the upper 16 bits of that
1208 * operand. If we can determine that one of the args is in the low
1209 * 16 bits, though, we can just emit a single MUL.
1211 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1212 if (devinfo
->gen
< 7)
1213 emit(MUL(dst
, op
[0], op
[1]));
1215 emit(MUL(dst
, op
[1], op
[0]));
1216 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1217 if (devinfo
->gen
< 7)
1218 emit(MUL(dst
, op
[1], op
[0]));
1220 emit(MUL(dst
, op
[0], op
[1]));
1222 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1224 emit(MUL(acc
, op
[0], op
[1]));
1225 emit(MACH(dst_null_d(), op
[0], op
[1]));
1226 emit(MOV(dst
, src_reg(acc
)));
1229 emit(MUL(dst
, op
[0], op
[1]));
1234 case nir_op_imul_high
:
1235 case nir_op_umul_high
: {
1236 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1237 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1239 if (devinfo
->gen
>= 8)
1240 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1242 emit(MUL(acc
, op
[0], op
[1]));
1244 emit(MACH(dst
, op
[0], op
[1]));
1249 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1250 inst
->saturate
= instr
->dest
.saturate
;
1254 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1255 inst
->saturate
= instr
->dest
.saturate
;
1259 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1260 inst
->saturate
= instr
->dest
.saturate
;
1264 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1265 inst
->saturate
= instr
->dest
.saturate
;
1269 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1270 inst
->saturate
= instr
->dest
.saturate
;
1275 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1276 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1281 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1282 * appears that our hardware just does the right thing for signed
1285 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1286 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1290 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1291 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1293 /* Math instructions don't support conditional mod */
1294 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1295 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1297 /* Now, we need to determine if signs of the sources are different.
1298 * When we XOR the sources, the top bit is 0 if they are the same and 1
1299 * if they are different. We can then use a conditional modifier to
1300 * turn that into a predicate. This leads us to an XOR.l instruction.
1302 * Technically, according to the PRM, you're not allowed to use .l on a
1303 * XOR instruction. However, emperical experiments and Curro's reading
1304 * of the simulator source both indicate that it's safe.
1306 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1307 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1308 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1309 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1311 /* If the result of the initial remainder operation is non-zero and the
1312 * two sources have different signs, add in a copy of op[1] to get the
1313 * final integer modulus value.
1315 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1316 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1321 unreachable("not reached: should be handled by ldexp_to_arith()");
1324 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1325 inst
->saturate
= instr
->dest
.saturate
;
1329 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1330 inst
->saturate
= instr
->dest
.saturate
;
1334 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1335 inst
->saturate
= instr
->dest
.saturate
;
1338 case nir_op_uadd_carry
: {
1339 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1340 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1342 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1343 emit(MOV(dst
, src_reg(acc
)));
1347 case nir_op_usub_borrow
: {
1348 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1349 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1351 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1352 emit(MOV(dst
, src_reg(acc
)));
1357 inst
= emit(RNDZ(dst
, op
[0]));
1358 inst
->saturate
= instr
->dest
.saturate
;
1361 case nir_op_fceil
: {
1362 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1364 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1365 instr
->src
[0].src
.ssa
->num_components
:
1366 instr
->src
[0].src
.reg
.reg
->num_components
);
1368 op
[0].negate
= !op
[0].negate
;
1369 emit(RNDD(dst_reg(tmp
), op
[0]));
1371 inst
= emit(MOV(dst
, tmp
));
1372 inst
->saturate
= instr
->dest
.saturate
;
1377 inst
= emit(RNDD(dst
, op
[0]));
1378 inst
->saturate
= instr
->dest
.saturate
;
1382 inst
= emit(FRC(dst
, op
[0]));
1383 inst
->saturate
= instr
->dest
.saturate
;
1386 case nir_op_fround_even
:
1387 inst
= emit(RNDE(dst
, op
[0]));
1388 inst
->saturate
= instr
->dest
.saturate
;
1391 case nir_op_fquantize2f16
: {
1392 /* See also vec4_visitor::emit_pack_half_2x16() */
1393 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1394 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1395 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1397 /* Check for denormal */
1398 src_reg abs_src0
= op
[0];
1399 abs_src0
.abs
= true;
1400 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1401 BRW_CONDITIONAL_L
));
1402 /* Get the appropriately signed zero */
1403 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1404 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1405 brw_imm_ud(0x80000000)));
1406 /* Do the actual F32 -> F16 -> F32 conversion */
1407 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1408 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1409 /* Select that or zero based on normal status */
1410 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1411 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1412 inst
->saturate
= instr
->dest
.saturate
;
1418 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1421 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1422 inst
->saturate
= instr
->dest
.saturate
;
1427 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1430 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1431 inst
->saturate
= instr
->dest
.saturate
;
1435 case nir_op_fddx_coarse
:
1436 case nir_op_fddx_fine
:
1438 case nir_op_fddy_coarse
:
1439 case nir_op_fddy_fine
:
1440 unreachable("derivatives are not valid in vertex shaders");
1448 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1454 enum brw_conditional_mod conditional_mod
=
1455 brw_conditional_for_nir_comparison(instr
->op
);
1457 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1458 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1460 /* Produce a 32-bit boolean result from the DF comparison by selecting
1461 * only the low 32-bit in each DF produced. Do this in a temporary
1462 * so we can then move from there to the result using align16 again
1463 * to honor the original writemask.
1465 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1466 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1467 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1468 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1469 emit(MOV(dst
, src_reg(result
)));
1474 case nir_op_ball_iequal2
:
1475 case nir_op_ball_iequal3
:
1476 case nir_op_ball_iequal4
:
1477 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1479 case nir_op_ball_fequal2
:
1480 case nir_op_ball_fequal3
:
1481 case nir_op_ball_fequal4
: {
1483 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1485 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1486 brw_conditional_for_nir_comparison(instr
->op
)));
1487 emit(MOV(dst
, brw_imm_d(0)));
1488 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1489 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1493 case nir_op_bany_inequal2
:
1494 case nir_op_bany_inequal3
:
1495 case nir_op_bany_inequal4
:
1496 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1498 case nir_op_bany_fnequal2
:
1499 case nir_op_bany_fnequal3
:
1500 case nir_op_bany_fnequal4
: {
1502 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1504 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1505 brw_conditional_for_nir_comparison(instr
->op
)));
1507 emit(MOV(dst
, brw_imm_d(0)));
1508 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1509 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1514 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1515 if (devinfo
->gen
>= 8) {
1516 op
[0] = resolve_source_modifiers(op
[0]);
1518 emit(NOT(dst
, op
[0]));
1522 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1523 if (devinfo
->gen
>= 8) {
1524 op
[0] = resolve_source_modifiers(op
[0]);
1525 op
[1] = resolve_source_modifiers(op
[1]);
1527 emit(XOR(dst
, op
[0], op
[1]));
1531 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1532 if (devinfo
->gen
>= 8) {
1533 op
[0] = resolve_source_modifiers(op
[0]);
1534 op
[1] = resolve_source_modifiers(op
[1]);
1536 emit(OR(dst
, op
[0], op
[1]));
1540 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1541 if (devinfo
->gen
>= 8) {
1542 op
[0] = resolve_source_modifiers(op
[0]);
1543 op
[1] = resolve_source_modifiers(op
[1]);
1545 emit(AND(dst
, op
[0], op
[1]));
1550 if (nir_dest_bit_size(instr
->dest
.dest
) > 32) {
1551 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
1552 emit_conversion_to_double(dst
, negate(op
[0]), false);
1554 emit(MOV(dst
, negate(op
[0])));
1559 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1560 /* We use a MOV with conditional_mod to check if the provided value is
1561 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1562 * source modifier on the source operand to trigger this, as source
1563 * modifiers don't affect the result of the testing against 0.0.
1565 src_reg value
= op
[0];
1567 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1568 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1570 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1571 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1572 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1573 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1575 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1580 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1583 case nir_op_fnoise1_1
:
1584 case nir_op_fnoise1_2
:
1585 case nir_op_fnoise1_3
:
1586 case nir_op_fnoise1_4
:
1587 case nir_op_fnoise2_1
:
1588 case nir_op_fnoise2_2
:
1589 case nir_op_fnoise2_3
:
1590 case nir_op_fnoise2_4
:
1591 case nir_op_fnoise3_1
:
1592 case nir_op_fnoise3_2
:
1593 case nir_op_fnoise3_3
:
1594 case nir_op_fnoise3_4
:
1595 case nir_op_fnoise4_1
:
1596 case nir_op_fnoise4_2
:
1597 case nir_op_fnoise4_3
:
1598 case nir_op_fnoise4_4
:
1599 unreachable("not reached: should be handled by lower_noise");
1601 case nir_op_unpack_half_2x16_split_x
:
1602 case nir_op_unpack_half_2x16_split_y
:
1603 case nir_op_pack_half_2x16_split
:
1604 unreachable("not reached: should not occur in vertex shader");
1606 case nir_op_unpack_snorm_2x16
:
1607 case nir_op_unpack_unorm_2x16
:
1608 case nir_op_pack_snorm_2x16
:
1609 case nir_op_pack_unorm_2x16
:
1610 unreachable("not reached: should be handled by lower_packing_builtins");
1612 case nir_op_pack_uvec4_to_uint
:
1613 unreachable("not reached");
1615 case nir_op_pack_uvec2_to_uint
: {
1616 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1617 tmp1
.writemask
= WRITEMASK_X
;
1618 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1619 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1621 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1622 tmp2
.writemask
= WRITEMASK_X
;
1623 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1624 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1626 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1630 case nir_op_pack_64_2x32_split
: {
1631 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1632 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1633 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1634 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1635 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1636 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1637 emit(MOV(dst
, src_reg(result
)));
1641 case nir_op_unpack_64_2x32_split_x
:
1642 case nir_op_unpack_64_2x32_split_y
: {
1643 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1644 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1645 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1646 emit(MOV(tmp
, op
[0]));
1647 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1648 emit(oper
, tmp2
, src_reg(tmp
));
1649 emit(MOV(dst
, src_reg(tmp2
)));
1653 case nir_op_unpack_half_2x16
:
1654 /* As NIR does not guarantee that we have a correct swizzle outside the
1655 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1656 * uses the source operand in an operation with WRITEMASK_Y while our
1657 * source operand has only size 1, it accessed incorrect data producing
1658 * regressions in Piglit. We repeat the swizzle of the first component on the
1659 * rest of components to avoid regressions. In the vec4_visitor IR code path
1660 * this is not needed because the operand has already the correct swizzle.
1662 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1663 emit_unpack_half_2x16(dst
, op
[0]);
1666 case nir_op_pack_half_2x16
:
1667 emit_pack_half_2x16(dst
, op
[0]);
1670 case nir_op_unpack_unorm_4x8
:
1671 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1672 emit_unpack_unorm_4x8(dst
, op
[0]);
1675 case nir_op_pack_unorm_4x8
:
1676 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1677 emit_pack_unorm_4x8(dst
, op
[0]);
1680 case nir_op_unpack_snorm_4x8
:
1681 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1682 emit_unpack_snorm_4x8(dst
, op
[0]);
1685 case nir_op_pack_snorm_4x8
:
1686 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1687 emit_pack_snorm_4x8(dst
, op
[0]);
1690 case nir_op_bitfield_reverse
:
1691 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1692 emit(BFREV(dst
, op
[0]));
1695 case nir_op_bit_count
:
1696 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1697 emit(CBIT(dst
, op
[0]));
1700 case nir_op_ufind_msb
:
1701 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1702 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1705 case nir_op_ifind_msb
: {
1706 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1707 vec4_builder bld
= vec4_builder(this).at_end();
1710 if (devinfo
->gen
< 7) {
1711 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1713 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1715 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1716 * count from the LSB side. If FBH didn't return an error
1717 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1718 * count into an LSB count.
1720 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1722 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1723 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1724 inst
->src
[0].negate
= true;
1729 case nir_op_find_lsb
: {
1730 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1731 vec4_builder bld
= vec4_builder(this).at_end();
1733 if (devinfo
->gen
< 7) {
1734 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1736 /* (x & -x) generates a value that consists of only the LSB of x.
1737 * For all powers of 2, findMSB(y) == findLSB(y).
1739 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1740 src_reg negated_src
= src
;
1742 /* One must be negated, and the other must be non-negated. It
1743 * doesn't matter which is which.
1745 negated_src
.negate
= true;
1748 bld
.AND(temp
, src
, negated_src
);
1749 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1751 bld
.FBL(dst
, op
[0]);
1756 case nir_op_ubitfield_extract
:
1757 case nir_op_ibitfield_extract
:
1758 unreachable("should have been lowered");
1761 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1762 op
[0] = fix_3src_operand(op
[0]);
1763 op
[1] = fix_3src_operand(op
[1]);
1764 op
[2] = fix_3src_operand(op
[2]);
1766 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1770 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1771 emit(BFI1(dst
, op
[0], op
[1]));
1775 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1776 op
[0] = fix_3src_operand(op
[0]);
1777 op
[1] = fix_3src_operand(op
[1]);
1778 op
[2] = fix_3src_operand(op
[2]);
1780 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1783 case nir_op_bitfield_insert
:
1784 unreachable("not reached: should have been lowered");
1787 assert(!instr
->dest
.saturate
);
1789 /* Straightforward since the source can be assumed to be either
1790 * strictly >= 0 or strictly <= 0 depending on the setting of the
1793 inst
= emit(MOV(dst
, op
[0]));
1794 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1796 inst
= (op
[0].negate
)
1797 ? emit(MOV(dst
, brw_imm_f(-1.0f
)))
1798 : emit(MOV(dst
, brw_imm_f(1.0f
)));
1799 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1800 } else if (type_sz(op
[0].type
) < 8) {
1801 /* AND(val, 0x80000000) gives the sign bit.
1803 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1806 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1808 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1809 dst
.type
= BRW_REGISTER_TYPE_UD
;
1810 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1812 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1813 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1814 dst
.type
= BRW_REGISTER_TYPE_F
;
1816 /* For doubles we do the same but we need to consider:
1818 * - We use a MOV with conditional_mod instead of a CMP so that we can
1819 * skip loading a 0.0 immediate. We use a source modifier on the
1820 * source of the MOV so that we flush denormalized values to 0.
1821 * Since we want to compare against 0, this won't alter the result.
1822 * - We need to extract the high 32-bit of each DF where the sign
1824 * - We need to produce a DF result.
1827 /* Check for zero */
1828 src_reg value
= op
[0];
1830 inst
= emit(MOV(dst_null_df(), value
));
1831 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1833 /* AND each high 32-bit channel with 0x80000000u */
1834 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1835 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1836 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1838 /* Add 1.0 to each channel, predicated to skip the cases where the
1839 * channel's value was 0
1841 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1842 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1844 /* Now convert the result from float to double */
1845 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1846 BRW_REGISTER_TYPE_F
),
1852 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1853 * -> non-negative val generates 0x00000000.
1854 * Predicated OR sets 1 if val is positive.
1856 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1857 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1858 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1859 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1860 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1864 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1865 emit(SHL(dst
, op
[0], op
[1]));
1869 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1870 emit(ASR(dst
, op
[0], op
[1]));
1874 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1875 emit(SHR(dst
, op
[0], op
[1]));
1879 if (type_sz(dst
.type
) == 8) {
1880 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1881 emit(MUL(mul_dst
, op
[1], op
[0]));
1882 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1883 inst
->saturate
= instr
->dest
.saturate
;
1885 op
[0] = fix_3src_operand(op
[0]);
1886 op
[1] = fix_3src_operand(op
[1]);
1887 op
[2] = fix_3src_operand(op
[2]);
1889 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1890 inst
->saturate
= instr
->dest
.saturate
;
1895 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1896 inst
->saturate
= instr
->dest
.saturate
;
1900 enum brw_predicate predicate
;
1901 if (!optimize_predicate(instr
, &predicate
)) {
1902 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1903 switch (dst
.writemask
) {
1905 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1908 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1911 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1914 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1917 predicate
= BRW_PREDICATE_NORMAL
;
1921 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1922 inst
->predicate
= predicate
;
1925 case nir_op_fdot_replicated2
:
1926 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1927 inst
->saturate
= instr
->dest
.saturate
;
1930 case nir_op_fdot_replicated3
:
1931 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1932 inst
->saturate
= instr
->dest
.saturate
;
1935 case nir_op_fdot_replicated4
:
1936 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1937 inst
->saturate
= instr
->dest
.saturate
;
1940 case nir_op_fdph_replicated
:
1941 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1942 inst
->saturate
= instr
->dest
.saturate
;
1947 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1952 unreachable("not reached: should be lowered by lower_source mods");
1955 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1958 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1962 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1965 unreachable("Unimplemented ALU operation");
1968 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1969 * to sign extend the low bit to 0/~0
1971 if (devinfo
->gen
<= 5 &&
1972 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
1973 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1974 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
1975 masked
.writemask
= dst
.writemask
;
1976 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
1977 src_reg masked_neg
= src_reg(masked
);
1978 masked_neg
.negate
= true;
1979 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
1984 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1986 switch (instr
->type
) {
1987 case nir_jump_break
:
1988 emit(BRW_OPCODE_BREAK
);
1991 case nir_jump_continue
:
1992 emit(BRW_OPCODE_CONTINUE
);
1995 case nir_jump_return
:
1998 unreachable("unknown jump");
2002 static enum ir_texture_opcode
2003 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2005 enum ir_texture_opcode op
;
2008 case nir_texop_lod
: op
= ir_lod
; break;
2009 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2010 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2011 case nir_texop_tex
: op
= ir_tex
; break;
2012 case nir_texop_tg4
: op
= ir_tg4
; break;
2013 case nir_texop_txb
: op
= ir_txb
; break;
2014 case nir_texop_txd
: op
= ir_txd
; break;
2015 case nir_texop_txf
: op
= ir_txf
; break;
2016 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2017 case nir_texop_txl
: op
= ir_txl
; break;
2018 case nir_texop_txs
: op
= ir_txs
; break;
2019 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2021 unreachable("unknown texture opcode");
2027 static const glsl_type
*
2028 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2029 unsigned components
)
2031 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2036 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2038 unsigned texture
= instr
->texture_index
;
2039 unsigned sampler
= instr
->sampler_index
;
2040 src_reg texture_reg
= brw_imm_ud(texture
);
2041 src_reg sampler_reg
= brw_imm_ud(sampler
);
2043 const glsl_type
*coord_type
= NULL
;
2044 src_reg shadow_comparator
;
2045 src_reg offset_value
;
2047 src_reg sample_index
;
2050 const glsl_type
*dest_type
=
2051 glsl_type_for_nir_alu_type(instr
->dest_type
,
2052 nir_tex_instr_dest_size(instr
));
2053 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2055 /* The hardware requires a LOD for buffer textures */
2056 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2059 /* Load the texture operation sources */
2060 uint32_t constant_offset
= 0;
2061 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2062 switch (instr
->src
[i
].src_type
) {
2063 case nir_tex_src_comparator
:
2064 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2065 BRW_REGISTER_TYPE_F
, 1);
2068 case nir_tex_src_coord
: {
2069 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2071 switch (instr
->op
) {
2073 case nir_texop_txf_ms
:
2074 case nir_texop_samples_identical
:
2075 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2077 coord_type
= glsl_type::ivec(src_size
);
2081 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2083 coord_type
= glsl_type::vec(src_size
);
2089 case nir_tex_src_ddx
:
2090 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2091 nir_tex_instr_src_size(instr
, i
));
2094 case nir_tex_src_ddy
:
2095 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2096 nir_tex_instr_src_size(instr
, i
));
2099 case nir_tex_src_lod
:
2100 switch (instr
->op
) {
2103 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2107 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2112 case nir_tex_src_ms_index
: {
2113 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2117 case nir_tex_src_offset
: {
2118 nir_const_value
*const_offset
=
2119 nir_src_as_const_value(instr
->src
[i
].src
);
2120 if (!const_offset
||
2121 !brw_texture_offset(const_offset
->i32
,
2122 nir_tex_instr_src_size(instr
, i
),
2123 &constant_offset
)) {
2125 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2130 case nir_tex_src_texture_offset
: {
2131 /* The highest texture which may be used by this operation is
2132 * the last element of the array. Mark it here, because the generator
2133 * doesn't have enough information to determine the bound.
2135 uint32_t array_size
= instr
->texture_array_size
;
2136 uint32_t max_used
= texture
+ array_size
- 1;
2137 if (instr
->op
== nir_texop_tg4
) {
2138 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2140 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2143 brw_mark_surface_used(&prog_data
->base
, max_used
);
2145 /* Emit code to evaluate the actual indexing expression */
2146 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2147 src_reg
temp(this, glsl_type::uint_type
);
2148 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2149 texture_reg
= emit_uniformize(temp
);
2153 case nir_tex_src_sampler_offset
: {
2154 /* Emit code to evaluate the actual indexing expression */
2155 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2156 src_reg
temp(this, glsl_type::uint_type
);
2157 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2158 sampler_reg
= emit_uniformize(temp
);
2162 case nir_tex_src_projector
:
2163 unreachable("Should be lowered by do_lower_texture_projection");
2165 case nir_tex_src_bias
:
2166 unreachable("LOD bias is not valid for vertex shaders.\n");
2169 unreachable("unknown texture source");
2173 if (instr
->op
== nir_texop_txf_ms
||
2174 instr
->op
== nir_texop_samples_identical
) {
2175 assert(coord_type
!= NULL
);
2176 if (devinfo
->gen
>= 7 &&
2177 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2178 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2180 mcs
= brw_imm_ud(0u);
2184 /* Stuff the channel select bits in the top of the texture offset */
2185 if (instr
->op
== nir_texop_tg4
) {
2186 if (instr
->component
== 1 &&
2187 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2188 /* gather4 sampler is broken for green channel on RG32F --
2189 * we must ask for blue instead.
2191 constant_offset
|= 2 << 16;
2193 constant_offset
|= instr
->component
<< 16;
2197 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2199 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2201 lod
, lod2
, sample_index
,
2202 constant_offset
, offset_value
, mcs
,
2203 texture
, texture_reg
, sampler_reg
);
2207 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2209 nir_ssa_values
[instr
->def
.index
] =
2210 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2213 /* SIMD4x2 64bit data is stored in register space like this:
2215 * r0.0:DF x0 y0 z0 w0
2216 * r1.0:DF x1 y1 z1 w1
2218 * When we need to write data such as this to memory using 32-bit write
2219 * messages we need to shuffle it in this fashion:
2221 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2222 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2224 * We need to do the inverse operation when we read using 32-bit messages,
2225 * which we can do by applying the same exact shuffling on the 64-bit data
2226 * read, only that because the data for each vertex is positioned differently
2227 * we need to apply different channel enables.
2229 * This function takes 64bit data and shuffles it as explained above.
2231 * The @for_write parameter is used to specify if the shuffling is being done
2232 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2233 * write message (for_write = true), or instead we are doing the inverse
2234 * operation and we have just read 64-bit data using a 32-bit messages that we
2235 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2237 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2238 * otherwise the instructions are emitted normally at the end. The function
2239 * returns the last instruction inserted.
2241 * Notice that @src and @dst cannot be the same register.
2244 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2245 bblock_t
*block
, vec4_instruction
*ref
)
2247 assert(type_sz(src
.type
) == 8);
2248 assert(type_sz(dst
.type
) == 8);
2249 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2250 assert(!ref
== !block
);
2252 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2253 vec4_builder(this).at(block
, ref
->next
);
2255 /* Resolve swizzle in src */
2256 vec4_instruction
*inst
;
2257 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2258 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2259 inst
= bld
.MOV(data
, src
);
2260 src
= src_reg(data
);
2263 /* dst+0.XY = src+0.XY */
2264 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2266 /* dst+0.ZW = src+1.XY */
2267 inst
= bld
.group(4, for_write
? 1 : 0)
2268 .MOV(writemask(dst
, WRITEMASK_ZW
),
2269 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2271 /* dst+1.XY = src+0.ZW */
2272 inst
= bld
.group(4, for_write
? 0 : 1)
2273 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2274 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2276 /* dst+1.ZW = src+1.ZW */
2277 inst
= bld
.group(4, 1)
2278 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2279 byte_offset(src
, REG_SIZE
));