2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
31 using namespace brw::surface_access
;
36 vec4_visitor::emit_nir_code()
38 if (nir
->num_uniforms
> 0)
41 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
45 vec4_visitor::nir_setup_uniforms()
47 uniforms
= nir
->num_uniforms
/ 16;
51 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
53 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
54 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
55 nir_locals
[i
] = dst_reg();
58 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
59 unsigned array_elems
=
60 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
61 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
62 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
64 if (reg
->bit_size
== 64)
65 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
68 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
70 nir_emit_cf_list(&impl
->body
);
74 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
76 exec_list_validate(list
);
77 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
80 nir_emit_if(nir_cf_node_as_if(node
));
83 case nir_cf_node_loop
:
84 nir_emit_loop(nir_cf_node_as_loop(node
));
87 case nir_cf_node_block
:
88 nir_emit_block(nir_cf_node_as_block(node
));
92 unreachable("Invalid CFG node block");
98 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
100 /* First, put the condition in f0 */
101 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
102 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
103 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
105 /* We can just predicate based on the X channel, as the condition only
106 * goes on its own line */
107 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
109 nir_emit_cf_list(&if_stmt
->then_list
);
111 /* note: if the else is empty, dead CF elimination will remove it */
112 emit(BRW_OPCODE_ELSE
);
114 nir_emit_cf_list(&if_stmt
->else_list
);
116 emit(BRW_OPCODE_ENDIF
);
120 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
124 nir_emit_cf_list(&loop
->body
);
126 emit(BRW_OPCODE_WHILE
);
130 vec4_visitor::nir_emit_block(nir_block
*block
)
132 nir_foreach_instr(instr
, block
) {
133 nir_emit_instr(instr
);
138 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
142 switch (instr
->type
) {
143 case nir_instr_type_load_const
:
144 nir_emit_load_const(nir_instr_as_load_const(instr
));
147 case nir_instr_type_intrinsic
:
148 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
151 case nir_instr_type_alu
:
152 nir_emit_alu(nir_instr_as_alu(instr
));
155 case nir_instr_type_jump
:
156 nir_emit_jump(nir_instr_as_jump(instr
));
159 case nir_instr_type_tex
:
160 nir_emit_texture(nir_instr_as_tex(instr
));
163 case nir_instr_type_ssa_undef
:
164 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
168 unreachable("VS instruction not yet implemented by NIR->vec4");
173 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
174 unsigned base_offset
, nir_src
*indirect
)
178 reg
= v
->nir_locals
[nir_reg
->index
];
179 if (nir_reg
->bit_size
== 64)
180 reg
.type
= BRW_REGISTER_TYPE_DF
;
181 reg
= offset(reg
, 8, base_offset
);
184 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
192 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
196 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
197 if (dest
.ssa
.bit_size
== 64)
198 dst
.type
= BRW_REGISTER_TYPE_DF
;
199 nir_ssa_values
[dest
.ssa
.index
] = dst
;
202 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
208 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
210 return retype(get_nir_dest(dest
), type
);
214 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
216 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
220 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
221 unsigned num_components
)
226 assert(src
.ssa
!= NULL
);
227 reg
= nir_ssa_values
[src
.ssa
->index
];
230 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
234 reg
= retype(reg
, type
);
236 src_reg reg_as_src
= src_reg(reg
);
237 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
242 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
243 unsigned num_components
)
245 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
250 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
252 /* if type is not specified, default to signed int */
253 return get_nir_src(src
, nir_type_int32
, num_components
);
257 vec4_visitor::get_nir_src_imm(const nir_src
&src
)
259 assert(nir_src_num_components(src
) == 1);
260 assert(nir_src_bit_size(src
) == 32);
261 return nir_src_is_const(src
) ? src_reg(brw_imm_d(nir_src_as_int(src
))) :
266 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
268 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
270 if (nir_src_is_const(*offset_src
)) {
271 /* The only constant offset we should find is 0. brw_nir.c's
272 * add_const_offset_to_base() will fold other constant offsets
273 * into instr->const_index[0].
275 assert(nir_src_as_uint(*offset_src
) == 0);
279 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
283 setup_imm_df(const vec4_builder
&bld
, double v
)
285 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
286 assert(devinfo
->gen
>= 7);
288 if (devinfo
->gen
>= 8)
289 return brw_imm_df(v
);
291 /* gen7.5 does not support DF immediates straighforward but the DIM
292 * instruction allows to set the 64-bit immediate value.
294 if (devinfo
->is_haswell
) {
295 const vec4_builder ubld
= bld
.exec_all();
296 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
297 ubld
.DIM(dst
, brw_imm_df(v
));
298 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
301 /* gen7 does not support DF immediates */
312 /* Write the low 32-bit of the constant to the X:UD channel and the
313 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
314 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
315 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
316 * XXXX so any access to the VGRF only reads the constant data in these
319 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
320 for (unsigned n
= 0; n
< 2; n
++) {
321 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
322 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
323 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
326 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
330 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
334 if (instr
->def
.bit_size
== 64) {
335 reg
= dst_reg(VGRF
, alloc
.allocate(2));
336 reg
.type
= BRW_REGISTER_TYPE_DF
;
338 reg
= dst_reg(VGRF
, alloc
.allocate(1));
339 reg
.type
= BRW_REGISTER_TYPE_D
;
342 const vec4_builder ibld
= vec4_builder(this).at_end();
343 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
345 /* @FIXME: consider emitting vector operations to save some MOVs in
346 * cases where the components are representable in 8 bits.
347 * For now, we emit a MOV for each distinct value.
349 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
350 unsigned writemask
= 1 << i
;
352 if ((remaining
& writemask
) == 0)
355 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
356 if ((instr
->def
.bit_size
== 32 &&
357 instr
->value
[i
].u32
== instr
->value
[j
].u32
) ||
358 (instr
->def
.bit_size
== 64 &&
359 instr
->value
[i
].f64
== instr
->value
[j
].f64
)) {
364 reg
.writemask
= writemask
;
365 if (instr
->def
.bit_size
== 64) {
366 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
[i
].f64
)));
368 emit(MOV(reg
, brw_imm_d(instr
->value
[i
].i32
)));
371 remaining
&= ~writemask
;
374 /* Set final writemask */
375 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
377 nir_ssa_values
[instr
->def
.index
] = reg
;
381 vec4_visitor::get_nir_ssbo_intrinsic_index(nir_intrinsic_instr
*instr
)
383 /* SSBO stores are weird in that their index is in src[1] */
384 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
387 if (nir_src_is_const(instr
->src
[src
])) {
388 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
389 nir_src_as_uint(instr
->src
[src
]);
390 surf_index
= brw_imm_ud(index
);
392 surf_index
= src_reg(this, glsl_type::uint_type
);
393 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[src
], 1),
394 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
395 surf_index
= emit_uniformize(surf_index
);
402 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
407 switch (instr
->intrinsic
) {
409 case nir_intrinsic_load_input
: {
410 /* We set EmitNoIndirectInput for VS */
411 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
413 dest
= get_nir_dest(instr
->dest
);
414 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
416 src
= src_reg(ATTR
, instr
->const_index
[0] + load_offset
,
417 glsl_type::uvec4_type
);
418 src
= retype(src
, dest
.type
);
420 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
422 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
423 src
.swizzle
= BRW_SWIZZLE_XYZW
;
424 shuffle_64bit_data(tmp
, src
, false);
425 emit(MOV(dest
, src_reg(tmp
)));
427 /* Swizzle source based on component layout qualifier */
428 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
429 emit(MOV(dest
, src
));
434 case nir_intrinsic_store_output
: {
435 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
436 int varying
= instr
->const_index
[0] + store_offset
;
438 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
441 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
442 instr
->num_components
);
443 data
= src_reg(this, glsl_type::dvec4_type
);
444 shuffle_64bit_data(dst_reg(data
), src
, true);
445 src
= retype(data
, BRW_REGISTER_TYPE_F
);
447 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
448 instr
->num_components
);
451 unsigned c
= nir_intrinsic_component(instr
);
452 output_reg
[varying
][c
] = dst_reg(src
);
453 output_num_components
[varying
][c
] = instr
->num_components
;
455 unsigned num_components
= instr
->num_components
;
459 output_reg
[varying
][c
] = dst_reg(src
);
460 output_num_components
[varying
][c
] = MIN2(4, num_components
);
462 if (is_64bit
&& num_components
> 4) {
463 assert(num_components
<= 8);
464 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
465 output_num_components
[varying
+ 1][c
] = num_components
- 4;
470 case nir_intrinsic_get_buffer_size
: {
471 assert(nir_src_num_components(instr
->src
[0]) == 1);
472 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
473 nir_src_as_uint(instr
->src
[0]) : 0;
475 const unsigned index
=
476 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
477 dst_reg result_dst
= get_nir_dest(instr
->dest
);
478 vec4_instruction
*inst
= new(mem_ctx
)
479 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE
, result_dst
);
482 inst
->mlen
= 1; /* always at least one */
483 inst
->src
[1] = brw_imm_ud(index
);
485 /* MRF for the first parameter */
486 src_reg lod
= brw_imm_d(0);
487 int param_base
= inst
->base_mrf
;
488 int writemask
= WRITEMASK_X
;
489 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
495 case nir_intrinsic_store_ssbo
: {
496 assert(devinfo
->gen
>= 7);
498 /* brw_nir_lower_mem_access_bit_sizes takes care of this */
499 assert(nir_src_bit_size(instr
->src
[0]) == 32);
500 assert(nir_intrinsic_write_mask(instr
) ==
501 (1u << instr
->num_components
) - 1);
503 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
504 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[2]),
505 BRW_REGISTER_TYPE_UD
);
508 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
510 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
511 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
512 * typed and untyped messages and across hardware platforms, the
513 * current implementation of the untyped messages will transparently convert
514 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
515 * and enabling only channel X on the SEND instruction.
517 * The above, works well for full vector writes, but not for partial writes
518 * where we want to write some channels and not others, like when we have
519 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
520 * quite restrictive with regards to the channel enables we can configure in
521 * the message descriptor (not all combinations are allowed) we cannot simply
522 * implement these scenarios with a single message while keeping the
523 * aforementioned symmetry in the implementation. For now we de decided that
524 * it is better to keep the symmetry to reduce complexity, so in situations
525 * such as the one described we end up emitting two untyped write messages
526 * (one for xy and another for w).
528 * The code below packs consecutive channels into a single write message,
529 * detects gaps in the vector write and if needed, sends a second message
530 * with the remaining channels. If in the future we decide that we want to
531 * emit a single message at the expense of losing the symmetry in the
532 * implementation we can:
534 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
535 * message payload. In this mode we can write up to 8 offsets and dwords
536 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
537 * and select which of the 8 channels carry data to write by setting the
538 * appropriate writemask in the dst register of the SEND instruction.
539 * It would require to write a new generator opcode specifically for
540 * IvyBridge since we would need to prepare a SIMD8 payload that could
541 * use any channel, not just X.
543 * 2) For Haswell+: Simply send a single write message but set the writemask
544 * on the dst of the SEND instruction to select the channels we want to
545 * write. It would require to modify the current messages to receive
546 * and honor the writemask provided.
548 const vec4_builder bld
= vec4_builder(this).at_end()
549 .annotate(current_annotation
, base_ir
);
551 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
552 1 /* dims */, instr
->num_components
/* size */,
557 case nir_intrinsic_load_ssbo
: {
558 assert(devinfo
->gen
>= 7);
560 /* brw_nir_lower_mem_access_bit_sizes takes care of this */
561 assert(nir_dest_bit_size(instr
->dest
) == 32);
563 src_reg surf_index
= get_nir_ssbo_intrinsic_index(instr
);
564 src_reg offset_reg
= retype(get_nir_src_imm(instr
->src
[1]),
565 BRW_REGISTER_TYPE_UD
);
567 /* Read the vector */
568 const vec4_builder bld
= vec4_builder(this).at_end()
569 .annotate(current_annotation
, base_ir
);
571 src_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
572 1 /* dims */, 4 /* size*/,
574 dst_reg dest
= get_nir_dest(instr
->dest
);
575 read_result
.type
= dest
.type
;
576 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
577 emit(MOV(dest
, read_result
));
581 case nir_intrinsic_ssbo_atomic_add
: {
582 int op
= BRW_AOP_ADD
;
584 if (nir_src_is_const(instr
->src
[2])) {
585 int add_val
= nir_src_as_int(instr
->src
[2]);
588 else if (add_val
== -1)
592 nir_emit_ssbo_atomic(op
, instr
);
595 case nir_intrinsic_ssbo_atomic_imin
:
596 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
598 case nir_intrinsic_ssbo_atomic_umin
:
599 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
601 case nir_intrinsic_ssbo_atomic_imax
:
602 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
604 case nir_intrinsic_ssbo_atomic_umax
:
605 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
607 case nir_intrinsic_ssbo_atomic_and
:
608 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
610 case nir_intrinsic_ssbo_atomic_or
:
611 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
613 case nir_intrinsic_ssbo_atomic_xor
:
614 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
616 case nir_intrinsic_ssbo_atomic_exchange
:
617 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
619 case nir_intrinsic_ssbo_atomic_comp_swap
:
620 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
623 case nir_intrinsic_load_vertex_id
:
624 unreachable("should be lowered by lower_vertex_id()");
626 case nir_intrinsic_load_vertex_id_zero_base
:
627 case nir_intrinsic_load_base_vertex
:
628 case nir_intrinsic_load_instance_id
:
629 case nir_intrinsic_load_base_instance
:
630 case nir_intrinsic_load_draw_id
:
631 case nir_intrinsic_load_invocation_id
:
632 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
634 case nir_intrinsic_load_uniform
: {
635 /* Offsets are in bytes but they should always be multiples of 4 */
636 assert(nir_intrinsic_base(instr
) % 4 == 0);
638 dest
= get_nir_dest(instr
->dest
);
640 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
641 src
.type
= dest
.type
;
643 /* Uniforms don't actually have to be vec4 aligned. In the case that
644 * it isn't, we have to use a swizzle to shift things around. They
645 * do still have the std140 alignment requirement that vec2's have to
646 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
648 * The swizzle also works in the indirect case as the generator adds
649 * the swizzle to the offset for us.
651 const int type_size
= type_sz(src
.type
);
652 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
653 assert(shift
+ instr
->num_components
<= 4);
655 if (nir_src_is_const(instr
->src
[0])) {
656 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
657 /* Offsets are in bytes but they should always be multiples of 4 */
658 assert(load_offset
% 4 == 0);
660 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
661 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
662 unsigned offset
= load_offset
+ shift
* type_size
;
663 src
.offset
= ROUND_DOWN_TO(offset
, 16);
664 shift
= (offset
% 16) / type_size
;
665 assert(shift
+ instr
->num_components
<= 4);
666 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
668 emit(MOV(dest
, src
));
670 /* Uniform arrays are vec4 aligned, because of std140 alignment
675 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
677 /* MOV_INDIRECT is going to stomp the whole thing anyway */
678 dest
.writemask
= WRITEMASK_XYZW
;
680 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
681 indirect
, brw_imm_ud(instr
->const_index
[1]));
686 case nir_intrinsic_load_ubo
: {
689 dest
= get_nir_dest(instr
->dest
);
691 if (nir_src_is_const(instr
->src
[0])) {
692 /* The block index is a constant, so just emit the binding table entry
695 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
696 nir_src_as_uint(instr
->src
[0]);
697 surf_index
= brw_imm_ud(index
);
699 /* The block index is not a constant. Evaluate the index expression
700 * per-channel and add the base UBO index; we have to select a value
701 * from any live channel.
703 surf_index
= src_reg(this, glsl_type::uint_type
);
704 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
705 instr
->num_components
),
706 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
707 surf_index
= emit_uniformize(surf_index
);
711 if (nir_src_is_const(instr
->src
[1])) {
712 unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
713 offset_reg
= brw_imm_ud(load_offset
& ~15);
715 offset_reg
= src_reg(this, glsl_type::uint_type
);
716 emit(MOV(dst_reg(offset_reg
),
717 get_nir_src(instr
->src
[1], nir_type_uint32
, 1)));
720 src_reg packed_consts
;
721 if (nir_dest_bit_size(instr
->dest
) == 32) {
722 packed_consts
= src_reg(this, glsl_type::vec4_type
);
723 emit_pull_constant_load_reg(dst_reg(packed_consts
),
726 NULL
, NULL
/* before_block/inst */);
728 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
729 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
731 emit_pull_constant_load_reg(dst_reg(temp_float
),
732 surf_index
, offset_reg
, NULL
, NULL
);
733 if (offset_reg
.file
== IMM
)
736 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
737 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
738 surf_index
, offset_reg
, NULL
, NULL
);
740 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
741 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
744 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
745 if (nir_src_is_const(instr
->src
[1])) {
746 unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
747 unsigned type_size
= type_sz(dest
.type
);
748 packed_consts
.swizzle
+=
749 BRW_SWIZZLE4(load_offset
% 16 / type_size
,
750 load_offset
% 16 / type_size
,
751 load_offset
% 16 / type_size
,
752 load_offset
% 16 / type_size
);
755 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
760 case nir_intrinsic_memory_barrier
: {
761 const vec4_builder bld
=
762 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
763 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
764 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
, brw_vec8_grf(0, 0))
765 ->size_written
= 2 * REG_SIZE
;
769 case nir_intrinsic_shader_clock
: {
770 /* We cannot do anything if there is an event, so ignore it for now */
771 const src_reg shader_clock
= get_timestamp();
772 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
774 dest
= get_nir_dest(instr
->dest
, type
);
775 emit(MOV(dest
, shader_clock
));
780 unreachable("Unknown intrinsic");
785 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
788 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
789 dest
= get_nir_dest(instr
->dest
);
791 src_reg surface
= get_nir_ssbo_intrinsic_index(instr
);
792 src_reg offset
= get_nir_src(instr
->src
[1], 1);
794 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
795 data1
= get_nir_src(instr
->src
[2], 1);
797 if (op
== BRW_AOP_CMPWR
)
798 data2
= get_nir_src(instr
->src
[3], 1);
800 /* Emit the actual atomic operation operation */
801 const vec4_builder bld
=
802 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
804 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
806 1 /* dims */, 1 /* rsize */,
809 dest
.type
= atomic_result
.type
;
810 bld
.MOV(dest
, atomic_result
);
814 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
816 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
819 static enum brw_conditional_mod
820 brw_conditional_for_nir_comparison(nir_op op
)
826 return BRW_CONDITIONAL_L
;
831 return BRW_CONDITIONAL_GE
;
835 case nir_op_b32all_fequal2
:
836 case nir_op_b32all_iequal2
:
837 case nir_op_b32all_fequal3
:
838 case nir_op_b32all_iequal3
:
839 case nir_op_b32all_fequal4
:
840 case nir_op_b32all_iequal4
:
841 return BRW_CONDITIONAL_Z
;
845 case nir_op_b32any_fnequal2
:
846 case nir_op_b32any_inequal2
:
847 case nir_op_b32any_fnequal3
:
848 case nir_op_b32any_inequal3
:
849 case nir_op_b32any_fnequal4
:
850 case nir_op_b32any_inequal4
:
851 return BRW_CONDITIONAL_NZ
;
854 unreachable("not reached: bad operation for comparison");
859 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
860 enum brw_predicate
*predicate
)
862 if (!instr
->src
[0].src
.is_ssa
||
863 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
866 nir_alu_instr
*cmp_instr
=
867 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
869 switch (cmp_instr
->op
) {
870 case nir_op_b32any_fnequal2
:
871 case nir_op_b32any_inequal2
:
872 case nir_op_b32any_fnequal3
:
873 case nir_op_b32any_inequal3
:
874 case nir_op_b32any_fnequal4
:
875 case nir_op_b32any_inequal4
:
876 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
878 case nir_op_b32all_fequal2
:
879 case nir_op_b32all_iequal2
:
880 case nir_op_b32all_fequal3
:
881 case nir_op_b32all_iequal3
:
882 case nir_op_b32all_fequal4
:
883 case nir_op_b32all_iequal4
:
884 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
890 unsigned size_swizzle
=
891 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
894 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
895 for (unsigned i
= 0; i
< 2; i
++) {
896 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
897 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
898 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
899 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
900 unsigned base_swizzle
=
901 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
902 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
903 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
904 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
907 emit(CMP(dst_null_d(), op
[0], op
[1],
908 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
914 emit_find_msb_using_lzd(const vec4_builder
&bld
,
919 vec4_instruction
*inst
;
923 /* LZD of an absolute value source almost always does the right
924 * thing. There are two problem values:
926 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
927 * 0. However, findMSB(int(0x80000000)) == 30.
929 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
930 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
932 * For a value of zero or negative one, -1 will be returned.
934 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
935 * findMSB(-(1<<x)) should return x-1.
937 * For all negative number cases, including 0x80000000 and
938 * 0xffffffff, the correct value is obtained from LZD if instead of
939 * negating the (already negative) value the logical-not is used. A
940 * conditonal logical-not can be achieved in two instructions.
942 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
944 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
945 bld
.XOR(dst_reg(temp
), temp
, src
);
948 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
949 retype(temp
, BRW_REGISTER_TYPE_UD
));
951 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
952 * from the LSB side. Subtract the result from 31 to convert the MSB count
953 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
954 * which is exactly what findMSB() is supposed to return.
956 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
958 inst
->src
[0].negate
= true;
962 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
965 /* BDW PRM vol 15 - workarounds:
966 * DF->f format conversion for Align16 has wrong emask calculation when
967 * source is immediate.
969 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
970 src
.file
== BRW_IMMEDIATE_VALUE
) {
971 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
972 inst
->saturate
= saturate
;
978 case BRW_REGISTER_TYPE_D
:
979 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
981 case BRW_REGISTER_TYPE_UD
:
982 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
984 case BRW_REGISTER_TYPE_F
:
985 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
988 unreachable("Unknown conversion");
991 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
992 emit(MOV(temp
, src
));
993 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
994 emit(op
, temp2
, src_reg(temp
));
996 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
997 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
998 inst
->saturate
= saturate
;
1002 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1005 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1006 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1007 emit(MOV(dst_reg(tmp_src
), src
));
1008 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1009 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1010 inst
->saturate
= saturate
;
1014 * Try to use an immediate value for a source
1016 * In cases of flow control, constant propagation is sometimes unable to
1017 * determine that a register contains a constant value. To work around this,
1018 * try to emit a literal as one of the sources. If \c try_src0_also is set,
1019 * \c op[0] will also be tried for an immediate value.
1021 * If \c op[0] is modified, the operands will be exchanged so that \c op[1]
1022 * will always be the immediate value.
1024 * \return The index of the source that was modified, 0 or 1, if successful.
1027 * \param op - Operands to the instruction
1028 * \param try_src0_also - True if \c op[0] should also be a candidate for
1029 * getting an immediate value. This should only be set
1030 * for commutative operations.
1033 try_immediate_source(const nir_alu_instr
*instr
, src_reg
*op
,
1035 MAYBE_UNUSED
const gen_device_info
*devinfo
)
1039 if (nir_src_bit_size(instr
->src
[1].src
) == 32 &&
1040 nir_src_is_const(instr
->src
[1].src
)) {
1042 } else if (try_src0_also
&&
1043 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
1044 nir_src_is_const(instr
->src
[0].src
)) {
1050 const enum brw_reg_type old_type
= op
[idx
].type
;
1053 case BRW_REGISTER_TYPE_D
:
1054 case BRW_REGISTER_TYPE_UD
: {
1055 int first_comp
= -1;
1058 for (unsigned i
= 0; i
< NIR_MAX_VEC_COMPONENTS
; i
++) {
1059 if (nir_alu_instr_channel_used(instr
, idx
, i
)) {
1060 if (first_comp
< 0) {
1062 d
= nir_src_comp_as_int(instr
->src
[idx
].src
,
1063 instr
->src
[idx
].swizzle
[i
]);
1064 } else if (d
!= nir_src_comp_as_int(instr
->src
[idx
].src
,
1065 instr
->src
[idx
].swizzle
[i
])) {
1074 if (op
[idx
].negate
) {
1075 /* On Gen8+ a negation source modifier on a logical operation means
1076 * something different. Nothing should generate this, so assert that
1077 * it does not occur.
1079 assert(devinfo
->gen
< 8 || (instr
->op
!= nir_op_iand
&&
1080 instr
->op
!= nir_op_ior
&&
1081 instr
->op
!= nir_op_ixor
));
1085 op
[idx
] = retype(src_reg(brw_imm_d(d
)), old_type
);
1089 case BRW_REGISTER_TYPE_F
: {
1090 int first_comp
= -1;
1093 for (unsigned i
= 0; i
< NIR_MAX_VEC_COMPONENTS
; i
++) {
1094 if (nir_alu_instr_channel_used(instr
, idx
, i
)) {
1095 if (first_comp
< 0) {
1097 f
= nir_src_comp_as_float(instr
->src
[idx
].src
,
1098 instr
->src
[idx
].swizzle
[i
]);
1099 } else if (f
!= nir_src_comp_as_float(instr
->src
[idx
].src
,
1100 instr
->src
[idx
].swizzle
[i
])) {
1112 op
[idx
] = src_reg(brw_imm_f(f
));
1113 assert(op
[idx
].type
== old_type
);
1118 unreachable("Non-32bit type.");
1121 /* The instruction format only allows source 1 to be an immediate value.
1122 * If the immediate value was source 0, then the sources must be exchanged.
1125 src_reg tmp
= op
[0];
1134 vec4_visitor::fix_float_operands(src_reg op
[3])
1136 bool fixed
[3] = { false, false, false };
1138 for (unsigned i
= 0; i
< 3; i
++) {
1140 op
[i
] = fix_3src_operand(op
[i
]);
1145 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1147 vec4_instruction
*inst
;
1149 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1150 nir_dest_bit_size(instr
->dest
.dest
));
1151 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1152 dst
.writemask
= instr
->dest
.write_mask
;
1155 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1156 nir_alu_type src_type
= (nir_alu_type
)
1157 (nir_op_infos
[instr
->op
].input_types
[i
] |
1158 nir_src_bit_size(instr
->src
[i
].src
));
1159 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1160 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1161 op
[i
].abs
= instr
->src
[i
].abs
;
1162 op
[i
].negate
= instr
->src
[i
].negate
;
1165 switch (instr
->op
) {
1167 inst
= emit(MOV(dst
, op
[0]));
1168 inst
->saturate
= instr
->dest
.saturate
;
1174 unreachable("not reached: should be handled by lower_vec_to_movs()");
1178 inst
= emit(MOV(dst
, op
[0]));
1179 inst
->saturate
= instr
->dest
.saturate
;
1185 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1186 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1188 inst
= emit(MOV(dst
, op
[0]));
1194 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1198 inst
= emit(MOV(dst
, op
[0]));
1199 inst
->saturate
= true;
1204 op
[0].negate
= true;
1205 inst
= emit(MOV(dst
, op
[0]));
1206 if (instr
->op
== nir_op_fneg
)
1207 inst
->saturate
= instr
->dest
.saturate
;
1212 op
[0].negate
= false;
1214 inst
= emit(MOV(dst
, op
[0]));
1215 if (instr
->op
== nir_op_fabs
)
1216 inst
->saturate
= instr
->dest
.saturate
;
1220 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1223 try_immediate_source(instr
, op
, true, devinfo
);
1224 inst
= emit(ADD(dst
, op
[0], op
[1]));
1225 inst
->saturate
= instr
->dest
.saturate
;
1228 case nir_op_uadd_sat
:
1229 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1230 inst
= emit(ADD(dst
, op
[0], op
[1]));
1231 inst
->saturate
= true;
1235 try_immediate_source(instr
, op
, true, devinfo
);
1236 inst
= emit(MUL(dst
, op
[0], op
[1]));
1237 inst
->saturate
= instr
->dest
.saturate
;
1241 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1242 if (devinfo
->gen
< 8) {
1243 /* For integer multiplication, the MUL uses the low 16 bits of one of
1244 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1245 * accumulates in the contribution of the upper 16 bits of that
1246 * operand. If we can determine that one of the args is in the low
1247 * 16 bits, though, we can just emit a single MUL.
1249 if (nir_src_is_const(instr
->src
[0].src
) &&
1250 nir_alu_instr_src_read_mask(instr
, 0) == 1 &&
1251 nir_src_comp_as_uint(instr
->src
[0].src
, 0) < (1 << 16)) {
1252 if (devinfo
->gen
< 7)
1253 emit(MUL(dst
, op
[0], op
[1]));
1255 emit(MUL(dst
, op
[1], op
[0]));
1256 } else if (nir_src_is_const(instr
->src
[1].src
) &&
1257 nir_alu_instr_src_read_mask(instr
, 1) == 1 &&
1258 nir_src_comp_as_uint(instr
->src
[1].src
, 0) < (1 << 16)) {
1259 if (devinfo
->gen
< 7)
1260 emit(MUL(dst
, op
[1], op
[0]));
1262 emit(MUL(dst
, op
[0], op
[1]));
1264 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1266 emit(MUL(acc
, op
[0], op
[1]));
1267 emit(MACH(dst_null_d(), op
[0], op
[1]));
1268 emit(MOV(dst
, src_reg(acc
)));
1271 emit(MUL(dst
, op
[0], op
[1]));
1276 case nir_op_imul_high
:
1277 case nir_op_umul_high
: {
1278 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1279 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1281 if (devinfo
->gen
>= 8)
1282 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1284 emit(MUL(acc
, op
[0], op
[1]));
1286 emit(MACH(dst
, op
[0], op
[1]));
1291 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1292 inst
->saturate
= instr
->dest
.saturate
;
1296 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1297 inst
->saturate
= instr
->dest
.saturate
;
1301 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1302 inst
->saturate
= instr
->dest
.saturate
;
1306 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1307 inst
->saturate
= instr
->dest
.saturate
;
1311 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1312 inst
->saturate
= instr
->dest
.saturate
;
1317 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1318 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1323 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1324 * appears that our hardware just does the right thing for signed
1327 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1328 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1332 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1333 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1335 /* Math instructions don't support conditional mod */
1336 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1337 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1339 /* Now, we need to determine if signs of the sources are different.
1340 * When we XOR the sources, the top bit is 0 if they are the same and 1
1341 * if they are different. We can then use a conditional modifier to
1342 * turn that into a predicate. This leads us to an XOR.l instruction.
1344 * Technically, according to the PRM, you're not allowed to use .l on a
1345 * XOR instruction. However, emperical experiments and Curro's reading
1346 * of the simulator source both indicate that it's safe.
1348 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1349 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1350 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1351 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1353 /* If the result of the initial remainder operation is non-zero and the
1354 * two sources have different signs, add in a copy of op[1] to get the
1355 * final integer modulus value.
1357 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1358 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1363 unreachable("not reached: should be handled by ldexp_to_arith()");
1366 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1367 inst
->saturate
= instr
->dest
.saturate
;
1371 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1372 inst
->saturate
= instr
->dest
.saturate
;
1376 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1377 inst
->saturate
= instr
->dest
.saturate
;
1380 case nir_op_uadd_carry
: {
1381 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1382 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1384 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1385 emit(MOV(dst
, src_reg(acc
)));
1389 case nir_op_usub_borrow
: {
1390 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1391 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1393 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1394 emit(MOV(dst
, src_reg(acc
)));
1399 inst
= emit(RNDZ(dst
, op
[0]));
1400 inst
->saturate
= instr
->dest
.saturate
;
1403 case nir_op_fceil
: {
1404 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1406 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1407 instr
->src
[0].src
.ssa
->num_components
:
1408 instr
->src
[0].src
.reg
.reg
->num_components
);
1410 op
[0].negate
= !op
[0].negate
;
1411 emit(RNDD(dst_reg(tmp
), op
[0]));
1413 inst
= emit(MOV(dst
, tmp
));
1414 inst
->saturate
= instr
->dest
.saturate
;
1419 inst
= emit(RNDD(dst
, op
[0]));
1420 inst
->saturate
= instr
->dest
.saturate
;
1424 inst
= emit(FRC(dst
, op
[0]));
1425 inst
->saturate
= instr
->dest
.saturate
;
1428 case nir_op_fround_even
:
1429 inst
= emit(RNDE(dst
, op
[0]));
1430 inst
->saturate
= instr
->dest
.saturate
;
1433 case nir_op_fquantize2f16
: {
1434 /* See also vec4_visitor::emit_pack_half_2x16() */
1435 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1436 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1437 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1439 /* Check for denormal */
1440 src_reg abs_src0
= op
[0];
1441 abs_src0
.abs
= true;
1442 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1443 BRW_CONDITIONAL_L
));
1444 /* Get the appropriately signed zero */
1445 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1446 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1447 brw_imm_ud(0x80000000)));
1448 /* Do the actual F32 -> F16 -> F32 conversion */
1449 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1450 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1451 /* Select that or zero based on normal status */
1452 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1453 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1454 inst
->saturate
= instr
->dest
.saturate
;
1460 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1463 try_immediate_source(instr
, op
, true, devinfo
);
1464 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1465 inst
->saturate
= instr
->dest
.saturate
;
1470 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1473 try_immediate_source(instr
, op
, true, devinfo
);
1474 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1475 inst
->saturate
= instr
->dest
.saturate
;
1479 case nir_op_fddx_coarse
:
1480 case nir_op_fddx_fine
:
1482 case nir_op_fddy_coarse
:
1483 case nir_op_fddy_fine
:
1484 unreachable("derivatives are not valid in vertex shaders");
1492 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1497 case nir_op_fne32
: {
1498 enum brw_conditional_mod conditional_mod
=
1499 brw_conditional_for_nir_comparison(instr
->op
);
1501 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1502 /* If the order of the sources is changed due to an immediate value,
1503 * then the condition must also be changed.
1505 if (try_immediate_source(instr
, op
, true, devinfo
) == 0)
1506 conditional_mod
= brw_swap_cmod(conditional_mod
);
1508 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1510 /* Produce a 32-bit boolean result from the DF comparison by selecting
1511 * only the low 32-bit in each DF produced. Do this in a temporary
1512 * so we can then move from there to the result using align16 again
1513 * to honor the original writemask.
1515 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1516 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1517 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1518 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1519 emit(MOV(dst
, src_reg(result
)));
1524 case nir_op_b32all_iequal2
:
1525 case nir_op_b32all_iequal3
:
1526 case nir_op_b32all_iequal4
:
1527 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1529 case nir_op_b32all_fequal2
:
1530 case nir_op_b32all_fequal3
:
1531 case nir_op_b32all_fequal4
: {
1533 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1535 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1536 brw_conditional_for_nir_comparison(instr
->op
)));
1537 emit(MOV(dst
, brw_imm_d(0)));
1538 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1539 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1543 case nir_op_b32any_inequal2
:
1544 case nir_op_b32any_inequal3
:
1545 case nir_op_b32any_inequal4
:
1546 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1548 case nir_op_b32any_fnequal2
:
1549 case nir_op_b32any_fnequal3
:
1550 case nir_op_b32any_fnequal4
: {
1552 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1554 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1555 brw_conditional_for_nir_comparison(instr
->op
)));
1557 emit(MOV(dst
, brw_imm_d(0)));
1558 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1559 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1564 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1565 if (devinfo
->gen
>= 8) {
1566 op
[0] = resolve_source_modifiers(op
[0]);
1568 emit(NOT(dst
, op
[0]));
1572 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1573 if (devinfo
->gen
>= 8) {
1574 op
[0] = resolve_source_modifiers(op
[0]);
1575 op
[1] = resolve_source_modifiers(op
[1]);
1577 try_immediate_source(instr
, op
, true, devinfo
);
1578 emit(XOR(dst
, op
[0], op
[1]));
1582 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1583 if (devinfo
->gen
>= 8) {
1584 op
[0] = resolve_source_modifiers(op
[0]);
1585 op
[1] = resolve_source_modifiers(op
[1]);
1587 try_immediate_source(instr
, op
, true, devinfo
);
1588 emit(OR(dst
, op
[0], op
[1]));
1592 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1593 if (devinfo
->gen
>= 8) {
1594 op
[0] = resolve_source_modifiers(op
[0]);
1595 op
[1] = resolve_source_modifiers(op
[1]);
1597 try_immediate_source(instr
, op
, true, devinfo
);
1598 emit(AND(dst
, op
[0], op
[1]));
1604 if (nir_dest_bit_size(instr
->dest
.dest
) > 32) {
1605 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
1606 emit_conversion_to_double(dst
, negate(op
[0]), false);
1608 emit(MOV(dst
, negate(op
[0])));
1613 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1614 /* We use a MOV with conditional_mod to check if the provided value is
1615 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1616 * source modifier on the source operand to trigger this, as source
1617 * modifiers don't affect the result of the testing against 0.0.
1619 src_reg value
= op
[0];
1621 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1622 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1624 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1625 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1626 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1627 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1629 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1634 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1637 case nir_op_fnoise1_1
:
1638 case nir_op_fnoise1_2
:
1639 case nir_op_fnoise1_3
:
1640 case nir_op_fnoise1_4
:
1641 case nir_op_fnoise2_1
:
1642 case nir_op_fnoise2_2
:
1643 case nir_op_fnoise2_3
:
1644 case nir_op_fnoise2_4
:
1645 case nir_op_fnoise3_1
:
1646 case nir_op_fnoise3_2
:
1647 case nir_op_fnoise3_3
:
1648 case nir_op_fnoise3_4
:
1649 case nir_op_fnoise4_1
:
1650 case nir_op_fnoise4_2
:
1651 case nir_op_fnoise4_3
:
1652 case nir_op_fnoise4_4
:
1653 unreachable("not reached: should be handled by lower_noise");
1655 case nir_op_unpack_half_2x16_split_x
:
1656 case nir_op_unpack_half_2x16_split_y
:
1657 case nir_op_pack_half_2x16_split
:
1658 unreachable("not reached: should not occur in vertex shader");
1660 case nir_op_unpack_snorm_2x16
:
1661 case nir_op_unpack_unorm_2x16
:
1662 case nir_op_pack_snorm_2x16
:
1663 case nir_op_pack_unorm_2x16
:
1664 unreachable("not reached: should be handled by lower_packing_builtins");
1666 case nir_op_pack_uvec4_to_uint
:
1667 unreachable("not reached");
1669 case nir_op_pack_uvec2_to_uint
: {
1670 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1671 tmp1
.writemask
= WRITEMASK_X
;
1672 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1673 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1675 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1676 tmp2
.writemask
= WRITEMASK_X
;
1677 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1678 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1680 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1684 case nir_op_pack_64_2x32_split
: {
1685 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1686 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1687 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1688 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1689 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1690 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1691 emit(MOV(dst
, src_reg(result
)));
1695 case nir_op_unpack_64_2x32_split_x
:
1696 case nir_op_unpack_64_2x32_split_y
: {
1697 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1698 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1699 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1700 emit(MOV(tmp
, op
[0]));
1701 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1702 emit(oper
, tmp2
, src_reg(tmp
));
1703 emit(MOV(dst
, src_reg(tmp2
)));
1707 case nir_op_unpack_half_2x16
:
1708 /* As NIR does not guarantee that we have a correct swizzle outside the
1709 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1710 * uses the source operand in an operation with WRITEMASK_Y while our
1711 * source operand has only size 1, it accessed incorrect data producing
1712 * regressions in Piglit. We repeat the swizzle of the first component on the
1713 * rest of components to avoid regressions. In the vec4_visitor IR code path
1714 * this is not needed because the operand has already the correct swizzle.
1716 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1717 emit_unpack_half_2x16(dst
, op
[0]);
1720 case nir_op_pack_half_2x16
:
1721 emit_pack_half_2x16(dst
, op
[0]);
1724 case nir_op_unpack_unorm_4x8
:
1725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1726 emit_unpack_unorm_4x8(dst
, op
[0]);
1729 case nir_op_pack_unorm_4x8
:
1730 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1731 emit_pack_unorm_4x8(dst
, op
[0]);
1734 case nir_op_unpack_snorm_4x8
:
1735 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1736 emit_unpack_snorm_4x8(dst
, op
[0]);
1739 case nir_op_pack_snorm_4x8
:
1740 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1741 emit_pack_snorm_4x8(dst
, op
[0]);
1744 case nir_op_bitfield_reverse
:
1745 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1746 emit(BFREV(dst
, op
[0]));
1749 case nir_op_bit_count
:
1750 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1751 emit(CBIT(dst
, op
[0]));
1754 case nir_op_ufind_msb
:
1755 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1756 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1759 case nir_op_ifind_msb
: {
1760 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1761 vec4_builder bld
= vec4_builder(this).at_end();
1764 if (devinfo
->gen
< 7) {
1765 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1767 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1769 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1770 * count from the LSB side. If FBH didn't return an error
1771 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1772 * count into an LSB count.
1774 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1776 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1777 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1778 inst
->src
[0].negate
= true;
1783 case nir_op_find_lsb
: {
1784 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1785 vec4_builder bld
= vec4_builder(this).at_end();
1787 if (devinfo
->gen
< 7) {
1788 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1790 /* (x & -x) generates a value that consists of only the LSB of x.
1791 * For all powers of 2, findMSB(y) == findLSB(y).
1793 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1794 src_reg negated_src
= src
;
1796 /* One must be negated, and the other must be non-negated. It
1797 * doesn't matter which is which.
1799 negated_src
.negate
= true;
1802 bld
.AND(temp
, src
, negated_src
);
1803 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1805 bld
.FBL(dst
, op
[0]);
1810 case nir_op_ubitfield_extract
:
1811 case nir_op_ibitfield_extract
:
1812 unreachable("should have been lowered");
1815 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1816 op
[0] = fix_3src_operand(op
[0]);
1817 op
[1] = fix_3src_operand(op
[1]);
1818 op
[2] = fix_3src_operand(op
[2]);
1820 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1824 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1825 emit(BFI1(dst
, op
[0], op
[1]));
1829 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1830 op
[0] = fix_3src_operand(op
[0]);
1831 op
[1] = fix_3src_operand(op
[1]);
1832 op
[2] = fix_3src_operand(op
[2]);
1834 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1837 case nir_op_bitfield_insert
:
1838 unreachable("not reached: should have been lowered");
1841 assert(!instr
->dest
.saturate
);
1843 /* Straightforward since the source can be assumed to be either
1844 * strictly >= 0 or strictly <= 0 depending on the setting of the
1847 inst
= emit(MOV(dst
, op
[0]));
1848 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1850 inst
= (op
[0].negate
)
1851 ? emit(MOV(dst
, brw_imm_f(-1.0f
)))
1852 : emit(MOV(dst
, brw_imm_f(1.0f
)));
1853 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1854 } else if (type_sz(op
[0].type
) < 8) {
1855 /* AND(val, 0x80000000) gives the sign bit.
1857 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1860 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1862 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1863 dst
.type
= BRW_REGISTER_TYPE_UD
;
1864 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1866 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1867 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1868 dst
.type
= BRW_REGISTER_TYPE_F
;
1870 /* For doubles we do the same but we need to consider:
1872 * - We use a MOV with conditional_mod instead of a CMP so that we can
1873 * skip loading a 0.0 immediate. We use a source modifier on the
1874 * source of the MOV so that we flush denormalized values to 0.
1875 * Since we want to compare against 0, this won't alter the result.
1876 * - We need to extract the high 32-bit of each DF where the sign
1878 * - We need to produce a DF result.
1881 /* Check for zero */
1882 src_reg value
= op
[0];
1884 inst
= emit(MOV(dst_null_df(), value
));
1885 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1887 /* AND each high 32-bit channel with 0x80000000u */
1888 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1889 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1890 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1892 /* Add 1.0 to each channel, predicated to skip the cases where the
1893 * channel's value was 0
1895 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1896 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1898 /* Now convert the result from float to double */
1899 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1900 BRW_REGISTER_TYPE_F
),
1906 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1907 try_immediate_source(instr
, op
, false, devinfo
);
1908 emit(SHL(dst
, op
[0], op
[1]));
1912 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1913 try_immediate_source(instr
, op
, false, devinfo
);
1914 emit(ASR(dst
, op
[0], op
[1]));
1918 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1919 try_immediate_source(instr
, op
, false, devinfo
);
1920 emit(SHR(dst
, op
[0], op
[1]));
1924 if (type_sz(dst
.type
) == 8) {
1925 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1926 emit(MUL(mul_dst
, op
[1], op
[0]));
1927 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1928 inst
->saturate
= instr
->dest
.saturate
;
1930 fix_float_operands(op
);
1931 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1932 inst
->saturate
= instr
->dest
.saturate
;
1937 fix_float_operands(op
);
1938 inst
= emit(LRP(dst
, op
[2], op
[1], op
[0]));
1939 inst
->saturate
= instr
->dest
.saturate
;
1942 case nir_op_b32csel
:
1943 enum brw_predicate predicate
;
1944 if (!optimize_predicate(instr
, &predicate
)) {
1945 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1946 switch (dst
.writemask
) {
1948 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1951 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1954 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1957 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1960 predicate
= BRW_PREDICATE_NORMAL
;
1964 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1965 inst
->predicate
= predicate
;
1968 case nir_op_fdot_replicated2
:
1969 try_immediate_source(instr
, op
, true, devinfo
);
1970 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1971 inst
->saturate
= instr
->dest
.saturate
;
1974 case nir_op_fdot_replicated3
:
1975 try_immediate_source(instr
, op
, true, devinfo
);
1976 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1977 inst
->saturate
= instr
->dest
.saturate
;
1980 case nir_op_fdot_replicated4
:
1981 try_immediate_source(instr
, op
, true, devinfo
);
1982 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1983 inst
->saturate
= instr
->dest
.saturate
;
1986 case nir_op_fdph_replicated
:
1987 try_immediate_source(instr
, op
, true, devinfo
);
1988 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1989 inst
->saturate
= instr
->dest
.saturate
;
1993 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1996 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
2000 unreachable("not reached: should be handled by ir_sub_to_add_neg");
2003 unreachable("Unimplemented ALU operation");
2006 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2007 * to sign extend the low bit to 0/~0
2009 if (devinfo
->gen
<= 5 &&
2010 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2011 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2012 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2013 masked
.writemask
= dst
.writemask
;
2014 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2015 src_reg masked_neg
= src_reg(masked
);
2016 masked_neg
.negate
= true;
2017 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2022 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2024 switch (instr
->type
) {
2025 case nir_jump_break
:
2026 emit(BRW_OPCODE_BREAK
);
2029 case nir_jump_continue
:
2030 emit(BRW_OPCODE_CONTINUE
);
2033 case nir_jump_return
:
2036 unreachable("unknown jump");
2040 static enum ir_texture_opcode
2041 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2043 enum ir_texture_opcode op
;
2046 case nir_texop_lod
: op
= ir_lod
; break;
2047 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2048 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2049 case nir_texop_tex
: op
= ir_tex
; break;
2050 case nir_texop_tg4
: op
= ir_tg4
; break;
2051 case nir_texop_txb
: op
= ir_txb
; break;
2052 case nir_texop_txd
: op
= ir_txd
; break;
2053 case nir_texop_txf
: op
= ir_txf
; break;
2054 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2055 case nir_texop_txl
: op
= ir_txl
; break;
2056 case nir_texop_txs
: op
= ir_txs
; break;
2057 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2059 unreachable("unknown texture opcode");
2065 static const glsl_type
*
2066 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2067 unsigned components
)
2069 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2074 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2076 unsigned texture
= instr
->texture_index
;
2077 unsigned sampler
= instr
->sampler_index
;
2078 src_reg texture_reg
= brw_imm_ud(texture
);
2079 src_reg sampler_reg
= brw_imm_ud(sampler
);
2081 const glsl_type
*coord_type
= NULL
;
2082 src_reg shadow_comparator
;
2083 src_reg offset_value
;
2085 src_reg sample_index
;
2088 const glsl_type
*dest_type
=
2089 glsl_type_for_nir_alu_type(instr
->dest_type
,
2090 nir_tex_instr_dest_size(instr
));
2091 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2093 /* The hardware requires a LOD for buffer textures */
2094 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2097 /* Load the texture operation sources */
2098 uint32_t constant_offset
= 0;
2099 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2100 switch (instr
->src
[i
].src_type
) {
2101 case nir_tex_src_comparator
:
2102 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2103 BRW_REGISTER_TYPE_F
, 1);
2106 case nir_tex_src_coord
: {
2107 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2109 switch (instr
->op
) {
2111 case nir_texop_txf_ms
:
2112 case nir_texop_samples_identical
:
2113 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2115 coord_type
= glsl_type::ivec(src_size
);
2119 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2121 coord_type
= glsl_type::vec(src_size
);
2127 case nir_tex_src_ddx
:
2128 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2129 nir_tex_instr_src_size(instr
, i
));
2132 case nir_tex_src_ddy
:
2133 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2134 nir_tex_instr_src_size(instr
, i
));
2137 case nir_tex_src_lod
:
2138 switch (instr
->op
) {
2141 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2145 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2150 case nir_tex_src_ms_index
: {
2151 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2155 case nir_tex_src_offset
:
2156 if (!brw_texture_offset(instr
, i
, &constant_offset
)) {
2158 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2162 case nir_tex_src_texture_offset
: {
2163 /* Emit code to evaluate the actual indexing expression */
2164 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2165 src_reg
temp(this, glsl_type::uint_type
);
2166 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2167 texture_reg
= emit_uniformize(temp
);
2171 case nir_tex_src_sampler_offset
: {
2172 /* Emit code to evaluate the actual indexing expression */
2173 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2174 src_reg
temp(this, glsl_type::uint_type
);
2175 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2176 sampler_reg
= emit_uniformize(temp
);
2180 case nir_tex_src_projector
:
2181 unreachable("Should be lowered by do_lower_texture_projection");
2183 case nir_tex_src_bias
:
2184 unreachable("LOD bias is not valid for vertex shaders.\n");
2187 unreachable("unknown texture source");
2191 if (instr
->op
== nir_texop_txf_ms
||
2192 instr
->op
== nir_texop_samples_identical
) {
2193 assert(coord_type
!= NULL
);
2194 if (devinfo
->gen
>= 7 &&
2195 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2196 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2198 mcs
= brw_imm_ud(0u);
2202 /* Stuff the channel select bits in the top of the texture offset */
2203 if (instr
->op
== nir_texop_tg4
) {
2204 if (instr
->component
== 1 &&
2205 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2206 /* gather4 sampler is broken for green channel on RG32F --
2207 * we must ask for blue instead.
2209 constant_offset
|= 2 << 16;
2211 constant_offset
|= instr
->component
<< 16;
2215 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2217 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2219 lod
, lod2
, sample_index
,
2220 constant_offset
, offset_value
, mcs
,
2221 texture
, texture_reg
, sampler_reg
);
2225 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2227 nir_ssa_values
[instr
->def
.index
] =
2228 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2231 /* SIMD4x2 64bit data is stored in register space like this:
2233 * r0.0:DF x0 y0 z0 w0
2234 * r1.0:DF x1 y1 z1 w1
2236 * When we need to write data such as this to memory using 32-bit write
2237 * messages we need to shuffle it in this fashion:
2239 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2240 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2242 * We need to do the inverse operation when we read using 32-bit messages,
2243 * which we can do by applying the same exact shuffling on the 64-bit data
2244 * read, only that because the data for each vertex is positioned differently
2245 * we need to apply different channel enables.
2247 * This function takes 64bit data and shuffles it as explained above.
2249 * The @for_write parameter is used to specify if the shuffling is being done
2250 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2251 * write message (for_write = true), or instead we are doing the inverse
2252 * operation and we have just read 64-bit data using a 32-bit messages that we
2253 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2255 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2256 * otherwise the instructions are emitted normally at the end. The function
2257 * returns the last instruction inserted.
2259 * Notice that @src and @dst cannot be the same register.
2262 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2263 bblock_t
*block
, vec4_instruction
*ref
)
2265 assert(type_sz(src
.type
) == 8);
2266 assert(type_sz(dst
.type
) == 8);
2267 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2268 assert(!ref
== !block
);
2270 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2271 vec4_builder(this).at(block
, ref
->next
);
2273 /* Resolve swizzle in src */
2274 vec4_instruction
*inst
;
2275 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2276 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2277 inst
= bld
.MOV(data
, src
);
2278 src
= src_reg(data
);
2281 /* dst+0.XY = src+0.XY */
2282 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2284 /* dst+0.ZW = src+1.XY */
2285 inst
= bld
.group(4, for_write
? 1 : 0)
2286 .MOV(writemask(dst
, WRITEMASK_ZW
),
2287 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2289 /* dst+1.XY = src+0.ZW */
2290 inst
= bld
.group(4, for_write
? 0 : 1)
2291 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2292 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2294 /* dst+1.ZW = src+1.ZW */
2295 inst
= bld
.group(4, 1)
2296 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2297 byte_offset(src
, REG_SIZE
));