2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 nir_setup_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr
*instr
)
55 switch (instr
->intrinsic
) {
56 case nir_intrinsic_load_vertex_id
:
57 unreachable("should be lowered by lower_vertex_id().");
59 case nir_intrinsic_load_vertex_id_zero_base
:
60 reg
= &nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
61 if (reg
->file
== BAD_FILE
)
62 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
65 case nir_intrinsic_load_base_vertex
:
66 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
67 if (reg
->file
== BAD_FILE
)
68 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_VERTEX
);
71 case nir_intrinsic_load_instance_id
:
72 reg
= &nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
73 if (reg
->file
== BAD_FILE
)
74 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_INSTANCE_ID
);
77 case nir_intrinsic_load_base_instance
:
78 reg
= &nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
79 if (reg
->file
== BAD_FILE
)
80 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
83 case nir_intrinsic_load_draw_id
:
84 reg
= &nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
85 if (reg
->file
== BAD_FILE
)
86 *reg
= *make_reg_for_system_value(SYSTEM_VALUE_DRAW_ID
);
95 setup_system_values_block(nir_block
*block
, vec4_visitor
*v
)
97 nir_foreach_instr(instr
, block
) {
98 if (instr
->type
!= nir_instr_type_intrinsic
)
101 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
102 v
->nir_setup_system_value_intrinsic(intrin
);
109 vec4_visitor::nir_setup_system_values()
111 nir_system_values
= ralloc_array(mem_ctx
, dst_reg
, SYSTEM_VALUE_MAX
);
112 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
113 nir_system_values
[i
] = dst_reg();
116 nir_foreach_function(function
, nir
) {
117 assert(strcmp(function
->name
, "main") == 0);
118 assert(function
->impl
);
119 nir_foreach_block(block
, function
->impl
) {
120 setup_system_values_block(block
, this);
126 vec4_visitor::nir_setup_uniforms()
128 uniforms
= nir
->num_uniforms
/ 16;
132 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
134 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
135 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
136 nir_locals
[i
] = dst_reg();
139 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
140 unsigned array_elems
=
141 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
142 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
143 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
145 if (reg
->bit_size
== 64)
146 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
149 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
151 nir_emit_cf_list(&impl
->body
);
155 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
157 exec_list_validate(list
);
158 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
159 switch (node
->type
) {
161 nir_emit_if(nir_cf_node_as_if(node
));
164 case nir_cf_node_loop
:
165 nir_emit_loop(nir_cf_node_as_loop(node
));
168 case nir_cf_node_block
:
169 nir_emit_block(nir_cf_node_as_block(node
));
173 unreachable("Invalid CFG node block");
179 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
181 /* First, put the condition in f0 */
182 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
183 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
184 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
186 /* We can just predicate based on the X channel, as the condition only
187 * goes on its own line */
188 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
190 nir_emit_cf_list(&if_stmt
->then_list
);
192 /* note: if the else is empty, dead CF elimination will remove it */
193 emit(BRW_OPCODE_ELSE
);
195 nir_emit_cf_list(&if_stmt
->else_list
);
197 emit(BRW_OPCODE_ENDIF
);
201 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
205 nir_emit_cf_list(&loop
->body
);
207 emit(BRW_OPCODE_WHILE
);
211 vec4_visitor::nir_emit_block(nir_block
*block
)
213 nir_foreach_instr(instr
, block
) {
214 nir_emit_instr(instr
);
219 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
223 switch (instr
->type
) {
224 case nir_instr_type_load_const
:
225 nir_emit_load_const(nir_instr_as_load_const(instr
));
228 case nir_instr_type_intrinsic
:
229 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
232 case nir_instr_type_alu
:
233 nir_emit_alu(nir_instr_as_alu(instr
));
236 case nir_instr_type_jump
:
237 nir_emit_jump(nir_instr_as_jump(instr
));
240 case nir_instr_type_tex
:
241 nir_emit_texture(nir_instr_as_tex(instr
));
244 case nir_instr_type_ssa_undef
:
245 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
249 fprintf(stderr
, "VS instruction not yet implemented by NIR->vec4\n");
255 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
256 unsigned base_offset
, nir_src
*indirect
)
260 reg
= v
->nir_locals
[nir_reg
->index
];
261 if (nir_reg
->bit_size
== 64)
262 reg
.type
= BRW_REGISTER_TYPE_DF
;
263 reg
= offset(reg
, 8, base_offset
);
266 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
274 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
278 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
279 if (dest
.ssa
.bit_size
== 64)
280 dst
.type
= BRW_REGISTER_TYPE_DF
;
281 nir_ssa_values
[dest
.ssa
.index
] = dst
;
284 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
290 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
292 return retype(get_nir_dest(dest
), type
);
296 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
298 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
302 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
303 unsigned num_components
)
308 assert(src
.ssa
!= NULL
);
309 reg
= nir_ssa_values
[src
.ssa
->index
];
312 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
316 reg
= retype(reg
, type
);
318 src_reg reg_as_src
= src_reg(reg
);
319 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
324 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
325 unsigned num_components
)
327 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
332 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
334 /* if type is not specified, default to signed int */
335 return get_nir_src(src
, nir_type_int32
, num_components
);
339 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
341 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
342 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
345 /* The only constant offset we should find is 0. brw_nir.c's
346 * add_const_offset_to_base() will fold other constant offsets
347 * into instr->const_index[0].
349 assert(const_value
->u32
[0] == 0);
353 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
357 setup_imm_df(const vec4_builder
&bld
, double v
)
359 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
360 assert(devinfo
->gen
>= 7);
362 if (devinfo
->gen
>= 8)
363 return brw_imm_df(v
);
365 /* gen7.5 does not support DF immediates straighforward but the DIM
366 * instruction allows to set the 64-bit immediate value.
368 if (devinfo
->is_haswell
) {
369 const vec4_builder ubld
= bld
.exec_all();
370 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
371 ubld
.DIM(dst
, brw_imm_df(v
));
372 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
375 /* gen7 does not support DF immediates */
386 /* Write the low 32-bit of the constant to the X:UD channel and the
387 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
388 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
389 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
390 * XXXX so any access to the VGRF only reads the constant data in these
393 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
394 for (unsigned n
= 0; n
< 2; n
++) {
395 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
396 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
397 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
400 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
404 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
408 if (instr
->def
.bit_size
== 64) {
409 reg
= dst_reg(VGRF
, alloc
.allocate(2));
410 reg
.type
= BRW_REGISTER_TYPE_DF
;
412 reg
= dst_reg(VGRF
, alloc
.allocate(1));
413 reg
.type
= BRW_REGISTER_TYPE_D
;
416 const vec4_builder ibld
= vec4_builder(this).at_end();
417 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
419 /* @FIXME: consider emitting vector operations to save some MOVs in
420 * cases where the components are representable in 8 bits.
421 * For now, we emit a MOV for each distinct value.
423 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
424 unsigned writemask
= 1 << i
;
426 if ((remaining
& writemask
) == 0)
429 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
430 if ((instr
->def
.bit_size
== 32 &&
431 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
432 (instr
->def
.bit_size
== 64 &&
433 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
438 reg
.writemask
= writemask
;
439 if (instr
->def
.bit_size
== 64) {
440 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
442 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
445 remaining
&= ~writemask
;
448 /* Set final writemask */
449 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
451 nir_ssa_values
[instr
->def
.index
] = reg
;
455 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
460 switch (instr
->intrinsic
) {
462 case nir_intrinsic_load_input
: {
463 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
465 /* We set EmitNoIndirectInput for VS */
466 assert(const_offset
);
468 dest
= get_nir_dest(instr
->dest
);
469 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
471 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
472 glsl_type::uvec4_type
);
473 src
= retype(src
, dest
.type
);
475 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
477 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
478 src
.swizzle
= BRW_SWIZZLE_XYZW
;
479 shuffle_64bit_data(tmp
, src
, false);
480 emit(MOV(dest
, src_reg(tmp
)));
482 /* Swizzle source based on component layout qualifier */
483 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
484 emit(MOV(dest
, src
));
489 case nir_intrinsic_store_output
: {
490 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
491 assert(const_offset
);
493 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
495 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
498 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
499 instr
->num_components
);
500 data
= src_reg(this, glsl_type::dvec4_type
);
501 shuffle_64bit_data(dst_reg(data
), src
, true);
502 src
= retype(data
, BRW_REGISTER_TYPE_F
);
504 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
505 instr
->num_components
);
508 unsigned c
= nir_intrinsic_component(instr
);
509 output_reg
[varying
][c
] = dst_reg(src
);
510 output_num_components
[varying
][c
] = instr
->num_components
;
512 unsigned num_components
= instr
->num_components
;
516 output_reg
[varying
][c
] = dst_reg(src
);
517 output_num_components
[varying
][c
] = MIN2(4, num_components
);
519 if (is_64bit
&& num_components
> 4) {
520 assert(num_components
<= 8);
521 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
522 output_num_components
[varying
+ 1][c
] = num_components
- 4;
527 case nir_intrinsic_get_buffer_size
: {
528 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
529 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
531 const unsigned index
=
532 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
533 dst_reg result_dst
= get_nir_dest(instr
->dest
);
534 vec4_instruction
*inst
= new(mem_ctx
)
535 vec4_instruction(VS_OPCODE_GET_BUFFER_SIZE
, result_dst
);
538 inst
->mlen
= 1; /* always at least one */
539 inst
->src
[1] = brw_imm_ud(index
);
541 /* MRF for the first parameter */
542 src_reg lod
= brw_imm_d(0);
543 int param_base
= inst
->base_mrf
;
544 int writemask
= WRITEMASK_X
;
545 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
549 brw_mark_surface_used(&prog_data
->base
, index
);
553 case nir_intrinsic_store_ssbo
: {
554 assert(devinfo
->gen
>= 7);
558 nir_const_value
*const_uniform_block
=
559 nir_src_as_const_value(instr
->src
[1]);
560 if (const_uniform_block
) {
561 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
562 const_uniform_block
->u32
[0];
563 surf_index
= brw_imm_ud(index
);
564 brw_mark_surface_used(&prog_data
->base
, index
);
566 surf_index
= src_reg(this, glsl_type::uint_type
);
567 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
568 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
569 surf_index
= emit_uniformize(surf_index
);
571 brw_mark_surface_used(&prog_data
->base
,
572 prog_data
->base
.binding_table
.ssbo_start
+
573 nir
->info
.num_ssbos
- 1);
578 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
580 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
582 offset_reg
= get_nir_src(instr
->src
[2], 1);
586 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
589 unsigned write_mask
= instr
->const_index
[0];
591 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
592 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
593 * typed and untyped messages and across hardware platforms, the
594 * current implementation of the untyped messages will transparently convert
595 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
596 * and enabling only channel X on the SEND instruction.
598 * The above, works well for full vector writes, but not for partial writes
599 * where we want to write some channels and not others, like when we have
600 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
601 * quite restrictive with regards to the channel enables we can configure in
602 * the message descriptor (not all combinations are allowed) we cannot simply
603 * implement these scenarios with a single message while keeping the
604 * aforementioned symmetry in the implementation. For now we de decided that
605 * it is better to keep the symmetry to reduce complexity, so in situations
606 * such as the one described we end up emitting two untyped write messages
607 * (one for xy and another for w).
609 * The code below packs consecutive channels into a single write message,
610 * detects gaps in the vector write and if needed, sends a second message
611 * with the remaining channels. If in the future we decide that we want to
612 * emit a single message at the expense of losing the symmetry in the
613 * implementation we can:
615 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
616 * message payload. In this mode we can write up to 8 offsets and dwords
617 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
618 * and select which of the 8 channels carry data to write by setting the
619 * appropriate writemask in the dst register of the SEND instruction.
620 * It would require to write a new generator opcode specifically for
621 * IvyBridge since we would need to prepare a SIMD8 payload that could
622 * use any channel, not just X.
624 * 2) For Haswell+: Simply send a single write message but set the writemask
625 * on the dst of the SEND instruction to select the channels we want to
626 * write. It would require to modify the current messages to receive
627 * and honor the writemask provided.
629 const vec4_builder bld
= vec4_builder(this).at_end()
630 .annotate(current_annotation
, base_ir
);
632 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
633 if (type_slots
== 2) {
634 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
635 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
636 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
639 uint8_t swizzle
[4] = { 0, 0, 0, 0};
640 int num_channels
= 0;
641 unsigned skipped_channels
= 0;
642 int num_components
= instr
->num_components
;
643 for (int i
= 0; i
< num_components
; i
++) {
644 /* Read components Z/W of a dvec from the appropriate place. We will
645 * also have to adjust the swizzle (we do that with the '% 4' below)
647 if (i
== 2 && type_slots
== 2)
648 val_reg
= byte_offset(val_reg
, REG_SIZE
);
650 /* Check if this channel needs to be written. If so, record the
651 * channel we need to take the data from in the swizzle array
653 int component_mask
= 1 << i
;
654 int write_test
= write_mask
& component_mask
;
656 /* If we are writing doubles we have to write 2 channels worth of
657 * of data (64 bits) for each double component.
659 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
661 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
664 /* If we don't have to write this channel it means we have a gap in the
665 * vector, so write the channels we accumulated until now, if any. Do
666 * the same if this was the last component in the vector, if we have
667 * enough channels for a full vec4 write or if we have processed
668 * components XY of a dvec (since components ZW are not in the same
671 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
672 (i
== 1 && type_slots
== 2)) {
673 if (num_channels
> 0) {
674 /* We have channels to write, so update the offset we need to
675 * write at to skip the channels we skipped, if any.
677 if (skipped_channels
> 0) {
678 if (offset_reg
.file
== IMM
) {
679 offset_reg
.ud
+= 4 * skipped_channels
;
681 emit(ADD(dst_reg(offset_reg
), offset_reg
,
682 brw_imm_ud(4 * skipped_channels
)));
686 /* Swizzle the data register so we take the data from the channels
687 * we need to write and send the write message. This will write
688 * num_channels consecutive dwords starting at offset.
691 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
692 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
693 1 /* dims */, num_channels
/* size */,
696 /* If we have to do a second write we will have to update the
697 * offset so that we jump over the channels we have just written
700 skipped_channels
= num_channels
;
702 /* Restart the count for the next write message */
706 /* If we didn't write the channel, increase skipped count */
708 skipped_channels
+= type_slots
;
715 case nir_intrinsic_load_ssbo
: {
716 assert(devinfo
->gen
>= 7);
718 nir_const_value
*const_uniform_block
=
719 nir_src_as_const_value(instr
->src
[0]);
722 if (const_uniform_block
) {
723 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
724 const_uniform_block
->u32
[0];
725 surf_index
= brw_imm_ud(index
);
727 brw_mark_surface_used(&prog_data
->base
, index
);
729 surf_index
= src_reg(this, glsl_type::uint_type
);
730 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
731 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
732 surf_index
= emit_uniformize(surf_index
);
734 /* Assume this may touch any UBO. It would be nice to provide
735 * a tighter bound, but the array information is already lowered away.
737 brw_mark_surface_used(&prog_data
->base
,
738 prog_data
->base
.binding_table
.ssbo_start
+
739 nir
->info
.num_ssbos
- 1);
743 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
745 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
747 offset_reg
= get_nir_src(instr
->src
[1], 1);
750 /* Read the vector */
751 const vec4_builder bld
= vec4_builder(this).at_end()
752 .annotate(current_annotation
, base_ir
);
755 dst_reg dest
= get_nir_dest(instr
->dest
);
756 if (type_sz(dest
.type
) < 8) {
757 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
758 1 /* dims */, 4 /* size*/,
761 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
764 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
765 1 /* dims */, 4 /* size*/,
767 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
769 if (offset_reg
.file
== IMM
)
772 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
774 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
775 1 /* dims */, 4 /* size*/,
777 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
780 read_result
= src_reg(this, glsl_type::dvec4_type
);
781 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
784 read_result
.type
= dest
.type
;
785 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
786 emit(MOV(dest
, read_result
));
790 case nir_intrinsic_ssbo_atomic_add
:
791 nir_emit_ssbo_atomic(BRW_AOP_ADD
, instr
);
793 case nir_intrinsic_ssbo_atomic_imin
:
794 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
796 case nir_intrinsic_ssbo_atomic_umin
:
797 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
799 case nir_intrinsic_ssbo_atomic_imax
:
800 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
802 case nir_intrinsic_ssbo_atomic_umax
:
803 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
805 case nir_intrinsic_ssbo_atomic_and
:
806 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
808 case nir_intrinsic_ssbo_atomic_or
:
809 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
811 case nir_intrinsic_ssbo_atomic_xor
:
812 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
814 case nir_intrinsic_ssbo_atomic_exchange
:
815 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
817 case nir_intrinsic_ssbo_atomic_comp_swap
:
818 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
821 case nir_intrinsic_load_vertex_id
:
822 unreachable("should be lowered by lower_vertex_id()");
824 case nir_intrinsic_load_vertex_id_zero_base
:
825 case nir_intrinsic_load_base_vertex
:
826 case nir_intrinsic_load_instance_id
:
827 case nir_intrinsic_load_base_instance
:
828 case nir_intrinsic_load_draw_id
:
829 case nir_intrinsic_load_invocation_id
: {
830 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
831 src_reg val
= src_reg(nir_system_values
[sv
]);
832 assert(val
.file
!= BAD_FILE
);
833 dest
= get_nir_dest(instr
->dest
, val
.type
);
834 emit(MOV(dest
, val
));
838 case nir_intrinsic_load_uniform
: {
839 /* Offsets are in bytes but they should always be multiples of 4 */
840 assert(nir_intrinsic_base(instr
) % 4 == 0);
842 dest
= get_nir_dest(instr
->dest
);
844 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
845 src
.type
= dest
.type
;
847 /* Uniforms don't actually have to be vec4 aligned. In the case that
848 * it isn't, we have to use a swizzle to shift things around. They
849 * do still have the std140 alignment requirement that vec2's have to
850 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
852 * The swizzle also works in the indirect case as the generator adds
853 * the swizzle to the offset for us.
855 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / 4;
856 assert(shift
+ instr
->num_components
<= 4);
858 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
860 /* Offsets are in bytes but they should always be multiples of 4 */
861 assert(const_offset
->u32
[0] % 4 == 0);
863 unsigned offset
= const_offset
->u32
[0] + shift
* 4;
864 src
.offset
= ROUND_DOWN_TO(offset
, 16);
865 shift
= (offset
% 16) / 4;
866 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
868 emit(MOV(dest
, src
));
870 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
872 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
874 /* MOV_INDIRECT is going to stomp the whole thing anyway */
875 dest
.writemask
= WRITEMASK_XYZW
;
877 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
878 indirect
, brw_imm_ud(instr
->const_index
[1]));
883 case nir_intrinsic_atomic_counter_read
:
884 case nir_intrinsic_atomic_counter_inc
:
885 case nir_intrinsic_atomic_counter_dec
: {
886 unsigned surf_index
= prog_data
->base
.binding_table
.abo_start
+
887 (unsigned) instr
->const_index
[0];
888 const vec4_builder bld
=
889 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
891 /* Get some metadata from the image intrinsic. */
892 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
894 /* Get the arguments of the atomic intrinsic. */
895 src_reg offset
= get_nir_src(instr
->src
[0], nir_type_int32
,
896 instr
->num_components
);
897 const src_reg surface
= brw_imm_ud(surf_index
);
898 const src_reg src0
= (info
->num_srcs
>= 2
899 ? get_nir_src(instr
->src
[1]) : src_reg());
900 const src_reg src1
= (info
->num_srcs
>= 3
901 ? get_nir_src(instr
->src
[2]) : src_reg());
905 dest
= get_nir_dest(instr
->dest
);
907 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
908 tmp
= emit_untyped_read(bld
, surface
, offset
, 1, 1);
910 tmp
= emit_untyped_atomic(bld
, surface
, offset
,
913 get_atomic_counter_op(instr
->intrinsic
));
916 bld
.MOV(retype(dest
, tmp
.type
), tmp
);
917 brw_mark_surface_used(stage_prog_data
, surf_index
);
921 case nir_intrinsic_load_ubo
: {
922 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
925 dest
= get_nir_dest(instr
->dest
);
927 if (const_block_index
) {
928 /* The block index is a constant, so just emit the binding table entry
931 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
932 const_block_index
->u32
[0];
933 surf_index
= brw_imm_ud(index
);
934 brw_mark_surface_used(&prog_data
->base
, index
);
936 /* The block index is not a constant. Evaluate the index expression
937 * per-channel and add the base UBO index; we have to select a value
938 * from any live channel.
940 surf_index
= src_reg(this, glsl_type::uint_type
);
941 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
942 instr
->num_components
),
943 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
944 surf_index
= emit_uniformize(surf_index
);
946 /* Assume this may touch any UBO. It would be nice to provide
947 * a tighter bound, but the array information is already lowered away.
949 brw_mark_surface_used(&prog_data
->base
,
950 prog_data
->base
.binding_table
.ubo_start
+
951 nir
->info
.num_ubos
- 1);
955 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
957 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
959 offset_reg
= get_nir_src(instr
->src
[1], nir_type_uint32
, 1);
962 src_reg packed_consts
;
963 if (nir_dest_bit_size(instr
->dest
) == 32) {
964 packed_consts
= src_reg(this, glsl_type::vec4_type
);
965 emit_pull_constant_load_reg(dst_reg(packed_consts
),
968 NULL
, NULL
/* before_block/inst */);
970 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
971 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
973 emit_pull_constant_load_reg(dst_reg(temp_float
),
974 surf_index
, offset_reg
, NULL
, NULL
);
975 if (offset_reg
.file
== IMM
)
978 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
979 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
980 surf_index
, offset_reg
, NULL
, NULL
);
982 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
983 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
986 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
988 unsigned type_size
= type_sz(dest
.type
);
989 packed_consts
.swizzle
+=
990 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
991 const_offset
->u32
[0] % 16 / type_size
,
992 const_offset
->u32
[0] % 16 / type_size
,
993 const_offset
->u32
[0] % 16 / type_size
);
996 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
1001 case nir_intrinsic_memory_barrier
: {
1002 const vec4_builder bld
=
1003 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
1004 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1005 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1006 ->size_written
= 2 * REG_SIZE
;
1010 case nir_intrinsic_shader_clock
: {
1011 /* We cannot do anything if there is an event, so ignore it for now */
1012 const src_reg shader_clock
= get_timestamp();
1013 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
1015 dest
= get_nir_dest(instr
->dest
, type
);
1016 emit(MOV(dest
, shader_clock
));
1021 unreachable("Unknown intrinsic");
1026 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
1029 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1030 dest
= get_nir_dest(instr
->dest
);
1033 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
1034 if (const_surface
) {
1035 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
1036 const_surface
->u32
[0];
1037 surface
= brw_imm_ud(surf_index
);
1038 brw_mark_surface_used(&prog_data
->base
, surf_index
);
1040 surface
= src_reg(this, glsl_type::uint_type
);
1041 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
1042 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
1044 /* Assume this may touch any UBO. This is the same we do for other
1045 * UBO/SSBO accesses with non-constant surface.
1047 brw_mark_surface_used(&prog_data
->base
,
1048 prog_data
->base
.binding_table
.ssbo_start
+
1049 nir
->info
.num_ssbos
- 1);
1052 src_reg offset
= get_nir_src(instr
->src
[1], 1);
1053 src_reg data1
= get_nir_src(instr
->src
[2], 1);
1055 if (op
== BRW_AOP_CMPWR
)
1056 data2
= get_nir_src(instr
->src
[3], 1);
1058 /* Emit the actual atomic operation operation */
1059 const vec4_builder bld
=
1060 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
1062 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
1064 1 /* dims */, 1 /* rsize */,
1066 BRW_PREDICATE_NONE
);
1067 dest
.type
= atomic_result
.type
;
1068 bld
.MOV(dest
, atomic_result
);
1072 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
1074 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
1077 static enum brw_conditional_mod
1078 brw_conditional_for_nir_comparison(nir_op op
)
1084 return BRW_CONDITIONAL_L
;
1089 return BRW_CONDITIONAL_GE
;
1093 case nir_op_ball_fequal2
:
1094 case nir_op_ball_iequal2
:
1095 case nir_op_ball_fequal3
:
1096 case nir_op_ball_iequal3
:
1097 case nir_op_ball_fequal4
:
1098 case nir_op_ball_iequal4
:
1099 return BRW_CONDITIONAL_Z
;
1103 case nir_op_bany_fnequal2
:
1104 case nir_op_bany_inequal2
:
1105 case nir_op_bany_fnequal3
:
1106 case nir_op_bany_inequal3
:
1107 case nir_op_bany_fnequal4
:
1108 case nir_op_bany_inequal4
:
1109 return BRW_CONDITIONAL_NZ
;
1112 unreachable("not reached: bad operation for comparison");
1117 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1118 enum brw_predicate
*predicate
)
1120 if (!instr
->src
[0].src
.is_ssa
||
1121 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1124 nir_alu_instr
*cmp_instr
=
1125 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1127 switch (cmp_instr
->op
) {
1128 case nir_op_bany_fnequal2
:
1129 case nir_op_bany_inequal2
:
1130 case nir_op_bany_fnequal3
:
1131 case nir_op_bany_inequal3
:
1132 case nir_op_bany_fnequal4
:
1133 case nir_op_bany_inequal4
:
1134 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1136 case nir_op_ball_fequal2
:
1137 case nir_op_ball_iequal2
:
1138 case nir_op_ball_fequal3
:
1139 case nir_op_ball_iequal3
:
1140 case nir_op_ball_fequal4
:
1141 case nir_op_ball_iequal4
:
1142 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1148 unsigned size_swizzle
=
1149 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1152 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1153 for (unsigned i
= 0; i
< 2; i
++) {
1154 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1155 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1156 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1157 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1158 unsigned base_swizzle
=
1159 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1160 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1161 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1162 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1165 emit(CMP(dst_null_d(), op
[0], op
[1],
1166 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1172 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1177 vec4_instruction
*inst
;
1181 /* LZD of an absolute value source almost always does the right
1182 * thing. There are two problem values:
1184 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1185 * 0. However, findMSB(int(0x80000000)) == 30.
1187 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1188 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1190 * For a value of zero or negative one, -1 will be returned.
1192 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1193 * findMSB(-(1<<x)) should return x-1.
1195 * For all negative number cases, including 0x80000000 and
1196 * 0xffffffff, the correct value is obtained from LZD if instead of
1197 * negating the (already negative) value the logical-not is used. A
1198 * conditonal logical-not can be achieved in two instructions.
1200 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1202 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1203 bld
.XOR(dst_reg(temp
), temp
, src
);
1206 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1207 retype(temp
, BRW_REGISTER_TYPE_UD
));
1209 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1210 * from the LSB side. Subtract the result from 31 to convert the MSB count
1211 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1212 * which is exactly what findMSB() is supposed to return.
1214 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1216 inst
->src
[0].negate
= true;
1220 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1223 /* BDW PRM vol 15 - workarounds:
1224 * DF->f format conversion for Align16 has wrong emask calculation when
1225 * source is immediate.
1227 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1228 src
.file
== BRW_IMMEDIATE_VALUE
) {
1229 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1230 inst
->saturate
= saturate
;
1236 case BRW_REGISTER_TYPE_D
:
1237 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1239 case BRW_REGISTER_TYPE_UD
:
1240 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1242 case BRW_REGISTER_TYPE_F
:
1243 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1246 unreachable("Unknown conversion");
1249 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1250 emit(MOV(temp
, src
));
1251 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1252 emit(op
, temp2
, src_reg(temp
));
1254 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1255 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1256 inst
->saturate
= saturate
;
1260 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1263 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1264 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1265 emit(MOV(dst_reg(tmp_src
), src
));
1266 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1267 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1268 inst
->saturate
= saturate
;
1272 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1274 vec4_instruction
*inst
;
1276 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1277 nir_dest_bit_size(instr
->dest
.dest
));
1278 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1279 dst
.writemask
= instr
->dest
.write_mask
;
1282 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1283 nir_alu_type src_type
= (nir_alu_type
)
1284 (nir_op_infos
[instr
->op
].input_types
[i
] |
1285 nir_src_bit_size(instr
->src
[i
].src
));
1286 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1287 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1288 op
[i
].abs
= instr
->src
[i
].abs
;
1289 op
[i
].negate
= instr
->src
[i
].negate
;
1292 switch (instr
->op
) {
1295 inst
= emit(MOV(dst
, op
[0]));
1296 inst
->saturate
= instr
->dest
.saturate
;
1302 unreachable("not reached: should be handled by lower_vec_to_movs()");
1306 inst
= emit(MOV(dst
, op
[0]));
1307 inst
->saturate
= instr
->dest
.saturate
;
1313 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1314 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1316 inst
= emit(MOV(dst
, op
[0]));
1322 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1326 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1329 inst
= emit(ADD(dst
, op
[0], op
[1]));
1330 inst
->saturate
= instr
->dest
.saturate
;
1334 inst
= emit(MUL(dst
, op
[0], op
[1]));
1335 inst
->saturate
= instr
->dest
.saturate
;
1339 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1340 if (devinfo
->gen
< 8) {
1341 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1342 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1344 /* For integer multiplication, the MUL uses the low 16 bits of one of
1345 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1346 * accumulates in the contribution of the upper 16 bits of that
1347 * operand. If we can determine that one of the args is in the low
1348 * 16 bits, though, we can just emit a single MUL.
1350 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1351 if (devinfo
->gen
< 7)
1352 emit(MUL(dst
, op
[0], op
[1]));
1354 emit(MUL(dst
, op
[1], op
[0]));
1355 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1356 if (devinfo
->gen
< 7)
1357 emit(MUL(dst
, op
[1], op
[0]));
1359 emit(MUL(dst
, op
[0], op
[1]));
1361 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1363 emit(MUL(acc
, op
[0], op
[1]));
1364 emit(MACH(dst_null_d(), op
[0], op
[1]));
1365 emit(MOV(dst
, src_reg(acc
)));
1368 emit(MUL(dst
, op
[0], op
[1]));
1373 case nir_op_imul_high
:
1374 case nir_op_umul_high
: {
1375 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1376 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1378 if (devinfo
->gen
>= 8)
1379 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1381 emit(MUL(acc
, op
[0], op
[1]));
1383 emit(MACH(dst
, op
[0], op
[1]));
1388 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1389 inst
->saturate
= instr
->dest
.saturate
;
1393 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1394 inst
->saturate
= instr
->dest
.saturate
;
1398 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1399 inst
->saturate
= instr
->dest
.saturate
;
1403 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1404 inst
->saturate
= instr
->dest
.saturate
;
1408 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1409 inst
->saturate
= instr
->dest
.saturate
;
1414 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1415 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1420 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1421 * appears that our hardware just does the right thing for signed
1424 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1425 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1429 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1430 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1432 /* Math instructions don't support conditional mod */
1433 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1434 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1436 /* Now, we need to determine if signs of the sources are different.
1437 * When we XOR the sources, the top bit is 0 if they are the same and 1
1438 * if they are different. We can then use a conditional modifier to
1439 * turn that into a predicate. This leads us to an XOR.l instruction.
1441 * Technically, according to the PRM, you're not allowed to use .l on a
1442 * XOR instruction. However, emperical experiments and Curro's reading
1443 * of the simulator source both indicate that it's safe.
1445 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1446 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1447 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1448 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1450 /* If the result of the initial remainder operation is non-zero and the
1451 * two sources have different signs, add in a copy of op[1] to get the
1452 * final integer modulus value.
1454 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1455 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1460 unreachable("not reached: should be handled by ldexp_to_arith()");
1463 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1464 inst
->saturate
= instr
->dest
.saturate
;
1468 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1469 inst
->saturate
= instr
->dest
.saturate
;
1473 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1474 inst
->saturate
= instr
->dest
.saturate
;
1477 case nir_op_uadd_carry
: {
1478 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1479 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1481 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1482 emit(MOV(dst
, src_reg(acc
)));
1486 case nir_op_usub_borrow
: {
1487 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1488 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1490 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1491 emit(MOV(dst
, src_reg(acc
)));
1496 inst
= emit(RNDZ(dst
, op
[0]));
1497 inst
->saturate
= instr
->dest
.saturate
;
1500 case nir_op_fceil
: {
1501 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1503 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1504 instr
->src
[0].src
.ssa
->num_components
:
1505 instr
->src
[0].src
.reg
.reg
->num_components
);
1507 op
[0].negate
= !op
[0].negate
;
1508 emit(RNDD(dst_reg(tmp
), op
[0]));
1510 inst
= emit(MOV(dst
, tmp
));
1511 inst
->saturate
= instr
->dest
.saturate
;
1516 inst
= emit(RNDD(dst
, op
[0]));
1517 inst
->saturate
= instr
->dest
.saturate
;
1521 inst
= emit(FRC(dst
, op
[0]));
1522 inst
->saturate
= instr
->dest
.saturate
;
1525 case nir_op_fround_even
:
1526 inst
= emit(RNDE(dst
, op
[0]));
1527 inst
->saturate
= instr
->dest
.saturate
;
1530 case nir_op_fquantize2f16
: {
1531 /* See also vec4_visitor::emit_pack_half_2x16() */
1532 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1533 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1534 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1536 /* Check for denormal */
1537 src_reg abs_src0
= op
[0];
1538 abs_src0
.abs
= true;
1539 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1540 BRW_CONDITIONAL_L
));
1541 /* Get the appropriately signed zero */
1542 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1543 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1544 brw_imm_ud(0x80000000)));
1545 /* Do the actual F32 -> F16 -> F32 conversion */
1546 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1547 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1548 /* Select that or zero based on normal status */
1549 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1550 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1551 inst
->saturate
= instr
->dest
.saturate
;
1557 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1560 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1561 inst
->saturate
= instr
->dest
.saturate
;
1566 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1569 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1570 inst
->saturate
= instr
->dest
.saturate
;
1574 case nir_op_fddx_coarse
:
1575 case nir_op_fddx_fine
:
1577 case nir_op_fddy_coarse
:
1578 case nir_op_fddy_fine
:
1579 unreachable("derivatives are not valid in vertex shaders");
1587 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1593 enum brw_conditional_mod conditional_mod
=
1594 brw_conditional_for_nir_comparison(instr
->op
);
1596 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1597 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1599 /* Produce a 32-bit boolean result from the DF comparison by selecting
1600 * only the low 32-bit in each DF produced. Do this in a temporary
1601 * so we can then move from there to the result using align16 again
1602 * to honor the original writemask.
1604 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1605 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1606 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1607 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1608 emit(MOV(dst
, src_reg(result
)));
1613 case nir_op_ball_iequal2
:
1614 case nir_op_ball_iequal3
:
1615 case nir_op_ball_iequal4
:
1616 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1618 case nir_op_ball_fequal2
:
1619 case nir_op_ball_fequal3
:
1620 case nir_op_ball_fequal4
: {
1622 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1624 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1625 brw_conditional_for_nir_comparison(instr
->op
)));
1626 emit(MOV(dst
, brw_imm_d(0)));
1627 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1628 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1632 case nir_op_bany_inequal2
:
1633 case nir_op_bany_inequal3
:
1634 case nir_op_bany_inequal4
:
1635 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1637 case nir_op_bany_fnequal2
:
1638 case nir_op_bany_fnequal3
:
1639 case nir_op_bany_fnequal4
: {
1641 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1643 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1644 brw_conditional_for_nir_comparison(instr
->op
)));
1646 emit(MOV(dst
, brw_imm_d(0)));
1647 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1648 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1653 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1654 if (devinfo
->gen
>= 8) {
1655 op
[0] = resolve_source_modifiers(op
[0]);
1657 emit(NOT(dst
, op
[0]));
1661 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1662 if (devinfo
->gen
>= 8) {
1663 op
[0] = resolve_source_modifiers(op
[0]);
1664 op
[1] = resolve_source_modifiers(op
[1]);
1666 emit(XOR(dst
, op
[0], op
[1]));
1670 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1671 if (devinfo
->gen
>= 8) {
1672 op
[0] = resolve_source_modifiers(op
[0]);
1673 op
[1] = resolve_source_modifiers(op
[1]);
1675 emit(OR(dst
, op
[0], op
[1]));
1679 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1680 if (devinfo
->gen
>= 8) {
1681 op
[0] = resolve_source_modifiers(op
[0]);
1682 op
[1] = resolve_source_modifiers(op
[1]);
1684 emit(AND(dst
, op
[0], op
[1]));
1689 emit(MOV(dst
, negate(op
[0])));
1693 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1694 /* We use a MOV with conditional_mod to check if the provided value is
1695 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1696 * source modifier on the source operand to trigger this, as source
1697 * modifiers don't affect the result of the testing against 0.0.
1699 src_reg value
= op
[0];
1701 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1702 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1704 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1705 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1706 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1707 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1709 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1714 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1717 case nir_op_fnoise1_1
:
1718 case nir_op_fnoise1_2
:
1719 case nir_op_fnoise1_3
:
1720 case nir_op_fnoise1_4
:
1721 case nir_op_fnoise2_1
:
1722 case nir_op_fnoise2_2
:
1723 case nir_op_fnoise2_3
:
1724 case nir_op_fnoise2_4
:
1725 case nir_op_fnoise3_1
:
1726 case nir_op_fnoise3_2
:
1727 case nir_op_fnoise3_3
:
1728 case nir_op_fnoise3_4
:
1729 case nir_op_fnoise4_1
:
1730 case nir_op_fnoise4_2
:
1731 case nir_op_fnoise4_3
:
1732 case nir_op_fnoise4_4
:
1733 unreachable("not reached: should be handled by lower_noise");
1735 case nir_op_unpack_half_2x16_split_x
:
1736 case nir_op_unpack_half_2x16_split_y
:
1737 case nir_op_pack_half_2x16_split
:
1738 unreachable("not reached: should not occur in vertex shader");
1740 case nir_op_unpack_snorm_2x16
:
1741 case nir_op_unpack_unorm_2x16
:
1742 case nir_op_pack_snorm_2x16
:
1743 case nir_op_pack_unorm_2x16
:
1744 unreachable("not reached: should be handled by lower_packing_builtins");
1746 case nir_op_pack_uvec4_to_uint
:
1747 unreachable("not reached");
1749 case nir_op_pack_uvec2_to_uint
: {
1750 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1751 tmp1
.writemask
= WRITEMASK_X
;
1752 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1753 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1755 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1756 tmp2
.writemask
= WRITEMASK_X
;
1757 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1758 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1760 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1764 case nir_op_pack_64_2x32_split
: {
1765 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1766 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1767 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1768 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1769 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1770 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1771 emit(MOV(dst
, src_reg(result
)));
1775 case nir_op_unpack_64_2x32_split_x
:
1776 case nir_op_unpack_64_2x32_split_y
: {
1777 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1778 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1779 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1780 emit(MOV(tmp
, op
[0]));
1781 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1782 emit(oper
, tmp2
, src_reg(tmp
));
1783 emit(MOV(dst
, src_reg(tmp2
)));
1787 case nir_op_unpack_half_2x16
:
1788 /* As NIR does not guarantee that we have a correct swizzle outside the
1789 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1790 * uses the source operand in an operation with WRITEMASK_Y while our
1791 * source operand has only size 1, it accessed incorrect data producing
1792 * regressions in Piglit. We repeat the swizzle of the first component on the
1793 * rest of components to avoid regressions. In the vec4_visitor IR code path
1794 * this is not needed because the operand has already the correct swizzle.
1796 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1797 emit_unpack_half_2x16(dst
, op
[0]);
1800 case nir_op_pack_half_2x16
:
1801 emit_pack_half_2x16(dst
, op
[0]);
1804 case nir_op_unpack_unorm_4x8
:
1805 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1806 emit_unpack_unorm_4x8(dst
, op
[0]);
1809 case nir_op_pack_unorm_4x8
:
1810 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1811 emit_pack_unorm_4x8(dst
, op
[0]);
1814 case nir_op_unpack_snorm_4x8
:
1815 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1816 emit_unpack_snorm_4x8(dst
, op
[0]);
1819 case nir_op_pack_snorm_4x8
:
1820 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1821 emit_pack_snorm_4x8(dst
, op
[0]);
1824 case nir_op_bitfield_reverse
:
1825 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1826 emit(BFREV(dst
, op
[0]));
1829 case nir_op_bit_count
:
1830 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1831 emit(CBIT(dst
, op
[0]));
1834 case nir_op_ufind_msb
:
1835 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1836 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1839 case nir_op_ifind_msb
: {
1840 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1841 vec4_builder bld
= vec4_builder(this).at_end();
1844 if (devinfo
->gen
< 7) {
1845 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1847 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1849 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1850 * count from the LSB side. If FBH didn't return an error
1851 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1852 * count into an LSB count.
1854 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1856 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1857 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1858 inst
->src
[0].negate
= true;
1863 case nir_op_find_lsb
: {
1864 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1865 vec4_builder bld
= vec4_builder(this).at_end();
1867 if (devinfo
->gen
< 7) {
1868 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1870 /* (x & -x) generates a value that consists of only the LSB of x.
1871 * For all powers of 2, findMSB(y) == findLSB(y).
1873 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1874 src_reg negated_src
= src
;
1876 /* One must be negated, and the other must be non-negated. It
1877 * doesn't matter which is which.
1879 negated_src
.negate
= true;
1882 bld
.AND(temp
, src
, negated_src
);
1883 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1885 bld
.FBL(dst
, op
[0]);
1890 case nir_op_ubitfield_extract
:
1891 case nir_op_ibitfield_extract
:
1892 unreachable("should have been lowered");
1895 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1896 op
[0] = fix_3src_operand(op
[0]);
1897 op
[1] = fix_3src_operand(op
[1]);
1898 op
[2] = fix_3src_operand(op
[2]);
1900 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1904 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1905 emit(BFI1(dst
, op
[0], op
[1]));
1909 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1910 op
[0] = fix_3src_operand(op
[0]);
1911 op
[1] = fix_3src_operand(op
[1]);
1912 op
[2] = fix_3src_operand(op
[2]);
1914 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1917 case nir_op_bitfield_insert
:
1918 unreachable("not reached: should have been lowered");
1921 if (type_sz(op
[0].type
) < 8) {
1922 /* AND(val, 0x80000000) gives the sign bit.
1924 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1927 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1929 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1930 dst
.type
= BRW_REGISTER_TYPE_UD
;
1931 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1933 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1934 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1935 dst
.type
= BRW_REGISTER_TYPE_F
;
1937 if (instr
->dest
.saturate
) {
1938 inst
= emit(MOV(dst
, src_reg(dst
)));
1939 inst
->saturate
= true;
1942 /* For doubles we do the same but we need to consider:
1944 * - We use a MOV with conditional_mod instead of a CMP so that we can
1945 * skip loading a 0.0 immediate. We use a source modifier on the
1946 * source of the MOV so that we flush denormalized values to 0.
1947 * Since we want to compare against 0, this won't alter the result.
1948 * - We need to extract the high 32-bit of each DF where the sign
1950 * - We need to produce a DF result.
1953 /* Check for zero */
1954 src_reg value
= op
[0];
1956 inst
= emit(MOV(dst_null_df(), value
));
1957 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1959 /* AND each high 32-bit channel with 0x80000000u */
1960 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1961 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1962 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1964 /* Add 1.0 to each channel, predicated to skip the cases where the
1965 * channel's value was 0
1967 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1968 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1970 /* Now convert the result from float to double */
1971 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1972 BRW_REGISTER_TYPE_F
),
1973 instr
->dest
.saturate
);
1978 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1979 * -> non-negative val generates 0x00000000.
1980 * Predicated OR sets 1 if val is positive.
1982 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1983 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1984 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1985 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1986 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1990 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1991 emit(SHL(dst
, op
[0], op
[1]));
1995 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1996 emit(ASR(dst
, op
[0], op
[1]));
2000 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
2001 emit(SHR(dst
, op
[0], op
[1]));
2005 if (type_sz(dst
.type
) == 8) {
2006 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
2007 emit(MUL(mul_dst
, op
[1], op
[0]));
2008 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
2009 inst
->saturate
= instr
->dest
.saturate
;
2011 op
[0] = fix_3src_operand(op
[0]);
2012 op
[1] = fix_3src_operand(op
[1]);
2013 op
[2] = fix_3src_operand(op
[2]);
2015 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
2016 inst
->saturate
= instr
->dest
.saturate
;
2021 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
2022 inst
->saturate
= instr
->dest
.saturate
;
2026 enum brw_predicate predicate
;
2027 if (!optimize_predicate(instr
, &predicate
)) {
2028 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
2029 switch (dst
.writemask
) {
2031 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
2034 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
2037 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
2040 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
2043 predicate
= BRW_PREDICATE_NORMAL
;
2047 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
2048 inst
->predicate
= predicate
;
2051 case nir_op_fdot_replicated2
:
2052 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
2053 inst
->saturate
= instr
->dest
.saturate
;
2056 case nir_op_fdot_replicated3
:
2057 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
2058 inst
->saturate
= instr
->dest
.saturate
;
2061 case nir_op_fdot_replicated4
:
2062 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
2063 inst
->saturate
= instr
->dest
.saturate
;
2066 case nir_op_fdph_replicated
:
2067 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
2068 inst
->saturate
= instr
->dest
.saturate
;
2073 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
2078 unreachable("not reached: should be lowered by lower_source mods");
2081 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
2084 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
2088 unreachable("not reached: should be handled by ir_sub_to_add_neg");
2091 unreachable("Unimplemented ALU operation");
2094 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2095 * to sign extend the low bit to 0/~0
2097 if (devinfo
->gen
<= 5 &&
2098 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2099 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2100 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2101 masked
.writemask
= dst
.writemask
;
2102 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2103 src_reg masked_neg
= src_reg(masked
);
2104 masked_neg
.negate
= true;
2105 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2110 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2112 switch (instr
->type
) {
2113 case nir_jump_break
:
2114 emit(BRW_OPCODE_BREAK
);
2117 case nir_jump_continue
:
2118 emit(BRW_OPCODE_CONTINUE
);
2121 case nir_jump_return
:
2124 unreachable("unknown jump");
2128 enum ir_texture_opcode
2129 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2131 enum ir_texture_opcode op
;
2134 case nir_texop_lod
: op
= ir_lod
; break;
2135 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2136 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2137 case nir_texop_tex
: op
= ir_tex
; break;
2138 case nir_texop_tg4
: op
= ir_tg4
; break;
2139 case nir_texop_txb
: op
= ir_txb
; break;
2140 case nir_texop_txd
: op
= ir_txd
; break;
2141 case nir_texop_txf
: op
= ir_txf
; break;
2142 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2143 case nir_texop_txl
: op
= ir_txl
; break;
2144 case nir_texop_txs
: op
= ir_txs
; break;
2145 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2147 unreachable("unknown texture opcode");
2153 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2154 unsigned components
)
2156 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2161 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2163 unsigned texture
= instr
->texture_index
;
2164 unsigned sampler
= instr
->sampler_index
;
2165 src_reg texture_reg
= brw_imm_ud(texture
);
2166 src_reg sampler_reg
= brw_imm_ud(sampler
);
2168 const glsl_type
*coord_type
= NULL
;
2169 src_reg shadow_comparator
;
2170 src_reg offset_value
;
2172 src_reg sample_index
;
2175 const glsl_type
*dest_type
=
2176 glsl_type_for_nir_alu_type(instr
->dest_type
,
2177 nir_tex_instr_dest_size(instr
));
2178 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2180 /* The hardware requires a LOD for buffer textures */
2181 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2184 /* Load the texture operation sources */
2185 uint32_t constant_offset
= 0;
2186 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2187 switch (instr
->src
[i
].src_type
) {
2188 case nir_tex_src_comparator
:
2189 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2190 BRW_REGISTER_TYPE_F
, 1);
2193 case nir_tex_src_coord
: {
2194 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2196 switch (instr
->op
) {
2198 case nir_texop_txf_ms
:
2199 case nir_texop_samples_identical
:
2200 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2202 coord_type
= glsl_type::ivec(src_size
);
2206 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2208 coord_type
= glsl_type::vec(src_size
);
2214 case nir_tex_src_ddx
:
2215 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2216 nir_tex_instr_src_size(instr
, i
));
2219 case nir_tex_src_ddy
:
2220 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2221 nir_tex_instr_src_size(instr
, i
));
2224 case nir_tex_src_lod
:
2225 switch (instr
->op
) {
2228 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2232 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2237 case nir_tex_src_ms_index
: {
2238 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2242 case nir_tex_src_offset
: {
2243 nir_const_value
*const_offset
=
2244 nir_src_as_const_value(instr
->src
[i
].src
);
2245 if (!const_offset
||
2246 !brw_texture_offset(const_offset
->i32
,
2247 nir_tex_instr_src_size(instr
, i
),
2248 &constant_offset
)) {
2250 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2255 case nir_tex_src_texture_offset
: {
2256 /* The highest texture which may be used by this operation is
2257 * the last element of the array. Mark it here, because the generator
2258 * doesn't have enough information to determine the bound.
2260 uint32_t array_size
= instr
->texture_array_size
;
2261 uint32_t max_used
= texture
+ array_size
- 1;
2262 if (instr
->op
== nir_texop_tg4
) {
2263 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2265 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2268 brw_mark_surface_used(&prog_data
->base
, max_used
);
2270 /* Emit code to evaluate the actual indexing expression */
2271 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2272 src_reg
temp(this, glsl_type::uint_type
);
2273 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2274 texture_reg
= emit_uniformize(temp
);
2278 case nir_tex_src_sampler_offset
: {
2279 /* Emit code to evaluate the actual indexing expression */
2280 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2281 src_reg
temp(this, glsl_type::uint_type
);
2282 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2283 sampler_reg
= emit_uniformize(temp
);
2287 case nir_tex_src_projector
:
2288 unreachable("Should be lowered by do_lower_texture_projection");
2290 case nir_tex_src_bias
:
2291 unreachable("LOD bias is not valid for vertex shaders.\n");
2294 unreachable("unknown texture source");
2298 if (instr
->op
== nir_texop_txf_ms
||
2299 instr
->op
== nir_texop_samples_identical
) {
2300 assert(coord_type
!= NULL
);
2301 if (devinfo
->gen
>= 7 &&
2302 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2303 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2305 mcs
= brw_imm_ud(0u);
2309 /* Stuff the channel select bits in the top of the texture offset */
2310 if (instr
->op
== nir_texop_tg4
) {
2311 if (instr
->component
== 1 &&
2312 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2313 /* gather4 sampler is broken for green channel on RG32F --
2314 * we must ask for blue instead.
2316 constant_offset
|= 2 << 16;
2318 constant_offset
|= instr
->component
<< 16;
2322 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2324 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2326 lod
, lod2
, sample_index
,
2327 constant_offset
, offset_value
, mcs
,
2328 texture
, texture_reg
, sampler_reg
);
2332 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2334 nir_ssa_values
[instr
->def
.index
] =
2335 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2338 /* SIMD4x2 64bit data is stored in register space like this:
2340 * r0.0:DF x0 y0 z0 w0
2341 * r1.0:DF x1 y1 z1 w1
2343 * When we need to write data such as this to memory using 32-bit write
2344 * messages we need to shuffle it in this fashion:
2346 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2347 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2349 * We need to do the inverse operation when we read using 32-bit messages,
2350 * which we can do by applying the same exact shuffling on the 64-bit data
2351 * read, only that because the data for each vertex is positioned differently
2352 * we need to apply different channel enables.
2354 * This function takes 64bit data and shuffles it as explained above.
2356 * The @for_write parameter is used to specify if the shuffling is being done
2357 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2358 * write message (for_write = true), or instead we are doing the inverse
2359 * operation and we have just read 64-bit data using a 32-bit messages that we
2360 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2362 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2363 * otherwise the instructions are emitted normally at the end. The function
2364 * returns the last instruction inserted.
2366 * Notice that @src and @dst cannot be the same register.
2369 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2370 bblock_t
*block
, vec4_instruction
*ref
)
2372 assert(type_sz(src
.type
) == 8);
2373 assert(type_sz(dst
.type
) == 8);
2374 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2375 assert(!ref
== !block
);
2377 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2378 vec4_builder(this).at(block
, ref
->next
);
2380 /* Resolve swizzle in src */
2381 vec4_instruction
*inst
;
2382 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2383 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2384 inst
= bld
.MOV(data
, src
);
2385 src
= src_reg(data
);
2388 /* dst+0.XY = src+0.XY */
2389 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2391 /* dst+0.ZW = src+1.XY */
2392 inst
= bld
.group(4, for_write
? 1 : 0)
2393 .MOV(writemask(dst
, WRITEMASK_ZW
),
2394 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2396 /* dst+1.XY = src+0.ZW */
2397 inst
= bld
.group(4, for_write
? 0 : 1)
2398 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2399 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2401 /* dst+1.ZW = src+1.ZW */
2402 inst
= bld
.group(4, 1)
2403 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2404 byte_offset(src
, REG_SIZE
));