2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_vec4_builder.h"
27 #include "brw_vec4_surface_builder.h"
30 using namespace brw::surface_access
;
35 vec4_visitor::emit_nir_code()
37 if (nir
->num_uniforms
> 0)
40 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
44 vec4_visitor::nir_setup_uniforms()
46 uniforms
= nir
->num_uniforms
/ 16;
50 vec4_visitor::nir_emit_impl(nir_function_impl
*impl
)
52 nir_locals
= ralloc_array(mem_ctx
, dst_reg
, impl
->reg_alloc
);
53 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
54 nir_locals
[i
] = dst_reg();
57 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
58 unsigned array_elems
=
59 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
60 const unsigned num_regs
= array_elems
* DIV_ROUND_UP(reg
->bit_size
, 32);
61 nir_locals
[reg
->index
] = dst_reg(VGRF
, alloc
.allocate(num_regs
));
63 if (reg
->bit_size
== 64)
64 nir_locals
[reg
->index
].type
= BRW_REGISTER_TYPE_DF
;
67 nir_ssa_values
= ralloc_array(mem_ctx
, dst_reg
, impl
->ssa_alloc
);
69 nir_emit_cf_list(&impl
->body
);
73 vec4_visitor::nir_emit_cf_list(exec_list
*list
)
75 exec_list_validate(list
);
76 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
79 nir_emit_if(nir_cf_node_as_if(node
));
82 case nir_cf_node_loop
:
83 nir_emit_loop(nir_cf_node_as_loop(node
));
86 case nir_cf_node_block
:
87 nir_emit_block(nir_cf_node_as_block(node
));
91 unreachable("Invalid CFG node block");
97 vec4_visitor::nir_emit_if(nir_if
*if_stmt
)
99 /* First, put the condition in f0 */
100 src_reg condition
= get_nir_src(if_stmt
->condition
, BRW_REGISTER_TYPE_D
, 1);
101 vec4_instruction
*inst
= emit(MOV(dst_null_d(), condition
));
102 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
104 /* We can just predicate based on the X channel, as the condition only
105 * goes on its own line */
106 emit(IF(BRW_PREDICATE_ALIGN16_REPLICATE_X
));
108 nir_emit_cf_list(&if_stmt
->then_list
);
110 /* note: if the else is empty, dead CF elimination will remove it */
111 emit(BRW_OPCODE_ELSE
);
113 nir_emit_cf_list(&if_stmt
->else_list
);
115 emit(BRW_OPCODE_ENDIF
);
119 vec4_visitor::nir_emit_loop(nir_loop
*loop
)
123 nir_emit_cf_list(&loop
->body
);
125 emit(BRW_OPCODE_WHILE
);
129 vec4_visitor::nir_emit_block(nir_block
*block
)
131 nir_foreach_instr(instr
, block
) {
132 nir_emit_instr(instr
);
137 vec4_visitor::nir_emit_instr(nir_instr
*instr
)
141 switch (instr
->type
) {
142 case nir_instr_type_load_const
:
143 nir_emit_load_const(nir_instr_as_load_const(instr
));
146 case nir_instr_type_intrinsic
:
147 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
150 case nir_instr_type_alu
:
151 nir_emit_alu(nir_instr_as_alu(instr
));
154 case nir_instr_type_jump
:
155 nir_emit_jump(nir_instr_as_jump(instr
));
158 case nir_instr_type_tex
:
159 nir_emit_texture(nir_instr_as_tex(instr
));
162 case nir_instr_type_ssa_undef
:
163 nir_emit_undef(nir_instr_as_ssa_undef(instr
));
167 unreachable("VS instruction not yet implemented by NIR->vec4");
172 dst_reg_for_nir_reg(vec4_visitor
*v
, nir_register
*nir_reg
,
173 unsigned base_offset
, nir_src
*indirect
)
177 reg
= v
->nir_locals
[nir_reg
->index
];
178 if (nir_reg
->bit_size
== 64)
179 reg
.type
= BRW_REGISTER_TYPE_DF
;
180 reg
= offset(reg
, 8, base_offset
);
183 new(v
->mem_ctx
) src_reg(v
->get_nir_src(*indirect
,
191 vec4_visitor::get_nir_dest(const nir_dest
&dest
)
195 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(dest
.ssa
.bit_size
, 32)));
196 if (dest
.ssa
.bit_size
== 64)
197 dst
.type
= BRW_REGISTER_TYPE_DF
;
198 nir_ssa_values
[dest
.ssa
.index
] = dst
;
201 return dst_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
207 vec4_visitor::get_nir_dest(const nir_dest
&dest
, enum brw_reg_type type
)
209 return retype(get_nir_dest(dest
), type
);
213 vec4_visitor::get_nir_dest(const nir_dest
&dest
, nir_alu_type type
)
215 return get_nir_dest(dest
, brw_type_for_nir_type(devinfo
, type
));
219 vec4_visitor::get_nir_src(const nir_src
&src
, enum brw_reg_type type
,
220 unsigned num_components
)
225 assert(src
.ssa
!= NULL
);
226 reg
= nir_ssa_values
[src
.ssa
->index
];
229 reg
= dst_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
233 reg
= retype(reg
, type
);
235 src_reg reg_as_src
= src_reg(reg
);
236 reg_as_src
.swizzle
= brw_swizzle_for_size(num_components
);
241 vec4_visitor::get_nir_src(const nir_src
&src
, nir_alu_type type
,
242 unsigned num_components
)
244 return get_nir_src(src
, brw_type_for_nir_type(devinfo
, type
),
249 vec4_visitor::get_nir_src(const nir_src
&src
, unsigned num_components
)
251 /* if type is not specified, default to signed int */
252 return get_nir_src(src
, nir_type_int32
, num_components
);
256 vec4_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
258 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
259 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
262 /* The only constant offset we should find is 0. brw_nir.c's
263 * add_const_offset_to_base() will fold other constant offsets
264 * into instr->const_index[0].
266 assert(const_value
->u32
[0] == 0);
270 return get_nir_src(*offset_src
, BRW_REGISTER_TYPE_UD
, 1);
274 setup_imm_df(const vec4_builder
&bld
, double v
)
276 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
277 assert(devinfo
->gen
>= 7);
279 if (devinfo
->gen
>= 8)
280 return brw_imm_df(v
);
282 /* gen7.5 does not support DF immediates straighforward but the DIM
283 * instruction allows to set the 64-bit immediate value.
285 if (devinfo
->is_haswell
) {
286 const vec4_builder ubld
= bld
.exec_all();
287 const dst_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_DF
);
288 ubld
.DIM(dst
, brw_imm_df(v
));
289 return swizzle(src_reg(dst
), BRW_SWIZZLE_XXXX
);
292 /* gen7 does not support DF immediates */
303 /* Write the low 32-bit of the constant to the X:UD channel and the
304 * high 32-bit to the Y:UD channel to build the constant in a VGRF.
305 * We have to do this twice (offset 0 and offset 1), since a DF VGRF takes
306 * two SIMD8 registers in SIMD4x2 execution. Finally, return a swizzle
307 * XXXX so any access to the VGRF only reads the constant data in these
310 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
311 for (unsigned n
= 0; n
< 2; n
++) {
312 const vec4_builder ubld
= bld
.exec_all().group(4, n
);
313 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_X
), brw_imm_ud(di
.i1
));
314 ubld
.MOV(writemask(offset(tmp
, 8, n
), WRITEMASK_Y
), brw_imm_ud(di
.i2
));
317 return swizzle(src_reg(retype(tmp
, BRW_REGISTER_TYPE_DF
)), BRW_SWIZZLE_XXXX
);
321 vec4_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
325 if (instr
->def
.bit_size
== 64) {
326 reg
= dst_reg(VGRF
, alloc
.allocate(2));
327 reg
.type
= BRW_REGISTER_TYPE_DF
;
329 reg
= dst_reg(VGRF
, alloc
.allocate(1));
330 reg
.type
= BRW_REGISTER_TYPE_D
;
333 const vec4_builder ibld
= vec4_builder(this).at_end();
334 unsigned remaining
= brw_writemask_for_size(instr
->def
.num_components
);
336 /* @FIXME: consider emitting vector operations to save some MOVs in
337 * cases where the components are representable in 8 bits.
338 * For now, we emit a MOV for each distinct value.
340 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
341 unsigned writemask
= 1 << i
;
343 if ((remaining
& writemask
) == 0)
346 for (unsigned j
= i
; j
< instr
->def
.num_components
; j
++) {
347 if ((instr
->def
.bit_size
== 32 &&
348 instr
->value
.u32
[i
] == instr
->value
.u32
[j
]) ||
349 (instr
->def
.bit_size
== 64 &&
350 instr
->value
.f64
[i
] == instr
->value
.f64
[j
])) {
355 reg
.writemask
= writemask
;
356 if (instr
->def
.bit_size
== 64) {
357 emit(MOV(reg
, setup_imm_df(ibld
, instr
->value
.f64
[i
])));
359 emit(MOV(reg
, brw_imm_d(instr
->value
.i32
[i
])));
362 remaining
&= ~writemask
;
365 /* Set final writemask */
366 reg
.writemask
= brw_writemask_for_size(instr
->def
.num_components
);
368 nir_ssa_values
[instr
->def
.index
] = reg
;
372 vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
377 switch (instr
->intrinsic
) {
379 case nir_intrinsic_load_input
: {
380 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
382 /* We set EmitNoIndirectInput for VS */
383 assert(const_offset
);
385 dest
= get_nir_dest(instr
->dest
);
386 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
388 src
= src_reg(ATTR
, instr
->const_index
[0] + const_offset
->u32
[0],
389 glsl_type::uvec4_type
);
390 src
= retype(src
, dest
.type
);
392 bool is_64bit
= nir_dest_bit_size(instr
->dest
) == 64;
394 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
395 src
.swizzle
= BRW_SWIZZLE_XYZW
;
396 shuffle_64bit_data(tmp
, src
, false);
397 emit(MOV(dest
, src_reg(tmp
)));
399 /* Swizzle source based on component layout qualifier */
400 src
.swizzle
= BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr
));
401 emit(MOV(dest
, src
));
406 case nir_intrinsic_store_output
: {
407 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
408 assert(const_offset
);
410 int varying
= instr
->const_index
[0] + const_offset
->u32
[0];
412 bool is_64bit
= nir_src_bit_size(instr
->src
[0]) == 64;
415 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_DF
,
416 instr
->num_components
);
417 data
= src_reg(this, glsl_type::dvec4_type
);
418 shuffle_64bit_data(dst_reg(data
), src
, true);
419 src
= retype(data
, BRW_REGISTER_TYPE_F
);
421 src
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
,
422 instr
->num_components
);
425 unsigned c
= nir_intrinsic_component(instr
);
426 output_reg
[varying
][c
] = dst_reg(src
);
427 output_num_components
[varying
][c
] = instr
->num_components
;
429 unsigned num_components
= instr
->num_components
;
433 output_reg
[varying
][c
] = dst_reg(src
);
434 output_num_components
[varying
][c
] = MIN2(4, num_components
);
436 if (is_64bit
&& num_components
> 4) {
437 assert(num_components
<= 8);
438 output_reg
[varying
+ 1][c
] = byte_offset(dst_reg(src
), REG_SIZE
);
439 output_num_components
[varying
+ 1][c
] = num_components
- 4;
444 case nir_intrinsic_get_buffer_size
: {
445 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
446 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
448 const unsigned index
=
449 prog_data
->base
.binding_table
.ssbo_start
+ ssbo_index
;
450 dst_reg result_dst
= get_nir_dest(instr
->dest
);
451 vec4_instruction
*inst
= new(mem_ctx
)
452 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE
, result_dst
);
455 inst
->mlen
= 1; /* always at least one */
456 inst
->src
[1] = brw_imm_ud(index
);
458 /* MRF for the first parameter */
459 src_reg lod
= brw_imm_d(0);
460 int param_base
= inst
->base_mrf
;
461 int writemask
= WRITEMASK_X
;
462 emit(MOV(dst_reg(MRF
, param_base
, glsl_type::int_type
, writemask
), lod
));
466 brw_mark_surface_used(&prog_data
->base
, index
);
470 case nir_intrinsic_store_ssbo
: {
471 assert(devinfo
->gen
>= 7);
475 nir_const_value
*const_uniform_block
=
476 nir_src_as_const_value(instr
->src
[1]);
477 if (const_uniform_block
) {
478 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
479 const_uniform_block
->u32
[0];
480 surf_index
= brw_imm_ud(index
);
481 brw_mark_surface_used(&prog_data
->base
, index
);
483 surf_index
= src_reg(this, glsl_type::uint_type
);
484 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[1], 1),
485 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
486 surf_index
= emit_uniformize(surf_index
);
488 brw_mark_surface_used(&prog_data
->base
,
489 prog_data
->base
.binding_table
.ssbo_start
+
490 nir
->info
.num_ssbos
- 1);
495 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
497 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
499 offset_reg
= get_nir_src(instr
->src
[2], 1);
503 src_reg val_reg
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_F
, 4);
506 unsigned write_mask
= instr
->const_index
[0];
508 /* IvyBridge does not have a native SIMD4x2 untyped write message so untyped
509 * writes will use SIMD8 mode. In order to hide this and keep symmetry across
510 * typed and untyped messages and across hardware platforms, the
511 * current implementation of the untyped messages will transparently convert
512 * the SIMD4x2 payload into an equivalent SIMD8 payload by transposing it
513 * and enabling only channel X on the SEND instruction.
515 * The above, works well for full vector writes, but not for partial writes
516 * where we want to write some channels and not others, like when we have
517 * code such as v.xyw = vec3(1,2,4). Because the untyped write messages are
518 * quite restrictive with regards to the channel enables we can configure in
519 * the message descriptor (not all combinations are allowed) we cannot simply
520 * implement these scenarios with a single message while keeping the
521 * aforementioned symmetry in the implementation. For now we de decided that
522 * it is better to keep the symmetry to reduce complexity, so in situations
523 * such as the one described we end up emitting two untyped write messages
524 * (one for xy and another for w).
526 * The code below packs consecutive channels into a single write message,
527 * detects gaps in the vector write and if needed, sends a second message
528 * with the remaining channels. If in the future we decide that we want to
529 * emit a single message at the expense of losing the symmetry in the
530 * implementation we can:
532 * 1) For IvyBridge: Only use the red channel of the untyped write SIMD8
533 * message payload. In this mode we can write up to 8 offsets and dwords
534 * to the red channel only (for the two vec4s in the SIMD4x2 execution)
535 * and select which of the 8 channels carry data to write by setting the
536 * appropriate writemask in the dst register of the SEND instruction.
537 * It would require to write a new generator opcode specifically for
538 * IvyBridge since we would need to prepare a SIMD8 payload that could
539 * use any channel, not just X.
541 * 2) For Haswell+: Simply send a single write message but set the writemask
542 * on the dst of the SEND instruction to select the channels we want to
543 * write. It would require to modify the current messages to receive
544 * and honor the writemask provided.
546 const vec4_builder bld
= vec4_builder(this).at_end()
547 .annotate(current_annotation
, base_ir
);
549 unsigned type_slots
= nir_src_bit_size(instr
->src
[0]) / 32;
550 if (type_slots
== 2) {
551 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
552 shuffle_64bit_data(tmp
, retype(val_reg
, tmp
.type
), true);
553 val_reg
= src_reg(retype(tmp
, BRW_REGISTER_TYPE_F
));
556 uint8_t swizzle
[4] = { 0, 0, 0, 0};
557 int num_channels
= 0;
558 unsigned skipped_channels
= 0;
559 int num_components
= instr
->num_components
;
560 for (int i
= 0; i
< num_components
; i
++) {
561 /* Read components Z/W of a dvec from the appropriate place. We will
562 * also have to adjust the swizzle (we do that with the '% 4' below)
564 if (i
== 2 && type_slots
== 2)
565 val_reg
= byte_offset(val_reg
, REG_SIZE
);
567 /* Check if this channel needs to be written. If so, record the
568 * channel we need to take the data from in the swizzle array
570 int component_mask
= 1 << i
;
571 int write_test
= write_mask
& component_mask
;
573 /* If we are writing doubles we have to write 2 channels worth of
574 * of data (64 bits) for each double component.
576 swizzle
[num_channels
++] = (i
* type_slots
) % 4;
578 swizzle
[num_channels
++] = (i
* type_slots
+ 1) % 4;
581 /* If we don't have to write this channel it means we have a gap in the
582 * vector, so write the channels we accumulated until now, if any. Do
583 * the same if this was the last component in the vector, if we have
584 * enough channels for a full vec4 write or if we have processed
585 * components XY of a dvec (since components ZW are not in the same
588 if (!write_test
|| i
== num_components
- 1 || num_channels
== 4 ||
589 (i
== 1 && type_slots
== 2)) {
590 if (num_channels
> 0) {
591 /* We have channels to write, so update the offset we need to
592 * write at to skip the channels we skipped, if any.
594 if (skipped_channels
> 0) {
595 if (offset_reg
.file
== IMM
) {
596 offset_reg
.ud
+= 4 * skipped_channels
;
598 emit(ADD(dst_reg(offset_reg
), offset_reg
,
599 brw_imm_ud(4 * skipped_channels
)));
603 /* Swizzle the data register so we take the data from the channels
604 * we need to write and send the write message. This will write
605 * num_channels consecutive dwords starting at offset.
608 BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
609 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
610 1 /* dims */, num_channels
/* size */,
613 /* If we have to do a second write we will have to update the
614 * offset so that we jump over the channels we have just written
617 skipped_channels
= num_channels
;
619 /* Restart the count for the next write message */
623 /* If we didn't write the channel, increase skipped count */
625 skipped_channels
+= type_slots
;
632 case nir_intrinsic_load_ssbo
: {
633 assert(devinfo
->gen
>= 7);
635 nir_const_value
*const_uniform_block
=
636 nir_src_as_const_value(instr
->src
[0]);
639 if (const_uniform_block
) {
640 unsigned index
= prog_data
->base
.binding_table
.ssbo_start
+
641 const_uniform_block
->u32
[0];
642 surf_index
= brw_imm_ud(index
);
644 brw_mark_surface_used(&prog_data
->base
, index
);
646 surf_index
= src_reg(this, glsl_type::uint_type
);
647 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], 1),
648 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
649 surf_index
= emit_uniformize(surf_index
);
651 /* Assume this may touch any UBO. It would be nice to provide
652 * a tighter bound, but the array information is already lowered away.
654 brw_mark_surface_used(&prog_data
->base
,
655 prog_data
->base
.binding_table
.ssbo_start
+
656 nir
->info
.num_ssbos
- 1);
660 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
662 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
664 offset_reg
= get_nir_src(instr
->src
[1], 1);
667 /* Read the vector */
668 const vec4_builder bld
= vec4_builder(this).at_end()
669 .annotate(current_annotation
, base_ir
);
672 dst_reg dest
= get_nir_dest(instr
->dest
);
673 if (type_sz(dest
.type
) < 8) {
674 read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
675 1 /* dims */, 4 /* size*/,
678 src_reg shuffled
= src_reg(this, glsl_type::dvec4_type
);
681 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
682 1 /* dims */, 4 /* size*/,
684 emit(MOV(dst_reg(retype(shuffled
, temp
.type
)), temp
));
686 if (offset_reg
.file
== IMM
)
689 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16)));
691 temp
= emit_untyped_read(bld
, surf_index
, offset_reg
,
692 1 /* dims */, 4 /* size*/,
694 emit(MOV(dst_reg(retype(byte_offset(shuffled
, REG_SIZE
), temp
.type
)),
697 read_result
= src_reg(this, glsl_type::dvec4_type
);
698 shuffle_64bit_data(dst_reg(read_result
), shuffled
, false);
701 read_result
.type
= dest
.type
;
702 read_result
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
703 emit(MOV(dest
, read_result
));
707 case nir_intrinsic_ssbo_atomic_add
: {
708 int op
= BRW_AOP_ADD
;
709 const nir_const_value
*const val
= nir_src_as_const_value(instr
->src
[2]);
712 if (val
->i32
[0] == 1)
714 else if (val
->i32
[0] == -1)
718 nir_emit_ssbo_atomic(op
, instr
);
721 case nir_intrinsic_ssbo_atomic_imin
:
722 nir_emit_ssbo_atomic(BRW_AOP_IMIN
, instr
);
724 case nir_intrinsic_ssbo_atomic_umin
:
725 nir_emit_ssbo_atomic(BRW_AOP_UMIN
, instr
);
727 case nir_intrinsic_ssbo_atomic_imax
:
728 nir_emit_ssbo_atomic(BRW_AOP_IMAX
, instr
);
730 case nir_intrinsic_ssbo_atomic_umax
:
731 nir_emit_ssbo_atomic(BRW_AOP_UMAX
, instr
);
733 case nir_intrinsic_ssbo_atomic_and
:
734 nir_emit_ssbo_atomic(BRW_AOP_AND
, instr
);
736 case nir_intrinsic_ssbo_atomic_or
:
737 nir_emit_ssbo_atomic(BRW_AOP_OR
, instr
);
739 case nir_intrinsic_ssbo_atomic_xor
:
740 nir_emit_ssbo_atomic(BRW_AOP_XOR
, instr
);
742 case nir_intrinsic_ssbo_atomic_exchange
:
743 nir_emit_ssbo_atomic(BRW_AOP_MOV
, instr
);
745 case nir_intrinsic_ssbo_atomic_comp_swap
:
746 nir_emit_ssbo_atomic(BRW_AOP_CMPWR
, instr
);
749 case nir_intrinsic_load_vertex_id
:
750 unreachable("should be lowered by lower_vertex_id()");
752 case nir_intrinsic_load_vertex_id_zero_base
:
753 case nir_intrinsic_load_base_vertex
:
754 case nir_intrinsic_load_instance_id
:
755 case nir_intrinsic_load_base_instance
:
756 case nir_intrinsic_load_draw_id
:
757 case nir_intrinsic_load_invocation_id
:
758 unreachable("should be lowered by brw_nir_lower_vs_inputs()");
760 case nir_intrinsic_load_uniform
: {
761 /* Offsets are in bytes but they should always be multiples of 4 */
762 assert(nir_intrinsic_base(instr
) % 4 == 0);
764 dest
= get_nir_dest(instr
->dest
);
766 src
= src_reg(dst_reg(UNIFORM
, nir_intrinsic_base(instr
) / 16));
767 src
.type
= dest
.type
;
769 /* Uniforms don't actually have to be vec4 aligned. In the case that
770 * it isn't, we have to use a swizzle to shift things around. They
771 * do still have the std140 alignment requirement that vec2's have to
772 * be vec2-aligned and vec3's and vec4's have to be vec4-aligned.
774 * The swizzle also works in the indirect case as the generator adds
775 * the swizzle to the offset for us.
777 const int type_size
= type_sz(src
.type
);
778 unsigned shift
= (nir_intrinsic_base(instr
) % 16) / type_size
;
779 assert(shift
+ instr
->num_components
<= 4);
781 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
783 /* Offsets are in bytes but they should always be multiples of 4 */
784 assert(const_offset
->u32
[0] % 4 == 0);
786 src
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
787 dest
.writemask
= brw_writemask_for_size(instr
->num_components
);
788 unsigned offset
= const_offset
->u32
[0] + shift
* type_size
;
789 src
.offset
= ROUND_DOWN_TO(offset
, 16);
790 shift
= (offset
% 16) / type_size
;
791 assert(shift
+ instr
->num_components
<= 4);
792 src
.swizzle
+= BRW_SWIZZLE4(shift
, shift
, shift
, shift
);
794 emit(MOV(dest
, src
));
796 /* Uniform arrays are vec4 aligned, because of std140 alignment
801 src_reg indirect
= get_nir_src(instr
->src
[0], BRW_REGISTER_TYPE_UD
, 1);
803 /* MOV_INDIRECT is going to stomp the whole thing anyway */
804 dest
.writemask
= WRITEMASK_XYZW
;
806 emit(SHADER_OPCODE_MOV_INDIRECT
, dest
, src
,
807 indirect
, brw_imm_ud(instr
->const_index
[1]));
812 case nir_intrinsic_load_ubo
: {
813 nir_const_value
*const_block_index
= nir_src_as_const_value(instr
->src
[0]);
816 dest
= get_nir_dest(instr
->dest
);
818 if (const_block_index
) {
819 /* The block index is a constant, so just emit the binding table entry
822 const unsigned index
= prog_data
->base
.binding_table
.ubo_start
+
823 const_block_index
->u32
[0];
824 surf_index
= brw_imm_ud(index
);
825 brw_mark_surface_used(&prog_data
->base
, index
);
827 /* The block index is not a constant. Evaluate the index expression
828 * per-channel and add the base UBO index; we have to select a value
829 * from any live channel.
831 surf_index
= src_reg(this, glsl_type::uint_type
);
832 emit(ADD(dst_reg(surf_index
), get_nir_src(instr
->src
[0], nir_type_int32
,
833 instr
->num_components
),
834 brw_imm_ud(prog_data
->base
.binding_table
.ubo_start
)));
835 surf_index
= emit_uniformize(surf_index
);
837 /* Assume this may touch any UBO. It would be nice to provide
838 * a tighter bound, but the array information is already lowered away.
840 brw_mark_surface_used(&prog_data
->base
,
841 prog_data
->base
.binding_table
.ubo_start
+
842 nir
->info
.num_ubos
- 1);
846 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
848 offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
850 offset_reg
= src_reg(this, glsl_type::uint_type
);
851 emit(MOV(dst_reg(offset_reg
),
852 get_nir_src(instr
->src
[1], nir_type_uint32
, 1)));
855 src_reg packed_consts
;
856 if (nir_dest_bit_size(instr
->dest
) == 32) {
857 packed_consts
= src_reg(this, glsl_type::vec4_type
);
858 emit_pull_constant_load_reg(dst_reg(packed_consts
),
861 NULL
, NULL
/* before_block/inst */);
863 src_reg temp
= src_reg(this, glsl_type::dvec4_type
);
864 src_reg temp_float
= retype(temp
, BRW_REGISTER_TYPE_F
);
866 emit_pull_constant_load_reg(dst_reg(temp_float
),
867 surf_index
, offset_reg
, NULL
, NULL
);
868 if (offset_reg
.file
== IMM
)
871 emit(ADD(dst_reg(offset_reg
), offset_reg
, brw_imm_ud(16u)));
872 emit_pull_constant_load_reg(dst_reg(byte_offset(temp_float
, REG_SIZE
)),
873 surf_index
, offset_reg
, NULL
, NULL
);
875 packed_consts
= src_reg(this, glsl_type::dvec4_type
);
876 shuffle_64bit_data(dst_reg(packed_consts
), temp
, false);
879 packed_consts
.swizzle
= brw_swizzle_for_size(instr
->num_components
);
881 unsigned type_size
= type_sz(dest
.type
);
882 packed_consts
.swizzle
+=
883 BRW_SWIZZLE4(const_offset
->u32
[0] % 16 / type_size
,
884 const_offset
->u32
[0] % 16 / type_size
,
885 const_offset
->u32
[0] % 16 / type_size
,
886 const_offset
->u32
[0] % 16 / type_size
);
889 emit(MOV(dest
, retype(packed_consts
, dest
.type
)));
894 case nir_intrinsic_memory_barrier
: {
895 const vec4_builder bld
=
896 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
897 const dst_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
898 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
899 ->size_written
= 2 * REG_SIZE
;
903 case nir_intrinsic_shader_clock
: {
904 /* We cannot do anything if there is an event, so ignore it for now */
905 const src_reg shader_clock
= get_timestamp();
906 const enum brw_reg_type type
= brw_type_for_base_type(glsl_type::uvec2_type
);
908 dest
= get_nir_dest(instr
->dest
, type
);
909 emit(MOV(dest
, shader_clock
));
914 unreachable("Unknown intrinsic");
919 vec4_visitor::nir_emit_ssbo_atomic(int op
, nir_intrinsic_instr
*instr
)
922 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
923 dest
= get_nir_dest(instr
->dest
);
926 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
928 unsigned surf_index
= prog_data
->base
.binding_table
.ssbo_start
+
929 const_surface
->u32
[0];
930 surface
= brw_imm_ud(surf_index
);
931 brw_mark_surface_used(&prog_data
->base
, surf_index
);
933 surface
= src_reg(this, glsl_type::uint_type
);
934 emit(ADD(dst_reg(surface
), get_nir_src(instr
->src
[0]),
935 brw_imm_ud(prog_data
->base
.binding_table
.ssbo_start
)));
937 /* Assume this may touch any UBO. This is the same we do for other
938 * UBO/SSBO accesses with non-constant surface.
940 brw_mark_surface_used(&prog_data
->base
,
941 prog_data
->base
.binding_table
.ssbo_start
+
942 nir
->info
.num_ssbos
- 1);
945 src_reg offset
= get_nir_src(instr
->src
[1], 1);
947 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
948 data1
= get_nir_src(instr
->src
[2], 1);
950 if (op
== BRW_AOP_CMPWR
)
951 data2
= get_nir_src(instr
->src
[3], 1);
953 /* Emit the actual atomic operation operation */
954 const vec4_builder bld
=
955 vec4_builder(this).at_end().annotate(current_annotation
, base_ir
);
957 src_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
959 1 /* dims */, 1 /* rsize */,
962 dest
.type
= atomic_result
.type
;
963 bld
.MOV(dest
, atomic_result
);
967 brw_swizzle_for_nir_swizzle(uint8_t swizzle
[4])
969 return BRW_SWIZZLE4(swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
972 static enum brw_conditional_mod
973 brw_conditional_for_nir_comparison(nir_op op
)
979 return BRW_CONDITIONAL_L
;
984 return BRW_CONDITIONAL_GE
;
988 case nir_op_ball_fequal2
:
989 case nir_op_ball_iequal2
:
990 case nir_op_ball_fequal3
:
991 case nir_op_ball_iequal3
:
992 case nir_op_ball_fequal4
:
993 case nir_op_ball_iequal4
:
994 return BRW_CONDITIONAL_Z
;
998 case nir_op_bany_fnequal2
:
999 case nir_op_bany_inequal2
:
1000 case nir_op_bany_fnequal3
:
1001 case nir_op_bany_inequal3
:
1002 case nir_op_bany_fnequal4
:
1003 case nir_op_bany_inequal4
:
1004 return BRW_CONDITIONAL_NZ
;
1007 unreachable("not reached: bad operation for comparison");
1012 vec4_visitor::optimize_predicate(nir_alu_instr
*instr
,
1013 enum brw_predicate
*predicate
)
1015 if (!instr
->src
[0].src
.is_ssa
||
1016 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1019 nir_alu_instr
*cmp_instr
=
1020 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1022 switch (cmp_instr
->op
) {
1023 case nir_op_bany_fnequal2
:
1024 case nir_op_bany_inequal2
:
1025 case nir_op_bany_fnequal3
:
1026 case nir_op_bany_inequal3
:
1027 case nir_op_bany_fnequal4
:
1028 case nir_op_bany_inequal4
:
1029 *predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1031 case nir_op_ball_fequal2
:
1032 case nir_op_ball_iequal2
:
1033 case nir_op_ball_fequal3
:
1034 case nir_op_ball_iequal3
:
1035 case nir_op_ball_fequal4
:
1036 case nir_op_ball_iequal4
:
1037 *predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1043 unsigned size_swizzle
=
1044 brw_swizzle_for_size(nir_op_infos
[cmp_instr
->op
].input_sizes
[0]);
1047 assert(nir_op_infos
[cmp_instr
->op
].num_inputs
== 2);
1048 for (unsigned i
= 0; i
< 2; i
++) {
1049 nir_alu_type type
= nir_op_infos
[cmp_instr
->op
].input_types
[i
];
1050 unsigned bit_size
= nir_src_bit_size(cmp_instr
->src
[i
].src
);
1051 type
= (nir_alu_type
) (((unsigned) type
) | bit_size
);
1052 op
[i
] = get_nir_src(cmp_instr
->src
[i
].src
, type
, 4);
1053 unsigned base_swizzle
=
1054 brw_swizzle_for_nir_swizzle(cmp_instr
->src
[i
].swizzle
);
1055 op
[i
].swizzle
= brw_compose_swizzle(size_swizzle
, base_swizzle
);
1056 op
[i
].abs
= cmp_instr
->src
[i
].abs
;
1057 op
[i
].negate
= cmp_instr
->src
[i
].negate
;
1060 emit(CMP(dst_null_d(), op
[0], op
[1],
1061 brw_conditional_for_nir_comparison(cmp_instr
->op
)));
1067 emit_find_msb_using_lzd(const vec4_builder
&bld
,
1072 vec4_instruction
*inst
;
1076 /* LZD of an absolute value source almost always does the right
1077 * thing. There are two problem values:
1079 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
1080 * 0. However, findMSB(int(0x80000000)) == 30.
1082 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
1083 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
1085 * For a value of zero or negative one, -1 will be returned.
1087 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
1088 * findMSB(-(1<<x)) should return x-1.
1090 * For all negative number cases, including 0x80000000 and
1091 * 0xffffffff, the correct value is obtained from LZD if instead of
1092 * negating the (already negative) value the logical-not is used. A
1093 * conditonal logical-not can be achieved in two instructions.
1095 temp
= src_reg(bld
.vgrf(BRW_REGISTER_TYPE_D
));
1097 bld
.ASR(dst_reg(temp
), src
, brw_imm_d(31));
1098 bld
.XOR(dst_reg(temp
), temp
, src
);
1101 bld
.LZD(retype(dst
, BRW_REGISTER_TYPE_UD
),
1102 retype(temp
, BRW_REGISTER_TYPE_UD
));
1104 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
1105 * from the LSB side. Subtract the result from 31 to convert the MSB count
1106 * into an LSB count. If no bits are set, LZD will return 32. 31-32 = -1,
1107 * which is exactly what findMSB() is supposed to return.
1109 inst
= bld
.ADD(dst
, retype(src_reg(dst
), BRW_REGISTER_TYPE_D
),
1111 inst
->src
[0].negate
= true;
1115 vec4_visitor::emit_conversion_from_double(dst_reg dst
, src_reg src
,
1118 /* BDW PRM vol 15 - workarounds:
1119 * DF->f format conversion for Align16 has wrong emask calculation when
1120 * source is immediate.
1122 if (devinfo
->gen
== 8 && dst
.type
== BRW_REGISTER_TYPE_F
&&
1123 src
.file
== BRW_IMMEDIATE_VALUE
) {
1124 vec4_instruction
*inst
= emit(MOV(dst
, brw_imm_f(src
.df
)));
1125 inst
->saturate
= saturate
;
1131 case BRW_REGISTER_TYPE_D
:
1132 op
= VEC4_OPCODE_DOUBLE_TO_D32
;
1134 case BRW_REGISTER_TYPE_UD
:
1135 op
= VEC4_OPCODE_DOUBLE_TO_U32
;
1137 case BRW_REGISTER_TYPE_F
:
1138 op
= VEC4_OPCODE_DOUBLE_TO_F32
;
1141 unreachable("Unknown conversion");
1144 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1145 emit(MOV(temp
, src
));
1146 dst_reg temp2
= dst_reg(this, glsl_type::dvec4_type
);
1147 emit(op
, temp2
, src_reg(temp
));
1149 emit(VEC4_OPCODE_PICK_LOW_32BIT
, retype(temp2
, dst
.type
), src_reg(temp2
));
1150 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(retype(temp2
, dst
.type
))));
1151 inst
->saturate
= saturate
;
1155 vec4_visitor::emit_conversion_to_double(dst_reg dst
, src_reg src
,
1158 dst_reg tmp_dst
= dst_reg(src_reg(this, glsl_type::dvec4_type
));
1159 src_reg tmp_src
= retype(src_reg(this, glsl_type::vec4_type
), src
.type
);
1160 emit(MOV(dst_reg(tmp_src
), src
));
1161 emit(VEC4_OPCODE_TO_DOUBLE
, tmp_dst
, tmp_src
);
1162 vec4_instruction
*inst
= emit(MOV(dst
, src_reg(tmp_dst
)));
1163 inst
->saturate
= saturate
;
1167 vec4_visitor::nir_emit_alu(nir_alu_instr
*instr
)
1169 vec4_instruction
*inst
;
1171 nir_alu_type dst_type
= (nir_alu_type
) (nir_op_infos
[instr
->op
].output_type
|
1172 nir_dest_bit_size(instr
->dest
.dest
));
1173 dst_reg dst
= get_nir_dest(instr
->dest
.dest
, dst_type
);
1174 dst
.writemask
= instr
->dest
.write_mask
;
1177 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1178 nir_alu_type src_type
= (nir_alu_type
)
1179 (nir_op_infos
[instr
->op
].input_types
[i
] |
1180 nir_src_bit_size(instr
->src
[i
].src
));
1181 op
[i
] = get_nir_src(instr
->src
[i
].src
, src_type
, 4);
1182 op
[i
].swizzle
= brw_swizzle_for_nir_swizzle(instr
->src
[i
].swizzle
);
1183 op
[i
].abs
= instr
->src
[i
].abs
;
1184 op
[i
].negate
= instr
->src
[i
].negate
;
1187 switch (instr
->op
) {
1190 inst
= emit(MOV(dst
, op
[0]));
1191 inst
->saturate
= instr
->dest
.saturate
;
1197 unreachable("not reached: should be handled by lower_vec_to_movs()");
1201 inst
= emit(MOV(dst
, op
[0]));
1202 inst
->saturate
= instr
->dest
.saturate
;
1208 if (nir_src_bit_size(instr
->src
[0].src
) == 64)
1209 emit_conversion_from_double(dst
, op
[0], instr
->dest
.saturate
);
1211 inst
= emit(MOV(dst
, op
[0]));
1217 emit_conversion_to_double(dst
, op
[0], instr
->dest
.saturate
);
1221 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1224 inst
= emit(ADD(dst
, op
[0], op
[1]));
1225 inst
->saturate
= instr
->dest
.saturate
;
1229 inst
= emit(MUL(dst
, op
[0], op
[1]));
1230 inst
->saturate
= instr
->dest
.saturate
;
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 if (devinfo
->gen
< 8) {
1236 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
1237 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
1239 /* For integer multiplication, the MUL uses the low 16 bits of one of
1240 * the operands (src0 through SNB, src1 on IVB and later). The MACH
1241 * accumulates in the contribution of the upper 16 bits of that
1242 * operand. If we can determine that one of the args is in the low
1243 * 16 bits, though, we can just emit a single MUL.
1245 if (value0
&& value0
->u32
[0] < (1 << 16)) {
1246 if (devinfo
->gen
< 7)
1247 emit(MUL(dst
, op
[0], op
[1]));
1249 emit(MUL(dst
, op
[1], op
[0]));
1250 } else if (value1
&& value1
->u32
[0] < (1 << 16)) {
1251 if (devinfo
->gen
< 7)
1252 emit(MUL(dst
, op
[1], op
[0]));
1254 emit(MUL(dst
, op
[0], op
[1]));
1256 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1258 emit(MUL(acc
, op
[0], op
[1]));
1259 emit(MACH(dst_null_d(), op
[0], op
[1]));
1260 emit(MOV(dst
, src_reg(acc
)));
1263 emit(MUL(dst
, op
[0], op
[1]));
1268 case nir_op_imul_high
:
1269 case nir_op_umul_high
: {
1270 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1271 struct brw_reg acc
= retype(brw_acc_reg(8), dst
.type
);
1273 if (devinfo
->gen
>= 8)
1274 emit(MUL(acc
, op
[0], retype(op
[1], BRW_REGISTER_TYPE_UW
)));
1276 emit(MUL(acc
, op
[0], op
[1]));
1278 emit(MACH(dst
, op
[0], op
[1]));
1283 inst
= emit_math(SHADER_OPCODE_RCP
, dst
, op
[0]);
1284 inst
->saturate
= instr
->dest
.saturate
;
1288 inst
= emit_math(SHADER_OPCODE_EXP2
, dst
, op
[0]);
1289 inst
->saturate
= instr
->dest
.saturate
;
1293 inst
= emit_math(SHADER_OPCODE_LOG2
, dst
, op
[0]);
1294 inst
->saturate
= instr
->dest
.saturate
;
1298 inst
= emit_math(SHADER_OPCODE_SIN
, dst
, op
[0]);
1299 inst
->saturate
= instr
->dest
.saturate
;
1303 inst
= emit_math(SHADER_OPCODE_COS
, dst
, op
[0]);
1304 inst
->saturate
= instr
->dest
.saturate
;
1309 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1310 emit_math(SHADER_OPCODE_INT_QUOTIENT
, dst
, op
[0], op
[1]);
1315 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1316 * appears that our hardware just does the right thing for signed
1319 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1320 emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1324 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1325 inst
= emit_math(SHADER_OPCODE_INT_REMAINDER
, dst
, op
[0], op
[1]);
1327 /* Math instructions don't support conditional mod */
1328 inst
= emit(MOV(dst_null_d(), src_reg(dst
)));
1329 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1331 /* Now, we need to determine if signs of the sources are different.
1332 * When we XOR the sources, the top bit is 0 if they are the same and 1
1333 * if they are different. We can then use a conditional modifier to
1334 * turn that into a predicate. This leads us to an XOR.l instruction.
1336 * Technically, according to the PRM, you're not allowed to use .l on a
1337 * XOR instruction. However, emperical experiments and Curro's reading
1338 * of the simulator source both indicate that it's safe.
1340 src_reg tmp
= src_reg(this, glsl_type::ivec4_type
);
1341 inst
= emit(XOR(dst_reg(tmp
), op
[0], op
[1]));
1342 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1343 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1345 /* If the result of the initial remainder operation is non-zero and the
1346 * two sources have different signs, add in a copy of op[1] to get the
1347 * final integer modulus value.
1349 inst
= emit(ADD(dst
, src_reg(dst
), op
[1]));
1350 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1355 unreachable("not reached: should be handled by ldexp_to_arith()");
1358 inst
= emit_math(SHADER_OPCODE_SQRT
, dst
, op
[0]);
1359 inst
->saturate
= instr
->dest
.saturate
;
1363 inst
= emit_math(SHADER_OPCODE_RSQ
, dst
, op
[0]);
1364 inst
->saturate
= instr
->dest
.saturate
;
1368 inst
= emit_math(SHADER_OPCODE_POW
, dst
, op
[0], op
[1]);
1369 inst
->saturate
= instr
->dest
.saturate
;
1372 case nir_op_uadd_carry
: {
1373 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1374 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1376 emit(ADDC(dst_null_ud(), op
[0], op
[1]));
1377 emit(MOV(dst
, src_reg(acc
)));
1381 case nir_op_usub_borrow
: {
1382 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1383 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD
);
1385 emit(SUBB(dst_null_ud(), op
[0], op
[1]));
1386 emit(MOV(dst
, src_reg(acc
)));
1391 inst
= emit(RNDZ(dst
, op
[0]));
1392 inst
->saturate
= instr
->dest
.saturate
;
1395 case nir_op_fceil
: {
1396 src_reg tmp
= src_reg(this, glsl_type::float_type
);
1398 brw_swizzle_for_size(instr
->src
[0].src
.is_ssa
?
1399 instr
->src
[0].src
.ssa
->num_components
:
1400 instr
->src
[0].src
.reg
.reg
->num_components
);
1402 op
[0].negate
= !op
[0].negate
;
1403 emit(RNDD(dst_reg(tmp
), op
[0]));
1405 inst
= emit(MOV(dst
, tmp
));
1406 inst
->saturate
= instr
->dest
.saturate
;
1411 inst
= emit(RNDD(dst
, op
[0]));
1412 inst
->saturate
= instr
->dest
.saturate
;
1416 inst
= emit(FRC(dst
, op
[0]));
1417 inst
->saturate
= instr
->dest
.saturate
;
1420 case nir_op_fround_even
:
1421 inst
= emit(RNDE(dst
, op
[0]));
1422 inst
->saturate
= instr
->dest
.saturate
;
1425 case nir_op_fquantize2f16
: {
1426 /* See also vec4_visitor::emit_pack_half_2x16() */
1427 src_reg tmp16
= src_reg(this, glsl_type::uvec4_type
);
1428 src_reg tmp32
= src_reg(this, glsl_type::vec4_type
);
1429 src_reg zero
= src_reg(this, glsl_type::vec4_type
);
1431 /* Check for denormal */
1432 src_reg abs_src0
= op
[0];
1433 abs_src0
.abs
= true;
1434 emit(CMP(dst_null_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1435 BRW_CONDITIONAL_L
));
1436 /* Get the appropriately signed zero */
1437 emit(AND(retype(dst_reg(zero
), BRW_REGISTER_TYPE_UD
),
1438 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1439 brw_imm_ud(0x80000000)));
1440 /* Do the actual F32 -> F16 -> F32 conversion */
1441 emit(F32TO16(dst_reg(tmp16
), op
[0]));
1442 emit(F16TO32(dst_reg(tmp32
), tmp16
));
1443 /* Select that or zero based on normal status */
1444 inst
= emit(BRW_OPCODE_SEL
, dst
, zero
, tmp32
);
1445 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1446 inst
->saturate
= instr
->dest
.saturate
;
1452 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1455 inst
= emit_minmax(BRW_CONDITIONAL_L
, dst
, op
[0], op
[1]);
1456 inst
->saturate
= instr
->dest
.saturate
;
1461 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1464 inst
= emit_minmax(BRW_CONDITIONAL_GE
, dst
, op
[0], op
[1]);
1465 inst
->saturate
= instr
->dest
.saturate
;
1469 case nir_op_fddx_coarse
:
1470 case nir_op_fddx_fine
:
1472 case nir_op_fddy_coarse
:
1473 case nir_op_fddy_fine
:
1474 unreachable("derivatives are not valid in vertex shaders");
1482 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1488 enum brw_conditional_mod conditional_mod
=
1489 brw_conditional_for_nir_comparison(instr
->op
);
1491 if (nir_src_bit_size(instr
->src
[0].src
) < 64) {
1492 emit(CMP(dst
, op
[0], op
[1], conditional_mod
));
1494 /* Produce a 32-bit boolean result from the DF comparison by selecting
1495 * only the low 32-bit in each DF produced. Do this in a temporary
1496 * so we can then move from there to the result using align16 again
1497 * to honor the original writemask.
1499 dst_reg temp
= dst_reg(this, glsl_type::dvec4_type
);
1500 emit(CMP(temp
, op
[0], op
[1], conditional_mod
));
1501 dst_reg result
= dst_reg(this, glsl_type::bvec4_type
);
1502 emit(VEC4_OPCODE_PICK_LOW_32BIT
, result
, src_reg(temp
));
1503 emit(MOV(dst
, src_reg(result
)));
1508 case nir_op_ball_iequal2
:
1509 case nir_op_ball_iequal3
:
1510 case nir_op_ball_iequal4
:
1511 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1513 case nir_op_ball_fequal2
:
1514 case nir_op_ball_fequal3
:
1515 case nir_op_ball_fequal4
: {
1517 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1519 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1520 brw_conditional_for_nir_comparison(instr
->op
)));
1521 emit(MOV(dst
, brw_imm_d(0)));
1522 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1523 inst
->predicate
= BRW_PREDICATE_ALIGN16_ALL4H
;
1527 case nir_op_bany_inequal2
:
1528 case nir_op_bany_inequal3
:
1529 case nir_op_bany_inequal4
:
1530 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1532 case nir_op_bany_fnequal2
:
1533 case nir_op_bany_fnequal3
:
1534 case nir_op_bany_fnequal4
: {
1536 brw_swizzle_for_size(nir_op_infos
[instr
->op
].input_sizes
[0]);
1538 emit(CMP(dst_null_d(), swizzle(op
[0], swiz
), swizzle(op
[1], swiz
),
1539 brw_conditional_for_nir_comparison(instr
->op
)));
1541 emit(MOV(dst
, brw_imm_d(0)));
1542 inst
= emit(MOV(dst
, brw_imm_d(~0)));
1543 inst
->predicate
= BRW_PREDICATE_ALIGN16_ANY4H
;
1548 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1549 if (devinfo
->gen
>= 8) {
1550 op
[0] = resolve_source_modifiers(op
[0]);
1552 emit(NOT(dst
, op
[0]));
1556 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1557 if (devinfo
->gen
>= 8) {
1558 op
[0] = resolve_source_modifiers(op
[0]);
1559 op
[1] = resolve_source_modifiers(op
[1]);
1561 emit(XOR(dst
, op
[0], op
[1]));
1565 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1566 if (devinfo
->gen
>= 8) {
1567 op
[0] = resolve_source_modifiers(op
[0]);
1568 op
[1] = resolve_source_modifiers(op
[1]);
1570 emit(OR(dst
, op
[0], op
[1]));
1574 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1575 if (devinfo
->gen
>= 8) {
1576 op
[0] = resolve_source_modifiers(op
[0]);
1577 op
[1] = resolve_source_modifiers(op
[1]);
1579 emit(AND(dst
, op
[0], op
[1]));
1584 if (nir_dest_bit_size(instr
->dest
.dest
) > 32) {
1585 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
1586 emit_conversion_to_double(dst
, negate(op
[0]), false);
1588 emit(MOV(dst
, negate(op
[0])));
1593 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1594 /* We use a MOV with conditional_mod to check if the provided value is
1595 * 0.0. We want this to flush denormalized numbers to zero, so we set a
1596 * source modifier on the source operand to trigger this, as source
1597 * modifiers don't affect the result of the testing against 0.0.
1599 src_reg value
= op
[0];
1601 vec4_instruction
*inst
= emit(MOV(dst_null_df(), value
));
1602 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1604 src_reg one
= src_reg(this, glsl_type::ivec4_type
);
1605 emit(MOV(dst_reg(one
), brw_imm_d(~0)));
1606 inst
= emit(BRW_OPCODE_SEL
, dst
, one
, brw_imm_d(0));
1607 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1609 emit(CMP(dst
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1614 emit(CMP(dst
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1617 case nir_op_fnoise1_1
:
1618 case nir_op_fnoise1_2
:
1619 case nir_op_fnoise1_3
:
1620 case nir_op_fnoise1_4
:
1621 case nir_op_fnoise2_1
:
1622 case nir_op_fnoise2_2
:
1623 case nir_op_fnoise2_3
:
1624 case nir_op_fnoise2_4
:
1625 case nir_op_fnoise3_1
:
1626 case nir_op_fnoise3_2
:
1627 case nir_op_fnoise3_3
:
1628 case nir_op_fnoise3_4
:
1629 case nir_op_fnoise4_1
:
1630 case nir_op_fnoise4_2
:
1631 case nir_op_fnoise4_3
:
1632 case nir_op_fnoise4_4
:
1633 unreachable("not reached: should be handled by lower_noise");
1635 case nir_op_unpack_half_2x16_split_x
:
1636 case nir_op_unpack_half_2x16_split_y
:
1637 case nir_op_pack_half_2x16_split
:
1638 unreachable("not reached: should not occur in vertex shader");
1640 case nir_op_unpack_snorm_2x16
:
1641 case nir_op_unpack_unorm_2x16
:
1642 case nir_op_pack_snorm_2x16
:
1643 case nir_op_pack_unorm_2x16
:
1644 unreachable("not reached: should be handled by lower_packing_builtins");
1646 case nir_op_pack_uvec4_to_uint
:
1647 unreachable("not reached");
1649 case nir_op_pack_uvec2_to_uint
: {
1650 dst_reg tmp1
= dst_reg(this, glsl_type::uint_type
);
1651 tmp1
.writemask
= WRITEMASK_X
;
1652 op
[0].swizzle
= BRW_SWIZZLE_YYYY
;
1653 emit(SHL(tmp1
, op
[0], src_reg(brw_imm_ud(16u))));
1655 dst_reg tmp2
= dst_reg(this, glsl_type::uint_type
);
1656 tmp2
.writemask
= WRITEMASK_X
;
1657 op
[0].swizzle
= BRW_SWIZZLE_XXXX
;
1658 emit(AND(tmp2
, op
[0], src_reg(brw_imm_ud(0xffffu
))));
1660 emit(OR(dst
, src_reg(tmp1
), src_reg(tmp2
)));
1664 case nir_op_pack_64_2x32_split
: {
1665 dst_reg result
= dst_reg(this, glsl_type::dvec4_type
);
1666 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1667 emit(MOV(tmp
, retype(op
[0], BRW_REGISTER_TYPE_UD
)));
1668 emit(VEC4_OPCODE_SET_LOW_32BIT
, result
, src_reg(tmp
));
1669 emit(MOV(tmp
, retype(op
[1], BRW_REGISTER_TYPE_UD
)));
1670 emit(VEC4_OPCODE_SET_HIGH_32BIT
, result
, src_reg(tmp
));
1671 emit(MOV(dst
, src_reg(result
)));
1675 case nir_op_unpack_64_2x32_split_x
:
1676 case nir_op_unpack_64_2x32_split_y
: {
1677 enum opcode oper
= (instr
->op
== nir_op_unpack_64_2x32_split_x
) ?
1678 VEC4_OPCODE_PICK_LOW_32BIT
: VEC4_OPCODE_PICK_HIGH_32BIT
;
1679 dst_reg tmp
= dst_reg(this, glsl_type::dvec4_type
);
1680 emit(MOV(tmp
, op
[0]));
1681 dst_reg tmp2
= dst_reg(this, glsl_type::uvec4_type
);
1682 emit(oper
, tmp2
, src_reg(tmp
));
1683 emit(MOV(dst
, src_reg(tmp2
)));
1687 case nir_op_unpack_half_2x16
:
1688 /* As NIR does not guarantee that we have a correct swizzle outside the
1689 * boundaries of a vector, and the implementation of emit_unpack_half_2x16
1690 * uses the source operand in an operation with WRITEMASK_Y while our
1691 * source operand has only size 1, it accessed incorrect data producing
1692 * regressions in Piglit. We repeat the swizzle of the first component on the
1693 * rest of components to avoid regressions. In the vec4_visitor IR code path
1694 * this is not needed because the operand has already the correct swizzle.
1696 op
[0].swizzle
= brw_compose_swizzle(BRW_SWIZZLE_XXXX
, op
[0].swizzle
);
1697 emit_unpack_half_2x16(dst
, op
[0]);
1700 case nir_op_pack_half_2x16
:
1701 emit_pack_half_2x16(dst
, op
[0]);
1704 case nir_op_unpack_unorm_4x8
:
1705 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1706 emit_unpack_unorm_4x8(dst
, op
[0]);
1709 case nir_op_pack_unorm_4x8
:
1710 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1711 emit_pack_unorm_4x8(dst
, op
[0]);
1714 case nir_op_unpack_snorm_4x8
:
1715 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1716 emit_unpack_snorm_4x8(dst
, op
[0]);
1719 case nir_op_pack_snorm_4x8
:
1720 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1721 emit_pack_snorm_4x8(dst
, op
[0]);
1724 case nir_op_bitfield_reverse
:
1725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1726 emit(BFREV(dst
, op
[0]));
1729 case nir_op_bit_count
:
1730 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1731 emit(CBIT(dst
, op
[0]));
1734 case nir_op_ufind_msb
:
1735 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1736 emit_find_msb_using_lzd(vec4_builder(this).at_end(), dst
, op
[0], false);
1739 case nir_op_ifind_msb
: {
1740 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1741 vec4_builder bld
= vec4_builder(this).at_end();
1744 if (devinfo
->gen
< 7) {
1745 emit_find_msb_using_lzd(bld
, dst
, op
[0], true);
1747 emit(FBH(retype(dst
, BRW_REGISTER_TYPE_UD
), op
[0]));
1749 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1750 * count from the LSB side. If FBH didn't return an error
1751 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1752 * count into an LSB count.
1754 bld
.CMP(dst_null_d(), src
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1756 inst
= bld
.ADD(dst
, src
, brw_imm_d(31));
1757 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1758 inst
->src
[0].negate
= true;
1763 case nir_op_find_lsb
: {
1764 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1765 vec4_builder bld
= vec4_builder(this).at_end();
1767 if (devinfo
->gen
< 7) {
1768 dst_reg temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1770 /* (x & -x) generates a value that consists of only the LSB of x.
1771 * For all powers of 2, findMSB(y) == findLSB(y).
1773 src_reg src
= src_reg(retype(op
[0], BRW_REGISTER_TYPE_D
));
1774 src_reg negated_src
= src
;
1776 /* One must be negated, and the other must be non-negated. It
1777 * doesn't matter which is which.
1779 negated_src
.negate
= true;
1782 bld
.AND(temp
, src
, negated_src
);
1783 emit_find_msb_using_lzd(bld
, dst
, src_reg(temp
), false);
1785 bld
.FBL(dst
, op
[0]);
1790 case nir_op_ubitfield_extract
:
1791 case nir_op_ibitfield_extract
:
1792 unreachable("should have been lowered");
1795 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1796 op
[0] = fix_3src_operand(op
[0]);
1797 op
[1] = fix_3src_operand(op
[1]);
1798 op
[2] = fix_3src_operand(op
[2]);
1800 emit(BFE(dst
, op
[2], op
[1], op
[0]));
1804 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1805 emit(BFI1(dst
, op
[0], op
[1]));
1809 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1810 op
[0] = fix_3src_operand(op
[0]);
1811 op
[1] = fix_3src_operand(op
[1]);
1812 op
[2] = fix_3src_operand(op
[2]);
1814 emit(BFI2(dst
, op
[0], op
[1], op
[2]));
1817 case nir_op_bitfield_insert
:
1818 unreachable("not reached: should have been lowered");
1821 assert(!instr
->dest
.saturate
);
1823 /* Straightforward since the source can be assumed to be either
1824 * strictly >= 0 or strictly <= 0 depending on the setting of the
1827 inst
= emit(MOV(dst
, op
[0]));
1828 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1830 inst
= (op
[0].negate
)
1831 ? emit(MOV(dst
, brw_imm_f(-1.0f
)))
1832 : emit(MOV(dst
, brw_imm_f(1.0f
)));
1833 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1834 } else if (type_sz(op
[0].type
) < 8) {
1835 /* AND(val, 0x80000000) gives the sign bit.
1837 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
1840 emit(CMP(dst_null_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
));
1842 op
[0].type
= BRW_REGISTER_TYPE_UD
;
1843 dst
.type
= BRW_REGISTER_TYPE_UD
;
1844 emit(AND(dst
, op
[0], brw_imm_ud(0x80000000u
)));
1846 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_ud(0x3f800000u
)));
1847 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1848 dst
.type
= BRW_REGISTER_TYPE_F
;
1850 /* For doubles we do the same but we need to consider:
1852 * - We use a MOV with conditional_mod instead of a CMP so that we can
1853 * skip loading a 0.0 immediate. We use a source modifier on the
1854 * source of the MOV so that we flush denormalized values to 0.
1855 * Since we want to compare against 0, this won't alter the result.
1856 * - We need to extract the high 32-bit of each DF where the sign
1858 * - We need to produce a DF result.
1861 /* Check for zero */
1862 src_reg value
= op
[0];
1864 inst
= emit(MOV(dst_null_df(), value
));
1865 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1867 /* AND each high 32-bit channel with 0x80000000u */
1868 dst_reg tmp
= dst_reg(this, glsl_type::uvec4_type
);
1869 emit(VEC4_OPCODE_PICK_HIGH_32BIT
, tmp
, op
[0]);
1870 emit(AND(tmp
, src_reg(tmp
), brw_imm_ud(0x80000000u
)));
1872 /* Add 1.0 to each channel, predicated to skip the cases where the
1873 * channel's value was 0
1875 inst
= emit(OR(tmp
, src_reg(tmp
), brw_imm_ud(0x3f800000u
)));
1876 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1878 /* Now convert the result from float to double */
1879 emit_conversion_to_double(dst
, retype(src_reg(tmp
),
1880 BRW_REGISTER_TYPE_F
),
1886 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
1887 * -> non-negative val generates 0x00000000.
1888 * Predicated OR sets 1 if val is positive.
1890 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1891 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
));
1892 emit(ASR(dst
, op
[0], brw_imm_d(31)));
1893 inst
= emit(OR(dst
, src_reg(dst
), brw_imm_d(1)));
1894 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1898 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1899 emit(SHL(dst
, op
[0], op
[1]));
1903 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1904 emit(ASR(dst
, op
[0], op
[1]));
1908 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1909 emit(SHR(dst
, op
[0], op
[1]));
1913 if (type_sz(dst
.type
) == 8) {
1914 dst_reg mul_dst
= dst_reg(this, glsl_type::dvec4_type
);
1915 emit(MUL(mul_dst
, op
[1], op
[0]));
1916 inst
= emit(ADD(dst
, src_reg(mul_dst
), op
[2]));
1917 inst
->saturate
= instr
->dest
.saturate
;
1919 op
[0] = fix_3src_operand(op
[0]);
1920 op
[1] = fix_3src_operand(op
[1]);
1921 op
[2] = fix_3src_operand(op
[2]);
1923 inst
= emit(MAD(dst
, op
[2], op
[1], op
[0]));
1924 inst
->saturate
= instr
->dest
.saturate
;
1929 inst
= emit_lrp(dst
, op
[0], op
[1], op
[2]);
1930 inst
->saturate
= instr
->dest
.saturate
;
1934 enum brw_predicate predicate
;
1935 if (!optimize_predicate(instr
, &predicate
)) {
1936 emit(CMP(dst_null_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
));
1937 switch (dst
.writemask
) {
1939 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_X
;
1942 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Y
;
1945 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_Z
;
1948 predicate
= BRW_PREDICATE_ALIGN16_REPLICATE_W
;
1951 predicate
= BRW_PREDICATE_NORMAL
;
1955 inst
= emit(BRW_OPCODE_SEL
, dst
, op
[1], op
[2]);
1956 inst
->predicate
= predicate
;
1959 case nir_op_fdot_replicated2
:
1960 inst
= emit(BRW_OPCODE_DP2
, dst
, op
[0], op
[1]);
1961 inst
->saturate
= instr
->dest
.saturate
;
1964 case nir_op_fdot_replicated3
:
1965 inst
= emit(BRW_OPCODE_DP3
, dst
, op
[0], op
[1]);
1966 inst
->saturate
= instr
->dest
.saturate
;
1969 case nir_op_fdot_replicated4
:
1970 inst
= emit(BRW_OPCODE_DP4
, dst
, op
[0], op
[1]);
1971 inst
->saturate
= instr
->dest
.saturate
;
1974 case nir_op_fdph_replicated
:
1975 inst
= emit(BRW_OPCODE_DPH
, dst
, op
[0], op
[1]);
1976 inst
->saturate
= instr
->dest
.saturate
;
1981 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1986 unreachable("not reached: should be lowered by lower_source mods");
1989 unreachable("not reached: should be lowered by DIV_TO_MUL_RCP in the compiler");
1992 unreachable("not reached: should be lowered by MOD_TO_FLOOR in the compiler");
1996 unreachable("not reached: should be handled by ir_sub_to_add_neg");
1999 unreachable("Unimplemented ALU operation");
2002 /* If we need to do a boolean resolve, replace the result with -(x & 1)
2003 * to sign extend the low bit to 0/~0
2005 if (devinfo
->gen
<= 5 &&
2006 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) ==
2007 BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
2008 dst_reg masked
= dst_reg(this, glsl_type::int_type
);
2009 masked
.writemask
= dst
.writemask
;
2010 emit(AND(masked
, src_reg(dst
), brw_imm_d(1)));
2011 src_reg masked_neg
= src_reg(masked
);
2012 masked_neg
.negate
= true;
2013 emit(MOV(retype(dst
, BRW_REGISTER_TYPE_D
), masked_neg
));
2018 vec4_visitor::nir_emit_jump(nir_jump_instr
*instr
)
2020 switch (instr
->type
) {
2021 case nir_jump_break
:
2022 emit(BRW_OPCODE_BREAK
);
2025 case nir_jump_continue
:
2026 emit(BRW_OPCODE_CONTINUE
);
2029 case nir_jump_return
:
2032 unreachable("unknown jump");
2036 static enum ir_texture_opcode
2037 ir_texture_opcode_for_nir_texop(nir_texop texop
)
2039 enum ir_texture_opcode op
;
2042 case nir_texop_lod
: op
= ir_lod
; break;
2043 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2044 case nir_texop_texture_samples
: op
= ir_texture_samples
; break;
2045 case nir_texop_tex
: op
= ir_tex
; break;
2046 case nir_texop_tg4
: op
= ir_tg4
; break;
2047 case nir_texop_txb
: op
= ir_txb
; break;
2048 case nir_texop_txd
: op
= ir_txd
; break;
2049 case nir_texop_txf
: op
= ir_txf
; break;
2050 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2051 case nir_texop_txl
: op
= ir_txl
; break;
2052 case nir_texop_txs
: op
= ir_txs
; break;
2053 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2055 unreachable("unknown texture opcode");
2061 static const glsl_type
*
2062 glsl_type_for_nir_alu_type(nir_alu_type alu_type
,
2063 unsigned components
)
2065 return glsl_type::get_instance(brw_glsl_base_type_for_nir_type(alu_type
),
2070 vec4_visitor::nir_emit_texture(nir_tex_instr
*instr
)
2072 unsigned texture
= instr
->texture_index
;
2073 unsigned sampler
= instr
->sampler_index
;
2074 src_reg texture_reg
= brw_imm_ud(texture
);
2075 src_reg sampler_reg
= brw_imm_ud(sampler
);
2077 const glsl_type
*coord_type
= NULL
;
2078 src_reg shadow_comparator
;
2079 src_reg offset_value
;
2081 src_reg sample_index
;
2084 const glsl_type
*dest_type
=
2085 glsl_type_for_nir_alu_type(instr
->dest_type
,
2086 nir_tex_instr_dest_size(instr
));
2087 dst_reg dest
= get_nir_dest(instr
->dest
, instr
->dest_type
);
2089 /* The hardware requires a LOD for buffer textures */
2090 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2093 /* Load the texture operation sources */
2094 uint32_t constant_offset
= 0;
2095 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2096 switch (instr
->src
[i
].src_type
) {
2097 case nir_tex_src_comparator
:
2098 shadow_comparator
= get_nir_src(instr
->src
[i
].src
,
2099 BRW_REGISTER_TYPE_F
, 1);
2102 case nir_tex_src_coord
: {
2103 unsigned src_size
= nir_tex_instr_src_size(instr
, i
);
2105 switch (instr
->op
) {
2107 case nir_texop_txf_ms
:
2108 case nir_texop_samples_identical
:
2109 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
,
2111 coord_type
= glsl_type::ivec(src_size
);
2115 coordinate
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2117 coord_type
= glsl_type::vec(src_size
);
2123 case nir_tex_src_ddx
:
2124 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2125 nir_tex_instr_src_size(instr
, i
));
2128 case nir_tex_src_ddy
:
2129 lod2
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
,
2130 nir_tex_instr_src_size(instr
, i
));
2133 case nir_tex_src_lod
:
2134 switch (instr
->op
) {
2137 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2141 lod
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_F
, 1);
2146 case nir_tex_src_ms_index
: {
2147 sample_index
= get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 1);
2151 case nir_tex_src_offset
: {
2152 nir_const_value
*const_offset
=
2153 nir_src_as_const_value(instr
->src
[i
].src
);
2154 if (!const_offset
||
2155 !brw_texture_offset(const_offset
->i32
,
2156 nir_tex_instr_src_size(instr
, i
),
2157 &constant_offset
)) {
2159 get_nir_src(instr
->src
[i
].src
, BRW_REGISTER_TYPE_D
, 2);
2164 case nir_tex_src_texture_offset
: {
2165 /* The highest texture which may be used by this operation is
2166 * the last element of the array. Mark it here, because the generator
2167 * doesn't have enough information to determine the bound.
2169 uint32_t array_size
= instr
->texture_array_size
;
2170 uint32_t max_used
= texture
+ array_size
- 1;
2171 if (instr
->op
== nir_texop_tg4
) {
2172 max_used
+= prog_data
->base
.binding_table
.gather_texture_start
;
2174 max_used
+= prog_data
->base
.binding_table
.texture_start
;
2177 brw_mark_surface_used(&prog_data
->base
, max_used
);
2179 /* Emit code to evaluate the actual indexing expression */
2180 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2181 src_reg
temp(this, glsl_type::uint_type
);
2182 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(texture
)));
2183 texture_reg
= emit_uniformize(temp
);
2187 case nir_tex_src_sampler_offset
: {
2188 /* Emit code to evaluate the actual indexing expression */
2189 src_reg src
= get_nir_src(instr
->src
[i
].src
, 1);
2190 src_reg
temp(this, glsl_type::uint_type
);
2191 emit(ADD(dst_reg(temp
), src
, brw_imm_ud(sampler
)));
2192 sampler_reg
= emit_uniformize(temp
);
2196 case nir_tex_src_projector
:
2197 unreachable("Should be lowered by do_lower_texture_projection");
2199 case nir_tex_src_bias
:
2200 unreachable("LOD bias is not valid for vertex shaders.\n");
2203 unreachable("unknown texture source");
2207 if (instr
->op
== nir_texop_txf_ms
||
2208 instr
->op
== nir_texop_samples_identical
) {
2209 assert(coord_type
!= NULL
);
2210 if (devinfo
->gen
>= 7 &&
2211 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2212 mcs
= emit_mcs_fetch(coord_type
, coordinate
, texture_reg
);
2214 mcs
= brw_imm_ud(0u);
2218 /* Stuff the channel select bits in the top of the texture offset */
2219 if (instr
->op
== nir_texop_tg4
) {
2220 if (instr
->component
== 1 &&
2221 (key_tex
->gather_channel_quirk_mask
& (1 << texture
))) {
2222 /* gather4 sampler is broken for green channel on RG32F --
2223 * we must ask for blue instead.
2225 constant_offset
|= 2 << 16;
2227 constant_offset
|= instr
->component
<< 16;
2231 ir_texture_opcode op
= ir_texture_opcode_for_nir_texop(instr
->op
);
2233 emit_texture(op
, dest
, dest_type
, coordinate
, instr
->coord_components
,
2235 lod
, lod2
, sample_index
,
2236 constant_offset
, offset_value
, mcs
,
2237 texture
, texture_reg
, sampler_reg
);
2241 vec4_visitor::nir_emit_undef(nir_ssa_undef_instr
*instr
)
2243 nir_ssa_values
[instr
->def
.index
] =
2244 dst_reg(VGRF
, alloc
.allocate(DIV_ROUND_UP(instr
->def
.bit_size
, 32)));
2247 /* SIMD4x2 64bit data is stored in register space like this:
2249 * r0.0:DF x0 y0 z0 w0
2250 * r1.0:DF x1 y1 z1 w1
2252 * When we need to write data such as this to memory using 32-bit write
2253 * messages we need to shuffle it in this fashion:
2255 * r0.0:DF x0 y0 x1 y1 (to be written at base offset)
2256 * r0.0:DF z0 w0 z1 w1 (to be written at base offset + 16)
2258 * We need to do the inverse operation when we read using 32-bit messages,
2259 * which we can do by applying the same exact shuffling on the 64-bit data
2260 * read, only that because the data for each vertex is positioned differently
2261 * we need to apply different channel enables.
2263 * This function takes 64bit data and shuffles it as explained above.
2265 * The @for_write parameter is used to specify if the shuffling is being done
2266 * for proper SIMD4x2 64-bit data that needs to be shuffled prior to a 32-bit
2267 * write message (for_write = true), or instead we are doing the inverse
2268 * operation and we have just read 64-bit data using a 32-bit messages that we
2269 * need to shuffle to create valid SIMD4x2 64-bit data (for_write = false).
2271 * If @block and @ref are non-NULL, then the shuffling is done after @ref,
2272 * otherwise the instructions are emitted normally at the end. The function
2273 * returns the last instruction inserted.
2275 * Notice that @src and @dst cannot be the same register.
2278 vec4_visitor::shuffle_64bit_data(dst_reg dst
, src_reg src
, bool for_write
,
2279 bblock_t
*block
, vec4_instruction
*ref
)
2281 assert(type_sz(src
.type
) == 8);
2282 assert(type_sz(dst
.type
) == 8);
2283 assert(!regions_overlap(dst
, 2 * REG_SIZE
, src
, 2 * REG_SIZE
));
2284 assert(!ref
== !block
);
2286 const vec4_builder bld
= !ref
? vec4_builder(this).at_end() :
2287 vec4_builder(this).at(block
, ref
->next
);
2289 /* Resolve swizzle in src */
2290 vec4_instruction
*inst
;
2291 if (src
.swizzle
!= BRW_SWIZZLE_XYZW
) {
2292 dst_reg data
= dst_reg(this, glsl_type::dvec4_type
);
2293 inst
= bld
.MOV(data
, src
);
2294 src
= src_reg(data
);
2297 /* dst+0.XY = src+0.XY */
2298 inst
= bld
.group(4, 0).MOV(writemask(dst
, WRITEMASK_XY
), src
);
2300 /* dst+0.ZW = src+1.XY */
2301 inst
= bld
.group(4, for_write
? 1 : 0)
2302 .MOV(writemask(dst
, WRITEMASK_ZW
),
2303 swizzle(byte_offset(src
, REG_SIZE
), BRW_SWIZZLE_XYXY
));
2305 /* dst+1.XY = src+0.ZW */
2306 inst
= bld
.group(4, for_write
? 0 : 1)
2307 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_XY
),
2308 swizzle(src
, BRW_SWIZZLE_ZWZW
));
2310 /* dst+1.ZW = src+1.ZW */
2311 inst
= bld
.group(4, 1)
2312 .MOV(writemask(byte_offset(dst
, REG_SIZE
), WRITEMASK_ZW
),
2313 byte_offset(src
, REG_SIZE
));